2 * Copyright © 2010 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 #include "compiler/glsl/ir.h"
26 #include "brw_fs_surface_builder.h"
30 using namespace brw::surface_access
;
33 fs_visitor::emit_nir_code()
35 /* emit the arrays used for inputs and outputs - load/store intrinsics will
36 * be converted to reads/writes of these arrays
40 nir_emit_system_values();
42 /* get the main function and emit it */
43 nir_foreach_function(function
, nir
) {
44 assert(strcmp(function
->name
, "main") == 0);
45 assert(function
->impl
);
46 nir_emit_impl(function
->impl
);
51 fs_visitor::nir_setup_outputs()
53 if (stage
== MESA_SHADER_TESS_CTRL
|| stage
== MESA_SHADER_FRAGMENT
)
56 unsigned vec4s
[VARYING_SLOT_TESS_MAX
] = { 0, };
58 /* Calculate the size of output registers in a separate pass, before
59 * allocating them. With ARB_enhanced_layouts, multiple output variables
60 * may occupy the same slot, but have different type sizes.
62 nir_foreach_variable(var
, &nir
->outputs
) {
63 const int loc
= var
->data
.driver_location
;
64 const unsigned var_vec4s
=
65 var
->data
.compact
? DIV_ROUND_UP(glsl_get_length(var
->type
), 4)
66 : type_size_vec4(var
->type
);
67 vec4s
[loc
] = MAX2(vec4s
[loc
], var_vec4s
);
70 nir_foreach_variable(var
, &nir
->outputs
) {
71 const int loc
= var
->data
.driver_location
;
72 if (outputs
[loc
].file
== BAD_FILE
) {
73 fs_reg reg
= bld
.vgrf(BRW_REGISTER_TYPE_F
, 4 * vec4s
[loc
]);
74 for (unsigned i
= 0; i
< vec4s
[loc
]; i
++) {
75 outputs
[loc
+ i
] = offset(reg
, bld
, 4 * i
);
82 fs_visitor::nir_setup_uniforms()
84 /* Only the first compile gets to set up uniforms. */
85 if (push_constant_loc
) {
86 assert(pull_constant_loc
);
90 uniforms
= nir
->num_uniforms
/ 4;
92 if (stage
== MESA_SHADER_COMPUTE
) {
93 /* Add a uniform for the thread local id. It must be the last uniform
96 assert(uniforms
== prog_data
->nr_params
);
97 uint32_t *param
= brw_stage_prog_data_add_params(prog_data
, 1);
98 *param
= BRW_PARAM_BUILTIN_SUBGROUP_ID
;
99 subgroup_id
= fs_reg(UNIFORM
, uniforms
++, BRW_REGISTER_TYPE_UD
);
104 emit_system_values_block(nir_block
*block
, fs_visitor
*v
)
108 nir_foreach_instr(instr
, block
) {
109 if (instr
->type
!= nir_instr_type_intrinsic
)
112 nir_intrinsic_instr
*intrin
= nir_instr_as_intrinsic(instr
);
113 switch (intrin
->intrinsic
) {
114 case nir_intrinsic_load_vertex_id
:
115 case nir_intrinsic_load_base_vertex
:
116 unreachable("should be lowered by nir_lower_system_values().");
118 case nir_intrinsic_load_vertex_id_zero_base
:
119 case nir_intrinsic_load_is_indexed_draw
:
120 case nir_intrinsic_load_first_vertex
:
121 case nir_intrinsic_load_instance_id
:
122 case nir_intrinsic_load_base_instance
:
123 case nir_intrinsic_load_draw_id
:
124 unreachable("should be lowered by brw_nir_lower_vs_inputs().");
126 case nir_intrinsic_load_invocation_id
:
127 if (v
->stage
== MESA_SHADER_TESS_CTRL
)
129 assert(v
->stage
== MESA_SHADER_GEOMETRY
);
130 reg
= &v
->nir_system_values
[SYSTEM_VALUE_INVOCATION_ID
];
131 if (reg
->file
== BAD_FILE
) {
132 const fs_builder abld
= v
->bld
.annotate("gl_InvocationID", NULL
);
133 fs_reg
g1(retype(brw_vec8_grf(1, 0), BRW_REGISTER_TYPE_UD
));
134 fs_reg iid
= abld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
135 abld
.SHR(iid
, g1
, brw_imm_ud(27u));
140 case nir_intrinsic_load_sample_pos
:
141 assert(v
->stage
== MESA_SHADER_FRAGMENT
);
142 reg
= &v
->nir_system_values
[SYSTEM_VALUE_SAMPLE_POS
];
143 if (reg
->file
== BAD_FILE
)
144 *reg
= *v
->emit_samplepos_setup();
147 case nir_intrinsic_load_sample_id
:
148 assert(v
->stage
== MESA_SHADER_FRAGMENT
);
149 reg
= &v
->nir_system_values
[SYSTEM_VALUE_SAMPLE_ID
];
150 if (reg
->file
== BAD_FILE
)
151 *reg
= *v
->emit_sampleid_setup();
154 case nir_intrinsic_load_sample_mask_in
:
155 assert(v
->stage
== MESA_SHADER_FRAGMENT
);
156 assert(v
->devinfo
->gen
>= 7);
157 reg
= &v
->nir_system_values
[SYSTEM_VALUE_SAMPLE_MASK_IN
];
158 if (reg
->file
== BAD_FILE
)
159 *reg
= *v
->emit_samplemaskin_setup();
162 case nir_intrinsic_load_work_group_id
:
163 assert(v
->stage
== MESA_SHADER_COMPUTE
);
164 reg
= &v
->nir_system_values
[SYSTEM_VALUE_WORK_GROUP_ID
];
165 if (reg
->file
== BAD_FILE
)
166 *reg
= *v
->emit_cs_work_group_id_setup();
169 case nir_intrinsic_load_helper_invocation
:
170 assert(v
->stage
== MESA_SHADER_FRAGMENT
);
171 reg
= &v
->nir_system_values
[SYSTEM_VALUE_HELPER_INVOCATION
];
172 if (reg
->file
== BAD_FILE
) {
173 const fs_builder abld
=
174 v
->bld
.annotate("gl_HelperInvocation", NULL
);
176 /* On Gen6+ (gl_HelperInvocation is only exposed on Gen7+) the
177 * pixel mask is in g1.7 of the thread payload.
179 * We move the per-channel pixel enable bit to the low bit of each
180 * channel by shifting the byte containing the pixel mask by the
181 * vector immediate 0x76543210UV.
183 * The region of <1,8,0> reads only 1 byte (the pixel masks for
184 * subspans 0 and 1) in SIMD8 and an additional byte (the pixel
185 * masks for 2 and 3) in SIMD16.
187 fs_reg shifted
= abld
.vgrf(BRW_REGISTER_TYPE_UW
, 1);
189 stride(byte_offset(retype(brw_vec1_grf(1, 0),
190 BRW_REGISTER_TYPE_UB
), 28),
192 brw_imm_v(0x76543210));
194 /* A set bit in the pixel mask means the channel is enabled, but
195 * that is the opposite of gl_HelperInvocation so we need to invert
198 * The negate source-modifier bit of logical instructions on Gen8+
199 * performs 1's complement negation, so we can use that instead of
202 fs_reg inverted
= negate(shifted
);
203 if (v
->devinfo
->gen
< 8) {
204 inverted
= abld
.vgrf(BRW_REGISTER_TYPE_UW
);
205 abld
.NOT(inverted
, shifted
);
208 /* We then resolve the 0/1 result to 0/~0 boolean values by ANDing
209 * with 1 and negating.
211 fs_reg anded
= abld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
212 abld
.AND(anded
, inverted
, brw_imm_uw(1));
214 fs_reg dst
= abld
.vgrf(BRW_REGISTER_TYPE_D
, 1);
215 abld
.MOV(dst
, negate(retype(anded
, BRW_REGISTER_TYPE_D
)));
229 fs_visitor::nir_emit_system_values()
231 nir_system_values
= ralloc_array(mem_ctx
, fs_reg
, SYSTEM_VALUE_MAX
);
232 for (unsigned i
= 0; i
< SYSTEM_VALUE_MAX
; i
++) {
233 nir_system_values
[i
] = fs_reg();
236 /* Always emit SUBGROUP_INVOCATION. Dead code will clean it up if we
237 * never end up using it.
240 const fs_builder abld
= bld
.annotate("gl_SubgroupInvocation", NULL
);
241 fs_reg
®
= nir_system_values
[SYSTEM_VALUE_SUBGROUP_INVOCATION
];
242 reg
= abld
.vgrf(BRW_REGISTER_TYPE_UW
);
244 const fs_builder allbld8
= abld
.group(8, 0).exec_all();
245 allbld8
.MOV(reg
, brw_imm_v(0x76543210));
246 if (dispatch_width
> 8)
247 allbld8
.ADD(byte_offset(reg
, 16), reg
, brw_imm_uw(8u));
248 if (dispatch_width
> 16) {
249 const fs_builder allbld16
= abld
.group(16, 0).exec_all();
250 allbld16
.ADD(byte_offset(reg
, 32), reg
, brw_imm_uw(16u));
254 nir_foreach_function(function
, nir
) {
255 assert(strcmp(function
->name
, "main") == 0);
256 assert(function
->impl
);
257 nir_foreach_block(block
, function
->impl
) {
258 emit_system_values_block(block
, this);
264 * Returns a type based on a reference_type (word, float, half-float) and a
267 * Reference BRW_REGISTER_TYPE are HF,F,DF,W,D,UW,UD.
269 * @FIXME: 64-bit return types are always DF on integer types to maintain
270 * compability with uses of DF previously to the introduction of int64
274 brw_reg_type_from_bit_size(const unsigned bit_size
,
275 const brw_reg_type reference_type
)
277 switch(reference_type
) {
278 case BRW_REGISTER_TYPE_HF
:
279 case BRW_REGISTER_TYPE_F
:
280 case BRW_REGISTER_TYPE_DF
:
283 return BRW_REGISTER_TYPE_HF
;
285 return BRW_REGISTER_TYPE_F
;
287 return BRW_REGISTER_TYPE_DF
;
289 unreachable("Invalid bit size");
291 case BRW_REGISTER_TYPE_W
:
292 case BRW_REGISTER_TYPE_D
:
293 case BRW_REGISTER_TYPE_Q
:
296 return BRW_REGISTER_TYPE_W
;
298 return BRW_REGISTER_TYPE_D
;
300 return BRW_REGISTER_TYPE_Q
;
302 unreachable("Invalid bit size");
304 case BRW_REGISTER_TYPE_UW
:
305 case BRW_REGISTER_TYPE_UD
:
306 case BRW_REGISTER_TYPE_UQ
:
309 return BRW_REGISTER_TYPE_UW
;
311 return BRW_REGISTER_TYPE_UD
;
313 return BRW_REGISTER_TYPE_UQ
;
315 unreachable("Invalid bit size");
318 unreachable("Unknown type");
323 fs_visitor::nir_emit_impl(nir_function_impl
*impl
)
325 nir_locals
= ralloc_array(mem_ctx
, fs_reg
, impl
->reg_alloc
);
326 for (unsigned i
= 0; i
< impl
->reg_alloc
; i
++) {
327 nir_locals
[i
] = fs_reg();
330 foreach_list_typed(nir_register
, reg
, node
, &impl
->registers
) {
331 unsigned array_elems
=
332 reg
->num_array_elems
== 0 ? 1 : reg
->num_array_elems
;
333 unsigned size
= array_elems
* reg
->num_components
;
334 const brw_reg_type reg_type
=
335 brw_reg_type_from_bit_size(reg
->bit_size
, BRW_REGISTER_TYPE_F
);
336 nir_locals
[reg
->index
] = bld
.vgrf(reg_type
, size
);
339 nir_ssa_values
= reralloc(mem_ctx
, nir_ssa_values
, fs_reg
,
342 nir_emit_cf_list(&impl
->body
);
346 fs_visitor::nir_emit_cf_list(exec_list
*list
)
348 exec_list_validate(list
);
349 foreach_list_typed(nir_cf_node
, node
, node
, list
) {
350 switch (node
->type
) {
352 nir_emit_if(nir_cf_node_as_if(node
));
355 case nir_cf_node_loop
:
356 nir_emit_loop(nir_cf_node_as_loop(node
));
359 case nir_cf_node_block
:
360 nir_emit_block(nir_cf_node_as_block(node
));
364 unreachable("Invalid CFG node block");
370 fs_visitor::nir_emit_if(nir_if
*if_stmt
)
372 /* first, put the condition into f0 */
373 fs_inst
*inst
= bld
.MOV(bld
.null_reg_d(),
374 retype(get_nir_src(if_stmt
->condition
),
375 BRW_REGISTER_TYPE_D
));
376 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
378 bld
.IF(BRW_PREDICATE_NORMAL
);
380 nir_emit_cf_list(&if_stmt
->then_list
);
382 /* note: if the else is empty, dead CF elimination will remove it */
383 bld
.emit(BRW_OPCODE_ELSE
);
385 nir_emit_cf_list(&if_stmt
->else_list
);
387 bld
.emit(BRW_OPCODE_ENDIF
);
391 fs_visitor::nir_emit_loop(nir_loop
*loop
)
393 bld
.emit(BRW_OPCODE_DO
);
395 nir_emit_cf_list(&loop
->body
);
397 bld
.emit(BRW_OPCODE_WHILE
);
401 fs_visitor::nir_emit_block(nir_block
*block
)
403 nir_foreach_instr(instr
, block
) {
404 nir_emit_instr(instr
);
409 fs_visitor::nir_emit_instr(nir_instr
*instr
)
411 const fs_builder abld
= bld
.annotate(NULL
, instr
);
413 switch (instr
->type
) {
414 case nir_instr_type_alu
:
415 nir_emit_alu(abld
, nir_instr_as_alu(instr
));
418 case nir_instr_type_intrinsic
:
420 case MESA_SHADER_VERTEX
:
421 nir_emit_vs_intrinsic(abld
, nir_instr_as_intrinsic(instr
));
423 case MESA_SHADER_TESS_CTRL
:
424 nir_emit_tcs_intrinsic(abld
, nir_instr_as_intrinsic(instr
));
426 case MESA_SHADER_TESS_EVAL
:
427 nir_emit_tes_intrinsic(abld
, nir_instr_as_intrinsic(instr
));
429 case MESA_SHADER_GEOMETRY
:
430 nir_emit_gs_intrinsic(abld
, nir_instr_as_intrinsic(instr
));
432 case MESA_SHADER_FRAGMENT
:
433 nir_emit_fs_intrinsic(abld
, nir_instr_as_intrinsic(instr
));
435 case MESA_SHADER_COMPUTE
:
436 nir_emit_cs_intrinsic(abld
, nir_instr_as_intrinsic(instr
));
439 unreachable("unsupported shader stage");
443 case nir_instr_type_tex
:
444 nir_emit_texture(abld
, nir_instr_as_tex(instr
));
447 case nir_instr_type_load_const
:
448 nir_emit_load_const(abld
, nir_instr_as_load_const(instr
));
451 case nir_instr_type_ssa_undef
:
452 /* We create a new VGRF for undefs on every use (by handling
453 * them in get_nir_src()), rather than for each definition.
454 * This helps register coalescing eliminate MOVs from undef.
458 case nir_instr_type_jump
:
459 nir_emit_jump(abld
, nir_instr_as_jump(instr
));
463 unreachable("unknown instruction type");
468 * Recognizes a parent instruction of nir_op_extract_* and changes the type to
472 fs_visitor::optimize_extract_to_float(nir_alu_instr
*instr
,
473 const fs_reg
&result
)
475 if (!instr
->src
[0].src
.is_ssa
||
476 !instr
->src
[0].src
.ssa
->parent_instr
)
479 if (instr
->src
[0].src
.ssa
->parent_instr
->type
!= nir_instr_type_alu
)
482 nir_alu_instr
*src0
=
483 nir_instr_as_alu(instr
->src
[0].src
.ssa
->parent_instr
);
485 if (src0
->op
!= nir_op_extract_u8
&& src0
->op
!= nir_op_extract_u16
&&
486 src0
->op
!= nir_op_extract_i8
&& src0
->op
!= nir_op_extract_i16
)
489 nir_const_value
*element
= nir_src_as_const_value(src0
->src
[1].src
);
490 assert(element
!= NULL
);
492 /* Element type to extract.*/
493 const brw_reg_type type
= brw_int_type(
494 src0
->op
== nir_op_extract_u16
|| src0
->op
== nir_op_extract_i16
? 2 : 1,
495 src0
->op
== nir_op_extract_i16
|| src0
->op
== nir_op_extract_i8
);
497 fs_reg op0
= get_nir_src(src0
->src
[0].src
);
498 op0
.type
= brw_type_for_nir_type(devinfo
,
499 (nir_alu_type
)(nir_op_infos
[src0
->op
].input_types
[0] |
500 nir_src_bit_size(src0
->src
[0].src
)));
501 op0
= offset(op0
, bld
, src0
->src
[0].swizzle
[0]);
503 set_saturate(instr
->dest
.saturate
,
504 bld
.MOV(result
, subscript(op0
, type
, element
->u32
[0])));
509 fs_visitor::optimize_frontfacing_ternary(nir_alu_instr
*instr
,
510 const fs_reg
&result
)
512 if (!instr
->src
[0].src
.is_ssa
||
513 instr
->src
[0].src
.ssa
->parent_instr
->type
!= nir_instr_type_intrinsic
)
516 nir_intrinsic_instr
*src0
=
517 nir_instr_as_intrinsic(instr
->src
[0].src
.ssa
->parent_instr
);
519 if (src0
->intrinsic
!= nir_intrinsic_load_front_face
)
522 nir_const_value
*value1
= nir_src_as_const_value(instr
->src
[1].src
);
523 if (!value1
|| fabsf(value1
->f32
[0]) != 1.0f
)
526 nir_const_value
*value2
= nir_src_as_const_value(instr
->src
[2].src
);
527 if (!value2
|| fabsf(value2
->f32
[0]) != 1.0f
)
530 fs_reg tmp
= vgrf(glsl_type::int_type
);
532 if (devinfo
->gen
>= 6) {
533 /* Bit 15 of g0.0 is 0 if the polygon is front facing. */
534 fs_reg g0
= fs_reg(retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_W
));
536 /* For (gl_FrontFacing ? 1.0 : -1.0), emit:
538 * or(8) tmp.1<2>W g0.0<0,1,0>W 0x00003f80W
539 * and(8) dst<1>D tmp<8,8,1>D 0xbf800000D
541 * and negate g0.0<0,1,0>W for (gl_FrontFacing ? -1.0 : 1.0).
543 * This negation looks like it's safe in practice, because bits 0:4 will
544 * surely be TRIANGLES
547 if (value1
->f32
[0] == -1.0f
) {
551 bld
.OR(subscript(tmp
, BRW_REGISTER_TYPE_W
, 1),
552 g0
, brw_imm_uw(0x3f80));
554 /* Bit 31 of g1.6 is 0 if the polygon is front facing. */
555 fs_reg g1_6
= fs_reg(retype(brw_vec1_grf(1, 6), BRW_REGISTER_TYPE_D
));
557 /* For (gl_FrontFacing ? 1.0 : -1.0), emit:
559 * or(8) tmp<1>D g1.6<0,1,0>D 0x3f800000D
560 * and(8) dst<1>D tmp<8,8,1>D 0xbf800000D
562 * and negate g1.6<0,1,0>D for (gl_FrontFacing ? -1.0 : 1.0).
564 * This negation looks like it's safe in practice, because bits 0:4 will
565 * surely be TRIANGLES
568 if (value1
->f32
[0] == -1.0f
) {
572 bld
.OR(tmp
, g1_6
, brw_imm_d(0x3f800000));
574 bld
.AND(retype(result
, BRW_REGISTER_TYPE_D
), tmp
, brw_imm_d(0xbf800000));
580 emit_find_msb_using_lzd(const fs_builder
&bld
,
581 const fs_reg
&result
,
589 /* LZD of an absolute value source almost always does the right
590 * thing. There are two problem values:
592 * * 0x80000000. Since abs(0x80000000) == 0x80000000, LZD returns
593 * 0. However, findMSB(int(0x80000000)) == 30.
595 * * 0xffffffff. Since abs(0xffffffff) == 1, LZD returns
596 * 31. Section 8.8 (Integer Functions) of the GLSL 4.50 spec says:
598 * For a value of zero or negative one, -1 will be returned.
600 * * Negative powers of two. LZD(abs(-(1<<x))) returns x, but
601 * findMSB(-(1<<x)) should return x-1.
603 * For all negative number cases, including 0x80000000 and
604 * 0xffffffff, the correct value is obtained from LZD if instead of
605 * negating the (already negative) value the logical-not is used. A
606 * conditonal logical-not can be achieved in two instructions.
608 temp
= bld
.vgrf(BRW_REGISTER_TYPE_D
);
610 bld
.ASR(temp
, src
, brw_imm_d(31));
611 bld
.XOR(temp
, temp
, src
);
614 bld
.LZD(retype(result
, BRW_REGISTER_TYPE_UD
),
615 retype(temp
, BRW_REGISTER_TYPE_UD
));
617 /* LZD counts from the MSB side, while GLSL's findMSB() wants the count
618 * from the LSB side. Subtract the result from 31 to convert the MSB
619 * count into an LSB count. If no bits are set, LZD will return 32.
620 * 31-32 = -1, which is exactly what findMSB() is supposed to return.
622 inst
= bld
.ADD(result
, retype(result
, BRW_REGISTER_TYPE_D
), brw_imm_d(31));
623 inst
->src
[0].negate
= true;
627 brw_rnd_mode_from_nir_op (const nir_op op
) {
629 case nir_op_f2f16_rtz
:
630 return BRW_RND_MODE_RTZ
;
631 case nir_op_f2f16_rtne
:
632 return BRW_RND_MODE_RTNE
;
634 unreachable("Operation doesn't support rounding mode");
639 fs_visitor::nir_emit_alu(const fs_builder
&bld
, nir_alu_instr
*instr
)
641 struct brw_wm_prog_key
*fs_key
= (struct brw_wm_prog_key
*) this->key
;
644 fs_reg result
= get_nir_dest(instr
->dest
.dest
);
645 result
.type
= brw_type_for_nir_type(devinfo
,
646 (nir_alu_type
)(nir_op_infos
[instr
->op
].output_type
|
647 nir_dest_bit_size(instr
->dest
.dest
)));
650 for (unsigned i
= 0; i
< nir_op_infos
[instr
->op
].num_inputs
; i
++) {
651 op
[i
] = get_nir_src(instr
->src
[i
].src
);
652 op
[i
].type
= brw_type_for_nir_type(devinfo
,
653 (nir_alu_type
)(nir_op_infos
[instr
->op
].input_types
[i
] |
654 nir_src_bit_size(instr
->src
[i
].src
)));
655 op
[i
].abs
= instr
->src
[i
].abs
;
656 op
[i
].negate
= instr
->src
[i
].negate
;
659 /* We get a bunch of mov's out of the from_ssa pass and they may still
660 * be vectorized. We'll handle them as a special-case. We'll also
661 * handle vecN here because it's basically the same thing.
669 fs_reg temp
= result
;
670 bool need_extra_copy
= false;
671 for (unsigned i
= 0; i
< nir_op_infos
[instr
->op
].num_inputs
; i
++) {
672 if (!instr
->src
[i
].src
.is_ssa
&&
673 instr
->dest
.dest
.reg
.reg
== instr
->src
[i
].src
.reg
.reg
) {
674 need_extra_copy
= true;
675 temp
= bld
.vgrf(result
.type
, 4);
680 for (unsigned i
= 0; i
< 4; i
++) {
681 if (!(instr
->dest
.write_mask
& (1 << i
)))
684 if (instr
->op
== nir_op_imov
|| instr
->op
== nir_op_fmov
) {
685 inst
= bld
.MOV(offset(temp
, bld
, i
),
686 offset(op
[0], bld
, instr
->src
[0].swizzle
[i
]));
688 inst
= bld
.MOV(offset(temp
, bld
, i
),
689 offset(op
[i
], bld
, instr
->src
[i
].swizzle
[0]));
691 inst
->saturate
= instr
->dest
.saturate
;
694 /* In this case the source and destination registers were the same,
695 * so we need to insert an extra set of moves in order to deal with
698 if (need_extra_copy
) {
699 for (unsigned i
= 0; i
< 4; i
++) {
700 if (!(instr
->dest
.write_mask
& (1 << i
)))
703 bld
.MOV(offset(result
, bld
, i
), offset(temp
, bld
, i
));
712 /* At this point, we have dealt with any instruction that operates on
713 * more than a single channel. Therefore, we can just adjust the source
714 * and destination registers for that channel and emit the instruction.
716 unsigned channel
= 0;
717 if (nir_op_infos
[instr
->op
].output_size
== 0) {
718 /* Since NIR is doing the scalarizing for us, we should only ever see
719 * vectorized operations with a single channel.
721 assert(_mesa_bitcount(instr
->dest
.write_mask
) == 1);
722 channel
= ffs(instr
->dest
.write_mask
) - 1;
724 result
= offset(result
, bld
, channel
);
727 for (unsigned i
= 0; i
< nir_op_infos
[instr
->op
].num_inputs
; i
++) {
728 assert(nir_op_infos
[instr
->op
].input_sizes
[i
] < 2);
729 op
[i
] = offset(op
[i
], bld
, instr
->src
[i
].swizzle
[channel
]);
735 if (optimize_extract_to_float(instr
, result
))
737 inst
= bld
.MOV(result
, op
[0]);
738 inst
->saturate
= instr
->dest
.saturate
;
741 case nir_op_f2f16_rtne
:
742 case nir_op_f2f16_rtz
:
743 bld
.emit(SHADER_OPCODE_RND_MODE
, bld
.null_reg_ud(),
744 brw_imm_d(brw_rnd_mode_from_nir_op(instr
->op
)));
747 /* In theory, it would be better to use BRW_OPCODE_F32TO16. Depending
748 * on the HW gen, it is a special hw opcode or just a MOV, and
749 * brw_F32TO16 (at brw_eu_emit) would do the work to chose.
751 * But if we want to use that opcode, we need to provide support on
752 * different optimizations and lowerings. As right now HF support is
753 * only for gen8+, it will be better to use directly the MOV, and use
754 * BRW_OPCODE_F32TO16 when/if we work for HF support on gen7.
757 case nir_op_f2f16_undef
:
758 inst
= bld
.MOV(result
, op
[0]);
759 inst
->saturate
= instr
->dest
.saturate
;
769 /* CHV PRM, vol07, 3D Media GPGPU Engine, Register Region Restrictions:
771 * "When source or destination is 64b (...), regioning in Align1
772 * must follow these rules:
774 * 1. Source and destination horizontal stride must be aligned to
778 * This means that 32-bit to 64-bit conversions need to have the 32-bit
779 * data elements aligned to 64-bit. This restriction does not apply to
782 if (nir_dest_bit_size(instr
->dest
.dest
) == 64 &&
783 nir_src_bit_size(instr
->src
[0].src
) == 32 &&
784 (devinfo
->is_cherryview
|| gen_device_info_is_9lp(devinfo
))) {
785 fs_reg tmp
= bld
.vgrf(result
.type
, 1);
786 tmp
= subscript(tmp
, op
[0].type
, 0);
787 inst
= bld
.MOV(tmp
, op
[0]);
788 inst
= bld
.MOV(result
, tmp
);
789 inst
->saturate
= instr
->dest
.saturate
;
800 inst
= bld
.MOV(result
, op
[0]);
801 inst
->saturate
= instr
->dest
.saturate
;
806 /* Straightforward since the source can be assumed to be
809 set_condmod(BRW_CONDITIONAL_NZ
, bld
.MOV(result
, op
[0]));
810 set_predicate(BRW_PREDICATE_NORMAL
, bld
.MOV(result
, brw_imm_f(1.0f
)));
812 } else if (type_sz(op
[0].type
) < 8) {
813 /* AND(val, 0x80000000) gives the sign bit.
815 * Predicated OR ORs 1.0 (0x3f800000) with the sign bit if val is not
818 bld
.CMP(bld
.null_reg_f(), op
[0], brw_imm_f(0.0f
), BRW_CONDITIONAL_NZ
);
820 fs_reg result_int
= retype(result
, BRW_REGISTER_TYPE_UD
);
821 op
[0].type
= BRW_REGISTER_TYPE_UD
;
822 result
.type
= BRW_REGISTER_TYPE_UD
;
823 bld
.AND(result_int
, op
[0], brw_imm_ud(0x80000000u
));
825 inst
= bld
.OR(result_int
, result_int
, brw_imm_ud(0x3f800000u
));
826 inst
->predicate
= BRW_PREDICATE_NORMAL
;
827 if (instr
->dest
.saturate
) {
828 inst
= bld
.MOV(result
, result
);
829 inst
->saturate
= true;
832 /* For doubles we do the same but we need to consider:
834 * - 2-src instructions can't operate with 64-bit immediates
835 * - The sign is encoded in the high 32-bit of each DF
836 * - We need to produce a DF result.
839 fs_reg zero
= vgrf(glsl_type::double_type
);
840 bld
.MOV(zero
, setup_imm_df(bld
, 0.0));
841 bld
.CMP(bld
.null_reg_df(), op
[0], zero
, BRW_CONDITIONAL_NZ
);
843 bld
.MOV(result
, zero
);
845 fs_reg r
= subscript(result
, BRW_REGISTER_TYPE_UD
, 1);
846 bld
.AND(r
, subscript(op
[0], BRW_REGISTER_TYPE_UD
, 1),
847 brw_imm_ud(0x80000000u
));
849 set_predicate(BRW_PREDICATE_NORMAL
,
850 bld
.OR(r
, r
, brw_imm_ud(0x3ff00000u
)));
852 if (instr
->dest
.saturate
) {
853 inst
= bld
.MOV(result
, result
);
854 inst
->saturate
= true;
861 /* ASR(val, 31) -> negative val generates 0xffffffff (signed -1).
862 * -> non-negative val generates 0x00000000.
863 * Predicated OR sets 1 if val is positive.
865 uint32_t bit_size
= nir_dest_bit_size(instr
->dest
.dest
);
866 assert(bit_size
== 32 || bit_size
== 16);
868 fs_reg zero
= bit_size
== 32 ? brw_imm_d(0) : brw_imm_w(0);
869 fs_reg one
= bit_size
== 32 ? brw_imm_d(1) : brw_imm_w(1);
870 fs_reg shift
= bit_size
== 32 ? brw_imm_d(31) : brw_imm_w(15);
872 bld
.CMP(bld
.null_reg_d(), op
[0], zero
, BRW_CONDITIONAL_G
);
873 bld
.ASR(result
, op
[0], shift
);
874 inst
= bld
.OR(result
, result
, one
);
875 inst
->predicate
= BRW_PREDICATE_NORMAL
;
880 inst
= bld
.emit(SHADER_OPCODE_RCP
, result
, op
[0]);
881 inst
->saturate
= instr
->dest
.saturate
;
885 inst
= bld
.emit(SHADER_OPCODE_EXP2
, result
, op
[0]);
886 inst
->saturate
= instr
->dest
.saturate
;
890 inst
= bld
.emit(SHADER_OPCODE_LOG2
, result
, op
[0]);
891 inst
->saturate
= instr
->dest
.saturate
;
895 inst
= bld
.emit(SHADER_OPCODE_SIN
, result
, op
[0]);
896 inst
->saturate
= instr
->dest
.saturate
;
900 inst
= bld
.emit(SHADER_OPCODE_COS
, result
, op
[0]);
901 inst
->saturate
= instr
->dest
.saturate
;
905 if (fs_key
->high_quality_derivatives
) {
906 inst
= bld
.emit(FS_OPCODE_DDX_FINE
, result
, op
[0]);
908 inst
= bld
.emit(FS_OPCODE_DDX_COARSE
, result
, op
[0]);
910 inst
->saturate
= instr
->dest
.saturate
;
912 case nir_op_fddx_fine
:
913 inst
= bld
.emit(FS_OPCODE_DDX_FINE
, result
, op
[0]);
914 inst
->saturate
= instr
->dest
.saturate
;
916 case nir_op_fddx_coarse
:
917 inst
= bld
.emit(FS_OPCODE_DDX_COARSE
, result
, op
[0]);
918 inst
->saturate
= instr
->dest
.saturate
;
921 if (fs_key
->high_quality_derivatives
) {
922 inst
= bld
.emit(FS_OPCODE_DDY_FINE
, result
, op
[0]);
924 inst
= bld
.emit(FS_OPCODE_DDY_COARSE
, result
, op
[0]);
926 inst
->saturate
= instr
->dest
.saturate
;
928 case nir_op_fddy_fine
:
929 inst
= bld
.emit(FS_OPCODE_DDY_FINE
, result
, op
[0]);
930 inst
->saturate
= instr
->dest
.saturate
;
932 case nir_op_fddy_coarse
:
933 inst
= bld
.emit(FS_OPCODE_DDY_COARSE
, result
, op
[0]);
934 inst
->saturate
= instr
->dest
.saturate
;
939 inst
= bld
.ADD(result
, op
[0], op
[1]);
940 inst
->saturate
= instr
->dest
.saturate
;
944 inst
= bld
.MUL(result
, op
[0], op
[1]);
945 inst
->saturate
= instr
->dest
.saturate
;
949 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
950 bld
.MUL(result
, op
[0], op
[1]);
953 case nir_op_imul_high
:
954 case nir_op_umul_high
:
955 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
956 bld
.emit(SHADER_OPCODE_MULH
, result
, op
[0], op
[1]);
961 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
962 bld
.emit(SHADER_OPCODE_INT_QUOTIENT
, result
, op
[0], op
[1]);
965 case nir_op_uadd_carry
:
966 unreachable("Should have been lowered by carry_to_arith().");
968 case nir_op_usub_borrow
:
969 unreachable("Should have been lowered by borrow_to_arith().");
973 /* According to the sign table for INT DIV in the Ivy Bridge PRM, it
974 * appears that our hardware just does the right thing for signed
977 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
978 bld
.emit(SHADER_OPCODE_INT_REMAINDER
, result
, op
[0], op
[1]);
982 /* Get a regular C-style remainder. If a % b == 0, set the predicate. */
983 bld
.emit(SHADER_OPCODE_INT_REMAINDER
, result
, op
[0], op
[1]);
985 /* Math instructions don't support conditional mod */
986 inst
= bld
.MOV(bld
.null_reg_d(), result
);
987 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
989 /* Now, we need to determine if signs of the sources are different.
990 * When we XOR the sources, the top bit is 0 if they are the same and 1
991 * if they are different. We can then use a conditional modifier to
992 * turn that into a predicate. This leads us to an XOR.l instruction.
994 * Technically, according to the PRM, you're not allowed to use .l on a
995 * XOR instruction. However, emperical experiments and Curro's reading
996 * of the simulator source both indicate that it's safe.
998 fs_reg tmp
= bld
.vgrf(BRW_REGISTER_TYPE_D
);
999 inst
= bld
.XOR(tmp
, op
[0], op
[1]);
1000 inst
->predicate
= BRW_PREDICATE_NORMAL
;
1001 inst
->conditional_mod
= BRW_CONDITIONAL_L
;
1003 /* If the result of the initial remainder operation is non-zero and the
1004 * two sources have different signs, add in a copy of op[1] to get the
1005 * final integer modulus value.
1007 inst
= bld
.ADD(result
, result
, op
[1]);
1008 inst
->predicate
= BRW_PREDICATE_NORMAL
;
1016 fs_reg dest
= result
;
1017 if (nir_src_bit_size(instr
->src
[0].src
) > 32) {
1018 dest
= bld
.vgrf(BRW_REGISTER_TYPE_DF
, 1);
1020 brw_conditional_mod cond
;
1021 switch (instr
->op
) {
1023 cond
= BRW_CONDITIONAL_L
;
1026 cond
= BRW_CONDITIONAL_GE
;
1029 cond
= BRW_CONDITIONAL_Z
;
1032 cond
= BRW_CONDITIONAL_NZ
;
1035 unreachable("bad opcode");
1037 bld
.CMP(dest
, op
[0], op
[1], cond
);
1038 if (nir_src_bit_size(instr
->src
[0].src
) > 32) {
1039 bld
.MOV(result
, subscript(dest
, BRW_REGISTER_TYPE_UD
, 0));
1050 fs_reg dest
= result
;
1051 if (nir_src_bit_size(instr
->src
[0].src
) > 32) {
1052 dest
= bld
.vgrf(BRW_REGISTER_TYPE_UQ
, 1);
1055 brw_conditional_mod cond
;
1056 switch (instr
->op
) {
1059 cond
= BRW_CONDITIONAL_L
;
1063 cond
= BRW_CONDITIONAL_GE
;
1066 cond
= BRW_CONDITIONAL_Z
;
1069 cond
= BRW_CONDITIONAL_NZ
;
1072 unreachable("bad opcode");
1074 bld
.CMP(dest
, op
[0], op
[1], cond
);
1075 if (nir_src_bit_size(instr
->src
[0].src
) > 32) {
1076 bld
.MOV(result
, subscript(dest
, BRW_REGISTER_TYPE_UD
, 0));
1082 if (devinfo
->gen
>= 8) {
1083 op
[0] = resolve_source_modifiers(op
[0]);
1085 bld
.NOT(result
, op
[0]);
1088 if (devinfo
->gen
>= 8) {
1089 op
[0] = resolve_source_modifiers(op
[0]);
1090 op
[1] = resolve_source_modifiers(op
[1]);
1092 bld
.XOR(result
, op
[0], op
[1]);
1095 if (devinfo
->gen
>= 8) {
1096 op
[0] = resolve_source_modifiers(op
[0]);
1097 op
[1] = resolve_source_modifiers(op
[1]);
1099 bld
.OR(result
, op
[0], op
[1]);
1102 if (devinfo
->gen
>= 8) {
1103 op
[0] = resolve_source_modifiers(op
[0]);
1104 op
[1] = resolve_source_modifiers(op
[1]);
1106 bld
.AND(result
, op
[0], op
[1]);
1112 case nir_op_ball_fequal2
:
1113 case nir_op_ball_iequal2
:
1114 case nir_op_ball_fequal3
:
1115 case nir_op_ball_iequal3
:
1116 case nir_op_ball_fequal4
:
1117 case nir_op_ball_iequal4
:
1118 case nir_op_bany_fnequal2
:
1119 case nir_op_bany_inequal2
:
1120 case nir_op_bany_fnequal3
:
1121 case nir_op_bany_inequal3
:
1122 case nir_op_bany_fnequal4
:
1123 case nir_op_bany_inequal4
:
1124 unreachable("Lowered by nir_lower_alu_reductions");
1126 case nir_op_fnoise1_1
:
1127 case nir_op_fnoise1_2
:
1128 case nir_op_fnoise1_3
:
1129 case nir_op_fnoise1_4
:
1130 case nir_op_fnoise2_1
:
1131 case nir_op_fnoise2_2
:
1132 case nir_op_fnoise2_3
:
1133 case nir_op_fnoise2_4
:
1134 case nir_op_fnoise3_1
:
1135 case nir_op_fnoise3_2
:
1136 case nir_op_fnoise3_3
:
1137 case nir_op_fnoise3_4
:
1138 case nir_op_fnoise4_1
:
1139 case nir_op_fnoise4_2
:
1140 case nir_op_fnoise4_3
:
1141 case nir_op_fnoise4_4
:
1142 unreachable("not reached: should be handled by lower_noise");
1145 unreachable("not reached: should be handled by ldexp_to_arith()");
1148 inst
= bld
.emit(SHADER_OPCODE_SQRT
, result
, op
[0]);
1149 inst
->saturate
= instr
->dest
.saturate
;
1153 inst
= bld
.emit(SHADER_OPCODE_RSQ
, result
, op
[0]);
1154 inst
->saturate
= instr
->dest
.saturate
;
1159 bld
.MOV(result
, negate(op
[0]));
1164 if (nir_src_bit_size(instr
->src
[0].src
) == 64) {
1165 /* two-argument instructions can't take 64-bit immediates */
1169 if (instr
->op
== nir_op_f2b
) {
1170 zero
= vgrf(glsl_type::double_type
);
1171 tmp
= vgrf(glsl_type::double_type
);
1172 bld
.MOV(zero
, setup_imm_df(bld
, 0.0));
1174 zero
= vgrf(glsl_type::int64_t_type
);
1175 tmp
= vgrf(glsl_type::int64_t_type
);
1176 bld
.MOV(zero
, brw_imm_q(0));
1179 /* A SIMD16 execution needs to be split in two instructions, so use
1180 * a vgrf instead of the flag register as dst so instruction splitting
1183 bld
.CMP(tmp
, op
[0], zero
, BRW_CONDITIONAL_NZ
);
1184 bld
.MOV(result
, subscript(tmp
, BRW_REGISTER_TYPE_UD
, 0));
1186 if (instr
->op
== nir_op_f2b
) {
1187 bld
.CMP(result
, op
[0], brw_imm_f(0.0f
), BRW_CONDITIONAL_NZ
);
1189 bld
.CMP(result
, op
[0], brw_imm_d(0), BRW_CONDITIONAL_NZ
);
1195 inst
= bld
.RNDZ(result
, op
[0]);
1196 inst
->saturate
= instr
->dest
.saturate
;
1199 case nir_op_fceil
: {
1200 op
[0].negate
= !op
[0].negate
;
1201 fs_reg temp
= vgrf(glsl_type::float_type
);
1202 bld
.RNDD(temp
, op
[0]);
1204 inst
= bld
.MOV(result
, temp
);
1205 inst
->saturate
= instr
->dest
.saturate
;
1209 inst
= bld
.RNDD(result
, op
[0]);
1210 inst
->saturate
= instr
->dest
.saturate
;
1213 inst
= bld
.FRC(result
, op
[0]);
1214 inst
->saturate
= instr
->dest
.saturate
;
1216 case nir_op_fround_even
:
1217 inst
= bld
.RNDE(result
, op
[0]);
1218 inst
->saturate
= instr
->dest
.saturate
;
1221 case nir_op_fquantize2f16
: {
1222 fs_reg tmp16
= bld
.vgrf(BRW_REGISTER_TYPE_D
);
1223 fs_reg tmp32
= bld
.vgrf(BRW_REGISTER_TYPE_F
);
1224 fs_reg zero
= bld
.vgrf(BRW_REGISTER_TYPE_F
);
1226 /* The destination stride must be at least as big as the source stride. */
1227 tmp16
.type
= BRW_REGISTER_TYPE_W
;
1230 /* Check for denormal */
1231 fs_reg abs_src0
= op
[0];
1232 abs_src0
.abs
= true;
1233 bld
.CMP(bld
.null_reg_f(), abs_src0
, brw_imm_f(ldexpf(1.0, -14)),
1235 /* Get the appropriately signed zero */
1236 bld
.AND(retype(zero
, BRW_REGISTER_TYPE_UD
),
1237 retype(op
[0], BRW_REGISTER_TYPE_UD
),
1238 brw_imm_ud(0x80000000));
1239 /* Do the actual F32 -> F16 -> F32 conversion */
1240 bld
.emit(BRW_OPCODE_F32TO16
, tmp16
, op
[0]);
1241 bld
.emit(BRW_OPCODE_F16TO32
, tmp32
, tmp16
);
1242 /* Select that or zero based on normal status */
1243 inst
= bld
.SEL(result
, zero
, tmp32
);
1244 inst
->predicate
= BRW_PREDICATE_NORMAL
;
1245 inst
->saturate
= instr
->dest
.saturate
;
1252 inst
= bld
.emit_minmax(result
, op
[0], op
[1], BRW_CONDITIONAL_L
);
1253 inst
->saturate
= instr
->dest
.saturate
;
1259 inst
= bld
.emit_minmax(result
, op
[0], op
[1], BRW_CONDITIONAL_GE
);
1260 inst
->saturate
= instr
->dest
.saturate
;
1263 case nir_op_pack_snorm_2x16
:
1264 case nir_op_pack_snorm_4x8
:
1265 case nir_op_pack_unorm_2x16
:
1266 case nir_op_pack_unorm_4x8
:
1267 case nir_op_unpack_snorm_2x16
:
1268 case nir_op_unpack_snorm_4x8
:
1269 case nir_op_unpack_unorm_2x16
:
1270 case nir_op_unpack_unorm_4x8
:
1271 case nir_op_unpack_half_2x16
:
1272 case nir_op_pack_half_2x16
:
1273 unreachable("not reached: should be handled by lower_packing_builtins");
1275 case nir_op_unpack_half_2x16_split_x
:
1276 inst
= bld
.emit(FS_OPCODE_UNPACK_HALF_2x16_SPLIT_X
, result
, op
[0]);
1277 inst
->saturate
= instr
->dest
.saturate
;
1279 case nir_op_unpack_half_2x16_split_y
:
1280 inst
= bld
.emit(FS_OPCODE_UNPACK_HALF_2x16_SPLIT_Y
, result
, op
[0]);
1281 inst
->saturate
= instr
->dest
.saturate
;
1284 case nir_op_pack_64_2x32_split
:
1285 bld
.emit(FS_OPCODE_PACK
, result
, op
[0], op
[1]);
1288 case nir_op_unpack_64_2x32_split_x
:
1289 case nir_op_unpack_64_2x32_split_y
: {
1290 if (instr
->op
== nir_op_unpack_64_2x32_split_x
)
1291 bld
.MOV(result
, subscript(op
[0], BRW_REGISTER_TYPE_UD
, 0));
1293 bld
.MOV(result
, subscript(op
[0], BRW_REGISTER_TYPE_UD
, 1));
1298 inst
= bld
.emit(SHADER_OPCODE_POW
, result
, op
[0], op
[1]);
1299 inst
->saturate
= instr
->dest
.saturate
;
1302 case nir_op_bitfield_reverse
:
1303 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1304 bld
.BFREV(result
, op
[0]);
1307 case nir_op_bit_count
:
1308 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1309 bld
.CBIT(result
, op
[0]);
1312 case nir_op_ufind_msb
: {
1313 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1314 emit_find_msb_using_lzd(bld
, result
, op
[0], false);
1318 case nir_op_ifind_msb
: {
1319 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1321 if (devinfo
->gen
< 7) {
1322 emit_find_msb_using_lzd(bld
, result
, op
[0], true);
1324 bld
.FBH(retype(result
, BRW_REGISTER_TYPE_UD
), op
[0]);
1326 /* FBH counts from the MSB side, while GLSL's findMSB() wants the
1327 * count from the LSB side. If FBH didn't return an error
1328 * (0xFFFFFFFF), then subtract the result from 31 to convert the MSB
1329 * count into an LSB count.
1331 bld
.CMP(bld
.null_reg_d(), result
, brw_imm_d(-1), BRW_CONDITIONAL_NZ
);
1333 inst
= bld
.ADD(result
, result
, brw_imm_d(31));
1334 inst
->predicate
= BRW_PREDICATE_NORMAL
;
1335 inst
->src
[0].negate
= true;
1340 case nir_op_find_lsb
:
1341 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1343 if (devinfo
->gen
< 7) {
1344 fs_reg temp
= vgrf(glsl_type::int_type
);
1346 /* (x & -x) generates a value that consists of only the LSB of x.
1347 * For all powers of 2, findMSB(y) == findLSB(y).
1349 fs_reg src
= retype(op
[0], BRW_REGISTER_TYPE_D
);
1350 fs_reg negated_src
= src
;
1352 /* One must be negated, and the other must be non-negated. It
1353 * doesn't matter which is which.
1355 negated_src
.negate
= true;
1358 bld
.AND(temp
, src
, negated_src
);
1359 emit_find_msb_using_lzd(bld
, result
, temp
, false);
1361 bld
.FBL(result
, op
[0]);
1365 case nir_op_ubitfield_extract
:
1366 case nir_op_ibitfield_extract
:
1367 unreachable("should have been lowered");
1370 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1371 bld
.BFE(result
, op
[2], op
[1], op
[0]);
1374 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1375 bld
.BFI1(result
, op
[0], op
[1]);
1378 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1379 bld
.BFI2(result
, op
[0], op
[1], op
[2]);
1382 case nir_op_bitfield_insert
:
1383 unreachable("not reached: should have been lowered");
1388 fs_reg shift_count
= op
[1];
1390 if (devinfo
->is_cherryview
|| gen_device_info_is_9lp(devinfo
)) {
1391 if (op
[1].file
== VGRF
&&
1392 (result
.type
== BRW_REGISTER_TYPE_Q
||
1393 result
.type
== BRW_REGISTER_TYPE_UQ
)) {
1394 shift_count
= fs_reg(VGRF
, alloc
.allocate(dispatch_width
/ 4),
1395 BRW_REGISTER_TYPE_UD
);
1396 shift_count
.stride
= 2;
1397 bld
.MOV(shift_count
, op
[1]);
1401 switch (instr
->op
) {
1403 bld
.SHL(result
, op
[0], shift_count
);
1406 bld
.ASR(result
, op
[0], shift_count
);
1409 bld
.SHR(result
, op
[0], shift_count
);
1412 unreachable("not reached");
1417 case nir_op_pack_half_2x16_split
:
1418 bld
.emit(FS_OPCODE_PACK_HALF_2x16_SPLIT
, result
, op
[0], op
[1]);
1422 inst
= bld
.MAD(result
, op
[2], op
[1], op
[0]);
1423 inst
->saturate
= instr
->dest
.saturate
;
1427 inst
= bld
.LRP(result
, op
[0], op
[1], op
[2]);
1428 inst
->saturate
= instr
->dest
.saturate
;
1432 if (optimize_frontfacing_ternary(instr
, result
))
1435 bld
.CMP(bld
.null_reg_d(), op
[0], brw_imm_d(0), BRW_CONDITIONAL_NZ
);
1436 inst
= bld
.SEL(result
, op
[1], op
[2]);
1437 inst
->predicate
= BRW_PREDICATE_NORMAL
;
1440 case nir_op_extract_u8
:
1441 case nir_op_extract_i8
: {
1442 nir_const_value
*byte
= nir_src_as_const_value(instr
->src
[1].src
);
1443 assert(byte
!= NULL
);
1448 * There is no direct conversion from B/UB to Q/UQ or Q/UQ to B/UB.
1449 * Use two instructions and a word or DWord intermediate integer type.
1451 if (nir_dest_bit_size(instr
->dest
.dest
) == 64) {
1452 const brw_reg_type type
= brw_int_type(2, instr
->op
== nir_op_extract_i8
);
1454 if (instr
->op
== nir_op_extract_i8
) {
1455 /* If we need to sign extend, extract to a word first */
1456 fs_reg w_temp
= bld
.vgrf(BRW_REGISTER_TYPE_W
);
1457 bld
.MOV(w_temp
, subscript(op
[0], type
, byte
->u32
[0]));
1458 bld
.MOV(result
, w_temp
);
1460 /* Otherwise use an AND with 0xff and a word type */
1461 bld
.AND(result
, subscript(op
[0], type
, byte
->u32
[0] / 2), brw_imm_uw(0xff));
1464 const brw_reg_type type
= brw_int_type(1, instr
->op
== nir_op_extract_i8
);
1465 bld
.MOV(result
, subscript(op
[0], type
, byte
->u32
[0]));
1470 case nir_op_extract_u16
:
1471 case nir_op_extract_i16
: {
1472 const brw_reg_type type
= brw_int_type(2, instr
->op
== nir_op_extract_i16
);
1473 nir_const_value
*word
= nir_src_as_const_value(instr
->src
[1].src
);
1474 assert(word
!= NULL
);
1475 bld
.MOV(result
, subscript(op
[0], type
, word
->u32
[0]));
1480 unreachable("unhandled instruction");
1483 /* If we need to do a boolean resolve, replace the result with -(x & 1)
1484 * to sign extend the low bit to 0/~0
1486 if (devinfo
->gen
<= 5 &&
1487 (instr
->instr
.pass_flags
& BRW_NIR_BOOLEAN_MASK
) == BRW_NIR_BOOLEAN_NEEDS_RESOLVE
) {
1488 fs_reg masked
= vgrf(glsl_type::int_type
);
1489 bld
.AND(masked
, result
, brw_imm_d(1));
1490 masked
.negate
= true;
1491 bld
.MOV(retype(result
, BRW_REGISTER_TYPE_D
), masked
);
1496 fs_visitor::nir_emit_load_const(const fs_builder
&bld
,
1497 nir_load_const_instr
*instr
)
1499 const brw_reg_type reg_type
=
1500 brw_reg_type_from_bit_size(instr
->def
.bit_size
, BRW_REGISTER_TYPE_D
);
1501 fs_reg reg
= bld
.vgrf(reg_type
, instr
->def
.num_components
);
1503 switch (instr
->def
.bit_size
) {
1505 for (unsigned i
= 0; i
< instr
->def
.num_components
; i
++)
1506 bld
.MOV(offset(reg
, bld
, i
), brw_imm_d(instr
->value
.i32
[i
]));
1510 assert(devinfo
->gen
>= 7);
1511 if (devinfo
->gen
== 7) {
1512 /* We don't get 64-bit integer types until gen8 */
1513 for (unsigned i
= 0; i
< instr
->def
.num_components
; i
++) {
1514 bld
.MOV(retype(offset(reg
, bld
, i
), BRW_REGISTER_TYPE_DF
),
1515 setup_imm_df(bld
, instr
->value
.f64
[i
]));
1518 for (unsigned i
= 0; i
< instr
->def
.num_components
; i
++)
1519 bld
.MOV(offset(reg
, bld
, i
), brw_imm_q(instr
->value
.i64
[i
]));
1524 unreachable("Invalid bit size");
1527 nir_ssa_values
[instr
->def
.index
] = reg
;
1531 fs_visitor::get_nir_src(const nir_src
&src
)
1535 if (src
.ssa
->parent_instr
->type
== nir_instr_type_ssa_undef
) {
1536 const brw_reg_type reg_type
=
1537 brw_reg_type_from_bit_size(src
.ssa
->bit_size
, BRW_REGISTER_TYPE_D
);
1538 reg
= bld
.vgrf(reg_type
, src
.ssa
->num_components
);
1540 reg
= nir_ssa_values
[src
.ssa
->index
];
1543 /* We don't handle indirects on locals */
1544 assert(src
.reg
.indirect
== NULL
);
1545 reg
= offset(nir_locals
[src
.reg
.reg
->index
], bld
,
1546 src
.reg
.base_offset
* src
.reg
.reg
->num_components
);
1549 if (nir_src_bit_size(src
) == 64 && devinfo
->gen
== 7) {
1550 /* The only 64-bit type available on gen7 is DF, so use that. */
1551 reg
.type
= BRW_REGISTER_TYPE_DF
;
1553 /* To avoid floating-point denorm flushing problems, set the type by
1554 * default to an integer type - instructions that need floating point
1555 * semantics will set this to F if they need to
1557 reg
.type
= brw_reg_type_from_bit_size(nir_src_bit_size(src
),
1558 BRW_REGISTER_TYPE_D
);
1565 * Return an IMM for constants; otherwise call get_nir_src() as normal.
1567 * This function should not be called on any value which may be 64 bits.
1568 * We could theoretically support 64-bit on gen8+ but we choose not to
1569 * because it wouldn't work in general (no gen7 support) and there are
1570 * enough restrictions in 64-bit immediates that you can't take the return
1571 * value and treat it the same as the result of get_nir_src().
1574 fs_visitor::get_nir_src_imm(const nir_src
&src
)
1576 nir_const_value
*val
= nir_src_as_const_value(src
);
1577 assert(nir_src_bit_size(src
) == 32);
1578 return val
? fs_reg(brw_imm_d(val
->i32
[0])) : get_nir_src(src
);
1582 fs_visitor::get_nir_dest(const nir_dest
&dest
)
1585 const brw_reg_type reg_type
=
1586 brw_reg_type_from_bit_size(dest
.ssa
.bit_size
, BRW_REGISTER_TYPE_F
);
1587 nir_ssa_values
[dest
.ssa
.index
] =
1588 bld
.vgrf(reg_type
, dest
.ssa
.num_components
);
1589 return nir_ssa_values
[dest
.ssa
.index
];
1591 /* We don't handle indirects on locals */
1592 assert(dest
.reg
.indirect
== NULL
);
1593 return offset(nir_locals
[dest
.reg
.reg
->index
], bld
,
1594 dest
.reg
.base_offset
* dest
.reg
.reg
->num_components
);
1599 fs_visitor::get_nir_image_deref(const nir_deref_var
*deref
)
1601 fs_reg
image(UNIFORM
, deref
->var
->data
.driver_location
/ 4,
1602 BRW_REGISTER_TYPE_UD
);
1604 unsigned indirect_max
= 0;
1606 for (const nir_deref
*tail
= &deref
->deref
; tail
->child
;
1607 tail
= tail
->child
) {
1608 const nir_deref_array
*deref_array
= nir_deref_as_array(tail
->child
);
1609 assert(tail
->child
->deref_type
== nir_deref_type_array
);
1610 const unsigned size
= glsl_get_length(tail
->type
);
1611 const unsigned element_size
= type_size_scalar(deref_array
->deref
.type
);
1612 const unsigned base
= MIN2(deref_array
->base_offset
, size
- 1);
1613 image
= offset(image
, bld
, base
* element_size
);
1615 if (deref_array
->deref_array_type
== nir_deref_array_type_indirect
) {
1616 fs_reg tmp
= vgrf(glsl_type::uint_type
);
1618 /* Accessing an invalid surface index with the dataport can result
1619 * in a hang. According to the spec "if the index used to
1620 * select an individual element is negative or greater than or
1621 * equal to the size of the array, the results of the operation
1622 * are undefined but may not lead to termination" -- which is one
1623 * of the possible outcomes of the hang. Clamp the index to
1624 * prevent access outside of the array bounds.
1626 bld
.emit_minmax(tmp
, retype(get_nir_src(deref_array
->indirect
),
1627 BRW_REGISTER_TYPE_UD
),
1628 brw_imm_ud(size
- base
- 1), BRW_CONDITIONAL_L
);
1630 indirect_max
+= element_size
* (tail
->type
->length
- 1);
1632 bld
.MUL(tmp
, tmp
, brw_imm_ud(element_size
* 4));
1633 if (indirect
.file
== BAD_FILE
) {
1636 bld
.ADD(indirect
, indirect
, tmp
);
1641 if (indirect
.file
== BAD_FILE
) {
1644 /* Emit a pile of MOVs to load the uniform into a temporary. The
1645 * dead-code elimination pass will get rid of what we don't use.
1647 fs_reg tmp
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, BRW_IMAGE_PARAM_SIZE
);
1648 for (unsigned j
= 0; j
< BRW_IMAGE_PARAM_SIZE
; j
++) {
1649 bld
.emit(SHADER_OPCODE_MOV_INDIRECT
,
1650 offset(tmp
, bld
, j
), offset(image
, bld
, j
),
1651 indirect
, brw_imm_ud((indirect_max
+ 1) * 4));
1658 fs_visitor::emit_percomp(const fs_builder
&bld
, const fs_inst
&inst
,
1661 for (unsigned i
= 0; i
< 4; i
++) {
1662 if (!((wr_mask
>> i
) & 1))
1665 fs_inst
*new_inst
= new(mem_ctx
) fs_inst(inst
);
1666 new_inst
->dst
= offset(new_inst
->dst
, bld
, i
);
1667 for (unsigned j
= 0; j
< new_inst
->sources
; j
++)
1668 if (new_inst
->src
[j
].file
== VGRF
)
1669 new_inst
->src
[j
] = offset(new_inst
->src
[j
], bld
, i
);
1676 * Get the matching channel register datatype for an image intrinsic of the
1677 * specified GLSL image type.
1680 get_image_base_type(const glsl_type
*type
)
1682 switch ((glsl_base_type
)type
->sampled_type
) {
1683 case GLSL_TYPE_UINT
:
1684 return BRW_REGISTER_TYPE_UD
;
1686 return BRW_REGISTER_TYPE_D
;
1687 case GLSL_TYPE_FLOAT
:
1688 return BRW_REGISTER_TYPE_F
;
1690 unreachable("Not reached.");
1695 * Get the appropriate atomic op for an image atomic intrinsic.
1698 get_image_atomic_op(nir_intrinsic_op op
, const glsl_type
*type
)
1701 case nir_intrinsic_image_var_atomic_add
:
1703 case nir_intrinsic_image_var_atomic_min
:
1704 return (get_image_base_type(type
) == BRW_REGISTER_TYPE_D
?
1705 BRW_AOP_IMIN
: BRW_AOP_UMIN
);
1706 case nir_intrinsic_image_var_atomic_max
:
1707 return (get_image_base_type(type
) == BRW_REGISTER_TYPE_D
?
1708 BRW_AOP_IMAX
: BRW_AOP_UMAX
);
1709 case nir_intrinsic_image_var_atomic_and
:
1711 case nir_intrinsic_image_var_atomic_or
:
1713 case nir_intrinsic_image_var_atomic_xor
:
1715 case nir_intrinsic_image_var_atomic_exchange
:
1717 case nir_intrinsic_image_var_atomic_comp_swap
:
1718 return BRW_AOP_CMPWR
;
1720 unreachable("Not reachable.");
1725 emit_pixel_interpolater_send(const fs_builder
&bld
,
1730 glsl_interp_mode interpolation
)
1732 struct brw_wm_prog_data
*wm_prog_data
=
1733 brw_wm_prog_data(bld
.shader
->stage_prog_data
);
1738 if (src
.file
== BAD_FILE
) {
1740 payload
= bld
.vgrf(BRW_REGISTER_TYPE_F
, 1);
1744 mlen
= 2 * bld
.dispatch_width() / 8;
1747 inst
= bld
.emit(opcode
, dst
, payload
, desc
);
1749 /* 2 floats per slot returned */
1750 inst
->size_written
= 2 * dst
.component_size(inst
->exec_size
);
1751 inst
->pi_noperspective
= interpolation
== INTERP_MODE_NOPERSPECTIVE
;
1753 wm_prog_data
->pulls_bary
= true;
1759 * Computes 1 << x, given a D/UD register containing some value x.
1762 intexp2(const fs_builder
&bld
, const fs_reg
&x
)
1764 assert(x
.type
== BRW_REGISTER_TYPE_UD
|| x
.type
== BRW_REGISTER_TYPE_D
);
1766 fs_reg result
= bld
.vgrf(x
.type
, 1);
1767 fs_reg one
= bld
.vgrf(x
.type
, 1);
1769 bld
.MOV(one
, retype(brw_imm_d(1), one
.type
));
1770 bld
.SHL(result
, one
, x
);
1775 fs_visitor::emit_gs_end_primitive(const nir_src
&vertex_count_nir_src
)
1777 assert(stage
== MESA_SHADER_GEOMETRY
);
1779 struct brw_gs_prog_data
*gs_prog_data
= brw_gs_prog_data(prog_data
);
1781 if (gs_compile
->control_data_header_size_bits
== 0)
1784 /* We can only do EndPrimitive() functionality when the control data
1785 * consists of cut bits. Fortunately, the only time it isn't is when the
1786 * output type is points, in which case EndPrimitive() is a no-op.
1788 if (gs_prog_data
->control_data_format
!=
1789 GEN7_GS_CONTROL_DATA_FORMAT_GSCTL_CUT
) {
1793 /* Cut bits use one bit per vertex. */
1794 assert(gs_compile
->control_data_bits_per_vertex
== 1);
1796 fs_reg vertex_count
= get_nir_src(vertex_count_nir_src
);
1797 vertex_count
.type
= BRW_REGISTER_TYPE_UD
;
1799 /* Cut bit n should be set to 1 if EndPrimitive() was called after emitting
1800 * vertex n, 0 otherwise. So all we need to do here is mark bit
1801 * (vertex_count - 1) % 32 in the cut_bits register to indicate that
1802 * EndPrimitive() was called after emitting vertex (vertex_count - 1);
1803 * vec4_gs_visitor::emit_control_data_bits() will take care of the rest.
1805 * Note that if EndPrimitive() is called before emitting any vertices, this
1806 * will cause us to set bit 31 of the control_data_bits register to 1.
1807 * That's fine because:
1809 * - If max_vertices < 32, then vertex number 31 (zero-based) will never be
1810 * output, so the hardware will ignore cut bit 31.
1812 * - If max_vertices == 32, then vertex number 31 is guaranteed to be the
1813 * last vertex, so setting cut bit 31 has no effect (since the primitive
1814 * is automatically ended when the GS terminates).
1816 * - If max_vertices > 32, then the ir_emit_vertex visitor will reset the
1817 * control_data_bits register to 0 when the first vertex is emitted.
1820 const fs_builder abld
= bld
.annotate("end primitive");
1822 /* control_data_bits |= 1 << ((vertex_count - 1) % 32) */
1823 fs_reg prev_count
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
1824 abld
.ADD(prev_count
, vertex_count
, brw_imm_ud(0xffffffffu
));
1825 fs_reg mask
= intexp2(abld
, prev_count
);
1826 /* Note: we're relying on the fact that the GEN SHL instruction only pays
1827 * attention to the lower 5 bits of its second source argument, so on this
1828 * architecture, 1 << (vertex_count - 1) is equivalent to 1 <<
1829 * ((vertex_count - 1) % 32).
1831 abld
.OR(this->control_data_bits
, this->control_data_bits
, mask
);
1835 fs_visitor::emit_gs_control_data_bits(const fs_reg
&vertex_count
)
1837 assert(stage
== MESA_SHADER_GEOMETRY
);
1838 assert(gs_compile
->control_data_bits_per_vertex
!= 0);
1840 struct brw_gs_prog_data
*gs_prog_data
= brw_gs_prog_data(prog_data
);
1842 const fs_builder abld
= bld
.annotate("emit control data bits");
1843 const fs_builder fwa_bld
= bld
.exec_all();
1845 /* We use a single UD register to accumulate control data bits (32 bits
1846 * for each of the SIMD8 channels). So we need to write a DWord (32 bits)
1849 * Unfortunately, the URB_WRITE_SIMD8 message uses 128-bit (OWord) offsets.
1850 * We have select a 128-bit group via the Global and Per-Slot Offsets, then
1851 * use the Channel Mask phase to enable/disable which DWord within that
1852 * group to write. (Remember, different SIMD8 channels may have emitted
1853 * different numbers of vertices, so we may need per-slot offsets.)
1855 * Channel masking presents an annoying problem: we may have to replicate
1856 * the data up to 4 times:
1858 * Msg = Handles, Per-Slot Offsets, Channel Masks, Data, Data, Data, Data.
1860 * To avoid penalizing shaders that emit a small number of vertices, we
1861 * can avoid these sometimes: if the size of the control data header is
1862 * <= 128 bits, then there is only 1 OWord. All SIMD8 channels will land
1863 * land in the same 128-bit group, so we can skip per-slot offsets.
1865 * Similarly, if the control data header is <= 32 bits, there is only one
1866 * DWord, so we can skip channel masks.
1868 enum opcode opcode
= SHADER_OPCODE_URB_WRITE_SIMD8
;
1870 fs_reg channel_mask
, per_slot_offset
;
1872 if (gs_compile
->control_data_header_size_bits
> 32) {
1873 opcode
= SHADER_OPCODE_URB_WRITE_SIMD8_MASKED
;
1874 channel_mask
= vgrf(glsl_type::uint_type
);
1877 if (gs_compile
->control_data_header_size_bits
> 128) {
1878 opcode
= SHADER_OPCODE_URB_WRITE_SIMD8_MASKED_PER_SLOT
;
1879 per_slot_offset
= vgrf(glsl_type::uint_type
);
1882 /* Figure out which DWord we're trying to write to using the formula:
1884 * dword_index = (vertex_count - 1) * bits_per_vertex / 32
1886 * Since bits_per_vertex is a power of two, and is known at compile
1887 * time, this can be optimized to:
1889 * dword_index = (vertex_count - 1) >> (6 - log2(bits_per_vertex))
1891 if (opcode
!= SHADER_OPCODE_URB_WRITE_SIMD8
) {
1892 fs_reg dword_index
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
1893 fs_reg prev_count
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
1894 abld
.ADD(prev_count
, vertex_count
, brw_imm_ud(0xffffffffu
));
1895 unsigned log2_bits_per_vertex
=
1896 util_last_bit(gs_compile
->control_data_bits_per_vertex
);
1897 abld
.SHR(dword_index
, prev_count
, brw_imm_ud(6u - log2_bits_per_vertex
));
1899 if (per_slot_offset
.file
!= BAD_FILE
) {
1900 /* Set the per-slot offset to dword_index / 4, so that we'll write to
1901 * the appropriate OWord within the control data header.
1903 abld
.SHR(per_slot_offset
, dword_index
, brw_imm_ud(2u));
1906 /* Set the channel masks to 1 << (dword_index % 4), so that we'll
1907 * write to the appropriate DWORD within the OWORD.
1909 fs_reg channel
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
1910 fwa_bld
.AND(channel
, dword_index
, brw_imm_ud(3u));
1911 channel_mask
= intexp2(fwa_bld
, channel
);
1912 /* Then the channel masks need to be in bits 23:16. */
1913 fwa_bld
.SHL(channel_mask
, channel_mask
, brw_imm_ud(16u));
1916 /* Store the control data bits in the message payload and send it. */
1918 if (channel_mask
.file
!= BAD_FILE
)
1919 mlen
+= 4; /* channel masks, plus 3 extra copies of the data */
1920 if (per_slot_offset
.file
!= BAD_FILE
)
1923 fs_reg payload
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, mlen
);
1924 fs_reg
*sources
= ralloc_array(mem_ctx
, fs_reg
, mlen
);
1926 sources
[i
++] = fs_reg(retype(brw_vec8_grf(1, 0), BRW_REGISTER_TYPE_UD
));
1927 if (per_slot_offset
.file
!= BAD_FILE
)
1928 sources
[i
++] = per_slot_offset
;
1929 if (channel_mask
.file
!= BAD_FILE
)
1930 sources
[i
++] = channel_mask
;
1932 sources
[i
++] = this->control_data_bits
;
1935 abld
.LOAD_PAYLOAD(payload
, sources
, mlen
, mlen
);
1936 fs_inst
*inst
= abld
.emit(opcode
, reg_undef
, payload
);
1938 /* We need to increment Global Offset by 256-bits to make room for
1939 * Broadwell's extra "Vertex Count" payload at the beginning of the
1940 * URB entry. Since this is an OWord message, Global Offset is counted
1941 * in 128-bit units, so we must set it to 2.
1943 if (gs_prog_data
->static_vertex_count
== -1)
1948 fs_visitor::set_gs_stream_control_data_bits(const fs_reg
&vertex_count
,
1951 /* control_data_bits |= stream_id << ((2 * (vertex_count - 1)) % 32) */
1953 /* Note: we are calling this *before* increasing vertex_count, so
1954 * this->vertex_count == vertex_count - 1 in the formula above.
1957 /* Stream mode uses 2 bits per vertex */
1958 assert(gs_compile
->control_data_bits_per_vertex
== 2);
1960 /* Must be a valid stream */
1961 assert(stream_id
< MAX_VERTEX_STREAMS
);
1963 /* Control data bits are initialized to 0 so we don't have to set any
1964 * bits when sending vertices to stream 0.
1969 const fs_builder abld
= bld
.annotate("set stream control data bits", NULL
);
1971 /* reg::sid = stream_id */
1972 fs_reg sid
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
1973 abld
.MOV(sid
, brw_imm_ud(stream_id
));
1975 /* reg:shift_count = 2 * (vertex_count - 1) */
1976 fs_reg shift_count
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
1977 abld
.SHL(shift_count
, vertex_count
, brw_imm_ud(1u));
1979 /* Note: we're relying on the fact that the GEN SHL instruction only pays
1980 * attention to the lower 5 bits of its second source argument, so on this
1981 * architecture, stream_id << 2 * (vertex_count - 1) is equivalent to
1982 * stream_id << ((2 * (vertex_count - 1)) % 32).
1984 fs_reg mask
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
1985 abld
.SHL(mask
, sid
, shift_count
);
1986 abld
.OR(this->control_data_bits
, this->control_data_bits
, mask
);
1990 fs_visitor::emit_gs_vertex(const nir_src
&vertex_count_nir_src
,
1993 assert(stage
== MESA_SHADER_GEOMETRY
);
1995 struct brw_gs_prog_data
*gs_prog_data
= brw_gs_prog_data(prog_data
);
1997 fs_reg vertex_count
= get_nir_src(vertex_count_nir_src
);
1998 vertex_count
.type
= BRW_REGISTER_TYPE_UD
;
2000 /* Haswell and later hardware ignores the "Render Stream Select" bits
2001 * from the 3DSTATE_STREAMOUT packet when the SOL stage is disabled,
2002 * and instead sends all primitives down the pipeline for rasterization.
2003 * If the SOL stage is enabled, "Render Stream Select" is honored and
2004 * primitives bound to non-zero streams are discarded after stream output.
2006 * Since the only purpose of primives sent to non-zero streams is to
2007 * be recorded by transform feedback, we can simply discard all geometry
2008 * bound to these streams when transform feedback is disabled.
2010 if (stream_id
> 0 && !nir
->info
.has_transform_feedback_varyings
)
2013 /* If we're outputting 32 control data bits or less, then we can wait
2014 * until the shader is over to output them all. Otherwise we need to
2015 * output them as we go. Now is the time to do it, since we're about to
2016 * output the vertex_count'th vertex, so it's guaranteed that the
2017 * control data bits associated with the (vertex_count - 1)th vertex are
2020 if (gs_compile
->control_data_header_size_bits
> 32) {
2021 const fs_builder abld
=
2022 bld
.annotate("emit vertex: emit control data bits");
2024 /* Only emit control data bits if we've finished accumulating a batch
2025 * of 32 bits. This is the case when:
2027 * (vertex_count * bits_per_vertex) % 32 == 0
2029 * (in other words, when the last 5 bits of vertex_count *
2030 * bits_per_vertex are 0). Assuming bits_per_vertex == 2^n for some
2031 * integer n (which is always the case, since bits_per_vertex is
2032 * always 1 or 2), this is equivalent to requiring that the last 5-n
2033 * bits of vertex_count are 0:
2035 * vertex_count & (2^(5-n) - 1) == 0
2037 * 2^(5-n) == 2^5 / 2^n == 32 / bits_per_vertex, so this is
2040 * vertex_count & (32 / bits_per_vertex - 1) == 0
2042 * TODO: If vertex_count is an immediate, we could do some of this math
2043 * at compile time...
2046 abld
.AND(bld
.null_reg_d(), vertex_count
,
2047 brw_imm_ud(32u / gs_compile
->control_data_bits_per_vertex
- 1u));
2048 inst
->conditional_mod
= BRW_CONDITIONAL_Z
;
2050 abld
.IF(BRW_PREDICATE_NORMAL
);
2051 /* If vertex_count is 0, then no control data bits have been
2052 * accumulated yet, so we can skip emitting them.
2054 abld
.CMP(bld
.null_reg_d(), vertex_count
, brw_imm_ud(0u),
2055 BRW_CONDITIONAL_NEQ
);
2056 abld
.IF(BRW_PREDICATE_NORMAL
);
2057 emit_gs_control_data_bits(vertex_count
);
2058 abld
.emit(BRW_OPCODE_ENDIF
);
2060 /* Reset control_data_bits to 0 so we can start accumulating a new
2063 * Note: in the case where vertex_count == 0, this neutralizes the
2064 * effect of any call to EndPrimitive() that the shader may have
2065 * made before outputting its first vertex.
2067 inst
= abld
.MOV(this->control_data_bits
, brw_imm_ud(0u));
2068 inst
->force_writemask_all
= true;
2069 abld
.emit(BRW_OPCODE_ENDIF
);
2072 emit_urb_writes(vertex_count
);
2074 /* In stream mode we have to set control data bits for all vertices
2075 * unless we have disabled control data bits completely (which we do
2076 * do for GL_POINTS outputs that don't use streams).
2078 if (gs_compile
->control_data_header_size_bits
> 0 &&
2079 gs_prog_data
->control_data_format
==
2080 GEN7_GS_CONTROL_DATA_FORMAT_GSCTL_SID
) {
2081 set_gs_stream_control_data_bits(vertex_count
, stream_id
);
2086 fs_visitor::emit_gs_input_load(const fs_reg
&dst
,
2087 const nir_src
&vertex_src
,
2088 unsigned base_offset
,
2089 const nir_src
&offset_src
,
2090 unsigned num_components
,
2091 unsigned first_component
)
2093 struct brw_gs_prog_data
*gs_prog_data
= brw_gs_prog_data(prog_data
);
2095 nir_const_value
*vertex_const
= nir_src_as_const_value(vertex_src
);
2096 nir_const_value
*offset_const
= nir_src_as_const_value(offset_src
);
2097 const unsigned push_reg_count
= gs_prog_data
->base
.urb_read_length
* 8;
2099 /* TODO: figure out push input layout for invocations == 1 */
2100 /* TODO: make this work with 64-bit inputs */
2101 if (gs_prog_data
->invocations
== 1 &&
2102 type_sz(dst
.type
) <= 4 &&
2103 offset_const
!= NULL
&& vertex_const
!= NULL
&&
2104 4 * (base_offset
+ offset_const
->u32
[0]) < push_reg_count
) {
2105 int imm_offset
= (base_offset
+ offset_const
->u32
[0]) * 4 +
2106 vertex_const
->u32
[0] * push_reg_count
;
2107 for (unsigned i
= 0; i
< num_components
; i
++) {
2108 bld
.MOV(offset(dst
, bld
, i
),
2109 fs_reg(ATTR
, imm_offset
+ i
+ first_component
, dst
.type
));
2114 /* Resort to the pull model. Ensure the VUE handles are provided. */
2115 assert(gs_prog_data
->base
.include_vue_handles
);
2117 unsigned first_icp_handle
= gs_prog_data
->include_primitive_id
? 3 : 2;
2118 fs_reg icp_handle
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2120 if (gs_prog_data
->invocations
== 1) {
2122 /* The vertex index is constant; just select the proper URB handle. */
2124 retype(brw_vec8_grf(first_icp_handle
+ vertex_const
->i32
[0], 0),
2125 BRW_REGISTER_TYPE_UD
);
2127 /* The vertex index is non-constant. We need to use indirect
2128 * addressing to fetch the proper URB handle.
2130 * First, we start with the sequence <7, 6, 5, 4, 3, 2, 1, 0>
2131 * indicating that channel <n> should read the handle from
2132 * DWord <n>. We convert that to bytes by multiplying by 4.
2134 * Next, we convert the vertex index to bytes by multiplying
2135 * by 32 (shifting by 5), and add the two together. This is
2136 * the final indirect byte offset.
2138 fs_reg sequence
= bld
.vgrf(BRW_REGISTER_TYPE_UW
, 1);
2139 fs_reg channel_offsets
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2140 fs_reg vertex_offset_bytes
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2141 fs_reg icp_offset_bytes
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2143 /* sequence = <7, 6, 5, 4, 3, 2, 1, 0> */
2144 bld
.MOV(sequence
, fs_reg(brw_imm_v(0x76543210)));
2145 /* channel_offsets = 4 * sequence = <28, 24, 20, 16, 12, 8, 4, 0> */
2146 bld
.SHL(channel_offsets
, sequence
, brw_imm_ud(2u));
2147 /* Convert vertex_index to bytes (multiply by 32) */
2148 bld
.SHL(vertex_offset_bytes
,
2149 retype(get_nir_src(vertex_src
), BRW_REGISTER_TYPE_UD
),
2151 bld
.ADD(icp_offset_bytes
, vertex_offset_bytes
, channel_offsets
);
2153 /* Use first_icp_handle as the base offset. There is one register
2154 * of URB handles per vertex, so inform the register allocator that
2155 * we might read up to nir->info.gs.vertices_in registers.
2157 bld
.emit(SHADER_OPCODE_MOV_INDIRECT
, icp_handle
,
2158 retype(brw_vec8_grf(first_icp_handle
, 0), icp_handle
.type
),
2159 fs_reg(icp_offset_bytes
),
2160 brw_imm_ud(nir
->info
.gs
.vertices_in
* REG_SIZE
));
2163 assert(gs_prog_data
->invocations
> 1);
2166 assert(devinfo
->gen
>= 9 || vertex_const
->i32
[0] <= 5);
2168 retype(brw_vec1_grf(first_icp_handle
+
2169 vertex_const
->i32
[0] / 8,
2170 vertex_const
->i32
[0] % 8),
2171 BRW_REGISTER_TYPE_UD
));
2173 /* The vertex index is non-constant. We need to use indirect
2174 * addressing to fetch the proper URB handle.
2177 fs_reg icp_offset_bytes
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2179 /* Convert vertex_index to bytes (multiply by 4) */
2180 bld
.SHL(icp_offset_bytes
,
2181 retype(get_nir_src(vertex_src
), BRW_REGISTER_TYPE_UD
),
2184 /* Use first_icp_handle as the base offset. There is one DWord
2185 * of URB handles per vertex, so inform the register allocator that
2186 * we might read up to ceil(nir->info.gs.vertices_in / 8) registers.
2188 bld
.emit(SHADER_OPCODE_MOV_INDIRECT
, icp_handle
,
2189 retype(brw_vec8_grf(first_icp_handle
, 0), icp_handle
.type
),
2190 fs_reg(icp_offset_bytes
),
2191 brw_imm_ud(DIV_ROUND_UP(nir
->info
.gs
.vertices_in
, 8) *
2198 fs_reg tmp_dst
= dst
;
2199 fs_reg indirect_offset
= get_nir_src(offset_src
);
2200 unsigned num_iterations
= 1;
2201 unsigned orig_num_components
= num_components
;
2203 if (type_sz(dst
.type
) == 8) {
2204 if (num_components
> 2) {
2208 fs_reg tmp
= fs_reg(VGRF
, alloc
.allocate(4), dst
.type
);
2210 first_component
= first_component
/ 2;
2213 for (unsigned iter
= 0; iter
< num_iterations
; iter
++) {
2215 /* Constant indexing - use global offset. */
2216 if (first_component
!= 0) {
2217 unsigned read_components
= num_components
+ first_component
;
2218 fs_reg tmp
= bld
.vgrf(dst
.type
, read_components
);
2219 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8
, tmp
, icp_handle
);
2220 inst
->size_written
= read_components
*
2221 tmp
.component_size(inst
->exec_size
);
2222 for (unsigned i
= 0; i
< num_components
; i
++) {
2223 bld
.MOV(offset(tmp_dst
, bld
, i
),
2224 offset(tmp
, bld
, i
+ first_component
));
2227 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8
, tmp_dst
,
2229 inst
->size_written
= num_components
*
2230 tmp_dst
.component_size(inst
->exec_size
);
2232 inst
->offset
= base_offset
+ offset_const
->u32
[0];
2235 /* Indirect indexing - use per-slot offsets as well. */
2236 const fs_reg srcs
[] = { icp_handle
, indirect_offset
};
2237 unsigned read_components
= num_components
+ first_component
;
2238 fs_reg tmp
= bld
.vgrf(dst
.type
, read_components
);
2239 fs_reg payload
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 2);
2240 bld
.LOAD_PAYLOAD(payload
, srcs
, ARRAY_SIZE(srcs
), 0);
2241 if (first_component
!= 0) {
2242 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT
, tmp
,
2244 inst
->size_written
= read_components
*
2245 tmp
.component_size(inst
->exec_size
);
2246 for (unsigned i
= 0; i
< num_components
; i
++) {
2247 bld
.MOV(offset(tmp_dst
, bld
, i
),
2248 offset(tmp
, bld
, i
+ first_component
));
2251 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT
, tmp_dst
,
2253 inst
->size_written
= num_components
*
2254 tmp_dst
.component_size(inst
->exec_size
);
2256 inst
->offset
= base_offset
;
2260 if (type_sz(dst
.type
) == 8) {
2261 shuffle_32bit_load_result_to_64bit_data(
2262 bld
, tmp_dst
, retype(tmp_dst
, BRW_REGISTER_TYPE_F
), num_components
);
2264 for (unsigned c
= 0; c
< num_components
; c
++)
2265 bld
.MOV(offset(dst
, bld
, iter
* 2 + c
), offset(tmp_dst
, bld
, c
));
2268 if (num_iterations
> 1) {
2269 num_components
= orig_num_components
- 2;
2273 fs_reg new_indirect
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2274 bld
.ADD(new_indirect
, indirect_offset
, brw_imm_ud(1u));
2275 indirect_offset
= new_indirect
;
2282 fs_visitor::get_indirect_offset(nir_intrinsic_instr
*instr
)
2284 nir_src
*offset_src
= nir_get_io_offset_src(instr
);
2285 nir_const_value
*const_value
= nir_src_as_const_value(*offset_src
);
2288 /* The only constant offset we should find is 0. brw_nir.c's
2289 * add_const_offset_to_base() will fold other constant offsets
2290 * into instr->const_index[0].
2292 assert(const_value
->u32
[0] == 0);
2296 return get_nir_src(*offset_src
);
2300 do_untyped_vector_read(const fs_builder
&bld
,
2302 const fs_reg surf_index
,
2303 const fs_reg offset_reg
,
2304 unsigned num_components
)
2306 if (type_sz(dest
.type
) <= 2) {
2307 assert(dest
.stride
== 1);
2308 boolean is_const_offset
= offset_reg
.file
== BRW_IMMEDIATE_VALUE
;
2310 if (is_const_offset
) {
2311 uint32_t start
= offset_reg
.ud
& ~3;
2312 uint32_t end
= offset_reg
.ud
+ num_components
* type_sz(dest
.type
);
2313 end
= ALIGN(end
, 4);
2314 assert (end
- start
<= 16);
2316 /* At this point we have 16-bit component/s that have constant
2317 * offset aligned to 4-bytes that can be read with untyped_reads.
2318 * untyped_read message requires 32-bit aligned offsets.
2320 unsigned first_component
= (offset_reg
.ud
& 3) / type_sz(dest
.type
);
2321 unsigned num_components_32bit
= (end
- start
) / 4;
2323 fs_reg read_result
=
2324 emit_untyped_read(bld
, surf_index
, brw_imm_ud(start
),
2326 num_components_32bit
,
2327 BRW_PREDICATE_NONE
);
2328 shuffle_32bit_load_result_to_16bit_data(bld
,
2329 retype(dest
, BRW_REGISTER_TYPE_W
),
2330 retype(read_result
, BRW_REGISTER_TYPE_D
),
2331 first_component
, num_components
);
2333 fs_reg read_offset
= bld
.vgrf(BRW_REGISTER_TYPE_UD
);
2334 for (unsigned i
= 0; i
< num_components
; i
++) {
2336 bld
.MOV(read_offset
, offset_reg
);
2338 bld
.ADD(read_offset
, offset_reg
,
2339 brw_imm_ud(i
* type_sz(dest
.type
)));
2341 /* Non constant offsets are not guaranteed to be aligned 32-bits
2342 * so they are read using one byte_scattered_read message
2343 * for each component.
2345 fs_reg read_result
=
2346 emit_byte_scattered_read(bld
, surf_index
, read_offset
,
2348 type_sz(dest
.type
) * 8 /* bit_size */,
2349 BRW_PREDICATE_NONE
);
2350 bld
.MOV(offset(dest
, bld
, i
),
2351 subscript (read_result
, dest
.type
, 0));
2354 } else if (type_sz(dest
.type
) == 4) {
2355 fs_reg read_result
= emit_untyped_read(bld
, surf_index
, offset_reg
,
2358 BRW_PREDICATE_NONE
);
2359 read_result
.type
= dest
.type
;
2360 for (unsigned i
= 0; i
< num_components
; i
++)
2361 bld
.MOV(offset(dest
, bld
, i
), offset(read_result
, bld
, i
));
2362 } else if (type_sz(dest
.type
) == 8) {
2363 /* Reading a dvec, so we need to:
2365 * 1. Multiply num_components by 2, to account for the fact that we
2366 * need to read 64-bit components.
2367 * 2. Shuffle the result of the load to form valid 64-bit elements
2368 * 3. Emit a second load (for components z/w) if needed.
2370 fs_reg read_offset
= bld
.vgrf(BRW_REGISTER_TYPE_UD
);
2371 bld
.MOV(read_offset
, offset_reg
);
2373 int iters
= num_components
<= 2 ? 1 : 2;
2375 /* Load the dvec, the first iteration loads components x/y, the second
2376 * iteration, if needed, loads components z/w
2378 for (int it
= 0; it
< iters
; it
++) {
2379 /* Compute number of components to read in this iteration */
2380 int iter_components
= MIN2(2, num_components
);
2381 num_components
-= iter_components
;
2383 /* Read. Since this message reads 32-bit components, we need to
2384 * read twice as many components.
2386 fs_reg read_result
= emit_untyped_read(bld
, surf_index
, read_offset
,
2388 iter_components
* 2,
2389 BRW_PREDICATE_NONE
);
2391 /* Shuffle the 32-bit load result into valid 64-bit data */
2392 const fs_reg packed_result
= bld
.vgrf(dest
.type
, iter_components
);
2393 shuffle_32bit_load_result_to_64bit_data(
2394 bld
, packed_result
, read_result
, iter_components
);
2396 /* Move each component to its destination */
2397 read_result
= retype(read_result
, BRW_REGISTER_TYPE_DF
);
2398 for (int c
= 0; c
< iter_components
; c
++) {
2399 bld
.MOV(offset(dest
, bld
, it
* 2 + c
),
2400 offset(packed_result
, bld
, c
));
2403 bld
.ADD(read_offset
, read_offset
, brw_imm_ud(16));
2406 unreachable("Unsupported type");
2411 fs_visitor::nir_emit_vs_intrinsic(const fs_builder
&bld
,
2412 nir_intrinsic_instr
*instr
)
2414 assert(stage
== MESA_SHADER_VERTEX
);
2417 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
2418 dest
= get_nir_dest(instr
->dest
);
2420 switch (instr
->intrinsic
) {
2421 case nir_intrinsic_load_vertex_id
:
2422 case nir_intrinsic_load_base_vertex
:
2423 unreachable("should be lowered by nir_lower_system_values()");
2425 case nir_intrinsic_load_vertex_id_zero_base
:
2426 case nir_intrinsic_load_instance_id
:
2427 case nir_intrinsic_load_base_instance
:
2428 case nir_intrinsic_load_draw_id
: {
2429 gl_system_value sv
= nir_system_value_from_intrinsic(instr
->intrinsic
);
2430 fs_reg val
= nir_system_values
[sv
];
2431 assert(val
.file
!= BAD_FILE
);
2432 dest
.type
= val
.type
;
2437 case nir_intrinsic_load_input
: {
2438 fs_reg src
= fs_reg(ATTR
, nir_intrinsic_base(instr
) * 4, dest
.type
);
2439 unsigned first_component
= nir_intrinsic_component(instr
);
2440 unsigned num_components
= instr
->num_components
;
2442 nir_const_value
*const_offset
= nir_src_as_const_value(instr
->src
[0]);
2443 assert(const_offset
&& "Indirect input loads not allowed");
2444 src
= offset(src
, bld
, const_offset
->u32
[0]);
2446 if (type_sz(dest
.type
) == 8)
2447 first_component
/= 2;
2449 for (unsigned j
= 0; j
< num_components
; j
++) {
2450 bld
.MOV(offset(dest
, bld
, j
), offset(src
, bld
, j
+ first_component
));
2453 if (type_sz(dest
.type
) == 8) {
2454 shuffle_32bit_load_result_to_64bit_data(bld
,
2456 retype(dest
, BRW_REGISTER_TYPE_F
),
2457 instr
->num_components
);
2462 case nir_intrinsic_load_first_vertex
:
2463 case nir_intrinsic_load_is_indexed_draw
:
2464 unreachable("lowered by brw_nir_lower_vs_inputs");
2467 nir_emit_intrinsic(bld
, instr
);
2473 fs_visitor::nir_emit_tcs_intrinsic(const fs_builder
&bld
,
2474 nir_intrinsic_instr
*instr
)
2476 assert(stage
== MESA_SHADER_TESS_CTRL
);
2477 struct brw_tcs_prog_key
*tcs_key
= (struct brw_tcs_prog_key
*) key
;
2478 struct brw_tcs_prog_data
*tcs_prog_data
= brw_tcs_prog_data(prog_data
);
2481 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
2482 dst
= get_nir_dest(instr
->dest
);
2484 switch (instr
->intrinsic
) {
2485 case nir_intrinsic_load_primitive_id
:
2486 bld
.MOV(dst
, fs_reg(brw_vec1_grf(0, 1)));
2488 case nir_intrinsic_load_invocation_id
:
2489 bld
.MOV(retype(dst
, invocation_id
.type
), invocation_id
);
2491 case nir_intrinsic_load_patch_vertices_in
:
2492 bld
.MOV(retype(dst
, BRW_REGISTER_TYPE_D
),
2493 brw_imm_d(tcs_key
->input_vertices
));
2496 case nir_intrinsic_barrier
: {
2497 if (tcs_prog_data
->instances
== 1)
2500 fs_reg m0
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2501 fs_reg m0_2
= component(m0
, 2);
2503 const fs_builder chanbld
= bld
.exec_all().group(1, 0);
2505 /* Zero the message header */
2506 bld
.exec_all().MOV(m0
, brw_imm_ud(0u));
2508 /* Copy "Barrier ID" from r0.2, bits 16:13 */
2509 chanbld
.AND(m0_2
, retype(brw_vec1_grf(0, 2), BRW_REGISTER_TYPE_UD
),
2510 brw_imm_ud(INTEL_MASK(16, 13)));
2512 /* Shift it up to bits 27:24. */
2513 chanbld
.SHL(m0_2
, m0_2
, brw_imm_ud(11));
2515 /* Set the Barrier Count and the enable bit */
2516 chanbld
.OR(m0_2
, m0_2
,
2517 brw_imm_ud(tcs_prog_data
->instances
<< 9 | (1 << 15)));
2519 bld
.emit(SHADER_OPCODE_BARRIER
, bld
.null_reg_ud(), m0
);
2523 case nir_intrinsic_load_input
:
2524 unreachable("nir_lower_io should never give us these.");
2527 case nir_intrinsic_load_per_vertex_input
: {
2528 fs_reg indirect_offset
= get_indirect_offset(instr
);
2529 unsigned imm_offset
= instr
->const_index
[0];
2531 const nir_src
&vertex_src
= instr
->src
[0];
2532 nir_const_value
*vertex_const
= nir_src_as_const_value(vertex_src
);
2539 /* Emit a MOV to resolve <0,1,0> regioning. */
2540 icp_handle
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2542 retype(brw_vec1_grf(1 + (vertex_const
->i32
[0] >> 3),
2543 vertex_const
->i32
[0] & 7),
2544 BRW_REGISTER_TYPE_UD
));
2545 } else if (tcs_prog_data
->instances
== 1 &&
2546 vertex_src
.is_ssa
&&
2547 vertex_src
.ssa
->parent_instr
->type
== nir_instr_type_intrinsic
&&
2548 nir_instr_as_intrinsic(vertex_src
.ssa
->parent_instr
)->intrinsic
== nir_intrinsic_load_invocation_id
) {
2549 /* For the common case of only 1 instance, an array index of
2550 * gl_InvocationID means reading g1. Skip all the indirect work.
2552 icp_handle
= retype(brw_vec8_grf(1, 0), BRW_REGISTER_TYPE_UD
);
2554 /* The vertex index is non-constant. We need to use indirect
2555 * addressing to fetch the proper URB handle.
2557 icp_handle
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2559 /* Each ICP handle is a single DWord (4 bytes) */
2560 fs_reg vertex_offset_bytes
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2561 bld
.SHL(vertex_offset_bytes
,
2562 retype(get_nir_src(vertex_src
), BRW_REGISTER_TYPE_UD
),
2565 /* Start at g1. We might read up to 4 registers. */
2566 bld
.emit(SHADER_OPCODE_MOV_INDIRECT
, icp_handle
,
2567 retype(brw_vec8_grf(1, 0), icp_handle
.type
), vertex_offset_bytes
,
2568 brw_imm_ud(4 * REG_SIZE
));
2571 /* We can only read two double components with each URB read, so
2572 * we send two read messages in that case, each one loading up to
2573 * two double components.
2575 unsigned num_iterations
= 1;
2576 unsigned num_components
= instr
->num_components
;
2577 unsigned first_component
= nir_intrinsic_component(instr
);
2578 fs_reg orig_dst
= dst
;
2579 if (type_sz(dst
.type
) == 8) {
2580 first_component
= first_component
/ 2;
2581 if (instr
->num_components
> 2) {
2586 fs_reg tmp
= fs_reg(VGRF
, alloc
.allocate(4), dst
.type
);
2590 for (unsigned iter
= 0; iter
< num_iterations
; iter
++) {
2591 if (indirect_offset
.file
== BAD_FILE
) {
2592 /* Constant indexing - use global offset. */
2593 if (first_component
!= 0) {
2594 unsigned read_components
= num_components
+ first_component
;
2595 fs_reg tmp
= bld
.vgrf(dst
.type
, read_components
);
2596 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8
, tmp
, icp_handle
);
2597 for (unsigned i
= 0; i
< num_components
; i
++) {
2598 bld
.MOV(offset(dst
, bld
, i
),
2599 offset(tmp
, bld
, i
+ first_component
));
2602 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8
, dst
, icp_handle
);
2604 inst
->offset
= imm_offset
;
2607 /* Indirect indexing - use per-slot offsets as well. */
2608 const fs_reg srcs
[] = { icp_handle
, indirect_offset
};
2609 fs_reg payload
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 2);
2610 bld
.LOAD_PAYLOAD(payload
, srcs
, ARRAY_SIZE(srcs
), 0);
2611 if (first_component
!= 0) {
2612 unsigned read_components
= num_components
+ first_component
;
2613 fs_reg tmp
= bld
.vgrf(dst
.type
, read_components
);
2614 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT
, tmp
,
2616 for (unsigned i
= 0; i
< num_components
; i
++) {
2617 bld
.MOV(offset(dst
, bld
, i
),
2618 offset(tmp
, bld
, i
+ first_component
));
2621 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT
, dst
,
2624 inst
->offset
= imm_offset
;
2627 inst
->size_written
= (num_components
+ first_component
) *
2628 inst
->dst
.component_size(inst
->exec_size
);
2630 /* If we are reading 64-bit data using 32-bit read messages we need
2631 * build proper 64-bit data elements by shuffling the low and high
2632 * 32-bit components around like we do for other things like UBOs
2635 if (type_sz(dst
.type
) == 8) {
2636 shuffle_32bit_load_result_to_64bit_data(
2637 bld
, dst
, retype(dst
, BRW_REGISTER_TYPE_F
), num_components
);
2639 for (unsigned c
= 0; c
< num_components
; c
++) {
2640 bld
.MOV(offset(orig_dst
, bld
, iter
* 2 + c
),
2641 offset(dst
, bld
, c
));
2645 /* Copy the temporary to the destination to deal with writemasking.
2647 * Also attempt to deal with gl_PointSize being in the .w component.
2649 if (inst
->offset
== 0 && indirect_offset
.file
== BAD_FILE
) {
2650 assert(type_sz(dst
.type
) < 8);
2651 inst
->dst
= bld
.vgrf(dst
.type
, 4);
2652 inst
->size_written
= 4 * REG_SIZE
;
2653 bld
.MOV(dst
, offset(inst
->dst
, bld
, 3));
2656 /* If we are loading double data and we need a second read message
2657 * adjust the write offset
2659 if (num_iterations
> 1) {
2660 num_components
= instr
->num_components
- 2;
2667 case nir_intrinsic_load_output
:
2668 case nir_intrinsic_load_per_vertex_output
: {
2669 fs_reg indirect_offset
= get_indirect_offset(instr
);
2670 unsigned imm_offset
= instr
->const_index
[0];
2671 unsigned first_component
= nir_intrinsic_component(instr
);
2674 if (indirect_offset
.file
== BAD_FILE
) {
2675 /* Replicate the patch handle to all enabled channels */
2676 fs_reg patch_handle
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2677 bld
.MOV(patch_handle
,
2678 retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_UD
));
2681 if (first_component
!= 0) {
2682 unsigned read_components
=
2683 instr
->num_components
+ first_component
;
2684 fs_reg tmp
= bld
.vgrf(dst
.type
, read_components
);
2685 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8
, tmp
,
2687 inst
->size_written
= read_components
* REG_SIZE
;
2688 for (unsigned i
= 0; i
< instr
->num_components
; i
++) {
2689 bld
.MOV(offset(dst
, bld
, i
),
2690 offset(tmp
, bld
, i
+ first_component
));
2693 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8
, dst
,
2695 inst
->size_written
= instr
->num_components
* REG_SIZE
;
2697 inst
->offset
= imm_offset
;
2701 /* Indirect indexing - use per-slot offsets as well. */
2702 const fs_reg srcs
[] = {
2703 retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_UD
),
2706 fs_reg payload
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 2);
2707 bld
.LOAD_PAYLOAD(payload
, srcs
, ARRAY_SIZE(srcs
), 0);
2708 if (first_component
!= 0) {
2709 unsigned read_components
=
2710 instr
->num_components
+ first_component
;
2711 fs_reg tmp
= bld
.vgrf(dst
.type
, read_components
);
2712 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT
, tmp
,
2714 inst
->size_written
= read_components
* REG_SIZE
;
2715 for (unsigned i
= 0; i
< instr
->num_components
; i
++) {
2716 bld
.MOV(offset(dst
, bld
, i
),
2717 offset(tmp
, bld
, i
+ first_component
));
2720 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT
, dst
,
2722 inst
->size_written
= instr
->num_components
* REG_SIZE
;
2724 inst
->offset
= imm_offset
;
2730 case nir_intrinsic_store_output
:
2731 case nir_intrinsic_store_per_vertex_output
: {
2732 fs_reg value
= get_nir_src(instr
->src
[0]);
2733 bool is_64bit
= (instr
->src
[0].is_ssa
?
2734 instr
->src
[0].ssa
->bit_size
: instr
->src
[0].reg
.reg
->bit_size
) == 64;
2735 fs_reg indirect_offset
= get_indirect_offset(instr
);
2736 unsigned imm_offset
= instr
->const_index
[0];
2737 unsigned mask
= instr
->const_index
[1];
2738 unsigned header_regs
= 0;
2740 srcs
[header_regs
++] = retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_UD
);
2742 if (indirect_offset
.file
!= BAD_FILE
) {
2743 srcs
[header_regs
++] = indirect_offset
;
2749 unsigned num_components
= util_last_bit(mask
);
2752 /* We can only pack two 64-bit components in a single message, so send
2753 * 2 messages if we have more components
2755 unsigned num_iterations
= 1;
2756 unsigned iter_components
= num_components
;
2757 unsigned first_component
= nir_intrinsic_component(instr
);
2759 first_component
= first_component
/ 2;
2760 if (instr
->num_components
> 2) {
2762 iter_components
= 2;
2766 mask
= mask
<< first_component
;
2768 for (unsigned iter
= 0; iter
< num_iterations
; iter
++) {
2769 if (!is_64bit
&& mask
!= WRITEMASK_XYZW
) {
2770 srcs
[header_regs
++] = brw_imm_ud(mask
<< 16);
2771 opcode
= indirect_offset
.file
!= BAD_FILE
?
2772 SHADER_OPCODE_URB_WRITE_SIMD8_MASKED_PER_SLOT
:
2773 SHADER_OPCODE_URB_WRITE_SIMD8_MASKED
;
2774 } else if (is_64bit
&& ((mask
& WRITEMASK_XY
) != WRITEMASK_XY
)) {
2775 /* Expand the 64-bit mask to 32-bit channels. We only handle
2776 * two channels in each iteration, so we only care about X/Y.
2778 unsigned mask32
= 0;
2779 if (mask
& WRITEMASK_X
)
2780 mask32
|= WRITEMASK_XY
;
2781 if (mask
& WRITEMASK_Y
)
2782 mask32
|= WRITEMASK_ZW
;
2784 /* If the mask does not include any of the channels X or Y there
2785 * is nothing to do in this iteration. Move on to the next couple
2786 * of 64-bit channels.
2794 srcs
[header_regs
++] = brw_imm_ud(mask32
<< 16);
2795 opcode
= indirect_offset
.file
!= BAD_FILE
?
2796 SHADER_OPCODE_URB_WRITE_SIMD8_MASKED_PER_SLOT
:
2797 SHADER_OPCODE_URB_WRITE_SIMD8_MASKED
;
2799 opcode
= indirect_offset
.file
!= BAD_FILE
?
2800 SHADER_OPCODE_URB_WRITE_SIMD8_PER_SLOT
:
2801 SHADER_OPCODE_URB_WRITE_SIMD8
;
2804 for (unsigned i
= 0; i
< iter_components
; i
++) {
2805 if (!(mask
& (1 << (i
+ first_component
))))
2809 srcs
[header_regs
+ i
+ first_component
] = offset(value
, bld
, i
);
2811 /* We need to shuffle the 64-bit data to match the layout
2812 * expected by our 32-bit URB write messages. We use a temporary
2815 unsigned channel
= iter
* 2 + i
;
2816 fs_reg dest
= shuffle_64bit_data_for_32bit_write(bld
,
2817 offset(value
, bld
, channel
), 1);
2819 srcs
[header_regs
+ (i
+ first_component
) * 2] = dest
;
2820 srcs
[header_regs
+ (i
+ first_component
) * 2 + 1] =
2821 offset(dest
, bld
, 1);
2826 header_regs
+ (is_64bit
? 2 * iter_components
: iter_components
) +
2827 (is_64bit
? 2 * first_component
: first_component
);
2829 bld
.vgrf(BRW_REGISTER_TYPE_UD
, mlen
);
2830 bld
.LOAD_PAYLOAD(payload
, srcs
, mlen
, header_regs
);
2832 fs_inst
*inst
= bld
.emit(opcode
, bld
.null_reg_ud(), payload
);
2833 inst
->offset
= imm_offset
;
2836 /* If this is a 64-bit attribute, select the next two 64-bit channels
2837 * to be handled in the next iteration.
2848 nir_emit_intrinsic(bld
, instr
);
2854 fs_visitor::nir_emit_tes_intrinsic(const fs_builder
&bld
,
2855 nir_intrinsic_instr
*instr
)
2857 assert(stage
== MESA_SHADER_TESS_EVAL
);
2858 struct brw_tes_prog_data
*tes_prog_data
= brw_tes_prog_data(prog_data
);
2861 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
2862 dest
= get_nir_dest(instr
->dest
);
2864 switch (instr
->intrinsic
) {
2865 case nir_intrinsic_load_primitive_id
:
2866 bld
.MOV(dest
, fs_reg(brw_vec1_grf(0, 1)));
2868 case nir_intrinsic_load_tess_coord
:
2869 /* gl_TessCoord is part of the payload in g1-3 */
2870 for (unsigned i
= 0; i
< 3; i
++) {
2871 bld
.MOV(offset(dest
, bld
, i
), fs_reg(brw_vec8_grf(1 + i
, 0)));
2875 case nir_intrinsic_load_input
:
2876 case nir_intrinsic_load_per_vertex_input
: {
2877 fs_reg indirect_offset
= get_indirect_offset(instr
);
2878 unsigned imm_offset
= instr
->const_index
[0];
2879 unsigned first_component
= nir_intrinsic_component(instr
);
2881 if (type_sz(dest
.type
) == 8) {
2882 first_component
= first_component
/ 2;
2886 if (indirect_offset
.file
== BAD_FILE
) {
2887 /* Arbitrarily only push up to 32 vec4 slots worth of data,
2888 * which is 16 registers (since each holds 2 vec4 slots).
2890 unsigned slot_count
= 1;
2891 if (type_sz(dest
.type
) == 8 && instr
->num_components
> 2)
2894 const unsigned max_push_slots
= 32;
2895 if (imm_offset
+ slot_count
<= max_push_slots
) {
2896 fs_reg src
= fs_reg(ATTR
, imm_offset
/ 2, dest
.type
);
2897 for (int i
= 0; i
< instr
->num_components
; i
++) {
2898 unsigned comp
= 16 / type_sz(dest
.type
) * (imm_offset
% 2) +
2899 i
+ first_component
;
2900 bld
.MOV(offset(dest
, bld
, i
), component(src
, comp
));
2903 tes_prog_data
->base
.urb_read_length
=
2904 MAX2(tes_prog_data
->base
.urb_read_length
,
2905 DIV_ROUND_UP(imm_offset
+ slot_count
, 2));
2907 /* Replicate the patch handle to all enabled channels */
2908 const fs_reg srcs
[] = {
2909 retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_UD
)
2911 fs_reg patch_handle
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2912 bld
.LOAD_PAYLOAD(patch_handle
, srcs
, ARRAY_SIZE(srcs
), 0);
2914 if (first_component
!= 0) {
2915 unsigned read_components
=
2916 instr
->num_components
+ first_component
;
2917 fs_reg tmp
= bld
.vgrf(dest
.type
, read_components
);
2918 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8
, tmp
,
2920 inst
->size_written
= read_components
* REG_SIZE
;
2921 for (unsigned i
= 0; i
< instr
->num_components
; i
++) {
2922 bld
.MOV(offset(dest
, bld
, i
),
2923 offset(tmp
, bld
, i
+ first_component
));
2926 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8
, dest
,
2928 inst
->size_written
= instr
->num_components
* REG_SIZE
;
2931 inst
->offset
= imm_offset
;
2934 /* Indirect indexing - use per-slot offsets as well. */
2936 /* We can only read two double components with each URB read, so
2937 * we send two read messages in that case, each one loading up to
2938 * two double components.
2940 unsigned num_iterations
= 1;
2941 unsigned num_components
= instr
->num_components
;
2942 fs_reg orig_dest
= dest
;
2943 if (type_sz(dest
.type
) == 8) {
2944 if (instr
->num_components
> 2) {
2948 fs_reg tmp
= fs_reg(VGRF
, alloc
.allocate(4), dest
.type
);
2952 for (unsigned iter
= 0; iter
< num_iterations
; iter
++) {
2953 const fs_reg srcs
[] = {
2954 retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_UD
),
2957 fs_reg payload
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 2);
2958 bld
.LOAD_PAYLOAD(payload
, srcs
, ARRAY_SIZE(srcs
), 0);
2960 if (first_component
!= 0) {
2961 unsigned read_components
=
2962 num_components
+ first_component
;
2963 fs_reg tmp
= bld
.vgrf(dest
.type
, read_components
);
2964 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT
, tmp
,
2966 for (unsigned i
= 0; i
< num_components
; i
++) {
2967 bld
.MOV(offset(dest
, bld
, i
),
2968 offset(tmp
, bld
, i
+ first_component
));
2971 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT
, dest
,
2975 inst
->offset
= imm_offset
;
2976 inst
->size_written
= (num_components
+ first_component
) *
2977 inst
->dst
.component_size(inst
->exec_size
);
2979 /* If we are reading 64-bit data using 32-bit read messages we need
2980 * build proper 64-bit data elements by shuffling the low and high
2981 * 32-bit components around like we do for other things like UBOs
2984 if (type_sz(dest
.type
) == 8) {
2985 shuffle_32bit_load_result_to_64bit_data(
2986 bld
, dest
, retype(dest
, BRW_REGISTER_TYPE_F
), num_components
);
2988 for (unsigned c
= 0; c
< num_components
; c
++) {
2989 bld
.MOV(offset(orig_dest
, bld
, iter
* 2 + c
),
2990 offset(dest
, bld
, c
));
2994 /* If we are loading double data and we need a second read message
2997 if (num_iterations
> 1) {
2998 num_components
= instr
->num_components
- 2;
3006 nir_emit_intrinsic(bld
, instr
);
3012 fs_visitor::nir_emit_gs_intrinsic(const fs_builder
&bld
,
3013 nir_intrinsic_instr
*instr
)
3015 assert(stage
== MESA_SHADER_GEOMETRY
);
3016 fs_reg indirect_offset
;
3019 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
3020 dest
= get_nir_dest(instr
->dest
);
3022 switch (instr
->intrinsic
) {
3023 case nir_intrinsic_load_primitive_id
:
3024 assert(stage
== MESA_SHADER_GEOMETRY
);
3025 assert(brw_gs_prog_data(prog_data
)->include_primitive_id
);
3026 bld
.MOV(retype(dest
, BRW_REGISTER_TYPE_UD
),
3027 retype(fs_reg(brw_vec8_grf(2, 0)), BRW_REGISTER_TYPE_UD
));
3030 case nir_intrinsic_load_input
:
3031 unreachable("load_input intrinsics are invalid for the GS stage");
3033 case nir_intrinsic_load_per_vertex_input
:
3034 emit_gs_input_load(dest
, instr
->src
[0], instr
->const_index
[0],
3035 instr
->src
[1], instr
->num_components
,
3036 nir_intrinsic_component(instr
));
3039 case nir_intrinsic_emit_vertex_with_counter
:
3040 emit_gs_vertex(instr
->src
[0], instr
->const_index
[0]);
3043 case nir_intrinsic_end_primitive_with_counter
:
3044 emit_gs_end_primitive(instr
->src
[0]);
3047 case nir_intrinsic_set_vertex_count
:
3048 bld
.MOV(this->final_gs_vertex_count
, get_nir_src(instr
->src
[0]));
3051 case nir_intrinsic_load_invocation_id
: {
3052 fs_reg val
= nir_system_values
[SYSTEM_VALUE_INVOCATION_ID
];
3053 assert(val
.file
!= BAD_FILE
);
3054 dest
.type
= val
.type
;
3060 nir_emit_intrinsic(bld
, instr
);
3066 * Fetch the current render target layer index.
3069 fetch_render_target_array_index(const fs_builder
&bld
)
3071 if (bld
.shader
->devinfo
->gen
>= 6) {
3072 /* The render target array index is provided in the thread payload as
3073 * bits 26:16 of r0.0.
3075 const fs_reg idx
= bld
.vgrf(BRW_REGISTER_TYPE_UD
);
3076 bld
.AND(idx
, brw_uw1_reg(BRW_GENERAL_REGISTER_FILE
, 0, 1),
3080 /* Pre-SNB we only ever render into the first layer of the framebuffer
3081 * since layered rendering is not implemented.
3083 return brw_imm_ud(0);
3088 * Fake non-coherent framebuffer read implemented using TXF to fetch from the
3089 * framebuffer at the current fragment coordinates and sample index.
3092 fs_visitor::emit_non_coherent_fb_read(const fs_builder
&bld
, const fs_reg
&dst
,
3095 const struct gen_device_info
*devinfo
= bld
.shader
->devinfo
;
3097 assert(bld
.shader
->stage
== MESA_SHADER_FRAGMENT
);
3098 const brw_wm_prog_key
*wm_key
=
3099 reinterpret_cast<const brw_wm_prog_key
*>(key
);
3100 assert(!wm_key
->coherent_fb_fetch
);
3101 const struct brw_wm_prog_data
*wm_prog_data
=
3102 brw_wm_prog_data(stage_prog_data
);
3104 /* Calculate the surface index relative to the start of the texture binding
3105 * table block, since that's what the texturing messages expect.
3107 const unsigned surface
= target
+
3108 wm_prog_data
->binding_table
.render_target_read_start
-
3109 wm_prog_data
->base
.binding_table
.texture_start
;
3111 brw_mark_surface_used(
3112 bld
.shader
->stage_prog_data
,
3113 wm_prog_data
->binding_table
.render_target_read_start
+ target
);
3115 /* Calculate the fragment coordinates. */
3116 const fs_reg coords
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 3);
3117 bld
.MOV(offset(coords
, bld
, 0), pixel_x
);
3118 bld
.MOV(offset(coords
, bld
, 1), pixel_y
);
3119 bld
.MOV(offset(coords
, bld
, 2), fetch_render_target_array_index(bld
));
3121 /* Calculate the sample index and MCS payload when multisampling. Luckily
3122 * the MCS fetch message behaves deterministically for UMS surfaces, so it
3123 * shouldn't be necessary to recompile based on whether the framebuffer is
3126 if (wm_key
->multisample_fbo
&&
3127 nir_system_values
[SYSTEM_VALUE_SAMPLE_ID
].file
== BAD_FILE
)
3128 nir_system_values
[SYSTEM_VALUE_SAMPLE_ID
] = *emit_sampleid_setup();
3130 const fs_reg sample
= nir_system_values
[SYSTEM_VALUE_SAMPLE_ID
];
3131 const fs_reg mcs
= wm_key
->multisample_fbo
?
3132 emit_mcs_fetch(coords
, 3, brw_imm_ud(surface
)) : fs_reg();
3134 /* Use either a normal or a CMS texel fetch message depending on whether
3135 * the framebuffer is single or multisample. On SKL+ use the wide CMS
3136 * message just in case the framebuffer uses 16x multisampling, it should
3137 * be equivalent to the normal CMS fetch for lower multisampling modes.
3139 const opcode op
= !wm_key
->multisample_fbo
? SHADER_OPCODE_TXF_LOGICAL
:
3140 devinfo
->gen
>= 9 ? SHADER_OPCODE_TXF_CMS_W_LOGICAL
:
3141 SHADER_OPCODE_TXF_CMS_LOGICAL
;
3143 /* Emit the instruction. */
3144 const fs_reg srcs
[] = { coords
, fs_reg(), brw_imm_ud(0), fs_reg(),
3146 brw_imm_ud(surface
), brw_imm_ud(0),
3147 fs_reg(), brw_imm_ud(3), brw_imm_ud(0) };
3148 STATIC_ASSERT(ARRAY_SIZE(srcs
) == TEX_LOGICAL_NUM_SRCS
);
3150 fs_inst
*inst
= bld
.emit(op
, dst
, srcs
, ARRAY_SIZE(srcs
));
3151 inst
->size_written
= 4 * inst
->dst
.component_size(inst
->exec_size
);
3157 * Actual coherent framebuffer read implemented using the native render target
3158 * read message. Requires SKL+.
3161 emit_coherent_fb_read(const fs_builder
&bld
, const fs_reg
&dst
, unsigned target
)
3163 assert(bld
.shader
->devinfo
->gen
>= 9);
3164 fs_inst
*inst
= bld
.emit(FS_OPCODE_FB_READ_LOGICAL
, dst
);
3165 inst
->target
= target
;
3166 inst
->size_written
= 4 * inst
->dst
.component_size(inst
->exec_size
);
3172 alloc_temporary(const fs_builder
&bld
, unsigned size
, fs_reg
*regs
, unsigned n
)
3174 if (n
&& regs
[0].file
!= BAD_FILE
) {
3178 const fs_reg tmp
= bld
.vgrf(BRW_REGISTER_TYPE_F
, size
);
3180 for (unsigned i
= 0; i
< n
; i
++)
3188 alloc_frag_output(fs_visitor
*v
, unsigned location
)
3190 assert(v
->stage
== MESA_SHADER_FRAGMENT
);
3191 const brw_wm_prog_key
*const key
=
3192 reinterpret_cast<const brw_wm_prog_key
*>(v
->key
);
3193 const unsigned l
= GET_FIELD(location
, BRW_NIR_FRAG_OUTPUT_LOCATION
);
3194 const unsigned i
= GET_FIELD(location
, BRW_NIR_FRAG_OUTPUT_INDEX
);
3196 if (i
> 0 || (key
->force_dual_color_blend
&& l
== FRAG_RESULT_DATA1
))
3197 return alloc_temporary(v
->bld
, 4, &v
->dual_src_output
, 1);
3199 else if (l
== FRAG_RESULT_COLOR
)
3200 return alloc_temporary(v
->bld
, 4, v
->outputs
,
3201 MAX2(key
->nr_color_regions
, 1));
3203 else if (l
== FRAG_RESULT_DEPTH
)
3204 return alloc_temporary(v
->bld
, 1, &v
->frag_depth
, 1);
3206 else if (l
== FRAG_RESULT_STENCIL
)
3207 return alloc_temporary(v
->bld
, 1, &v
->frag_stencil
, 1);
3209 else if (l
== FRAG_RESULT_SAMPLE_MASK
)
3210 return alloc_temporary(v
->bld
, 1, &v
->sample_mask
, 1);
3212 else if (l
>= FRAG_RESULT_DATA0
&&
3213 l
< FRAG_RESULT_DATA0
+ BRW_MAX_DRAW_BUFFERS
)
3214 return alloc_temporary(v
->bld
, 4,
3215 &v
->outputs
[l
- FRAG_RESULT_DATA0
], 1);
3218 unreachable("Invalid location");
3222 fs_visitor::nir_emit_fs_intrinsic(const fs_builder
&bld
,
3223 nir_intrinsic_instr
*instr
)
3225 assert(stage
== MESA_SHADER_FRAGMENT
);
3228 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
3229 dest
= get_nir_dest(instr
->dest
);
3231 switch (instr
->intrinsic
) {
3232 case nir_intrinsic_load_front_face
:
3233 bld
.MOV(retype(dest
, BRW_REGISTER_TYPE_D
),
3234 *emit_frontfacing_interpolation());
3237 case nir_intrinsic_load_sample_pos
: {
3238 fs_reg sample_pos
= nir_system_values
[SYSTEM_VALUE_SAMPLE_POS
];
3239 assert(sample_pos
.file
!= BAD_FILE
);
3240 dest
.type
= sample_pos
.type
;
3241 bld
.MOV(dest
, sample_pos
);
3242 bld
.MOV(offset(dest
, bld
, 1), offset(sample_pos
, bld
, 1));
3246 case nir_intrinsic_load_layer_id
:
3247 dest
.type
= BRW_REGISTER_TYPE_UD
;
3248 bld
.MOV(dest
, fetch_render_target_array_index(bld
));
3251 case nir_intrinsic_load_helper_invocation
:
3252 case nir_intrinsic_load_sample_mask_in
:
3253 case nir_intrinsic_load_sample_id
: {
3254 gl_system_value sv
= nir_system_value_from_intrinsic(instr
->intrinsic
);
3255 fs_reg val
= nir_system_values
[sv
];
3256 assert(val
.file
!= BAD_FILE
);
3257 dest
.type
= val
.type
;
3262 case nir_intrinsic_store_output
: {
3263 const fs_reg src
= get_nir_src(instr
->src
[0]);
3264 const nir_const_value
*const_offset
= nir_src_as_const_value(instr
->src
[1]);
3265 assert(const_offset
&& "Indirect output stores not allowed");
3266 const unsigned location
= nir_intrinsic_base(instr
) +
3267 SET_FIELD(const_offset
->u32
[0], BRW_NIR_FRAG_OUTPUT_LOCATION
);
3268 const fs_reg new_dest
= retype(alloc_frag_output(this, location
),
3271 for (unsigned j
= 0; j
< instr
->num_components
; j
++)
3272 bld
.MOV(offset(new_dest
, bld
, nir_intrinsic_component(instr
) + j
),
3273 offset(src
, bld
, j
));
3278 case nir_intrinsic_load_output
: {
3279 const unsigned l
= GET_FIELD(nir_intrinsic_base(instr
),
3280 BRW_NIR_FRAG_OUTPUT_LOCATION
);
3281 assert(l
>= FRAG_RESULT_DATA0
);
3282 nir_const_value
*const_offset
= nir_src_as_const_value(instr
->src
[0]);
3283 assert(const_offset
&& "Indirect output loads not allowed");
3284 const unsigned target
= l
- FRAG_RESULT_DATA0
+ const_offset
->u32
[0];
3285 const fs_reg tmp
= bld
.vgrf(dest
.type
, 4);
3287 if (reinterpret_cast<const brw_wm_prog_key
*>(key
)->coherent_fb_fetch
)
3288 emit_coherent_fb_read(bld
, tmp
, target
);
3290 emit_non_coherent_fb_read(bld
, tmp
, target
);
3292 for (unsigned j
= 0; j
< instr
->num_components
; j
++) {
3293 bld
.MOV(offset(dest
, bld
, j
),
3294 offset(tmp
, bld
, nir_intrinsic_component(instr
) + j
));
3300 case nir_intrinsic_discard
:
3301 case nir_intrinsic_discard_if
: {
3302 /* We track our discarded pixels in f0.1. By predicating on it, we can
3303 * update just the flag bits that aren't yet discarded. If there's no
3304 * condition, we emit a CMP of g0 != g0, so all currently executing
3305 * channels will get turned off.
3308 if (instr
->intrinsic
== nir_intrinsic_discard_if
) {
3309 cmp
= bld
.CMP(bld
.null_reg_f(), get_nir_src(instr
->src
[0]),
3310 brw_imm_d(0), BRW_CONDITIONAL_Z
);
3312 fs_reg some_reg
= fs_reg(retype(brw_vec8_grf(0, 0),
3313 BRW_REGISTER_TYPE_UW
));
3314 cmp
= bld
.CMP(bld
.null_reg_f(), some_reg
, some_reg
, BRW_CONDITIONAL_NZ
);
3316 cmp
->predicate
= BRW_PREDICATE_NORMAL
;
3317 cmp
->flag_subreg
= 1;
3319 if (devinfo
->gen
>= 6) {
3320 emit_discard_jump();
3325 case nir_intrinsic_load_input
: {
3326 /* load_input is only used for flat inputs */
3327 unsigned base
= nir_intrinsic_base(instr
);
3328 unsigned component
= nir_intrinsic_component(instr
);
3329 unsigned num_components
= instr
->num_components
;
3330 enum brw_reg_type type
= dest
.type
;
3332 /* Special case fields in the VUE header */
3333 if (base
== VARYING_SLOT_LAYER
)
3335 else if (base
== VARYING_SLOT_VIEWPORT
)
3338 if (nir_dest_bit_size(instr
->dest
) == 64) {
3339 /* const_index is in 32-bit type size units that could not be aligned
3340 * with DF. We need to read the double vector as if it was a float
3341 * vector of twice the number of components to fetch the right data.
3343 type
= BRW_REGISTER_TYPE_F
;
3344 num_components
*= 2;
3347 for (unsigned int i
= 0; i
< num_components
; i
++) {
3348 struct brw_reg interp
= interp_reg(base
, component
+ i
);
3349 interp
= suboffset(interp
, 3);
3350 bld
.emit(FS_OPCODE_CINTERP
, offset(retype(dest
, type
), bld
, i
),
3351 retype(fs_reg(interp
), type
));
3354 if (nir_dest_bit_size(instr
->dest
) == 64) {
3355 shuffle_32bit_load_result_to_64bit_data(bld
,
3358 instr
->num_components
);
3363 case nir_intrinsic_load_barycentric_pixel
:
3364 case nir_intrinsic_load_barycentric_centroid
:
3365 case nir_intrinsic_load_barycentric_sample
:
3366 /* Do nothing - load_interpolated_input handling will handle it later. */
3369 case nir_intrinsic_load_barycentric_at_sample
: {
3370 const glsl_interp_mode interpolation
=
3371 (enum glsl_interp_mode
) nir_intrinsic_interp_mode(instr
);
3373 nir_const_value
*const_sample
= nir_src_as_const_value(instr
->src
[0]);
3376 unsigned msg_data
= const_sample
->i32
[0] << 4;
3378 emit_pixel_interpolater_send(bld
,
3379 FS_OPCODE_INTERPOLATE_AT_SAMPLE
,
3382 brw_imm_ud(msg_data
),
3385 const fs_reg sample_src
= retype(get_nir_src(instr
->src
[0]),
3386 BRW_REGISTER_TYPE_UD
);
3388 if (nir_src_is_dynamically_uniform(instr
->src
[0])) {
3389 const fs_reg sample_id
= bld
.emit_uniformize(sample_src
);
3390 const fs_reg msg_data
= vgrf(glsl_type::uint_type
);
3391 bld
.exec_all().group(1, 0)
3392 .SHL(msg_data
, sample_id
, brw_imm_ud(4u));
3393 emit_pixel_interpolater_send(bld
,
3394 FS_OPCODE_INTERPOLATE_AT_SAMPLE
,
3400 /* Make a loop that sends a message to the pixel interpolater
3401 * for the sample number in each live channel. If there are
3402 * multiple channels with the same sample number then these
3403 * will be handled simultaneously with a single interation of
3406 bld
.emit(BRW_OPCODE_DO
);
3408 /* Get the next live sample number into sample_id_reg */
3409 const fs_reg sample_id
= bld
.emit_uniformize(sample_src
);
3411 /* Set the flag register so that we can perform the send
3412 * message on all channels that have the same sample number
3414 bld
.CMP(bld
.null_reg_ud(),
3415 sample_src
, sample_id
,
3416 BRW_CONDITIONAL_EQ
);
3417 const fs_reg msg_data
= vgrf(glsl_type::uint_type
);
3418 bld
.exec_all().group(1, 0)
3419 .SHL(msg_data
, sample_id
, brw_imm_ud(4u));
3421 emit_pixel_interpolater_send(bld
,
3422 FS_OPCODE_INTERPOLATE_AT_SAMPLE
,
3427 set_predicate(BRW_PREDICATE_NORMAL
, inst
);
3429 /* Continue the loop if there are any live channels left */
3430 set_predicate_inv(BRW_PREDICATE_NORMAL
,
3432 bld
.emit(BRW_OPCODE_WHILE
));
3438 case nir_intrinsic_load_barycentric_at_offset
: {
3439 const glsl_interp_mode interpolation
=
3440 (enum glsl_interp_mode
) nir_intrinsic_interp_mode(instr
);
3442 nir_const_value
*const_offset
= nir_src_as_const_value(instr
->src
[0]);
3445 unsigned off_x
= MIN2((int)(const_offset
->f32
[0] * 16), 7) & 0xf;
3446 unsigned off_y
= MIN2((int)(const_offset
->f32
[1] * 16), 7) & 0xf;
3448 emit_pixel_interpolater_send(bld
,
3449 FS_OPCODE_INTERPOLATE_AT_SHARED_OFFSET
,
3452 brw_imm_ud(off_x
| (off_y
<< 4)),
3455 fs_reg src
= vgrf(glsl_type::ivec2_type
);
3456 fs_reg offset_src
= retype(get_nir_src(instr
->src
[0]),
3457 BRW_REGISTER_TYPE_F
);
3458 for (int i
= 0; i
< 2; i
++) {
3459 fs_reg temp
= vgrf(glsl_type::float_type
);
3460 bld
.MUL(temp
, offset(offset_src
, bld
, i
), brw_imm_f(16.0f
));
3461 fs_reg itemp
= vgrf(glsl_type::int_type
);
3463 bld
.MOV(itemp
, temp
);
3465 /* Clamp the upper end of the range to +7/16.
3466 * ARB_gpu_shader5 requires that we support a maximum offset
3467 * of +0.5, which isn't representable in a S0.4 value -- if
3468 * we didn't clamp it, we'd end up with -8/16, which is the
3469 * opposite of what the shader author wanted.
3471 * This is legal due to ARB_gpu_shader5's quantization
3474 * "Not all values of <offset> may be supported; x and y
3475 * offsets may be rounded to fixed-point values with the
3476 * number of fraction bits given by the
3477 * implementation-dependent constant
3478 * FRAGMENT_INTERPOLATION_OFFSET_BITS"
3480 set_condmod(BRW_CONDITIONAL_L
,
3481 bld
.SEL(offset(src
, bld
, i
), itemp
, brw_imm_d(7)));
3484 const enum opcode opcode
= FS_OPCODE_INTERPOLATE_AT_PER_SLOT_OFFSET
;
3485 emit_pixel_interpolater_send(bld
,
3495 case nir_intrinsic_load_interpolated_input
: {
3496 if (nir_intrinsic_base(instr
) == VARYING_SLOT_POS
) {
3497 emit_fragcoord_interpolation(dest
);
3501 assert(instr
->src
[0].ssa
&&
3502 instr
->src
[0].ssa
->parent_instr
->type
== nir_instr_type_intrinsic
);
3503 nir_intrinsic_instr
*bary_intrinsic
=
3504 nir_instr_as_intrinsic(instr
->src
[0].ssa
->parent_instr
);
3505 nir_intrinsic_op bary_intrin
= bary_intrinsic
->intrinsic
;
3506 enum glsl_interp_mode interp_mode
=
3507 (enum glsl_interp_mode
) nir_intrinsic_interp_mode(bary_intrinsic
);
3510 if (bary_intrin
== nir_intrinsic_load_barycentric_at_offset
||
3511 bary_intrin
== nir_intrinsic_load_barycentric_at_sample
) {
3512 /* Use the result of the PI message */
3513 dst_xy
= retype(get_nir_src(instr
->src
[0]), BRW_REGISTER_TYPE_F
);
3515 /* Use the delta_xy values computed from the payload */
3516 enum brw_barycentric_mode bary
=
3517 brw_barycentric_mode(interp_mode
, bary_intrin
);
3519 dst_xy
= this->delta_xy
[bary
];
3522 for (unsigned int i
= 0; i
< instr
->num_components
; i
++) {
3524 fs_reg(interp_reg(nir_intrinsic_base(instr
),
3525 nir_intrinsic_component(instr
) + i
));
3526 interp
.type
= BRW_REGISTER_TYPE_F
;
3527 dest
.type
= BRW_REGISTER_TYPE_F
;
3529 if (devinfo
->gen
< 6 && interp_mode
== INTERP_MODE_SMOOTH
) {
3530 fs_reg tmp
= vgrf(glsl_type::float_type
);
3531 bld
.emit(FS_OPCODE_LINTERP
, tmp
, dst_xy
, interp
);
3532 bld
.MUL(offset(dest
, bld
, i
), tmp
, this->pixel_w
);
3534 bld
.emit(FS_OPCODE_LINTERP
, offset(dest
, bld
, i
), dst_xy
, interp
);
3541 nir_emit_intrinsic(bld
, instr
);
3547 fs_visitor::nir_emit_cs_intrinsic(const fs_builder
&bld
,
3548 nir_intrinsic_instr
*instr
)
3550 assert(stage
== MESA_SHADER_COMPUTE
);
3551 struct brw_cs_prog_data
*cs_prog_data
= brw_cs_prog_data(prog_data
);
3554 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
3555 dest
= get_nir_dest(instr
->dest
);
3557 switch (instr
->intrinsic
) {
3558 case nir_intrinsic_barrier
:
3560 cs_prog_data
->uses_barrier
= true;
3563 case nir_intrinsic_load_subgroup_id
:
3564 bld
.MOV(retype(dest
, BRW_REGISTER_TYPE_UD
), subgroup_id
);
3567 case nir_intrinsic_load_local_invocation_id
:
3568 case nir_intrinsic_load_work_group_id
: {
3569 gl_system_value sv
= nir_system_value_from_intrinsic(instr
->intrinsic
);
3570 fs_reg val
= nir_system_values
[sv
];
3571 assert(val
.file
!= BAD_FILE
);
3572 dest
.type
= val
.type
;
3573 for (unsigned i
= 0; i
< 3; i
++)
3574 bld
.MOV(offset(dest
, bld
, i
), offset(val
, bld
, i
));
3578 case nir_intrinsic_load_num_work_groups
: {
3579 const unsigned surface
=
3580 cs_prog_data
->binding_table
.work_groups_start
;
3582 cs_prog_data
->uses_num_work_groups
= true;
3584 fs_reg surf_index
= brw_imm_ud(surface
);
3585 brw_mark_surface_used(prog_data
, surface
);
3587 /* Read the 3 GLuint components of gl_NumWorkGroups */
3588 for (unsigned i
= 0; i
< 3; i
++) {
3589 fs_reg read_result
=
3590 emit_untyped_read(bld
, surf_index
,
3592 1 /* dims */, 1 /* size */,
3593 BRW_PREDICATE_NONE
);
3594 read_result
.type
= dest
.type
;
3595 bld
.MOV(dest
, read_result
);
3596 dest
= offset(dest
, bld
, 1);
3601 case nir_intrinsic_shared_atomic_add
:
3602 nir_emit_shared_atomic(bld
, BRW_AOP_ADD
, instr
);
3604 case nir_intrinsic_shared_atomic_imin
:
3605 nir_emit_shared_atomic(bld
, BRW_AOP_IMIN
, instr
);
3607 case nir_intrinsic_shared_atomic_umin
:
3608 nir_emit_shared_atomic(bld
, BRW_AOP_UMIN
, instr
);
3610 case nir_intrinsic_shared_atomic_imax
:
3611 nir_emit_shared_atomic(bld
, BRW_AOP_IMAX
, instr
);
3613 case nir_intrinsic_shared_atomic_umax
:
3614 nir_emit_shared_atomic(bld
, BRW_AOP_UMAX
, instr
);
3616 case nir_intrinsic_shared_atomic_and
:
3617 nir_emit_shared_atomic(bld
, BRW_AOP_AND
, instr
);
3619 case nir_intrinsic_shared_atomic_or
:
3620 nir_emit_shared_atomic(bld
, BRW_AOP_OR
, instr
);
3622 case nir_intrinsic_shared_atomic_xor
:
3623 nir_emit_shared_atomic(bld
, BRW_AOP_XOR
, instr
);
3625 case nir_intrinsic_shared_atomic_exchange
:
3626 nir_emit_shared_atomic(bld
, BRW_AOP_MOV
, instr
);
3628 case nir_intrinsic_shared_atomic_comp_swap
:
3629 nir_emit_shared_atomic(bld
, BRW_AOP_CMPWR
, instr
);
3632 case nir_intrinsic_load_shared
: {
3633 assert(devinfo
->gen
>= 7);
3635 fs_reg surf_index
= brw_imm_ud(GEN7_BTI_SLM
);
3637 /* Get the offset to read from */
3639 nir_const_value
*const_offset
= nir_src_as_const_value(instr
->src
[0]);
3641 offset_reg
= brw_imm_ud(instr
->const_index
[0] + const_offset
->u32
[0]);
3643 offset_reg
= vgrf(glsl_type::uint_type
);
3645 retype(get_nir_src(instr
->src
[0]), BRW_REGISTER_TYPE_UD
),
3646 brw_imm_ud(instr
->const_index
[0]));
3649 /* Read the vector */
3650 do_untyped_vector_read(bld
, dest
, surf_index
, offset_reg
,
3651 instr
->num_components
);
3655 case nir_intrinsic_store_shared
: {
3656 assert(devinfo
->gen
>= 7);
3659 fs_reg surf_index
= brw_imm_ud(GEN7_BTI_SLM
);
3662 fs_reg val_reg
= get_nir_src(instr
->src
[0]);
3665 unsigned writemask
= instr
->const_index
[1];
3667 /* get_nir_src() retypes to integer. Be wary of 64-bit types though
3668 * since the untyped writes below operate in units of 32-bits, which
3669 * means that we need to write twice as many components each time.
3670 * Also, we have to suffle 64-bit data to be in the appropriate layout
3671 * expected by our 32-bit write messages.
3673 unsigned type_size
= 4;
3674 if (nir_src_bit_size(instr
->src
[0]) == 64) {
3676 val_reg
= shuffle_64bit_data_for_32bit_write(bld
,
3677 val_reg
, instr
->num_components
);
3680 unsigned type_slots
= type_size
/ 4;
3682 /* Combine groups of consecutive enabled channels in one write
3683 * message. We use ffs to find the first enabled channel and then ffs on
3684 * the bit-inverse, down-shifted writemask to determine the length of
3685 * the block of enabled bits.
3688 unsigned first_component
= ffs(writemask
) - 1;
3689 unsigned length
= ffs(~(writemask
>> first_component
)) - 1;
3691 /* We can't write more than 2 64-bit components at once. Limit the
3692 * length of the write to what we can do and let the next iteration
3696 length
= MIN2(2, length
);
3699 nir_const_value
*const_offset
= nir_src_as_const_value(instr
->src
[1]);
3701 offset_reg
= brw_imm_ud(instr
->const_index
[0] + const_offset
->u32
[0] +
3702 type_size
* first_component
);
3704 offset_reg
= vgrf(glsl_type::uint_type
);
3706 retype(get_nir_src(instr
->src
[1]), BRW_REGISTER_TYPE_UD
),
3707 brw_imm_ud(instr
->const_index
[0] + type_size
* first_component
));
3710 emit_untyped_write(bld
, surf_index
, offset_reg
,
3711 offset(val_reg
, bld
, first_component
* type_slots
),
3712 1 /* dims */, length
* type_slots
,
3713 BRW_PREDICATE_NONE
);
3715 /* Clear the bits in the writemask that we just wrote, then try
3716 * again to see if more channels are left.
3718 writemask
&= (15 << (first_component
+ length
));
3725 nir_emit_intrinsic(bld
, instr
);
3731 brw_nir_reduction_op_identity(const fs_builder
&bld
,
3732 nir_op op
, brw_reg_type type
)
3734 nir_const_value value
= nir_alu_binop_identity(op
, type_sz(type
) * 8);
3735 switch (type_sz(type
)) {
3737 assert(type
!= BRW_REGISTER_TYPE_HF
);
3738 return retype(brw_imm_uw(value
.u16
[0]), type
);
3740 return retype(brw_imm_ud(value
.u32
[0]), type
);
3742 if (type
== BRW_REGISTER_TYPE_DF
)
3743 return setup_imm_df(bld
, value
.f64
[0]);
3745 return retype(brw_imm_u64(value
.u64
[0]), type
);
3747 unreachable("Invalid type size");
3752 brw_op_for_nir_reduction_op(nir_op op
)
3755 case nir_op_iadd
: return BRW_OPCODE_ADD
;
3756 case nir_op_fadd
: return BRW_OPCODE_ADD
;
3757 case nir_op_imul
: return BRW_OPCODE_MUL
;
3758 case nir_op_fmul
: return BRW_OPCODE_MUL
;
3759 case nir_op_imin
: return BRW_OPCODE_SEL
;
3760 case nir_op_umin
: return BRW_OPCODE_SEL
;
3761 case nir_op_fmin
: return BRW_OPCODE_SEL
;
3762 case nir_op_imax
: return BRW_OPCODE_SEL
;
3763 case nir_op_umax
: return BRW_OPCODE_SEL
;
3764 case nir_op_fmax
: return BRW_OPCODE_SEL
;
3765 case nir_op_iand
: return BRW_OPCODE_AND
;
3766 case nir_op_ior
: return BRW_OPCODE_OR
;
3767 case nir_op_ixor
: return BRW_OPCODE_XOR
;
3769 unreachable("Invalid reduction operation");
3773 static brw_conditional_mod
3774 brw_cond_mod_for_nir_reduction_op(nir_op op
)
3777 case nir_op_iadd
: return BRW_CONDITIONAL_NONE
;
3778 case nir_op_fadd
: return BRW_CONDITIONAL_NONE
;
3779 case nir_op_imul
: return BRW_CONDITIONAL_NONE
;
3780 case nir_op_fmul
: return BRW_CONDITIONAL_NONE
;
3781 case nir_op_imin
: return BRW_CONDITIONAL_L
;
3782 case nir_op_umin
: return BRW_CONDITIONAL_L
;
3783 case nir_op_fmin
: return BRW_CONDITIONAL_L
;
3784 case nir_op_imax
: return BRW_CONDITIONAL_GE
;
3785 case nir_op_umax
: return BRW_CONDITIONAL_GE
;
3786 case nir_op_fmax
: return BRW_CONDITIONAL_GE
;
3787 case nir_op_iand
: return BRW_CONDITIONAL_NONE
;
3788 case nir_op_ior
: return BRW_CONDITIONAL_NONE
;
3789 case nir_op_ixor
: return BRW_CONDITIONAL_NONE
;
3791 unreachable("Invalid reduction operation");
3796 fs_visitor::nir_emit_intrinsic(const fs_builder
&bld
, nir_intrinsic_instr
*instr
)
3799 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
3800 dest
= get_nir_dest(instr
->dest
);
3802 switch (instr
->intrinsic
) {
3803 case nir_intrinsic_image_var_load
:
3804 case nir_intrinsic_image_var_store
:
3805 case nir_intrinsic_image_var_atomic_add
:
3806 case nir_intrinsic_image_var_atomic_min
:
3807 case nir_intrinsic_image_var_atomic_max
:
3808 case nir_intrinsic_image_var_atomic_and
:
3809 case nir_intrinsic_image_var_atomic_or
:
3810 case nir_intrinsic_image_var_atomic_xor
:
3811 case nir_intrinsic_image_var_atomic_exchange
:
3812 case nir_intrinsic_image_var_atomic_comp_swap
: {
3813 using namespace image_access
;
3815 if (stage
== MESA_SHADER_FRAGMENT
&&
3816 instr
->intrinsic
!= nir_intrinsic_image_var_load
)
3817 brw_wm_prog_data(prog_data
)->has_side_effects
= true;
3819 /* Get the referenced image variable and type. */
3820 const nir_variable
*var
= instr
->variables
[0]->var
;
3821 const glsl_type
*type
= var
->type
->without_array();
3822 const brw_reg_type base_type
= get_image_base_type(type
);
3824 /* Get some metadata from the image intrinsic. */
3825 const nir_intrinsic_info
*info
= &nir_intrinsic_infos
[instr
->intrinsic
];
3826 const unsigned arr_dims
= type
->sampler_array
? 1 : 0;
3827 const unsigned surf_dims
= type
->coordinate_components() - arr_dims
;
3828 const unsigned format
= var
->data
.image
.format
;
3829 const unsigned dest_components
= nir_intrinsic_dest_components(instr
);
3831 /* Get the arguments of the image intrinsic. */
3832 const fs_reg image
= get_nir_image_deref(instr
->variables
[0]);
3833 const fs_reg addr
= retype(get_nir_src(instr
->src
[0]),
3834 BRW_REGISTER_TYPE_UD
);
3835 const fs_reg src0
= (info
->num_srcs
>= 3 ?
3836 retype(get_nir_src(instr
->src
[2]), base_type
) :
3838 const fs_reg src1
= (info
->num_srcs
>= 4 ?
3839 retype(get_nir_src(instr
->src
[3]), base_type
) :
3843 /* Emit an image load, store or atomic op. */
3844 if (instr
->intrinsic
== nir_intrinsic_image_var_load
)
3845 tmp
= emit_image_load(bld
, image
, addr
, surf_dims
, arr_dims
, format
);
3847 else if (instr
->intrinsic
== nir_intrinsic_image_var_store
)
3848 emit_image_store(bld
, image
, addr
, src0
, surf_dims
, arr_dims
,
3849 var
->data
.image
.write_only
? GL_NONE
: format
);
3852 tmp
= emit_image_atomic(bld
, image
, addr
, src0
, src1
,
3853 surf_dims
, arr_dims
, dest_components
,
3854 get_image_atomic_op(instr
->intrinsic
, type
));
3856 /* Assign the result. */
3857 for (unsigned c
= 0; c
< dest_components
; ++c
) {
3858 bld
.MOV(offset(retype(dest
, base_type
), bld
, c
),
3859 offset(tmp
, bld
, c
));
3864 case nir_intrinsic_memory_barrier_atomic_counter
:
3865 case nir_intrinsic_memory_barrier_buffer
:
3866 case nir_intrinsic_memory_barrier_image
:
3867 case nir_intrinsic_memory_barrier
: {
3868 const fs_builder ubld
= bld
.group(8, 0);
3869 const fs_reg tmp
= ubld
.vgrf(BRW_REGISTER_TYPE_UD
, 2);
3870 ubld
.emit(SHADER_OPCODE_MEMORY_FENCE
, tmp
)
3871 ->size_written
= 2 * REG_SIZE
;
3875 case nir_intrinsic_group_memory_barrier
:
3876 case nir_intrinsic_memory_barrier_shared
:
3877 /* We treat these workgroup-level barriers as no-ops. This should be
3878 * safe at present and as long as:
3880 * - Memory access instructions are not subsequently reordered by the
3881 * compiler back-end.
3883 * - All threads from a given compute shader workgroup fit within a
3884 * single subslice and therefore talk to the same HDC shared unit
3885 * what supposedly guarantees ordering and coherency between threads
3886 * from the same workgroup. This may change in the future when we
3887 * start splitting workgroups across multiple subslices.
3889 * - The context is not in fault-and-stream mode, which could cause
3890 * memory transactions (including to SLM) prior to the barrier to be
3891 * replayed after the barrier if a pagefault occurs. This shouldn't
3892 * be a problem up to and including SKL because fault-and-stream is
3893 * not usable due to hardware issues, but that's likely to change in
3898 case nir_intrinsic_shader_clock
: {
3899 /* We cannot do anything if there is an event, so ignore it for now */
3900 const fs_reg shader_clock
= get_timestamp(bld
);
3901 const fs_reg srcs
[] = { component(shader_clock
, 0),
3902 component(shader_clock
, 1) };
3903 bld
.LOAD_PAYLOAD(dest
, srcs
, ARRAY_SIZE(srcs
), 0);
3907 case nir_intrinsic_image_var_size
: {
3908 /* Get the referenced image variable and type. */
3909 const nir_variable
*var
= instr
->variables
[0]->var
;
3910 const glsl_type
*type
= var
->type
->without_array();
3912 /* Get the size of the image. */
3913 const fs_reg image
= get_nir_image_deref(instr
->variables
[0]);
3914 const fs_reg size
= offset(image
, bld
, BRW_IMAGE_PARAM_SIZE_OFFSET
);
3916 /* For 1DArray image types, the array index is stored in the Z component.
3917 * Fix this by swizzling the Z component to the Y component.
3919 const bool is_1d_array_image
=
3920 type
->sampler_dimensionality
== GLSL_SAMPLER_DIM_1D
&&
3921 type
->sampler_array
;
3923 /* For CubeArray images, we should count the number of cubes instead
3924 * of the number of faces. Fix it by dividing the (Z component) by 6.
3926 const bool is_cube_array_image
=
3927 type
->sampler_dimensionality
== GLSL_SAMPLER_DIM_CUBE
&&
3928 type
->sampler_array
;
3930 /* Copy all the components. */
3931 for (unsigned c
= 0; c
< instr
->dest
.ssa
.num_components
; ++c
) {
3932 if ((int)c
>= type
->coordinate_components()) {
3933 bld
.MOV(offset(retype(dest
, BRW_REGISTER_TYPE_D
), bld
, c
),
3935 } else if (c
== 1 && is_1d_array_image
) {
3936 bld
.MOV(offset(retype(dest
, BRW_REGISTER_TYPE_D
), bld
, c
),
3937 offset(size
, bld
, 2));
3938 } else if (c
== 2 && is_cube_array_image
) {
3939 bld
.emit(SHADER_OPCODE_INT_QUOTIENT
,
3940 offset(retype(dest
, BRW_REGISTER_TYPE_D
), bld
, c
),
3941 offset(size
, bld
, c
), brw_imm_d(6));
3943 bld
.MOV(offset(retype(dest
, BRW_REGISTER_TYPE_D
), bld
, c
),
3944 offset(size
, bld
, c
));
3951 case nir_intrinsic_image_var_samples
:
3952 /* The driver does not support multi-sampled images. */
3953 bld
.MOV(retype(dest
, BRW_REGISTER_TYPE_D
), brw_imm_d(1));
3956 case nir_intrinsic_load_uniform
: {
3957 /* Offsets are in bytes but they should always aligned to
3960 assert(instr
->const_index
[0] % 4 == 0 ||
3961 instr
->const_index
[0] % type_sz(dest
.type
) == 0);
3963 fs_reg
src(UNIFORM
, instr
->const_index
[0] / 4, dest
.type
);
3965 nir_const_value
*const_offset
= nir_src_as_const_value(instr
->src
[0]);
3967 assert(const_offset
->u32
[0] % type_sz(dest
.type
) == 0);
3968 /* For 16-bit types we add the module of the const_index[0]
3969 * offset to access to not 32-bit aligned element
3971 src
.offset
= const_offset
->u32
[0] + instr
->const_index
[0] % 4;
3973 for (unsigned j
= 0; j
< instr
->num_components
; j
++) {
3974 bld
.MOV(offset(dest
, bld
, j
), offset(src
, bld
, j
));
3977 fs_reg indirect
= retype(get_nir_src(instr
->src
[0]),
3978 BRW_REGISTER_TYPE_UD
);
3980 /* We need to pass a size to the MOV_INDIRECT but we don't want it to
3981 * go past the end of the uniform. In order to keep the n'th
3982 * component from running past, we subtract off the size of all but
3983 * one component of the vector.
3985 assert(instr
->const_index
[1] >=
3986 instr
->num_components
* (int) type_sz(dest
.type
));
3987 unsigned read_size
= instr
->const_index
[1] -
3988 (instr
->num_components
- 1) * type_sz(dest
.type
);
3990 bool supports_64bit_indirects
=
3991 !devinfo
->is_cherryview
&& !gen_device_info_is_9lp(devinfo
);
3993 if (type_sz(dest
.type
) != 8 || supports_64bit_indirects
) {
3994 for (unsigned j
= 0; j
< instr
->num_components
; j
++) {
3995 bld
.emit(SHADER_OPCODE_MOV_INDIRECT
,
3996 offset(dest
, bld
, j
), offset(src
, bld
, j
),
3997 indirect
, brw_imm_ud(read_size
));
4000 const unsigned num_mov_indirects
=
4001 type_sz(dest
.type
) / type_sz(BRW_REGISTER_TYPE_UD
);
4002 /* We read a little bit less per MOV INDIRECT, as they are now
4003 * 32-bits ones instead of 64-bit. Fix read_size then.
4005 const unsigned read_size_32bit
= read_size
-
4006 (num_mov_indirects
- 1) * type_sz(BRW_REGISTER_TYPE_UD
);
4007 for (unsigned j
= 0; j
< instr
->num_components
; j
++) {
4008 for (unsigned i
= 0; i
< num_mov_indirects
; i
++) {
4009 bld
.emit(SHADER_OPCODE_MOV_INDIRECT
,
4010 subscript(offset(dest
, bld
, j
), BRW_REGISTER_TYPE_UD
, i
),
4011 subscript(offset(src
, bld
, j
), BRW_REGISTER_TYPE_UD
, i
),
4012 indirect
, brw_imm_ud(read_size_32bit
));
4020 case nir_intrinsic_load_ubo
: {
4021 nir_const_value
*const_index
= nir_src_as_const_value(instr
->src
[0]);
4025 const unsigned index
= stage_prog_data
->binding_table
.ubo_start
+
4026 const_index
->u32
[0];
4027 surf_index
= brw_imm_ud(index
);
4028 brw_mark_surface_used(prog_data
, index
);
4030 /* The block index is not a constant. Evaluate the index expression
4031 * per-channel and add the base UBO index; we have to select a value
4032 * from any live channel.
4034 surf_index
= vgrf(glsl_type::uint_type
);
4035 bld
.ADD(surf_index
, get_nir_src(instr
->src
[0]),
4036 brw_imm_ud(stage_prog_data
->binding_table
.ubo_start
));
4037 surf_index
= bld
.emit_uniformize(surf_index
);
4039 /* Assume this may touch any UBO. It would be nice to provide
4040 * a tighter bound, but the array information is already lowered away.
4042 brw_mark_surface_used(prog_data
,
4043 stage_prog_data
->binding_table
.ubo_start
+
4044 nir
->info
.num_ubos
- 1);
4047 nir_const_value
*const_offset
= nir_src_as_const_value(instr
->src
[1]);
4048 if (const_offset
== NULL
) {
4049 fs_reg base_offset
= retype(get_nir_src(instr
->src
[1]),
4050 BRW_REGISTER_TYPE_UD
);
4052 for (int i
= 0; i
< instr
->num_components
; i
++)
4053 VARYING_PULL_CONSTANT_LOAD(bld
, offset(dest
, bld
, i
), surf_index
,
4054 base_offset
, i
* type_sz(dest
.type
));
4056 /* Even if we are loading doubles, a pull constant load will load
4057 * a 32-bit vec4, so should only reserve vgrf space for that. If we
4058 * need to load a full dvec4 we will have to emit 2 loads. This is
4059 * similar to demote_pull_constants(), except that in that case we
4060 * see individual accesses to each component of the vector and then
4061 * we let CSE deal with duplicate loads. Here we see a vector access
4062 * and we have to split it if necessary.
4064 const unsigned type_size
= type_sz(dest
.type
);
4066 /* See if we've selected this as a push constant candidate */
4068 const unsigned ubo_block
= const_index
->u32
[0];
4069 const unsigned offset_256b
= const_offset
->u32
[0] / 32;
4072 for (int i
= 0; i
< 4; i
++) {
4073 const struct brw_ubo_range
*range
= &prog_data
->ubo_ranges
[i
];
4074 if (range
->block
== ubo_block
&&
4075 offset_256b
>= range
->start
&&
4076 offset_256b
< range
->start
+ range
->length
) {
4078 push_reg
= fs_reg(UNIFORM
, UBO_START
+ i
, dest
.type
);
4079 push_reg
.offset
= const_offset
->u32
[0] - 32 * range
->start
;
4084 if (push_reg
.file
!= BAD_FILE
) {
4085 for (unsigned i
= 0; i
< instr
->num_components
; i
++) {
4086 bld
.MOV(offset(dest
, bld
, i
),
4087 byte_offset(push_reg
, i
* type_size
));
4093 const unsigned block_sz
= 64; /* Fetch one cacheline at a time. */
4094 const fs_builder ubld
= bld
.exec_all().group(block_sz
/ 4, 0);
4095 const fs_reg packed_consts
= ubld
.vgrf(BRW_REGISTER_TYPE_UD
);
4097 for (unsigned c
= 0; c
< instr
->num_components
;) {
4098 const unsigned base
= const_offset
->u32
[0] + c
* type_size
;
4099 /* Number of usable components in the next block-aligned load. */
4100 const unsigned count
= MIN2(instr
->num_components
- c
,
4101 (block_sz
- base
% block_sz
) / type_size
);
4103 ubld
.emit(FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD
,
4104 packed_consts
, surf_index
,
4105 brw_imm_ud(base
& ~(block_sz
- 1)));
4107 const fs_reg consts
=
4108 retype(byte_offset(packed_consts
, base
& (block_sz
- 1)),
4111 for (unsigned d
= 0; d
< count
; d
++)
4112 bld
.MOV(offset(dest
, bld
, c
+ d
), component(consts
, d
));
4120 case nir_intrinsic_load_ssbo
: {
4121 assert(devinfo
->gen
>= 7);
4123 nir_const_value
*const_uniform_block
=
4124 nir_src_as_const_value(instr
->src
[0]);
4127 if (const_uniform_block
) {
4128 unsigned index
= stage_prog_data
->binding_table
.ssbo_start
+
4129 const_uniform_block
->u32
[0];
4130 surf_index
= brw_imm_ud(index
);
4131 brw_mark_surface_used(prog_data
, index
);
4133 surf_index
= vgrf(glsl_type::uint_type
);
4134 bld
.ADD(surf_index
, get_nir_src(instr
->src
[0]),
4135 brw_imm_ud(stage_prog_data
->binding_table
.ssbo_start
));
4137 /* Assume this may touch any UBO. It would be nice to provide
4138 * a tighter bound, but the array information is already lowered away.
4140 brw_mark_surface_used(prog_data
,
4141 stage_prog_data
->binding_table
.ssbo_start
+
4142 nir
->info
.num_ssbos
- 1);
4146 nir_const_value
*const_offset
= nir_src_as_const_value(instr
->src
[1]);
4148 offset_reg
= brw_imm_ud(const_offset
->u32
[0]);
4150 offset_reg
= retype(get_nir_src(instr
->src
[1]), BRW_REGISTER_TYPE_UD
);
4153 /* Read the vector */
4154 do_untyped_vector_read(bld
, dest
, surf_index
, offset_reg
,
4155 instr
->num_components
);
4160 case nir_intrinsic_store_ssbo
: {
4161 assert(devinfo
->gen
>= 7);
4163 if (stage
== MESA_SHADER_FRAGMENT
)
4164 brw_wm_prog_data(prog_data
)->has_side_effects
= true;
4168 nir_const_value
*const_uniform_block
=
4169 nir_src_as_const_value(instr
->src
[1]);
4170 if (const_uniform_block
) {
4171 unsigned index
= stage_prog_data
->binding_table
.ssbo_start
+
4172 const_uniform_block
->u32
[0];
4173 surf_index
= brw_imm_ud(index
);
4174 brw_mark_surface_used(prog_data
, index
);
4176 surf_index
= vgrf(glsl_type::uint_type
);
4177 bld
.ADD(surf_index
, get_nir_src(instr
->src
[1]),
4178 brw_imm_ud(stage_prog_data
->binding_table
.ssbo_start
));
4180 brw_mark_surface_used(prog_data
,
4181 stage_prog_data
->binding_table
.ssbo_start
+
4182 nir
->info
.num_ssbos
- 1);
4186 fs_reg val_reg
= get_nir_src(instr
->src
[0]);
4189 unsigned writemask
= instr
->const_index
[0];
4191 /* get_nir_src() retypes to integer. Be wary of 64-bit types though
4192 * since the untyped writes below operate in units of 32-bits, which
4193 * means that we need to write twice as many components each time.
4194 * Also, we have to suffle 64-bit data to be in the appropriate layout
4195 * expected by our 32-bit write messages.
4197 unsigned bit_size
= nir_src_bit_size(instr
->src
[0]);
4198 unsigned type_size
= bit_size
/ 8;
4200 /* Combine groups of consecutive enabled channels in one write
4201 * message. We use ffs to find the first enabled channel and then ffs on
4202 * the bit-inverse, down-shifted writemask to determine the num_components
4203 * of the block of enabled bits.
4206 unsigned first_component
= ffs(writemask
) - 1;
4207 unsigned num_components
= ffs(~(writemask
>> first_component
)) - 1;
4208 fs_reg write_src
= offset(val_reg
, bld
, first_component
);
4210 nir_const_value
*const_offset
= nir_src_as_const_value(instr
->src
[2]);
4212 if (type_size
> 4) {
4213 /* We can't write more than 2 64-bit components at once. Limit
4214 * the num_components of the write to what we can do and let the next
4215 * iteration handle the rest.
4217 num_components
= MIN2(2, num_components
);
4218 write_src
= shuffle_64bit_data_for_32bit_write(bld
, write_src
,
4220 } else if (type_size
< 4) {
4221 assert(type_size
== 2);
4222 /* For 16-bit types we pack two consecutive values into a 32-bit
4223 * word and use an untyped write message. For single values or not
4224 * 32-bit-aligned we need to use byte-scattered writes because
4225 * untyped writes works with 32-bit components with 32-bit
4226 * alignment. byte_scattered_write messages only support one
4227 * 16-bit component at a time. As VK_KHR_relaxed_block_layout
4228 * could be enabled we can not guarantee that not constant offsets
4229 * to be 32-bit aligned for 16-bit types. For example an array, of
4230 * 16-bit vec3 with array element stride of 6.
4232 * In the case of 32-bit aligned constant offsets if there is
4233 * a 3-components vector we submit one untyped-write message
4234 * of 32-bit (first two components), and one byte-scattered
4235 * write message (the last component).
4238 if ( !const_offset
|| ((const_offset
->u32
[0] +
4239 type_size
* first_component
) % 4)) {
4240 /* If we use a .yz writemask we also need to emit 2
4241 * byte-scattered write messages because of y-component not
4242 * being aligned to 32-bit.
4245 } else if (num_components
> 2 && (num_components
% 2)) {
4246 /* If there is an odd number of consecutive components we left
4247 * the not paired component for a following emit of length == 1
4248 * with byte_scattered_write.
4252 /* For num_components == 1 we are also shuffling the component
4253 * because byte scattered writes of 16-bit need values to be dword
4254 * aligned. Shuffling only one component would be the same as
4257 fs_reg tmp
= bld
.vgrf(BRW_REGISTER_TYPE_D
,
4258 DIV_ROUND_UP(num_components
, 2));
4259 shuffle_16bit_data_for_32bit_write(bld
, tmp
, write_src
,
4267 offset_reg
= brw_imm_ud(const_offset
->u32
[0] +
4268 type_size
* first_component
);
4270 offset_reg
= vgrf(glsl_type::uint_type
);
4272 retype(get_nir_src(instr
->src
[2]), BRW_REGISTER_TYPE_UD
),
4273 brw_imm_ud(type_size
* first_component
));
4276 if (type_size
< 4 && num_components
== 1) {
4277 assert(type_size
== 2);
4278 /* Untyped Surface messages have a fixed 32-bit size, so we need
4279 * to rely on byte scattered in order to write 16-bit elements.
4280 * The byte_scattered_write message needs that every written 16-bit
4281 * type to be aligned 32-bits (stride=2).
4283 emit_byte_scattered_write(bld
, surf_index
, offset_reg
,
4287 BRW_PREDICATE_NONE
);
4289 assert(num_components
* type_size
<= 16);
4290 assert((num_components
* type_size
) % 4 == 0);
4291 assert(offset_reg
.file
!= BRW_IMMEDIATE_VALUE
||
4292 offset_reg
.ud
% 4 == 0);
4293 unsigned num_slots
= (num_components
* type_size
) / 4;
4295 emit_untyped_write(bld
, surf_index
, offset_reg
,
4297 1 /* dims */, num_slots
,
4298 BRW_PREDICATE_NONE
);
4301 /* Clear the bits in the writemask that we just wrote, then try
4302 * again to see if more channels are left.
4304 writemask
&= (15 << (first_component
+ num_components
));
4309 case nir_intrinsic_store_output
: {
4310 fs_reg src
= get_nir_src(instr
->src
[0]);
4312 nir_const_value
*const_offset
= nir_src_as_const_value(instr
->src
[1]);
4313 assert(const_offset
&& "Indirect output stores not allowed");
4315 unsigned num_components
= instr
->num_components
;
4316 unsigned first_component
= nir_intrinsic_component(instr
);
4317 if (nir_src_bit_size(instr
->src
[0]) == 64) {
4318 src
= shuffle_64bit_data_for_32bit_write(bld
, src
, num_components
);
4319 num_components
*= 2;
4322 fs_reg new_dest
= retype(offset(outputs
[instr
->const_index
[0]], bld
,
4323 4 * const_offset
->u32
[0]), src
.type
);
4324 for (unsigned j
= 0; j
< num_components
; j
++) {
4325 bld
.MOV(offset(new_dest
, bld
, j
+ first_component
),
4326 offset(src
, bld
, j
));
4331 case nir_intrinsic_ssbo_atomic_add
:
4332 nir_emit_ssbo_atomic(bld
, BRW_AOP_ADD
, instr
);
4334 case nir_intrinsic_ssbo_atomic_imin
:
4335 nir_emit_ssbo_atomic(bld
, BRW_AOP_IMIN
, instr
);
4337 case nir_intrinsic_ssbo_atomic_umin
:
4338 nir_emit_ssbo_atomic(bld
, BRW_AOP_UMIN
, instr
);
4340 case nir_intrinsic_ssbo_atomic_imax
:
4341 nir_emit_ssbo_atomic(bld
, BRW_AOP_IMAX
, instr
);
4343 case nir_intrinsic_ssbo_atomic_umax
:
4344 nir_emit_ssbo_atomic(bld
, BRW_AOP_UMAX
, instr
);
4346 case nir_intrinsic_ssbo_atomic_and
:
4347 nir_emit_ssbo_atomic(bld
, BRW_AOP_AND
, instr
);
4349 case nir_intrinsic_ssbo_atomic_or
:
4350 nir_emit_ssbo_atomic(bld
, BRW_AOP_OR
, instr
);
4352 case nir_intrinsic_ssbo_atomic_xor
:
4353 nir_emit_ssbo_atomic(bld
, BRW_AOP_XOR
, instr
);
4355 case nir_intrinsic_ssbo_atomic_exchange
:
4356 nir_emit_ssbo_atomic(bld
, BRW_AOP_MOV
, instr
);
4358 case nir_intrinsic_ssbo_atomic_comp_swap
:
4359 nir_emit_ssbo_atomic(bld
, BRW_AOP_CMPWR
, instr
);
4362 case nir_intrinsic_get_buffer_size
: {
4363 nir_const_value
*const_uniform_block
= nir_src_as_const_value(instr
->src
[0]);
4364 unsigned ssbo_index
= const_uniform_block
? const_uniform_block
->u32
[0] : 0;
4366 /* A resinfo's sampler message is used to get the buffer size. The
4367 * SIMD8's writeback message consists of four registers and SIMD16's
4368 * writeback message consists of 8 destination registers (two per each
4369 * component). Because we are only interested on the first channel of
4370 * the first returned component, where resinfo returns the buffer size
4371 * for SURFTYPE_BUFFER, we can just use the SIMD8 variant regardless of
4372 * the dispatch width.
4374 const fs_builder ubld
= bld
.exec_all().group(8, 0);
4375 fs_reg src_payload
= ubld
.vgrf(BRW_REGISTER_TYPE_UD
);
4376 fs_reg ret_payload
= ubld
.vgrf(BRW_REGISTER_TYPE_UD
, 4);
4379 ubld
.MOV(src_payload
, brw_imm_d(0));
4381 const unsigned index
= prog_data
->binding_table
.ssbo_start
+ ssbo_index
;
4382 fs_inst
*inst
= ubld
.emit(SHADER_OPCODE_GET_BUFFER_SIZE
, ret_payload
,
4383 src_payload
, brw_imm_ud(index
));
4384 inst
->header_size
= 0;
4386 inst
->size_written
= 4 * REG_SIZE
;
4388 /* SKL PRM, vol07, 3D Media GPGPU Engine, Bounds Checking and Faulting:
4390 * "Out-of-bounds checking is always performed at a DWord granularity. If
4391 * any part of the DWord is out-of-bounds then the whole DWord is
4392 * considered out-of-bounds."
4394 * This implies that types with size smaller than 4-bytes need to be
4395 * padded if they don't complete the last dword of the buffer. But as we
4396 * need to maintain the original size we need to reverse the padding
4397 * calculation to return the correct size to know the number of elements
4398 * of an unsized array. As we stored in the last two bits of the surface
4399 * size the needed padding for the buffer, we calculate here the
4400 * original buffer_size reversing the surface_size calculation:
4402 * surface_size = isl_align(buffer_size, 4) +
4403 * (isl_align(buffer_size) - buffer_size)
4405 * buffer_size = surface_size & ~3 - surface_size & 3
4408 fs_reg size_aligned4
= ubld
.vgrf(BRW_REGISTER_TYPE_UD
);
4409 fs_reg size_padding
= ubld
.vgrf(BRW_REGISTER_TYPE_UD
);
4410 fs_reg buffer_size
= ubld
.vgrf(BRW_REGISTER_TYPE_UD
);
4412 ubld
.AND(size_padding
, ret_payload
, brw_imm_ud(3));
4413 ubld
.AND(size_aligned4
, ret_payload
, brw_imm_ud(~3));
4414 ubld
.ADD(buffer_size
, size_aligned4
, negate(size_padding
));
4416 bld
.MOV(retype(dest
, ret_payload
.type
), component(buffer_size
, 0));
4418 brw_mark_surface_used(prog_data
, index
);
4422 case nir_intrinsic_load_subgroup_invocation
:
4423 bld
.MOV(retype(dest
, BRW_REGISTER_TYPE_D
),
4424 nir_system_values
[SYSTEM_VALUE_SUBGROUP_INVOCATION
]);
4427 case nir_intrinsic_load_subgroup_eq_mask
:
4428 case nir_intrinsic_load_subgroup_ge_mask
:
4429 case nir_intrinsic_load_subgroup_gt_mask
:
4430 case nir_intrinsic_load_subgroup_le_mask
:
4431 case nir_intrinsic_load_subgroup_lt_mask
:
4432 unreachable("not reached");
4434 case nir_intrinsic_vote_any
: {
4435 const fs_builder ubld
= bld
.exec_all().group(1, 0);
4437 /* The any/all predicates do not consider channel enables. To prevent
4438 * dead channels from affecting the result, we initialize the flag with
4439 * with the identity value for the logical operation.
4441 if (dispatch_width
== 32) {
4442 /* For SIMD32, we use a UD type so we fill both f0.0 and f0.1. */
4443 ubld
.MOV(retype(brw_flag_reg(0, 0), BRW_REGISTER_TYPE_UD
),
4446 ubld
.MOV(brw_flag_reg(0, 0), brw_imm_uw(0));
4448 bld
.CMP(bld
.null_reg_d(), get_nir_src(instr
->src
[0]), brw_imm_d(0), BRW_CONDITIONAL_NZ
);
4450 /* For some reason, the any/all predicates don't work properly with
4451 * SIMD32. In particular, it appears that a SEL with a QtrCtrl of 2H
4452 * doesn't read the correct subset of the flag register and you end up
4453 * getting garbage in the second half. Work around this by using a pair
4454 * of 1-wide MOVs and scattering the result.
4456 fs_reg res1
= ubld
.vgrf(BRW_REGISTER_TYPE_D
);
4457 ubld
.MOV(res1
, brw_imm_d(0));
4458 set_predicate(dispatch_width
== 8 ? BRW_PREDICATE_ALIGN1_ANY8H
:
4459 dispatch_width
== 16 ? BRW_PREDICATE_ALIGN1_ANY16H
:
4460 BRW_PREDICATE_ALIGN1_ANY32H
,
4461 ubld
.MOV(res1
, brw_imm_d(-1)));
4463 bld
.MOV(retype(dest
, BRW_REGISTER_TYPE_D
), component(res1
, 0));
4466 case nir_intrinsic_vote_all
: {
4467 const fs_builder ubld
= bld
.exec_all().group(1, 0);
4469 /* The any/all predicates do not consider channel enables. To prevent
4470 * dead channels from affecting the result, we initialize the flag with
4471 * with the identity value for the logical operation.
4473 if (dispatch_width
== 32) {
4474 /* For SIMD32, we use a UD type so we fill both f0.0 and f0.1. */
4475 ubld
.MOV(retype(brw_flag_reg(0, 0), BRW_REGISTER_TYPE_UD
),
4476 brw_imm_ud(0xffffffff));
4478 ubld
.MOV(brw_flag_reg(0, 0), brw_imm_uw(0xffff));
4480 bld
.CMP(bld
.null_reg_d(), get_nir_src(instr
->src
[0]), brw_imm_d(0), BRW_CONDITIONAL_NZ
);
4482 /* For some reason, the any/all predicates don't work properly with
4483 * SIMD32. In particular, it appears that a SEL with a QtrCtrl of 2H
4484 * doesn't read the correct subset of the flag register and you end up
4485 * getting garbage in the second half. Work around this by using a pair
4486 * of 1-wide MOVs and scattering the result.
4488 fs_reg res1
= ubld
.vgrf(BRW_REGISTER_TYPE_D
);
4489 ubld
.MOV(res1
, brw_imm_d(0));
4490 set_predicate(dispatch_width
== 8 ? BRW_PREDICATE_ALIGN1_ALL8H
:
4491 dispatch_width
== 16 ? BRW_PREDICATE_ALIGN1_ALL16H
:
4492 BRW_PREDICATE_ALIGN1_ALL32H
,
4493 ubld
.MOV(res1
, brw_imm_d(-1)));
4495 bld
.MOV(retype(dest
, BRW_REGISTER_TYPE_D
), component(res1
, 0));
4498 case nir_intrinsic_vote_feq
:
4499 case nir_intrinsic_vote_ieq
: {
4500 fs_reg value
= get_nir_src(instr
->src
[0]);
4501 if (instr
->intrinsic
== nir_intrinsic_vote_feq
) {
4502 const unsigned bit_size
= nir_src_bit_size(instr
->src
[0]);
4503 value
.type
= brw_reg_type_from_bit_size(bit_size
, BRW_REGISTER_TYPE_F
);
4506 fs_reg uniformized
= bld
.emit_uniformize(value
);
4507 const fs_builder ubld
= bld
.exec_all().group(1, 0);
4509 /* The any/all predicates do not consider channel enables. To prevent
4510 * dead channels from affecting the result, we initialize the flag with
4511 * with the identity value for the logical operation.
4513 if (dispatch_width
== 32) {
4514 /* For SIMD32, we use a UD type so we fill both f0.0 and f0.1. */
4515 ubld
.MOV(retype(brw_flag_reg(0, 0), BRW_REGISTER_TYPE_UD
),
4516 brw_imm_ud(0xffffffff));
4518 ubld
.MOV(brw_flag_reg(0, 0), brw_imm_uw(0xffff));
4520 bld
.CMP(bld
.null_reg_d(), value
, uniformized
, BRW_CONDITIONAL_Z
);
4522 /* For some reason, the any/all predicates don't work properly with
4523 * SIMD32. In particular, it appears that a SEL with a QtrCtrl of 2H
4524 * doesn't read the correct subset of the flag register and you end up
4525 * getting garbage in the second half. Work around this by using a pair
4526 * of 1-wide MOVs and scattering the result.
4528 fs_reg res1
= ubld
.vgrf(BRW_REGISTER_TYPE_D
);
4529 ubld
.MOV(res1
, brw_imm_d(0));
4530 set_predicate(dispatch_width
== 8 ? BRW_PREDICATE_ALIGN1_ALL8H
:
4531 dispatch_width
== 16 ? BRW_PREDICATE_ALIGN1_ALL16H
:
4532 BRW_PREDICATE_ALIGN1_ALL32H
,
4533 ubld
.MOV(res1
, brw_imm_d(-1)));
4535 bld
.MOV(retype(dest
, BRW_REGISTER_TYPE_D
), component(res1
, 0));
4539 case nir_intrinsic_ballot
: {
4540 const fs_reg value
= retype(get_nir_src(instr
->src
[0]),
4541 BRW_REGISTER_TYPE_UD
);
4542 struct brw_reg flag
= brw_flag_reg(0, 0);
4543 /* FIXME: For SIMD32 programs, this causes us to stomp on f0.1 as well
4544 * as f0.0. This is a problem for fragment programs as we currently use
4545 * f0.1 for discards. Fortunately, we don't support SIMD32 fragment
4546 * programs yet so this isn't a problem. When we do, something will
4549 if (dispatch_width
== 32)
4550 flag
.type
= BRW_REGISTER_TYPE_UD
;
4552 bld
.exec_all().group(1, 0).MOV(flag
, brw_imm_ud(0u));
4553 bld
.CMP(bld
.null_reg_ud(), value
, brw_imm_ud(0u), BRW_CONDITIONAL_NZ
);
4555 if (instr
->dest
.ssa
.bit_size
> 32) {
4556 dest
.type
= BRW_REGISTER_TYPE_UQ
;
4558 dest
.type
= BRW_REGISTER_TYPE_UD
;
4560 bld
.MOV(dest
, flag
);
4564 case nir_intrinsic_read_invocation
: {
4565 const fs_reg value
= get_nir_src(instr
->src
[0]);
4566 const fs_reg invocation
= get_nir_src(instr
->src
[1]);
4567 fs_reg tmp
= bld
.vgrf(value
.type
);
4569 bld
.exec_all().emit(SHADER_OPCODE_BROADCAST
, tmp
, value
,
4570 bld
.emit_uniformize(invocation
));
4572 bld
.MOV(retype(dest
, value
.type
), fs_reg(component(tmp
, 0)));
4576 case nir_intrinsic_read_first_invocation
: {
4577 const fs_reg value
= get_nir_src(instr
->src
[0]);
4578 bld
.MOV(retype(dest
, value
.type
), bld
.emit_uniformize(value
));
4582 case nir_intrinsic_shuffle
: {
4583 const fs_reg value
= get_nir_src(instr
->src
[0]);
4584 const fs_reg index
= get_nir_src(instr
->src
[1]);
4586 bld
.emit(SHADER_OPCODE_SHUFFLE
, retype(dest
, value
.type
), value
, index
);
4590 case nir_intrinsic_first_invocation
: {
4591 fs_reg tmp
= bld
.vgrf(BRW_REGISTER_TYPE_UD
);
4592 bld
.exec_all().emit(SHADER_OPCODE_FIND_LIVE_CHANNEL
, tmp
);
4593 bld
.MOV(retype(dest
, BRW_REGISTER_TYPE_UD
),
4594 fs_reg(component(tmp
, 0)));
4598 case nir_intrinsic_quad_broadcast
: {
4599 const fs_reg value
= get_nir_src(instr
->src
[0]);
4600 nir_const_value
*index
= nir_src_as_const_value(instr
->src
[1]);
4601 assert(nir_src_bit_size(instr
->src
[1]) == 32);
4603 bld
.emit(SHADER_OPCODE_CLUSTER_BROADCAST
, retype(dest
, value
.type
),
4604 value
, brw_imm_ud(index
->u32
[0]), brw_imm_ud(4));
4608 case nir_intrinsic_quad_swap_horizontal
: {
4609 const fs_reg value
= get_nir_src(instr
->src
[0]);
4610 const fs_reg tmp
= bld
.vgrf(value
.type
);
4611 const fs_builder ubld
= bld
.exec_all().group(dispatch_width
/ 2, 0);
4613 const fs_reg src_left
= horiz_stride(value
, 2);
4614 const fs_reg src_right
= horiz_stride(horiz_offset(value
, 1), 2);
4615 const fs_reg tmp_left
= horiz_stride(tmp
, 2);
4616 const fs_reg tmp_right
= horiz_stride(horiz_offset(tmp
, 1), 2);
4618 /* From the Cherryview PRM Vol. 7, "Register Region Restrictiosn":
4620 * "When source or destination datatype is 64b or operation is
4621 * integer DWord multiply, regioning in Align1 must follow
4626 * 3. Source and Destination offset must be the same, except
4627 * the case of scalar source."
4629 * In order to work around this, we have to emit two 32-bit MOVs instead
4630 * of a single 64-bit MOV to do the shuffle.
4632 if (type_sz(value
.type
) > 4 &&
4633 (devinfo
->is_cherryview
|| gen_device_info_is_9lp(devinfo
))) {
4634 ubld
.MOV(subscript(tmp_left
, BRW_REGISTER_TYPE_D
, 0),
4635 subscript(src_right
, BRW_REGISTER_TYPE_D
, 0));
4636 ubld
.MOV(subscript(tmp_left
, BRW_REGISTER_TYPE_D
, 1),
4637 subscript(src_right
, BRW_REGISTER_TYPE_D
, 1));
4638 ubld
.MOV(subscript(tmp_right
, BRW_REGISTER_TYPE_D
, 0),
4639 subscript(src_left
, BRW_REGISTER_TYPE_D
, 0));
4640 ubld
.MOV(subscript(tmp_right
, BRW_REGISTER_TYPE_D
, 1),
4641 subscript(src_left
, BRW_REGISTER_TYPE_D
, 1));
4643 ubld
.MOV(tmp_left
, src_right
);
4644 ubld
.MOV(tmp_right
, src_left
);
4646 bld
.MOV(retype(dest
, value
.type
), tmp
);
4650 case nir_intrinsic_quad_swap_vertical
: {
4651 const fs_reg value
= get_nir_src(instr
->src
[0]);
4652 if (nir_src_bit_size(instr
->src
[0]) == 32) {
4653 /* For 32-bit, we can use a SIMD4x2 instruction to do this easily */
4654 const fs_reg tmp
= bld
.vgrf(value
.type
);
4655 const fs_builder ubld
= bld
.exec_all();
4656 ubld
.emit(SHADER_OPCODE_QUAD_SWIZZLE
, tmp
, value
,
4657 brw_imm_ud(BRW_SWIZZLE4(2,3,0,1)));
4658 bld
.MOV(retype(dest
, value
.type
), tmp
);
4660 /* For larger data types, we have to either emit dispatch_width many
4661 * MOVs or else fall back to doing indirects.
4663 fs_reg idx
= bld
.vgrf(BRW_REGISTER_TYPE_W
);
4664 bld
.XOR(idx
, nir_system_values
[SYSTEM_VALUE_SUBGROUP_INVOCATION
],
4666 bld
.emit(SHADER_OPCODE_SHUFFLE
, retype(dest
, value
.type
), value
, idx
);
4671 case nir_intrinsic_quad_swap_diagonal
: {
4672 const fs_reg value
= get_nir_src(instr
->src
[0]);
4673 if (nir_src_bit_size(instr
->src
[0]) == 32) {
4674 /* For 32-bit, we can use a SIMD4x2 instruction to do this easily */
4675 const fs_reg tmp
= bld
.vgrf(value
.type
);
4676 const fs_builder ubld
= bld
.exec_all();
4677 ubld
.emit(SHADER_OPCODE_QUAD_SWIZZLE
, tmp
, value
,
4678 brw_imm_ud(BRW_SWIZZLE4(3,2,1,0)));
4679 bld
.MOV(retype(dest
, value
.type
), tmp
);
4681 /* For larger data types, we have to either emit dispatch_width many
4682 * MOVs or else fall back to doing indirects.
4684 fs_reg idx
= bld
.vgrf(BRW_REGISTER_TYPE_W
);
4685 bld
.XOR(idx
, nir_system_values
[SYSTEM_VALUE_SUBGROUP_INVOCATION
],
4687 bld
.emit(SHADER_OPCODE_SHUFFLE
, retype(dest
, value
.type
), value
, idx
);
4692 case nir_intrinsic_reduce
: {
4693 fs_reg src
= get_nir_src(instr
->src
[0]);
4694 nir_op redop
= (nir_op
)nir_intrinsic_reduction_op(instr
);
4695 unsigned cluster_size
= nir_intrinsic_cluster_size(instr
);
4696 if (cluster_size
== 0 || cluster_size
> dispatch_width
)
4697 cluster_size
= dispatch_width
;
4699 /* Figure out the source type */
4700 src
.type
= brw_type_for_nir_type(devinfo
,
4701 (nir_alu_type
)(nir_op_infos
[redop
].input_types
[0] |
4702 nir_src_bit_size(instr
->src
[0])));
4704 fs_reg identity
= brw_nir_reduction_op_identity(bld
, redop
, src
.type
);
4705 opcode brw_op
= brw_op_for_nir_reduction_op(redop
);
4706 brw_conditional_mod cond_mod
= brw_cond_mod_for_nir_reduction_op(redop
);
4708 /* Set up a register for all of our scratching around and initialize it
4709 * to reduction operation's identity value.
4711 fs_reg scan
= bld
.vgrf(src
.type
);
4712 bld
.exec_all().emit(SHADER_OPCODE_SEL_EXEC
, scan
, src
, identity
);
4714 bld
.emit_scan(brw_op
, scan
, cluster_size
, cond_mod
);
4716 dest
.type
= src
.type
;
4717 if (cluster_size
* type_sz(src
.type
) >= REG_SIZE
* 2) {
4718 /* In this case, CLUSTER_BROADCAST instruction isn't needed because
4719 * the distance between clusters is at least 2 GRFs. In this case,
4720 * we don't need the weird striding of the CLUSTER_BROADCAST
4721 * instruction and can just do regular MOVs.
4723 assert((cluster_size
* type_sz(src
.type
)) % (REG_SIZE
* 2) == 0);
4724 const unsigned groups
=
4725 (dispatch_width
* type_sz(src
.type
)) / (REG_SIZE
* 2);
4726 const unsigned group_size
= dispatch_width
/ groups
;
4727 for (unsigned i
= 0; i
< groups
; i
++) {
4728 const unsigned cluster
= (i
* group_size
) / cluster_size
;
4729 const unsigned comp
= cluster
* cluster_size
+ (cluster_size
- 1);
4730 bld
.group(group_size
, i
).MOV(horiz_offset(dest
, i
* group_size
),
4731 component(scan
, comp
));
4734 bld
.emit(SHADER_OPCODE_CLUSTER_BROADCAST
, dest
, scan
,
4735 brw_imm_ud(cluster_size
- 1), brw_imm_ud(cluster_size
));
4740 case nir_intrinsic_inclusive_scan
:
4741 case nir_intrinsic_exclusive_scan
: {
4742 fs_reg src
= get_nir_src(instr
->src
[0]);
4743 nir_op redop
= (nir_op
)nir_intrinsic_reduction_op(instr
);
4745 /* Figure out the source type */
4746 src
.type
= brw_type_for_nir_type(devinfo
,
4747 (nir_alu_type
)(nir_op_infos
[redop
].input_types
[0] |
4748 nir_src_bit_size(instr
->src
[0])));
4750 fs_reg identity
= brw_nir_reduction_op_identity(bld
, redop
, src
.type
);
4751 opcode brw_op
= brw_op_for_nir_reduction_op(redop
);
4752 brw_conditional_mod cond_mod
= brw_cond_mod_for_nir_reduction_op(redop
);
4754 /* Set up a register for all of our scratching around and initialize it
4755 * to reduction operation's identity value.
4757 fs_reg scan
= bld
.vgrf(src
.type
);
4758 const fs_builder allbld
= bld
.exec_all();
4759 allbld
.emit(SHADER_OPCODE_SEL_EXEC
, scan
, src
, identity
);
4761 if (instr
->intrinsic
== nir_intrinsic_exclusive_scan
) {
4762 /* Exclusive scan is a bit harder because we have to do an annoying
4763 * shift of the contents before we can begin. To make things worse,
4764 * we can't do this with a normal stride; we have to use indirects.
4766 fs_reg shifted
= bld
.vgrf(src
.type
);
4767 fs_reg idx
= bld
.vgrf(BRW_REGISTER_TYPE_W
);
4768 allbld
.ADD(idx
, nir_system_values
[SYSTEM_VALUE_SUBGROUP_INVOCATION
],
4770 allbld
.emit(SHADER_OPCODE_SHUFFLE
, shifted
, scan
, idx
);
4771 allbld
.group(1, 0).MOV(component(shifted
, 0), identity
);
4775 bld
.emit_scan(brw_op
, scan
, dispatch_width
, cond_mod
);
4777 bld
.MOV(retype(dest
, src
.type
), scan
);
4782 unreachable("unknown intrinsic");
4787 fs_visitor::nir_emit_ssbo_atomic(const fs_builder
&bld
,
4788 int op
, nir_intrinsic_instr
*instr
)
4790 if (stage
== MESA_SHADER_FRAGMENT
)
4791 brw_wm_prog_data(prog_data
)->has_side_effects
= true;
4794 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
4795 dest
= get_nir_dest(instr
->dest
);
4798 nir_const_value
*const_surface
= nir_src_as_const_value(instr
->src
[0]);
4799 if (const_surface
) {
4800 unsigned surf_index
= stage_prog_data
->binding_table
.ssbo_start
+
4801 const_surface
->u32
[0];
4802 surface
= brw_imm_ud(surf_index
);
4803 brw_mark_surface_used(prog_data
, surf_index
);
4805 surface
= vgrf(glsl_type::uint_type
);
4806 bld
.ADD(surface
, get_nir_src(instr
->src
[0]),
4807 brw_imm_ud(stage_prog_data
->binding_table
.ssbo_start
));
4809 /* Assume this may touch any SSBO. This is the same we do for other
4810 * UBO/SSBO accesses with non-constant surface.
4812 brw_mark_surface_used(prog_data
,
4813 stage_prog_data
->binding_table
.ssbo_start
+
4814 nir
->info
.num_ssbos
- 1);
4817 fs_reg offset
= get_nir_src(instr
->src
[1]);
4818 fs_reg data1
= get_nir_src(instr
->src
[2]);
4820 if (op
== BRW_AOP_CMPWR
)
4821 data2
= get_nir_src(instr
->src
[3]);
4823 /* Emit the actual atomic operation */
4825 fs_reg atomic_result
= emit_untyped_atomic(bld
, surface
, offset
,
4827 1 /* dims */, 1 /* rsize */,
4829 BRW_PREDICATE_NONE
);
4830 dest
.type
= atomic_result
.type
;
4831 bld
.MOV(dest
, atomic_result
);
4835 fs_visitor::nir_emit_shared_atomic(const fs_builder
&bld
,
4836 int op
, nir_intrinsic_instr
*instr
)
4839 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
4840 dest
= get_nir_dest(instr
->dest
);
4842 fs_reg surface
= brw_imm_ud(GEN7_BTI_SLM
);
4844 fs_reg data1
= get_nir_src(instr
->src
[1]);
4846 if (op
== BRW_AOP_CMPWR
)
4847 data2
= get_nir_src(instr
->src
[2]);
4849 /* Get the offset */
4850 nir_const_value
*const_offset
= nir_src_as_const_value(instr
->src
[0]);
4852 offset
= brw_imm_ud(instr
->const_index
[0] + const_offset
->u32
[0]);
4854 offset
= vgrf(glsl_type::uint_type
);
4856 retype(get_nir_src(instr
->src
[0]), BRW_REGISTER_TYPE_UD
),
4857 brw_imm_ud(instr
->const_index
[0]));
4860 /* Emit the actual atomic operation operation */
4862 fs_reg atomic_result
= emit_untyped_atomic(bld
, surface
, offset
,
4864 1 /* dims */, 1 /* rsize */,
4866 BRW_PREDICATE_NONE
);
4867 dest
.type
= atomic_result
.type
;
4868 bld
.MOV(dest
, atomic_result
);
4872 fs_visitor::nir_emit_texture(const fs_builder
&bld
, nir_tex_instr
*instr
)
4874 unsigned texture
= instr
->texture_index
;
4875 unsigned sampler
= instr
->sampler_index
;
4877 fs_reg srcs
[TEX_LOGICAL_NUM_SRCS
];
4879 srcs
[TEX_LOGICAL_SRC_SURFACE
] = brw_imm_ud(texture
);
4880 srcs
[TEX_LOGICAL_SRC_SAMPLER
] = brw_imm_ud(sampler
);
4882 int lod_components
= 0;
4884 /* The hardware requires a LOD for buffer textures */
4885 if (instr
->sampler_dim
== GLSL_SAMPLER_DIM_BUF
)
4886 srcs
[TEX_LOGICAL_SRC_LOD
] = brw_imm_d(0);
4888 uint32_t header_bits
= 0;
4889 for (unsigned i
= 0; i
< instr
->num_srcs
; i
++) {
4890 fs_reg src
= get_nir_src(instr
->src
[i
].src
);
4891 switch (instr
->src
[i
].src_type
) {
4892 case nir_tex_src_bias
:
4893 srcs
[TEX_LOGICAL_SRC_LOD
] =
4894 retype(get_nir_src_imm(instr
->src
[i
].src
), BRW_REGISTER_TYPE_F
);
4896 case nir_tex_src_comparator
:
4897 srcs
[TEX_LOGICAL_SRC_SHADOW_C
] = retype(src
, BRW_REGISTER_TYPE_F
);
4899 case nir_tex_src_coord
:
4900 switch (instr
->op
) {
4902 case nir_texop_txf_ms
:
4903 case nir_texop_txf_ms_mcs
:
4904 case nir_texop_samples_identical
:
4905 srcs
[TEX_LOGICAL_SRC_COORDINATE
] = retype(src
, BRW_REGISTER_TYPE_D
);
4908 srcs
[TEX_LOGICAL_SRC_COORDINATE
] = retype(src
, BRW_REGISTER_TYPE_F
);
4912 case nir_tex_src_ddx
:
4913 srcs
[TEX_LOGICAL_SRC_LOD
] = retype(src
, BRW_REGISTER_TYPE_F
);
4914 lod_components
= nir_tex_instr_src_size(instr
, i
);
4916 case nir_tex_src_ddy
:
4917 srcs
[TEX_LOGICAL_SRC_LOD2
] = retype(src
, BRW_REGISTER_TYPE_F
);
4919 case nir_tex_src_lod
:
4920 switch (instr
->op
) {
4922 srcs
[TEX_LOGICAL_SRC_LOD
] =
4923 retype(get_nir_src_imm(instr
->src
[i
].src
), BRW_REGISTER_TYPE_UD
);
4926 srcs
[TEX_LOGICAL_SRC_LOD
] =
4927 retype(get_nir_src_imm(instr
->src
[i
].src
), BRW_REGISTER_TYPE_D
);
4930 srcs
[TEX_LOGICAL_SRC_LOD
] =
4931 retype(get_nir_src_imm(instr
->src
[i
].src
), BRW_REGISTER_TYPE_F
);
4935 case nir_tex_src_ms_index
:
4936 srcs
[TEX_LOGICAL_SRC_SAMPLE_INDEX
] = retype(src
, BRW_REGISTER_TYPE_UD
);
4939 case nir_tex_src_offset
: {
4940 nir_const_value
*const_offset
=
4941 nir_src_as_const_value(instr
->src
[i
].src
);
4942 unsigned offset_bits
= 0;
4944 brw_texture_offset(const_offset
->i32
,
4945 nir_tex_instr_src_size(instr
, i
),
4947 header_bits
|= offset_bits
;
4949 srcs
[TEX_LOGICAL_SRC_TG4_OFFSET
] =
4950 retype(src
, BRW_REGISTER_TYPE_D
);
4955 case nir_tex_src_projector
:
4956 unreachable("should be lowered");
4958 case nir_tex_src_texture_offset
: {
4959 /* Figure out the highest possible texture index and mark it as used */
4960 uint32_t max_used
= texture
+ instr
->texture_array_size
- 1;
4961 if (instr
->op
== nir_texop_tg4
&& devinfo
->gen
< 8) {
4962 max_used
+= stage_prog_data
->binding_table
.gather_texture_start
;
4964 max_used
+= stage_prog_data
->binding_table
.texture_start
;
4966 brw_mark_surface_used(prog_data
, max_used
);
4968 /* Emit code to evaluate the actual indexing expression */
4969 fs_reg tmp
= vgrf(glsl_type::uint_type
);
4970 bld
.ADD(tmp
, src
, brw_imm_ud(texture
));
4971 srcs
[TEX_LOGICAL_SRC_SURFACE
] = bld
.emit_uniformize(tmp
);
4975 case nir_tex_src_sampler_offset
: {
4976 /* Emit code to evaluate the actual indexing expression */
4977 fs_reg tmp
= vgrf(glsl_type::uint_type
);
4978 bld
.ADD(tmp
, src
, brw_imm_ud(sampler
));
4979 srcs
[TEX_LOGICAL_SRC_SAMPLER
] = bld
.emit_uniformize(tmp
);
4983 case nir_tex_src_ms_mcs
:
4984 assert(instr
->op
== nir_texop_txf_ms
);
4985 srcs
[TEX_LOGICAL_SRC_MCS
] = retype(src
, BRW_REGISTER_TYPE_D
);
4988 case nir_tex_src_plane
: {
4989 nir_const_value
*const_plane
=
4990 nir_src_as_const_value(instr
->src
[i
].src
);
4991 const uint32_t plane
= const_plane
->u32
[0];
4992 const uint32_t texture_index
=
4993 instr
->texture_index
+
4994 stage_prog_data
->binding_table
.plane_start
[plane
] -
4995 stage_prog_data
->binding_table
.texture_start
;
4997 srcs
[TEX_LOGICAL_SRC_SURFACE
] = brw_imm_ud(texture_index
);
5002 unreachable("unknown texture source");
5006 if (srcs
[TEX_LOGICAL_SRC_MCS
].file
== BAD_FILE
&&
5007 (instr
->op
== nir_texop_txf_ms
||
5008 instr
->op
== nir_texop_samples_identical
)) {
5009 if (devinfo
->gen
>= 7 &&
5010 key_tex
->compressed_multisample_layout_mask
& (1 << texture
)) {
5011 srcs
[TEX_LOGICAL_SRC_MCS
] =
5012 emit_mcs_fetch(srcs
[TEX_LOGICAL_SRC_COORDINATE
],
5013 instr
->coord_components
,
5014 srcs
[TEX_LOGICAL_SRC_SURFACE
]);
5016 srcs
[TEX_LOGICAL_SRC_MCS
] = brw_imm_ud(0u);
5020 srcs
[TEX_LOGICAL_SRC_COORD_COMPONENTS
] = brw_imm_d(instr
->coord_components
);
5021 srcs
[TEX_LOGICAL_SRC_GRAD_COMPONENTS
] = brw_imm_d(lod_components
);
5024 switch (instr
->op
) {
5026 opcode
= (stage
== MESA_SHADER_FRAGMENT
? SHADER_OPCODE_TEX_LOGICAL
:
5027 SHADER_OPCODE_TXL_LOGICAL
);
5030 opcode
= FS_OPCODE_TXB_LOGICAL
;
5033 opcode
= SHADER_OPCODE_TXL_LOGICAL
;
5036 opcode
= SHADER_OPCODE_TXD_LOGICAL
;
5039 opcode
= SHADER_OPCODE_TXF_LOGICAL
;
5041 case nir_texop_txf_ms
:
5042 if ((key_tex
->msaa_16
& (1 << sampler
)))
5043 opcode
= SHADER_OPCODE_TXF_CMS_W_LOGICAL
;
5045 opcode
= SHADER_OPCODE_TXF_CMS_LOGICAL
;
5047 case nir_texop_txf_ms_mcs
:
5048 opcode
= SHADER_OPCODE_TXF_MCS_LOGICAL
;
5050 case nir_texop_query_levels
:
5052 opcode
= SHADER_OPCODE_TXS_LOGICAL
;
5055 opcode
= SHADER_OPCODE_LOD_LOGICAL
;
5058 if (srcs
[TEX_LOGICAL_SRC_TG4_OFFSET
].file
!= BAD_FILE
)
5059 opcode
= SHADER_OPCODE_TG4_OFFSET_LOGICAL
;
5061 opcode
= SHADER_OPCODE_TG4_LOGICAL
;
5063 case nir_texop_texture_samples
:
5064 opcode
= SHADER_OPCODE_SAMPLEINFO_LOGICAL
;
5066 case nir_texop_samples_identical
: {
5067 fs_reg dst
= retype(get_nir_dest(instr
->dest
), BRW_REGISTER_TYPE_D
);
5069 /* If mcs is an immediate value, it means there is no MCS. In that case
5070 * just return false.
5072 if (srcs
[TEX_LOGICAL_SRC_MCS
].file
== BRW_IMMEDIATE_VALUE
) {
5073 bld
.MOV(dst
, brw_imm_ud(0u));
5074 } else if ((key_tex
->msaa_16
& (1 << sampler
))) {
5075 fs_reg tmp
= vgrf(glsl_type::uint_type
);
5076 bld
.OR(tmp
, srcs
[TEX_LOGICAL_SRC_MCS
],
5077 offset(srcs
[TEX_LOGICAL_SRC_MCS
], bld
, 1));
5078 bld
.CMP(dst
, tmp
, brw_imm_ud(0u), BRW_CONDITIONAL_EQ
);
5080 bld
.CMP(dst
, srcs
[TEX_LOGICAL_SRC_MCS
], brw_imm_ud(0u),
5081 BRW_CONDITIONAL_EQ
);
5086 unreachable("unknown texture opcode");
5089 if (instr
->op
== nir_texop_tg4
) {
5090 if (instr
->component
== 1 &&
5091 key_tex
->gather_channel_quirk_mask
& (1 << texture
)) {
5092 /* gather4 sampler is broken for green channel on RG32F --
5093 * we must ask for blue instead.
5095 header_bits
|= 2 << 16;
5097 header_bits
|= instr
->component
<< 16;
5101 fs_reg dst
= bld
.vgrf(brw_type_for_nir_type(devinfo
, instr
->dest_type
), 4);
5102 fs_inst
*inst
= bld
.emit(opcode
, dst
, srcs
, ARRAY_SIZE(srcs
));
5103 inst
->offset
= header_bits
;
5105 const unsigned dest_size
= nir_tex_instr_dest_size(instr
);
5106 if (devinfo
->gen
>= 9 &&
5107 instr
->op
!= nir_texop_tg4
&& instr
->op
!= nir_texop_query_levels
) {
5108 unsigned write_mask
= instr
->dest
.is_ssa
?
5109 nir_ssa_def_components_read(&instr
->dest
.ssa
):
5110 (1 << dest_size
) - 1;
5111 assert(write_mask
!= 0); /* dead code should have been eliminated */
5112 inst
->size_written
= util_last_bit(write_mask
) *
5113 inst
->dst
.component_size(inst
->exec_size
);
5115 inst
->size_written
= 4 * inst
->dst
.component_size(inst
->exec_size
);
5118 if (srcs
[TEX_LOGICAL_SRC_SHADOW_C
].file
!= BAD_FILE
)
5119 inst
->shadow_compare
= true;
5121 if (instr
->op
== nir_texop_tg4
&& devinfo
->gen
== 6)
5122 emit_gen6_gather_wa(key_tex
->gen6_gather_wa
[texture
], dst
);
5125 for (unsigned i
= 0; i
< dest_size
; i
++)
5126 nir_dest
[i
] = offset(dst
, bld
, i
);
5128 if (instr
->op
== nir_texop_query_levels
) {
5129 /* # levels is in .w */
5130 nir_dest
[0] = offset(dst
, bld
, 3);
5131 } else if (instr
->op
== nir_texop_txs
&&
5132 dest_size
>= 3 && devinfo
->gen
< 7) {
5133 /* Gen4-6 return 0 instead of 1 for single layer surfaces. */
5134 fs_reg depth
= offset(dst
, bld
, 2);
5135 nir_dest
[2] = vgrf(glsl_type::int_type
);
5136 bld
.emit_minmax(nir_dest
[2], depth
, brw_imm_d(1), BRW_CONDITIONAL_GE
);
5139 bld
.LOAD_PAYLOAD(get_nir_dest(instr
->dest
), nir_dest
, dest_size
, 0);
5143 fs_visitor::nir_emit_jump(const fs_builder
&bld
, nir_jump_instr
*instr
)
5145 switch (instr
->type
) {
5146 case nir_jump_break
:
5147 bld
.emit(BRW_OPCODE_BREAK
);
5149 case nir_jump_continue
:
5150 bld
.emit(BRW_OPCODE_CONTINUE
);
5152 case nir_jump_return
:
5154 unreachable("unknown jump");
5159 * This helper takes the result of a load operation that reads 32-bit elements
5167 * and shuffles the data to get this:
5174 * Which is exactly what we want if the load is reading 64-bit components
5175 * like doubles, where x represents the low 32-bit of the x double component
5176 * and y represents the high 32-bit of the x double component (likewise with
5177 * z and w for double component y). The parameter @components represents
5178 * the number of 64-bit components present in @src. This would typically be
5179 * 2 at most, since we can only fit 2 double elements in the result of a
5182 * Notice that @dst and @src can be the same register.
5185 shuffle_32bit_load_result_to_64bit_data(const fs_builder
&bld
,
5188 uint32_t components
)
5190 assert(type_sz(src
.type
) == 4);
5191 assert(type_sz(dst
.type
) == 8);
5193 /* A temporary that we will use to shuffle the 32-bit data of each
5194 * component in the vector into valid 64-bit data. We can't write directly
5195 * to dst because dst can be (and would usually be) the same as src
5196 * and in that case the first MOV in the loop below would overwrite the
5197 * data read in the second MOV.
5199 fs_reg tmp
= bld
.vgrf(dst
.type
);
5201 for (unsigned i
= 0; i
< components
; i
++) {
5202 const fs_reg component_i
= offset(src
, bld
, 2 * i
);
5204 bld
.MOV(subscript(tmp
, src
.type
, 0), component_i
);
5205 bld
.MOV(subscript(tmp
, src
.type
, 1), offset(component_i
, bld
, 1));
5207 bld
.MOV(offset(dst
, bld
, i
), tmp
);
5212 shuffle_32bit_load_result_to_16bit_data(const fs_builder
&bld
,
5215 uint32_t first_component
,
5216 uint32_t components
)
5218 assert(type_sz(src
.type
) == 4);
5219 assert(type_sz(dst
.type
) == 2);
5221 /* A temporary is used to un-shuffle the 32-bit data of each component in
5222 * into a valid 16-bit vector. We can't write directly to dst because it
5223 * can be the same register as src and in that case the first MOV in the
5224 * loop below would overwrite the data read in the second MOV.
5226 fs_reg tmp
= retype(bld
.vgrf(src
.type
), dst
.type
);
5228 for (unsigned i
= 0; i
< components
; i
++) {
5229 const fs_reg component_i
=
5230 subscript(offset(src
, bld
, (first_component
+ i
) / 2), dst
.type
,
5231 (first_component
+ i
) % 2);
5233 bld
.MOV(offset(tmp
, bld
, i
% 2), component_i
);
5236 bld
.MOV(offset(dst
, bld
, i
-1), offset(tmp
, bld
, 0));
5237 bld
.MOV(offset(dst
, bld
, i
), offset(tmp
, bld
, 1));
5240 if (components
% 2) {
5241 bld
.MOV(offset(dst
, bld
, components
- 1), tmp
);
5246 * This helper does the inverse operation of
5247 * SHUFFLE_32BIT_LOAD_RESULT_TO_64BIT_DATA.
5249 * We need to do this when we are going to use untyped write messsages that
5250 * operate with 32-bit components in order to arrange our 64-bit data to be
5251 * in the expected layout.
5253 * Notice that callers of this function, unlike in the case of the inverse
5254 * operation, would typically need to call this with dst and src being
5255 * different registers, since they would otherwise corrupt the original
5256 * 64-bit data they are about to write. Because of this the function checks
5257 * that the src and dst regions involved in the operation do not overlap.
5260 shuffle_64bit_data_for_32bit_write(const fs_builder
&bld
,
5262 uint32_t components
)
5264 assert(type_sz(src
.type
) == 8);
5266 fs_reg dst
= bld
.vgrf(BRW_REGISTER_TYPE_D
, 2 * components
);
5268 for (unsigned i
= 0; i
< components
; i
++) {
5269 const fs_reg component_i
= offset(src
, bld
, i
);
5270 bld
.MOV(offset(dst
, bld
, 2 * i
), subscript(component_i
, dst
.type
, 0));
5271 bld
.MOV(offset(dst
, bld
, 2 * i
+ 1), subscript(component_i
, dst
.type
, 1));
5278 shuffle_16bit_data_for_32bit_write(const fs_builder
&bld
,
5281 uint32_t components
)
5283 assert(type_sz(src
.type
) == 2);
5284 assert(type_sz(dst
.type
) == 4);
5286 /* A temporary is used to shuffle the 16-bit data of each component in the
5287 * 32-bit data vector. We can't write directly to dst because it can be the
5288 * same register as src and in that case the first MOV in the loop below
5289 * would overwrite the data read in the second MOV.
5291 fs_reg tmp
= bld
.vgrf(dst
.type
);
5293 for (unsigned i
= 0; i
< components
; i
++) {
5294 const fs_reg component_i
= offset(src
, bld
, i
);
5295 bld
.MOV(subscript(tmp
, src
.type
, i
% 2), component_i
);
5297 bld
.MOV(offset(dst
, bld
, i
/ 2), tmp
);
5300 if (components
% 2) {
5301 bld
.MOV(offset(dst
, bld
, components
/ 2), tmp
);
5306 setup_imm_df(const fs_builder
&bld
, double v
)
5308 const struct gen_device_info
*devinfo
= bld
.shader
->devinfo
;
5309 assert(devinfo
->gen
>= 7);
5311 if (devinfo
->gen
>= 8)
5312 return brw_imm_df(v
);
5314 /* gen7.5 does not support DF immediates straighforward but the DIM
5315 * instruction allows to set the 64-bit immediate value.
5317 if (devinfo
->is_haswell
) {
5318 const fs_builder ubld
= bld
.exec_all().group(1, 0);
5319 fs_reg dst
= ubld
.vgrf(BRW_REGISTER_TYPE_DF
, 1);
5320 ubld
.DIM(dst
, brw_imm_df(v
));
5321 return component(dst
, 0);
5324 /* gen7 does not support DF immediates, so we generate a 64-bit constant by
5325 * writing the low 32-bit of the constant to suboffset 0 of a VGRF and
5326 * the high 32-bit to suboffset 4 and then applying a stride of 0.
5328 * Alternatively, we could also produce a normal VGRF (without stride 0)
5329 * by writing to all the channels in the VGRF, however, that would hit the
5330 * gen7 bug where we have to split writes that span more than 1 register
5331 * into instructions with a width of 4 (otherwise the write to the second
5332 * register written runs into an execmask hardware bug) which isn't very
5345 const fs_builder ubld
= bld
.exec_all().group(1, 0);
5346 const fs_reg tmp
= ubld
.vgrf(BRW_REGISTER_TYPE_UD
, 2);
5347 ubld
.MOV(tmp
, brw_imm_ud(di
.i1
));
5348 ubld
.MOV(horiz_offset(tmp
, 1), brw_imm_ud(di
.i2
));
5350 return component(retype(tmp
, BRW_REGISTER_TYPE_DF
), 0);