2 * Copyright © 2010 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 #include "compiler/glsl/ir.h"
26 #include "brw_fs_surface_builder.h"
30 using namespace brw::surface_access
;
33 fs_visitor::emit_nir_code()
35 /* emit the arrays used for inputs and outputs - load/store intrinsics will
36 * be converted to reads/writes of these arrays
40 nir_emit_system_values();
42 /* get the main function and emit it */
43 nir_foreach_function(function
, nir
) {
44 assert(strcmp(function
->name
, "main") == 0);
45 assert(function
->impl
);
46 nir_emit_impl(function
->impl
);
51 fs_visitor::nir_setup_outputs()
53 if (stage
== MESA_SHADER_TESS_CTRL
|| stage
== MESA_SHADER_FRAGMENT
)
56 unsigned vec4s
[VARYING_SLOT_TESS_MAX
] = { 0, };
58 /* Calculate the size of output registers in a separate pass, before
59 * allocating them. With ARB_enhanced_layouts, multiple output variables
60 * may occupy the same slot, but have different type sizes.
62 nir_foreach_variable(var
, &nir
->outputs
) {
63 const int loc
= var
->data
.driver_location
;
64 const unsigned var_vec4s
=
65 var
->data
.compact
? DIV_ROUND_UP(glsl_get_length(var
->type
), 4)
66 : type_size_vec4(var
->type
);
67 vec4s
[loc
] = MAX2(vec4s
[loc
], var_vec4s
);
70 nir_foreach_variable(var
, &nir
->outputs
) {
71 const int loc
= var
->data
.driver_location
;
72 if (outputs
[loc
].file
== BAD_FILE
) {
73 fs_reg reg
= bld
.vgrf(BRW_REGISTER_TYPE_F
, 4 * vec4s
[loc
]);
74 for (unsigned i
= 0; i
< vec4s
[loc
]; i
++) {
75 outputs
[loc
+ i
] = offset(reg
, bld
, 4 * i
);
82 fs_visitor::nir_setup_uniforms()
84 if (dispatch_width
!= min_dispatch_width
)
87 uniforms
= nir
->num_uniforms
/ 4;
91 emit_system_values_block(nir_block
*block
, fs_visitor
*v
)
95 nir_foreach_instr(instr
, block
) {
96 if (instr
->type
!= nir_instr_type_intrinsic
)
99 nir_intrinsic_instr
*intrin
= nir_instr_as_intrinsic(instr
);
100 switch (intrin
->intrinsic
) {
101 case nir_intrinsic_load_vertex_id
:
102 unreachable("should be lowered by lower_vertex_id().");
104 case nir_intrinsic_load_vertex_id_zero_base
:
105 case nir_intrinsic_load_base_vertex
:
106 case nir_intrinsic_load_instance_id
:
107 case nir_intrinsic_load_base_instance
:
108 case nir_intrinsic_load_draw_id
:
109 unreachable("should be lowered by brw_nir_lower_vs_inputs().");
111 case nir_intrinsic_load_invocation_id
:
112 if (v
->stage
== MESA_SHADER_TESS_CTRL
)
114 assert(v
->stage
== MESA_SHADER_GEOMETRY
);
115 reg
= &v
->nir_system_values
[SYSTEM_VALUE_INVOCATION_ID
];
116 if (reg
->file
== BAD_FILE
) {
117 const fs_builder abld
= v
->bld
.annotate("gl_InvocationID", NULL
);
118 fs_reg
g1(retype(brw_vec8_grf(1, 0), BRW_REGISTER_TYPE_UD
));
119 fs_reg iid
= abld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
120 abld
.SHR(iid
, g1
, brw_imm_ud(27u));
125 case nir_intrinsic_load_sample_pos
:
126 assert(v
->stage
== MESA_SHADER_FRAGMENT
);
127 reg
= &v
->nir_system_values
[SYSTEM_VALUE_SAMPLE_POS
];
128 if (reg
->file
== BAD_FILE
)
129 *reg
= *v
->emit_samplepos_setup();
132 case nir_intrinsic_load_sample_id
:
133 assert(v
->stage
== MESA_SHADER_FRAGMENT
);
134 reg
= &v
->nir_system_values
[SYSTEM_VALUE_SAMPLE_ID
];
135 if (reg
->file
== BAD_FILE
)
136 *reg
= *v
->emit_sampleid_setup();
139 case nir_intrinsic_load_sample_mask_in
:
140 assert(v
->stage
== MESA_SHADER_FRAGMENT
);
141 assert(v
->devinfo
->gen
>= 7);
142 reg
= &v
->nir_system_values
[SYSTEM_VALUE_SAMPLE_MASK_IN
];
143 if (reg
->file
== BAD_FILE
)
144 *reg
= *v
->emit_samplemaskin_setup();
147 case nir_intrinsic_load_work_group_id
:
148 assert(v
->stage
== MESA_SHADER_COMPUTE
);
149 reg
= &v
->nir_system_values
[SYSTEM_VALUE_WORK_GROUP_ID
];
150 if (reg
->file
== BAD_FILE
)
151 *reg
= *v
->emit_cs_work_group_id_setup();
154 case nir_intrinsic_load_helper_invocation
:
155 assert(v
->stage
== MESA_SHADER_FRAGMENT
);
156 reg
= &v
->nir_system_values
[SYSTEM_VALUE_HELPER_INVOCATION
];
157 if (reg
->file
== BAD_FILE
) {
158 const fs_builder abld
=
159 v
->bld
.annotate("gl_HelperInvocation", NULL
);
161 /* On Gen6+ (gl_HelperInvocation is only exposed on Gen7+) the
162 * pixel mask is in g1.7 of the thread payload.
164 * We move the per-channel pixel enable bit to the low bit of each
165 * channel by shifting the byte containing the pixel mask by the
166 * vector immediate 0x76543210UV.
168 * The region of <1,8,0> reads only 1 byte (the pixel masks for
169 * subspans 0 and 1) in SIMD8 and an additional byte (the pixel
170 * masks for 2 and 3) in SIMD16.
172 fs_reg shifted
= abld
.vgrf(BRW_REGISTER_TYPE_UW
, 1);
174 stride(byte_offset(retype(brw_vec1_grf(1, 0),
175 BRW_REGISTER_TYPE_UB
), 28),
177 brw_imm_v(0x76543210));
179 /* A set bit in the pixel mask means the channel is enabled, but
180 * that is the opposite of gl_HelperInvocation so we need to invert
183 * The negate source-modifier bit of logical instructions on Gen8+
184 * performs 1's complement negation, so we can use that instead of
187 fs_reg inverted
= negate(shifted
);
188 if (v
->devinfo
->gen
< 8) {
189 inverted
= abld
.vgrf(BRW_REGISTER_TYPE_UW
);
190 abld
.NOT(inverted
, shifted
);
193 /* We then resolve the 0/1 result to 0/~0 boolean values by ANDing
194 * with 1 and negating.
196 fs_reg anded
= abld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
197 abld
.AND(anded
, inverted
, brw_imm_uw(1));
199 fs_reg dst
= abld
.vgrf(BRW_REGISTER_TYPE_D
, 1);
200 abld
.MOV(dst
, negate(retype(anded
, BRW_REGISTER_TYPE_D
)));
214 fs_visitor::nir_emit_system_values()
216 nir_system_values
= ralloc_array(mem_ctx
, fs_reg
, SYSTEM_VALUE_MAX
);
217 for (unsigned i
= 0; i
< SYSTEM_VALUE_MAX
; i
++) {
218 nir_system_values
[i
] = fs_reg();
221 nir_foreach_function(function
, nir
) {
222 assert(strcmp(function
->name
, "main") == 0);
223 assert(function
->impl
);
224 nir_foreach_block(block
, function
->impl
) {
225 emit_system_values_block(block
, this);
231 fs_visitor::nir_emit_impl(nir_function_impl
*impl
)
233 nir_locals
= ralloc_array(mem_ctx
, fs_reg
, impl
->reg_alloc
);
234 for (unsigned i
= 0; i
< impl
->reg_alloc
; i
++) {
235 nir_locals
[i
] = fs_reg();
238 foreach_list_typed(nir_register
, reg
, node
, &impl
->registers
) {
239 unsigned array_elems
=
240 reg
->num_array_elems
== 0 ? 1 : reg
->num_array_elems
;
241 unsigned size
= array_elems
* reg
->num_components
;
242 const brw_reg_type reg_type
=
243 reg
->bit_size
== 32 ? BRW_REGISTER_TYPE_F
: BRW_REGISTER_TYPE_DF
;
244 nir_locals
[reg
->index
] = bld
.vgrf(reg_type
, size
);
247 nir_ssa_values
= reralloc(mem_ctx
, nir_ssa_values
, fs_reg
,
250 nir_emit_cf_list(&impl
->body
);
254 fs_visitor::nir_emit_cf_list(exec_list
*list
)
256 exec_list_validate(list
);
257 foreach_list_typed(nir_cf_node
, node
, node
, list
) {
258 switch (node
->type
) {
260 nir_emit_if(nir_cf_node_as_if(node
));
263 case nir_cf_node_loop
:
264 nir_emit_loop(nir_cf_node_as_loop(node
));
267 case nir_cf_node_block
:
268 nir_emit_block(nir_cf_node_as_block(node
));
272 unreachable("Invalid CFG node block");
278 fs_visitor::nir_emit_if(nir_if
*if_stmt
)
280 /* first, put the condition into f0 */
281 fs_inst
*inst
= bld
.MOV(bld
.null_reg_d(),
282 retype(get_nir_src(if_stmt
->condition
),
283 BRW_REGISTER_TYPE_D
));
284 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
286 bld
.IF(BRW_PREDICATE_NORMAL
);
288 nir_emit_cf_list(&if_stmt
->then_list
);
290 /* note: if the else is empty, dead CF elimination will remove it */
291 bld
.emit(BRW_OPCODE_ELSE
);
293 nir_emit_cf_list(&if_stmt
->else_list
);
295 bld
.emit(BRW_OPCODE_ENDIF
);
299 fs_visitor::nir_emit_loop(nir_loop
*loop
)
301 bld
.emit(BRW_OPCODE_DO
);
303 nir_emit_cf_list(&loop
->body
);
305 bld
.emit(BRW_OPCODE_WHILE
);
309 fs_visitor::nir_emit_block(nir_block
*block
)
311 nir_foreach_instr(instr
, block
) {
312 nir_emit_instr(instr
);
317 fs_visitor::nir_emit_instr(nir_instr
*instr
)
319 const fs_builder abld
= bld
.annotate(NULL
, instr
);
321 switch (instr
->type
) {
322 case nir_instr_type_alu
:
323 nir_emit_alu(abld
, nir_instr_as_alu(instr
));
326 case nir_instr_type_intrinsic
:
328 case MESA_SHADER_VERTEX
:
329 nir_emit_vs_intrinsic(abld
, nir_instr_as_intrinsic(instr
));
331 case MESA_SHADER_TESS_CTRL
:
332 nir_emit_tcs_intrinsic(abld
, nir_instr_as_intrinsic(instr
));
334 case MESA_SHADER_TESS_EVAL
:
335 nir_emit_tes_intrinsic(abld
, nir_instr_as_intrinsic(instr
));
337 case MESA_SHADER_GEOMETRY
:
338 nir_emit_gs_intrinsic(abld
, nir_instr_as_intrinsic(instr
));
340 case MESA_SHADER_FRAGMENT
:
341 nir_emit_fs_intrinsic(abld
, nir_instr_as_intrinsic(instr
));
343 case MESA_SHADER_COMPUTE
:
344 nir_emit_cs_intrinsic(abld
, nir_instr_as_intrinsic(instr
));
347 unreachable("unsupported shader stage");
351 case nir_instr_type_tex
:
352 nir_emit_texture(abld
, nir_instr_as_tex(instr
));
355 case nir_instr_type_load_const
:
356 nir_emit_load_const(abld
, nir_instr_as_load_const(instr
));
359 case nir_instr_type_ssa_undef
:
360 /* We create a new VGRF for undefs on every use (by handling
361 * them in get_nir_src()), rather than for each definition.
362 * This helps register coalescing eliminate MOVs from undef.
366 case nir_instr_type_jump
:
367 nir_emit_jump(abld
, nir_instr_as_jump(instr
));
371 unreachable("unknown instruction type");
376 * Recognizes a parent instruction of nir_op_extract_* and changes the type to
380 fs_visitor::optimize_extract_to_float(nir_alu_instr
*instr
,
381 const fs_reg
&result
)
383 if (!instr
->src
[0].src
.is_ssa
||
384 !instr
->src
[0].src
.ssa
->parent_instr
)
387 if (instr
->src
[0].src
.ssa
->parent_instr
->type
!= nir_instr_type_alu
)
390 nir_alu_instr
*src0
=
391 nir_instr_as_alu(instr
->src
[0].src
.ssa
->parent_instr
);
393 if (src0
->op
!= nir_op_extract_u8
&& src0
->op
!= nir_op_extract_u16
&&
394 src0
->op
!= nir_op_extract_i8
&& src0
->op
!= nir_op_extract_i16
)
397 nir_const_value
*element
= nir_src_as_const_value(src0
->src
[1].src
);
398 assert(element
!= NULL
);
400 /* Element type to extract.*/
401 const brw_reg_type type
= brw_int_type(
402 src0
->op
== nir_op_extract_u16
|| src0
->op
== nir_op_extract_i16
? 2 : 1,
403 src0
->op
== nir_op_extract_i16
|| src0
->op
== nir_op_extract_i8
);
405 fs_reg op0
= get_nir_src(src0
->src
[0].src
);
406 op0
.type
= brw_type_for_nir_type(devinfo
,
407 (nir_alu_type
)(nir_op_infos
[src0
->op
].input_types
[0] |
408 nir_src_bit_size(src0
->src
[0].src
)));
409 op0
= offset(op0
, bld
, src0
->src
[0].swizzle
[0]);
411 set_saturate(instr
->dest
.saturate
,
412 bld
.MOV(result
, subscript(op0
, type
, element
->u32
[0])));
417 fs_visitor::optimize_frontfacing_ternary(nir_alu_instr
*instr
,
418 const fs_reg
&result
)
420 if (!instr
->src
[0].src
.is_ssa
||
421 instr
->src
[0].src
.ssa
->parent_instr
->type
!= nir_instr_type_intrinsic
)
424 nir_intrinsic_instr
*src0
=
425 nir_instr_as_intrinsic(instr
->src
[0].src
.ssa
->parent_instr
);
427 if (src0
->intrinsic
!= nir_intrinsic_load_front_face
)
430 nir_const_value
*value1
= nir_src_as_const_value(instr
->src
[1].src
);
431 if (!value1
|| fabsf(value1
->f32
[0]) != 1.0f
)
434 nir_const_value
*value2
= nir_src_as_const_value(instr
->src
[2].src
);
435 if (!value2
|| fabsf(value2
->f32
[0]) != 1.0f
)
438 fs_reg tmp
= vgrf(glsl_type::int_type
);
440 if (devinfo
->gen
>= 6) {
441 /* Bit 15 of g0.0 is 0 if the polygon is front facing. */
442 fs_reg g0
= fs_reg(retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_W
));
444 /* For (gl_FrontFacing ? 1.0 : -1.0), emit:
446 * or(8) tmp.1<2>W g0.0<0,1,0>W 0x00003f80W
447 * and(8) dst<1>D tmp<8,8,1>D 0xbf800000D
449 * and negate g0.0<0,1,0>W for (gl_FrontFacing ? -1.0 : 1.0).
451 * This negation looks like it's safe in practice, because bits 0:4 will
452 * surely be TRIANGLES
455 if (value1
->f32
[0] == -1.0f
) {
459 bld
.OR(subscript(tmp
, BRW_REGISTER_TYPE_W
, 1),
460 g0
, brw_imm_uw(0x3f80));
462 /* Bit 31 of g1.6 is 0 if the polygon is front facing. */
463 fs_reg g1_6
= fs_reg(retype(brw_vec1_grf(1, 6), BRW_REGISTER_TYPE_D
));
465 /* For (gl_FrontFacing ? 1.0 : -1.0), emit:
467 * or(8) tmp<1>D g1.6<0,1,0>D 0x3f800000D
468 * and(8) dst<1>D tmp<8,8,1>D 0xbf800000D
470 * and negate g1.6<0,1,0>D for (gl_FrontFacing ? -1.0 : 1.0).
472 * This negation looks like it's safe in practice, because bits 0:4 will
473 * surely be TRIANGLES
476 if (value1
->f32
[0] == -1.0f
) {
480 bld
.OR(tmp
, g1_6
, brw_imm_d(0x3f800000));
482 bld
.AND(retype(result
, BRW_REGISTER_TYPE_D
), tmp
, brw_imm_d(0xbf800000));
488 emit_find_msb_using_lzd(const fs_builder
&bld
,
489 const fs_reg
&result
,
497 /* LZD of an absolute value source almost always does the right
498 * thing. There are two problem values:
500 * * 0x80000000. Since abs(0x80000000) == 0x80000000, LZD returns
501 * 0. However, findMSB(int(0x80000000)) == 30.
503 * * 0xffffffff. Since abs(0xffffffff) == 1, LZD returns
504 * 31. Section 8.8 (Integer Functions) of the GLSL 4.50 spec says:
506 * For a value of zero or negative one, -1 will be returned.
508 * * Negative powers of two. LZD(abs(-(1<<x))) returns x, but
509 * findMSB(-(1<<x)) should return x-1.
511 * For all negative number cases, including 0x80000000 and
512 * 0xffffffff, the correct value is obtained from LZD if instead of
513 * negating the (already negative) value the logical-not is used. A
514 * conditonal logical-not can be achieved in two instructions.
516 temp
= bld
.vgrf(BRW_REGISTER_TYPE_D
);
518 bld
.ASR(temp
, src
, brw_imm_d(31));
519 bld
.XOR(temp
, temp
, src
);
522 bld
.LZD(retype(result
, BRW_REGISTER_TYPE_UD
),
523 retype(temp
, BRW_REGISTER_TYPE_UD
));
525 /* LZD counts from the MSB side, while GLSL's findMSB() wants the count
526 * from the LSB side. Subtract the result from 31 to convert the MSB
527 * count into an LSB count. If no bits are set, LZD will return 32.
528 * 31-32 = -1, which is exactly what findMSB() is supposed to return.
530 inst
= bld
.ADD(result
, retype(result
, BRW_REGISTER_TYPE_D
), brw_imm_d(31));
531 inst
->src
[0].negate
= true;
535 fs_visitor::nir_emit_alu(const fs_builder
&bld
, nir_alu_instr
*instr
)
537 struct brw_wm_prog_key
*fs_key
= (struct brw_wm_prog_key
*) this->key
;
540 fs_reg result
= get_nir_dest(instr
->dest
.dest
);
541 result
.type
= brw_type_for_nir_type(devinfo
,
542 (nir_alu_type
)(nir_op_infos
[instr
->op
].output_type
|
543 nir_dest_bit_size(instr
->dest
.dest
)));
546 for (unsigned i
= 0; i
< nir_op_infos
[instr
->op
].num_inputs
; i
++) {
547 op
[i
] = get_nir_src(instr
->src
[i
].src
);
548 op
[i
].type
= brw_type_for_nir_type(devinfo
,
549 (nir_alu_type
)(nir_op_infos
[instr
->op
].input_types
[i
] |
550 nir_src_bit_size(instr
->src
[i
].src
)));
551 op
[i
].abs
= instr
->src
[i
].abs
;
552 op
[i
].negate
= instr
->src
[i
].negate
;
555 /* We get a bunch of mov's out of the from_ssa pass and they may still
556 * be vectorized. We'll handle them as a special-case. We'll also
557 * handle vecN here because it's basically the same thing.
565 fs_reg temp
= result
;
566 bool need_extra_copy
= false;
567 for (unsigned i
= 0; i
< nir_op_infos
[instr
->op
].num_inputs
; i
++) {
568 if (!instr
->src
[i
].src
.is_ssa
&&
569 instr
->dest
.dest
.reg
.reg
== instr
->src
[i
].src
.reg
.reg
) {
570 need_extra_copy
= true;
571 temp
= bld
.vgrf(result
.type
, 4);
576 for (unsigned i
= 0; i
< 4; i
++) {
577 if (!(instr
->dest
.write_mask
& (1 << i
)))
580 if (instr
->op
== nir_op_imov
|| instr
->op
== nir_op_fmov
) {
581 inst
= bld
.MOV(offset(temp
, bld
, i
),
582 offset(op
[0], bld
, instr
->src
[0].swizzle
[i
]));
584 inst
= bld
.MOV(offset(temp
, bld
, i
),
585 offset(op
[i
], bld
, instr
->src
[i
].swizzle
[0]));
587 inst
->saturate
= instr
->dest
.saturate
;
590 /* In this case the source and destination registers were the same,
591 * so we need to insert an extra set of moves in order to deal with
594 if (need_extra_copy
) {
595 for (unsigned i
= 0; i
< 4; i
++) {
596 if (!(instr
->dest
.write_mask
& (1 << i
)))
599 bld
.MOV(offset(result
, bld
, i
), offset(temp
, bld
, i
));
608 /* At this point, we have dealt with any instruction that operates on
609 * more than a single channel. Therefore, we can just adjust the source
610 * and destination registers for that channel and emit the instruction.
612 unsigned channel
= 0;
613 if (nir_op_infos
[instr
->op
].output_size
== 0) {
614 /* Since NIR is doing the scalarizing for us, we should only ever see
615 * vectorized operations with a single channel.
617 assert(_mesa_bitcount(instr
->dest
.write_mask
) == 1);
618 channel
= ffs(instr
->dest
.write_mask
) - 1;
620 result
= offset(result
, bld
, channel
);
623 for (unsigned i
= 0; i
< nir_op_infos
[instr
->op
].num_inputs
; i
++) {
624 assert(nir_op_infos
[instr
->op
].input_sizes
[i
] < 2);
625 op
[i
] = offset(op
[i
], bld
, instr
->src
[i
].swizzle
[channel
]);
631 if (optimize_extract_to_float(instr
, result
))
633 inst
= bld
.MOV(result
, op
[0]);
634 inst
->saturate
= instr
->dest
.saturate
;
640 /* CHV PRM, vol07, 3D Media GPGPU Engine, Register Region Restrictions:
642 * "When source or destination is 64b (...), regioning in Align1
643 * must follow these rules:
645 * 1. Source and destination horizontal stride must be aligned to
649 * This means that 32-bit to 64-bit conversions need to have the 32-bit
650 * data elements aligned to 64-bit. This restriction does not apply to
653 if (nir_dest_bit_size(instr
->dest
.dest
) == 64 &&
654 nir_src_bit_size(instr
->src
[0].src
) == 32 &&
655 (devinfo
->is_cherryview
|| gen_device_info_is_9lp(devinfo
))) {
656 fs_reg tmp
= bld
.vgrf(result
.type
, 1);
657 tmp
= subscript(tmp
, op
[0].type
, 0);
658 inst
= bld
.MOV(tmp
, op
[0]);
659 inst
= bld
.MOV(result
, tmp
);
660 inst
->saturate
= instr
->dest
.saturate
;
673 inst
= bld
.MOV(result
, op
[0]);
674 inst
->saturate
= instr
->dest
.saturate
;
679 /* Straightforward since the source can be assumed to be
682 set_condmod(BRW_CONDITIONAL_NZ
, bld
.MOV(result
, op
[0]));
683 set_predicate(BRW_PREDICATE_NORMAL
, bld
.MOV(result
, brw_imm_f(1.0f
)));
685 } else if (type_sz(op
[0].type
) < 8) {
686 /* AND(val, 0x80000000) gives the sign bit.
688 * Predicated OR ORs 1.0 (0x3f800000) with the sign bit if val is not
691 bld
.CMP(bld
.null_reg_f(), op
[0], brw_imm_f(0.0f
), BRW_CONDITIONAL_NZ
);
693 fs_reg result_int
= retype(result
, BRW_REGISTER_TYPE_UD
);
694 op
[0].type
= BRW_REGISTER_TYPE_UD
;
695 result
.type
= BRW_REGISTER_TYPE_UD
;
696 bld
.AND(result_int
, op
[0], brw_imm_ud(0x80000000u
));
698 inst
= bld
.OR(result_int
, result_int
, brw_imm_ud(0x3f800000u
));
699 inst
->predicate
= BRW_PREDICATE_NORMAL
;
700 if (instr
->dest
.saturate
) {
701 inst
= bld
.MOV(result
, result
);
702 inst
->saturate
= true;
705 /* For doubles we do the same but we need to consider:
707 * - 2-src instructions can't operate with 64-bit immediates
708 * - The sign is encoded in the high 32-bit of each DF
709 * - We need to produce a DF result.
712 fs_reg zero
= vgrf(glsl_type::double_type
);
713 bld
.MOV(zero
, setup_imm_df(bld
, 0.0));
714 bld
.CMP(bld
.null_reg_df(), op
[0], zero
, BRW_CONDITIONAL_NZ
);
716 bld
.MOV(result
, zero
);
718 fs_reg r
= subscript(result
, BRW_REGISTER_TYPE_UD
, 1);
719 bld
.AND(r
, subscript(op
[0], BRW_REGISTER_TYPE_UD
, 1),
720 brw_imm_ud(0x80000000u
));
722 set_predicate(BRW_PREDICATE_NORMAL
,
723 bld
.OR(r
, r
, brw_imm_ud(0x3ff00000u
)));
725 if (instr
->dest
.saturate
) {
726 inst
= bld
.MOV(result
, result
);
727 inst
->saturate
= true;
734 /* ASR(val, 31) -> negative val generates 0xffffffff (signed -1).
735 * -> non-negative val generates 0x00000000.
736 * Predicated OR sets 1 if val is positive.
738 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
739 bld
.CMP(bld
.null_reg_d(), op
[0], brw_imm_d(0), BRW_CONDITIONAL_G
);
740 bld
.ASR(result
, op
[0], brw_imm_d(31));
741 inst
= bld
.OR(result
, result
, brw_imm_d(1));
742 inst
->predicate
= BRW_PREDICATE_NORMAL
;
746 inst
= bld
.emit(SHADER_OPCODE_RCP
, result
, op
[0]);
747 inst
->saturate
= instr
->dest
.saturate
;
751 inst
= bld
.emit(SHADER_OPCODE_EXP2
, result
, op
[0]);
752 inst
->saturate
= instr
->dest
.saturate
;
756 inst
= bld
.emit(SHADER_OPCODE_LOG2
, result
, op
[0]);
757 inst
->saturate
= instr
->dest
.saturate
;
761 inst
= bld
.emit(SHADER_OPCODE_SIN
, result
, op
[0]);
762 inst
->saturate
= instr
->dest
.saturate
;
766 inst
= bld
.emit(SHADER_OPCODE_COS
, result
, op
[0]);
767 inst
->saturate
= instr
->dest
.saturate
;
771 if (fs_key
->high_quality_derivatives
) {
772 inst
= bld
.emit(FS_OPCODE_DDX_FINE
, result
, op
[0]);
774 inst
= bld
.emit(FS_OPCODE_DDX_COARSE
, result
, op
[0]);
776 inst
->saturate
= instr
->dest
.saturate
;
778 case nir_op_fddx_fine
:
779 inst
= bld
.emit(FS_OPCODE_DDX_FINE
, result
, op
[0]);
780 inst
->saturate
= instr
->dest
.saturate
;
782 case nir_op_fddx_coarse
:
783 inst
= bld
.emit(FS_OPCODE_DDX_COARSE
, result
, op
[0]);
784 inst
->saturate
= instr
->dest
.saturate
;
787 if (fs_key
->high_quality_derivatives
) {
788 inst
= bld
.emit(FS_OPCODE_DDY_FINE
, result
, op
[0]);
790 inst
= bld
.emit(FS_OPCODE_DDY_COARSE
, result
, op
[0]);
792 inst
->saturate
= instr
->dest
.saturate
;
794 case nir_op_fddy_fine
:
795 inst
= bld
.emit(FS_OPCODE_DDY_FINE
, result
, op
[0]);
796 inst
->saturate
= instr
->dest
.saturate
;
798 case nir_op_fddy_coarse
:
799 inst
= bld
.emit(FS_OPCODE_DDY_COARSE
, result
, op
[0]);
800 inst
->saturate
= instr
->dest
.saturate
;
805 inst
= bld
.ADD(result
, op
[0], op
[1]);
806 inst
->saturate
= instr
->dest
.saturate
;
810 inst
= bld
.MUL(result
, op
[0], op
[1]);
811 inst
->saturate
= instr
->dest
.saturate
;
815 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
816 bld
.MUL(result
, op
[0], op
[1]);
819 case nir_op_imul_high
:
820 case nir_op_umul_high
:
821 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
822 bld
.emit(SHADER_OPCODE_MULH
, result
, op
[0], op
[1]);
827 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
828 bld
.emit(SHADER_OPCODE_INT_QUOTIENT
, result
, op
[0], op
[1]);
831 case nir_op_uadd_carry
:
832 unreachable("Should have been lowered by carry_to_arith().");
834 case nir_op_usub_borrow
:
835 unreachable("Should have been lowered by borrow_to_arith().");
839 /* According to the sign table for INT DIV in the Ivy Bridge PRM, it
840 * appears that our hardware just does the right thing for signed
843 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
844 bld
.emit(SHADER_OPCODE_INT_REMAINDER
, result
, op
[0], op
[1]);
848 /* Get a regular C-style remainder. If a % b == 0, set the predicate. */
849 bld
.emit(SHADER_OPCODE_INT_REMAINDER
, result
, op
[0], op
[1]);
851 /* Math instructions don't support conditional mod */
852 inst
= bld
.MOV(bld
.null_reg_d(), result
);
853 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
855 /* Now, we need to determine if signs of the sources are different.
856 * When we XOR the sources, the top bit is 0 if they are the same and 1
857 * if they are different. We can then use a conditional modifier to
858 * turn that into a predicate. This leads us to an XOR.l instruction.
860 * Technically, according to the PRM, you're not allowed to use .l on a
861 * XOR instruction. However, emperical experiments and Curro's reading
862 * of the simulator source both indicate that it's safe.
864 fs_reg tmp
= bld
.vgrf(BRW_REGISTER_TYPE_D
);
865 inst
= bld
.XOR(tmp
, op
[0], op
[1]);
866 inst
->predicate
= BRW_PREDICATE_NORMAL
;
867 inst
->conditional_mod
= BRW_CONDITIONAL_L
;
869 /* If the result of the initial remainder operation is non-zero and the
870 * two sources have different signs, add in a copy of op[1] to get the
871 * final integer modulus value.
873 inst
= bld
.ADD(result
, result
, op
[1]);
874 inst
->predicate
= BRW_PREDICATE_NORMAL
;
882 fs_reg dest
= result
;
883 if (nir_src_bit_size(instr
->src
[0].src
) > 32) {
884 dest
= bld
.vgrf(BRW_REGISTER_TYPE_DF
, 1);
886 brw_conditional_mod cond
;
889 cond
= BRW_CONDITIONAL_L
;
892 cond
= BRW_CONDITIONAL_GE
;
895 cond
= BRW_CONDITIONAL_Z
;
898 cond
= BRW_CONDITIONAL_NZ
;
901 unreachable("bad opcode");
903 bld
.CMP(dest
, op
[0], op
[1], cond
);
904 if (nir_src_bit_size(instr
->src
[0].src
) > 32) {
905 bld
.MOV(result
, subscript(dest
, BRW_REGISTER_TYPE_UD
, 0));
916 fs_reg dest
= result
;
917 if (nir_src_bit_size(instr
->src
[0].src
) > 32) {
918 dest
= bld
.vgrf(BRW_REGISTER_TYPE_UQ
, 1);
921 brw_conditional_mod cond
;
925 cond
= BRW_CONDITIONAL_L
;
929 cond
= BRW_CONDITIONAL_GE
;
932 cond
= BRW_CONDITIONAL_Z
;
935 cond
= BRW_CONDITIONAL_NZ
;
938 unreachable("bad opcode");
940 bld
.CMP(dest
, op
[0], op
[1], cond
);
941 if (nir_src_bit_size(instr
->src
[0].src
) > 32) {
942 bld
.MOV(result
, subscript(dest
, BRW_REGISTER_TYPE_UD
, 0));
948 if (devinfo
->gen
>= 8) {
949 op
[0] = resolve_source_modifiers(op
[0]);
951 bld
.NOT(result
, op
[0]);
954 if (devinfo
->gen
>= 8) {
955 op
[0] = resolve_source_modifiers(op
[0]);
956 op
[1] = resolve_source_modifiers(op
[1]);
958 bld
.XOR(result
, op
[0], op
[1]);
961 if (devinfo
->gen
>= 8) {
962 op
[0] = resolve_source_modifiers(op
[0]);
963 op
[1] = resolve_source_modifiers(op
[1]);
965 bld
.OR(result
, op
[0], op
[1]);
968 if (devinfo
->gen
>= 8) {
969 op
[0] = resolve_source_modifiers(op
[0]);
970 op
[1] = resolve_source_modifiers(op
[1]);
972 bld
.AND(result
, op
[0], op
[1]);
978 case nir_op_ball_fequal2
:
979 case nir_op_ball_iequal2
:
980 case nir_op_ball_fequal3
:
981 case nir_op_ball_iequal3
:
982 case nir_op_ball_fequal4
:
983 case nir_op_ball_iequal4
:
984 case nir_op_bany_fnequal2
:
985 case nir_op_bany_inequal2
:
986 case nir_op_bany_fnequal3
:
987 case nir_op_bany_inequal3
:
988 case nir_op_bany_fnequal4
:
989 case nir_op_bany_inequal4
:
990 unreachable("Lowered by nir_lower_alu_reductions");
992 case nir_op_fnoise1_1
:
993 case nir_op_fnoise1_2
:
994 case nir_op_fnoise1_3
:
995 case nir_op_fnoise1_4
:
996 case nir_op_fnoise2_1
:
997 case nir_op_fnoise2_2
:
998 case nir_op_fnoise2_3
:
999 case nir_op_fnoise2_4
:
1000 case nir_op_fnoise3_1
:
1001 case nir_op_fnoise3_2
:
1002 case nir_op_fnoise3_3
:
1003 case nir_op_fnoise3_4
:
1004 case nir_op_fnoise4_1
:
1005 case nir_op_fnoise4_2
:
1006 case nir_op_fnoise4_3
:
1007 case nir_op_fnoise4_4
:
1008 unreachable("not reached: should be handled by lower_noise");
1011 unreachable("not reached: should be handled by ldexp_to_arith()");
1014 inst
= bld
.emit(SHADER_OPCODE_SQRT
, result
, op
[0]);
1015 inst
->saturate
= instr
->dest
.saturate
;
1019 inst
= bld
.emit(SHADER_OPCODE_RSQ
, result
, op
[0]);
1020 inst
->saturate
= instr
->dest
.saturate
;
1025 bld
.MOV(result
, negate(op
[0]));
1030 if (nir_src_bit_size(instr
->src
[0].src
) == 64) {
1031 /* two-argument instructions can't take 64-bit immediates */
1035 if (instr
->op
== nir_op_f2b
) {
1036 zero
= vgrf(glsl_type::double_type
);
1037 tmp
= vgrf(glsl_type::double_type
);
1039 zero
= vgrf(glsl_type::int64_t_type
);
1040 tmp
= vgrf(glsl_type::int64_t_type
);
1043 bld
.MOV(zero
, setup_imm_df(bld
, 0.0));
1044 /* A SIMD16 execution needs to be split in two instructions, so use
1045 * a vgrf instead of the flag register as dst so instruction splitting
1048 bld
.CMP(tmp
, op
[0], zero
, BRW_CONDITIONAL_NZ
);
1049 bld
.MOV(result
, subscript(tmp
, BRW_REGISTER_TYPE_UD
, 0));
1051 if (instr
->op
== nir_op_f2b
) {
1052 bld
.CMP(result
, op
[0], brw_imm_f(0.0f
), BRW_CONDITIONAL_NZ
);
1054 bld
.CMP(result
, op
[0], brw_imm_d(0), BRW_CONDITIONAL_NZ
);
1060 inst
= bld
.RNDZ(result
, op
[0]);
1061 inst
->saturate
= instr
->dest
.saturate
;
1064 case nir_op_fceil
: {
1065 op
[0].negate
= !op
[0].negate
;
1066 fs_reg temp
= vgrf(glsl_type::float_type
);
1067 bld
.RNDD(temp
, op
[0]);
1069 inst
= bld
.MOV(result
, temp
);
1070 inst
->saturate
= instr
->dest
.saturate
;
1074 inst
= bld
.RNDD(result
, op
[0]);
1075 inst
->saturate
= instr
->dest
.saturate
;
1078 inst
= bld
.FRC(result
, op
[0]);
1079 inst
->saturate
= instr
->dest
.saturate
;
1081 case nir_op_fround_even
:
1082 inst
= bld
.RNDE(result
, op
[0]);
1083 inst
->saturate
= instr
->dest
.saturate
;
1086 case nir_op_fquantize2f16
: {
1087 fs_reg tmp16
= bld
.vgrf(BRW_REGISTER_TYPE_D
);
1088 fs_reg tmp32
= bld
.vgrf(BRW_REGISTER_TYPE_F
);
1089 fs_reg zero
= bld
.vgrf(BRW_REGISTER_TYPE_F
);
1091 /* The destination stride must be at least as big as the source stride. */
1092 tmp16
.type
= BRW_REGISTER_TYPE_W
;
1095 /* Check for denormal */
1096 fs_reg abs_src0
= op
[0];
1097 abs_src0
.abs
= true;
1098 bld
.CMP(bld
.null_reg_f(), abs_src0
, brw_imm_f(ldexpf(1.0, -14)),
1100 /* Get the appropriately signed zero */
1101 bld
.AND(retype(zero
, BRW_REGISTER_TYPE_UD
),
1102 retype(op
[0], BRW_REGISTER_TYPE_UD
),
1103 brw_imm_ud(0x80000000));
1104 /* Do the actual F32 -> F16 -> F32 conversion */
1105 bld
.emit(BRW_OPCODE_F32TO16
, tmp16
, op
[0]);
1106 bld
.emit(BRW_OPCODE_F16TO32
, tmp32
, tmp16
);
1107 /* Select that or zero based on normal status */
1108 inst
= bld
.SEL(result
, zero
, tmp32
);
1109 inst
->predicate
= BRW_PREDICATE_NORMAL
;
1110 inst
->saturate
= instr
->dest
.saturate
;
1117 inst
= bld
.emit_minmax(result
, op
[0], op
[1], BRW_CONDITIONAL_L
);
1118 inst
->saturate
= instr
->dest
.saturate
;
1124 inst
= bld
.emit_minmax(result
, op
[0], op
[1], BRW_CONDITIONAL_GE
);
1125 inst
->saturate
= instr
->dest
.saturate
;
1128 case nir_op_pack_snorm_2x16
:
1129 case nir_op_pack_snorm_4x8
:
1130 case nir_op_pack_unorm_2x16
:
1131 case nir_op_pack_unorm_4x8
:
1132 case nir_op_unpack_snorm_2x16
:
1133 case nir_op_unpack_snorm_4x8
:
1134 case nir_op_unpack_unorm_2x16
:
1135 case nir_op_unpack_unorm_4x8
:
1136 case nir_op_unpack_half_2x16
:
1137 case nir_op_pack_half_2x16
:
1138 unreachable("not reached: should be handled by lower_packing_builtins");
1140 case nir_op_unpack_half_2x16_split_x
:
1141 inst
= bld
.emit(FS_OPCODE_UNPACK_HALF_2x16_SPLIT_X
, result
, op
[0]);
1142 inst
->saturate
= instr
->dest
.saturate
;
1144 case nir_op_unpack_half_2x16_split_y
:
1145 inst
= bld
.emit(FS_OPCODE_UNPACK_HALF_2x16_SPLIT_Y
, result
, op
[0]);
1146 inst
->saturate
= instr
->dest
.saturate
;
1149 case nir_op_pack_64_2x32_split
:
1150 bld
.emit(FS_OPCODE_PACK
, result
, op
[0], op
[1]);
1153 case nir_op_unpack_64_2x32_split_x
:
1154 case nir_op_unpack_64_2x32_split_y
: {
1155 if (instr
->op
== nir_op_unpack_64_2x32_split_x
)
1156 bld
.MOV(result
, subscript(op
[0], BRW_REGISTER_TYPE_UD
, 0));
1158 bld
.MOV(result
, subscript(op
[0], BRW_REGISTER_TYPE_UD
, 1));
1163 inst
= bld
.emit(SHADER_OPCODE_POW
, result
, op
[0], op
[1]);
1164 inst
->saturate
= instr
->dest
.saturate
;
1167 case nir_op_bitfield_reverse
:
1168 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1169 bld
.BFREV(result
, op
[0]);
1172 case nir_op_bit_count
:
1173 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1174 bld
.CBIT(result
, op
[0]);
1177 case nir_op_ufind_msb
: {
1178 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1179 emit_find_msb_using_lzd(bld
, result
, op
[0], false);
1183 case nir_op_ifind_msb
: {
1184 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1186 if (devinfo
->gen
< 7) {
1187 emit_find_msb_using_lzd(bld
, result
, op
[0], true);
1189 bld
.FBH(retype(result
, BRW_REGISTER_TYPE_UD
), op
[0]);
1191 /* FBH counts from the MSB side, while GLSL's findMSB() wants the
1192 * count from the LSB side. If FBH didn't return an error
1193 * (0xFFFFFFFF), then subtract the result from 31 to convert the MSB
1194 * count into an LSB count.
1196 bld
.CMP(bld
.null_reg_d(), result
, brw_imm_d(-1), BRW_CONDITIONAL_NZ
);
1198 inst
= bld
.ADD(result
, result
, brw_imm_d(31));
1199 inst
->predicate
= BRW_PREDICATE_NORMAL
;
1200 inst
->src
[0].negate
= true;
1205 case nir_op_find_lsb
:
1206 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1208 if (devinfo
->gen
< 7) {
1209 fs_reg temp
= vgrf(glsl_type::int_type
);
1211 /* (x & -x) generates a value that consists of only the LSB of x.
1212 * For all powers of 2, findMSB(y) == findLSB(y).
1214 fs_reg src
= retype(op
[0], BRW_REGISTER_TYPE_D
);
1215 fs_reg negated_src
= src
;
1217 /* One must be negated, and the other must be non-negated. It
1218 * doesn't matter which is which.
1220 negated_src
.negate
= true;
1223 bld
.AND(temp
, src
, negated_src
);
1224 emit_find_msb_using_lzd(bld
, result
, temp
, false);
1226 bld
.FBL(result
, op
[0]);
1230 case nir_op_ubitfield_extract
:
1231 case nir_op_ibitfield_extract
:
1232 unreachable("should have been lowered");
1235 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1236 bld
.BFE(result
, op
[2], op
[1], op
[0]);
1239 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1240 bld
.BFI1(result
, op
[0], op
[1]);
1243 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1244 bld
.BFI2(result
, op
[0], op
[1], op
[2]);
1247 case nir_op_bitfield_insert
:
1248 unreachable("not reached: should have been lowered");
1253 fs_reg shift_count
= op
[1];
1255 if (devinfo
->is_cherryview
|| gen_device_info_is_9lp(devinfo
)) {
1256 if (op
[1].file
== VGRF
&&
1257 (result
.type
== BRW_REGISTER_TYPE_Q
||
1258 result
.type
== BRW_REGISTER_TYPE_UQ
)) {
1259 shift_count
= fs_reg(VGRF
, alloc
.allocate(dispatch_width
/ 4),
1260 BRW_REGISTER_TYPE_UD
);
1261 shift_count
.stride
= 2;
1262 bld
.MOV(shift_count
, op
[1]);
1266 switch (instr
->op
) {
1268 bld
.SHL(result
, op
[0], shift_count
);
1271 bld
.ASR(result
, op
[0], shift_count
);
1274 bld
.SHR(result
, op
[0], shift_count
);
1277 unreachable("not reached");
1282 case nir_op_pack_half_2x16_split
:
1283 bld
.emit(FS_OPCODE_PACK_HALF_2x16_SPLIT
, result
, op
[0], op
[1]);
1287 inst
= bld
.MAD(result
, op
[2], op
[1], op
[0]);
1288 inst
->saturate
= instr
->dest
.saturate
;
1292 inst
= bld
.LRP(result
, op
[0], op
[1], op
[2]);
1293 inst
->saturate
= instr
->dest
.saturate
;
1297 if (optimize_frontfacing_ternary(instr
, result
))
1300 bld
.CMP(bld
.null_reg_d(), op
[0], brw_imm_d(0), BRW_CONDITIONAL_NZ
);
1301 inst
= bld
.SEL(result
, op
[1], op
[2]);
1302 inst
->predicate
= BRW_PREDICATE_NORMAL
;
1305 case nir_op_extract_u8
:
1306 case nir_op_extract_i8
: {
1307 const brw_reg_type type
= brw_int_type(1, instr
->op
== nir_op_extract_i8
);
1308 nir_const_value
*byte
= nir_src_as_const_value(instr
->src
[1].src
);
1309 assert(byte
!= NULL
);
1310 bld
.MOV(result
, subscript(op
[0], type
, byte
->u32
[0]));
1314 case nir_op_extract_u16
:
1315 case nir_op_extract_i16
: {
1316 const brw_reg_type type
= brw_int_type(2, instr
->op
== nir_op_extract_i16
);
1317 nir_const_value
*word
= nir_src_as_const_value(instr
->src
[1].src
);
1318 assert(word
!= NULL
);
1319 bld
.MOV(result
, subscript(op
[0], type
, word
->u32
[0]));
1324 unreachable("unhandled instruction");
1327 /* If we need to do a boolean resolve, replace the result with -(x & 1)
1328 * to sign extend the low bit to 0/~0
1330 if (devinfo
->gen
<= 5 &&
1331 (instr
->instr
.pass_flags
& BRW_NIR_BOOLEAN_MASK
) == BRW_NIR_BOOLEAN_NEEDS_RESOLVE
) {
1332 fs_reg masked
= vgrf(glsl_type::int_type
);
1333 bld
.AND(masked
, result
, brw_imm_d(1));
1334 masked
.negate
= true;
1335 bld
.MOV(retype(result
, BRW_REGISTER_TYPE_D
), masked
);
1340 fs_visitor::nir_emit_load_const(const fs_builder
&bld
,
1341 nir_load_const_instr
*instr
)
1343 const brw_reg_type reg_type
=
1344 instr
->def
.bit_size
== 32 ? BRW_REGISTER_TYPE_D
: BRW_REGISTER_TYPE_DF
;
1345 fs_reg reg
= bld
.vgrf(reg_type
, instr
->def
.num_components
);
1347 switch (instr
->def
.bit_size
) {
1349 for (unsigned i
= 0; i
< instr
->def
.num_components
; i
++)
1350 bld
.MOV(offset(reg
, bld
, i
), brw_imm_d(instr
->value
.i32
[i
]));
1354 for (unsigned i
= 0; i
< instr
->def
.num_components
; i
++)
1355 bld
.MOV(offset(reg
, bld
, i
),
1356 setup_imm_df(bld
, instr
->value
.f64
[i
]));
1360 unreachable("Invalid bit size");
1363 nir_ssa_values
[instr
->def
.index
] = reg
;
1367 fs_visitor::get_nir_src(const nir_src
&src
)
1371 if (src
.ssa
->parent_instr
->type
== nir_instr_type_ssa_undef
) {
1372 const brw_reg_type reg_type
= src
.ssa
->bit_size
== 32 ?
1373 BRW_REGISTER_TYPE_D
: BRW_REGISTER_TYPE_DF
;
1374 reg
= bld
.vgrf(reg_type
, src
.ssa
->num_components
);
1376 reg
= nir_ssa_values
[src
.ssa
->index
];
1379 /* We don't handle indirects on locals */
1380 assert(src
.reg
.indirect
== NULL
);
1381 reg
= offset(nir_locals
[src
.reg
.reg
->index
], bld
,
1382 src
.reg
.base_offset
* src
.reg
.reg
->num_components
);
1385 /* to avoid floating-point denorm flushing problems, set the type by
1386 * default to D - instructions that need floating point semantics will set
1387 * this to F if they need to
1389 return retype(reg
, BRW_REGISTER_TYPE_D
);
1393 * Return an IMM for constants; otherwise call get_nir_src() as normal.
1396 fs_visitor::get_nir_src_imm(const nir_src
&src
)
1398 nir_const_value
*val
= nir_src_as_const_value(src
);
1399 return val
? fs_reg(brw_imm_d(val
->i32
[0])) : get_nir_src(src
);
1403 fs_visitor::get_nir_dest(const nir_dest
&dest
)
1406 const brw_reg_type reg_type
=
1407 dest
.ssa
.bit_size
== 32 ? BRW_REGISTER_TYPE_F
: BRW_REGISTER_TYPE_DF
;
1408 nir_ssa_values
[dest
.ssa
.index
] =
1409 bld
.vgrf(reg_type
, dest
.ssa
.num_components
);
1410 return nir_ssa_values
[dest
.ssa
.index
];
1412 /* We don't handle indirects on locals */
1413 assert(dest
.reg
.indirect
== NULL
);
1414 return offset(nir_locals
[dest
.reg
.reg
->index
], bld
,
1415 dest
.reg
.base_offset
* dest
.reg
.reg
->num_components
);
1420 fs_visitor::get_nir_image_deref(const nir_deref_var
*deref
)
1422 fs_reg
image(UNIFORM
, deref
->var
->data
.driver_location
/ 4,
1423 BRW_REGISTER_TYPE_UD
);
1425 unsigned indirect_max
= 0;
1427 for (const nir_deref
*tail
= &deref
->deref
; tail
->child
;
1428 tail
= tail
->child
) {
1429 const nir_deref_array
*deref_array
= nir_deref_as_array(tail
->child
);
1430 assert(tail
->child
->deref_type
== nir_deref_type_array
);
1431 const unsigned size
= glsl_get_length(tail
->type
);
1432 const unsigned element_size
= type_size_scalar(deref_array
->deref
.type
);
1433 const unsigned base
= MIN2(deref_array
->base_offset
, size
- 1);
1434 image
= offset(image
, bld
, base
* element_size
);
1436 if (deref_array
->deref_array_type
== nir_deref_array_type_indirect
) {
1437 fs_reg tmp
= vgrf(glsl_type::uint_type
);
1439 /* Accessing an invalid surface index with the dataport can result
1440 * in a hang. According to the spec "if the index used to
1441 * select an individual element is negative or greater than or
1442 * equal to the size of the array, the results of the operation
1443 * are undefined but may not lead to termination" -- which is one
1444 * of the possible outcomes of the hang. Clamp the index to
1445 * prevent access outside of the array bounds.
1447 bld
.emit_minmax(tmp
, retype(get_nir_src(deref_array
->indirect
),
1448 BRW_REGISTER_TYPE_UD
),
1449 brw_imm_ud(size
- base
- 1), BRW_CONDITIONAL_L
);
1451 indirect_max
+= element_size
* (tail
->type
->length
- 1);
1453 bld
.MUL(tmp
, tmp
, brw_imm_ud(element_size
* 4));
1454 if (indirect
.file
== BAD_FILE
) {
1457 bld
.ADD(indirect
, indirect
, tmp
);
1462 if (indirect
.file
== BAD_FILE
) {
1465 /* Emit a pile of MOVs to load the uniform into a temporary. The
1466 * dead-code elimination pass will get rid of what we don't use.
1468 fs_reg tmp
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, BRW_IMAGE_PARAM_SIZE
);
1469 for (unsigned j
= 0; j
< BRW_IMAGE_PARAM_SIZE
; j
++) {
1470 bld
.emit(SHADER_OPCODE_MOV_INDIRECT
,
1471 offset(tmp
, bld
, j
), offset(image
, bld
, j
),
1472 indirect
, brw_imm_ud((indirect_max
+ 1) * 4));
1479 fs_visitor::emit_percomp(const fs_builder
&bld
, const fs_inst
&inst
,
1482 for (unsigned i
= 0; i
< 4; i
++) {
1483 if (!((wr_mask
>> i
) & 1))
1486 fs_inst
*new_inst
= new(mem_ctx
) fs_inst(inst
);
1487 new_inst
->dst
= offset(new_inst
->dst
, bld
, i
);
1488 for (unsigned j
= 0; j
< new_inst
->sources
; j
++)
1489 if (new_inst
->src
[j
].file
== VGRF
)
1490 new_inst
->src
[j
] = offset(new_inst
->src
[j
], bld
, i
);
1497 * Get the matching channel register datatype for an image intrinsic of the
1498 * specified GLSL image type.
1501 get_image_base_type(const glsl_type
*type
)
1503 switch ((glsl_base_type
)type
->sampled_type
) {
1504 case GLSL_TYPE_UINT
:
1505 return BRW_REGISTER_TYPE_UD
;
1507 return BRW_REGISTER_TYPE_D
;
1508 case GLSL_TYPE_FLOAT
:
1509 return BRW_REGISTER_TYPE_F
;
1511 unreachable("Not reached.");
1516 * Get the appropriate atomic op for an image atomic intrinsic.
1519 get_image_atomic_op(nir_intrinsic_op op
, const glsl_type
*type
)
1522 case nir_intrinsic_image_atomic_add
:
1524 case nir_intrinsic_image_atomic_min
:
1525 return (get_image_base_type(type
) == BRW_REGISTER_TYPE_D
?
1526 BRW_AOP_IMIN
: BRW_AOP_UMIN
);
1527 case nir_intrinsic_image_atomic_max
:
1528 return (get_image_base_type(type
) == BRW_REGISTER_TYPE_D
?
1529 BRW_AOP_IMAX
: BRW_AOP_UMAX
);
1530 case nir_intrinsic_image_atomic_and
:
1532 case nir_intrinsic_image_atomic_or
:
1534 case nir_intrinsic_image_atomic_xor
:
1536 case nir_intrinsic_image_atomic_exchange
:
1538 case nir_intrinsic_image_atomic_comp_swap
:
1539 return BRW_AOP_CMPWR
;
1541 unreachable("Not reachable.");
1546 emit_pixel_interpolater_send(const fs_builder
&bld
,
1551 glsl_interp_mode interpolation
)
1553 struct brw_wm_prog_data
*wm_prog_data
=
1554 brw_wm_prog_data(bld
.shader
->stage_prog_data
);
1559 if (src
.file
== BAD_FILE
) {
1561 payload
= bld
.vgrf(BRW_REGISTER_TYPE_F
, 1);
1565 mlen
= 2 * bld
.dispatch_width() / 8;
1568 inst
= bld
.emit(opcode
, dst
, payload
, desc
);
1570 /* 2 floats per slot returned */
1571 inst
->size_written
= 2 * dst
.component_size(inst
->exec_size
);
1572 inst
->pi_noperspective
= interpolation
== INTERP_MODE_NOPERSPECTIVE
;
1574 wm_prog_data
->pulls_bary
= true;
1580 * Computes 1 << x, given a D/UD register containing some value x.
1583 intexp2(const fs_builder
&bld
, const fs_reg
&x
)
1585 assert(x
.type
== BRW_REGISTER_TYPE_UD
|| x
.type
== BRW_REGISTER_TYPE_D
);
1587 fs_reg result
= bld
.vgrf(x
.type
, 1);
1588 fs_reg one
= bld
.vgrf(x
.type
, 1);
1590 bld
.MOV(one
, retype(brw_imm_d(1), one
.type
));
1591 bld
.SHL(result
, one
, x
);
1596 fs_visitor::emit_gs_end_primitive(const nir_src
&vertex_count_nir_src
)
1598 assert(stage
== MESA_SHADER_GEOMETRY
);
1600 struct brw_gs_prog_data
*gs_prog_data
= brw_gs_prog_data(prog_data
);
1602 if (gs_compile
->control_data_header_size_bits
== 0)
1605 /* We can only do EndPrimitive() functionality when the control data
1606 * consists of cut bits. Fortunately, the only time it isn't is when the
1607 * output type is points, in which case EndPrimitive() is a no-op.
1609 if (gs_prog_data
->control_data_format
!=
1610 GEN7_GS_CONTROL_DATA_FORMAT_GSCTL_CUT
) {
1614 /* Cut bits use one bit per vertex. */
1615 assert(gs_compile
->control_data_bits_per_vertex
== 1);
1617 fs_reg vertex_count
= get_nir_src(vertex_count_nir_src
);
1618 vertex_count
.type
= BRW_REGISTER_TYPE_UD
;
1620 /* Cut bit n should be set to 1 if EndPrimitive() was called after emitting
1621 * vertex n, 0 otherwise. So all we need to do here is mark bit
1622 * (vertex_count - 1) % 32 in the cut_bits register to indicate that
1623 * EndPrimitive() was called after emitting vertex (vertex_count - 1);
1624 * vec4_gs_visitor::emit_control_data_bits() will take care of the rest.
1626 * Note that if EndPrimitive() is called before emitting any vertices, this
1627 * will cause us to set bit 31 of the control_data_bits register to 1.
1628 * That's fine because:
1630 * - If max_vertices < 32, then vertex number 31 (zero-based) will never be
1631 * output, so the hardware will ignore cut bit 31.
1633 * - If max_vertices == 32, then vertex number 31 is guaranteed to be the
1634 * last vertex, so setting cut bit 31 has no effect (since the primitive
1635 * is automatically ended when the GS terminates).
1637 * - If max_vertices > 32, then the ir_emit_vertex visitor will reset the
1638 * control_data_bits register to 0 when the first vertex is emitted.
1641 const fs_builder abld
= bld
.annotate("end primitive");
1643 /* control_data_bits |= 1 << ((vertex_count - 1) % 32) */
1644 fs_reg prev_count
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
1645 abld
.ADD(prev_count
, vertex_count
, brw_imm_ud(0xffffffffu
));
1646 fs_reg mask
= intexp2(abld
, prev_count
);
1647 /* Note: we're relying on the fact that the GEN SHL instruction only pays
1648 * attention to the lower 5 bits of its second source argument, so on this
1649 * architecture, 1 << (vertex_count - 1) is equivalent to 1 <<
1650 * ((vertex_count - 1) % 32).
1652 abld
.OR(this->control_data_bits
, this->control_data_bits
, mask
);
1656 fs_visitor::emit_gs_control_data_bits(const fs_reg
&vertex_count
)
1658 assert(stage
== MESA_SHADER_GEOMETRY
);
1659 assert(gs_compile
->control_data_bits_per_vertex
!= 0);
1661 struct brw_gs_prog_data
*gs_prog_data
= brw_gs_prog_data(prog_data
);
1663 const fs_builder abld
= bld
.annotate("emit control data bits");
1664 const fs_builder fwa_bld
= bld
.exec_all();
1666 /* We use a single UD register to accumulate control data bits (32 bits
1667 * for each of the SIMD8 channels). So we need to write a DWord (32 bits)
1670 * Unfortunately, the URB_WRITE_SIMD8 message uses 128-bit (OWord) offsets.
1671 * We have select a 128-bit group via the Global and Per-Slot Offsets, then
1672 * use the Channel Mask phase to enable/disable which DWord within that
1673 * group to write. (Remember, different SIMD8 channels may have emitted
1674 * different numbers of vertices, so we may need per-slot offsets.)
1676 * Channel masking presents an annoying problem: we may have to replicate
1677 * the data up to 4 times:
1679 * Msg = Handles, Per-Slot Offsets, Channel Masks, Data, Data, Data, Data.
1681 * To avoid penalizing shaders that emit a small number of vertices, we
1682 * can avoid these sometimes: if the size of the control data header is
1683 * <= 128 bits, then there is only 1 OWord. All SIMD8 channels will land
1684 * land in the same 128-bit group, so we can skip per-slot offsets.
1686 * Similarly, if the control data header is <= 32 bits, there is only one
1687 * DWord, so we can skip channel masks.
1689 enum opcode opcode
= SHADER_OPCODE_URB_WRITE_SIMD8
;
1691 fs_reg channel_mask
, per_slot_offset
;
1693 if (gs_compile
->control_data_header_size_bits
> 32) {
1694 opcode
= SHADER_OPCODE_URB_WRITE_SIMD8_MASKED
;
1695 channel_mask
= vgrf(glsl_type::uint_type
);
1698 if (gs_compile
->control_data_header_size_bits
> 128) {
1699 opcode
= SHADER_OPCODE_URB_WRITE_SIMD8_MASKED_PER_SLOT
;
1700 per_slot_offset
= vgrf(glsl_type::uint_type
);
1703 /* Figure out which DWord we're trying to write to using the formula:
1705 * dword_index = (vertex_count - 1) * bits_per_vertex / 32
1707 * Since bits_per_vertex is a power of two, and is known at compile
1708 * time, this can be optimized to:
1710 * dword_index = (vertex_count - 1) >> (6 - log2(bits_per_vertex))
1712 if (opcode
!= SHADER_OPCODE_URB_WRITE_SIMD8
) {
1713 fs_reg dword_index
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
1714 fs_reg prev_count
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
1715 abld
.ADD(prev_count
, vertex_count
, brw_imm_ud(0xffffffffu
));
1716 unsigned log2_bits_per_vertex
=
1717 util_last_bit(gs_compile
->control_data_bits_per_vertex
);
1718 abld
.SHR(dword_index
, prev_count
, brw_imm_ud(6u - log2_bits_per_vertex
));
1720 if (per_slot_offset
.file
!= BAD_FILE
) {
1721 /* Set the per-slot offset to dword_index / 4, so that we'll write to
1722 * the appropriate OWord within the control data header.
1724 abld
.SHR(per_slot_offset
, dword_index
, brw_imm_ud(2u));
1727 /* Set the channel masks to 1 << (dword_index % 4), so that we'll
1728 * write to the appropriate DWORD within the OWORD.
1730 fs_reg channel
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
1731 fwa_bld
.AND(channel
, dword_index
, brw_imm_ud(3u));
1732 channel_mask
= intexp2(fwa_bld
, channel
);
1733 /* Then the channel masks need to be in bits 23:16. */
1734 fwa_bld
.SHL(channel_mask
, channel_mask
, brw_imm_ud(16u));
1737 /* Store the control data bits in the message payload and send it. */
1739 if (channel_mask
.file
!= BAD_FILE
)
1740 mlen
+= 4; /* channel masks, plus 3 extra copies of the data */
1741 if (per_slot_offset
.file
!= BAD_FILE
)
1744 fs_reg payload
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, mlen
);
1745 fs_reg
*sources
= ralloc_array(mem_ctx
, fs_reg
, mlen
);
1747 sources
[i
++] = fs_reg(retype(brw_vec8_grf(1, 0), BRW_REGISTER_TYPE_UD
));
1748 if (per_slot_offset
.file
!= BAD_FILE
)
1749 sources
[i
++] = per_slot_offset
;
1750 if (channel_mask
.file
!= BAD_FILE
)
1751 sources
[i
++] = channel_mask
;
1753 sources
[i
++] = this->control_data_bits
;
1756 abld
.LOAD_PAYLOAD(payload
, sources
, mlen
, mlen
);
1757 fs_inst
*inst
= abld
.emit(opcode
, reg_undef
, payload
);
1759 /* We need to increment Global Offset by 256-bits to make room for
1760 * Broadwell's extra "Vertex Count" payload at the beginning of the
1761 * URB entry. Since this is an OWord message, Global Offset is counted
1762 * in 128-bit units, so we must set it to 2.
1764 if (gs_prog_data
->static_vertex_count
== -1)
1769 fs_visitor::set_gs_stream_control_data_bits(const fs_reg
&vertex_count
,
1772 /* control_data_bits |= stream_id << ((2 * (vertex_count - 1)) % 32) */
1774 /* Note: we are calling this *before* increasing vertex_count, so
1775 * this->vertex_count == vertex_count - 1 in the formula above.
1778 /* Stream mode uses 2 bits per vertex */
1779 assert(gs_compile
->control_data_bits_per_vertex
== 2);
1781 /* Must be a valid stream */
1782 assert(stream_id
< MAX_VERTEX_STREAMS
);
1784 /* Control data bits are initialized to 0 so we don't have to set any
1785 * bits when sending vertices to stream 0.
1790 const fs_builder abld
= bld
.annotate("set stream control data bits", NULL
);
1792 /* reg::sid = stream_id */
1793 fs_reg sid
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
1794 abld
.MOV(sid
, brw_imm_ud(stream_id
));
1796 /* reg:shift_count = 2 * (vertex_count - 1) */
1797 fs_reg shift_count
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
1798 abld
.SHL(shift_count
, vertex_count
, brw_imm_ud(1u));
1800 /* Note: we're relying on the fact that the GEN SHL instruction only pays
1801 * attention to the lower 5 bits of its second source argument, so on this
1802 * architecture, stream_id << 2 * (vertex_count - 1) is equivalent to
1803 * stream_id << ((2 * (vertex_count - 1)) % 32).
1805 fs_reg mask
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
1806 abld
.SHL(mask
, sid
, shift_count
);
1807 abld
.OR(this->control_data_bits
, this->control_data_bits
, mask
);
1811 fs_visitor::emit_gs_vertex(const nir_src
&vertex_count_nir_src
,
1814 assert(stage
== MESA_SHADER_GEOMETRY
);
1816 struct brw_gs_prog_data
*gs_prog_data
= brw_gs_prog_data(prog_data
);
1818 fs_reg vertex_count
= get_nir_src(vertex_count_nir_src
);
1819 vertex_count
.type
= BRW_REGISTER_TYPE_UD
;
1821 /* Haswell and later hardware ignores the "Render Stream Select" bits
1822 * from the 3DSTATE_STREAMOUT packet when the SOL stage is disabled,
1823 * and instead sends all primitives down the pipeline for rasterization.
1824 * If the SOL stage is enabled, "Render Stream Select" is honored and
1825 * primitives bound to non-zero streams are discarded after stream output.
1827 * Since the only purpose of primives sent to non-zero streams is to
1828 * be recorded by transform feedback, we can simply discard all geometry
1829 * bound to these streams when transform feedback is disabled.
1831 if (stream_id
> 0 && !nir
->info
.has_transform_feedback_varyings
)
1834 /* If we're outputting 32 control data bits or less, then we can wait
1835 * until the shader is over to output them all. Otherwise we need to
1836 * output them as we go. Now is the time to do it, since we're about to
1837 * output the vertex_count'th vertex, so it's guaranteed that the
1838 * control data bits associated with the (vertex_count - 1)th vertex are
1841 if (gs_compile
->control_data_header_size_bits
> 32) {
1842 const fs_builder abld
=
1843 bld
.annotate("emit vertex: emit control data bits");
1845 /* Only emit control data bits if we've finished accumulating a batch
1846 * of 32 bits. This is the case when:
1848 * (vertex_count * bits_per_vertex) % 32 == 0
1850 * (in other words, when the last 5 bits of vertex_count *
1851 * bits_per_vertex are 0). Assuming bits_per_vertex == 2^n for some
1852 * integer n (which is always the case, since bits_per_vertex is
1853 * always 1 or 2), this is equivalent to requiring that the last 5-n
1854 * bits of vertex_count are 0:
1856 * vertex_count & (2^(5-n) - 1) == 0
1858 * 2^(5-n) == 2^5 / 2^n == 32 / bits_per_vertex, so this is
1861 * vertex_count & (32 / bits_per_vertex - 1) == 0
1863 * TODO: If vertex_count is an immediate, we could do some of this math
1864 * at compile time...
1867 abld
.AND(bld
.null_reg_d(), vertex_count
,
1868 brw_imm_ud(32u / gs_compile
->control_data_bits_per_vertex
- 1u));
1869 inst
->conditional_mod
= BRW_CONDITIONAL_Z
;
1871 abld
.IF(BRW_PREDICATE_NORMAL
);
1872 /* If vertex_count is 0, then no control data bits have been
1873 * accumulated yet, so we can skip emitting them.
1875 abld
.CMP(bld
.null_reg_d(), vertex_count
, brw_imm_ud(0u),
1876 BRW_CONDITIONAL_NEQ
);
1877 abld
.IF(BRW_PREDICATE_NORMAL
);
1878 emit_gs_control_data_bits(vertex_count
);
1879 abld
.emit(BRW_OPCODE_ENDIF
);
1881 /* Reset control_data_bits to 0 so we can start accumulating a new
1884 * Note: in the case where vertex_count == 0, this neutralizes the
1885 * effect of any call to EndPrimitive() that the shader may have
1886 * made before outputting its first vertex.
1888 inst
= abld
.MOV(this->control_data_bits
, brw_imm_ud(0u));
1889 inst
->force_writemask_all
= true;
1890 abld
.emit(BRW_OPCODE_ENDIF
);
1893 emit_urb_writes(vertex_count
);
1895 /* In stream mode we have to set control data bits for all vertices
1896 * unless we have disabled control data bits completely (which we do
1897 * do for GL_POINTS outputs that don't use streams).
1899 if (gs_compile
->control_data_header_size_bits
> 0 &&
1900 gs_prog_data
->control_data_format
==
1901 GEN7_GS_CONTROL_DATA_FORMAT_GSCTL_SID
) {
1902 set_gs_stream_control_data_bits(vertex_count
, stream_id
);
1907 fs_visitor::emit_gs_input_load(const fs_reg
&dst
,
1908 const nir_src
&vertex_src
,
1909 unsigned base_offset
,
1910 const nir_src
&offset_src
,
1911 unsigned num_components
,
1912 unsigned first_component
)
1914 struct brw_gs_prog_data
*gs_prog_data
= brw_gs_prog_data(prog_data
);
1916 nir_const_value
*vertex_const
= nir_src_as_const_value(vertex_src
);
1917 nir_const_value
*offset_const
= nir_src_as_const_value(offset_src
);
1918 const unsigned push_reg_count
= gs_prog_data
->base
.urb_read_length
* 8;
1920 /* TODO: figure out push input layout for invocations == 1 */
1921 /* TODO: make this work with 64-bit inputs */
1922 if (gs_prog_data
->invocations
== 1 &&
1923 type_sz(dst
.type
) <= 4 &&
1924 offset_const
!= NULL
&& vertex_const
!= NULL
&&
1925 4 * (base_offset
+ offset_const
->u32
[0]) < push_reg_count
) {
1926 int imm_offset
= (base_offset
+ offset_const
->u32
[0]) * 4 +
1927 vertex_const
->u32
[0] * push_reg_count
;
1928 for (unsigned i
= 0; i
< num_components
; i
++) {
1929 bld
.MOV(offset(dst
, bld
, i
),
1930 fs_reg(ATTR
, imm_offset
+ i
+ first_component
, dst
.type
));
1935 /* Resort to the pull model. Ensure the VUE handles are provided. */
1936 assert(gs_prog_data
->base
.include_vue_handles
);
1938 unsigned first_icp_handle
= gs_prog_data
->include_primitive_id
? 3 : 2;
1939 fs_reg icp_handle
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
1941 if (gs_prog_data
->invocations
== 1) {
1943 /* The vertex index is constant; just select the proper URB handle. */
1945 retype(brw_vec8_grf(first_icp_handle
+ vertex_const
->i32
[0], 0),
1946 BRW_REGISTER_TYPE_UD
);
1948 /* The vertex index is non-constant. We need to use indirect
1949 * addressing to fetch the proper URB handle.
1951 * First, we start with the sequence <7, 6, 5, 4, 3, 2, 1, 0>
1952 * indicating that channel <n> should read the handle from
1953 * DWord <n>. We convert that to bytes by multiplying by 4.
1955 * Next, we convert the vertex index to bytes by multiplying
1956 * by 32 (shifting by 5), and add the two together. This is
1957 * the final indirect byte offset.
1959 fs_reg sequence
= bld
.vgrf(BRW_REGISTER_TYPE_W
, 1);
1960 fs_reg channel_offsets
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
1961 fs_reg vertex_offset_bytes
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
1962 fs_reg icp_offset_bytes
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
1964 /* sequence = <7, 6, 5, 4, 3, 2, 1, 0> */
1965 bld
.MOV(sequence
, fs_reg(brw_imm_v(0x76543210)));
1966 /* channel_offsets = 4 * sequence = <28, 24, 20, 16, 12, 8, 4, 0> */
1967 bld
.SHL(channel_offsets
, sequence
, brw_imm_ud(2u));
1968 /* Convert vertex_index to bytes (multiply by 32) */
1969 bld
.SHL(vertex_offset_bytes
,
1970 retype(get_nir_src(vertex_src
), BRW_REGISTER_TYPE_UD
),
1972 bld
.ADD(icp_offset_bytes
, vertex_offset_bytes
, channel_offsets
);
1974 /* Use first_icp_handle as the base offset. There is one register
1975 * of URB handles per vertex, so inform the register allocator that
1976 * we might read up to nir->info.gs.vertices_in registers.
1978 bld
.emit(SHADER_OPCODE_MOV_INDIRECT
, icp_handle
,
1979 retype(brw_vec8_grf(first_icp_handle
, 0), icp_handle
.type
),
1980 fs_reg(icp_offset_bytes
),
1981 brw_imm_ud(nir
->info
.gs
.vertices_in
* REG_SIZE
));
1984 assert(gs_prog_data
->invocations
> 1);
1987 assert(devinfo
->gen
>= 9 || vertex_const
->i32
[0] <= 5);
1989 retype(brw_vec1_grf(first_icp_handle
+
1990 vertex_const
->i32
[0] / 8,
1991 vertex_const
->i32
[0] % 8),
1992 BRW_REGISTER_TYPE_UD
));
1994 /* The vertex index is non-constant. We need to use indirect
1995 * addressing to fetch the proper URB handle.
1998 fs_reg icp_offset_bytes
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2000 /* Convert vertex_index to bytes (multiply by 4) */
2001 bld
.SHL(icp_offset_bytes
,
2002 retype(get_nir_src(vertex_src
), BRW_REGISTER_TYPE_UD
),
2005 /* Use first_icp_handle as the base offset. There is one DWord
2006 * of URB handles per vertex, so inform the register allocator that
2007 * we might read up to ceil(nir->info.gs.vertices_in / 8) registers.
2009 bld
.emit(SHADER_OPCODE_MOV_INDIRECT
, icp_handle
,
2010 retype(brw_vec8_grf(first_icp_handle
, 0), icp_handle
.type
),
2011 fs_reg(icp_offset_bytes
),
2012 brw_imm_ud(DIV_ROUND_UP(nir
->info
.gs
.vertices_in
, 8) *
2019 fs_reg tmp_dst
= dst
;
2020 fs_reg indirect_offset
= get_nir_src(offset_src
);
2021 unsigned num_iterations
= 1;
2022 unsigned orig_num_components
= num_components
;
2024 if (type_sz(dst
.type
) == 8) {
2025 if (num_components
> 2) {
2029 fs_reg tmp
= fs_reg(VGRF
, alloc
.allocate(4), dst
.type
);
2031 first_component
= first_component
/ 2;
2034 for (unsigned iter
= 0; iter
< num_iterations
; iter
++) {
2036 /* Constant indexing - use global offset. */
2037 if (first_component
!= 0) {
2038 unsigned read_components
= num_components
+ first_component
;
2039 fs_reg tmp
= bld
.vgrf(dst
.type
, read_components
);
2040 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8
, tmp
, icp_handle
);
2041 inst
->size_written
= read_components
*
2042 tmp
.component_size(inst
->exec_size
);
2043 for (unsigned i
= 0; i
< num_components
; i
++) {
2044 bld
.MOV(offset(tmp_dst
, bld
, i
),
2045 offset(tmp
, bld
, i
+ first_component
));
2048 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8
, tmp_dst
,
2050 inst
->size_written
= num_components
*
2051 tmp_dst
.component_size(inst
->exec_size
);
2053 inst
->offset
= base_offset
+ offset_const
->u32
[0];
2056 /* Indirect indexing - use per-slot offsets as well. */
2057 const fs_reg srcs
[] = { icp_handle
, indirect_offset
};
2058 unsigned read_components
= num_components
+ first_component
;
2059 fs_reg tmp
= bld
.vgrf(dst
.type
, read_components
);
2060 fs_reg payload
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 2);
2061 bld
.LOAD_PAYLOAD(payload
, srcs
, ARRAY_SIZE(srcs
), 0);
2062 if (first_component
!= 0) {
2063 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT
, tmp
,
2065 inst
->size_written
= read_components
*
2066 tmp
.component_size(inst
->exec_size
);
2067 for (unsigned i
= 0; i
< num_components
; i
++) {
2068 bld
.MOV(offset(tmp_dst
, bld
, i
),
2069 offset(tmp
, bld
, i
+ first_component
));
2072 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT
, tmp_dst
,
2074 inst
->size_written
= num_components
*
2075 tmp_dst
.component_size(inst
->exec_size
);
2077 inst
->offset
= base_offset
;
2081 if (type_sz(dst
.type
) == 8) {
2082 shuffle_32bit_load_result_to_64bit_data(
2083 bld
, tmp_dst
, retype(tmp_dst
, BRW_REGISTER_TYPE_F
), num_components
);
2085 for (unsigned c
= 0; c
< num_components
; c
++)
2086 bld
.MOV(offset(dst
, bld
, iter
* 2 + c
), offset(tmp_dst
, bld
, c
));
2089 if (num_iterations
> 1) {
2090 num_components
= orig_num_components
- 2;
2094 fs_reg new_indirect
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2095 bld
.ADD(new_indirect
, indirect_offset
, brw_imm_ud(1u));
2096 indirect_offset
= new_indirect
;
2103 fs_visitor::get_indirect_offset(nir_intrinsic_instr
*instr
)
2105 nir_src
*offset_src
= nir_get_io_offset_src(instr
);
2106 nir_const_value
*const_value
= nir_src_as_const_value(*offset_src
);
2109 /* The only constant offset we should find is 0. brw_nir.c's
2110 * add_const_offset_to_base() will fold other constant offsets
2111 * into instr->const_index[0].
2113 assert(const_value
->u32
[0] == 0);
2117 return get_nir_src(*offset_src
);
2121 do_untyped_vector_read(const fs_builder
&bld
,
2123 const fs_reg surf_index
,
2124 const fs_reg offset_reg
,
2125 unsigned num_components
)
2127 if (type_sz(dest
.type
) == 4) {
2128 fs_reg read_result
= emit_untyped_read(bld
, surf_index
, offset_reg
,
2131 BRW_PREDICATE_NONE
);
2132 read_result
.type
= dest
.type
;
2133 for (unsigned i
= 0; i
< num_components
; i
++)
2134 bld
.MOV(offset(dest
, bld
, i
), offset(read_result
, bld
, i
));
2135 } else if (type_sz(dest
.type
) == 8) {
2136 /* Reading a dvec, so we need to:
2138 * 1. Multiply num_components by 2, to account for the fact that we
2139 * need to read 64-bit components.
2140 * 2. Shuffle the result of the load to form valid 64-bit elements
2141 * 3. Emit a second load (for components z/w) if needed.
2143 fs_reg read_offset
= bld
.vgrf(BRW_REGISTER_TYPE_UD
);
2144 bld
.MOV(read_offset
, offset_reg
);
2146 int iters
= num_components
<= 2 ? 1 : 2;
2148 /* Load the dvec, the first iteration loads components x/y, the second
2149 * iteration, if needed, loads components z/w
2151 for (int it
= 0; it
< iters
; it
++) {
2152 /* Compute number of components to read in this iteration */
2153 int iter_components
= MIN2(2, num_components
);
2154 num_components
-= iter_components
;
2156 /* Read. Since this message reads 32-bit components, we need to
2157 * read twice as many components.
2159 fs_reg read_result
= emit_untyped_read(bld
, surf_index
, read_offset
,
2161 iter_components
* 2,
2162 BRW_PREDICATE_NONE
);
2164 /* Shuffle the 32-bit load result into valid 64-bit data */
2165 const fs_reg packed_result
= bld
.vgrf(dest
.type
, iter_components
);
2166 shuffle_32bit_load_result_to_64bit_data(
2167 bld
, packed_result
, read_result
, iter_components
);
2169 /* Move each component to its destination */
2170 read_result
= retype(read_result
, BRW_REGISTER_TYPE_DF
);
2171 for (int c
= 0; c
< iter_components
; c
++) {
2172 bld
.MOV(offset(dest
, bld
, it
* 2 + c
),
2173 offset(packed_result
, bld
, c
));
2176 bld
.ADD(read_offset
, read_offset
, brw_imm_ud(16));
2179 unreachable("Unsupported type");
2184 fs_visitor::nir_emit_vs_intrinsic(const fs_builder
&bld
,
2185 nir_intrinsic_instr
*instr
)
2187 assert(stage
== MESA_SHADER_VERTEX
);
2190 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
2191 dest
= get_nir_dest(instr
->dest
);
2193 switch (instr
->intrinsic
) {
2194 case nir_intrinsic_load_vertex_id
:
2195 unreachable("should be lowered by lower_vertex_id()");
2197 case nir_intrinsic_load_vertex_id_zero_base
:
2198 case nir_intrinsic_load_base_vertex
:
2199 case nir_intrinsic_load_instance_id
:
2200 case nir_intrinsic_load_base_instance
:
2201 case nir_intrinsic_load_draw_id
: {
2202 gl_system_value sv
= nir_system_value_from_intrinsic(instr
->intrinsic
);
2203 fs_reg val
= nir_system_values
[sv
];
2204 assert(val
.file
!= BAD_FILE
);
2205 dest
.type
= val
.type
;
2210 case nir_intrinsic_load_input
: {
2211 fs_reg src
= fs_reg(ATTR
, nir_intrinsic_base(instr
) * 4, dest
.type
);
2212 unsigned first_component
= nir_intrinsic_component(instr
);
2213 unsigned num_components
= instr
->num_components
;
2214 enum brw_reg_type type
= dest
.type
;
2216 nir_const_value
*const_offset
= nir_src_as_const_value(instr
->src
[0]);
2217 assert(const_offset
&& "Indirect input loads not allowed");
2218 src
= offset(src
, bld
, const_offset
->u32
[0]);
2220 for (unsigned j
= 0; j
< num_components
; j
++) {
2221 bld
.MOV(offset(dest
, bld
, j
), offset(src
, bld
, j
+ first_component
));
2224 if (type
== BRW_REGISTER_TYPE_DF
) {
2225 /* Once the double vector is read, set again its original register
2226 * type to continue with normal execution.
2228 src
= retype(src
, type
);
2229 dest
= retype(dest
, type
);
2232 if (type_sz(src
.type
) == 8) {
2233 shuffle_32bit_load_result_to_64bit_data(bld
,
2235 retype(dest
, BRW_REGISTER_TYPE_F
),
2236 instr
->num_components
);
2242 nir_emit_intrinsic(bld
, instr
);
2248 fs_visitor::nir_emit_tcs_intrinsic(const fs_builder
&bld
,
2249 nir_intrinsic_instr
*instr
)
2251 assert(stage
== MESA_SHADER_TESS_CTRL
);
2252 struct brw_tcs_prog_key
*tcs_key
= (struct brw_tcs_prog_key
*) key
;
2253 struct brw_tcs_prog_data
*tcs_prog_data
= brw_tcs_prog_data(prog_data
);
2256 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
2257 dst
= get_nir_dest(instr
->dest
);
2259 switch (instr
->intrinsic
) {
2260 case nir_intrinsic_load_primitive_id
:
2261 bld
.MOV(dst
, fs_reg(brw_vec1_grf(0, 1)));
2263 case nir_intrinsic_load_invocation_id
:
2264 bld
.MOV(retype(dst
, invocation_id
.type
), invocation_id
);
2266 case nir_intrinsic_load_patch_vertices_in
:
2267 bld
.MOV(retype(dst
, BRW_REGISTER_TYPE_D
),
2268 brw_imm_d(tcs_key
->input_vertices
));
2271 case nir_intrinsic_barrier
: {
2272 if (tcs_prog_data
->instances
== 1)
2275 fs_reg m0
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2276 fs_reg m0_2
= component(m0
, 2);
2278 const fs_builder chanbld
= bld
.exec_all().group(1, 0);
2280 /* Zero the message header */
2281 bld
.exec_all().MOV(m0
, brw_imm_ud(0u));
2283 /* Copy "Barrier ID" from r0.2, bits 16:13 */
2284 chanbld
.AND(m0_2
, retype(brw_vec1_grf(0, 2), BRW_REGISTER_TYPE_UD
),
2285 brw_imm_ud(INTEL_MASK(16, 13)));
2287 /* Shift it up to bits 27:24. */
2288 chanbld
.SHL(m0_2
, m0_2
, brw_imm_ud(11));
2290 /* Set the Barrier Count and the enable bit */
2291 chanbld
.OR(m0_2
, m0_2
,
2292 brw_imm_ud(tcs_prog_data
->instances
<< 9 | (1 << 15)));
2294 bld
.emit(SHADER_OPCODE_BARRIER
, bld
.null_reg_ud(), m0
);
2298 case nir_intrinsic_load_input
:
2299 unreachable("nir_lower_io should never give us these.");
2302 case nir_intrinsic_load_per_vertex_input
: {
2303 fs_reg indirect_offset
= get_indirect_offset(instr
);
2304 unsigned imm_offset
= instr
->const_index
[0];
2306 const nir_src
&vertex_src
= instr
->src
[0];
2307 nir_const_value
*vertex_const
= nir_src_as_const_value(vertex_src
);
2314 /* Emit a MOV to resolve <0,1,0> regioning. */
2315 icp_handle
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2317 retype(brw_vec1_grf(1 + (vertex_const
->i32
[0] >> 3),
2318 vertex_const
->i32
[0] & 7),
2319 BRW_REGISTER_TYPE_UD
));
2320 } else if (tcs_prog_data
->instances
== 1 &&
2321 vertex_src
.is_ssa
&&
2322 vertex_src
.ssa
->parent_instr
->type
== nir_instr_type_intrinsic
&&
2323 nir_instr_as_intrinsic(vertex_src
.ssa
->parent_instr
)->intrinsic
== nir_intrinsic_load_invocation_id
) {
2324 /* For the common case of only 1 instance, an array index of
2325 * gl_InvocationID means reading g1. Skip all the indirect work.
2327 icp_handle
= retype(brw_vec8_grf(1, 0), BRW_REGISTER_TYPE_UD
);
2329 /* The vertex index is non-constant. We need to use indirect
2330 * addressing to fetch the proper URB handle.
2332 icp_handle
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2334 /* Each ICP handle is a single DWord (4 bytes) */
2335 fs_reg vertex_offset_bytes
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2336 bld
.SHL(vertex_offset_bytes
,
2337 retype(get_nir_src(vertex_src
), BRW_REGISTER_TYPE_UD
),
2340 /* Start at g1. We might read up to 4 registers. */
2341 bld
.emit(SHADER_OPCODE_MOV_INDIRECT
, icp_handle
,
2342 retype(brw_vec8_grf(1, 0), icp_handle
.type
), vertex_offset_bytes
,
2343 brw_imm_ud(4 * REG_SIZE
));
2346 /* We can only read two double components with each URB read, so
2347 * we send two read messages in that case, each one loading up to
2348 * two double components.
2350 unsigned num_iterations
= 1;
2351 unsigned num_components
= instr
->num_components
;
2352 unsigned first_component
= nir_intrinsic_component(instr
);
2353 fs_reg orig_dst
= dst
;
2354 if (type_sz(dst
.type
) == 8) {
2355 first_component
= first_component
/ 2;
2356 if (instr
->num_components
> 2) {
2361 fs_reg tmp
= fs_reg(VGRF
, alloc
.allocate(4), dst
.type
);
2365 for (unsigned iter
= 0; iter
< num_iterations
; iter
++) {
2366 if (indirect_offset
.file
== BAD_FILE
) {
2367 /* Constant indexing - use global offset. */
2368 if (first_component
!= 0) {
2369 unsigned read_components
= num_components
+ first_component
;
2370 fs_reg tmp
= bld
.vgrf(dst
.type
, read_components
);
2371 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8
, tmp
, icp_handle
);
2372 for (unsigned i
= 0; i
< num_components
; i
++) {
2373 bld
.MOV(offset(dst
, bld
, i
),
2374 offset(tmp
, bld
, i
+ first_component
));
2377 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8
, dst
, icp_handle
);
2379 inst
->offset
= imm_offset
;
2382 /* Indirect indexing - use per-slot offsets as well. */
2383 const fs_reg srcs
[] = { icp_handle
, indirect_offset
};
2384 fs_reg payload
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 2);
2385 bld
.LOAD_PAYLOAD(payload
, srcs
, ARRAY_SIZE(srcs
), 0);
2386 if (first_component
!= 0) {
2387 unsigned read_components
= num_components
+ first_component
;
2388 fs_reg tmp
= bld
.vgrf(dst
.type
, read_components
);
2389 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT
, tmp
,
2391 for (unsigned i
= 0; i
< num_components
; i
++) {
2392 bld
.MOV(offset(dst
, bld
, i
),
2393 offset(tmp
, bld
, i
+ first_component
));
2396 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT
, dst
,
2399 inst
->offset
= imm_offset
;
2402 inst
->size_written
= (num_components
+ first_component
) *
2403 inst
->dst
.component_size(inst
->exec_size
);
2405 /* If we are reading 64-bit data using 32-bit read messages we need
2406 * build proper 64-bit data elements by shuffling the low and high
2407 * 32-bit components around like we do for other things like UBOs
2410 if (type_sz(dst
.type
) == 8) {
2411 shuffle_32bit_load_result_to_64bit_data(
2412 bld
, dst
, retype(dst
, BRW_REGISTER_TYPE_F
), num_components
);
2414 for (unsigned c
= 0; c
< num_components
; c
++) {
2415 bld
.MOV(offset(orig_dst
, bld
, iter
* 2 + c
),
2416 offset(dst
, bld
, c
));
2420 /* Copy the temporary to the destination to deal with writemasking.
2422 * Also attempt to deal with gl_PointSize being in the .w component.
2424 if (inst
->offset
== 0 && indirect_offset
.file
== BAD_FILE
) {
2425 assert(type_sz(dst
.type
) < 8);
2426 inst
->dst
= bld
.vgrf(dst
.type
, 4);
2427 inst
->size_written
= 4 * REG_SIZE
;
2428 bld
.MOV(dst
, offset(inst
->dst
, bld
, 3));
2431 /* If we are loading double data and we need a second read message
2432 * adjust the write offset
2434 if (num_iterations
> 1) {
2435 num_components
= instr
->num_components
- 2;
2442 case nir_intrinsic_load_output
:
2443 case nir_intrinsic_load_per_vertex_output
: {
2444 fs_reg indirect_offset
= get_indirect_offset(instr
);
2445 unsigned imm_offset
= instr
->const_index
[0];
2446 unsigned first_component
= nir_intrinsic_component(instr
);
2449 if (indirect_offset
.file
== BAD_FILE
) {
2450 /* Replicate the patch handle to all enabled channels */
2451 fs_reg patch_handle
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2452 bld
.MOV(patch_handle
,
2453 retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_UD
));
2456 if (first_component
!= 0) {
2457 unsigned read_components
=
2458 instr
->num_components
+ first_component
;
2459 fs_reg tmp
= bld
.vgrf(dst
.type
, read_components
);
2460 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8
, tmp
,
2462 inst
->size_written
= read_components
* REG_SIZE
;
2463 for (unsigned i
= 0; i
< instr
->num_components
; i
++) {
2464 bld
.MOV(offset(dst
, bld
, i
),
2465 offset(tmp
, bld
, i
+ first_component
));
2468 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8
, dst
,
2470 inst
->size_written
= instr
->num_components
* REG_SIZE
;
2472 inst
->offset
= imm_offset
;
2476 /* Indirect indexing - use per-slot offsets as well. */
2477 const fs_reg srcs
[] = {
2478 retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_UD
),
2481 fs_reg payload
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 2);
2482 bld
.LOAD_PAYLOAD(payload
, srcs
, ARRAY_SIZE(srcs
), 0);
2483 if (first_component
!= 0) {
2484 unsigned read_components
=
2485 instr
->num_components
+ first_component
;
2486 fs_reg tmp
= bld
.vgrf(dst
.type
, read_components
);
2487 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT
, tmp
,
2489 inst
->size_written
= read_components
* REG_SIZE
;
2490 for (unsigned i
= 0; i
< instr
->num_components
; i
++) {
2491 bld
.MOV(offset(dst
, bld
, i
),
2492 offset(tmp
, bld
, i
+ first_component
));
2495 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT
, dst
,
2497 inst
->size_written
= instr
->num_components
* REG_SIZE
;
2499 inst
->offset
= imm_offset
;
2505 case nir_intrinsic_store_output
:
2506 case nir_intrinsic_store_per_vertex_output
: {
2507 fs_reg value
= get_nir_src(instr
->src
[0]);
2508 bool is_64bit
= (instr
->src
[0].is_ssa
?
2509 instr
->src
[0].ssa
->bit_size
: instr
->src
[0].reg
.reg
->bit_size
) == 64;
2510 fs_reg indirect_offset
= get_indirect_offset(instr
);
2511 unsigned imm_offset
= instr
->const_index
[0];
2512 unsigned swiz
= BRW_SWIZZLE_XYZW
;
2513 unsigned mask
= instr
->const_index
[1];
2514 unsigned header_regs
= 0;
2516 srcs
[header_regs
++] = retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_UD
);
2518 if (indirect_offset
.file
!= BAD_FILE
) {
2519 srcs
[header_regs
++] = indirect_offset
;
2525 unsigned num_components
= util_last_bit(mask
);
2528 /* We can only pack two 64-bit components in a single message, so send
2529 * 2 messages if we have more components
2531 unsigned num_iterations
= 1;
2532 unsigned iter_components
= num_components
;
2533 unsigned first_component
= nir_intrinsic_component(instr
);
2535 first_component
= first_component
/ 2;
2536 if (instr
->num_components
> 2) {
2538 iter_components
= 2;
2542 /* 64-bit data needs to me shuffled before we can write it to the URB.
2543 * We will use this temporary to shuffle the components in each
2547 fs_reg(VGRF
, alloc
.allocate(2 * iter_components
), value
.type
);
2549 mask
= mask
<< first_component
;
2551 for (unsigned iter
= 0; iter
< num_iterations
; iter
++) {
2552 if (!is_64bit
&& mask
!= WRITEMASK_XYZW
) {
2553 srcs
[header_regs
++] = brw_imm_ud(mask
<< 16);
2554 opcode
= indirect_offset
.file
!= BAD_FILE
?
2555 SHADER_OPCODE_URB_WRITE_SIMD8_MASKED_PER_SLOT
:
2556 SHADER_OPCODE_URB_WRITE_SIMD8_MASKED
;
2557 } else if (is_64bit
&& ((mask
& WRITEMASK_XY
) != WRITEMASK_XY
)) {
2558 /* Expand the 64-bit mask to 32-bit channels. We only handle
2559 * two channels in each iteration, so we only care about X/Y.
2561 unsigned mask32
= 0;
2562 if (mask
& WRITEMASK_X
)
2563 mask32
|= WRITEMASK_XY
;
2564 if (mask
& WRITEMASK_Y
)
2565 mask32
|= WRITEMASK_ZW
;
2567 /* If the mask does not include any of the channels X or Y there
2568 * is nothing to do in this iteration. Move on to the next couple
2569 * of 64-bit channels.
2577 srcs
[header_regs
++] = brw_imm_ud(mask32
<< 16);
2578 opcode
= indirect_offset
.file
!= BAD_FILE
?
2579 SHADER_OPCODE_URB_WRITE_SIMD8_MASKED_PER_SLOT
:
2580 SHADER_OPCODE_URB_WRITE_SIMD8_MASKED
;
2582 opcode
= indirect_offset
.file
!= BAD_FILE
?
2583 SHADER_OPCODE_URB_WRITE_SIMD8_PER_SLOT
:
2584 SHADER_OPCODE_URB_WRITE_SIMD8
;
2587 for (unsigned i
= 0; i
< iter_components
; i
++) {
2588 if (!(mask
& (1 << (i
+ first_component
))))
2592 srcs
[header_regs
+ i
+ first_component
] =
2593 offset(value
, bld
, BRW_GET_SWZ(swiz
, i
));
2595 /* We need to shuffle the 64-bit data to match the layout
2596 * expected by our 32-bit URB write messages. We use a temporary
2599 unsigned channel
= BRW_GET_SWZ(swiz
, iter
* 2 + i
);
2600 shuffle_64bit_data_for_32bit_write(bld
,
2601 retype(offset(tmp
, bld
, 2 * i
), BRW_REGISTER_TYPE_F
),
2602 retype(offset(value
, bld
, 2 * channel
), BRW_REGISTER_TYPE_DF
),
2605 /* Now copy the data to the destination */
2606 fs_reg dest
= fs_reg(VGRF
, alloc
.allocate(2), value
.type
);
2607 unsigned idx
= 2 * i
;
2608 bld
.MOV(dest
, offset(tmp
, bld
, idx
));
2609 bld
.MOV(offset(dest
, bld
, 1), offset(tmp
, bld
, idx
+ 1));
2610 srcs
[header_regs
+ idx
+ first_component
* 2] = dest
;
2611 srcs
[header_regs
+ idx
+ 1 + first_component
* 2] =
2612 offset(dest
, bld
, 1);
2617 header_regs
+ (is_64bit
? 2 * iter_components
: iter_components
) +
2618 (is_64bit
? 2 * first_component
: first_component
);
2620 bld
.vgrf(BRW_REGISTER_TYPE_UD
, mlen
);
2621 bld
.LOAD_PAYLOAD(payload
, srcs
, mlen
, header_regs
);
2623 fs_inst
*inst
= bld
.emit(opcode
, bld
.null_reg_ud(), payload
);
2624 inst
->offset
= imm_offset
;
2627 /* If this is a 64-bit attribute, select the next two 64-bit channels
2628 * to be handled in the next iteration.
2639 nir_emit_intrinsic(bld
, instr
);
2645 fs_visitor::nir_emit_tes_intrinsic(const fs_builder
&bld
,
2646 nir_intrinsic_instr
*instr
)
2648 assert(stage
== MESA_SHADER_TESS_EVAL
);
2649 struct brw_tes_prog_data
*tes_prog_data
= brw_tes_prog_data(prog_data
);
2652 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
2653 dest
= get_nir_dest(instr
->dest
);
2655 switch (instr
->intrinsic
) {
2656 case nir_intrinsic_load_primitive_id
:
2657 bld
.MOV(dest
, fs_reg(brw_vec1_grf(0, 1)));
2659 case nir_intrinsic_load_tess_coord
:
2660 /* gl_TessCoord is part of the payload in g1-3 */
2661 for (unsigned i
= 0; i
< 3; i
++) {
2662 bld
.MOV(offset(dest
, bld
, i
), fs_reg(brw_vec8_grf(1 + i
, 0)));
2666 case nir_intrinsic_load_input
:
2667 case nir_intrinsic_load_per_vertex_input
: {
2668 fs_reg indirect_offset
= get_indirect_offset(instr
);
2669 unsigned imm_offset
= instr
->const_index
[0];
2670 unsigned first_component
= nir_intrinsic_component(instr
);
2672 if (type_sz(dest
.type
) == 8) {
2673 first_component
= first_component
/ 2;
2677 if (indirect_offset
.file
== BAD_FILE
) {
2678 /* Arbitrarily only push up to 32 vec4 slots worth of data,
2679 * which is 16 registers (since each holds 2 vec4 slots).
2681 unsigned slot_count
= 1;
2682 if (type_sz(dest
.type
) == 8 && instr
->num_components
> 2)
2685 const unsigned max_push_slots
= 32;
2686 if (imm_offset
+ slot_count
<= max_push_slots
) {
2687 fs_reg src
= fs_reg(ATTR
, imm_offset
/ 2, dest
.type
);
2688 for (int i
= 0; i
< instr
->num_components
; i
++) {
2689 unsigned comp
= 16 / type_sz(dest
.type
) * (imm_offset
% 2) +
2690 i
+ first_component
;
2691 bld
.MOV(offset(dest
, bld
, i
), component(src
, comp
));
2694 tes_prog_data
->base
.urb_read_length
=
2695 MAX2(tes_prog_data
->base
.urb_read_length
,
2696 DIV_ROUND_UP(imm_offset
+ slot_count
, 2));
2698 /* Replicate the patch handle to all enabled channels */
2699 const fs_reg srcs
[] = {
2700 retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_UD
)
2702 fs_reg patch_handle
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2703 bld
.LOAD_PAYLOAD(patch_handle
, srcs
, ARRAY_SIZE(srcs
), 0);
2705 if (first_component
!= 0) {
2706 unsigned read_components
=
2707 instr
->num_components
+ first_component
;
2708 fs_reg tmp
= bld
.vgrf(dest
.type
, read_components
);
2709 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8
, tmp
,
2711 inst
->size_written
= read_components
* REG_SIZE
;
2712 for (unsigned i
= 0; i
< instr
->num_components
; i
++) {
2713 bld
.MOV(offset(dest
, bld
, i
),
2714 offset(tmp
, bld
, i
+ first_component
));
2717 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8
, dest
,
2719 inst
->size_written
= instr
->num_components
* REG_SIZE
;
2722 inst
->offset
= imm_offset
;
2725 /* Indirect indexing - use per-slot offsets as well. */
2727 /* We can only read two double components with each URB read, so
2728 * we send two read messages in that case, each one loading up to
2729 * two double components.
2731 unsigned num_iterations
= 1;
2732 unsigned num_components
= instr
->num_components
;
2733 fs_reg orig_dest
= dest
;
2734 if (type_sz(dest
.type
) == 8) {
2735 if (instr
->num_components
> 2) {
2739 fs_reg tmp
= fs_reg(VGRF
, alloc
.allocate(4), dest
.type
);
2743 for (unsigned iter
= 0; iter
< num_iterations
; iter
++) {
2744 const fs_reg srcs
[] = {
2745 retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_UD
),
2748 fs_reg payload
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 2);
2749 bld
.LOAD_PAYLOAD(payload
, srcs
, ARRAY_SIZE(srcs
), 0);
2751 if (first_component
!= 0) {
2752 unsigned read_components
=
2753 num_components
+ first_component
;
2754 fs_reg tmp
= bld
.vgrf(dest
.type
, read_components
);
2755 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT
, tmp
,
2757 for (unsigned i
= 0; i
< num_components
; i
++) {
2758 bld
.MOV(offset(dest
, bld
, i
),
2759 offset(tmp
, bld
, i
+ first_component
));
2762 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT
, dest
,
2766 inst
->offset
= imm_offset
;
2767 inst
->size_written
= (num_components
+ first_component
) *
2768 inst
->dst
.component_size(inst
->exec_size
);
2770 /* If we are reading 64-bit data using 32-bit read messages we need
2771 * build proper 64-bit data elements by shuffling the low and high
2772 * 32-bit components around like we do for other things like UBOs
2775 if (type_sz(dest
.type
) == 8) {
2776 shuffle_32bit_load_result_to_64bit_data(
2777 bld
, dest
, retype(dest
, BRW_REGISTER_TYPE_F
), num_components
);
2779 for (unsigned c
= 0; c
< num_components
; c
++) {
2780 bld
.MOV(offset(orig_dest
, bld
, iter
* 2 + c
),
2781 offset(dest
, bld
, c
));
2785 /* If we are loading double data and we need a second read message
2788 if (num_iterations
> 1) {
2789 num_components
= instr
->num_components
- 2;
2797 nir_emit_intrinsic(bld
, instr
);
2803 fs_visitor::nir_emit_gs_intrinsic(const fs_builder
&bld
,
2804 nir_intrinsic_instr
*instr
)
2806 assert(stage
== MESA_SHADER_GEOMETRY
);
2807 fs_reg indirect_offset
;
2810 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
2811 dest
= get_nir_dest(instr
->dest
);
2813 switch (instr
->intrinsic
) {
2814 case nir_intrinsic_load_primitive_id
:
2815 assert(stage
== MESA_SHADER_GEOMETRY
);
2816 assert(brw_gs_prog_data(prog_data
)->include_primitive_id
);
2817 bld
.MOV(retype(dest
, BRW_REGISTER_TYPE_UD
),
2818 retype(fs_reg(brw_vec8_grf(2, 0)), BRW_REGISTER_TYPE_UD
));
2821 case nir_intrinsic_load_input
:
2822 unreachable("load_input intrinsics are invalid for the GS stage");
2824 case nir_intrinsic_load_per_vertex_input
:
2825 emit_gs_input_load(dest
, instr
->src
[0], instr
->const_index
[0],
2826 instr
->src
[1], instr
->num_components
,
2827 nir_intrinsic_component(instr
));
2830 case nir_intrinsic_emit_vertex_with_counter
:
2831 emit_gs_vertex(instr
->src
[0], instr
->const_index
[0]);
2834 case nir_intrinsic_end_primitive_with_counter
:
2835 emit_gs_end_primitive(instr
->src
[0]);
2838 case nir_intrinsic_set_vertex_count
:
2839 bld
.MOV(this->final_gs_vertex_count
, get_nir_src(instr
->src
[0]));
2842 case nir_intrinsic_load_invocation_id
: {
2843 fs_reg val
= nir_system_values
[SYSTEM_VALUE_INVOCATION_ID
];
2844 assert(val
.file
!= BAD_FILE
);
2845 dest
.type
= val
.type
;
2851 nir_emit_intrinsic(bld
, instr
);
2857 * Fetch the current render target layer index.
2860 fetch_render_target_array_index(const fs_builder
&bld
)
2862 if (bld
.shader
->devinfo
->gen
>= 6) {
2863 /* The render target array index is provided in the thread payload as
2864 * bits 26:16 of r0.0.
2866 const fs_reg idx
= bld
.vgrf(BRW_REGISTER_TYPE_UD
);
2867 bld
.AND(idx
, brw_uw1_reg(BRW_GENERAL_REGISTER_FILE
, 0, 1),
2871 /* Pre-SNB we only ever render into the first layer of the framebuffer
2872 * since layered rendering is not implemented.
2874 return brw_imm_ud(0);
2879 * Fake non-coherent framebuffer read implemented using TXF to fetch from the
2880 * framebuffer at the current fragment coordinates and sample index.
2883 fs_visitor::emit_non_coherent_fb_read(const fs_builder
&bld
, const fs_reg
&dst
,
2886 const struct gen_device_info
*devinfo
= bld
.shader
->devinfo
;
2888 assert(bld
.shader
->stage
== MESA_SHADER_FRAGMENT
);
2889 const brw_wm_prog_key
*wm_key
=
2890 reinterpret_cast<const brw_wm_prog_key
*>(key
);
2891 assert(!wm_key
->coherent_fb_fetch
);
2892 const struct brw_wm_prog_data
*wm_prog_data
=
2893 brw_wm_prog_data(stage_prog_data
);
2895 /* Calculate the surface index relative to the start of the texture binding
2896 * table block, since that's what the texturing messages expect.
2898 const unsigned surface
= target
+
2899 wm_prog_data
->binding_table
.render_target_read_start
-
2900 wm_prog_data
->base
.binding_table
.texture_start
;
2902 brw_mark_surface_used(
2903 bld
.shader
->stage_prog_data
,
2904 wm_prog_data
->binding_table
.render_target_read_start
+ target
);
2906 /* Calculate the fragment coordinates. */
2907 const fs_reg coords
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 3);
2908 bld
.MOV(offset(coords
, bld
, 0), pixel_x
);
2909 bld
.MOV(offset(coords
, bld
, 1), pixel_y
);
2910 bld
.MOV(offset(coords
, bld
, 2), fetch_render_target_array_index(bld
));
2912 /* Calculate the sample index and MCS payload when multisampling. Luckily
2913 * the MCS fetch message behaves deterministically for UMS surfaces, so it
2914 * shouldn't be necessary to recompile based on whether the framebuffer is
2917 if (wm_key
->multisample_fbo
&&
2918 nir_system_values
[SYSTEM_VALUE_SAMPLE_ID
].file
== BAD_FILE
)
2919 nir_system_values
[SYSTEM_VALUE_SAMPLE_ID
] = *emit_sampleid_setup();
2921 const fs_reg sample
= nir_system_values
[SYSTEM_VALUE_SAMPLE_ID
];
2922 const fs_reg mcs
= wm_key
->multisample_fbo
?
2923 emit_mcs_fetch(coords
, 3, brw_imm_ud(surface
)) : fs_reg();
2925 /* Use either a normal or a CMS texel fetch message depending on whether
2926 * the framebuffer is single or multisample. On SKL+ use the wide CMS
2927 * message just in case the framebuffer uses 16x multisampling, it should
2928 * be equivalent to the normal CMS fetch for lower multisampling modes.
2930 const opcode op
= !wm_key
->multisample_fbo
? SHADER_OPCODE_TXF_LOGICAL
:
2931 devinfo
->gen
>= 9 ? SHADER_OPCODE_TXF_CMS_W_LOGICAL
:
2932 SHADER_OPCODE_TXF_CMS_LOGICAL
;
2934 /* Emit the instruction. */
2935 const fs_reg srcs
[] = { coords
, fs_reg(), brw_imm_ud(0), fs_reg(),
2937 brw_imm_ud(surface
), brw_imm_ud(0),
2938 fs_reg(), brw_imm_ud(3), brw_imm_ud(0) };
2939 STATIC_ASSERT(ARRAY_SIZE(srcs
) == TEX_LOGICAL_NUM_SRCS
);
2941 fs_inst
*inst
= bld
.emit(op
, dst
, srcs
, ARRAY_SIZE(srcs
));
2942 inst
->size_written
= 4 * inst
->dst
.component_size(inst
->exec_size
);
2948 * Actual coherent framebuffer read implemented using the native render target
2949 * read message. Requires SKL+.
2952 emit_coherent_fb_read(const fs_builder
&bld
, const fs_reg
&dst
, unsigned target
)
2954 assert(bld
.shader
->devinfo
->gen
>= 9);
2955 fs_inst
*inst
= bld
.emit(FS_OPCODE_FB_READ_LOGICAL
, dst
);
2956 inst
->target
= target
;
2957 inst
->size_written
= 4 * inst
->dst
.component_size(inst
->exec_size
);
2963 alloc_temporary(const fs_builder
&bld
, unsigned size
, fs_reg
*regs
, unsigned n
)
2965 if (n
&& regs
[0].file
!= BAD_FILE
) {
2969 const fs_reg tmp
= bld
.vgrf(BRW_REGISTER_TYPE_F
, size
);
2971 for (unsigned i
= 0; i
< n
; i
++)
2979 alloc_frag_output(fs_visitor
*v
, unsigned location
)
2981 assert(v
->stage
== MESA_SHADER_FRAGMENT
);
2982 const brw_wm_prog_key
*const key
=
2983 reinterpret_cast<const brw_wm_prog_key
*>(v
->key
);
2984 const unsigned l
= GET_FIELD(location
, BRW_NIR_FRAG_OUTPUT_LOCATION
);
2985 const unsigned i
= GET_FIELD(location
, BRW_NIR_FRAG_OUTPUT_INDEX
);
2987 if (i
> 0 || (key
->force_dual_color_blend
&& l
== FRAG_RESULT_DATA1
))
2988 return alloc_temporary(v
->bld
, 4, &v
->dual_src_output
, 1);
2990 else if (l
== FRAG_RESULT_COLOR
)
2991 return alloc_temporary(v
->bld
, 4, v
->outputs
,
2992 MAX2(key
->nr_color_regions
, 1));
2994 else if (l
== FRAG_RESULT_DEPTH
)
2995 return alloc_temporary(v
->bld
, 1, &v
->frag_depth
, 1);
2997 else if (l
== FRAG_RESULT_STENCIL
)
2998 return alloc_temporary(v
->bld
, 1, &v
->frag_stencil
, 1);
3000 else if (l
== FRAG_RESULT_SAMPLE_MASK
)
3001 return alloc_temporary(v
->bld
, 1, &v
->sample_mask
, 1);
3003 else if (l
>= FRAG_RESULT_DATA0
&&
3004 l
< FRAG_RESULT_DATA0
+ BRW_MAX_DRAW_BUFFERS
)
3005 return alloc_temporary(v
->bld
, 4,
3006 &v
->outputs
[l
- FRAG_RESULT_DATA0
], 1);
3009 unreachable("Invalid location");
3013 fs_visitor::nir_emit_fs_intrinsic(const fs_builder
&bld
,
3014 nir_intrinsic_instr
*instr
)
3016 assert(stage
== MESA_SHADER_FRAGMENT
);
3019 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
3020 dest
= get_nir_dest(instr
->dest
);
3022 switch (instr
->intrinsic
) {
3023 case nir_intrinsic_load_front_face
:
3024 bld
.MOV(retype(dest
, BRW_REGISTER_TYPE_D
),
3025 *emit_frontfacing_interpolation());
3028 case nir_intrinsic_load_sample_pos
: {
3029 fs_reg sample_pos
= nir_system_values
[SYSTEM_VALUE_SAMPLE_POS
];
3030 assert(sample_pos
.file
!= BAD_FILE
);
3031 dest
.type
= sample_pos
.type
;
3032 bld
.MOV(dest
, sample_pos
);
3033 bld
.MOV(offset(dest
, bld
, 1), offset(sample_pos
, bld
, 1));
3037 case nir_intrinsic_load_layer_id
:
3038 dest
.type
= BRW_REGISTER_TYPE_UD
;
3039 bld
.MOV(dest
, fetch_render_target_array_index(bld
));
3042 case nir_intrinsic_load_helper_invocation
:
3043 case nir_intrinsic_load_sample_mask_in
:
3044 case nir_intrinsic_load_sample_id
: {
3045 gl_system_value sv
= nir_system_value_from_intrinsic(instr
->intrinsic
);
3046 fs_reg val
= nir_system_values
[sv
];
3047 assert(val
.file
!= BAD_FILE
);
3048 dest
.type
= val
.type
;
3053 case nir_intrinsic_store_output
: {
3054 const fs_reg src
= get_nir_src(instr
->src
[0]);
3055 const nir_const_value
*const_offset
= nir_src_as_const_value(instr
->src
[1]);
3056 assert(const_offset
&& "Indirect output stores not allowed");
3057 const unsigned location
= nir_intrinsic_base(instr
) +
3058 SET_FIELD(const_offset
->u32
[0], BRW_NIR_FRAG_OUTPUT_LOCATION
);
3059 const fs_reg new_dest
= retype(alloc_frag_output(this, location
),
3062 for (unsigned j
= 0; j
< instr
->num_components
; j
++)
3063 bld
.MOV(offset(new_dest
, bld
, nir_intrinsic_component(instr
) + j
),
3064 offset(src
, bld
, j
));
3069 case nir_intrinsic_load_output
: {
3070 const unsigned l
= GET_FIELD(nir_intrinsic_base(instr
),
3071 BRW_NIR_FRAG_OUTPUT_LOCATION
);
3072 assert(l
>= FRAG_RESULT_DATA0
);
3073 nir_const_value
*const_offset
= nir_src_as_const_value(instr
->src
[0]);
3074 assert(const_offset
&& "Indirect output loads not allowed");
3075 const unsigned target
= l
- FRAG_RESULT_DATA0
+ const_offset
->u32
[0];
3076 const fs_reg tmp
= bld
.vgrf(dest
.type
, 4);
3078 if (reinterpret_cast<const brw_wm_prog_key
*>(key
)->coherent_fb_fetch
)
3079 emit_coherent_fb_read(bld
, tmp
, target
);
3081 emit_non_coherent_fb_read(bld
, tmp
, target
);
3083 for (unsigned j
= 0; j
< instr
->num_components
; j
++) {
3084 bld
.MOV(offset(dest
, bld
, j
),
3085 offset(tmp
, bld
, nir_intrinsic_component(instr
) + j
));
3091 case nir_intrinsic_discard
:
3092 case nir_intrinsic_discard_if
: {
3093 /* We track our discarded pixels in f0.1. By predicating on it, we can
3094 * update just the flag bits that aren't yet discarded. If there's no
3095 * condition, we emit a CMP of g0 != g0, so all currently executing
3096 * channels will get turned off.
3099 if (instr
->intrinsic
== nir_intrinsic_discard_if
) {
3100 cmp
= bld
.CMP(bld
.null_reg_f(), get_nir_src(instr
->src
[0]),
3101 brw_imm_d(0), BRW_CONDITIONAL_Z
);
3103 fs_reg some_reg
= fs_reg(retype(brw_vec8_grf(0, 0),
3104 BRW_REGISTER_TYPE_UW
));
3105 cmp
= bld
.CMP(bld
.null_reg_f(), some_reg
, some_reg
, BRW_CONDITIONAL_NZ
);
3107 cmp
->predicate
= BRW_PREDICATE_NORMAL
;
3108 cmp
->flag_subreg
= 1;
3110 if (devinfo
->gen
>= 6) {
3111 emit_discard_jump();
3116 case nir_intrinsic_load_input
: {
3117 /* load_input is only used for flat inputs */
3118 unsigned base
= nir_intrinsic_base(instr
);
3119 unsigned component
= nir_intrinsic_component(instr
);
3120 unsigned num_components
= instr
->num_components
;
3121 enum brw_reg_type type
= dest
.type
;
3123 /* Special case fields in the VUE header */
3124 if (base
== VARYING_SLOT_LAYER
)
3126 else if (base
== VARYING_SLOT_VIEWPORT
)
3129 if (nir_dest_bit_size(instr
->dest
) == 64) {
3130 /* const_index is in 32-bit type size units that could not be aligned
3131 * with DF. We need to read the double vector as if it was a float
3132 * vector of twice the number of components to fetch the right data.
3134 type
= BRW_REGISTER_TYPE_F
;
3135 num_components
*= 2;
3138 for (unsigned int i
= 0; i
< num_components
; i
++) {
3139 struct brw_reg interp
= interp_reg(base
, component
+ i
);
3140 interp
= suboffset(interp
, 3);
3141 bld
.emit(FS_OPCODE_CINTERP
, offset(retype(dest
, type
), bld
, i
),
3142 retype(fs_reg(interp
), type
));
3145 if (nir_dest_bit_size(instr
->dest
) == 64) {
3146 shuffle_32bit_load_result_to_64bit_data(bld
,
3149 instr
->num_components
);
3154 case nir_intrinsic_load_barycentric_pixel
:
3155 case nir_intrinsic_load_barycentric_centroid
:
3156 case nir_intrinsic_load_barycentric_sample
:
3157 /* Do nothing - load_interpolated_input handling will handle it later. */
3160 case nir_intrinsic_load_barycentric_at_sample
: {
3161 const glsl_interp_mode interpolation
=
3162 (enum glsl_interp_mode
) nir_intrinsic_interp_mode(instr
);
3164 nir_const_value
*const_sample
= nir_src_as_const_value(instr
->src
[0]);
3167 unsigned msg_data
= const_sample
->i32
[0] << 4;
3169 emit_pixel_interpolater_send(bld
,
3170 FS_OPCODE_INTERPOLATE_AT_SAMPLE
,
3173 brw_imm_ud(msg_data
),
3176 const fs_reg sample_src
= retype(get_nir_src(instr
->src
[0]),
3177 BRW_REGISTER_TYPE_UD
);
3179 if (nir_src_is_dynamically_uniform(instr
->src
[0])) {
3180 const fs_reg sample_id
= bld
.emit_uniformize(sample_src
);
3181 const fs_reg msg_data
= vgrf(glsl_type::uint_type
);
3182 bld
.exec_all().group(1, 0)
3183 .SHL(msg_data
, sample_id
, brw_imm_ud(4u));
3184 emit_pixel_interpolater_send(bld
,
3185 FS_OPCODE_INTERPOLATE_AT_SAMPLE
,
3191 /* Make a loop that sends a message to the pixel interpolater
3192 * for the sample number in each live channel. If there are
3193 * multiple channels with the same sample number then these
3194 * will be handled simultaneously with a single interation of
3197 bld
.emit(BRW_OPCODE_DO
);
3199 /* Get the next live sample number into sample_id_reg */
3200 const fs_reg sample_id
= bld
.emit_uniformize(sample_src
);
3202 /* Set the flag register so that we can perform the send
3203 * message on all channels that have the same sample number
3205 bld
.CMP(bld
.null_reg_ud(),
3206 sample_src
, sample_id
,
3207 BRW_CONDITIONAL_EQ
);
3208 const fs_reg msg_data
= vgrf(glsl_type::uint_type
);
3209 bld
.exec_all().group(1, 0)
3210 .SHL(msg_data
, sample_id
, brw_imm_ud(4u));
3212 emit_pixel_interpolater_send(bld
,
3213 FS_OPCODE_INTERPOLATE_AT_SAMPLE
,
3218 set_predicate(BRW_PREDICATE_NORMAL
, inst
);
3220 /* Continue the loop if there are any live channels left */
3221 set_predicate_inv(BRW_PREDICATE_NORMAL
,
3223 bld
.emit(BRW_OPCODE_WHILE
));
3229 case nir_intrinsic_load_barycentric_at_offset
: {
3230 const glsl_interp_mode interpolation
=
3231 (enum glsl_interp_mode
) nir_intrinsic_interp_mode(instr
);
3233 nir_const_value
*const_offset
= nir_src_as_const_value(instr
->src
[0]);
3236 unsigned off_x
= MIN2((int)(const_offset
->f32
[0] * 16), 7) & 0xf;
3237 unsigned off_y
= MIN2((int)(const_offset
->f32
[1] * 16), 7) & 0xf;
3239 emit_pixel_interpolater_send(bld
,
3240 FS_OPCODE_INTERPOLATE_AT_SHARED_OFFSET
,
3243 brw_imm_ud(off_x
| (off_y
<< 4)),
3246 fs_reg src
= vgrf(glsl_type::ivec2_type
);
3247 fs_reg offset_src
= retype(get_nir_src(instr
->src
[0]),
3248 BRW_REGISTER_TYPE_F
);
3249 for (int i
= 0; i
< 2; i
++) {
3250 fs_reg temp
= vgrf(glsl_type::float_type
);
3251 bld
.MUL(temp
, offset(offset_src
, bld
, i
), brw_imm_f(16.0f
));
3252 fs_reg itemp
= vgrf(glsl_type::int_type
);
3254 bld
.MOV(itemp
, temp
);
3256 /* Clamp the upper end of the range to +7/16.
3257 * ARB_gpu_shader5 requires that we support a maximum offset
3258 * of +0.5, which isn't representable in a S0.4 value -- if
3259 * we didn't clamp it, we'd end up with -8/16, which is the
3260 * opposite of what the shader author wanted.
3262 * This is legal due to ARB_gpu_shader5's quantization
3265 * "Not all values of <offset> may be supported; x and y
3266 * offsets may be rounded to fixed-point values with the
3267 * number of fraction bits given by the
3268 * implementation-dependent constant
3269 * FRAGMENT_INTERPOLATION_OFFSET_BITS"
3271 set_condmod(BRW_CONDITIONAL_L
,
3272 bld
.SEL(offset(src
, bld
, i
), itemp
, brw_imm_d(7)));
3275 const enum opcode opcode
= FS_OPCODE_INTERPOLATE_AT_PER_SLOT_OFFSET
;
3276 emit_pixel_interpolater_send(bld
,
3286 case nir_intrinsic_load_interpolated_input
: {
3287 if (nir_intrinsic_base(instr
) == VARYING_SLOT_POS
) {
3288 emit_fragcoord_interpolation(dest
);
3292 assert(instr
->src
[0].ssa
&&
3293 instr
->src
[0].ssa
->parent_instr
->type
== nir_instr_type_intrinsic
);
3294 nir_intrinsic_instr
*bary_intrinsic
=
3295 nir_instr_as_intrinsic(instr
->src
[0].ssa
->parent_instr
);
3296 nir_intrinsic_op bary_intrin
= bary_intrinsic
->intrinsic
;
3297 enum glsl_interp_mode interp_mode
=
3298 (enum glsl_interp_mode
) nir_intrinsic_interp_mode(bary_intrinsic
);
3301 if (bary_intrin
== nir_intrinsic_load_barycentric_at_offset
||
3302 bary_intrin
== nir_intrinsic_load_barycentric_at_sample
) {
3303 /* Use the result of the PI message */
3304 dst_xy
= retype(get_nir_src(instr
->src
[0]), BRW_REGISTER_TYPE_F
);
3306 /* Use the delta_xy values computed from the payload */
3307 enum brw_barycentric_mode bary
=
3308 brw_barycentric_mode(interp_mode
, bary_intrin
);
3310 dst_xy
= this->delta_xy
[bary
];
3313 for (unsigned int i
= 0; i
< instr
->num_components
; i
++) {
3315 fs_reg(interp_reg(nir_intrinsic_base(instr
),
3316 nir_intrinsic_component(instr
) + i
));
3317 interp
.type
= BRW_REGISTER_TYPE_F
;
3318 dest
.type
= BRW_REGISTER_TYPE_F
;
3320 if (devinfo
->gen
< 6 && interp_mode
== INTERP_MODE_SMOOTH
) {
3321 fs_reg tmp
= vgrf(glsl_type::float_type
);
3322 bld
.emit(FS_OPCODE_LINTERP
, tmp
, dst_xy
, interp
);
3323 bld
.MUL(offset(dest
, bld
, i
), tmp
, this->pixel_w
);
3325 bld
.emit(FS_OPCODE_LINTERP
, offset(dest
, bld
, i
), dst_xy
, interp
);
3332 nir_emit_intrinsic(bld
, instr
);
3338 fs_visitor::nir_emit_cs_intrinsic(const fs_builder
&bld
,
3339 nir_intrinsic_instr
*instr
)
3341 assert(stage
== MESA_SHADER_COMPUTE
);
3342 struct brw_cs_prog_data
*cs_prog_data
= brw_cs_prog_data(prog_data
);
3345 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
3346 dest
= get_nir_dest(instr
->dest
);
3348 switch (instr
->intrinsic
) {
3349 case nir_intrinsic_barrier
:
3351 cs_prog_data
->uses_barrier
= true;
3354 case nir_intrinsic_load_local_invocation_id
:
3355 case nir_intrinsic_load_work_group_id
: {
3356 gl_system_value sv
= nir_system_value_from_intrinsic(instr
->intrinsic
);
3357 fs_reg val
= nir_system_values
[sv
];
3358 assert(val
.file
!= BAD_FILE
);
3359 dest
.type
= val
.type
;
3360 for (unsigned i
= 0; i
< 3; i
++)
3361 bld
.MOV(offset(dest
, bld
, i
), offset(val
, bld
, i
));
3365 case nir_intrinsic_load_num_work_groups
: {
3366 const unsigned surface
=
3367 cs_prog_data
->binding_table
.work_groups_start
;
3369 cs_prog_data
->uses_num_work_groups
= true;
3371 fs_reg surf_index
= brw_imm_ud(surface
);
3372 brw_mark_surface_used(prog_data
, surface
);
3374 /* Read the 3 GLuint components of gl_NumWorkGroups */
3375 for (unsigned i
= 0; i
< 3; i
++) {
3376 fs_reg read_result
=
3377 emit_untyped_read(bld
, surf_index
,
3379 1 /* dims */, 1 /* size */,
3380 BRW_PREDICATE_NONE
);
3381 read_result
.type
= dest
.type
;
3382 bld
.MOV(dest
, read_result
);
3383 dest
= offset(dest
, bld
, 1);
3388 case nir_intrinsic_shared_atomic_add
:
3389 nir_emit_shared_atomic(bld
, BRW_AOP_ADD
, instr
);
3391 case nir_intrinsic_shared_atomic_imin
:
3392 nir_emit_shared_atomic(bld
, BRW_AOP_IMIN
, instr
);
3394 case nir_intrinsic_shared_atomic_umin
:
3395 nir_emit_shared_atomic(bld
, BRW_AOP_UMIN
, instr
);
3397 case nir_intrinsic_shared_atomic_imax
:
3398 nir_emit_shared_atomic(bld
, BRW_AOP_IMAX
, instr
);
3400 case nir_intrinsic_shared_atomic_umax
:
3401 nir_emit_shared_atomic(bld
, BRW_AOP_UMAX
, instr
);
3403 case nir_intrinsic_shared_atomic_and
:
3404 nir_emit_shared_atomic(bld
, BRW_AOP_AND
, instr
);
3406 case nir_intrinsic_shared_atomic_or
:
3407 nir_emit_shared_atomic(bld
, BRW_AOP_OR
, instr
);
3409 case nir_intrinsic_shared_atomic_xor
:
3410 nir_emit_shared_atomic(bld
, BRW_AOP_XOR
, instr
);
3412 case nir_intrinsic_shared_atomic_exchange
:
3413 nir_emit_shared_atomic(bld
, BRW_AOP_MOV
, instr
);
3415 case nir_intrinsic_shared_atomic_comp_swap
:
3416 nir_emit_shared_atomic(bld
, BRW_AOP_CMPWR
, instr
);
3419 case nir_intrinsic_load_shared
: {
3420 assert(devinfo
->gen
>= 7);
3422 fs_reg surf_index
= brw_imm_ud(GEN7_BTI_SLM
);
3424 /* Get the offset to read from */
3426 nir_const_value
*const_offset
= nir_src_as_const_value(instr
->src
[0]);
3428 offset_reg
= brw_imm_ud(instr
->const_index
[0] + const_offset
->u32
[0]);
3430 offset_reg
= vgrf(glsl_type::uint_type
);
3432 retype(get_nir_src(instr
->src
[0]), BRW_REGISTER_TYPE_UD
),
3433 brw_imm_ud(instr
->const_index
[0]));
3436 /* Read the vector */
3437 do_untyped_vector_read(bld
, dest
, surf_index
, offset_reg
,
3438 instr
->num_components
);
3442 case nir_intrinsic_store_shared
: {
3443 assert(devinfo
->gen
>= 7);
3446 fs_reg surf_index
= brw_imm_ud(GEN7_BTI_SLM
);
3449 fs_reg val_reg
= get_nir_src(instr
->src
[0]);
3452 unsigned writemask
= instr
->const_index
[1];
3454 /* get_nir_src() retypes to integer. Be wary of 64-bit types though
3455 * since the untyped writes below operate in units of 32-bits, which
3456 * means that we need to write twice as many components each time.
3457 * Also, we have to suffle 64-bit data to be in the appropriate layout
3458 * expected by our 32-bit write messages.
3460 unsigned type_size
= 4;
3461 if (nir_src_bit_size(instr
->src
[0]) == 64) {
3464 fs_reg(VGRF
, alloc
.allocate(alloc
.sizes
[val_reg
.nr
]), val_reg
.type
);
3465 shuffle_64bit_data_for_32bit_write(
3467 retype(tmp
, BRW_REGISTER_TYPE_F
),
3468 retype(val_reg
, BRW_REGISTER_TYPE_DF
),
3469 instr
->num_components
);
3473 unsigned type_slots
= type_size
/ 4;
3475 /* Combine groups of consecutive enabled channels in one write
3476 * message. We use ffs to find the first enabled channel and then ffs on
3477 * the bit-inverse, down-shifted writemask to determine the length of
3478 * the block of enabled bits.
3481 unsigned first_component
= ffs(writemask
) - 1;
3482 unsigned length
= ffs(~(writemask
>> first_component
)) - 1;
3484 /* We can't write more than 2 64-bit components at once. Limit the
3485 * length of the write to what we can do and let the next iteration
3489 length
= MIN2(2, length
);
3492 nir_const_value
*const_offset
= nir_src_as_const_value(instr
->src
[1]);
3494 offset_reg
= brw_imm_ud(instr
->const_index
[0] + const_offset
->u32
[0] +
3495 type_size
* first_component
);
3497 offset_reg
= vgrf(glsl_type::uint_type
);
3499 retype(get_nir_src(instr
->src
[1]), BRW_REGISTER_TYPE_UD
),
3500 brw_imm_ud(instr
->const_index
[0] + type_size
* first_component
));
3503 emit_untyped_write(bld
, surf_index
, offset_reg
,
3504 offset(val_reg
, bld
, first_component
* type_slots
),
3505 1 /* dims */, length
* type_slots
,
3506 BRW_PREDICATE_NONE
);
3508 /* Clear the bits in the writemask that we just wrote, then try
3509 * again to see if more channels are left.
3511 writemask
&= (15 << (first_component
+ length
));
3518 nir_emit_intrinsic(bld
, instr
);
3524 fs_visitor::nir_emit_intrinsic(const fs_builder
&bld
, nir_intrinsic_instr
*instr
)
3527 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
3528 dest
= get_nir_dest(instr
->dest
);
3530 switch (instr
->intrinsic
) {
3531 case nir_intrinsic_atomic_counter_inc
:
3532 case nir_intrinsic_atomic_counter_dec
:
3533 case nir_intrinsic_atomic_counter_read
:
3534 case nir_intrinsic_atomic_counter_add
:
3535 case nir_intrinsic_atomic_counter_min
:
3536 case nir_intrinsic_atomic_counter_max
:
3537 case nir_intrinsic_atomic_counter_and
:
3538 case nir_intrinsic_atomic_counter_or
:
3539 case nir_intrinsic_atomic_counter_xor
:
3540 case nir_intrinsic_atomic_counter_exchange
:
3541 case nir_intrinsic_atomic_counter_comp_swap
: {
3542 if (stage
== MESA_SHADER_FRAGMENT
&&
3543 instr
->intrinsic
!= nir_intrinsic_atomic_counter_read
)
3544 brw_wm_prog_data(prog_data
)->has_side_effects
= true;
3546 /* Get some metadata from the image intrinsic. */
3547 const nir_intrinsic_info
*info
= &nir_intrinsic_infos
[instr
->intrinsic
];
3549 /* Get the arguments of the atomic intrinsic. */
3550 const fs_reg offset
= get_nir_src(instr
->src
[0]);
3551 const unsigned surface
= (stage_prog_data
->binding_table
.abo_start
+
3552 instr
->const_index
[0]);
3553 const fs_reg src0
= (info
->num_srcs
>= 2
3554 ? get_nir_src(instr
->src
[1]) : fs_reg());
3555 const fs_reg src1
= (info
->num_srcs
>= 3
3556 ? get_nir_src(instr
->src
[2]) : fs_reg());
3559 assert(info
->num_srcs
<= 3);
3561 /* Emit a surface read or atomic op. */
3562 if (instr
->intrinsic
== nir_intrinsic_atomic_counter_read
) {
3563 tmp
= emit_untyped_read(bld
, brw_imm_ud(surface
), offset
, 1, 1);
3565 tmp
= emit_untyped_atomic(bld
, brw_imm_ud(surface
), offset
, src0
,
3567 get_atomic_counter_op(instr
->intrinsic
));
3570 /* Assign the result. */
3571 bld
.MOV(retype(dest
, BRW_REGISTER_TYPE_UD
), tmp
);
3573 /* Mark the surface as used. */
3574 brw_mark_surface_used(stage_prog_data
, surface
);
3578 case nir_intrinsic_image_load
:
3579 case nir_intrinsic_image_store
:
3580 case nir_intrinsic_image_atomic_add
:
3581 case nir_intrinsic_image_atomic_min
:
3582 case nir_intrinsic_image_atomic_max
:
3583 case nir_intrinsic_image_atomic_and
:
3584 case nir_intrinsic_image_atomic_or
:
3585 case nir_intrinsic_image_atomic_xor
:
3586 case nir_intrinsic_image_atomic_exchange
:
3587 case nir_intrinsic_image_atomic_comp_swap
: {
3588 using namespace image_access
;
3590 if (stage
== MESA_SHADER_FRAGMENT
&&
3591 instr
->intrinsic
!= nir_intrinsic_image_load
)
3592 brw_wm_prog_data(prog_data
)->has_side_effects
= true;
3594 /* Get the referenced image variable and type. */
3595 const nir_variable
*var
= instr
->variables
[0]->var
;
3596 const glsl_type
*type
= var
->type
->without_array();
3597 const brw_reg_type base_type
= get_image_base_type(type
);
3599 /* Get some metadata from the image intrinsic. */
3600 const nir_intrinsic_info
*info
= &nir_intrinsic_infos
[instr
->intrinsic
];
3601 const unsigned arr_dims
= type
->sampler_array
? 1 : 0;
3602 const unsigned surf_dims
= type
->coordinate_components() - arr_dims
;
3603 const unsigned format
= var
->data
.image
.format
;
3605 /* Get the arguments of the image intrinsic. */
3606 const fs_reg image
= get_nir_image_deref(instr
->variables
[0]);
3607 const fs_reg addr
= retype(get_nir_src(instr
->src
[0]),
3608 BRW_REGISTER_TYPE_UD
);
3609 const fs_reg src0
= (info
->num_srcs
>= 3 ?
3610 retype(get_nir_src(instr
->src
[2]), base_type
) :
3612 const fs_reg src1
= (info
->num_srcs
>= 4 ?
3613 retype(get_nir_src(instr
->src
[3]), base_type
) :
3617 /* Emit an image load, store or atomic op. */
3618 if (instr
->intrinsic
== nir_intrinsic_image_load
)
3619 tmp
= emit_image_load(bld
, image
, addr
, surf_dims
, arr_dims
, format
);
3621 else if (instr
->intrinsic
== nir_intrinsic_image_store
)
3622 emit_image_store(bld
, image
, addr
, src0
, surf_dims
, arr_dims
,
3623 var
->data
.image
.write_only
? GL_NONE
: format
);
3626 tmp
= emit_image_atomic(bld
, image
, addr
, src0
, src1
,
3627 surf_dims
, arr_dims
, info
->dest_components
,
3628 get_image_atomic_op(instr
->intrinsic
, type
));
3630 /* Assign the result. */
3631 for (unsigned c
= 0; c
< info
->dest_components
; ++c
)
3632 bld
.MOV(offset(retype(dest
, base_type
), bld
, c
),
3633 offset(tmp
, bld
, c
));
3637 case nir_intrinsic_memory_barrier_atomic_counter
:
3638 case nir_intrinsic_memory_barrier_buffer
:
3639 case nir_intrinsic_memory_barrier_image
:
3640 case nir_intrinsic_memory_barrier
: {
3641 const fs_builder ubld
= bld
.group(8, 0);
3642 const fs_reg tmp
= ubld
.vgrf(BRW_REGISTER_TYPE_UD
, 2);
3643 ubld
.emit(SHADER_OPCODE_MEMORY_FENCE
, tmp
)
3644 ->size_written
= 2 * REG_SIZE
;
3648 case nir_intrinsic_group_memory_barrier
:
3649 case nir_intrinsic_memory_barrier_shared
:
3650 /* We treat these workgroup-level barriers as no-ops. This should be
3651 * safe at present and as long as:
3653 * - Memory access instructions are not subsequently reordered by the
3654 * compiler back-end.
3656 * - All threads from a given compute shader workgroup fit within a
3657 * single subslice and therefore talk to the same HDC shared unit
3658 * what supposedly guarantees ordering and coherency between threads
3659 * from the same workgroup. This may change in the future when we
3660 * start splitting workgroups across multiple subslices.
3662 * - The context is not in fault-and-stream mode, which could cause
3663 * memory transactions (including to SLM) prior to the barrier to be
3664 * replayed after the barrier if a pagefault occurs. This shouldn't
3665 * be a problem up to and including SKL because fault-and-stream is
3666 * not usable due to hardware issues, but that's likely to change in
3671 case nir_intrinsic_shader_clock
: {
3672 /* We cannot do anything if there is an event, so ignore it for now */
3673 const fs_reg shader_clock
= get_timestamp(bld
);
3674 const fs_reg srcs
[] = { component(shader_clock
, 0),
3675 component(shader_clock
, 1) };
3676 bld
.LOAD_PAYLOAD(dest
, srcs
, ARRAY_SIZE(srcs
), 0);
3680 case nir_intrinsic_image_size
: {
3681 /* Get the referenced image variable and type. */
3682 const nir_variable
*var
= instr
->variables
[0]->var
;
3683 const glsl_type
*type
= var
->type
->without_array();
3685 /* Get the size of the image. */
3686 const fs_reg image
= get_nir_image_deref(instr
->variables
[0]);
3687 const fs_reg size
= offset(image
, bld
, BRW_IMAGE_PARAM_SIZE_OFFSET
);
3689 /* For 1DArray image types, the array index is stored in the Z component.
3690 * Fix this by swizzling the Z component to the Y component.
3692 const bool is_1d_array_image
=
3693 type
->sampler_dimensionality
== GLSL_SAMPLER_DIM_1D
&&
3694 type
->sampler_array
;
3696 /* For CubeArray images, we should count the number of cubes instead
3697 * of the number of faces. Fix it by dividing the (Z component) by 6.
3699 const bool is_cube_array_image
=
3700 type
->sampler_dimensionality
== GLSL_SAMPLER_DIM_CUBE
&&
3701 type
->sampler_array
;
3703 /* Copy all the components. */
3704 for (unsigned c
= 0; c
< instr
->dest
.ssa
.num_components
; ++c
) {
3705 if ((int)c
>= type
->coordinate_components()) {
3706 bld
.MOV(offset(retype(dest
, BRW_REGISTER_TYPE_D
), bld
, c
),
3708 } else if (c
== 1 && is_1d_array_image
) {
3709 bld
.MOV(offset(retype(dest
, BRW_REGISTER_TYPE_D
), bld
, c
),
3710 offset(size
, bld
, 2));
3711 } else if (c
== 2 && is_cube_array_image
) {
3712 bld
.emit(SHADER_OPCODE_INT_QUOTIENT
,
3713 offset(retype(dest
, BRW_REGISTER_TYPE_D
), bld
, c
),
3714 offset(size
, bld
, c
), brw_imm_d(6));
3716 bld
.MOV(offset(retype(dest
, BRW_REGISTER_TYPE_D
), bld
, c
),
3717 offset(size
, bld
, c
));
3724 case nir_intrinsic_image_samples
:
3725 /* The driver does not support multi-sampled images. */
3726 bld
.MOV(retype(dest
, BRW_REGISTER_TYPE_D
), brw_imm_d(1));
3729 case nir_intrinsic_load_uniform
: {
3730 /* Offsets are in bytes but they should always be multiples of 4 */
3731 assert(instr
->const_index
[0] % 4 == 0);
3733 fs_reg
src(UNIFORM
, instr
->const_index
[0] / 4, dest
.type
);
3735 nir_const_value
*const_offset
= nir_src_as_const_value(instr
->src
[0]);
3737 /* Offsets are in bytes but they should always be multiples of 4 */
3738 assert(const_offset
->u32
[0] % 4 == 0);
3739 src
.offset
= const_offset
->u32
[0];
3741 for (unsigned j
= 0; j
< instr
->num_components
; j
++) {
3742 bld
.MOV(offset(dest
, bld
, j
), offset(src
, bld
, j
));
3745 fs_reg indirect
= retype(get_nir_src(instr
->src
[0]),
3746 BRW_REGISTER_TYPE_UD
);
3748 /* We need to pass a size to the MOV_INDIRECT but we don't want it to
3749 * go past the end of the uniform. In order to keep the n'th
3750 * component from running past, we subtract off the size of all but
3751 * one component of the vector.
3753 assert(instr
->const_index
[1] >=
3754 instr
->num_components
* (int) type_sz(dest
.type
));
3755 unsigned read_size
= instr
->const_index
[1] -
3756 (instr
->num_components
- 1) * type_sz(dest
.type
);
3758 bool supports_64bit_indirects
=
3759 !devinfo
->is_cherryview
&& !gen_device_info_is_9lp(devinfo
);
3761 if (type_sz(dest
.type
) != 8 || supports_64bit_indirects
) {
3762 for (unsigned j
= 0; j
< instr
->num_components
; j
++) {
3763 bld
.emit(SHADER_OPCODE_MOV_INDIRECT
,
3764 offset(dest
, bld
, j
), offset(src
, bld
, j
),
3765 indirect
, brw_imm_ud(read_size
));
3768 const unsigned num_mov_indirects
=
3769 type_sz(dest
.type
) / type_sz(BRW_REGISTER_TYPE_UD
);
3770 /* We read a little bit less per MOV INDIRECT, as they are now
3771 * 32-bits ones instead of 64-bit. Fix read_size then.
3773 const unsigned read_size_32bit
= read_size
-
3774 (num_mov_indirects
- 1) * type_sz(BRW_REGISTER_TYPE_UD
);
3775 for (unsigned j
= 0; j
< instr
->num_components
; j
++) {
3776 for (unsigned i
= 0; i
< num_mov_indirects
; i
++) {
3777 bld
.emit(SHADER_OPCODE_MOV_INDIRECT
,
3778 subscript(offset(dest
, bld
, j
), BRW_REGISTER_TYPE_UD
, i
),
3779 subscript(offset(src
, bld
, j
), BRW_REGISTER_TYPE_UD
, i
),
3780 indirect
, brw_imm_ud(read_size_32bit
));
3788 case nir_intrinsic_load_ubo
: {
3789 nir_const_value
*const_index
= nir_src_as_const_value(instr
->src
[0]);
3793 const unsigned index
= stage_prog_data
->binding_table
.ubo_start
+
3794 const_index
->u32
[0];
3795 surf_index
= brw_imm_ud(index
);
3796 brw_mark_surface_used(prog_data
, index
);
3798 /* The block index is not a constant. Evaluate the index expression
3799 * per-channel and add the base UBO index; we have to select a value
3800 * from any live channel.
3802 surf_index
= vgrf(glsl_type::uint_type
);
3803 bld
.ADD(surf_index
, get_nir_src(instr
->src
[0]),
3804 brw_imm_ud(stage_prog_data
->binding_table
.ubo_start
));
3805 surf_index
= bld
.emit_uniformize(surf_index
);
3807 /* Assume this may touch any UBO. It would be nice to provide
3808 * a tighter bound, but the array information is already lowered away.
3810 brw_mark_surface_used(prog_data
,
3811 stage_prog_data
->binding_table
.ubo_start
+
3812 nir
->info
.num_ubos
- 1);
3815 nir_const_value
*const_offset
= nir_src_as_const_value(instr
->src
[1]);
3816 if (const_offset
== NULL
) {
3817 fs_reg base_offset
= retype(get_nir_src(instr
->src
[1]),
3818 BRW_REGISTER_TYPE_UD
);
3820 for (int i
= 0; i
< instr
->num_components
; i
++)
3821 VARYING_PULL_CONSTANT_LOAD(bld
, offset(dest
, bld
, i
), surf_index
,
3822 base_offset
, i
* type_sz(dest
.type
));
3824 /* Even if we are loading doubles, a pull constant load will load
3825 * a 32-bit vec4, so should only reserve vgrf space for that. If we
3826 * need to load a full dvec4 we will have to emit 2 loads. This is
3827 * similar to demote_pull_constants(), except that in that case we
3828 * see individual accesses to each component of the vector and then
3829 * we let CSE deal with duplicate loads. Here we see a vector access
3830 * and we have to split it if necessary.
3832 const unsigned type_size
= type_sz(dest
.type
);
3834 /* See if we've selected this as a push constant candidate */
3836 const unsigned ubo_block
= const_index
->u32
[0];
3837 const unsigned offset_256b
= const_offset
->u32
[0] / 32;
3840 for (int i
= 0; i
< 4; i
++) {
3841 const struct brw_ubo_range
*range
= &prog_data
->ubo_ranges
[i
];
3842 if (range
->block
== ubo_block
&&
3843 offset_256b
>= range
->start
&&
3844 offset_256b
< range
->start
+ range
->length
) {
3846 push_reg
= fs_reg(UNIFORM
, UBO_START
+ i
, dest
.type
);
3847 push_reg
.offset
= const_offset
->u32
[0] - 32 * range
->start
;
3852 if (push_reg
.file
!= BAD_FILE
) {
3853 for (unsigned i
= 0; i
< instr
->num_components
; i
++) {
3854 bld
.MOV(offset(dest
, bld
, i
),
3855 byte_offset(push_reg
, i
* type_size
));
3861 const unsigned block_sz
= 64; /* Fetch one cacheline at a time. */
3862 const fs_builder ubld
= bld
.exec_all().group(block_sz
/ 4, 0);
3863 const fs_reg packed_consts
= ubld
.vgrf(BRW_REGISTER_TYPE_UD
);
3865 for (unsigned c
= 0; c
< instr
->num_components
;) {
3866 const unsigned base
= const_offset
->u32
[0] + c
* type_size
;
3867 /* Number of usable components in the next block-aligned load. */
3868 const unsigned count
= MIN2(instr
->num_components
- c
,
3869 (block_sz
- base
% block_sz
) / type_size
);
3871 ubld
.emit(FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD
,
3872 packed_consts
, surf_index
,
3873 brw_imm_ud(base
& ~(block_sz
- 1)));
3875 const fs_reg consts
=
3876 retype(byte_offset(packed_consts
, base
& (block_sz
- 1)),
3879 for (unsigned d
= 0; d
< count
; d
++)
3880 bld
.MOV(offset(dest
, bld
, c
+ d
), component(consts
, d
));
3888 case nir_intrinsic_load_ssbo
: {
3889 assert(devinfo
->gen
>= 7);
3891 nir_const_value
*const_uniform_block
=
3892 nir_src_as_const_value(instr
->src
[0]);
3895 if (const_uniform_block
) {
3896 unsigned index
= stage_prog_data
->binding_table
.ssbo_start
+
3897 const_uniform_block
->u32
[0];
3898 surf_index
= brw_imm_ud(index
);
3899 brw_mark_surface_used(prog_data
, index
);
3901 surf_index
= vgrf(glsl_type::uint_type
);
3902 bld
.ADD(surf_index
, get_nir_src(instr
->src
[0]),
3903 brw_imm_ud(stage_prog_data
->binding_table
.ssbo_start
));
3905 /* Assume this may touch any UBO. It would be nice to provide
3906 * a tighter bound, but the array information is already lowered away.
3908 brw_mark_surface_used(prog_data
,
3909 stage_prog_data
->binding_table
.ssbo_start
+
3910 nir
->info
.num_ssbos
- 1);
3914 nir_const_value
*const_offset
= nir_src_as_const_value(instr
->src
[1]);
3916 offset_reg
= brw_imm_ud(const_offset
->u32
[0]);
3918 offset_reg
= get_nir_src(instr
->src
[1]);
3921 /* Read the vector */
3922 do_untyped_vector_read(bld
, dest
, surf_index
, offset_reg
,
3923 instr
->num_components
);
3928 case nir_intrinsic_store_ssbo
: {
3929 assert(devinfo
->gen
>= 7);
3931 if (stage
== MESA_SHADER_FRAGMENT
)
3932 brw_wm_prog_data(prog_data
)->has_side_effects
= true;
3936 nir_const_value
*const_uniform_block
=
3937 nir_src_as_const_value(instr
->src
[1]);
3938 if (const_uniform_block
) {
3939 unsigned index
= stage_prog_data
->binding_table
.ssbo_start
+
3940 const_uniform_block
->u32
[0];
3941 surf_index
= brw_imm_ud(index
);
3942 brw_mark_surface_used(prog_data
, index
);
3944 surf_index
= vgrf(glsl_type::uint_type
);
3945 bld
.ADD(surf_index
, get_nir_src(instr
->src
[1]),
3946 brw_imm_ud(stage_prog_data
->binding_table
.ssbo_start
));
3948 brw_mark_surface_used(prog_data
,
3949 stage_prog_data
->binding_table
.ssbo_start
+
3950 nir
->info
.num_ssbos
- 1);
3954 fs_reg val_reg
= get_nir_src(instr
->src
[0]);
3957 unsigned writemask
= instr
->const_index
[0];
3959 /* get_nir_src() retypes to integer. Be wary of 64-bit types though
3960 * since the untyped writes below operate in units of 32-bits, which
3961 * means that we need to write twice as many components each time.
3962 * Also, we have to suffle 64-bit data to be in the appropriate layout
3963 * expected by our 32-bit write messages.
3965 unsigned type_size
= 4;
3966 if (nir_src_bit_size(instr
->src
[0]) == 64) {
3969 fs_reg(VGRF
, alloc
.allocate(alloc
.sizes
[val_reg
.nr
]), val_reg
.type
);
3970 shuffle_64bit_data_for_32bit_write(bld
,
3971 retype(tmp
, BRW_REGISTER_TYPE_F
),
3972 retype(val_reg
, BRW_REGISTER_TYPE_DF
),
3973 instr
->num_components
);
3977 unsigned type_slots
= type_size
/ 4;
3979 /* Combine groups of consecutive enabled channels in one write
3980 * message. We use ffs to find the first enabled channel and then ffs on
3981 * the bit-inverse, down-shifted writemask to determine the length of
3982 * the block of enabled bits.
3985 unsigned first_component
= ffs(writemask
) - 1;
3986 unsigned length
= ffs(~(writemask
>> first_component
)) - 1;
3988 /* We can't write more than 2 64-bit components at once. Limit the
3989 * length of the write to what we can do and let the next iteration
3993 length
= MIN2(2, length
);
3996 nir_const_value
*const_offset
= nir_src_as_const_value(instr
->src
[2]);
3998 offset_reg
= brw_imm_ud(const_offset
->u32
[0] +
3999 type_size
* first_component
);
4001 offset_reg
= vgrf(glsl_type::uint_type
);
4003 retype(get_nir_src(instr
->src
[2]), BRW_REGISTER_TYPE_UD
),
4004 brw_imm_ud(type_size
* first_component
));
4008 emit_untyped_write(bld
, surf_index
, offset_reg
,
4009 offset(val_reg
, bld
, first_component
* type_slots
),
4010 1 /* dims */, length
* type_slots
,
4011 BRW_PREDICATE_NONE
);
4013 /* Clear the bits in the writemask that we just wrote, then try
4014 * again to see if more channels are left.
4016 writemask
&= (15 << (first_component
+ length
));
4021 case nir_intrinsic_store_output
: {
4022 fs_reg src
= get_nir_src(instr
->src
[0]);
4024 nir_const_value
*const_offset
= nir_src_as_const_value(instr
->src
[1]);
4025 assert(const_offset
&& "Indirect output stores not allowed");
4026 fs_reg new_dest
= retype(offset(outputs
[instr
->const_index
[0]], bld
,
4027 4 * const_offset
->u32
[0]), src
.type
);
4029 unsigned num_components
= instr
->num_components
;
4030 unsigned first_component
= nir_intrinsic_component(instr
);
4031 if (nir_src_bit_size(instr
->src
[0]) == 64) {
4033 fs_reg(VGRF
, alloc
.allocate(2 * num_components
),
4034 BRW_REGISTER_TYPE_F
);
4035 shuffle_64bit_data_for_32bit_write(
4036 bld
, tmp
, retype(src
, BRW_REGISTER_TYPE_DF
), num_components
);
4037 src
= retype(tmp
, src
.type
);
4038 num_components
*= 2;
4041 for (unsigned j
= 0; j
< num_components
; j
++) {
4042 bld
.MOV(offset(new_dest
, bld
, j
+ first_component
),
4043 offset(src
, bld
, j
));
4048 case nir_intrinsic_ssbo_atomic_add
:
4049 nir_emit_ssbo_atomic(bld
, BRW_AOP_ADD
, instr
);
4051 case nir_intrinsic_ssbo_atomic_imin
:
4052 nir_emit_ssbo_atomic(bld
, BRW_AOP_IMIN
, instr
);
4054 case nir_intrinsic_ssbo_atomic_umin
:
4055 nir_emit_ssbo_atomic(bld
, BRW_AOP_UMIN
, instr
);
4057 case nir_intrinsic_ssbo_atomic_imax
:
4058 nir_emit_ssbo_atomic(bld
, BRW_AOP_IMAX
, instr
);
4060 case nir_intrinsic_ssbo_atomic_umax
:
4061 nir_emit_ssbo_atomic(bld
, BRW_AOP_UMAX
, instr
);
4063 case nir_intrinsic_ssbo_atomic_and
:
4064 nir_emit_ssbo_atomic(bld
, BRW_AOP_AND
, instr
);
4066 case nir_intrinsic_ssbo_atomic_or
:
4067 nir_emit_ssbo_atomic(bld
, BRW_AOP_OR
, instr
);
4069 case nir_intrinsic_ssbo_atomic_xor
:
4070 nir_emit_ssbo_atomic(bld
, BRW_AOP_XOR
, instr
);
4072 case nir_intrinsic_ssbo_atomic_exchange
:
4073 nir_emit_ssbo_atomic(bld
, BRW_AOP_MOV
, instr
);
4075 case nir_intrinsic_ssbo_atomic_comp_swap
:
4076 nir_emit_ssbo_atomic(bld
, BRW_AOP_CMPWR
, instr
);
4079 case nir_intrinsic_get_buffer_size
: {
4080 nir_const_value
*const_uniform_block
= nir_src_as_const_value(instr
->src
[0]);
4081 unsigned ssbo_index
= const_uniform_block
? const_uniform_block
->u32
[0] : 0;
4083 /* A resinfo's sampler message is used to get the buffer size. The
4084 * SIMD8's writeback message consists of four registers and SIMD16's
4085 * writeback message consists of 8 destination registers (two per each
4086 * component). Because we are only interested on the first channel of
4087 * the first returned component, where resinfo returns the buffer size
4088 * for SURFTYPE_BUFFER, we can just use the SIMD8 variant regardless of
4089 * the dispatch width.
4091 const fs_builder ubld
= bld
.exec_all().group(8, 0);
4092 fs_reg src_payload
= ubld
.vgrf(BRW_REGISTER_TYPE_UD
);
4093 fs_reg ret_payload
= ubld
.vgrf(BRW_REGISTER_TYPE_UD
, 4);
4096 ubld
.MOV(src_payload
, brw_imm_d(0));
4098 const unsigned index
= prog_data
->binding_table
.ssbo_start
+ ssbo_index
;
4099 fs_inst
*inst
= ubld
.emit(FS_OPCODE_GET_BUFFER_SIZE
, ret_payload
,
4100 src_payload
, brw_imm_ud(index
));
4101 inst
->header_size
= 0;
4103 inst
->size_written
= 4 * REG_SIZE
;
4105 bld
.MOV(retype(dest
, ret_payload
.type
), component(ret_payload
, 0));
4106 brw_mark_surface_used(prog_data
, index
);
4110 case nir_intrinsic_load_subgroup_size
:
4111 bld
.MOV(retype(dest
, BRW_REGISTER_TYPE_D
), brw_imm_d(dispatch_width
));
4114 case nir_intrinsic_load_subgroup_invocation
: {
4115 fs_reg tmp
= bld
.vgrf(BRW_REGISTER_TYPE_UW
);
4116 dest
= retype(dest
, BRW_REGISTER_TYPE_UD
);
4117 const fs_builder allbld8
= bld
.group(8, 0).exec_all();
4118 allbld8
.MOV(tmp
, brw_imm_v(0x76543210));
4119 if (dispatch_width
> 8)
4120 allbld8
.ADD(byte_offset(tmp
, 16), tmp
, brw_imm_uw(8u));
4121 if (dispatch_width
> 16) {
4122 const fs_builder allbld16
= bld
.group(16, 0).exec_all();
4123 allbld16
.ADD(byte_offset(tmp
, 32), tmp
, brw_imm_uw(16u));
4129 case nir_intrinsic_load_subgroup_eq_mask
:
4130 case nir_intrinsic_load_subgroup_ge_mask
:
4131 case nir_intrinsic_load_subgroup_gt_mask
:
4132 case nir_intrinsic_load_subgroup_le_mask
:
4133 case nir_intrinsic_load_subgroup_lt_mask
:
4134 unreachable("not reached");
4136 case nir_intrinsic_vote_any
: {
4137 const fs_builder ubld
= bld
.exec_all();
4139 /* The any/all predicates do not consider channel enables. To prevent
4140 * dead channels from affecting the result, we initialize the flag with
4141 * with the identity value for the logical operation.
4143 ubld
.MOV(brw_flag_reg(0, 0), brw_imm_uw(0));
4144 bld
.CMP(bld
.null_reg_d(), get_nir_src(instr
->src
[0]), brw_imm_d(0), BRW_CONDITIONAL_NZ
);
4145 bld
.MOV(dest
, brw_imm_d(-1));
4146 set_predicate(dispatch_width
== 8 ?
4147 BRW_PREDICATE_ALIGN1_ANY8H
:
4148 BRW_PREDICATE_ALIGN1_ANY16H
,
4149 bld
.SEL(dest
, dest
, brw_imm_d(0)));
4152 case nir_intrinsic_vote_all
: {
4153 const fs_builder ubld
= bld
.exec_all();
4155 /* The any/all predicates do not consider channel enables. To prevent
4156 * dead channels from affecting the result, we initialize the flag with
4157 * with the identity value for the logical operation.
4159 ubld
.MOV(brw_flag_reg(0, 0), brw_imm_uw(0xffff));
4160 bld
.CMP(bld
.null_reg_d(), get_nir_src(instr
->src
[0]), brw_imm_d(0), BRW_CONDITIONAL_NZ
);
4161 bld
.MOV(dest
, brw_imm_d(-1));
4162 set_predicate(dispatch_width
== 8 ?
4163 BRW_PREDICATE_ALIGN1_ALL8H
:
4164 BRW_PREDICATE_ALIGN1_ALL16H
,
4165 bld
.SEL(dest
, dest
, brw_imm_d(0)));
4168 case nir_intrinsic_vote_eq
: {
4169 fs_reg value
= get_nir_src(instr
->src
[0]);
4170 fs_reg uniformized
= bld
.emit_uniformize(value
);
4171 const fs_builder ubld
= bld
.exec_all();
4173 /* The any/all predicates do not consider channel enables. To prevent
4174 * dead channels from affecting the result, we initialize the flag with
4175 * with the identity value for the logical operation.
4177 ubld
.MOV(brw_flag_reg(0, 0), brw_imm_uw(0xffff));
4178 bld
.CMP(bld
.null_reg_d(), value
, uniformized
, BRW_CONDITIONAL_Z
);
4179 bld
.MOV(dest
, brw_imm_d(-1));
4180 set_predicate(dispatch_width
== 8 ?
4181 BRW_PREDICATE_ALIGN1_ALL8H
:
4182 BRW_PREDICATE_ALIGN1_ALL16H
,
4183 bld
.SEL(dest
, dest
, brw_imm_d(0)));
4187 case nir_intrinsic_ballot
: {
4188 const fs_reg value
= retype(get_nir_src(instr
->src
[0]),
4189 BRW_REGISTER_TYPE_UD
);
4190 const struct brw_reg flag
= retype(brw_flag_reg(0, 0),
4191 BRW_REGISTER_TYPE_UD
);
4193 bld
.exec_all().MOV(flag
, brw_imm_ud(0u));
4194 bld
.CMP(bld
.null_reg_ud(), value
, brw_imm_ud(0u), BRW_CONDITIONAL_NZ
);
4196 if (instr
->dest
.ssa
.bit_size
> 32) {
4197 dest
.type
= BRW_REGISTER_TYPE_UQ
;
4199 dest
.type
= BRW_REGISTER_TYPE_UD
;
4201 bld
.MOV(dest
, flag
);
4205 case nir_intrinsic_read_invocation
: {
4206 const fs_reg value
= get_nir_src(instr
->src
[0]);
4207 const fs_reg invocation
= get_nir_src(instr
->src
[1]);
4208 fs_reg tmp
= bld
.vgrf(value
.type
);
4210 bld
.exec_all().emit(SHADER_OPCODE_BROADCAST
, tmp
, value
,
4211 component(invocation
, 0));
4213 bld
.MOV(retype(dest
, BRW_REGISTER_TYPE_D
),
4214 fs_reg(component(tmp
, 0)));
4218 case nir_intrinsic_read_first_invocation
: {
4219 const fs_reg value
= get_nir_src(instr
->src
[0]);
4220 bld
.MOV(retype(dest
, BRW_REGISTER_TYPE_D
),
4221 bld
.emit_uniformize(value
));
4226 unreachable("unknown intrinsic");
4231 fs_visitor::nir_emit_ssbo_atomic(const fs_builder
&bld
,
4232 int op
, nir_intrinsic_instr
*instr
)
4234 if (stage
== MESA_SHADER_FRAGMENT
)
4235 brw_wm_prog_data(prog_data
)->has_side_effects
= true;
4238 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
4239 dest
= get_nir_dest(instr
->dest
);
4242 nir_const_value
*const_surface
= nir_src_as_const_value(instr
->src
[0]);
4243 if (const_surface
) {
4244 unsigned surf_index
= stage_prog_data
->binding_table
.ssbo_start
+
4245 const_surface
->u32
[0];
4246 surface
= brw_imm_ud(surf_index
);
4247 brw_mark_surface_used(prog_data
, surf_index
);
4249 surface
= vgrf(glsl_type::uint_type
);
4250 bld
.ADD(surface
, get_nir_src(instr
->src
[0]),
4251 brw_imm_ud(stage_prog_data
->binding_table
.ssbo_start
));
4253 /* Assume this may touch any SSBO. This is the same we do for other
4254 * UBO/SSBO accesses with non-constant surface.
4256 brw_mark_surface_used(prog_data
,
4257 stage_prog_data
->binding_table
.ssbo_start
+
4258 nir
->info
.num_ssbos
- 1);
4261 fs_reg offset
= get_nir_src(instr
->src
[1]);
4262 fs_reg data1
= get_nir_src(instr
->src
[2]);
4264 if (op
== BRW_AOP_CMPWR
)
4265 data2
= get_nir_src(instr
->src
[3]);
4267 /* Emit the actual atomic operation */
4269 fs_reg atomic_result
= emit_untyped_atomic(bld
, surface
, offset
,
4271 1 /* dims */, 1 /* rsize */,
4273 BRW_PREDICATE_NONE
);
4274 dest
.type
= atomic_result
.type
;
4275 bld
.MOV(dest
, atomic_result
);
4279 fs_visitor::nir_emit_shared_atomic(const fs_builder
&bld
,
4280 int op
, nir_intrinsic_instr
*instr
)
4283 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
4284 dest
= get_nir_dest(instr
->dest
);
4286 fs_reg surface
= brw_imm_ud(GEN7_BTI_SLM
);
4288 fs_reg data1
= get_nir_src(instr
->src
[1]);
4290 if (op
== BRW_AOP_CMPWR
)
4291 data2
= get_nir_src(instr
->src
[2]);
4293 /* Get the offset */
4294 nir_const_value
*const_offset
= nir_src_as_const_value(instr
->src
[0]);
4296 offset
= brw_imm_ud(instr
->const_index
[0] + const_offset
->u32
[0]);
4298 offset
= vgrf(glsl_type::uint_type
);
4300 retype(get_nir_src(instr
->src
[0]), BRW_REGISTER_TYPE_UD
),
4301 brw_imm_ud(instr
->const_index
[0]));
4304 /* Emit the actual atomic operation operation */
4306 fs_reg atomic_result
= emit_untyped_atomic(bld
, surface
, offset
,
4308 1 /* dims */, 1 /* rsize */,
4310 BRW_PREDICATE_NONE
);
4311 dest
.type
= atomic_result
.type
;
4312 bld
.MOV(dest
, atomic_result
);
4316 fs_visitor::nir_emit_texture(const fs_builder
&bld
, nir_tex_instr
*instr
)
4318 unsigned texture
= instr
->texture_index
;
4319 unsigned sampler
= instr
->sampler_index
;
4321 fs_reg srcs
[TEX_LOGICAL_NUM_SRCS
];
4323 srcs
[TEX_LOGICAL_SRC_SURFACE
] = brw_imm_ud(texture
);
4324 srcs
[TEX_LOGICAL_SRC_SAMPLER
] = brw_imm_ud(sampler
);
4326 int lod_components
= 0;
4328 /* The hardware requires a LOD for buffer textures */
4329 if (instr
->sampler_dim
== GLSL_SAMPLER_DIM_BUF
)
4330 srcs
[TEX_LOGICAL_SRC_LOD
] = brw_imm_d(0);
4332 uint32_t header_bits
= 0;
4333 for (unsigned i
= 0; i
< instr
->num_srcs
; i
++) {
4334 fs_reg src
= get_nir_src(instr
->src
[i
].src
);
4335 switch (instr
->src
[i
].src_type
) {
4336 case nir_tex_src_bias
:
4337 srcs
[TEX_LOGICAL_SRC_LOD
] =
4338 retype(get_nir_src_imm(instr
->src
[i
].src
), BRW_REGISTER_TYPE_F
);
4340 case nir_tex_src_comparator
:
4341 srcs
[TEX_LOGICAL_SRC_SHADOW_C
] = retype(src
, BRW_REGISTER_TYPE_F
);
4343 case nir_tex_src_coord
:
4344 switch (instr
->op
) {
4346 case nir_texop_txf_ms
:
4347 case nir_texop_txf_ms_mcs
:
4348 case nir_texop_samples_identical
:
4349 srcs
[TEX_LOGICAL_SRC_COORDINATE
] = retype(src
, BRW_REGISTER_TYPE_D
);
4352 srcs
[TEX_LOGICAL_SRC_COORDINATE
] = retype(src
, BRW_REGISTER_TYPE_F
);
4356 case nir_tex_src_ddx
:
4357 srcs
[TEX_LOGICAL_SRC_LOD
] = retype(src
, BRW_REGISTER_TYPE_F
);
4358 lod_components
= nir_tex_instr_src_size(instr
, i
);
4360 case nir_tex_src_ddy
:
4361 srcs
[TEX_LOGICAL_SRC_LOD2
] = retype(src
, BRW_REGISTER_TYPE_F
);
4363 case nir_tex_src_lod
:
4364 switch (instr
->op
) {
4366 srcs
[TEX_LOGICAL_SRC_LOD
] =
4367 retype(get_nir_src_imm(instr
->src
[i
].src
), BRW_REGISTER_TYPE_UD
);
4370 srcs
[TEX_LOGICAL_SRC_LOD
] =
4371 retype(get_nir_src_imm(instr
->src
[i
].src
), BRW_REGISTER_TYPE_D
);
4374 srcs
[TEX_LOGICAL_SRC_LOD
] =
4375 retype(get_nir_src_imm(instr
->src
[i
].src
), BRW_REGISTER_TYPE_F
);
4379 case nir_tex_src_ms_index
:
4380 srcs
[TEX_LOGICAL_SRC_SAMPLE_INDEX
] = retype(src
, BRW_REGISTER_TYPE_UD
);
4383 case nir_tex_src_offset
: {
4384 nir_const_value
*const_offset
=
4385 nir_src_as_const_value(instr
->src
[i
].src
);
4386 unsigned offset_bits
= 0;
4388 brw_texture_offset(const_offset
->i32
,
4389 nir_tex_instr_src_size(instr
, i
),
4391 header_bits
|= offset_bits
;
4393 srcs
[TEX_LOGICAL_SRC_TG4_OFFSET
] =
4394 retype(src
, BRW_REGISTER_TYPE_D
);
4399 case nir_tex_src_projector
:
4400 unreachable("should be lowered");
4402 case nir_tex_src_texture_offset
: {
4403 /* Figure out the highest possible texture index and mark it as used */
4404 uint32_t max_used
= texture
+ instr
->texture_array_size
- 1;
4405 if (instr
->op
== nir_texop_tg4
&& devinfo
->gen
< 8) {
4406 max_used
+= stage_prog_data
->binding_table
.gather_texture_start
;
4408 max_used
+= stage_prog_data
->binding_table
.texture_start
;
4410 brw_mark_surface_used(prog_data
, max_used
);
4412 /* Emit code to evaluate the actual indexing expression */
4413 fs_reg tmp
= vgrf(glsl_type::uint_type
);
4414 bld
.ADD(tmp
, src
, brw_imm_ud(texture
));
4415 srcs
[TEX_LOGICAL_SRC_SURFACE
] = bld
.emit_uniformize(tmp
);
4419 case nir_tex_src_sampler_offset
: {
4420 /* Emit code to evaluate the actual indexing expression */
4421 fs_reg tmp
= vgrf(glsl_type::uint_type
);
4422 bld
.ADD(tmp
, src
, brw_imm_ud(sampler
));
4423 srcs
[TEX_LOGICAL_SRC_SAMPLER
] = bld
.emit_uniformize(tmp
);
4427 case nir_tex_src_ms_mcs
:
4428 assert(instr
->op
== nir_texop_txf_ms
);
4429 srcs
[TEX_LOGICAL_SRC_MCS
] = retype(src
, BRW_REGISTER_TYPE_D
);
4432 case nir_tex_src_plane
: {
4433 nir_const_value
*const_plane
=
4434 nir_src_as_const_value(instr
->src
[i
].src
);
4435 const uint32_t plane
= const_plane
->u32
[0];
4436 const uint32_t texture_index
=
4437 instr
->texture_index
+
4438 stage_prog_data
->binding_table
.plane_start
[plane
] -
4439 stage_prog_data
->binding_table
.texture_start
;
4441 srcs
[TEX_LOGICAL_SRC_SURFACE
] = brw_imm_ud(texture_index
);
4446 unreachable("unknown texture source");
4450 if (srcs
[TEX_LOGICAL_SRC_MCS
].file
== BAD_FILE
&&
4451 (instr
->op
== nir_texop_txf_ms
||
4452 instr
->op
== nir_texop_samples_identical
)) {
4453 if (devinfo
->gen
>= 7 &&
4454 key_tex
->compressed_multisample_layout_mask
& (1 << texture
)) {
4455 srcs
[TEX_LOGICAL_SRC_MCS
] =
4456 emit_mcs_fetch(srcs
[TEX_LOGICAL_SRC_COORDINATE
],
4457 instr
->coord_components
,
4458 srcs
[TEX_LOGICAL_SRC_SURFACE
]);
4460 srcs
[TEX_LOGICAL_SRC_MCS
] = brw_imm_ud(0u);
4464 srcs
[TEX_LOGICAL_SRC_COORD_COMPONENTS
] = brw_imm_d(instr
->coord_components
);
4465 srcs
[TEX_LOGICAL_SRC_GRAD_COMPONENTS
] = brw_imm_d(lod_components
);
4468 switch (instr
->op
) {
4470 opcode
= (stage
== MESA_SHADER_FRAGMENT
? SHADER_OPCODE_TEX_LOGICAL
:
4471 SHADER_OPCODE_TXL_LOGICAL
);
4474 opcode
= FS_OPCODE_TXB_LOGICAL
;
4477 opcode
= SHADER_OPCODE_TXL_LOGICAL
;
4480 opcode
= SHADER_OPCODE_TXD_LOGICAL
;
4483 opcode
= SHADER_OPCODE_TXF_LOGICAL
;
4485 case nir_texop_txf_ms
:
4486 if ((key_tex
->msaa_16
& (1 << sampler
)))
4487 opcode
= SHADER_OPCODE_TXF_CMS_W_LOGICAL
;
4489 opcode
= SHADER_OPCODE_TXF_CMS_LOGICAL
;
4491 case nir_texop_txf_ms_mcs
:
4492 opcode
= SHADER_OPCODE_TXF_MCS_LOGICAL
;
4494 case nir_texop_query_levels
:
4496 opcode
= SHADER_OPCODE_TXS_LOGICAL
;
4499 opcode
= SHADER_OPCODE_LOD_LOGICAL
;
4502 if (srcs
[TEX_LOGICAL_SRC_TG4_OFFSET
].file
!= BAD_FILE
)
4503 opcode
= SHADER_OPCODE_TG4_OFFSET_LOGICAL
;
4505 opcode
= SHADER_OPCODE_TG4_LOGICAL
;
4507 case nir_texop_texture_samples
:
4508 opcode
= SHADER_OPCODE_SAMPLEINFO_LOGICAL
;
4510 case nir_texop_samples_identical
: {
4511 fs_reg dst
= retype(get_nir_dest(instr
->dest
), BRW_REGISTER_TYPE_D
);
4513 /* If mcs is an immediate value, it means there is no MCS. In that case
4514 * just return false.
4516 if (srcs
[TEX_LOGICAL_SRC_MCS
].file
== BRW_IMMEDIATE_VALUE
) {
4517 bld
.MOV(dst
, brw_imm_ud(0u));
4518 } else if ((key_tex
->msaa_16
& (1 << sampler
))) {
4519 fs_reg tmp
= vgrf(glsl_type::uint_type
);
4520 bld
.OR(tmp
, srcs
[TEX_LOGICAL_SRC_MCS
],
4521 offset(srcs
[TEX_LOGICAL_SRC_MCS
], bld
, 1));
4522 bld
.CMP(dst
, tmp
, brw_imm_ud(0u), BRW_CONDITIONAL_EQ
);
4524 bld
.CMP(dst
, srcs
[TEX_LOGICAL_SRC_MCS
], brw_imm_ud(0u),
4525 BRW_CONDITIONAL_EQ
);
4530 unreachable("unknown texture opcode");
4533 if (instr
->op
== nir_texop_tg4
) {
4534 if (instr
->component
== 1 &&
4535 key_tex
->gather_channel_quirk_mask
& (1 << texture
)) {
4536 /* gather4 sampler is broken for green channel on RG32F --
4537 * we must ask for blue instead.
4539 header_bits
|= 2 << 16;
4541 header_bits
|= instr
->component
<< 16;
4545 fs_reg dst
= bld
.vgrf(brw_type_for_nir_type(devinfo
, instr
->dest_type
), 4);
4546 fs_inst
*inst
= bld
.emit(opcode
, dst
, srcs
, ARRAY_SIZE(srcs
));
4547 inst
->offset
= header_bits
;
4549 const unsigned dest_size
= nir_tex_instr_dest_size(instr
);
4550 if (devinfo
->gen
>= 9 &&
4551 instr
->op
!= nir_texop_tg4
&& instr
->op
!= nir_texop_query_levels
) {
4552 unsigned write_mask
= instr
->dest
.is_ssa
?
4553 nir_ssa_def_components_read(&instr
->dest
.ssa
):
4554 (1 << dest_size
) - 1;
4555 assert(write_mask
!= 0); /* dead code should have been eliminated */
4556 inst
->size_written
= util_last_bit(write_mask
) *
4557 inst
->dst
.component_size(inst
->exec_size
);
4559 inst
->size_written
= 4 * inst
->dst
.component_size(inst
->exec_size
);
4562 if (srcs
[TEX_LOGICAL_SRC_SHADOW_C
].file
!= BAD_FILE
)
4563 inst
->shadow_compare
= true;
4565 if (instr
->op
== nir_texop_tg4
&& devinfo
->gen
== 6)
4566 emit_gen6_gather_wa(key_tex
->gen6_gather_wa
[texture
], dst
);
4569 for (unsigned i
= 0; i
< dest_size
; i
++)
4570 nir_dest
[i
] = offset(dst
, bld
, i
);
4572 if (instr
->op
== nir_texop_query_levels
) {
4573 /* # levels is in .w */
4574 nir_dest
[0] = offset(dst
, bld
, 3);
4575 } else if (instr
->op
== nir_texop_txs
&&
4576 dest_size
>= 3 && devinfo
->gen
< 7) {
4577 /* Gen4-6 return 0 instead of 1 for single layer surfaces. */
4578 fs_reg depth
= offset(dst
, bld
, 2);
4579 nir_dest
[2] = vgrf(glsl_type::int_type
);
4580 bld
.emit_minmax(nir_dest
[2], depth
, brw_imm_d(1), BRW_CONDITIONAL_GE
);
4583 bld
.LOAD_PAYLOAD(get_nir_dest(instr
->dest
), nir_dest
, dest_size
, 0);
4587 fs_visitor::nir_emit_jump(const fs_builder
&bld
, nir_jump_instr
*instr
)
4589 switch (instr
->type
) {
4590 case nir_jump_break
:
4591 bld
.emit(BRW_OPCODE_BREAK
);
4593 case nir_jump_continue
:
4594 bld
.emit(BRW_OPCODE_CONTINUE
);
4596 case nir_jump_return
:
4598 unreachable("unknown jump");
4603 * This helper takes the result of a load operation that reads 32-bit elements
4611 * and shuffles the data to get this:
4618 * Which is exactly what we want if the load is reading 64-bit components
4619 * like doubles, where x represents the low 32-bit of the x double component
4620 * and y represents the high 32-bit of the x double component (likewise with
4621 * z and w for double component y). The parameter @components represents
4622 * the number of 64-bit components present in @src. This would typically be
4623 * 2 at most, since we can only fit 2 double elements in the result of a
4626 * Notice that @dst and @src can be the same register.
4629 shuffle_32bit_load_result_to_64bit_data(const fs_builder
&bld
,
4632 uint32_t components
)
4634 assert(type_sz(src
.type
) == 4);
4635 assert(type_sz(dst
.type
) == 8);
4637 /* A temporary that we will use to shuffle the 32-bit data of each
4638 * component in the vector into valid 64-bit data. We can't write directly
4639 * to dst because dst can be (and would usually be) the same as src
4640 * and in that case the first MOV in the loop below would overwrite the
4641 * data read in the second MOV.
4643 fs_reg tmp
= bld
.vgrf(dst
.type
);
4645 for (unsigned i
= 0; i
< components
; i
++) {
4646 const fs_reg component_i
= offset(src
, bld
, 2 * i
);
4648 bld
.MOV(subscript(tmp
, src
.type
, 0), component_i
);
4649 bld
.MOV(subscript(tmp
, src
.type
, 1), offset(component_i
, bld
, 1));
4651 bld
.MOV(offset(dst
, bld
, i
), tmp
);
4656 * This helper does the inverse operation of
4657 * SHUFFLE_32BIT_LOAD_RESULT_TO_64BIT_DATA.
4659 * We need to do this when we are going to use untyped write messsages that
4660 * operate with 32-bit components in order to arrange our 64-bit data to be
4661 * in the expected layout.
4663 * Notice that callers of this function, unlike in the case of the inverse
4664 * operation, would typically need to call this with dst and src being
4665 * different registers, since they would otherwise corrupt the original
4666 * 64-bit data they are about to write. Because of this the function checks
4667 * that the src and dst regions involved in the operation do not overlap.
4670 shuffle_64bit_data_for_32bit_write(const fs_builder
&bld
,
4673 uint32_t components
)
4675 assert(type_sz(src
.type
) == 8);
4676 assert(type_sz(dst
.type
) == 4);
4678 assert(!regions_overlap(
4679 dst
, 2 * components
* dst
.component_size(bld
.dispatch_width()),
4680 src
, components
* src
.component_size(bld
.dispatch_width())));
4682 for (unsigned i
= 0; i
< components
; i
++) {
4683 const fs_reg component_i
= offset(src
, bld
, i
);
4684 bld
.MOV(offset(dst
, bld
, 2 * i
), subscript(component_i
, dst
.type
, 0));
4685 bld
.MOV(offset(dst
, bld
, 2 * i
+ 1), subscript(component_i
, dst
.type
, 1));
4690 setup_imm_df(const fs_builder
&bld
, double v
)
4692 const struct gen_device_info
*devinfo
= bld
.shader
->devinfo
;
4693 assert(devinfo
->gen
>= 7);
4695 if (devinfo
->gen
>= 8)
4696 return brw_imm_df(v
);
4698 /* gen7.5 does not support DF immediates straighforward but the DIM
4699 * instruction allows to set the 64-bit immediate value.
4701 if (devinfo
->is_haswell
) {
4702 const fs_builder ubld
= bld
.exec_all().group(1, 0);
4703 fs_reg dst
= ubld
.vgrf(BRW_REGISTER_TYPE_DF
, 1);
4704 ubld
.DIM(dst
, brw_imm_df(v
));
4705 return component(dst
, 0);
4708 /* gen7 does not support DF immediates, so we generate a 64-bit constant by
4709 * writing the low 32-bit of the constant to suboffset 0 of a VGRF and
4710 * the high 32-bit to suboffset 4 and then applying a stride of 0.
4712 * Alternatively, we could also produce a normal VGRF (without stride 0)
4713 * by writing to all the channels in the VGRF, however, that would hit the
4714 * gen7 bug where we have to split writes that span more than 1 register
4715 * into instructions with a width of 4 (otherwise the write to the second
4716 * register written runs into an execmask hardware bug) which isn't very
4729 const fs_builder ubld
= bld
.exec_all().group(1, 0);
4730 const fs_reg tmp
= ubld
.vgrf(BRW_REGISTER_TYPE_UD
, 2);
4731 ubld
.MOV(tmp
, brw_imm_ud(di
.i1
));
4732 ubld
.MOV(horiz_offset(tmp
, 1), brw_imm_ud(di
.i2
));
4734 return component(retype(tmp
, BRW_REGISTER_TYPE_DF
), 0);