2 * Copyright © 2010 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 #include "compiler/glsl/ir.h"
26 #include "brw_fs_surface_builder.h"
30 using namespace brw::surface_access
;
33 fs_visitor::emit_nir_code()
35 /* emit the arrays used for inputs and outputs - load/store intrinsics will
36 * be converted to reads/writes of these arrays
40 nir_emit_system_values();
42 /* get the main function and emit it */
43 nir_foreach_function(function
, nir
) {
44 assert(strcmp(function
->name
, "main") == 0);
45 assert(function
->impl
);
46 nir_emit_impl(function
->impl
);
51 fs_visitor::nir_setup_outputs()
53 if (stage
== MESA_SHADER_TESS_CTRL
|| stage
== MESA_SHADER_FRAGMENT
)
56 unsigned vec4s
[VARYING_SLOT_TESS_MAX
] = { 0, };
58 /* Calculate the size of output registers in a separate pass, before
59 * allocating them. With ARB_enhanced_layouts, multiple output variables
60 * may occupy the same slot, but have different type sizes.
62 nir_foreach_variable(var
, &nir
->outputs
) {
63 const int loc
= var
->data
.driver_location
;
64 const unsigned var_vec4s
=
65 var
->data
.compact
? DIV_ROUND_UP(glsl_get_length(var
->type
), 4)
66 : type_size_vec4(var
->type
);
67 vec4s
[loc
] = MAX2(vec4s
[loc
], var_vec4s
);
70 nir_foreach_variable(var
, &nir
->outputs
) {
71 const int loc
= var
->data
.driver_location
;
72 if (outputs
[loc
].file
== BAD_FILE
) {
73 fs_reg reg
= bld
.vgrf(BRW_REGISTER_TYPE_F
, 4 * vec4s
[loc
]);
74 for (unsigned i
= 0; i
< vec4s
[loc
]; i
++) {
75 outputs
[loc
+ i
] = offset(reg
, bld
, 4 * i
);
82 fs_visitor::nir_setup_uniforms()
84 /* Only the first compile gets to set up uniforms. */
85 if (push_constant_loc
) {
86 assert(pull_constant_loc
);
90 uniforms
= nir
->num_uniforms
/ 4;
92 if (stage
== MESA_SHADER_COMPUTE
) {
93 /* Add a uniform for the thread local id. It must be the last uniform
96 assert(uniforms
== prog_data
->nr_params
);
97 uint32_t *param
= brw_stage_prog_data_add_params(prog_data
, 1);
98 *param
= BRW_PARAM_BUILTIN_SUBGROUP_ID
;
99 subgroup_id
= fs_reg(UNIFORM
, uniforms
++, BRW_REGISTER_TYPE_UD
);
104 emit_system_values_block(nir_block
*block
, fs_visitor
*v
)
108 nir_foreach_instr(instr
, block
) {
109 if (instr
->type
!= nir_instr_type_intrinsic
)
112 nir_intrinsic_instr
*intrin
= nir_instr_as_intrinsic(instr
);
113 switch (intrin
->intrinsic
) {
114 case nir_intrinsic_load_vertex_id
:
115 case nir_intrinsic_load_base_vertex
:
116 unreachable("should be lowered by nir_lower_system_values().");
118 case nir_intrinsic_load_vertex_id_zero_base
:
119 case nir_intrinsic_load_is_indexed_draw
:
120 case nir_intrinsic_load_first_vertex
:
121 case nir_intrinsic_load_instance_id
:
122 case nir_intrinsic_load_base_instance
:
123 case nir_intrinsic_load_draw_id
:
124 unreachable("should be lowered by brw_nir_lower_vs_inputs().");
126 case nir_intrinsic_load_invocation_id
:
127 if (v
->stage
== MESA_SHADER_TESS_CTRL
)
129 assert(v
->stage
== MESA_SHADER_GEOMETRY
);
130 reg
= &v
->nir_system_values
[SYSTEM_VALUE_INVOCATION_ID
];
131 if (reg
->file
== BAD_FILE
) {
132 const fs_builder abld
= v
->bld
.annotate("gl_InvocationID", NULL
);
133 fs_reg
g1(retype(brw_vec8_grf(1, 0), BRW_REGISTER_TYPE_UD
));
134 fs_reg iid
= abld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
135 abld
.SHR(iid
, g1
, brw_imm_ud(27u));
140 case nir_intrinsic_load_sample_pos
:
141 assert(v
->stage
== MESA_SHADER_FRAGMENT
);
142 reg
= &v
->nir_system_values
[SYSTEM_VALUE_SAMPLE_POS
];
143 if (reg
->file
== BAD_FILE
)
144 *reg
= *v
->emit_samplepos_setup();
147 case nir_intrinsic_load_sample_id
:
148 assert(v
->stage
== MESA_SHADER_FRAGMENT
);
149 reg
= &v
->nir_system_values
[SYSTEM_VALUE_SAMPLE_ID
];
150 if (reg
->file
== BAD_FILE
)
151 *reg
= *v
->emit_sampleid_setup();
154 case nir_intrinsic_load_sample_mask_in
:
155 assert(v
->stage
== MESA_SHADER_FRAGMENT
);
156 assert(v
->devinfo
->gen
>= 7);
157 reg
= &v
->nir_system_values
[SYSTEM_VALUE_SAMPLE_MASK_IN
];
158 if (reg
->file
== BAD_FILE
)
159 *reg
= *v
->emit_samplemaskin_setup();
162 case nir_intrinsic_load_work_group_id
:
163 assert(v
->stage
== MESA_SHADER_COMPUTE
);
164 reg
= &v
->nir_system_values
[SYSTEM_VALUE_WORK_GROUP_ID
];
165 if (reg
->file
== BAD_FILE
)
166 *reg
= *v
->emit_cs_work_group_id_setup();
169 case nir_intrinsic_load_helper_invocation
:
170 assert(v
->stage
== MESA_SHADER_FRAGMENT
);
171 reg
= &v
->nir_system_values
[SYSTEM_VALUE_HELPER_INVOCATION
];
172 if (reg
->file
== BAD_FILE
) {
173 const fs_builder abld
=
174 v
->bld
.annotate("gl_HelperInvocation", NULL
);
176 /* On Gen6+ (gl_HelperInvocation is only exposed on Gen7+) the
177 * pixel mask is in g1.7 of the thread payload.
179 * We move the per-channel pixel enable bit to the low bit of each
180 * channel by shifting the byte containing the pixel mask by the
181 * vector immediate 0x76543210UV.
183 * The region of <1,8,0> reads only 1 byte (the pixel masks for
184 * subspans 0 and 1) in SIMD8 and an additional byte (the pixel
185 * masks for 2 and 3) in SIMD16.
187 fs_reg shifted
= abld
.vgrf(BRW_REGISTER_TYPE_UW
, 1);
189 stride(byte_offset(retype(brw_vec1_grf(1, 0),
190 BRW_REGISTER_TYPE_UB
), 28),
192 brw_imm_v(0x76543210));
194 /* A set bit in the pixel mask means the channel is enabled, but
195 * that is the opposite of gl_HelperInvocation so we need to invert
198 * The negate source-modifier bit of logical instructions on Gen8+
199 * performs 1's complement negation, so we can use that instead of
202 fs_reg inverted
= negate(shifted
);
203 if (v
->devinfo
->gen
< 8) {
204 inverted
= abld
.vgrf(BRW_REGISTER_TYPE_UW
);
205 abld
.NOT(inverted
, shifted
);
208 /* We then resolve the 0/1 result to 0/~0 boolean values by ANDing
209 * with 1 and negating.
211 fs_reg anded
= abld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
212 abld
.AND(anded
, inverted
, brw_imm_uw(1));
214 fs_reg dst
= abld
.vgrf(BRW_REGISTER_TYPE_D
, 1);
215 abld
.MOV(dst
, negate(retype(anded
, BRW_REGISTER_TYPE_D
)));
229 fs_visitor::nir_emit_system_values()
231 nir_system_values
= ralloc_array(mem_ctx
, fs_reg
, SYSTEM_VALUE_MAX
);
232 for (unsigned i
= 0; i
< SYSTEM_VALUE_MAX
; i
++) {
233 nir_system_values
[i
] = fs_reg();
236 /* Always emit SUBGROUP_INVOCATION. Dead code will clean it up if we
237 * never end up using it.
240 const fs_builder abld
= bld
.annotate("gl_SubgroupInvocation", NULL
);
241 fs_reg
®
= nir_system_values
[SYSTEM_VALUE_SUBGROUP_INVOCATION
];
242 reg
= abld
.vgrf(BRW_REGISTER_TYPE_UW
);
244 const fs_builder allbld8
= abld
.group(8, 0).exec_all();
245 allbld8
.MOV(reg
, brw_imm_v(0x76543210));
246 if (dispatch_width
> 8)
247 allbld8
.ADD(byte_offset(reg
, 16), reg
, brw_imm_uw(8u));
248 if (dispatch_width
> 16) {
249 const fs_builder allbld16
= abld
.group(16, 0).exec_all();
250 allbld16
.ADD(byte_offset(reg
, 32), reg
, brw_imm_uw(16u));
254 nir_foreach_function(function
, nir
) {
255 assert(strcmp(function
->name
, "main") == 0);
256 assert(function
->impl
);
257 nir_foreach_block(block
, function
->impl
) {
258 emit_system_values_block(block
, this);
264 * Returns a type based on a reference_type (word, float, half-float) and a
267 * Reference BRW_REGISTER_TYPE are HF,F,DF,W,D,UW,UD.
269 * @FIXME: 64-bit return types are always DF on integer types to maintain
270 * compability with uses of DF previously to the introduction of int64
274 brw_reg_type_from_bit_size(const unsigned bit_size
,
275 const brw_reg_type reference_type
)
277 switch(reference_type
) {
278 case BRW_REGISTER_TYPE_HF
:
279 case BRW_REGISTER_TYPE_F
:
280 case BRW_REGISTER_TYPE_DF
:
283 return BRW_REGISTER_TYPE_HF
;
285 return BRW_REGISTER_TYPE_F
;
287 return BRW_REGISTER_TYPE_DF
;
289 unreachable("Invalid bit size");
291 case BRW_REGISTER_TYPE_W
:
292 case BRW_REGISTER_TYPE_D
:
293 case BRW_REGISTER_TYPE_Q
:
296 return BRW_REGISTER_TYPE_W
;
298 return BRW_REGISTER_TYPE_D
;
300 return BRW_REGISTER_TYPE_Q
;
302 unreachable("Invalid bit size");
304 case BRW_REGISTER_TYPE_UW
:
305 case BRW_REGISTER_TYPE_UD
:
306 case BRW_REGISTER_TYPE_UQ
:
309 return BRW_REGISTER_TYPE_UW
;
311 return BRW_REGISTER_TYPE_UD
;
313 return BRW_REGISTER_TYPE_UQ
;
315 unreachable("Invalid bit size");
318 unreachable("Unknown type");
323 fs_visitor::nir_emit_impl(nir_function_impl
*impl
)
325 nir_locals
= ralloc_array(mem_ctx
, fs_reg
, impl
->reg_alloc
);
326 for (unsigned i
= 0; i
< impl
->reg_alloc
; i
++) {
327 nir_locals
[i
] = fs_reg();
330 foreach_list_typed(nir_register
, reg
, node
, &impl
->registers
) {
331 unsigned array_elems
=
332 reg
->num_array_elems
== 0 ? 1 : reg
->num_array_elems
;
333 unsigned size
= array_elems
* reg
->num_components
;
334 const brw_reg_type reg_type
=
335 brw_reg_type_from_bit_size(reg
->bit_size
, BRW_REGISTER_TYPE_F
);
336 nir_locals
[reg
->index
] = bld
.vgrf(reg_type
, size
);
339 nir_ssa_values
= reralloc(mem_ctx
, nir_ssa_values
, fs_reg
,
342 nir_emit_cf_list(&impl
->body
);
346 fs_visitor::nir_emit_cf_list(exec_list
*list
)
348 exec_list_validate(list
);
349 foreach_list_typed(nir_cf_node
, node
, node
, list
) {
350 switch (node
->type
) {
352 nir_emit_if(nir_cf_node_as_if(node
));
355 case nir_cf_node_loop
:
356 nir_emit_loop(nir_cf_node_as_loop(node
));
359 case nir_cf_node_block
:
360 nir_emit_block(nir_cf_node_as_block(node
));
364 unreachable("Invalid CFG node block");
370 fs_visitor::nir_emit_if(nir_if
*if_stmt
)
372 /* first, put the condition into f0 */
373 fs_inst
*inst
= bld
.MOV(bld
.null_reg_d(),
374 retype(get_nir_src(if_stmt
->condition
),
375 BRW_REGISTER_TYPE_D
));
376 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
378 bld
.IF(BRW_PREDICATE_NORMAL
);
380 nir_emit_cf_list(&if_stmt
->then_list
);
382 /* note: if the else is empty, dead CF elimination will remove it */
383 bld
.emit(BRW_OPCODE_ELSE
);
385 nir_emit_cf_list(&if_stmt
->else_list
);
387 bld
.emit(BRW_OPCODE_ENDIF
);
391 fs_visitor::nir_emit_loop(nir_loop
*loop
)
393 bld
.emit(BRW_OPCODE_DO
);
395 nir_emit_cf_list(&loop
->body
);
397 bld
.emit(BRW_OPCODE_WHILE
);
401 fs_visitor::nir_emit_block(nir_block
*block
)
403 nir_foreach_instr(instr
, block
) {
404 nir_emit_instr(instr
);
409 fs_visitor::nir_emit_instr(nir_instr
*instr
)
411 const fs_builder abld
= bld
.annotate(NULL
, instr
);
413 switch (instr
->type
) {
414 case nir_instr_type_alu
:
415 nir_emit_alu(abld
, nir_instr_as_alu(instr
));
418 case nir_instr_type_intrinsic
:
420 case MESA_SHADER_VERTEX
:
421 nir_emit_vs_intrinsic(abld
, nir_instr_as_intrinsic(instr
));
423 case MESA_SHADER_TESS_CTRL
:
424 nir_emit_tcs_intrinsic(abld
, nir_instr_as_intrinsic(instr
));
426 case MESA_SHADER_TESS_EVAL
:
427 nir_emit_tes_intrinsic(abld
, nir_instr_as_intrinsic(instr
));
429 case MESA_SHADER_GEOMETRY
:
430 nir_emit_gs_intrinsic(abld
, nir_instr_as_intrinsic(instr
));
432 case MESA_SHADER_FRAGMENT
:
433 nir_emit_fs_intrinsic(abld
, nir_instr_as_intrinsic(instr
));
435 case MESA_SHADER_COMPUTE
:
436 nir_emit_cs_intrinsic(abld
, nir_instr_as_intrinsic(instr
));
439 unreachable("unsupported shader stage");
443 case nir_instr_type_tex
:
444 nir_emit_texture(abld
, nir_instr_as_tex(instr
));
447 case nir_instr_type_load_const
:
448 nir_emit_load_const(abld
, nir_instr_as_load_const(instr
));
451 case nir_instr_type_ssa_undef
:
452 /* We create a new VGRF for undefs on every use (by handling
453 * them in get_nir_src()), rather than for each definition.
454 * This helps register coalescing eliminate MOVs from undef.
458 case nir_instr_type_jump
:
459 nir_emit_jump(abld
, nir_instr_as_jump(instr
));
463 unreachable("unknown instruction type");
468 * Recognizes a parent instruction of nir_op_extract_* and changes the type to
472 fs_visitor::optimize_extract_to_float(nir_alu_instr
*instr
,
473 const fs_reg
&result
)
475 if (!instr
->src
[0].src
.is_ssa
||
476 !instr
->src
[0].src
.ssa
->parent_instr
)
479 if (instr
->src
[0].src
.ssa
->parent_instr
->type
!= nir_instr_type_alu
)
482 nir_alu_instr
*src0
=
483 nir_instr_as_alu(instr
->src
[0].src
.ssa
->parent_instr
);
485 if (src0
->op
!= nir_op_extract_u8
&& src0
->op
!= nir_op_extract_u16
&&
486 src0
->op
!= nir_op_extract_i8
&& src0
->op
!= nir_op_extract_i16
)
489 nir_const_value
*element
= nir_src_as_const_value(src0
->src
[1].src
);
490 assert(element
!= NULL
);
492 /* Element type to extract.*/
493 const brw_reg_type type
= brw_int_type(
494 src0
->op
== nir_op_extract_u16
|| src0
->op
== nir_op_extract_i16
? 2 : 1,
495 src0
->op
== nir_op_extract_i16
|| src0
->op
== nir_op_extract_i8
);
497 fs_reg op0
= get_nir_src(src0
->src
[0].src
);
498 op0
.type
= brw_type_for_nir_type(devinfo
,
499 (nir_alu_type
)(nir_op_infos
[src0
->op
].input_types
[0] |
500 nir_src_bit_size(src0
->src
[0].src
)));
501 op0
= offset(op0
, bld
, src0
->src
[0].swizzle
[0]);
503 set_saturate(instr
->dest
.saturate
,
504 bld
.MOV(result
, subscript(op0
, type
, element
->u32
[0])));
509 fs_visitor::optimize_frontfacing_ternary(nir_alu_instr
*instr
,
510 const fs_reg
&result
)
512 if (!instr
->src
[0].src
.is_ssa
||
513 instr
->src
[0].src
.ssa
->parent_instr
->type
!= nir_instr_type_intrinsic
)
516 nir_intrinsic_instr
*src0
=
517 nir_instr_as_intrinsic(instr
->src
[0].src
.ssa
->parent_instr
);
519 if (src0
->intrinsic
!= nir_intrinsic_load_front_face
)
522 nir_const_value
*value1
= nir_src_as_const_value(instr
->src
[1].src
);
523 if (!value1
|| fabsf(value1
->f32
[0]) != 1.0f
)
526 nir_const_value
*value2
= nir_src_as_const_value(instr
->src
[2].src
);
527 if (!value2
|| fabsf(value2
->f32
[0]) != 1.0f
)
530 fs_reg tmp
= vgrf(glsl_type::int_type
);
532 if (devinfo
->gen
>= 6) {
533 /* Bit 15 of g0.0 is 0 if the polygon is front facing. */
534 fs_reg g0
= fs_reg(retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_W
));
536 /* For (gl_FrontFacing ? 1.0 : -1.0), emit:
538 * or(8) tmp.1<2>W g0.0<0,1,0>W 0x00003f80W
539 * and(8) dst<1>D tmp<8,8,1>D 0xbf800000D
541 * and negate g0.0<0,1,0>W for (gl_FrontFacing ? -1.0 : 1.0).
543 * This negation looks like it's safe in practice, because bits 0:4 will
544 * surely be TRIANGLES
547 if (value1
->f32
[0] == -1.0f
) {
551 bld
.OR(subscript(tmp
, BRW_REGISTER_TYPE_W
, 1),
552 g0
, brw_imm_uw(0x3f80));
554 /* Bit 31 of g1.6 is 0 if the polygon is front facing. */
555 fs_reg g1_6
= fs_reg(retype(brw_vec1_grf(1, 6), BRW_REGISTER_TYPE_D
));
557 /* For (gl_FrontFacing ? 1.0 : -1.0), emit:
559 * or(8) tmp<1>D g1.6<0,1,0>D 0x3f800000D
560 * and(8) dst<1>D tmp<8,8,1>D 0xbf800000D
562 * and negate g1.6<0,1,0>D for (gl_FrontFacing ? -1.0 : 1.0).
564 * This negation looks like it's safe in practice, because bits 0:4 will
565 * surely be TRIANGLES
568 if (value1
->f32
[0] == -1.0f
) {
572 bld
.OR(tmp
, g1_6
, brw_imm_d(0x3f800000));
574 bld
.AND(retype(result
, BRW_REGISTER_TYPE_D
), tmp
, brw_imm_d(0xbf800000));
580 emit_find_msb_using_lzd(const fs_builder
&bld
,
581 const fs_reg
&result
,
589 /* LZD of an absolute value source almost always does the right
590 * thing. There are two problem values:
592 * * 0x80000000. Since abs(0x80000000) == 0x80000000, LZD returns
593 * 0. However, findMSB(int(0x80000000)) == 30.
595 * * 0xffffffff. Since abs(0xffffffff) == 1, LZD returns
596 * 31. Section 8.8 (Integer Functions) of the GLSL 4.50 spec says:
598 * For a value of zero or negative one, -1 will be returned.
600 * * Negative powers of two. LZD(abs(-(1<<x))) returns x, but
601 * findMSB(-(1<<x)) should return x-1.
603 * For all negative number cases, including 0x80000000 and
604 * 0xffffffff, the correct value is obtained from LZD if instead of
605 * negating the (already negative) value the logical-not is used. A
606 * conditonal logical-not can be achieved in two instructions.
608 temp
= bld
.vgrf(BRW_REGISTER_TYPE_D
);
610 bld
.ASR(temp
, src
, brw_imm_d(31));
611 bld
.XOR(temp
, temp
, src
);
614 bld
.LZD(retype(result
, BRW_REGISTER_TYPE_UD
),
615 retype(temp
, BRW_REGISTER_TYPE_UD
));
617 /* LZD counts from the MSB side, while GLSL's findMSB() wants the count
618 * from the LSB side. Subtract the result from 31 to convert the MSB
619 * count into an LSB count. If no bits are set, LZD will return 32.
620 * 31-32 = -1, which is exactly what findMSB() is supposed to return.
622 inst
= bld
.ADD(result
, retype(result
, BRW_REGISTER_TYPE_D
), brw_imm_d(31));
623 inst
->src
[0].negate
= true;
627 brw_rnd_mode_from_nir_op (const nir_op op
) {
629 case nir_op_f2f16_rtz
:
630 return BRW_RND_MODE_RTZ
;
631 case nir_op_f2f16_rtne
:
632 return BRW_RND_MODE_RTNE
;
634 unreachable("Operation doesn't support rounding mode");
639 fs_visitor::nir_emit_alu(const fs_builder
&bld
, nir_alu_instr
*instr
)
641 struct brw_wm_prog_key
*fs_key
= (struct brw_wm_prog_key
*) this->key
;
644 fs_reg result
= get_nir_dest(instr
->dest
.dest
);
645 result
.type
= brw_type_for_nir_type(devinfo
,
646 (nir_alu_type
)(nir_op_infos
[instr
->op
].output_type
|
647 nir_dest_bit_size(instr
->dest
.dest
)));
650 for (unsigned i
= 0; i
< nir_op_infos
[instr
->op
].num_inputs
; i
++) {
651 op
[i
] = get_nir_src(instr
->src
[i
].src
);
652 op
[i
].type
= brw_type_for_nir_type(devinfo
,
653 (nir_alu_type
)(nir_op_infos
[instr
->op
].input_types
[i
] |
654 nir_src_bit_size(instr
->src
[i
].src
)));
655 op
[i
].abs
= instr
->src
[i
].abs
;
656 op
[i
].negate
= instr
->src
[i
].negate
;
659 /* We get a bunch of mov's out of the from_ssa pass and they may still
660 * be vectorized. We'll handle them as a special-case. We'll also
661 * handle vecN here because it's basically the same thing.
669 fs_reg temp
= result
;
670 bool need_extra_copy
= false;
671 for (unsigned i
= 0; i
< nir_op_infos
[instr
->op
].num_inputs
; i
++) {
672 if (!instr
->src
[i
].src
.is_ssa
&&
673 instr
->dest
.dest
.reg
.reg
== instr
->src
[i
].src
.reg
.reg
) {
674 need_extra_copy
= true;
675 temp
= bld
.vgrf(result
.type
, 4);
680 for (unsigned i
= 0; i
< 4; i
++) {
681 if (!(instr
->dest
.write_mask
& (1 << i
)))
684 if (instr
->op
== nir_op_imov
|| instr
->op
== nir_op_fmov
) {
685 inst
= bld
.MOV(offset(temp
, bld
, i
),
686 offset(op
[0], bld
, instr
->src
[0].swizzle
[i
]));
688 inst
= bld
.MOV(offset(temp
, bld
, i
),
689 offset(op
[i
], bld
, instr
->src
[i
].swizzle
[0]));
691 inst
->saturate
= instr
->dest
.saturate
;
694 /* In this case the source and destination registers were the same,
695 * so we need to insert an extra set of moves in order to deal with
698 if (need_extra_copy
) {
699 for (unsigned i
= 0; i
< 4; i
++) {
700 if (!(instr
->dest
.write_mask
& (1 << i
)))
703 bld
.MOV(offset(result
, bld
, i
), offset(temp
, bld
, i
));
712 /* At this point, we have dealt with any instruction that operates on
713 * more than a single channel. Therefore, we can just adjust the source
714 * and destination registers for that channel and emit the instruction.
716 unsigned channel
= 0;
717 if (nir_op_infos
[instr
->op
].output_size
== 0) {
718 /* Since NIR is doing the scalarizing for us, we should only ever see
719 * vectorized operations with a single channel.
721 assert(_mesa_bitcount(instr
->dest
.write_mask
) == 1);
722 channel
= ffs(instr
->dest
.write_mask
) - 1;
724 result
= offset(result
, bld
, channel
);
727 for (unsigned i
= 0; i
< nir_op_infos
[instr
->op
].num_inputs
; i
++) {
728 assert(nir_op_infos
[instr
->op
].input_sizes
[i
] < 2);
729 op
[i
] = offset(op
[i
], bld
, instr
->src
[i
].swizzle
[channel
]);
735 if (optimize_extract_to_float(instr
, result
))
737 inst
= bld
.MOV(result
, op
[0]);
738 inst
->saturate
= instr
->dest
.saturate
;
741 case nir_op_f2f16_rtne
:
742 case nir_op_f2f16_rtz
:
743 bld
.emit(SHADER_OPCODE_RND_MODE
, bld
.null_reg_ud(),
744 brw_imm_d(brw_rnd_mode_from_nir_op(instr
->op
)));
747 /* In theory, it would be better to use BRW_OPCODE_F32TO16. Depending
748 * on the HW gen, it is a special hw opcode or just a MOV, and
749 * brw_F32TO16 (at brw_eu_emit) would do the work to chose.
751 * But if we want to use that opcode, we need to provide support on
752 * different optimizations and lowerings. As right now HF support is
753 * only for gen8+, it will be better to use directly the MOV, and use
754 * BRW_OPCODE_F32TO16 when/if we work for HF support on gen7.
757 case nir_op_f2f16_undef
:
760 /* TODO: Fixing aligment rules for conversions from 32-bits to
761 * 16-bit types should be moved to lower_conversions
763 fs_reg tmp
= bld
.vgrf(op
[0].type
, 1);
764 tmp
= subscript(tmp
, result
.type
, 0);
765 inst
= bld
.MOV(tmp
, op
[0]);
766 inst
->saturate
= instr
->dest
.saturate
;
767 inst
= bld
.MOV(result
, tmp
);
768 inst
->saturate
= instr
->dest
.saturate
;
779 /* CHV PRM, vol07, 3D Media GPGPU Engine, Register Region Restrictions:
781 * "When source or destination is 64b (...), regioning in Align1
782 * must follow these rules:
784 * 1. Source and destination horizontal stride must be aligned to
788 * This means that conversions from bit-sizes smaller than 64-bit to
789 * 64-bit need to have the source data elements aligned to 64-bit.
790 * This restriction does not apply to BDW and later.
792 if (nir_dest_bit_size(instr
->dest
.dest
) == 64 &&
793 nir_src_bit_size(instr
->src
[0].src
) < 64 &&
794 (devinfo
->is_cherryview
|| gen_device_info_is_9lp(devinfo
))) {
795 fs_reg tmp
= bld
.vgrf(result
.type
, 1);
796 tmp
= subscript(tmp
, op
[0].type
, 0);
797 inst
= bld
.MOV(tmp
, op
[0]);
798 inst
= bld
.MOV(result
, tmp
);
799 inst
->saturate
= instr
->dest
.saturate
;
812 inst
= bld
.MOV(result
, op
[0]);
813 inst
->saturate
= instr
->dest
.saturate
;
818 /* Straightforward since the source can be assumed to be
821 set_condmod(BRW_CONDITIONAL_NZ
, bld
.MOV(result
, op
[0]));
822 set_predicate(BRW_PREDICATE_NORMAL
, bld
.MOV(result
, brw_imm_f(1.0f
)));
824 } else if (type_sz(op
[0].type
) < 8) {
825 /* AND(val, 0x80000000) gives the sign bit.
827 * Predicated OR ORs 1.0 (0x3f800000) with the sign bit if val is not
830 bld
.CMP(bld
.null_reg_f(), op
[0], brw_imm_f(0.0f
), BRW_CONDITIONAL_NZ
);
832 fs_reg result_int
= retype(result
, BRW_REGISTER_TYPE_UD
);
833 op
[0].type
= BRW_REGISTER_TYPE_UD
;
834 result
.type
= BRW_REGISTER_TYPE_UD
;
835 bld
.AND(result_int
, op
[0], brw_imm_ud(0x80000000u
));
837 inst
= bld
.OR(result_int
, result_int
, brw_imm_ud(0x3f800000u
));
838 inst
->predicate
= BRW_PREDICATE_NORMAL
;
839 if (instr
->dest
.saturate
) {
840 inst
= bld
.MOV(result
, result
);
841 inst
->saturate
= true;
844 /* For doubles we do the same but we need to consider:
846 * - 2-src instructions can't operate with 64-bit immediates
847 * - The sign is encoded in the high 32-bit of each DF
848 * - We need to produce a DF result.
851 fs_reg zero
= vgrf(glsl_type::double_type
);
852 bld
.MOV(zero
, setup_imm_df(bld
, 0.0));
853 bld
.CMP(bld
.null_reg_df(), op
[0], zero
, BRW_CONDITIONAL_NZ
);
855 bld
.MOV(result
, zero
);
857 fs_reg r
= subscript(result
, BRW_REGISTER_TYPE_UD
, 1);
858 bld
.AND(r
, subscript(op
[0], BRW_REGISTER_TYPE_UD
, 1),
859 brw_imm_ud(0x80000000u
));
861 set_predicate(BRW_PREDICATE_NORMAL
,
862 bld
.OR(r
, r
, brw_imm_ud(0x3ff00000u
)));
864 if (instr
->dest
.saturate
) {
865 inst
= bld
.MOV(result
, result
);
866 inst
->saturate
= true;
873 /* ASR(val, 31) -> negative val generates 0xffffffff (signed -1).
874 * -> non-negative val generates 0x00000000.
875 * Predicated OR sets 1 if val is positive.
877 uint32_t bit_size
= nir_dest_bit_size(instr
->dest
.dest
);
878 assert(bit_size
== 32 || bit_size
== 16);
880 fs_reg zero
= bit_size
== 32 ? brw_imm_d(0) : brw_imm_w(0);
881 fs_reg one
= bit_size
== 32 ? brw_imm_d(1) : brw_imm_w(1);
882 fs_reg shift
= bit_size
== 32 ? brw_imm_d(31) : brw_imm_w(15);
884 bld
.CMP(bld
.null_reg_d(), op
[0], zero
, BRW_CONDITIONAL_G
);
885 bld
.ASR(result
, op
[0], shift
);
886 inst
= bld
.OR(result
, result
, one
);
887 inst
->predicate
= BRW_PREDICATE_NORMAL
;
892 inst
= bld
.emit(SHADER_OPCODE_RCP
, result
, op
[0]);
893 inst
->saturate
= instr
->dest
.saturate
;
897 inst
= bld
.emit(SHADER_OPCODE_EXP2
, result
, op
[0]);
898 inst
->saturate
= instr
->dest
.saturate
;
902 inst
= bld
.emit(SHADER_OPCODE_LOG2
, result
, op
[0]);
903 inst
->saturate
= instr
->dest
.saturate
;
907 inst
= bld
.emit(SHADER_OPCODE_SIN
, result
, op
[0]);
908 inst
->saturate
= instr
->dest
.saturate
;
912 inst
= bld
.emit(SHADER_OPCODE_COS
, result
, op
[0]);
913 inst
->saturate
= instr
->dest
.saturate
;
917 if (fs_key
->high_quality_derivatives
) {
918 inst
= bld
.emit(FS_OPCODE_DDX_FINE
, result
, op
[0]);
920 inst
= bld
.emit(FS_OPCODE_DDX_COARSE
, result
, op
[0]);
922 inst
->saturate
= instr
->dest
.saturate
;
924 case nir_op_fddx_fine
:
925 inst
= bld
.emit(FS_OPCODE_DDX_FINE
, result
, op
[0]);
926 inst
->saturate
= instr
->dest
.saturate
;
928 case nir_op_fddx_coarse
:
929 inst
= bld
.emit(FS_OPCODE_DDX_COARSE
, result
, op
[0]);
930 inst
->saturate
= instr
->dest
.saturate
;
933 if (fs_key
->high_quality_derivatives
) {
934 inst
= bld
.emit(FS_OPCODE_DDY_FINE
, result
, op
[0]);
936 inst
= bld
.emit(FS_OPCODE_DDY_COARSE
, result
, op
[0]);
938 inst
->saturate
= instr
->dest
.saturate
;
940 case nir_op_fddy_fine
:
941 inst
= bld
.emit(FS_OPCODE_DDY_FINE
, result
, op
[0]);
942 inst
->saturate
= instr
->dest
.saturate
;
944 case nir_op_fddy_coarse
:
945 inst
= bld
.emit(FS_OPCODE_DDY_COARSE
, result
, op
[0]);
946 inst
->saturate
= instr
->dest
.saturate
;
951 inst
= bld
.ADD(result
, op
[0], op
[1]);
952 inst
->saturate
= instr
->dest
.saturate
;
956 inst
= bld
.MUL(result
, op
[0], op
[1]);
957 inst
->saturate
= instr
->dest
.saturate
;
961 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
962 bld
.MUL(result
, op
[0], op
[1]);
965 case nir_op_imul_high
:
966 case nir_op_umul_high
:
967 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
968 bld
.emit(SHADER_OPCODE_MULH
, result
, op
[0], op
[1]);
973 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
974 bld
.emit(SHADER_OPCODE_INT_QUOTIENT
, result
, op
[0], op
[1]);
977 case nir_op_uadd_carry
:
978 unreachable("Should have been lowered by carry_to_arith().");
980 case nir_op_usub_borrow
:
981 unreachable("Should have been lowered by borrow_to_arith().");
985 /* According to the sign table for INT DIV in the Ivy Bridge PRM, it
986 * appears that our hardware just does the right thing for signed
989 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
990 bld
.emit(SHADER_OPCODE_INT_REMAINDER
, result
, op
[0], op
[1]);
994 /* Get a regular C-style remainder. If a % b == 0, set the predicate. */
995 bld
.emit(SHADER_OPCODE_INT_REMAINDER
, result
, op
[0], op
[1]);
997 /* Math instructions don't support conditional mod */
998 inst
= bld
.MOV(bld
.null_reg_d(), result
);
999 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
1001 /* Now, we need to determine if signs of the sources are different.
1002 * When we XOR the sources, the top bit is 0 if they are the same and 1
1003 * if they are different. We can then use a conditional modifier to
1004 * turn that into a predicate. This leads us to an XOR.l instruction.
1006 * Technically, according to the PRM, you're not allowed to use .l on a
1007 * XOR instruction. However, emperical experiments and Curro's reading
1008 * of the simulator source both indicate that it's safe.
1010 fs_reg tmp
= bld
.vgrf(BRW_REGISTER_TYPE_D
);
1011 inst
= bld
.XOR(tmp
, op
[0], op
[1]);
1012 inst
->predicate
= BRW_PREDICATE_NORMAL
;
1013 inst
->conditional_mod
= BRW_CONDITIONAL_L
;
1015 /* If the result of the initial remainder operation is non-zero and the
1016 * two sources have different signs, add in a copy of op[1] to get the
1017 * final integer modulus value.
1019 inst
= bld
.ADD(result
, result
, op
[1]);
1020 inst
->predicate
= BRW_PREDICATE_NORMAL
;
1028 fs_reg dest
= result
;
1030 const uint32_t bit_size
= nir_src_bit_size(instr
->src
[0].src
);
1032 dest
= bld
.vgrf(op
[0].type
, 1);
1034 brw_conditional_mod cond
;
1035 switch (instr
->op
) {
1037 cond
= BRW_CONDITIONAL_L
;
1040 cond
= BRW_CONDITIONAL_GE
;
1043 cond
= BRW_CONDITIONAL_Z
;
1046 cond
= BRW_CONDITIONAL_NZ
;
1049 unreachable("bad opcode");
1052 bld
.CMP(dest
, op
[0], op
[1], cond
);
1054 if (bit_size
> 32) {
1055 bld
.MOV(result
, subscript(dest
, BRW_REGISTER_TYPE_UD
, 0));
1056 } else if(bit_size
< 32) {
1057 /* When we convert the result to 32-bit we need to be careful and do
1058 * it as a signed conversion to get sign extension (for 32-bit true)
1060 const brw_reg_type src_type
=
1061 brw_reg_type_from_bit_size(bit_size
, BRW_REGISTER_TYPE_D
);
1063 bld
.MOV(retype(result
, BRW_REGISTER_TYPE_D
), retype(dest
, src_type
));
1074 fs_reg dest
= result
;
1076 const uint32_t bit_size
= nir_src_bit_size(instr
->src
[0].src
);
1078 dest
= bld
.vgrf(op
[0].type
, 1);
1080 brw_conditional_mod cond
;
1081 switch (instr
->op
) {
1084 cond
= BRW_CONDITIONAL_L
;
1088 cond
= BRW_CONDITIONAL_GE
;
1091 cond
= BRW_CONDITIONAL_Z
;
1094 cond
= BRW_CONDITIONAL_NZ
;
1097 unreachable("bad opcode");
1099 bld
.CMP(dest
, op
[0], op
[1], cond
);
1101 if (bit_size
> 32) {
1102 bld
.MOV(result
, subscript(dest
, BRW_REGISTER_TYPE_UD
, 0));
1103 } else if (bit_size
< 32) {
1104 /* When we convert the result to 32-bit we need to be careful and do
1105 * it as a signed conversion to get sign extension (for 32-bit true)
1107 const brw_reg_type src_type
=
1108 brw_reg_type_from_bit_size(bit_size
, BRW_REGISTER_TYPE_D
);
1110 bld
.MOV(retype(result
, BRW_REGISTER_TYPE_D
), retype(dest
, src_type
));
1116 if (devinfo
->gen
>= 8) {
1117 op
[0] = resolve_source_modifiers(op
[0]);
1119 bld
.NOT(result
, op
[0]);
1122 if (devinfo
->gen
>= 8) {
1123 op
[0] = resolve_source_modifiers(op
[0]);
1124 op
[1] = resolve_source_modifiers(op
[1]);
1126 bld
.XOR(result
, op
[0], op
[1]);
1129 if (devinfo
->gen
>= 8) {
1130 op
[0] = resolve_source_modifiers(op
[0]);
1131 op
[1] = resolve_source_modifiers(op
[1]);
1133 bld
.OR(result
, op
[0], op
[1]);
1136 if (devinfo
->gen
>= 8) {
1137 op
[0] = resolve_source_modifiers(op
[0]);
1138 op
[1] = resolve_source_modifiers(op
[1]);
1140 bld
.AND(result
, op
[0], op
[1]);
1146 case nir_op_ball_fequal2
:
1147 case nir_op_ball_iequal2
:
1148 case nir_op_ball_fequal3
:
1149 case nir_op_ball_iequal3
:
1150 case nir_op_ball_fequal4
:
1151 case nir_op_ball_iequal4
:
1152 case nir_op_bany_fnequal2
:
1153 case nir_op_bany_inequal2
:
1154 case nir_op_bany_fnequal3
:
1155 case nir_op_bany_inequal3
:
1156 case nir_op_bany_fnequal4
:
1157 case nir_op_bany_inequal4
:
1158 unreachable("Lowered by nir_lower_alu_reductions");
1160 case nir_op_fnoise1_1
:
1161 case nir_op_fnoise1_2
:
1162 case nir_op_fnoise1_3
:
1163 case nir_op_fnoise1_4
:
1164 case nir_op_fnoise2_1
:
1165 case nir_op_fnoise2_2
:
1166 case nir_op_fnoise2_3
:
1167 case nir_op_fnoise2_4
:
1168 case nir_op_fnoise3_1
:
1169 case nir_op_fnoise3_2
:
1170 case nir_op_fnoise3_3
:
1171 case nir_op_fnoise3_4
:
1172 case nir_op_fnoise4_1
:
1173 case nir_op_fnoise4_2
:
1174 case nir_op_fnoise4_3
:
1175 case nir_op_fnoise4_4
:
1176 unreachable("not reached: should be handled by lower_noise");
1179 unreachable("not reached: should be handled by ldexp_to_arith()");
1182 inst
= bld
.emit(SHADER_OPCODE_SQRT
, result
, op
[0]);
1183 inst
->saturate
= instr
->dest
.saturate
;
1187 inst
= bld
.emit(SHADER_OPCODE_RSQ
, result
, op
[0]);
1188 inst
->saturate
= instr
->dest
.saturate
;
1193 bld
.MOV(result
, negate(op
[0]));
1198 uint32_t bit_size
= nir_src_bit_size(instr
->src
[0].src
);
1199 if (bit_size
== 64) {
1200 /* two-argument instructions can't take 64-bit immediates */
1204 if (instr
->op
== nir_op_f2b
) {
1205 zero
= vgrf(glsl_type::double_type
);
1206 tmp
= vgrf(glsl_type::double_type
);
1207 bld
.MOV(zero
, setup_imm_df(bld
, 0.0));
1209 zero
= vgrf(glsl_type::int64_t_type
);
1210 tmp
= vgrf(glsl_type::int64_t_type
);
1211 bld
.MOV(zero
, brw_imm_q(0));
1214 /* A SIMD16 execution needs to be split in two instructions, so use
1215 * a vgrf instead of the flag register as dst so instruction splitting
1218 bld
.CMP(tmp
, op
[0], zero
, BRW_CONDITIONAL_NZ
);
1219 bld
.MOV(result
, subscript(tmp
, BRW_REGISTER_TYPE_UD
, 0));
1222 if (bit_size
== 32) {
1223 zero
= instr
->op
== nir_op_f2b
? brw_imm_f(0.0f
) : brw_imm_d(0);
1225 assert(bit_size
== 16);
1226 zero
= instr
->op
== nir_op_f2b
?
1227 retype(brw_imm_w(0), BRW_REGISTER_TYPE_HF
) : brw_imm_w(0);
1229 bld
.CMP(result
, op
[0], zero
, BRW_CONDITIONAL_NZ
);
1235 inst
= bld
.RNDZ(result
, op
[0]);
1236 inst
->saturate
= instr
->dest
.saturate
;
1239 case nir_op_fceil
: {
1240 op
[0].negate
= !op
[0].negate
;
1241 fs_reg temp
= vgrf(glsl_type::float_type
);
1242 bld
.RNDD(temp
, op
[0]);
1244 inst
= bld
.MOV(result
, temp
);
1245 inst
->saturate
= instr
->dest
.saturate
;
1249 inst
= bld
.RNDD(result
, op
[0]);
1250 inst
->saturate
= instr
->dest
.saturate
;
1253 inst
= bld
.FRC(result
, op
[0]);
1254 inst
->saturate
= instr
->dest
.saturate
;
1256 case nir_op_fround_even
:
1257 inst
= bld
.RNDE(result
, op
[0]);
1258 inst
->saturate
= instr
->dest
.saturate
;
1261 case nir_op_fquantize2f16
: {
1262 fs_reg tmp16
= bld
.vgrf(BRW_REGISTER_TYPE_D
);
1263 fs_reg tmp32
= bld
.vgrf(BRW_REGISTER_TYPE_F
);
1264 fs_reg zero
= bld
.vgrf(BRW_REGISTER_TYPE_F
);
1266 /* The destination stride must be at least as big as the source stride. */
1267 tmp16
.type
= BRW_REGISTER_TYPE_W
;
1270 /* Check for denormal */
1271 fs_reg abs_src0
= op
[0];
1272 abs_src0
.abs
= true;
1273 bld
.CMP(bld
.null_reg_f(), abs_src0
, brw_imm_f(ldexpf(1.0, -14)),
1275 /* Get the appropriately signed zero */
1276 bld
.AND(retype(zero
, BRW_REGISTER_TYPE_UD
),
1277 retype(op
[0], BRW_REGISTER_TYPE_UD
),
1278 brw_imm_ud(0x80000000));
1279 /* Do the actual F32 -> F16 -> F32 conversion */
1280 bld
.emit(BRW_OPCODE_F32TO16
, tmp16
, op
[0]);
1281 bld
.emit(BRW_OPCODE_F16TO32
, tmp32
, tmp16
);
1282 /* Select that or zero based on normal status */
1283 inst
= bld
.SEL(result
, zero
, tmp32
);
1284 inst
->predicate
= BRW_PREDICATE_NORMAL
;
1285 inst
->saturate
= instr
->dest
.saturate
;
1292 inst
= bld
.emit_minmax(result
, op
[0], op
[1], BRW_CONDITIONAL_L
);
1293 inst
->saturate
= instr
->dest
.saturate
;
1299 inst
= bld
.emit_minmax(result
, op
[0], op
[1], BRW_CONDITIONAL_GE
);
1300 inst
->saturate
= instr
->dest
.saturate
;
1303 case nir_op_pack_snorm_2x16
:
1304 case nir_op_pack_snorm_4x8
:
1305 case nir_op_pack_unorm_2x16
:
1306 case nir_op_pack_unorm_4x8
:
1307 case nir_op_unpack_snorm_2x16
:
1308 case nir_op_unpack_snorm_4x8
:
1309 case nir_op_unpack_unorm_2x16
:
1310 case nir_op_unpack_unorm_4x8
:
1311 case nir_op_unpack_half_2x16
:
1312 case nir_op_pack_half_2x16
:
1313 unreachable("not reached: should be handled by lower_packing_builtins");
1315 case nir_op_unpack_half_2x16_split_x
:
1316 inst
= bld
.emit(FS_OPCODE_UNPACK_HALF_2x16_SPLIT_X
, result
, op
[0]);
1317 inst
->saturate
= instr
->dest
.saturate
;
1319 case nir_op_unpack_half_2x16_split_y
:
1320 inst
= bld
.emit(FS_OPCODE_UNPACK_HALF_2x16_SPLIT_Y
, result
, op
[0]);
1321 inst
->saturate
= instr
->dest
.saturate
;
1324 case nir_op_pack_64_2x32_split
:
1325 case nir_op_pack_32_2x16_split
:
1326 bld
.emit(FS_OPCODE_PACK
, result
, op
[0], op
[1]);
1329 case nir_op_unpack_64_2x32_split_x
:
1330 case nir_op_unpack_64_2x32_split_y
: {
1331 if (instr
->op
== nir_op_unpack_64_2x32_split_x
)
1332 bld
.MOV(result
, subscript(op
[0], BRW_REGISTER_TYPE_UD
, 0));
1334 bld
.MOV(result
, subscript(op
[0], BRW_REGISTER_TYPE_UD
, 1));
1338 case nir_op_unpack_32_2x16_split_x
:
1339 case nir_op_unpack_32_2x16_split_y
: {
1340 if (instr
->op
== nir_op_unpack_32_2x16_split_x
)
1341 bld
.MOV(result
, subscript(op
[0], BRW_REGISTER_TYPE_UW
, 0));
1343 bld
.MOV(result
, subscript(op
[0], BRW_REGISTER_TYPE_UW
, 1));
1348 inst
= bld
.emit(SHADER_OPCODE_POW
, result
, op
[0], op
[1]);
1349 inst
->saturate
= instr
->dest
.saturate
;
1352 case nir_op_bitfield_reverse
:
1353 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1354 bld
.BFREV(result
, op
[0]);
1357 case nir_op_bit_count
:
1358 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1359 bld
.CBIT(result
, op
[0]);
1362 case nir_op_ufind_msb
: {
1363 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1364 emit_find_msb_using_lzd(bld
, result
, op
[0], false);
1368 case nir_op_ifind_msb
: {
1369 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1371 if (devinfo
->gen
< 7) {
1372 emit_find_msb_using_lzd(bld
, result
, op
[0], true);
1374 bld
.FBH(retype(result
, BRW_REGISTER_TYPE_UD
), op
[0]);
1376 /* FBH counts from the MSB side, while GLSL's findMSB() wants the
1377 * count from the LSB side. If FBH didn't return an error
1378 * (0xFFFFFFFF), then subtract the result from 31 to convert the MSB
1379 * count into an LSB count.
1381 bld
.CMP(bld
.null_reg_d(), result
, brw_imm_d(-1), BRW_CONDITIONAL_NZ
);
1383 inst
= bld
.ADD(result
, result
, brw_imm_d(31));
1384 inst
->predicate
= BRW_PREDICATE_NORMAL
;
1385 inst
->src
[0].negate
= true;
1390 case nir_op_find_lsb
:
1391 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1393 if (devinfo
->gen
< 7) {
1394 fs_reg temp
= vgrf(glsl_type::int_type
);
1396 /* (x & -x) generates a value that consists of only the LSB of x.
1397 * For all powers of 2, findMSB(y) == findLSB(y).
1399 fs_reg src
= retype(op
[0], BRW_REGISTER_TYPE_D
);
1400 fs_reg negated_src
= src
;
1402 /* One must be negated, and the other must be non-negated. It
1403 * doesn't matter which is which.
1405 negated_src
.negate
= true;
1408 bld
.AND(temp
, src
, negated_src
);
1409 emit_find_msb_using_lzd(bld
, result
, temp
, false);
1411 bld
.FBL(result
, op
[0]);
1415 case nir_op_ubitfield_extract
:
1416 case nir_op_ibitfield_extract
:
1417 unreachable("should have been lowered");
1420 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1421 bld
.BFE(result
, op
[2], op
[1], op
[0]);
1424 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1425 bld
.BFI1(result
, op
[0], op
[1]);
1428 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1429 bld
.BFI2(result
, op
[0], op
[1], op
[2]);
1432 case nir_op_bitfield_insert
:
1433 unreachable("not reached: should have been lowered");
1438 fs_reg shift_count
= op
[1];
1440 if (devinfo
->is_cherryview
|| gen_device_info_is_9lp(devinfo
)) {
1441 if (op
[1].file
== VGRF
&&
1442 (result
.type
== BRW_REGISTER_TYPE_Q
||
1443 result
.type
== BRW_REGISTER_TYPE_UQ
)) {
1444 shift_count
= fs_reg(VGRF
, alloc
.allocate(dispatch_width
/ 4),
1445 BRW_REGISTER_TYPE_UD
);
1446 shift_count
.stride
= 2;
1447 bld
.MOV(shift_count
, op
[1]);
1451 switch (instr
->op
) {
1453 bld
.SHL(result
, op
[0], shift_count
);
1456 bld
.ASR(result
, op
[0], shift_count
);
1459 bld
.SHR(result
, op
[0], shift_count
);
1462 unreachable("not reached");
1467 case nir_op_pack_half_2x16_split
:
1468 bld
.emit(FS_OPCODE_PACK_HALF_2x16_SPLIT
, result
, op
[0], op
[1]);
1472 inst
= bld
.MAD(result
, op
[2], op
[1], op
[0]);
1473 inst
->saturate
= instr
->dest
.saturate
;
1477 inst
= bld
.LRP(result
, op
[0], op
[1], op
[2]);
1478 inst
->saturate
= instr
->dest
.saturate
;
1482 if (optimize_frontfacing_ternary(instr
, result
))
1485 bld
.CMP(bld
.null_reg_d(), op
[0], brw_imm_d(0), BRW_CONDITIONAL_NZ
);
1486 inst
= bld
.SEL(result
, op
[1], op
[2]);
1487 inst
->predicate
= BRW_PREDICATE_NORMAL
;
1490 case nir_op_extract_u8
:
1491 case nir_op_extract_i8
: {
1492 nir_const_value
*byte
= nir_src_as_const_value(instr
->src
[1].src
);
1493 assert(byte
!= NULL
);
1498 * There is no direct conversion from B/UB to Q/UQ or Q/UQ to B/UB.
1499 * Use two instructions and a word or DWord intermediate integer type.
1501 if (nir_dest_bit_size(instr
->dest
.dest
) == 64) {
1502 const brw_reg_type type
= brw_int_type(2, instr
->op
== nir_op_extract_i8
);
1504 if (instr
->op
== nir_op_extract_i8
) {
1505 /* If we need to sign extend, extract to a word first */
1506 fs_reg w_temp
= bld
.vgrf(BRW_REGISTER_TYPE_W
);
1507 bld
.MOV(w_temp
, subscript(op
[0], type
, byte
->u32
[0]));
1508 bld
.MOV(result
, w_temp
);
1510 /* Otherwise use an AND with 0xff and a word type */
1511 bld
.AND(result
, subscript(op
[0], type
, byte
->u32
[0] / 2), brw_imm_uw(0xff));
1514 const brw_reg_type type
= brw_int_type(1, instr
->op
== nir_op_extract_i8
);
1515 bld
.MOV(result
, subscript(op
[0], type
, byte
->u32
[0]));
1520 case nir_op_extract_u16
:
1521 case nir_op_extract_i16
: {
1522 const brw_reg_type type
= brw_int_type(2, instr
->op
== nir_op_extract_i16
);
1523 nir_const_value
*word
= nir_src_as_const_value(instr
->src
[1].src
);
1524 assert(word
!= NULL
);
1525 bld
.MOV(result
, subscript(op
[0], type
, word
->u32
[0]));
1530 unreachable("unhandled instruction");
1533 /* If we need to do a boolean resolve, replace the result with -(x & 1)
1534 * to sign extend the low bit to 0/~0
1536 if (devinfo
->gen
<= 5 &&
1537 (instr
->instr
.pass_flags
& BRW_NIR_BOOLEAN_MASK
) == BRW_NIR_BOOLEAN_NEEDS_RESOLVE
) {
1538 fs_reg masked
= vgrf(glsl_type::int_type
);
1539 bld
.AND(masked
, result
, brw_imm_d(1));
1540 masked
.negate
= true;
1541 bld
.MOV(retype(result
, BRW_REGISTER_TYPE_D
), masked
);
1546 fs_visitor::nir_emit_load_const(const fs_builder
&bld
,
1547 nir_load_const_instr
*instr
)
1549 const brw_reg_type reg_type
=
1550 brw_reg_type_from_bit_size(instr
->def
.bit_size
, BRW_REGISTER_TYPE_D
);
1551 fs_reg reg
= bld
.vgrf(reg_type
, instr
->def
.num_components
);
1553 switch (instr
->def
.bit_size
) {
1555 for (unsigned i
= 0; i
< instr
->def
.num_components
; i
++)
1556 bld
.MOV(offset(reg
, bld
, i
), brw_imm_w(instr
->value
.i16
[i
]));
1560 for (unsigned i
= 0; i
< instr
->def
.num_components
; i
++)
1561 bld
.MOV(offset(reg
, bld
, i
), brw_imm_d(instr
->value
.i32
[i
]));
1565 assert(devinfo
->gen
>= 7);
1566 if (devinfo
->gen
== 7) {
1567 /* We don't get 64-bit integer types until gen8 */
1568 for (unsigned i
= 0; i
< instr
->def
.num_components
; i
++) {
1569 bld
.MOV(retype(offset(reg
, bld
, i
), BRW_REGISTER_TYPE_DF
),
1570 setup_imm_df(bld
, instr
->value
.f64
[i
]));
1573 for (unsigned i
= 0; i
< instr
->def
.num_components
; i
++)
1574 bld
.MOV(offset(reg
, bld
, i
), brw_imm_q(instr
->value
.i64
[i
]));
1579 unreachable("Invalid bit size");
1582 nir_ssa_values
[instr
->def
.index
] = reg
;
1586 fs_visitor::get_nir_src(const nir_src
&src
)
1590 if (src
.ssa
->parent_instr
->type
== nir_instr_type_ssa_undef
) {
1591 const brw_reg_type reg_type
=
1592 brw_reg_type_from_bit_size(src
.ssa
->bit_size
, BRW_REGISTER_TYPE_D
);
1593 reg
= bld
.vgrf(reg_type
, src
.ssa
->num_components
);
1595 reg
= nir_ssa_values
[src
.ssa
->index
];
1598 /* We don't handle indirects on locals */
1599 assert(src
.reg
.indirect
== NULL
);
1600 reg
= offset(nir_locals
[src
.reg
.reg
->index
], bld
,
1601 src
.reg
.base_offset
* src
.reg
.reg
->num_components
);
1604 if (nir_src_bit_size(src
) == 64 && devinfo
->gen
== 7) {
1605 /* The only 64-bit type available on gen7 is DF, so use that. */
1606 reg
.type
= BRW_REGISTER_TYPE_DF
;
1608 /* To avoid floating-point denorm flushing problems, set the type by
1609 * default to an integer type - instructions that need floating point
1610 * semantics will set this to F if they need to
1612 reg
.type
= brw_reg_type_from_bit_size(nir_src_bit_size(src
),
1613 BRW_REGISTER_TYPE_D
);
1620 * Return an IMM for constants; otherwise call get_nir_src() as normal.
1622 * This function should not be called on any value which may be 64 bits.
1623 * We could theoretically support 64-bit on gen8+ but we choose not to
1624 * because it wouldn't work in general (no gen7 support) and there are
1625 * enough restrictions in 64-bit immediates that you can't take the return
1626 * value and treat it the same as the result of get_nir_src().
1629 fs_visitor::get_nir_src_imm(const nir_src
&src
)
1631 nir_const_value
*val
= nir_src_as_const_value(src
);
1632 assert(nir_src_bit_size(src
) == 32);
1633 return val
? fs_reg(brw_imm_d(val
->i32
[0])) : get_nir_src(src
);
1637 fs_visitor::get_nir_dest(const nir_dest
&dest
)
1640 const brw_reg_type reg_type
=
1641 brw_reg_type_from_bit_size(dest
.ssa
.bit_size
, BRW_REGISTER_TYPE_F
);
1642 nir_ssa_values
[dest
.ssa
.index
] =
1643 bld
.vgrf(reg_type
, dest
.ssa
.num_components
);
1644 return nir_ssa_values
[dest
.ssa
.index
];
1646 /* We don't handle indirects on locals */
1647 assert(dest
.reg
.indirect
== NULL
);
1648 return offset(nir_locals
[dest
.reg
.reg
->index
], bld
,
1649 dest
.reg
.base_offset
* dest
.reg
.reg
->num_components
);
1654 fs_visitor::get_nir_image_deref(const nir_deref_var
*deref
)
1656 fs_reg
image(UNIFORM
, deref
->var
->data
.driver_location
/ 4,
1657 BRW_REGISTER_TYPE_UD
);
1659 unsigned indirect_max
= 0;
1661 for (const nir_deref
*tail
= &deref
->deref
; tail
->child
;
1662 tail
= tail
->child
) {
1663 const nir_deref_array
*deref_array
= nir_deref_as_array(tail
->child
);
1664 assert(tail
->child
->deref_type
== nir_deref_type_array
);
1665 const unsigned size
= glsl_get_length(tail
->type
);
1666 const unsigned element_size
= type_size_scalar(deref_array
->deref
.type
);
1667 const unsigned base
= MIN2(deref_array
->base_offset
, size
- 1);
1668 image
= offset(image
, bld
, base
* element_size
);
1670 if (deref_array
->deref_array_type
== nir_deref_array_type_indirect
) {
1671 fs_reg tmp
= vgrf(glsl_type::uint_type
);
1673 /* Accessing an invalid surface index with the dataport can result
1674 * in a hang. According to the spec "if the index used to
1675 * select an individual element is negative or greater than or
1676 * equal to the size of the array, the results of the operation
1677 * are undefined but may not lead to termination" -- which is one
1678 * of the possible outcomes of the hang. Clamp the index to
1679 * prevent access outside of the array bounds.
1681 bld
.emit_minmax(tmp
, retype(get_nir_src(deref_array
->indirect
),
1682 BRW_REGISTER_TYPE_UD
),
1683 brw_imm_ud(size
- base
- 1), BRW_CONDITIONAL_L
);
1685 indirect_max
+= element_size
* (tail
->type
->length
- 1);
1687 bld
.MUL(tmp
, tmp
, brw_imm_ud(element_size
* 4));
1688 if (indirect
.file
== BAD_FILE
) {
1691 bld
.ADD(indirect
, indirect
, tmp
);
1696 if (indirect
.file
== BAD_FILE
) {
1699 /* Emit a pile of MOVs to load the uniform into a temporary. The
1700 * dead-code elimination pass will get rid of what we don't use.
1702 fs_reg tmp
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, BRW_IMAGE_PARAM_SIZE
);
1703 for (unsigned j
= 0; j
< BRW_IMAGE_PARAM_SIZE
; j
++) {
1704 bld
.emit(SHADER_OPCODE_MOV_INDIRECT
,
1705 offset(tmp
, bld
, j
), offset(image
, bld
, j
),
1706 indirect
, brw_imm_ud((indirect_max
+ 1) * 4));
1713 fs_visitor::emit_percomp(const fs_builder
&bld
, const fs_inst
&inst
,
1716 for (unsigned i
= 0; i
< 4; i
++) {
1717 if (!((wr_mask
>> i
) & 1))
1720 fs_inst
*new_inst
= new(mem_ctx
) fs_inst(inst
);
1721 new_inst
->dst
= offset(new_inst
->dst
, bld
, i
);
1722 for (unsigned j
= 0; j
< new_inst
->sources
; j
++)
1723 if (new_inst
->src
[j
].file
== VGRF
)
1724 new_inst
->src
[j
] = offset(new_inst
->src
[j
], bld
, i
);
1731 * Get the matching channel register datatype for an image intrinsic of the
1732 * specified GLSL image type.
1735 get_image_base_type(const glsl_type
*type
)
1737 switch ((glsl_base_type
)type
->sampled_type
) {
1738 case GLSL_TYPE_UINT
:
1739 return BRW_REGISTER_TYPE_UD
;
1741 return BRW_REGISTER_TYPE_D
;
1742 case GLSL_TYPE_FLOAT
:
1743 return BRW_REGISTER_TYPE_F
;
1745 unreachable("Not reached.");
1750 * Get the appropriate atomic op for an image atomic intrinsic.
1753 get_image_atomic_op(nir_intrinsic_op op
, const glsl_type
*type
)
1756 case nir_intrinsic_image_var_atomic_add
:
1758 case nir_intrinsic_image_var_atomic_min
:
1759 return (get_image_base_type(type
) == BRW_REGISTER_TYPE_D
?
1760 BRW_AOP_IMIN
: BRW_AOP_UMIN
);
1761 case nir_intrinsic_image_var_atomic_max
:
1762 return (get_image_base_type(type
) == BRW_REGISTER_TYPE_D
?
1763 BRW_AOP_IMAX
: BRW_AOP_UMAX
);
1764 case nir_intrinsic_image_var_atomic_and
:
1766 case nir_intrinsic_image_var_atomic_or
:
1768 case nir_intrinsic_image_var_atomic_xor
:
1770 case nir_intrinsic_image_var_atomic_exchange
:
1772 case nir_intrinsic_image_var_atomic_comp_swap
:
1773 return BRW_AOP_CMPWR
;
1775 unreachable("Not reachable.");
1780 emit_pixel_interpolater_send(const fs_builder
&bld
,
1785 glsl_interp_mode interpolation
)
1787 struct brw_wm_prog_data
*wm_prog_data
=
1788 brw_wm_prog_data(bld
.shader
->stage_prog_data
);
1793 if (src
.file
== BAD_FILE
) {
1795 payload
= bld
.vgrf(BRW_REGISTER_TYPE_F
, 1);
1799 mlen
= 2 * bld
.dispatch_width() / 8;
1802 inst
= bld
.emit(opcode
, dst
, payload
, desc
);
1804 /* 2 floats per slot returned */
1805 inst
->size_written
= 2 * dst
.component_size(inst
->exec_size
);
1806 inst
->pi_noperspective
= interpolation
== INTERP_MODE_NOPERSPECTIVE
;
1808 wm_prog_data
->pulls_bary
= true;
1814 * Computes 1 << x, given a D/UD register containing some value x.
1817 intexp2(const fs_builder
&bld
, const fs_reg
&x
)
1819 assert(x
.type
== BRW_REGISTER_TYPE_UD
|| x
.type
== BRW_REGISTER_TYPE_D
);
1821 fs_reg result
= bld
.vgrf(x
.type
, 1);
1822 fs_reg one
= bld
.vgrf(x
.type
, 1);
1824 bld
.MOV(one
, retype(brw_imm_d(1), one
.type
));
1825 bld
.SHL(result
, one
, x
);
1830 fs_visitor::emit_gs_end_primitive(const nir_src
&vertex_count_nir_src
)
1832 assert(stage
== MESA_SHADER_GEOMETRY
);
1834 struct brw_gs_prog_data
*gs_prog_data
= brw_gs_prog_data(prog_data
);
1836 if (gs_compile
->control_data_header_size_bits
== 0)
1839 /* We can only do EndPrimitive() functionality when the control data
1840 * consists of cut bits. Fortunately, the only time it isn't is when the
1841 * output type is points, in which case EndPrimitive() is a no-op.
1843 if (gs_prog_data
->control_data_format
!=
1844 GEN7_GS_CONTROL_DATA_FORMAT_GSCTL_CUT
) {
1848 /* Cut bits use one bit per vertex. */
1849 assert(gs_compile
->control_data_bits_per_vertex
== 1);
1851 fs_reg vertex_count
= get_nir_src(vertex_count_nir_src
);
1852 vertex_count
.type
= BRW_REGISTER_TYPE_UD
;
1854 /* Cut bit n should be set to 1 if EndPrimitive() was called after emitting
1855 * vertex n, 0 otherwise. So all we need to do here is mark bit
1856 * (vertex_count - 1) % 32 in the cut_bits register to indicate that
1857 * EndPrimitive() was called after emitting vertex (vertex_count - 1);
1858 * vec4_gs_visitor::emit_control_data_bits() will take care of the rest.
1860 * Note that if EndPrimitive() is called before emitting any vertices, this
1861 * will cause us to set bit 31 of the control_data_bits register to 1.
1862 * That's fine because:
1864 * - If max_vertices < 32, then vertex number 31 (zero-based) will never be
1865 * output, so the hardware will ignore cut bit 31.
1867 * - If max_vertices == 32, then vertex number 31 is guaranteed to be the
1868 * last vertex, so setting cut bit 31 has no effect (since the primitive
1869 * is automatically ended when the GS terminates).
1871 * - If max_vertices > 32, then the ir_emit_vertex visitor will reset the
1872 * control_data_bits register to 0 when the first vertex is emitted.
1875 const fs_builder abld
= bld
.annotate("end primitive");
1877 /* control_data_bits |= 1 << ((vertex_count - 1) % 32) */
1878 fs_reg prev_count
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
1879 abld
.ADD(prev_count
, vertex_count
, brw_imm_ud(0xffffffffu
));
1880 fs_reg mask
= intexp2(abld
, prev_count
);
1881 /* Note: we're relying on the fact that the GEN SHL instruction only pays
1882 * attention to the lower 5 bits of its second source argument, so on this
1883 * architecture, 1 << (vertex_count - 1) is equivalent to 1 <<
1884 * ((vertex_count - 1) % 32).
1886 abld
.OR(this->control_data_bits
, this->control_data_bits
, mask
);
1890 fs_visitor::emit_gs_control_data_bits(const fs_reg
&vertex_count
)
1892 assert(stage
== MESA_SHADER_GEOMETRY
);
1893 assert(gs_compile
->control_data_bits_per_vertex
!= 0);
1895 struct brw_gs_prog_data
*gs_prog_data
= brw_gs_prog_data(prog_data
);
1897 const fs_builder abld
= bld
.annotate("emit control data bits");
1898 const fs_builder fwa_bld
= bld
.exec_all();
1900 /* We use a single UD register to accumulate control data bits (32 bits
1901 * for each of the SIMD8 channels). So we need to write a DWord (32 bits)
1904 * Unfortunately, the URB_WRITE_SIMD8 message uses 128-bit (OWord) offsets.
1905 * We have select a 128-bit group via the Global and Per-Slot Offsets, then
1906 * use the Channel Mask phase to enable/disable which DWord within that
1907 * group to write. (Remember, different SIMD8 channels may have emitted
1908 * different numbers of vertices, so we may need per-slot offsets.)
1910 * Channel masking presents an annoying problem: we may have to replicate
1911 * the data up to 4 times:
1913 * Msg = Handles, Per-Slot Offsets, Channel Masks, Data, Data, Data, Data.
1915 * To avoid penalizing shaders that emit a small number of vertices, we
1916 * can avoid these sometimes: if the size of the control data header is
1917 * <= 128 bits, then there is only 1 OWord. All SIMD8 channels will land
1918 * land in the same 128-bit group, so we can skip per-slot offsets.
1920 * Similarly, if the control data header is <= 32 bits, there is only one
1921 * DWord, so we can skip channel masks.
1923 enum opcode opcode
= SHADER_OPCODE_URB_WRITE_SIMD8
;
1925 fs_reg channel_mask
, per_slot_offset
;
1927 if (gs_compile
->control_data_header_size_bits
> 32) {
1928 opcode
= SHADER_OPCODE_URB_WRITE_SIMD8_MASKED
;
1929 channel_mask
= vgrf(glsl_type::uint_type
);
1932 if (gs_compile
->control_data_header_size_bits
> 128) {
1933 opcode
= SHADER_OPCODE_URB_WRITE_SIMD8_MASKED_PER_SLOT
;
1934 per_slot_offset
= vgrf(glsl_type::uint_type
);
1937 /* Figure out which DWord we're trying to write to using the formula:
1939 * dword_index = (vertex_count - 1) * bits_per_vertex / 32
1941 * Since bits_per_vertex is a power of two, and is known at compile
1942 * time, this can be optimized to:
1944 * dword_index = (vertex_count - 1) >> (6 - log2(bits_per_vertex))
1946 if (opcode
!= SHADER_OPCODE_URB_WRITE_SIMD8
) {
1947 fs_reg dword_index
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
1948 fs_reg prev_count
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
1949 abld
.ADD(prev_count
, vertex_count
, brw_imm_ud(0xffffffffu
));
1950 unsigned log2_bits_per_vertex
=
1951 util_last_bit(gs_compile
->control_data_bits_per_vertex
);
1952 abld
.SHR(dword_index
, prev_count
, brw_imm_ud(6u - log2_bits_per_vertex
));
1954 if (per_slot_offset
.file
!= BAD_FILE
) {
1955 /* Set the per-slot offset to dword_index / 4, so that we'll write to
1956 * the appropriate OWord within the control data header.
1958 abld
.SHR(per_slot_offset
, dword_index
, brw_imm_ud(2u));
1961 /* Set the channel masks to 1 << (dword_index % 4), so that we'll
1962 * write to the appropriate DWORD within the OWORD.
1964 fs_reg channel
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
1965 fwa_bld
.AND(channel
, dword_index
, brw_imm_ud(3u));
1966 channel_mask
= intexp2(fwa_bld
, channel
);
1967 /* Then the channel masks need to be in bits 23:16. */
1968 fwa_bld
.SHL(channel_mask
, channel_mask
, brw_imm_ud(16u));
1971 /* Store the control data bits in the message payload and send it. */
1973 if (channel_mask
.file
!= BAD_FILE
)
1974 mlen
+= 4; /* channel masks, plus 3 extra copies of the data */
1975 if (per_slot_offset
.file
!= BAD_FILE
)
1978 fs_reg payload
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, mlen
);
1979 fs_reg
*sources
= ralloc_array(mem_ctx
, fs_reg
, mlen
);
1981 sources
[i
++] = fs_reg(retype(brw_vec8_grf(1, 0), BRW_REGISTER_TYPE_UD
));
1982 if (per_slot_offset
.file
!= BAD_FILE
)
1983 sources
[i
++] = per_slot_offset
;
1984 if (channel_mask
.file
!= BAD_FILE
)
1985 sources
[i
++] = channel_mask
;
1987 sources
[i
++] = this->control_data_bits
;
1990 abld
.LOAD_PAYLOAD(payload
, sources
, mlen
, mlen
);
1991 fs_inst
*inst
= abld
.emit(opcode
, reg_undef
, payload
);
1993 /* We need to increment Global Offset by 256-bits to make room for
1994 * Broadwell's extra "Vertex Count" payload at the beginning of the
1995 * URB entry. Since this is an OWord message, Global Offset is counted
1996 * in 128-bit units, so we must set it to 2.
1998 if (gs_prog_data
->static_vertex_count
== -1)
2003 fs_visitor::set_gs_stream_control_data_bits(const fs_reg
&vertex_count
,
2006 /* control_data_bits |= stream_id << ((2 * (vertex_count - 1)) % 32) */
2008 /* Note: we are calling this *before* increasing vertex_count, so
2009 * this->vertex_count == vertex_count - 1 in the formula above.
2012 /* Stream mode uses 2 bits per vertex */
2013 assert(gs_compile
->control_data_bits_per_vertex
== 2);
2015 /* Must be a valid stream */
2016 assert(stream_id
< MAX_VERTEX_STREAMS
);
2018 /* Control data bits are initialized to 0 so we don't have to set any
2019 * bits when sending vertices to stream 0.
2024 const fs_builder abld
= bld
.annotate("set stream control data bits", NULL
);
2026 /* reg::sid = stream_id */
2027 fs_reg sid
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2028 abld
.MOV(sid
, brw_imm_ud(stream_id
));
2030 /* reg:shift_count = 2 * (vertex_count - 1) */
2031 fs_reg shift_count
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2032 abld
.SHL(shift_count
, vertex_count
, brw_imm_ud(1u));
2034 /* Note: we're relying on the fact that the GEN SHL instruction only pays
2035 * attention to the lower 5 bits of its second source argument, so on this
2036 * architecture, stream_id << 2 * (vertex_count - 1) is equivalent to
2037 * stream_id << ((2 * (vertex_count - 1)) % 32).
2039 fs_reg mask
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2040 abld
.SHL(mask
, sid
, shift_count
);
2041 abld
.OR(this->control_data_bits
, this->control_data_bits
, mask
);
2045 fs_visitor::emit_gs_vertex(const nir_src
&vertex_count_nir_src
,
2048 assert(stage
== MESA_SHADER_GEOMETRY
);
2050 struct brw_gs_prog_data
*gs_prog_data
= brw_gs_prog_data(prog_data
);
2052 fs_reg vertex_count
= get_nir_src(vertex_count_nir_src
);
2053 vertex_count
.type
= BRW_REGISTER_TYPE_UD
;
2055 /* Haswell and later hardware ignores the "Render Stream Select" bits
2056 * from the 3DSTATE_STREAMOUT packet when the SOL stage is disabled,
2057 * and instead sends all primitives down the pipeline for rasterization.
2058 * If the SOL stage is enabled, "Render Stream Select" is honored and
2059 * primitives bound to non-zero streams are discarded after stream output.
2061 * Since the only purpose of primives sent to non-zero streams is to
2062 * be recorded by transform feedback, we can simply discard all geometry
2063 * bound to these streams when transform feedback is disabled.
2065 if (stream_id
> 0 && !nir
->info
.has_transform_feedback_varyings
)
2068 /* If we're outputting 32 control data bits or less, then we can wait
2069 * until the shader is over to output them all. Otherwise we need to
2070 * output them as we go. Now is the time to do it, since we're about to
2071 * output the vertex_count'th vertex, so it's guaranteed that the
2072 * control data bits associated with the (vertex_count - 1)th vertex are
2075 if (gs_compile
->control_data_header_size_bits
> 32) {
2076 const fs_builder abld
=
2077 bld
.annotate("emit vertex: emit control data bits");
2079 /* Only emit control data bits if we've finished accumulating a batch
2080 * of 32 bits. This is the case when:
2082 * (vertex_count * bits_per_vertex) % 32 == 0
2084 * (in other words, when the last 5 bits of vertex_count *
2085 * bits_per_vertex are 0). Assuming bits_per_vertex == 2^n for some
2086 * integer n (which is always the case, since bits_per_vertex is
2087 * always 1 or 2), this is equivalent to requiring that the last 5-n
2088 * bits of vertex_count are 0:
2090 * vertex_count & (2^(5-n) - 1) == 0
2092 * 2^(5-n) == 2^5 / 2^n == 32 / bits_per_vertex, so this is
2095 * vertex_count & (32 / bits_per_vertex - 1) == 0
2097 * TODO: If vertex_count is an immediate, we could do some of this math
2098 * at compile time...
2101 abld
.AND(bld
.null_reg_d(), vertex_count
,
2102 brw_imm_ud(32u / gs_compile
->control_data_bits_per_vertex
- 1u));
2103 inst
->conditional_mod
= BRW_CONDITIONAL_Z
;
2105 abld
.IF(BRW_PREDICATE_NORMAL
);
2106 /* If vertex_count is 0, then no control data bits have been
2107 * accumulated yet, so we can skip emitting them.
2109 abld
.CMP(bld
.null_reg_d(), vertex_count
, brw_imm_ud(0u),
2110 BRW_CONDITIONAL_NEQ
);
2111 abld
.IF(BRW_PREDICATE_NORMAL
);
2112 emit_gs_control_data_bits(vertex_count
);
2113 abld
.emit(BRW_OPCODE_ENDIF
);
2115 /* Reset control_data_bits to 0 so we can start accumulating a new
2118 * Note: in the case where vertex_count == 0, this neutralizes the
2119 * effect of any call to EndPrimitive() that the shader may have
2120 * made before outputting its first vertex.
2122 inst
= abld
.MOV(this->control_data_bits
, brw_imm_ud(0u));
2123 inst
->force_writemask_all
= true;
2124 abld
.emit(BRW_OPCODE_ENDIF
);
2127 emit_urb_writes(vertex_count
);
2129 /* In stream mode we have to set control data bits for all vertices
2130 * unless we have disabled control data bits completely (which we do
2131 * do for GL_POINTS outputs that don't use streams).
2133 if (gs_compile
->control_data_header_size_bits
> 0 &&
2134 gs_prog_data
->control_data_format
==
2135 GEN7_GS_CONTROL_DATA_FORMAT_GSCTL_SID
) {
2136 set_gs_stream_control_data_bits(vertex_count
, stream_id
);
2141 fs_visitor::emit_gs_input_load(const fs_reg
&dst
,
2142 const nir_src
&vertex_src
,
2143 unsigned base_offset
,
2144 const nir_src
&offset_src
,
2145 unsigned num_components
,
2146 unsigned first_component
)
2148 struct brw_gs_prog_data
*gs_prog_data
= brw_gs_prog_data(prog_data
);
2150 nir_const_value
*vertex_const
= nir_src_as_const_value(vertex_src
);
2151 nir_const_value
*offset_const
= nir_src_as_const_value(offset_src
);
2152 const unsigned push_reg_count
= gs_prog_data
->base
.urb_read_length
* 8;
2154 /* TODO: figure out push input layout for invocations == 1 */
2155 /* TODO: make this work with 64-bit inputs */
2156 if (gs_prog_data
->invocations
== 1 &&
2157 type_sz(dst
.type
) <= 4 &&
2158 offset_const
!= NULL
&& vertex_const
!= NULL
&&
2159 4 * (base_offset
+ offset_const
->u32
[0]) < push_reg_count
) {
2160 int imm_offset
= (base_offset
+ offset_const
->u32
[0]) * 4 +
2161 vertex_const
->u32
[0] * push_reg_count
;
2162 for (unsigned i
= 0; i
< num_components
; i
++) {
2163 bld
.MOV(offset(dst
, bld
, i
),
2164 fs_reg(ATTR
, imm_offset
+ i
+ first_component
, dst
.type
));
2169 /* Resort to the pull model. Ensure the VUE handles are provided. */
2170 assert(gs_prog_data
->base
.include_vue_handles
);
2172 unsigned first_icp_handle
= gs_prog_data
->include_primitive_id
? 3 : 2;
2173 fs_reg icp_handle
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2175 if (gs_prog_data
->invocations
== 1) {
2177 /* The vertex index is constant; just select the proper URB handle. */
2179 retype(brw_vec8_grf(first_icp_handle
+ vertex_const
->i32
[0], 0),
2180 BRW_REGISTER_TYPE_UD
);
2182 /* The vertex index is non-constant. We need to use indirect
2183 * addressing to fetch the proper URB handle.
2185 * First, we start with the sequence <7, 6, 5, 4, 3, 2, 1, 0>
2186 * indicating that channel <n> should read the handle from
2187 * DWord <n>. We convert that to bytes by multiplying by 4.
2189 * Next, we convert the vertex index to bytes by multiplying
2190 * by 32 (shifting by 5), and add the two together. This is
2191 * the final indirect byte offset.
2193 fs_reg sequence
= bld
.vgrf(BRW_REGISTER_TYPE_UW
, 1);
2194 fs_reg channel_offsets
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2195 fs_reg vertex_offset_bytes
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2196 fs_reg icp_offset_bytes
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2198 /* sequence = <7, 6, 5, 4, 3, 2, 1, 0> */
2199 bld
.MOV(sequence
, fs_reg(brw_imm_v(0x76543210)));
2200 /* channel_offsets = 4 * sequence = <28, 24, 20, 16, 12, 8, 4, 0> */
2201 bld
.SHL(channel_offsets
, sequence
, brw_imm_ud(2u));
2202 /* Convert vertex_index to bytes (multiply by 32) */
2203 bld
.SHL(vertex_offset_bytes
,
2204 retype(get_nir_src(vertex_src
), BRW_REGISTER_TYPE_UD
),
2206 bld
.ADD(icp_offset_bytes
, vertex_offset_bytes
, channel_offsets
);
2208 /* Use first_icp_handle as the base offset. There is one register
2209 * of URB handles per vertex, so inform the register allocator that
2210 * we might read up to nir->info.gs.vertices_in registers.
2212 bld
.emit(SHADER_OPCODE_MOV_INDIRECT
, icp_handle
,
2213 retype(brw_vec8_grf(first_icp_handle
, 0), icp_handle
.type
),
2214 fs_reg(icp_offset_bytes
),
2215 brw_imm_ud(nir
->info
.gs
.vertices_in
* REG_SIZE
));
2218 assert(gs_prog_data
->invocations
> 1);
2221 assert(devinfo
->gen
>= 9 || vertex_const
->i32
[0] <= 5);
2223 retype(brw_vec1_grf(first_icp_handle
+
2224 vertex_const
->i32
[0] / 8,
2225 vertex_const
->i32
[0] % 8),
2226 BRW_REGISTER_TYPE_UD
));
2228 /* The vertex index is non-constant. We need to use indirect
2229 * addressing to fetch the proper URB handle.
2232 fs_reg icp_offset_bytes
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2234 /* Convert vertex_index to bytes (multiply by 4) */
2235 bld
.SHL(icp_offset_bytes
,
2236 retype(get_nir_src(vertex_src
), BRW_REGISTER_TYPE_UD
),
2239 /* Use first_icp_handle as the base offset. There is one DWord
2240 * of URB handles per vertex, so inform the register allocator that
2241 * we might read up to ceil(nir->info.gs.vertices_in / 8) registers.
2243 bld
.emit(SHADER_OPCODE_MOV_INDIRECT
, icp_handle
,
2244 retype(brw_vec8_grf(first_icp_handle
, 0), icp_handle
.type
),
2245 fs_reg(icp_offset_bytes
),
2246 brw_imm_ud(DIV_ROUND_UP(nir
->info
.gs
.vertices_in
, 8) *
2253 fs_reg tmp_dst
= dst
;
2254 fs_reg indirect_offset
= get_nir_src(offset_src
);
2255 unsigned num_iterations
= 1;
2256 unsigned orig_num_components
= num_components
;
2258 if (type_sz(dst
.type
) == 8) {
2259 if (num_components
> 2) {
2263 fs_reg tmp
= fs_reg(VGRF
, alloc
.allocate(4), dst
.type
);
2265 first_component
= first_component
/ 2;
2268 for (unsigned iter
= 0; iter
< num_iterations
; iter
++) {
2270 /* Constant indexing - use global offset. */
2271 if (first_component
!= 0) {
2272 unsigned read_components
= num_components
+ first_component
;
2273 fs_reg tmp
= bld
.vgrf(dst
.type
, read_components
);
2274 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8
, tmp
, icp_handle
);
2275 inst
->size_written
= read_components
*
2276 tmp
.component_size(inst
->exec_size
);
2277 for (unsigned i
= 0; i
< num_components
; i
++) {
2278 bld
.MOV(offset(tmp_dst
, bld
, i
),
2279 offset(tmp
, bld
, i
+ first_component
));
2282 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8
, tmp_dst
,
2284 inst
->size_written
= num_components
*
2285 tmp_dst
.component_size(inst
->exec_size
);
2287 inst
->offset
= base_offset
+ offset_const
->u32
[0];
2290 /* Indirect indexing - use per-slot offsets as well. */
2291 const fs_reg srcs
[] = { icp_handle
, indirect_offset
};
2292 unsigned read_components
= num_components
+ first_component
;
2293 fs_reg tmp
= bld
.vgrf(dst
.type
, read_components
);
2294 fs_reg payload
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 2);
2295 bld
.LOAD_PAYLOAD(payload
, srcs
, ARRAY_SIZE(srcs
), 0);
2296 if (first_component
!= 0) {
2297 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT
, tmp
,
2299 inst
->size_written
= read_components
*
2300 tmp
.component_size(inst
->exec_size
);
2301 for (unsigned i
= 0; i
< num_components
; i
++) {
2302 bld
.MOV(offset(tmp_dst
, bld
, i
),
2303 offset(tmp
, bld
, i
+ first_component
));
2306 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT
, tmp_dst
,
2308 inst
->size_written
= num_components
*
2309 tmp_dst
.component_size(inst
->exec_size
);
2311 inst
->offset
= base_offset
;
2315 if (type_sz(dst
.type
) == 8) {
2316 shuffle_32bit_load_result_to_64bit_data(
2317 bld
, tmp_dst
, retype(tmp_dst
, BRW_REGISTER_TYPE_F
), num_components
);
2319 for (unsigned c
= 0; c
< num_components
; c
++)
2320 bld
.MOV(offset(dst
, bld
, iter
* 2 + c
), offset(tmp_dst
, bld
, c
));
2323 if (num_iterations
> 1) {
2324 num_components
= orig_num_components
- 2;
2328 fs_reg new_indirect
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2329 bld
.ADD(new_indirect
, indirect_offset
, brw_imm_ud(1u));
2330 indirect_offset
= new_indirect
;
2337 fs_visitor::get_indirect_offset(nir_intrinsic_instr
*instr
)
2339 nir_src
*offset_src
= nir_get_io_offset_src(instr
);
2340 nir_const_value
*const_value
= nir_src_as_const_value(*offset_src
);
2343 /* The only constant offset we should find is 0. brw_nir.c's
2344 * add_const_offset_to_base() will fold other constant offsets
2345 * into instr->const_index[0].
2347 assert(const_value
->u32
[0] == 0);
2351 return get_nir_src(*offset_src
);
2355 do_untyped_vector_read(const fs_builder
&bld
,
2357 const fs_reg surf_index
,
2358 const fs_reg offset_reg
,
2359 unsigned num_components
)
2361 if (type_sz(dest
.type
) <= 2) {
2362 assert(dest
.stride
== 1);
2363 boolean is_const_offset
= offset_reg
.file
== BRW_IMMEDIATE_VALUE
;
2365 if (is_const_offset
) {
2366 uint32_t start
= offset_reg
.ud
& ~3;
2367 uint32_t end
= offset_reg
.ud
+ num_components
* type_sz(dest
.type
);
2368 end
= ALIGN(end
, 4);
2369 assert (end
- start
<= 16);
2371 /* At this point we have 16-bit component/s that have constant
2372 * offset aligned to 4-bytes that can be read with untyped_reads.
2373 * untyped_read message requires 32-bit aligned offsets.
2375 unsigned first_component
= (offset_reg
.ud
& 3) / type_sz(dest
.type
);
2376 unsigned num_components_32bit
= (end
- start
) / 4;
2378 fs_reg read_result
=
2379 emit_untyped_read(bld
, surf_index
, brw_imm_ud(start
),
2381 num_components_32bit
,
2382 BRW_PREDICATE_NONE
);
2383 shuffle_32bit_load_result_to_16bit_data(bld
,
2384 retype(dest
, BRW_REGISTER_TYPE_W
),
2385 retype(read_result
, BRW_REGISTER_TYPE_D
),
2386 first_component
, num_components
);
2388 fs_reg read_offset
= bld
.vgrf(BRW_REGISTER_TYPE_UD
);
2389 for (unsigned i
= 0; i
< num_components
; i
++) {
2391 bld
.MOV(read_offset
, offset_reg
);
2393 bld
.ADD(read_offset
, offset_reg
,
2394 brw_imm_ud(i
* type_sz(dest
.type
)));
2396 /* Non constant offsets are not guaranteed to be aligned 32-bits
2397 * so they are read using one byte_scattered_read message
2398 * for each component.
2400 fs_reg read_result
=
2401 emit_byte_scattered_read(bld
, surf_index
, read_offset
,
2403 type_sz(dest
.type
) * 8 /* bit_size */,
2404 BRW_PREDICATE_NONE
);
2405 bld
.MOV(offset(dest
, bld
, i
),
2406 subscript (read_result
, dest
.type
, 0));
2409 } else if (type_sz(dest
.type
) == 4) {
2410 fs_reg read_result
= emit_untyped_read(bld
, surf_index
, offset_reg
,
2413 BRW_PREDICATE_NONE
);
2414 read_result
.type
= dest
.type
;
2415 for (unsigned i
= 0; i
< num_components
; i
++)
2416 bld
.MOV(offset(dest
, bld
, i
), offset(read_result
, bld
, i
));
2417 } else if (type_sz(dest
.type
) == 8) {
2418 /* Reading a dvec, so we need to:
2420 * 1. Multiply num_components by 2, to account for the fact that we
2421 * need to read 64-bit components.
2422 * 2. Shuffle the result of the load to form valid 64-bit elements
2423 * 3. Emit a second load (for components z/w) if needed.
2425 fs_reg read_offset
= bld
.vgrf(BRW_REGISTER_TYPE_UD
);
2426 bld
.MOV(read_offset
, offset_reg
);
2428 int iters
= num_components
<= 2 ? 1 : 2;
2430 /* Load the dvec, the first iteration loads components x/y, the second
2431 * iteration, if needed, loads components z/w
2433 for (int it
= 0; it
< iters
; it
++) {
2434 /* Compute number of components to read in this iteration */
2435 int iter_components
= MIN2(2, num_components
);
2436 num_components
-= iter_components
;
2438 /* Read. Since this message reads 32-bit components, we need to
2439 * read twice as many components.
2441 fs_reg read_result
= emit_untyped_read(bld
, surf_index
, read_offset
,
2443 iter_components
* 2,
2444 BRW_PREDICATE_NONE
);
2446 /* Shuffle the 32-bit load result into valid 64-bit data */
2447 const fs_reg packed_result
= bld
.vgrf(dest
.type
, iter_components
);
2448 shuffle_32bit_load_result_to_64bit_data(
2449 bld
, packed_result
, read_result
, iter_components
);
2451 /* Move each component to its destination */
2452 read_result
= retype(read_result
, BRW_REGISTER_TYPE_DF
);
2453 for (int c
= 0; c
< iter_components
; c
++) {
2454 bld
.MOV(offset(dest
, bld
, it
* 2 + c
),
2455 offset(packed_result
, bld
, c
));
2458 bld
.ADD(read_offset
, read_offset
, brw_imm_ud(16));
2461 unreachable("Unsupported type");
2466 fs_visitor::nir_emit_vs_intrinsic(const fs_builder
&bld
,
2467 nir_intrinsic_instr
*instr
)
2469 assert(stage
== MESA_SHADER_VERTEX
);
2472 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
2473 dest
= get_nir_dest(instr
->dest
);
2475 switch (instr
->intrinsic
) {
2476 case nir_intrinsic_load_vertex_id
:
2477 case nir_intrinsic_load_base_vertex
:
2478 unreachable("should be lowered by nir_lower_system_values()");
2480 case nir_intrinsic_load_vertex_id_zero_base
:
2481 case nir_intrinsic_load_instance_id
:
2482 case nir_intrinsic_load_base_instance
:
2483 case nir_intrinsic_load_draw_id
: {
2484 gl_system_value sv
= nir_system_value_from_intrinsic(instr
->intrinsic
);
2485 fs_reg val
= nir_system_values
[sv
];
2486 assert(val
.file
!= BAD_FILE
);
2487 dest
.type
= val
.type
;
2492 case nir_intrinsic_load_input
: {
2493 fs_reg src
= fs_reg(ATTR
, nir_intrinsic_base(instr
) * 4, dest
.type
);
2494 unsigned first_component
= nir_intrinsic_component(instr
);
2495 unsigned num_components
= instr
->num_components
;
2497 nir_const_value
*const_offset
= nir_src_as_const_value(instr
->src
[0]);
2498 assert(const_offset
&& "Indirect input loads not allowed");
2499 src
= offset(src
, bld
, const_offset
->u32
[0]);
2501 if (type_sz(dest
.type
) == 8)
2502 first_component
/= 2;
2504 for (unsigned j
= 0; j
< num_components
; j
++) {
2505 bld
.MOV(offset(dest
, bld
, j
), offset(src
, bld
, j
+ first_component
));
2508 if (type_sz(dest
.type
) == 8) {
2509 shuffle_32bit_load_result_to_64bit_data(bld
,
2511 retype(dest
, BRW_REGISTER_TYPE_F
),
2512 instr
->num_components
);
2517 case nir_intrinsic_load_first_vertex
:
2518 case nir_intrinsic_load_is_indexed_draw
:
2519 unreachable("lowered by brw_nir_lower_vs_inputs");
2522 nir_emit_intrinsic(bld
, instr
);
2528 fs_visitor::nir_emit_tcs_intrinsic(const fs_builder
&bld
,
2529 nir_intrinsic_instr
*instr
)
2531 assert(stage
== MESA_SHADER_TESS_CTRL
);
2532 struct brw_tcs_prog_key
*tcs_key
= (struct brw_tcs_prog_key
*) key
;
2533 struct brw_tcs_prog_data
*tcs_prog_data
= brw_tcs_prog_data(prog_data
);
2536 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
2537 dst
= get_nir_dest(instr
->dest
);
2539 switch (instr
->intrinsic
) {
2540 case nir_intrinsic_load_primitive_id
:
2541 bld
.MOV(dst
, fs_reg(brw_vec1_grf(0, 1)));
2543 case nir_intrinsic_load_invocation_id
:
2544 bld
.MOV(retype(dst
, invocation_id
.type
), invocation_id
);
2546 case nir_intrinsic_load_patch_vertices_in
:
2547 bld
.MOV(retype(dst
, BRW_REGISTER_TYPE_D
),
2548 brw_imm_d(tcs_key
->input_vertices
));
2551 case nir_intrinsic_barrier
: {
2552 if (tcs_prog_data
->instances
== 1)
2555 fs_reg m0
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2556 fs_reg m0_2
= component(m0
, 2);
2558 const fs_builder chanbld
= bld
.exec_all().group(1, 0);
2560 /* Zero the message header */
2561 bld
.exec_all().MOV(m0
, brw_imm_ud(0u));
2563 /* Copy "Barrier ID" from r0.2, bits 16:13 */
2564 chanbld
.AND(m0_2
, retype(brw_vec1_grf(0, 2), BRW_REGISTER_TYPE_UD
),
2565 brw_imm_ud(INTEL_MASK(16, 13)));
2567 /* Shift it up to bits 27:24. */
2568 chanbld
.SHL(m0_2
, m0_2
, brw_imm_ud(11));
2570 /* Set the Barrier Count and the enable bit */
2571 chanbld
.OR(m0_2
, m0_2
,
2572 brw_imm_ud(tcs_prog_data
->instances
<< 9 | (1 << 15)));
2574 bld
.emit(SHADER_OPCODE_BARRIER
, bld
.null_reg_ud(), m0
);
2578 case nir_intrinsic_load_input
:
2579 unreachable("nir_lower_io should never give us these.");
2582 case nir_intrinsic_load_per_vertex_input
: {
2583 fs_reg indirect_offset
= get_indirect_offset(instr
);
2584 unsigned imm_offset
= instr
->const_index
[0];
2586 const nir_src
&vertex_src
= instr
->src
[0];
2587 nir_const_value
*vertex_const
= nir_src_as_const_value(vertex_src
);
2594 /* Emit a MOV to resolve <0,1,0> regioning. */
2595 icp_handle
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2597 retype(brw_vec1_grf(1 + (vertex_const
->i32
[0] >> 3),
2598 vertex_const
->i32
[0] & 7),
2599 BRW_REGISTER_TYPE_UD
));
2600 } else if (tcs_prog_data
->instances
== 1 &&
2601 vertex_src
.is_ssa
&&
2602 vertex_src
.ssa
->parent_instr
->type
== nir_instr_type_intrinsic
&&
2603 nir_instr_as_intrinsic(vertex_src
.ssa
->parent_instr
)->intrinsic
== nir_intrinsic_load_invocation_id
) {
2604 /* For the common case of only 1 instance, an array index of
2605 * gl_InvocationID means reading g1. Skip all the indirect work.
2607 icp_handle
= retype(brw_vec8_grf(1, 0), BRW_REGISTER_TYPE_UD
);
2609 /* The vertex index is non-constant. We need to use indirect
2610 * addressing to fetch the proper URB handle.
2612 icp_handle
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2614 /* Each ICP handle is a single DWord (4 bytes) */
2615 fs_reg vertex_offset_bytes
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2616 bld
.SHL(vertex_offset_bytes
,
2617 retype(get_nir_src(vertex_src
), BRW_REGISTER_TYPE_UD
),
2620 /* Start at g1. We might read up to 4 registers. */
2621 bld
.emit(SHADER_OPCODE_MOV_INDIRECT
, icp_handle
,
2622 retype(brw_vec8_grf(1, 0), icp_handle
.type
), vertex_offset_bytes
,
2623 brw_imm_ud(4 * REG_SIZE
));
2626 /* We can only read two double components with each URB read, so
2627 * we send two read messages in that case, each one loading up to
2628 * two double components.
2630 unsigned num_iterations
= 1;
2631 unsigned num_components
= instr
->num_components
;
2632 unsigned first_component
= nir_intrinsic_component(instr
);
2633 fs_reg orig_dst
= dst
;
2634 if (type_sz(dst
.type
) == 8) {
2635 first_component
= first_component
/ 2;
2636 if (instr
->num_components
> 2) {
2641 fs_reg tmp
= fs_reg(VGRF
, alloc
.allocate(4), dst
.type
);
2645 for (unsigned iter
= 0; iter
< num_iterations
; iter
++) {
2646 if (indirect_offset
.file
== BAD_FILE
) {
2647 /* Constant indexing - use global offset. */
2648 if (first_component
!= 0) {
2649 unsigned read_components
= num_components
+ first_component
;
2650 fs_reg tmp
= bld
.vgrf(dst
.type
, read_components
);
2651 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8
, tmp
, icp_handle
);
2652 for (unsigned i
= 0; i
< num_components
; i
++) {
2653 bld
.MOV(offset(dst
, bld
, i
),
2654 offset(tmp
, bld
, i
+ first_component
));
2657 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8
, dst
, icp_handle
);
2659 inst
->offset
= imm_offset
;
2662 /* Indirect indexing - use per-slot offsets as well. */
2663 const fs_reg srcs
[] = { icp_handle
, indirect_offset
};
2664 fs_reg payload
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 2);
2665 bld
.LOAD_PAYLOAD(payload
, srcs
, ARRAY_SIZE(srcs
), 0);
2666 if (first_component
!= 0) {
2667 unsigned read_components
= num_components
+ first_component
;
2668 fs_reg tmp
= bld
.vgrf(dst
.type
, read_components
);
2669 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT
, tmp
,
2671 for (unsigned i
= 0; i
< num_components
; i
++) {
2672 bld
.MOV(offset(dst
, bld
, i
),
2673 offset(tmp
, bld
, i
+ first_component
));
2676 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT
, dst
,
2679 inst
->offset
= imm_offset
;
2682 inst
->size_written
= (num_components
+ first_component
) *
2683 inst
->dst
.component_size(inst
->exec_size
);
2685 /* If we are reading 64-bit data using 32-bit read messages we need
2686 * build proper 64-bit data elements by shuffling the low and high
2687 * 32-bit components around like we do for other things like UBOs
2690 if (type_sz(dst
.type
) == 8) {
2691 shuffle_32bit_load_result_to_64bit_data(
2692 bld
, dst
, retype(dst
, BRW_REGISTER_TYPE_F
), num_components
);
2694 for (unsigned c
= 0; c
< num_components
; c
++) {
2695 bld
.MOV(offset(orig_dst
, bld
, iter
* 2 + c
),
2696 offset(dst
, bld
, c
));
2700 /* Copy the temporary to the destination to deal with writemasking.
2702 * Also attempt to deal with gl_PointSize being in the .w component.
2704 if (inst
->offset
== 0 && indirect_offset
.file
== BAD_FILE
) {
2705 assert(type_sz(dst
.type
) < 8);
2706 inst
->dst
= bld
.vgrf(dst
.type
, 4);
2707 inst
->size_written
= 4 * REG_SIZE
;
2708 bld
.MOV(dst
, offset(inst
->dst
, bld
, 3));
2711 /* If we are loading double data and we need a second read message
2712 * adjust the write offset
2714 if (num_iterations
> 1) {
2715 num_components
= instr
->num_components
- 2;
2722 case nir_intrinsic_load_output
:
2723 case nir_intrinsic_load_per_vertex_output
: {
2724 fs_reg indirect_offset
= get_indirect_offset(instr
);
2725 unsigned imm_offset
= instr
->const_index
[0];
2726 unsigned first_component
= nir_intrinsic_component(instr
);
2729 if (indirect_offset
.file
== BAD_FILE
) {
2730 /* Replicate the patch handle to all enabled channels */
2731 fs_reg patch_handle
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2732 bld
.MOV(patch_handle
,
2733 retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_UD
));
2736 if (first_component
!= 0) {
2737 unsigned read_components
=
2738 instr
->num_components
+ first_component
;
2739 fs_reg tmp
= bld
.vgrf(dst
.type
, read_components
);
2740 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8
, tmp
,
2742 inst
->size_written
= read_components
* REG_SIZE
;
2743 for (unsigned i
= 0; i
< instr
->num_components
; i
++) {
2744 bld
.MOV(offset(dst
, bld
, i
),
2745 offset(tmp
, bld
, i
+ first_component
));
2748 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8
, dst
,
2750 inst
->size_written
= instr
->num_components
* REG_SIZE
;
2752 inst
->offset
= imm_offset
;
2756 /* Indirect indexing - use per-slot offsets as well. */
2757 const fs_reg srcs
[] = {
2758 retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_UD
),
2761 fs_reg payload
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 2);
2762 bld
.LOAD_PAYLOAD(payload
, srcs
, ARRAY_SIZE(srcs
), 0);
2763 if (first_component
!= 0) {
2764 unsigned read_components
=
2765 instr
->num_components
+ first_component
;
2766 fs_reg tmp
= bld
.vgrf(dst
.type
, read_components
);
2767 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT
, tmp
,
2769 inst
->size_written
= read_components
* REG_SIZE
;
2770 for (unsigned i
= 0; i
< instr
->num_components
; i
++) {
2771 bld
.MOV(offset(dst
, bld
, i
),
2772 offset(tmp
, bld
, i
+ first_component
));
2775 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT
, dst
,
2777 inst
->size_written
= instr
->num_components
* REG_SIZE
;
2779 inst
->offset
= imm_offset
;
2785 case nir_intrinsic_store_output
:
2786 case nir_intrinsic_store_per_vertex_output
: {
2787 fs_reg value
= get_nir_src(instr
->src
[0]);
2788 bool is_64bit
= (instr
->src
[0].is_ssa
?
2789 instr
->src
[0].ssa
->bit_size
: instr
->src
[0].reg
.reg
->bit_size
) == 64;
2790 fs_reg indirect_offset
= get_indirect_offset(instr
);
2791 unsigned imm_offset
= instr
->const_index
[0];
2792 unsigned mask
= instr
->const_index
[1];
2793 unsigned header_regs
= 0;
2795 srcs
[header_regs
++] = retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_UD
);
2797 if (indirect_offset
.file
!= BAD_FILE
) {
2798 srcs
[header_regs
++] = indirect_offset
;
2804 unsigned num_components
= util_last_bit(mask
);
2807 /* We can only pack two 64-bit components in a single message, so send
2808 * 2 messages if we have more components
2810 unsigned num_iterations
= 1;
2811 unsigned iter_components
= num_components
;
2812 unsigned first_component
= nir_intrinsic_component(instr
);
2814 first_component
= first_component
/ 2;
2815 if (instr
->num_components
> 2) {
2817 iter_components
= 2;
2821 mask
= mask
<< first_component
;
2823 for (unsigned iter
= 0; iter
< num_iterations
; iter
++) {
2824 if (!is_64bit
&& mask
!= WRITEMASK_XYZW
) {
2825 srcs
[header_regs
++] = brw_imm_ud(mask
<< 16);
2826 opcode
= indirect_offset
.file
!= BAD_FILE
?
2827 SHADER_OPCODE_URB_WRITE_SIMD8_MASKED_PER_SLOT
:
2828 SHADER_OPCODE_URB_WRITE_SIMD8_MASKED
;
2829 } else if (is_64bit
&& ((mask
& WRITEMASK_XY
) != WRITEMASK_XY
)) {
2830 /* Expand the 64-bit mask to 32-bit channels. We only handle
2831 * two channels in each iteration, so we only care about X/Y.
2833 unsigned mask32
= 0;
2834 if (mask
& WRITEMASK_X
)
2835 mask32
|= WRITEMASK_XY
;
2836 if (mask
& WRITEMASK_Y
)
2837 mask32
|= WRITEMASK_ZW
;
2839 /* If the mask does not include any of the channels X or Y there
2840 * is nothing to do in this iteration. Move on to the next couple
2841 * of 64-bit channels.
2849 srcs
[header_regs
++] = brw_imm_ud(mask32
<< 16);
2850 opcode
= indirect_offset
.file
!= BAD_FILE
?
2851 SHADER_OPCODE_URB_WRITE_SIMD8_MASKED_PER_SLOT
:
2852 SHADER_OPCODE_URB_WRITE_SIMD8_MASKED
;
2854 opcode
= indirect_offset
.file
!= BAD_FILE
?
2855 SHADER_OPCODE_URB_WRITE_SIMD8_PER_SLOT
:
2856 SHADER_OPCODE_URB_WRITE_SIMD8
;
2859 for (unsigned i
= 0; i
< iter_components
; i
++) {
2860 if (!(mask
& (1 << (i
+ first_component
))))
2864 srcs
[header_regs
+ i
+ first_component
] = offset(value
, bld
, i
);
2866 /* We need to shuffle the 64-bit data to match the layout
2867 * expected by our 32-bit URB write messages. We use a temporary
2870 unsigned channel
= iter
* 2 + i
;
2871 fs_reg dest
= shuffle_64bit_data_for_32bit_write(bld
,
2872 offset(value
, bld
, channel
), 1);
2874 srcs
[header_regs
+ (i
+ first_component
) * 2] = dest
;
2875 srcs
[header_regs
+ (i
+ first_component
) * 2 + 1] =
2876 offset(dest
, bld
, 1);
2881 header_regs
+ (is_64bit
? 2 * iter_components
: iter_components
) +
2882 (is_64bit
? 2 * first_component
: first_component
);
2884 bld
.vgrf(BRW_REGISTER_TYPE_UD
, mlen
);
2885 bld
.LOAD_PAYLOAD(payload
, srcs
, mlen
, header_regs
);
2887 fs_inst
*inst
= bld
.emit(opcode
, bld
.null_reg_ud(), payload
);
2888 inst
->offset
= imm_offset
;
2891 /* If this is a 64-bit attribute, select the next two 64-bit channels
2892 * to be handled in the next iteration.
2903 nir_emit_intrinsic(bld
, instr
);
2909 fs_visitor::nir_emit_tes_intrinsic(const fs_builder
&bld
,
2910 nir_intrinsic_instr
*instr
)
2912 assert(stage
== MESA_SHADER_TESS_EVAL
);
2913 struct brw_tes_prog_data
*tes_prog_data
= brw_tes_prog_data(prog_data
);
2916 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
2917 dest
= get_nir_dest(instr
->dest
);
2919 switch (instr
->intrinsic
) {
2920 case nir_intrinsic_load_primitive_id
:
2921 bld
.MOV(dest
, fs_reg(brw_vec1_grf(0, 1)));
2923 case nir_intrinsic_load_tess_coord
:
2924 /* gl_TessCoord is part of the payload in g1-3 */
2925 for (unsigned i
= 0; i
< 3; i
++) {
2926 bld
.MOV(offset(dest
, bld
, i
), fs_reg(brw_vec8_grf(1 + i
, 0)));
2930 case nir_intrinsic_load_input
:
2931 case nir_intrinsic_load_per_vertex_input
: {
2932 fs_reg indirect_offset
= get_indirect_offset(instr
);
2933 unsigned imm_offset
= instr
->const_index
[0];
2934 unsigned first_component
= nir_intrinsic_component(instr
);
2936 if (type_sz(dest
.type
) == 8) {
2937 first_component
= first_component
/ 2;
2941 if (indirect_offset
.file
== BAD_FILE
) {
2942 /* Arbitrarily only push up to 32 vec4 slots worth of data,
2943 * which is 16 registers (since each holds 2 vec4 slots).
2945 unsigned slot_count
= 1;
2946 if (type_sz(dest
.type
) == 8 && instr
->num_components
> 2)
2949 const unsigned max_push_slots
= 32;
2950 if (imm_offset
+ slot_count
<= max_push_slots
) {
2951 fs_reg src
= fs_reg(ATTR
, imm_offset
/ 2, dest
.type
);
2952 for (int i
= 0; i
< instr
->num_components
; i
++) {
2953 unsigned comp
= 16 / type_sz(dest
.type
) * (imm_offset
% 2) +
2954 i
+ first_component
;
2955 bld
.MOV(offset(dest
, bld
, i
), component(src
, comp
));
2958 tes_prog_data
->base
.urb_read_length
=
2959 MAX2(tes_prog_data
->base
.urb_read_length
,
2960 DIV_ROUND_UP(imm_offset
+ slot_count
, 2));
2962 /* Replicate the patch handle to all enabled channels */
2963 const fs_reg srcs
[] = {
2964 retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_UD
)
2966 fs_reg patch_handle
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2967 bld
.LOAD_PAYLOAD(patch_handle
, srcs
, ARRAY_SIZE(srcs
), 0);
2969 if (first_component
!= 0) {
2970 unsigned read_components
=
2971 instr
->num_components
+ first_component
;
2972 fs_reg tmp
= bld
.vgrf(dest
.type
, read_components
);
2973 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8
, tmp
,
2975 inst
->size_written
= read_components
* REG_SIZE
;
2976 for (unsigned i
= 0; i
< instr
->num_components
; i
++) {
2977 bld
.MOV(offset(dest
, bld
, i
),
2978 offset(tmp
, bld
, i
+ first_component
));
2981 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8
, dest
,
2983 inst
->size_written
= instr
->num_components
* REG_SIZE
;
2986 inst
->offset
= imm_offset
;
2989 /* Indirect indexing - use per-slot offsets as well. */
2991 /* We can only read two double components with each URB read, so
2992 * we send two read messages in that case, each one loading up to
2993 * two double components.
2995 unsigned num_iterations
= 1;
2996 unsigned num_components
= instr
->num_components
;
2997 fs_reg orig_dest
= dest
;
2998 if (type_sz(dest
.type
) == 8) {
2999 if (instr
->num_components
> 2) {
3003 fs_reg tmp
= fs_reg(VGRF
, alloc
.allocate(4), dest
.type
);
3007 for (unsigned iter
= 0; iter
< num_iterations
; iter
++) {
3008 const fs_reg srcs
[] = {
3009 retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_UD
),
3012 fs_reg payload
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 2);
3013 bld
.LOAD_PAYLOAD(payload
, srcs
, ARRAY_SIZE(srcs
), 0);
3015 if (first_component
!= 0) {
3016 unsigned read_components
=
3017 num_components
+ first_component
;
3018 fs_reg tmp
= bld
.vgrf(dest
.type
, read_components
);
3019 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT
, tmp
,
3021 for (unsigned i
= 0; i
< num_components
; i
++) {
3022 bld
.MOV(offset(dest
, bld
, i
),
3023 offset(tmp
, bld
, i
+ first_component
));
3026 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT
, dest
,
3030 inst
->offset
= imm_offset
;
3031 inst
->size_written
= (num_components
+ first_component
) *
3032 inst
->dst
.component_size(inst
->exec_size
);
3034 /* If we are reading 64-bit data using 32-bit read messages we need
3035 * build proper 64-bit data elements by shuffling the low and high
3036 * 32-bit components around like we do for other things like UBOs
3039 if (type_sz(dest
.type
) == 8) {
3040 shuffle_32bit_load_result_to_64bit_data(
3041 bld
, dest
, retype(dest
, BRW_REGISTER_TYPE_F
), num_components
);
3043 for (unsigned c
= 0; c
< num_components
; c
++) {
3044 bld
.MOV(offset(orig_dest
, bld
, iter
* 2 + c
),
3045 offset(dest
, bld
, c
));
3049 /* If we are loading double data and we need a second read message
3052 if (num_iterations
> 1) {
3053 num_components
= instr
->num_components
- 2;
3061 nir_emit_intrinsic(bld
, instr
);
3067 fs_visitor::nir_emit_gs_intrinsic(const fs_builder
&bld
,
3068 nir_intrinsic_instr
*instr
)
3070 assert(stage
== MESA_SHADER_GEOMETRY
);
3071 fs_reg indirect_offset
;
3074 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
3075 dest
= get_nir_dest(instr
->dest
);
3077 switch (instr
->intrinsic
) {
3078 case nir_intrinsic_load_primitive_id
:
3079 assert(stage
== MESA_SHADER_GEOMETRY
);
3080 assert(brw_gs_prog_data(prog_data
)->include_primitive_id
);
3081 bld
.MOV(retype(dest
, BRW_REGISTER_TYPE_UD
),
3082 retype(fs_reg(brw_vec8_grf(2, 0)), BRW_REGISTER_TYPE_UD
));
3085 case nir_intrinsic_load_input
:
3086 unreachable("load_input intrinsics are invalid for the GS stage");
3088 case nir_intrinsic_load_per_vertex_input
:
3089 emit_gs_input_load(dest
, instr
->src
[0], instr
->const_index
[0],
3090 instr
->src
[1], instr
->num_components
,
3091 nir_intrinsic_component(instr
));
3094 case nir_intrinsic_emit_vertex_with_counter
:
3095 emit_gs_vertex(instr
->src
[0], instr
->const_index
[0]);
3098 case nir_intrinsic_end_primitive_with_counter
:
3099 emit_gs_end_primitive(instr
->src
[0]);
3102 case nir_intrinsic_set_vertex_count
:
3103 bld
.MOV(this->final_gs_vertex_count
, get_nir_src(instr
->src
[0]));
3106 case nir_intrinsic_load_invocation_id
: {
3107 fs_reg val
= nir_system_values
[SYSTEM_VALUE_INVOCATION_ID
];
3108 assert(val
.file
!= BAD_FILE
);
3109 dest
.type
= val
.type
;
3115 nir_emit_intrinsic(bld
, instr
);
3121 * Fetch the current render target layer index.
3124 fetch_render_target_array_index(const fs_builder
&bld
)
3126 if (bld
.shader
->devinfo
->gen
>= 6) {
3127 /* The render target array index is provided in the thread payload as
3128 * bits 26:16 of r0.0.
3130 const fs_reg idx
= bld
.vgrf(BRW_REGISTER_TYPE_UD
);
3131 bld
.AND(idx
, brw_uw1_reg(BRW_GENERAL_REGISTER_FILE
, 0, 1),
3135 /* Pre-SNB we only ever render into the first layer of the framebuffer
3136 * since layered rendering is not implemented.
3138 return brw_imm_ud(0);
3143 * Fake non-coherent framebuffer read implemented using TXF to fetch from the
3144 * framebuffer at the current fragment coordinates and sample index.
3147 fs_visitor::emit_non_coherent_fb_read(const fs_builder
&bld
, const fs_reg
&dst
,
3150 const struct gen_device_info
*devinfo
= bld
.shader
->devinfo
;
3152 assert(bld
.shader
->stage
== MESA_SHADER_FRAGMENT
);
3153 const brw_wm_prog_key
*wm_key
=
3154 reinterpret_cast<const brw_wm_prog_key
*>(key
);
3155 assert(!wm_key
->coherent_fb_fetch
);
3156 const struct brw_wm_prog_data
*wm_prog_data
=
3157 brw_wm_prog_data(stage_prog_data
);
3159 /* Calculate the surface index relative to the start of the texture binding
3160 * table block, since that's what the texturing messages expect.
3162 const unsigned surface
= target
+
3163 wm_prog_data
->binding_table
.render_target_read_start
-
3164 wm_prog_data
->base
.binding_table
.texture_start
;
3166 brw_mark_surface_used(
3167 bld
.shader
->stage_prog_data
,
3168 wm_prog_data
->binding_table
.render_target_read_start
+ target
);
3170 /* Calculate the fragment coordinates. */
3171 const fs_reg coords
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 3);
3172 bld
.MOV(offset(coords
, bld
, 0), pixel_x
);
3173 bld
.MOV(offset(coords
, bld
, 1), pixel_y
);
3174 bld
.MOV(offset(coords
, bld
, 2), fetch_render_target_array_index(bld
));
3176 /* Calculate the sample index and MCS payload when multisampling. Luckily
3177 * the MCS fetch message behaves deterministically for UMS surfaces, so it
3178 * shouldn't be necessary to recompile based on whether the framebuffer is
3181 if (wm_key
->multisample_fbo
&&
3182 nir_system_values
[SYSTEM_VALUE_SAMPLE_ID
].file
== BAD_FILE
)
3183 nir_system_values
[SYSTEM_VALUE_SAMPLE_ID
] = *emit_sampleid_setup();
3185 const fs_reg sample
= nir_system_values
[SYSTEM_VALUE_SAMPLE_ID
];
3186 const fs_reg mcs
= wm_key
->multisample_fbo
?
3187 emit_mcs_fetch(coords
, 3, brw_imm_ud(surface
)) : fs_reg();
3189 /* Use either a normal or a CMS texel fetch message depending on whether
3190 * the framebuffer is single or multisample. On SKL+ use the wide CMS
3191 * message just in case the framebuffer uses 16x multisampling, it should
3192 * be equivalent to the normal CMS fetch for lower multisampling modes.
3194 const opcode op
= !wm_key
->multisample_fbo
? SHADER_OPCODE_TXF_LOGICAL
:
3195 devinfo
->gen
>= 9 ? SHADER_OPCODE_TXF_CMS_W_LOGICAL
:
3196 SHADER_OPCODE_TXF_CMS_LOGICAL
;
3198 /* Emit the instruction. */
3199 const fs_reg srcs
[] = { coords
, fs_reg(), brw_imm_ud(0), fs_reg(),
3201 brw_imm_ud(surface
), brw_imm_ud(0),
3202 fs_reg(), brw_imm_ud(3), brw_imm_ud(0) };
3203 STATIC_ASSERT(ARRAY_SIZE(srcs
) == TEX_LOGICAL_NUM_SRCS
);
3205 fs_inst
*inst
= bld
.emit(op
, dst
, srcs
, ARRAY_SIZE(srcs
));
3206 inst
->size_written
= 4 * inst
->dst
.component_size(inst
->exec_size
);
3212 * Actual coherent framebuffer read implemented using the native render target
3213 * read message. Requires SKL+.
3216 emit_coherent_fb_read(const fs_builder
&bld
, const fs_reg
&dst
, unsigned target
)
3218 assert(bld
.shader
->devinfo
->gen
>= 9);
3219 fs_inst
*inst
= bld
.emit(FS_OPCODE_FB_READ_LOGICAL
, dst
);
3220 inst
->target
= target
;
3221 inst
->size_written
= 4 * inst
->dst
.component_size(inst
->exec_size
);
3227 alloc_temporary(const fs_builder
&bld
, unsigned size
, fs_reg
*regs
, unsigned n
)
3229 if (n
&& regs
[0].file
!= BAD_FILE
) {
3233 const fs_reg tmp
= bld
.vgrf(BRW_REGISTER_TYPE_F
, size
);
3235 for (unsigned i
= 0; i
< n
; i
++)
3243 alloc_frag_output(fs_visitor
*v
, unsigned location
)
3245 assert(v
->stage
== MESA_SHADER_FRAGMENT
);
3246 const brw_wm_prog_key
*const key
=
3247 reinterpret_cast<const brw_wm_prog_key
*>(v
->key
);
3248 const unsigned l
= GET_FIELD(location
, BRW_NIR_FRAG_OUTPUT_LOCATION
);
3249 const unsigned i
= GET_FIELD(location
, BRW_NIR_FRAG_OUTPUT_INDEX
);
3251 if (i
> 0 || (key
->force_dual_color_blend
&& l
== FRAG_RESULT_DATA1
))
3252 return alloc_temporary(v
->bld
, 4, &v
->dual_src_output
, 1);
3254 else if (l
== FRAG_RESULT_COLOR
)
3255 return alloc_temporary(v
->bld
, 4, v
->outputs
,
3256 MAX2(key
->nr_color_regions
, 1));
3258 else if (l
== FRAG_RESULT_DEPTH
)
3259 return alloc_temporary(v
->bld
, 1, &v
->frag_depth
, 1);
3261 else if (l
== FRAG_RESULT_STENCIL
)
3262 return alloc_temporary(v
->bld
, 1, &v
->frag_stencil
, 1);
3264 else if (l
== FRAG_RESULT_SAMPLE_MASK
)
3265 return alloc_temporary(v
->bld
, 1, &v
->sample_mask
, 1);
3267 else if (l
>= FRAG_RESULT_DATA0
&&
3268 l
< FRAG_RESULT_DATA0
+ BRW_MAX_DRAW_BUFFERS
)
3269 return alloc_temporary(v
->bld
, 4,
3270 &v
->outputs
[l
- FRAG_RESULT_DATA0
], 1);
3273 unreachable("Invalid location");
3277 fs_visitor::nir_emit_fs_intrinsic(const fs_builder
&bld
,
3278 nir_intrinsic_instr
*instr
)
3280 assert(stage
== MESA_SHADER_FRAGMENT
);
3283 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
3284 dest
= get_nir_dest(instr
->dest
);
3286 switch (instr
->intrinsic
) {
3287 case nir_intrinsic_load_front_face
:
3288 bld
.MOV(retype(dest
, BRW_REGISTER_TYPE_D
),
3289 *emit_frontfacing_interpolation());
3292 case nir_intrinsic_load_sample_pos
: {
3293 fs_reg sample_pos
= nir_system_values
[SYSTEM_VALUE_SAMPLE_POS
];
3294 assert(sample_pos
.file
!= BAD_FILE
);
3295 dest
.type
= sample_pos
.type
;
3296 bld
.MOV(dest
, sample_pos
);
3297 bld
.MOV(offset(dest
, bld
, 1), offset(sample_pos
, bld
, 1));
3301 case nir_intrinsic_load_layer_id
:
3302 dest
.type
= BRW_REGISTER_TYPE_UD
;
3303 bld
.MOV(dest
, fetch_render_target_array_index(bld
));
3306 case nir_intrinsic_load_helper_invocation
:
3307 case nir_intrinsic_load_sample_mask_in
:
3308 case nir_intrinsic_load_sample_id
: {
3309 gl_system_value sv
= nir_system_value_from_intrinsic(instr
->intrinsic
);
3310 fs_reg val
= nir_system_values
[sv
];
3311 assert(val
.file
!= BAD_FILE
);
3312 dest
.type
= val
.type
;
3317 case nir_intrinsic_store_output
: {
3318 const fs_reg src
= get_nir_src(instr
->src
[0]);
3319 const nir_const_value
*const_offset
= nir_src_as_const_value(instr
->src
[1]);
3320 assert(const_offset
&& "Indirect output stores not allowed");
3321 const unsigned location
= nir_intrinsic_base(instr
) +
3322 SET_FIELD(const_offset
->u32
[0], BRW_NIR_FRAG_OUTPUT_LOCATION
);
3323 const fs_reg new_dest
= retype(alloc_frag_output(this, location
),
3326 for (unsigned j
= 0; j
< instr
->num_components
; j
++)
3327 bld
.MOV(offset(new_dest
, bld
, nir_intrinsic_component(instr
) + j
),
3328 offset(src
, bld
, j
));
3333 case nir_intrinsic_load_output
: {
3334 const unsigned l
= GET_FIELD(nir_intrinsic_base(instr
),
3335 BRW_NIR_FRAG_OUTPUT_LOCATION
);
3336 assert(l
>= FRAG_RESULT_DATA0
);
3337 nir_const_value
*const_offset
= nir_src_as_const_value(instr
->src
[0]);
3338 assert(const_offset
&& "Indirect output loads not allowed");
3339 const unsigned target
= l
- FRAG_RESULT_DATA0
+ const_offset
->u32
[0];
3340 const fs_reg tmp
= bld
.vgrf(dest
.type
, 4);
3342 if (reinterpret_cast<const brw_wm_prog_key
*>(key
)->coherent_fb_fetch
)
3343 emit_coherent_fb_read(bld
, tmp
, target
);
3345 emit_non_coherent_fb_read(bld
, tmp
, target
);
3347 for (unsigned j
= 0; j
< instr
->num_components
; j
++) {
3348 bld
.MOV(offset(dest
, bld
, j
),
3349 offset(tmp
, bld
, nir_intrinsic_component(instr
) + j
));
3355 case nir_intrinsic_discard
:
3356 case nir_intrinsic_discard_if
: {
3357 /* We track our discarded pixels in f0.1. By predicating on it, we can
3358 * update just the flag bits that aren't yet discarded. If there's no
3359 * condition, we emit a CMP of g0 != g0, so all currently executing
3360 * channels will get turned off.
3363 if (instr
->intrinsic
== nir_intrinsic_discard_if
) {
3364 cmp
= bld
.CMP(bld
.null_reg_f(), get_nir_src(instr
->src
[0]),
3365 brw_imm_d(0), BRW_CONDITIONAL_Z
);
3367 fs_reg some_reg
= fs_reg(retype(brw_vec8_grf(0, 0),
3368 BRW_REGISTER_TYPE_UW
));
3369 cmp
= bld
.CMP(bld
.null_reg_f(), some_reg
, some_reg
, BRW_CONDITIONAL_NZ
);
3371 cmp
->predicate
= BRW_PREDICATE_NORMAL
;
3372 cmp
->flag_subreg
= 1;
3374 if (devinfo
->gen
>= 6) {
3375 emit_discard_jump();
3380 case nir_intrinsic_load_input
: {
3381 /* load_input is only used for flat inputs */
3382 unsigned base
= nir_intrinsic_base(instr
);
3383 unsigned component
= nir_intrinsic_component(instr
);
3384 unsigned num_components
= instr
->num_components
;
3385 enum brw_reg_type type
= dest
.type
;
3387 /* Special case fields in the VUE header */
3388 if (base
== VARYING_SLOT_LAYER
)
3390 else if (base
== VARYING_SLOT_VIEWPORT
)
3393 if (nir_dest_bit_size(instr
->dest
) == 64) {
3394 /* const_index is in 32-bit type size units that could not be aligned
3395 * with DF. We need to read the double vector as if it was a float
3396 * vector of twice the number of components to fetch the right data.
3398 type
= BRW_REGISTER_TYPE_F
;
3399 num_components
*= 2;
3402 for (unsigned int i
= 0; i
< num_components
; i
++) {
3403 struct brw_reg interp
= interp_reg(base
, component
+ i
);
3404 interp
= suboffset(interp
, 3);
3405 bld
.emit(FS_OPCODE_CINTERP
, offset(retype(dest
, type
), bld
, i
),
3406 retype(fs_reg(interp
), type
));
3409 if (nir_dest_bit_size(instr
->dest
) == 64) {
3410 shuffle_32bit_load_result_to_64bit_data(bld
,
3413 instr
->num_components
);
3418 case nir_intrinsic_load_barycentric_pixel
:
3419 case nir_intrinsic_load_barycentric_centroid
:
3420 case nir_intrinsic_load_barycentric_sample
:
3421 /* Do nothing - load_interpolated_input handling will handle it later. */
3424 case nir_intrinsic_load_barycentric_at_sample
: {
3425 const glsl_interp_mode interpolation
=
3426 (enum glsl_interp_mode
) nir_intrinsic_interp_mode(instr
);
3428 nir_const_value
*const_sample
= nir_src_as_const_value(instr
->src
[0]);
3431 unsigned msg_data
= const_sample
->i32
[0] << 4;
3433 emit_pixel_interpolater_send(bld
,
3434 FS_OPCODE_INTERPOLATE_AT_SAMPLE
,
3437 brw_imm_ud(msg_data
),
3440 const fs_reg sample_src
= retype(get_nir_src(instr
->src
[0]),
3441 BRW_REGISTER_TYPE_UD
);
3443 if (nir_src_is_dynamically_uniform(instr
->src
[0])) {
3444 const fs_reg sample_id
= bld
.emit_uniformize(sample_src
);
3445 const fs_reg msg_data
= vgrf(glsl_type::uint_type
);
3446 bld
.exec_all().group(1, 0)
3447 .SHL(msg_data
, sample_id
, brw_imm_ud(4u));
3448 emit_pixel_interpolater_send(bld
,
3449 FS_OPCODE_INTERPOLATE_AT_SAMPLE
,
3455 /* Make a loop that sends a message to the pixel interpolater
3456 * for the sample number in each live channel. If there are
3457 * multiple channels with the same sample number then these
3458 * will be handled simultaneously with a single interation of
3461 bld
.emit(BRW_OPCODE_DO
);
3463 /* Get the next live sample number into sample_id_reg */
3464 const fs_reg sample_id
= bld
.emit_uniformize(sample_src
);
3466 /* Set the flag register so that we can perform the send
3467 * message on all channels that have the same sample number
3469 bld
.CMP(bld
.null_reg_ud(),
3470 sample_src
, sample_id
,
3471 BRW_CONDITIONAL_EQ
);
3472 const fs_reg msg_data
= vgrf(glsl_type::uint_type
);
3473 bld
.exec_all().group(1, 0)
3474 .SHL(msg_data
, sample_id
, brw_imm_ud(4u));
3476 emit_pixel_interpolater_send(bld
,
3477 FS_OPCODE_INTERPOLATE_AT_SAMPLE
,
3482 set_predicate(BRW_PREDICATE_NORMAL
, inst
);
3484 /* Continue the loop if there are any live channels left */
3485 set_predicate_inv(BRW_PREDICATE_NORMAL
,
3487 bld
.emit(BRW_OPCODE_WHILE
));
3493 case nir_intrinsic_load_barycentric_at_offset
: {
3494 const glsl_interp_mode interpolation
=
3495 (enum glsl_interp_mode
) nir_intrinsic_interp_mode(instr
);
3497 nir_const_value
*const_offset
= nir_src_as_const_value(instr
->src
[0]);
3500 unsigned off_x
= MIN2((int)(const_offset
->f32
[0] * 16), 7) & 0xf;
3501 unsigned off_y
= MIN2((int)(const_offset
->f32
[1] * 16), 7) & 0xf;
3503 emit_pixel_interpolater_send(bld
,
3504 FS_OPCODE_INTERPOLATE_AT_SHARED_OFFSET
,
3507 brw_imm_ud(off_x
| (off_y
<< 4)),
3510 fs_reg src
= vgrf(glsl_type::ivec2_type
);
3511 fs_reg offset_src
= retype(get_nir_src(instr
->src
[0]),
3512 BRW_REGISTER_TYPE_F
);
3513 for (int i
= 0; i
< 2; i
++) {
3514 fs_reg temp
= vgrf(glsl_type::float_type
);
3515 bld
.MUL(temp
, offset(offset_src
, bld
, i
), brw_imm_f(16.0f
));
3516 fs_reg itemp
= vgrf(glsl_type::int_type
);
3518 bld
.MOV(itemp
, temp
);
3520 /* Clamp the upper end of the range to +7/16.
3521 * ARB_gpu_shader5 requires that we support a maximum offset
3522 * of +0.5, which isn't representable in a S0.4 value -- if
3523 * we didn't clamp it, we'd end up with -8/16, which is the
3524 * opposite of what the shader author wanted.
3526 * This is legal due to ARB_gpu_shader5's quantization
3529 * "Not all values of <offset> may be supported; x and y
3530 * offsets may be rounded to fixed-point values with the
3531 * number of fraction bits given by the
3532 * implementation-dependent constant
3533 * FRAGMENT_INTERPOLATION_OFFSET_BITS"
3535 set_condmod(BRW_CONDITIONAL_L
,
3536 bld
.SEL(offset(src
, bld
, i
), itemp
, brw_imm_d(7)));
3539 const enum opcode opcode
= FS_OPCODE_INTERPOLATE_AT_PER_SLOT_OFFSET
;
3540 emit_pixel_interpolater_send(bld
,
3550 case nir_intrinsic_load_interpolated_input
: {
3551 if (nir_intrinsic_base(instr
) == VARYING_SLOT_POS
) {
3552 emit_fragcoord_interpolation(dest
);
3556 assert(instr
->src
[0].ssa
&&
3557 instr
->src
[0].ssa
->parent_instr
->type
== nir_instr_type_intrinsic
);
3558 nir_intrinsic_instr
*bary_intrinsic
=
3559 nir_instr_as_intrinsic(instr
->src
[0].ssa
->parent_instr
);
3560 nir_intrinsic_op bary_intrin
= bary_intrinsic
->intrinsic
;
3561 enum glsl_interp_mode interp_mode
=
3562 (enum glsl_interp_mode
) nir_intrinsic_interp_mode(bary_intrinsic
);
3565 if (bary_intrin
== nir_intrinsic_load_barycentric_at_offset
||
3566 bary_intrin
== nir_intrinsic_load_barycentric_at_sample
) {
3567 /* Use the result of the PI message */
3568 dst_xy
= retype(get_nir_src(instr
->src
[0]), BRW_REGISTER_TYPE_F
);
3570 /* Use the delta_xy values computed from the payload */
3571 enum brw_barycentric_mode bary
=
3572 brw_barycentric_mode(interp_mode
, bary_intrin
);
3574 dst_xy
= this->delta_xy
[bary
];
3577 for (unsigned int i
= 0; i
< instr
->num_components
; i
++) {
3579 fs_reg(interp_reg(nir_intrinsic_base(instr
),
3580 nir_intrinsic_component(instr
) + i
));
3581 interp
.type
= BRW_REGISTER_TYPE_F
;
3582 dest
.type
= BRW_REGISTER_TYPE_F
;
3584 if (devinfo
->gen
< 6 && interp_mode
== INTERP_MODE_SMOOTH
) {
3585 fs_reg tmp
= vgrf(glsl_type::float_type
);
3586 bld
.emit(FS_OPCODE_LINTERP
, tmp
, dst_xy
, interp
);
3587 bld
.MUL(offset(dest
, bld
, i
), tmp
, this->pixel_w
);
3589 bld
.emit(FS_OPCODE_LINTERP
, offset(dest
, bld
, i
), dst_xy
, interp
);
3596 nir_emit_intrinsic(bld
, instr
);
3602 fs_visitor::nir_emit_cs_intrinsic(const fs_builder
&bld
,
3603 nir_intrinsic_instr
*instr
)
3605 assert(stage
== MESA_SHADER_COMPUTE
);
3606 struct brw_cs_prog_data
*cs_prog_data
= brw_cs_prog_data(prog_data
);
3609 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
3610 dest
= get_nir_dest(instr
->dest
);
3612 switch (instr
->intrinsic
) {
3613 case nir_intrinsic_barrier
:
3615 cs_prog_data
->uses_barrier
= true;
3618 case nir_intrinsic_load_subgroup_id
:
3619 bld
.MOV(retype(dest
, BRW_REGISTER_TYPE_UD
), subgroup_id
);
3622 case nir_intrinsic_load_local_invocation_id
:
3623 case nir_intrinsic_load_work_group_id
: {
3624 gl_system_value sv
= nir_system_value_from_intrinsic(instr
->intrinsic
);
3625 fs_reg val
= nir_system_values
[sv
];
3626 assert(val
.file
!= BAD_FILE
);
3627 dest
.type
= val
.type
;
3628 for (unsigned i
= 0; i
< 3; i
++)
3629 bld
.MOV(offset(dest
, bld
, i
), offset(val
, bld
, i
));
3633 case nir_intrinsic_load_num_work_groups
: {
3634 const unsigned surface
=
3635 cs_prog_data
->binding_table
.work_groups_start
;
3637 cs_prog_data
->uses_num_work_groups
= true;
3639 fs_reg surf_index
= brw_imm_ud(surface
);
3640 brw_mark_surface_used(prog_data
, surface
);
3642 /* Read the 3 GLuint components of gl_NumWorkGroups */
3643 for (unsigned i
= 0; i
< 3; i
++) {
3644 fs_reg read_result
=
3645 emit_untyped_read(bld
, surf_index
,
3647 1 /* dims */, 1 /* size */,
3648 BRW_PREDICATE_NONE
);
3649 read_result
.type
= dest
.type
;
3650 bld
.MOV(dest
, read_result
);
3651 dest
= offset(dest
, bld
, 1);
3656 case nir_intrinsic_shared_atomic_add
:
3657 nir_emit_shared_atomic(bld
, BRW_AOP_ADD
, instr
);
3659 case nir_intrinsic_shared_atomic_imin
:
3660 nir_emit_shared_atomic(bld
, BRW_AOP_IMIN
, instr
);
3662 case nir_intrinsic_shared_atomic_umin
:
3663 nir_emit_shared_atomic(bld
, BRW_AOP_UMIN
, instr
);
3665 case nir_intrinsic_shared_atomic_imax
:
3666 nir_emit_shared_atomic(bld
, BRW_AOP_IMAX
, instr
);
3668 case nir_intrinsic_shared_atomic_umax
:
3669 nir_emit_shared_atomic(bld
, BRW_AOP_UMAX
, instr
);
3671 case nir_intrinsic_shared_atomic_and
:
3672 nir_emit_shared_atomic(bld
, BRW_AOP_AND
, instr
);
3674 case nir_intrinsic_shared_atomic_or
:
3675 nir_emit_shared_atomic(bld
, BRW_AOP_OR
, instr
);
3677 case nir_intrinsic_shared_atomic_xor
:
3678 nir_emit_shared_atomic(bld
, BRW_AOP_XOR
, instr
);
3680 case nir_intrinsic_shared_atomic_exchange
:
3681 nir_emit_shared_atomic(bld
, BRW_AOP_MOV
, instr
);
3683 case nir_intrinsic_shared_atomic_comp_swap
:
3684 nir_emit_shared_atomic(bld
, BRW_AOP_CMPWR
, instr
);
3687 case nir_intrinsic_load_shared
: {
3688 assert(devinfo
->gen
>= 7);
3690 fs_reg surf_index
= brw_imm_ud(GEN7_BTI_SLM
);
3692 /* Get the offset to read from */
3694 nir_const_value
*const_offset
= nir_src_as_const_value(instr
->src
[0]);
3696 offset_reg
= brw_imm_ud(instr
->const_index
[0] + const_offset
->u32
[0]);
3698 offset_reg
= vgrf(glsl_type::uint_type
);
3700 retype(get_nir_src(instr
->src
[0]), BRW_REGISTER_TYPE_UD
),
3701 brw_imm_ud(instr
->const_index
[0]));
3704 /* Read the vector */
3705 do_untyped_vector_read(bld
, dest
, surf_index
, offset_reg
,
3706 instr
->num_components
);
3710 case nir_intrinsic_store_shared
: {
3711 assert(devinfo
->gen
>= 7);
3714 fs_reg surf_index
= brw_imm_ud(GEN7_BTI_SLM
);
3717 fs_reg val_reg
= get_nir_src(instr
->src
[0]);
3720 unsigned writemask
= instr
->const_index
[1];
3722 /* get_nir_src() retypes to integer. Be wary of 64-bit types though
3723 * since the untyped writes below operate in units of 32-bits, which
3724 * means that we need to write twice as many components each time.
3725 * Also, we have to suffle 64-bit data to be in the appropriate layout
3726 * expected by our 32-bit write messages.
3728 unsigned type_size
= 4;
3729 if (nir_src_bit_size(instr
->src
[0]) == 64) {
3731 val_reg
= shuffle_64bit_data_for_32bit_write(bld
,
3732 val_reg
, instr
->num_components
);
3735 unsigned type_slots
= type_size
/ 4;
3737 /* Combine groups of consecutive enabled channels in one write
3738 * message. We use ffs to find the first enabled channel and then ffs on
3739 * the bit-inverse, down-shifted writemask to determine the length of
3740 * the block of enabled bits.
3743 unsigned first_component
= ffs(writemask
) - 1;
3744 unsigned length
= ffs(~(writemask
>> first_component
)) - 1;
3746 /* We can't write more than 2 64-bit components at once. Limit the
3747 * length of the write to what we can do and let the next iteration
3751 length
= MIN2(2, length
);
3754 nir_const_value
*const_offset
= nir_src_as_const_value(instr
->src
[1]);
3756 offset_reg
= brw_imm_ud(instr
->const_index
[0] + const_offset
->u32
[0] +
3757 type_size
* first_component
);
3759 offset_reg
= vgrf(glsl_type::uint_type
);
3761 retype(get_nir_src(instr
->src
[1]), BRW_REGISTER_TYPE_UD
),
3762 brw_imm_ud(instr
->const_index
[0] + type_size
* first_component
));
3765 emit_untyped_write(bld
, surf_index
, offset_reg
,
3766 offset(val_reg
, bld
, first_component
* type_slots
),
3767 1 /* dims */, length
* type_slots
,
3768 BRW_PREDICATE_NONE
);
3770 /* Clear the bits in the writemask that we just wrote, then try
3771 * again to see if more channels are left.
3773 writemask
&= (15 << (first_component
+ length
));
3780 nir_emit_intrinsic(bld
, instr
);
3786 brw_nir_reduction_op_identity(const fs_builder
&bld
,
3787 nir_op op
, brw_reg_type type
)
3789 nir_const_value value
= nir_alu_binop_identity(op
, type_sz(type
) * 8);
3790 switch (type_sz(type
)) {
3792 assert(type
!= BRW_REGISTER_TYPE_HF
);
3793 return retype(brw_imm_uw(value
.u16
[0]), type
);
3795 return retype(brw_imm_ud(value
.u32
[0]), type
);
3797 if (type
== BRW_REGISTER_TYPE_DF
)
3798 return setup_imm_df(bld
, value
.f64
[0]);
3800 return retype(brw_imm_u64(value
.u64
[0]), type
);
3802 unreachable("Invalid type size");
3807 brw_op_for_nir_reduction_op(nir_op op
)
3810 case nir_op_iadd
: return BRW_OPCODE_ADD
;
3811 case nir_op_fadd
: return BRW_OPCODE_ADD
;
3812 case nir_op_imul
: return BRW_OPCODE_MUL
;
3813 case nir_op_fmul
: return BRW_OPCODE_MUL
;
3814 case nir_op_imin
: return BRW_OPCODE_SEL
;
3815 case nir_op_umin
: return BRW_OPCODE_SEL
;
3816 case nir_op_fmin
: return BRW_OPCODE_SEL
;
3817 case nir_op_imax
: return BRW_OPCODE_SEL
;
3818 case nir_op_umax
: return BRW_OPCODE_SEL
;
3819 case nir_op_fmax
: return BRW_OPCODE_SEL
;
3820 case nir_op_iand
: return BRW_OPCODE_AND
;
3821 case nir_op_ior
: return BRW_OPCODE_OR
;
3822 case nir_op_ixor
: return BRW_OPCODE_XOR
;
3824 unreachable("Invalid reduction operation");
3828 static brw_conditional_mod
3829 brw_cond_mod_for_nir_reduction_op(nir_op op
)
3832 case nir_op_iadd
: return BRW_CONDITIONAL_NONE
;
3833 case nir_op_fadd
: return BRW_CONDITIONAL_NONE
;
3834 case nir_op_imul
: return BRW_CONDITIONAL_NONE
;
3835 case nir_op_fmul
: return BRW_CONDITIONAL_NONE
;
3836 case nir_op_imin
: return BRW_CONDITIONAL_L
;
3837 case nir_op_umin
: return BRW_CONDITIONAL_L
;
3838 case nir_op_fmin
: return BRW_CONDITIONAL_L
;
3839 case nir_op_imax
: return BRW_CONDITIONAL_GE
;
3840 case nir_op_umax
: return BRW_CONDITIONAL_GE
;
3841 case nir_op_fmax
: return BRW_CONDITIONAL_GE
;
3842 case nir_op_iand
: return BRW_CONDITIONAL_NONE
;
3843 case nir_op_ior
: return BRW_CONDITIONAL_NONE
;
3844 case nir_op_ixor
: return BRW_CONDITIONAL_NONE
;
3846 unreachable("Invalid reduction operation");
3851 fs_visitor::nir_emit_intrinsic(const fs_builder
&bld
, nir_intrinsic_instr
*instr
)
3854 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
3855 dest
= get_nir_dest(instr
->dest
);
3857 switch (instr
->intrinsic
) {
3858 case nir_intrinsic_image_var_load
:
3859 case nir_intrinsic_image_var_store
:
3860 case nir_intrinsic_image_var_atomic_add
:
3861 case nir_intrinsic_image_var_atomic_min
:
3862 case nir_intrinsic_image_var_atomic_max
:
3863 case nir_intrinsic_image_var_atomic_and
:
3864 case nir_intrinsic_image_var_atomic_or
:
3865 case nir_intrinsic_image_var_atomic_xor
:
3866 case nir_intrinsic_image_var_atomic_exchange
:
3867 case nir_intrinsic_image_var_atomic_comp_swap
: {
3868 using namespace image_access
;
3870 if (stage
== MESA_SHADER_FRAGMENT
&&
3871 instr
->intrinsic
!= nir_intrinsic_image_var_load
)
3872 brw_wm_prog_data(prog_data
)->has_side_effects
= true;
3874 /* Get the referenced image variable and type. */
3875 const nir_variable
*var
= instr
->variables
[0]->var
;
3876 const glsl_type
*type
= var
->type
->without_array();
3877 const brw_reg_type base_type
= get_image_base_type(type
);
3879 /* Get some metadata from the image intrinsic. */
3880 const nir_intrinsic_info
*info
= &nir_intrinsic_infos
[instr
->intrinsic
];
3881 const unsigned arr_dims
= type
->sampler_array
? 1 : 0;
3882 const unsigned surf_dims
= type
->coordinate_components() - arr_dims
;
3883 const unsigned format
= var
->data
.image
.format
;
3884 const unsigned dest_components
= nir_intrinsic_dest_components(instr
);
3886 /* Get the arguments of the image intrinsic. */
3887 const fs_reg image
= get_nir_image_deref(instr
->variables
[0]);
3888 const fs_reg addr
= retype(get_nir_src(instr
->src
[0]),
3889 BRW_REGISTER_TYPE_UD
);
3890 const fs_reg src0
= (info
->num_srcs
>= 3 ?
3891 retype(get_nir_src(instr
->src
[2]), base_type
) :
3893 const fs_reg src1
= (info
->num_srcs
>= 4 ?
3894 retype(get_nir_src(instr
->src
[3]), base_type
) :
3898 /* Emit an image load, store or atomic op. */
3899 if (instr
->intrinsic
== nir_intrinsic_image_var_load
)
3900 tmp
= emit_image_load(bld
, image
, addr
, surf_dims
, arr_dims
, format
);
3902 else if (instr
->intrinsic
== nir_intrinsic_image_var_store
)
3903 emit_image_store(bld
, image
, addr
, src0
, surf_dims
, arr_dims
,
3904 var
->data
.image
.write_only
? GL_NONE
: format
);
3907 tmp
= emit_image_atomic(bld
, image
, addr
, src0
, src1
,
3908 surf_dims
, arr_dims
, dest_components
,
3909 get_image_atomic_op(instr
->intrinsic
, type
));
3911 /* Assign the result. */
3912 for (unsigned c
= 0; c
< dest_components
; ++c
) {
3913 bld
.MOV(offset(retype(dest
, base_type
), bld
, c
),
3914 offset(tmp
, bld
, c
));
3919 case nir_intrinsic_memory_barrier_atomic_counter
:
3920 case nir_intrinsic_memory_barrier_buffer
:
3921 case nir_intrinsic_memory_barrier_image
:
3922 case nir_intrinsic_memory_barrier
: {
3923 const fs_builder ubld
= bld
.group(8, 0);
3924 const fs_reg tmp
= ubld
.vgrf(BRW_REGISTER_TYPE_UD
, 2);
3925 ubld
.emit(SHADER_OPCODE_MEMORY_FENCE
, tmp
)
3926 ->size_written
= 2 * REG_SIZE
;
3930 case nir_intrinsic_group_memory_barrier
:
3931 case nir_intrinsic_memory_barrier_shared
:
3932 /* We treat these workgroup-level barriers as no-ops. This should be
3933 * safe at present and as long as:
3935 * - Memory access instructions are not subsequently reordered by the
3936 * compiler back-end.
3938 * - All threads from a given compute shader workgroup fit within a
3939 * single subslice and therefore talk to the same HDC shared unit
3940 * what supposedly guarantees ordering and coherency between threads
3941 * from the same workgroup. This may change in the future when we
3942 * start splitting workgroups across multiple subslices.
3944 * - The context is not in fault-and-stream mode, which could cause
3945 * memory transactions (including to SLM) prior to the barrier to be
3946 * replayed after the barrier if a pagefault occurs. This shouldn't
3947 * be a problem up to and including SKL because fault-and-stream is
3948 * not usable due to hardware issues, but that's likely to change in
3953 case nir_intrinsic_shader_clock
: {
3954 /* We cannot do anything if there is an event, so ignore it for now */
3955 const fs_reg shader_clock
= get_timestamp(bld
);
3956 const fs_reg srcs
[] = { component(shader_clock
, 0),
3957 component(shader_clock
, 1) };
3958 bld
.LOAD_PAYLOAD(dest
, srcs
, ARRAY_SIZE(srcs
), 0);
3962 case nir_intrinsic_image_var_size
: {
3963 /* Get the referenced image variable and type. */
3964 const nir_variable
*var
= instr
->variables
[0]->var
;
3965 const glsl_type
*type
= var
->type
->without_array();
3967 /* Get the size of the image. */
3968 const fs_reg image
= get_nir_image_deref(instr
->variables
[0]);
3969 const fs_reg size
= offset(image
, bld
, BRW_IMAGE_PARAM_SIZE_OFFSET
);
3971 /* For 1DArray image types, the array index is stored in the Z component.
3972 * Fix this by swizzling the Z component to the Y component.
3974 const bool is_1d_array_image
=
3975 type
->sampler_dimensionality
== GLSL_SAMPLER_DIM_1D
&&
3976 type
->sampler_array
;
3978 /* For CubeArray images, we should count the number of cubes instead
3979 * of the number of faces. Fix it by dividing the (Z component) by 6.
3981 const bool is_cube_array_image
=
3982 type
->sampler_dimensionality
== GLSL_SAMPLER_DIM_CUBE
&&
3983 type
->sampler_array
;
3985 /* Copy all the components. */
3986 for (unsigned c
= 0; c
< instr
->dest
.ssa
.num_components
; ++c
) {
3987 if ((int)c
>= type
->coordinate_components()) {
3988 bld
.MOV(offset(retype(dest
, BRW_REGISTER_TYPE_D
), bld
, c
),
3990 } else if (c
== 1 && is_1d_array_image
) {
3991 bld
.MOV(offset(retype(dest
, BRW_REGISTER_TYPE_D
), bld
, c
),
3992 offset(size
, bld
, 2));
3993 } else if (c
== 2 && is_cube_array_image
) {
3994 bld
.emit(SHADER_OPCODE_INT_QUOTIENT
,
3995 offset(retype(dest
, BRW_REGISTER_TYPE_D
), bld
, c
),
3996 offset(size
, bld
, c
), brw_imm_d(6));
3998 bld
.MOV(offset(retype(dest
, BRW_REGISTER_TYPE_D
), bld
, c
),
3999 offset(size
, bld
, c
));
4006 case nir_intrinsic_image_var_samples
:
4007 /* The driver does not support multi-sampled images. */
4008 bld
.MOV(retype(dest
, BRW_REGISTER_TYPE_D
), brw_imm_d(1));
4011 case nir_intrinsic_load_uniform
: {
4012 /* Offsets are in bytes but they should always aligned to
4015 assert(instr
->const_index
[0] % 4 == 0 ||
4016 instr
->const_index
[0] % type_sz(dest
.type
) == 0);
4018 fs_reg
src(UNIFORM
, instr
->const_index
[0] / 4, dest
.type
);
4020 nir_const_value
*const_offset
= nir_src_as_const_value(instr
->src
[0]);
4022 assert(const_offset
->u32
[0] % type_sz(dest
.type
) == 0);
4023 /* For 16-bit types we add the module of the const_index[0]
4024 * offset to access to not 32-bit aligned element
4026 src
.offset
= const_offset
->u32
[0] + instr
->const_index
[0] % 4;
4028 for (unsigned j
= 0; j
< instr
->num_components
; j
++) {
4029 bld
.MOV(offset(dest
, bld
, j
), offset(src
, bld
, j
));
4032 fs_reg indirect
= retype(get_nir_src(instr
->src
[0]),
4033 BRW_REGISTER_TYPE_UD
);
4035 /* We need to pass a size to the MOV_INDIRECT but we don't want it to
4036 * go past the end of the uniform. In order to keep the n'th
4037 * component from running past, we subtract off the size of all but
4038 * one component of the vector.
4040 assert(instr
->const_index
[1] >=
4041 instr
->num_components
* (int) type_sz(dest
.type
));
4042 unsigned read_size
= instr
->const_index
[1] -
4043 (instr
->num_components
- 1) * type_sz(dest
.type
);
4045 bool supports_64bit_indirects
=
4046 !devinfo
->is_cherryview
&& !gen_device_info_is_9lp(devinfo
);
4048 if (type_sz(dest
.type
) != 8 || supports_64bit_indirects
) {
4049 for (unsigned j
= 0; j
< instr
->num_components
; j
++) {
4050 bld
.emit(SHADER_OPCODE_MOV_INDIRECT
,
4051 offset(dest
, bld
, j
), offset(src
, bld
, j
),
4052 indirect
, brw_imm_ud(read_size
));
4055 const unsigned num_mov_indirects
=
4056 type_sz(dest
.type
) / type_sz(BRW_REGISTER_TYPE_UD
);
4057 /* We read a little bit less per MOV INDIRECT, as they are now
4058 * 32-bits ones instead of 64-bit. Fix read_size then.
4060 const unsigned read_size_32bit
= read_size
-
4061 (num_mov_indirects
- 1) * type_sz(BRW_REGISTER_TYPE_UD
);
4062 for (unsigned j
= 0; j
< instr
->num_components
; j
++) {
4063 for (unsigned i
= 0; i
< num_mov_indirects
; i
++) {
4064 bld
.emit(SHADER_OPCODE_MOV_INDIRECT
,
4065 subscript(offset(dest
, bld
, j
), BRW_REGISTER_TYPE_UD
, i
),
4066 subscript(offset(src
, bld
, j
), BRW_REGISTER_TYPE_UD
, i
),
4067 indirect
, brw_imm_ud(read_size_32bit
));
4075 case nir_intrinsic_load_ubo
: {
4076 nir_const_value
*const_index
= nir_src_as_const_value(instr
->src
[0]);
4080 const unsigned index
= stage_prog_data
->binding_table
.ubo_start
+
4081 const_index
->u32
[0];
4082 surf_index
= brw_imm_ud(index
);
4083 brw_mark_surface_used(prog_data
, index
);
4085 /* The block index is not a constant. Evaluate the index expression
4086 * per-channel and add the base UBO index; we have to select a value
4087 * from any live channel.
4089 surf_index
= vgrf(glsl_type::uint_type
);
4090 bld
.ADD(surf_index
, get_nir_src(instr
->src
[0]),
4091 brw_imm_ud(stage_prog_data
->binding_table
.ubo_start
));
4092 surf_index
= bld
.emit_uniformize(surf_index
);
4094 /* Assume this may touch any UBO. It would be nice to provide
4095 * a tighter bound, but the array information is already lowered away.
4097 brw_mark_surface_used(prog_data
,
4098 stage_prog_data
->binding_table
.ubo_start
+
4099 nir
->info
.num_ubos
- 1);
4102 nir_const_value
*const_offset
= nir_src_as_const_value(instr
->src
[1]);
4103 if (const_offset
== NULL
) {
4104 fs_reg base_offset
= retype(get_nir_src(instr
->src
[1]),
4105 BRW_REGISTER_TYPE_UD
);
4107 for (int i
= 0; i
< instr
->num_components
; i
++)
4108 VARYING_PULL_CONSTANT_LOAD(bld
, offset(dest
, bld
, i
), surf_index
,
4109 base_offset
, i
* type_sz(dest
.type
));
4111 /* Even if we are loading doubles, a pull constant load will load
4112 * a 32-bit vec4, so should only reserve vgrf space for that. If we
4113 * need to load a full dvec4 we will have to emit 2 loads. This is
4114 * similar to demote_pull_constants(), except that in that case we
4115 * see individual accesses to each component of the vector and then
4116 * we let CSE deal with duplicate loads. Here we see a vector access
4117 * and we have to split it if necessary.
4119 const unsigned type_size
= type_sz(dest
.type
);
4121 /* See if we've selected this as a push constant candidate */
4123 const unsigned ubo_block
= const_index
->u32
[0];
4124 const unsigned offset_256b
= const_offset
->u32
[0] / 32;
4127 for (int i
= 0; i
< 4; i
++) {
4128 const struct brw_ubo_range
*range
= &prog_data
->ubo_ranges
[i
];
4129 if (range
->block
== ubo_block
&&
4130 offset_256b
>= range
->start
&&
4131 offset_256b
< range
->start
+ range
->length
) {
4133 push_reg
= fs_reg(UNIFORM
, UBO_START
+ i
, dest
.type
);
4134 push_reg
.offset
= const_offset
->u32
[0] - 32 * range
->start
;
4139 if (push_reg
.file
!= BAD_FILE
) {
4140 for (unsigned i
= 0; i
< instr
->num_components
; i
++) {
4141 bld
.MOV(offset(dest
, bld
, i
),
4142 byte_offset(push_reg
, i
* type_size
));
4148 const unsigned block_sz
= 64; /* Fetch one cacheline at a time. */
4149 const fs_builder ubld
= bld
.exec_all().group(block_sz
/ 4, 0);
4150 const fs_reg packed_consts
= ubld
.vgrf(BRW_REGISTER_TYPE_UD
);
4152 for (unsigned c
= 0; c
< instr
->num_components
;) {
4153 const unsigned base
= const_offset
->u32
[0] + c
* type_size
;
4154 /* Number of usable components in the next block-aligned load. */
4155 const unsigned count
= MIN2(instr
->num_components
- c
,
4156 (block_sz
- base
% block_sz
) / type_size
);
4158 ubld
.emit(FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD
,
4159 packed_consts
, surf_index
,
4160 brw_imm_ud(base
& ~(block_sz
- 1)));
4162 const fs_reg consts
=
4163 retype(byte_offset(packed_consts
, base
& (block_sz
- 1)),
4166 for (unsigned d
= 0; d
< count
; d
++)
4167 bld
.MOV(offset(dest
, bld
, c
+ d
), component(consts
, d
));
4175 case nir_intrinsic_load_ssbo
: {
4176 assert(devinfo
->gen
>= 7);
4178 nir_const_value
*const_uniform_block
=
4179 nir_src_as_const_value(instr
->src
[0]);
4182 if (const_uniform_block
) {
4183 unsigned index
= stage_prog_data
->binding_table
.ssbo_start
+
4184 const_uniform_block
->u32
[0];
4185 surf_index
= brw_imm_ud(index
);
4186 brw_mark_surface_used(prog_data
, index
);
4188 surf_index
= vgrf(glsl_type::uint_type
);
4189 bld
.ADD(surf_index
, get_nir_src(instr
->src
[0]),
4190 brw_imm_ud(stage_prog_data
->binding_table
.ssbo_start
));
4192 /* Assume this may touch any UBO. It would be nice to provide
4193 * a tighter bound, but the array information is already lowered away.
4195 brw_mark_surface_used(prog_data
,
4196 stage_prog_data
->binding_table
.ssbo_start
+
4197 nir
->info
.num_ssbos
- 1);
4201 nir_const_value
*const_offset
= nir_src_as_const_value(instr
->src
[1]);
4203 offset_reg
= brw_imm_ud(const_offset
->u32
[0]);
4205 offset_reg
= retype(get_nir_src(instr
->src
[1]), BRW_REGISTER_TYPE_UD
);
4208 /* Read the vector */
4209 do_untyped_vector_read(bld
, dest
, surf_index
, offset_reg
,
4210 instr
->num_components
);
4215 case nir_intrinsic_store_ssbo
: {
4216 assert(devinfo
->gen
>= 7);
4218 if (stage
== MESA_SHADER_FRAGMENT
)
4219 brw_wm_prog_data(prog_data
)->has_side_effects
= true;
4223 nir_const_value
*const_uniform_block
=
4224 nir_src_as_const_value(instr
->src
[1]);
4225 if (const_uniform_block
) {
4226 unsigned index
= stage_prog_data
->binding_table
.ssbo_start
+
4227 const_uniform_block
->u32
[0];
4228 surf_index
= brw_imm_ud(index
);
4229 brw_mark_surface_used(prog_data
, index
);
4231 surf_index
= vgrf(glsl_type::uint_type
);
4232 bld
.ADD(surf_index
, get_nir_src(instr
->src
[1]),
4233 brw_imm_ud(stage_prog_data
->binding_table
.ssbo_start
));
4235 brw_mark_surface_used(prog_data
,
4236 stage_prog_data
->binding_table
.ssbo_start
+
4237 nir
->info
.num_ssbos
- 1);
4241 fs_reg val_reg
= get_nir_src(instr
->src
[0]);
4244 unsigned writemask
= instr
->const_index
[0];
4246 /* get_nir_src() retypes to integer. Be wary of 64-bit types though
4247 * since the untyped writes below operate in units of 32-bits, which
4248 * means that we need to write twice as many components each time.
4249 * Also, we have to suffle 64-bit data to be in the appropriate layout
4250 * expected by our 32-bit write messages.
4252 unsigned bit_size
= nir_src_bit_size(instr
->src
[0]);
4253 unsigned type_size
= bit_size
/ 8;
4255 /* Combine groups of consecutive enabled channels in one write
4256 * message. We use ffs to find the first enabled channel and then ffs on
4257 * the bit-inverse, down-shifted writemask to determine the num_components
4258 * of the block of enabled bits.
4261 unsigned first_component
= ffs(writemask
) - 1;
4262 unsigned num_components
= ffs(~(writemask
>> first_component
)) - 1;
4263 fs_reg write_src
= offset(val_reg
, bld
, first_component
);
4265 nir_const_value
*const_offset
= nir_src_as_const_value(instr
->src
[2]);
4267 if (type_size
> 4) {
4268 /* We can't write more than 2 64-bit components at once. Limit
4269 * the num_components of the write to what we can do and let the next
4270 * iteration handle the rest.
4272 num_components
= MIN2(2, num_components
);
4273 write_src
= shuffle_64bit_data_for_32bit_write(bld
, write_src
,
4275 } else if (type_size
< 4) {
4276 assert(type_size
== 2);
4277 /* For 16-bit types we pack two consecutive values into a 32-bit
4278 * word and use an untyped write message. For single values or not
4279 * 32-bit-aligned we need to use byte-scattered writes because
4280 * untyped writes works with 32-bit components with 32-bit
4281 * alignment. byte_scattered_write messages only support one
4282 * 16-bit component at a time. As VK_KHR_relaxed_block_layout
4283 * could be enabled we can not guarantee that not constant offsets
4284 * to be 32-bit aligned for 16-bit types. For example an array, of
4285 * 16-bit vec3 with array element stride of 6.
4287 * In the case of 32-bit aligned constant offsets if there is
4288 * a 3-components vector we submit one untyped-write message
4289 * of 32-bit (first two components), and one byte-scattered
4290 * write message (the last component).
4293 if ( !const_offset
|| ((const_offset
->u32
[0] +
4294 type_size
* first_component
) % 4)) {
4295 /* If we use a .yz writemask we also need to emit 2
4296 * byte-scattered write messages because of y-component not
4297 * being aligned to 32-bit.
4300 } else if (num_components
> 2 && (num_components
% 2)) {
4301 /* If there is an odd number of consecutive components we left
4302 * the not paired component for a following emit of length == 1
4303 * with byte_scattered_write.
4307 /* For num_components == 1 we are also shuffling the component
4308 * because byte scattered writes of 16-bit need values to be dword
4309 * aligned. Shuffling only one component would be the same as
4312 fs_reg tmp
= bld
.vgrf(BRW_REGISTER_TYPE_D
,
4313 DIV_ROUND_UP(num_components
, 2));
4314 shuffle_16bit_data_for_32bit_write(bld
, tmp
, write_src
,
4322 offset_reg
= brw_imm_ud(const_offset
->u32
[0] +
4323 type_size
* first_component
);
4325 offset_reg
= vgrf(glsl_type::uint_type
);
4327 retype(get_nir_src(instr
->src
[2]), BRW_REGISTER_TYPE_UD
),
4328 brw_imm_ud(type_size
* first_component
));
4331 if (type_size
< 4 && num_components
== 1) {
4332 assert(type_size
== 2);
4333 /* Untyped Surface messages have a fixed 32-bit size, so we need
4334 * to rely on byte scattered in order to write 16-bit elements.
4335 * The byte_scattered_write message needs that every written 16-bit
4336 * type to be aligned 32-bits (stride=2).
4338 emit_byte_scattered_write(bld
, surf_index
, offset_reg
,
4342 BRW_PREDICATE_NONE
);
4344 assert(num_components
* type_size
<= 16);
4345 assert((num_components
* type_size
) % 4 == 0);
4346 assert(offset_reg
.file
!= BRW_IMMEDIATE_VALUE
||
4347 offset_reg
.ud
% 4 == 0);
4348 unsigned num_slots
= (num_components
* type_size
) / 4;
4350 emit_untyped_write(bld
, surf_index
, offset_reg
,
4352 1 /* dims */, num_slots
,
4353 BRW_PREDICATE_NONE
);
4356 /* Clear the bits in the writemask that we just wrote, then try
4357 * again to see if more channels are left.
4359 writemask
&= (15 << (first_component
+ num_components
));
4364 case nir_intrinsic_store_output
: {
4365 fs_reg src
= get_nir_src(instr
->src
[0]);
4367 nir_const_value
*const_offset
= nir_src_as_const_value(instr
->src
[1]);
4368 assert(const_offset
&& "Indirect output stores not allowed");
4370 unsigned num_components
= instr
->num_components
;
4371 unsigned first_component
= nir_intrinsic_component(instr
);
4372 if (nir_src_bit_size(instr
->src
[0]) == 64) {
4373 src
= shuffle_64bit_data_for_32bit_write(bld
, src
, num_components
);
4374 num_components
*= 2;
4377 fs_reg new_dest
= retype(offset(outputs
[instr
->const_index
[0]], bld
,
4378 4 * const_offset
->u32
[0]), src
.type
);
4379 for (unsigned j
= 0; j
< num_components
; j
++) {
4380 bld
.MOV(offset(new_dest
, bld
, j
+ first_component
),
4381 offset(src
, bld
, j
));
4386 case nir_intrinsic_ssbo_atomic_add
:
4387 nir_emit_ssbo_atomic(bld
, BRW_AOP_ADD
, instr
);
4389 case nir_intrinsic_ssbo_atomic_imin
:
4390 nir_emit_ssbo_atomic(bld
, BRW_AOP_IMIN
, instr
);
4392 case nir_intrinsic_ssbo_atomic_umin
:
4393 nir_emit_ssbo_atomic(bld
, BRW_AOP_UMIN
, instr
);
4395 case nir_intrinsic_ssbo_atomic_imax
:
4396 nir_emit_ssbo_atomic(bld
, BRW_AOP_IMAX
, instr
);
4398 case nir_intrinsic_ssbo_atomic_umax
:
4399 nir_emit_ssbo_atomic(bld
, BRW_AOP_UMAX
, instr
);
4401 case nir_intrinsic_ssbo_atomic_and
:
4402 nir_emit_ssbo_atomic(bld
, BRW_AOP_AND
, instr
);
4404 case nir_intrinsic_ssbo_atomic_or
:
4405 nir_emit_ssbo_atomic(bld
, BRW_AOP_OR
, instr
);
4407 case nir_intrinsic_ssbo_atomic_xor
:
4408 nir_emit_ssbo_atomic(bld
, BRW_AOP_XOR
, instr
);
4410 case nir_intrinsic_ssbo_atomic_exchange
:
4411 nir_emit_ssbo_atomic(bld
, BRW_AOP_MOV
, instr
);
4413 case nir_intrinsic_ssbo_atomic_comp_swap
:
4414 nir_emit_ssbo_atomic(bld
, BRW_AOP_CMPWR
, instr
);
4417 case nir_intrinsic_get_buffer_size
: {
4418 nir_const_value
*const_uniform_block
= nir_src_as_const_value(instr
->src
[0]);
4419 unsigned ssbo_index
= const_uniform_block
? const_uniform_block
->u32
[0] : 0;
4421 /* A resinfo's sampler message is used to get the buffer size. The
4422 * SIMD8's writeback message consists of four registers and SIMD16's
4423 * writeback message consists of 8 destination registers (two per each
4424 * component). Because we are only interested on the first channel of
4425 * the first returned component, where resinfo returns the buffer size
4426 * for SURFTYPE_BUFFER, we can just use the SIMD8 variant regardless of
4427 * the dispatch width.
4429 const fs_builder ubld
= bld
.exec_all().group(8, 0);
4430 fs_reg src_payload
= ubld
.vgrf(BRW_REGISTER_TYPE_UD
);
4431 fs_reg ret_payload
= ubld
.vgrf(BRW_REGISTER_TYPE_UD
, 4);
4434 ubld
.MOV(src_payload
, brw_imm_d(0));
4436 const unsigned index
= prog_data
->binding_table
.ssbo_start
+ ssbo_index
;
4437 fs_inst
*inst
= ubld
.emit(SHADER_OPCODE_GET_BUFFER_SIZE
, ret_payload
,
4438 src_payload
, brw_imm_ud(index
));
4439 inst
->header_size
= 0;
4441 inst
->size_written
= 4 * REG_SIZE
;
4443 /* SKL PRM, vol07, 3D Media GPGPU Engine, Bounds Checking and Faulting:
4445 * "Out-of-bounds checking is always performed at a DWord granularity. If
4446 * any part of the DWord is out-of-bounds then the whole DWord is
4447 * considered out-of-bounds."
4449 * This implies that types with size smaller than 4-bytes need to be
4450 * padded if they don't complete the last dword of the buffer. But as we
4451 * need to maintain the original size we need to reverse the padding
4452 * calculation to return the correct size to know the number of elements
4453 * of an unsized array. As we stored in the last two bits of the surface
4454 * size the needed padding for the buffer, we calculate here the
4455 * original buffer_size reversing the surface_size calculation:
4457 * surface_size = isl_align(buffer_size, 4) +
4458 * (isl_align(buffer_size) - buffer_size)
4460 * buffer_size = surface_size & ~3 - surface_size & 3
4463 fs_reg size_aligned4
= ubld
.vgrf(BRW_REGISTER_TYPE_UD
);
4464 fs_reg size_padding
= ubld
.vgrf(BRW_REGISTER_TYPE_UD
);
4465 fs_reg buffer_size
= ubld
.vgrf(BRW_REGISTER_TYPE_UD
);
4467 ubld
.AND(size_padding
, ret_payload
, brw_imm_ud(3));
4468 ubld
.AND(size_aligned4
, ret_payload
, brw_imm_ud(~3));
4469 ubld
.ADD(buffer_size
, size_aligned4
, negate(size_padding
));
4471 bld
.MOV(retype(dest
, ret_payload
.type
), component(buffer_size
, 0));
4473 brw_mark_surface_used(prog_data
, index
);
4477 case nir_intrinsic_load_subgroup_invocation
:
4478 bld
.MOV(retype(dest
, BRW_REGISTER_TYPE_D
),
4479 nir_system_values
[SYSTEM_VALUE_SUBGROUP_INVOCATION
]);
4482 case nir_intrinsic_load_subgroup_eq_mask
:
4483 case nir_intrinsic_load_subgroup_ge_mask
:
4484 case nir_intrinsic_load_subgroup_gt_mask
:
4485 case nir_intrinsic_load_subgroup_le_mask
:
4486 case nir_intrinsic_load_subgroup_lt_mask
:
4487 unreachable("not reached");
4489 case nir_intrinsic_vote_any
: {
4490 const fs_builder ubld
= bld
.exec_all().group(1, 0);
4492 /* The any/all predicates do not consider channel enables. To prevent
4493 * dead channels from affecting the result, we initialize the flag with
4494 * with the identity value for the logical operation.
4496 if (dispatch_width
== 32) {
4497 /* For SIMD32, we use a UD type so we fill both f0.0 and f0.1. */
4498 ubld
.MOV(retype(brw_flag_reg(0, 0), BRW_REGISTER_TYPE_UD
),
4501 ubld
.MOV(brw_flag_reg(0, 0), brw_imm_uw(0));
4503 bld
.CMP(bld
.null_reg_d(), get_nir_src(instr
->src
[0]), brw_imm_d(0), BRW_CONDITIONAL_NZ
);
4505 /* For some reason, the any/all predicates don't work properly with
4506 * SIMD32. In particular, it appears that a SEL with a QtrCtrl of 2H
4507 * doesn't read the correct subset of the flag register and you end up
4508 * getting garbage in the second half. Work around this by using a pair
4509 * of 1-wide MOVs and scattering the result.
4511 fs_reg res1
= ubld
.vgrf(BRW_REGISTER_TYPE_D
);
4512 ubld
.MOV(res1
, brw_imm_d(0));
4513 set_predicate(dispatch_width
== 8 ? BRW_PREDICATE_ALIGN1_ANY8H
:
4514 dispatch_width
== 16 ? BRW_PREDICATE_ALIGN1_ANY16H
:
4515 BRW_PREDICATE_ALIGN1_ANY32H
,
4516 ubld
.MOV(res1
, brw_imm_d(-1)));
4518 bld
.MOV(retype(dest
, BRW_REGISTER_TYPE_D
), component(res1
, 0));
4521 case nir_intrinsic_vote_all
: {
4522 const fs_builder ubld
= bld
.exec_all().group(1, 0);
4524 /* The any/all predicates do not consider channel enables. To prevent
4525 * dead channels from affecting the result, we initialize the flag with
4526 * with the identity value for the logical operation.
4528 if (dispatch_width
== 32) {
4529 /* For SIMD32, we use a UD type so we fill both f0.0 and f0.1. */
4530 ubld
.MOV(retype(brw_flag_reg(0, 0), BRW_REGISTER_TYPE_UD
),
4531 brw_imm_ud(0xffffffff));
4533 ubld
.MOV(brw_flag_reg(0, 0), brw_imm_uw(0xffff));
4535 bld
.CMP(bld
.null_reg_d(), get_nir_src(instr
->src
[0]), brw_imm_d(0), BRW_CONDITIONAL_NZ
);
4537 /* For some reason, the any/all predicates don't work properly with
4538 * SIMD32. In particular, it appears that a SEL with a QtrCtrl of 2H
4539 * doesn't read the correct subset of the flag register and you end up
4540 * getting garbage in the second half. Work around this by using a pair
4541 * of 1-wide MOVs and scattering the result.
4543 fs_reg res1
= ubld
.vgrf(BRW_REGISTER_TYPE_D
);
4544 ubld
.MOV(res1
, brw_imm_d(0));
4545 set_predicate(dispatch_width
== 8 ? BRW_PREDICATE_ALIGN1_ALL8H
:
4546 dispatch_width
== 16 ? BRW_PREDICATE_ALIGN1_ALL16H
:
4547 BRW_PREDICATE_ALIGN1_ALL32H
,
4548 ubld
.MOV(res1
, brw_imm_d(-1)));
4550 bld
.MOV(retype(dest
, BRW_REGISTER_TYPE_D
), component(res1
, 0));
4553 case nir_intrinsic_vote_feq
:
4554 case nir_intrinsic_vote_ieq
: {
4555 fs_reg value
= get_nir_src(instr
->src
[0]);
4556 if (instr
->intrinsic
== nir_intrinsic_vote_feq
) {
4557 const unsigned bit_size
= nir_src_bit_size(instr
->src
[0]);
4558 value
.type
= brw_reg_type_from_bit_size(bit_size
, BRW_REGISTER_TYPE_F
);
4561 fs_reg uniformized
= bld
.emit_uniformize(value
);
4562 const fs_builder ubld
= bld
.exec_all().group(1, 0);
4564 /* The any/all predicates do not consider channel enables. To prevent
4565 * dead channels from affecting the result, we initialize the flag with
4566 * with the identity value for the logical operation.
4568 if (dispatch_width
== 32) {
4569 /* For SIMD32, we use a UD type so we fill both f0.0 and f0.1. */
4570 ubld
.MOV(retype(brw_flag_reg(0, 0), BRW_REGISTER_TYPE_UD
),
4571 brw_imm_ud(0xffffffff));
4573 ubld
.MOV(brw_flag_reg(0, 0), brw_imm_uw(0xffff));
4575 bld
.CMP(bld
.null_reg_d(), value
, uniformized
, BRW_CONDITIONAL_Z
);
4577 /* For some reason, the any/all predicates don't work properly with
4578 * SIMD32. In particular, it appears that a SEL with a QtrCtrl of 2H
4579 * doesn't read the correct subset of the flag register and you end up
4580 * getting garbage in the second half. Work around this by using a pair
4581 * of 1-wide MOVs and scattering the result.
4583 fs_reg res1
= ubld
.vgrf(BRW_REGISTER_TYPE_D
);
4584 ubld
.MOV(res1
, brw_imm_d(0));
4585 set_predicate(dispatch_width
== 8 ? BRW_PREDICATE_ALIGN1_ALL8H
:
4586 dispatch_width
== 16 ? BRW_PREDICATE_ALIGN1_ALL16H
:
4587 BRW_PREDICATE_ALIGN1_ALL32H
,
4588 ubld
.MOV(res1
, brw_imm_d(-1)));
4590 bld
.MOV(retype(dest
, BRW_REGISTER_TYPE_D
), component(res1
, 0));
4594 case nir_intrinsic_ballot
: {
4595 const fs_reg value
= retype(get_nir_src(instr
->src
[0]),
4596 BRW_REGISTER_TYPE_UD
);
4597 struct brw_reg flag
= brw_flag_reg(0, 0);
4598 /* FIXME: For SIMD32 programs, this causes us to stomp on f0.1 as well
4599 * as f0.0. This is a problem for fragment programs as we currently use
4600 * f0.1 for discards. Fortunately, we don't support SIMD32 fragment
4601 * programs yet so this isn't a problem. When we do, something will
4604 if (dispatch_width
== 32)
4605 flag
.type
= BRW_REGISTER_TYPE_UD
;
4607 bld
.exec_all().group(1, 0).MOV(flag
, brw_imm_ud(0u));
4608 bld
.CMP(bld
.null_reg_ud(), value
, brw_imm_ud(0u), BRW_CONDITIONAL_NZ
);
4610 if (instr
->dest
.ssa
.bit_size
> 32) {
4611 dest
.type
= BRW_REGISTER_TYPE_UQ
;
4613 dest
.type
= BRW_REGISTER_TYPE_UD
;
4615 bld
.MOV(dest
, flag
);
4619 case nir_intrinsic_read_invocation
: {
4620 const fs_reg value
= get_nir_src(instr
->src
[0]);
4621 const fs_reg invocation
= get_nir_src(instr
->src
[1]);
4622 fs_reg tmp
= bld
.vgrf(value
.type
);
4624 bld
.exec_all().emit(SHADER_OPCODE_BROADCAST
, tmp
, value
,
4625 bld
.emit_uniformize(invocation
));
4627 bld
.MOV(retype(dest
, value
.type
), fs_reg(component(tmp
, 0)));
4631 case nir_intrinsic_read_first_invocation
: {
4632 const fs_reg value
= get_nir_src(instr
->src
[0]);
4633 bld
.MOV(retype(dest
, value
.type
), bld
.emit_uniformize(value
));
4637 case nir_intrinsic_shuffle
: {
4638 const fs_reg value
= get_nir_src(instr
->src
[0]);
4639 const fs_reg index
= get_nir_src(instr
->src
[1]);
4641 bld
.emit(SHADER_OPCODE_SHUFFLE
, retype(dest
, value
.type
), value
, index
);
4645 case nir_intrinsic_first_invocation
: {
4646 fs_reg tmp
= bld
.vgrf(BRW_REGISTER_TYPE_UD
);
4647 bld
.exec_all().emit(SHADER_OPCODE_FIND_LIVE_CHANNEL
, tmp
);
4648 bld
.MOV(retype(dest
, BRW_REGISTER_TYPE_UD
),
4649 fs_reg(component(tmp
, 0)));
4653 case nir_intrinsic_quad_broadcast
: {
4654 const fs_reg value
= get_nir_src(instr
->src
[0]);
4655 nir_const_value
*index
= nir_src_as_const_value(instr
->src
[1]);
4656 assert(nir_src_bit_size(instr
->src
[1]) == 32);
4658 bld
.emit(SHADER_OPCODE_CLUSTER_BROADCAST
, retype(dest
, value
.type
),
4659 value
, brw_imm_ud(index
->u32
[0]), brw_imm_ud(4));
4663 case nir_intrinsic_quad_swap_horizontal
: {
4664 const fs_reg value
= get_nir_src(instr
->src
[0]);
4665 const fs_reg tmp
= bld
.vgrf(value
.type
);
4666 const fs_builder ubld
= bld
.exec_all().group(dispatch_width
/ 2, 0);
4668 const fs_reg src_left
= horiz_stride(value
, 2);
4669 const fs_reg src_right
= horiz_stride(horiz_offset(value
, 1), 2);
4670 const fs_reg tmp_left
= horiz_stride(tmp
, 2);
4671 const fs_reg tmp_right
= horiz_stride(horiz_offset(tmp
, 1), 2);
4673 /* From the Cherryview PRM Vol. 7, "Register Region Restrictiosn":
4675 * "When source or destination datatype is 64b or operation is
4676 * integer DWord multiply, regioning in Align1 must follow
4681 * 3. Source and Destination offset must be the same, except
4682 * the case of scalar source."
4684 * In order to work around this, we have to emit two 32-bit MOVs instead
4685 * of a single 64-bit MOV to do the shuffle.
4687 if (type_sz(value
.type
) > 4 &&
4688 (devinfo
->is_cherryview
|| gen_device_info_is_9lp(devinfo
))) {
4689 ubld
.MOV(subscript(tmp_left
, BRW_REGISTER_TYPE_D
, 0),
4690 subscript(src_right
, BRW_REGISTER_TYPE_D
, 0));
4691 ubld
.MOV(subscript(tmp_left
, BRW_REGISTER_TYPE_D
, 1),
4692 subscript(src_right
, BRW_REGISTER_TYPE_D
, 1));
4693 ubld
.MOV(subscript(tmp_right
, BRW_REGISTER_TYPE_D
, 0),
4694 subscript(src_left
, BRW_REGISTER_TYPE_D
, 0));
4695 ubld
.MOV(subscript(tmp_right
, BRW_REGISTER_TYPE_D
, 1),
4696 subscript(src_left
, BRW_REGISTER_TYPE_D
, 1));
4698 ubld
.MOV(tmp_left
, src_right
);
4699 ubld
.MOV(tmp_right
, src_left
);
4701 bld
.MOV(retype(dest
, value
.type
), tmp
);
4705 case nir_intrinsic_quad_swap_vertical
: {
4706 const fs_reg value
= get_nir_src(instr
->src
[0]);
4707 if (nir_src_bit_size(instr
->src
[0]) == 32) {
4708 /* For 32-bit, we can use a SIMD4x2 instruction to do this easily */
4709 const fs_reg tmp
= bld
.vgrf(value
.type
);
4710 const fs_builder ubld
= bld
.exec_all();
4711 ubld
.emit(SHADER_OPCODE_QUAD_SWIZZLE
, tmp
, value
,
4712 brw_imm_ud(BRW_SWIZZLE4(2,3,0,1)));
4713 bld
.MOV(retype(dest
, value
.type
), tmp
);
4715 /* For larger data types, we have to either emit dispatch_width many
4716 * MOVs or else fall back to doing indirects.
4718 fs_reg idx
= bld
.vgrf(BRW_REGISTER_TYPE_W
);
4719 bld
.XOR(idx
, nir_system_values
[SYSTEM_VALUE_SUBGROUP_INVOCATION
],
4721 bld
.emit(SHADER_OPCODE_SHUFFLE
, retype(dest
, value
.type
), value
, idx
);
4726 case nir_intrinsic_quad_swap_diagonal
: {
4727 const fs_reg value
= get_nir_src(instr
->src
[0]);
4728 if (nir_src_bit_size(instr
->src
[0]) == 32) {
4729 /* For 32-bit, we can use a SIMD4x2 instruction to do this easily */
4730 const fs_reg tmp
= bld
.vgrf(value
.type
);
4731 const fs_builder ubld
= bld
.exec_all();
4732 ubld
.emit(SHADER_OPCODE_QUAD_SWIZZLE
, tmp
, value
,
4733 brw_imm_ud(BRW_SWIZZLE4(3,2,1,0)));
4734 bld
.MOV(retype(dest
, value
.type
), tmp
);
4736 /* For larger data types, we have to either emit dispatch_width many
4737 * MOVs or else fall back to doing indirects.
4739 fs_reg idx
= bld
.vgrf(BRW_REGISTER_TYPE_W
);
4740 bld
.XOR(idx
, nir_system_values
[SYSTEM_VALUE_SUBGROUP_INVOCATION
],
4742 bld
.emit(SHADER_OPCODE_SHUFFLE
, retype(dest
, value
.type
), value
, idx
);
4747 case nir_intrinsic_reduce
: {
4748 fs_reg src
= get_nir_src(instr
->src
[0]);
4749 nir_op redop
= (nir_op
)nir_intrinsic_reduction_op(instr
);
4750 unsigned cluster_size
= nir_intrinsic_cluster_size(instr
);
4751 if (cluster_size
== 0 || cluster_size
> dispatch_width
)
4752 cluster_size
= dispatch_width
;
4754 /* Figure out the source type */
4755 src
.type
= brw_type_for_nir_type(devinfo
,
4756 (nir_alu_type
)(nir_op_infos
[redop
].input_types
[0] |
4757 nir_src_bit_size(instr
->src
[0])));
4759 fs_reg identity
= brw_nir_reduction_op_identity(bld
, redop
, src
.type
);
4760 opcode brw_op
= brw_op_for_nir_reduction_op(redop
);
4761 brw_conditional_mod cond_mod
= brw_cond_mod_for_nir_reduction_op(redop
);
4763 /* Set up a register for all of our scratching around and initialize it
4764 * to reduction operation's identity value.
4766 fs_reg scan
= bld
.vgrf(src
.type
);
4767 bld
.exec_all().emit(SHADER_OPCODE_SEL_EXEC
, scan
, src
, identity
);
4769 bld
.emit_scan(brw_op
, scan
, cluster_size
, cond_mod
);
4771 dest
.type
= src
.type
;
4772 if (cluster_size
* type_sz(src
.type
) >= REG_SIZE
* 2) {
4773 /* In this case, CLUSTER_BROADCAST instruction isn't needed because
4774 * the distance between clusters is at least 2 GRFs. In this case,
4775 * we don't need the weird striding of the CLUSTER_BROADCAST
4776 * instruction and can just do regular MOVs.
4778 assert((cluster_size
* type_sz(src
.type
)) % (REG_SIZE
* 2) == 0);
4779 const unsigned groups
=
4780 (dispatch_width
* type_sz(src
.type
)) / (REG_SIZE
* 2);
4781 const unsigned group_size
= dispatch_width
/ groups
;
4782 for (unsigned i
= 0; i
< groups
; i
++) {
4783 const unsigned cluster
= (i
* group_size
) / cluster_size
;
4784 const unsigned comp
= cluster
* cluster_size
+ (cluster_size
- 1);
4785 bld
.group(group_size
, i
).MOV(horiz_offset(dest
, i
* group_size
),
4786 component(scan
, comp
));
4789 bld
.emit(SHADER_OPCODE_CLUSTER_BROADCAST
, dest
, scan
,
4790 brw_imm_ud(cluster_size
- 1), brw_imm_ud(cluster_size
));
4795 case nir_intrinsic_inclusive_scan
:
4796 case nir_intrinsic_exclusive_scan
: {
4797 fs_reg src
= get_nir_src(instr
->src
[0]);
4798 nir_op redop
= (nir_op
)nir_intrinsic_reduction_op(instr
);
4800 /* Figure out the source type */
4801 src
.type
= brw_type_for_nir_type(devinfo
,
4802 (nir_alu_type
)(nir_op_infos
[redop
].input_types
[0] |
4803 nir_src_bit_size(instr
->src
[0])));
4805 fs_reg identity
= brw_nir_reduction_op_identity(bld
, redop
, src
.type
);
4806 opcode brw_op
= brw_op_for_nir_reduction_op(redop
);
4807 brw_conditional_mod cond_mod
= brw_cond_mod_for_nir_reduction_op(redop
);
4809 /* Set up a register for all of our scratching around and initialize it
4810 * to reduction operation's identity value.
4812 fs_reg scan
= bld
.vgrf(src
.type
);
4813 const fs_builder allbld
= bld
.exec_all();
4814 allbld
.emit(SHADER_OPCODE_SEL_EXEC
, scan
, src
, identity
);
4816 if (instr
->intrinsic
== nir_intrinsic_exclusive_scan
) {
4817 /* Exclusive scan is a bit harder because we have to do an annoying
4818 * shift of the contents before we can begin. To make things worse,
4819 * we can't do this with a normal stride; we have to use indirects.
4821 fs_reg shifted
= bld
.vgrf(src
.type
);
4822 fs_reg idx
= bld
.vgrf(BRW_REGISTER_TYPE_W
);
4823 allbld
.ADD(idx
, nir_system_values
[SYSTEM_VALUE_SUBGROUP_INVOCATION
],
4825 allbld
.emit(SHADER_OPCODE_SHUFFLE
, shifted
, scan
, idx
);
4826 allbld
.group(1, 0).MOV(component(shifted
, 0), identity
);
4830 bld
.emit_scan(brw_op
, scan
, dispatch_width
, cond_mod
);
4832 bld
.MOV(retype(dest
, src
.type
), scan
);
4837 unreachable("unknown intrinsic");
4842 fs_visitor::nir_emit_ssbo_atomic(const fs_builder
&bld
,
4843 int op
, nir_intrinsic_instr
*instr
)
4845 if (stage
== MESA_SHADER_FRAGMENT
)
4846 brw_wm_prog_data(prog_data
)->has_side_effects
= true;
4849 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
4850 dest
= get_nir_dest(instr
->dest
);
4853 nir_const_value
*const_surface
= nir_src_as_const_value(instr
->src
[0]);
4854 if (const_surface
) {
4855 unsigned surf_index
= stage_prog_data
->binding_table
.ssbo_start
+
4856 const_surface
->u32
[0];
4857 surface
= brw_imm_ud(surf_index
);
4858 brw_mark_surface_used(prog_data
, surf_index
);
4860 surface
= vgrf(glsl_type::uint_type
);
4861 bld
.ADD(surface
, get_nir_src(instr
->src
[0]),
4862 brw_imm_ud(stage_prog_data
->binding_table
.ssbo_start
));
4864 /* Assume this may touch any SSBO. This is the same we do for other
4865 * UBO/SSBO accesses with non-constant surface.
4867 brw_mark_surface_used(prog_data
,
4868 stage_prog_data
->binding_table
.ssbo_start
+
4869 nir
->info
.num_ssbos
- 1);
4872 fs_reg offset
= get_nir_src(instr
->src
[1]);
4873 fs_reg data1
= get_nir_src(instr
->src
[2]);
4875 if (op
== BRW_AOP_CMPWR
)
4876 data2
= get_nir_src(instr
->src
[3]);
4878 /* Emit the actual atomic operation */
4880 fs_reg atomic_result
= emit_untyped_atomic(bld
, surface
, offset
,
4882 1 /* dims */, 1 /* rsize */,
4884 BRW_PREDICATE_NONE
);
4885 dest
.type
= atomic_result
.type
;
4886 bld
.MOV(dest
, atomic_result
);
4890 fs_visitor::nir_emit_shared_atomic(const fs_builder
&bld
,
4891 int op
, nir_intrinsic_instr
*instr
)
4894 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
4895 dest
= get_nir_dest(instr
->dest
);
4897 fs_reg surface
= brw_imm_ud(GEN7_BTI_SLM
);
4899 fs_reg data1
= get_nir_src(instr
->src
[1]);
4901 if (op
== BRW_AOP_CMPWR
)
4902 data2
= get_nir_src(instr
->src
[2]);
4904 /* Get the offset */
4905 nir_const_value
*const_offset
= nir_src_as_const_value(instr
->src
[0]);
4907 offset
= brw_imm_ud(instr
->const_index
[0] + const_offset
->u32
[0]);
4909 offset
= vgrf(glsl_type::uint_type
);
4911 retype(get_nir_src(instr
->src
[0]), BRW_REGISTER_TYPE_UD
),
4912 brw_imm_ud(instr
->const_index
[0]));
4915 /* Emit the actual atomic operation operation */
4917 fs_reg atomic_result
= emit_untyped_atomic(bld
, surface
, offset
,
4919 1 /* dims */, 1 /* rsize */,
4921 BRW_PREDICATE_NONE
);
4922 dest
.type
= atomic_result
.type
;
4923 bld
.MOV(dest
, atomic_result
);
4927 fs_visitor::nir_emit_texture(const fs_builder
&bld
, nir_tex_instr
*instr
)
4929 unsigned texture
= instr
->texture_index
;
4930 unsigned sampler
= instr
->sampler_index
;
4932 fs_reg srcs
[TEX_LOGICAL_NUM_SRCS
];
4934 srcs
[TEX_LOGICAL_SRC_SURFACE
] = brw_imm_ud(texture
);
4935 srcs
[TEX_LOGICAL_SRC_SAMPLER
] = brw_imm_ud(sampler
);
4937 int lod_components
= 0;
4939 /* The hardware requires a LOD for buffer textures */
4940 if (instr
->sampler_dim
== GLSL_SAMPLER_DIM_BUF
)
4941 srcs
[TEX_LOGICAL_SRC_LOD
] = brw_imm_d(0);
4943 uint32_t header_bits
= 0;
4944 for (unsigned i
= 0; i
< instr
->num_srcs
; i
++) {
4945 fs_reg src
= get_nir_src(instr
->src
[i
].src
);
4946 switch (instr
->src
[i
].src_type
) {
4947 case nir_tex_src_bias
:
4948 srcs
[TEX_LOGICAL_SRC_LOD
] =
4949 retype(get_nir_src_imm(instr
->src
[i
].src
), BRW_REGISTER_TYPE_F
);
4951 case nir_tex_src_comparator
:
4952 srcs
[TEX_LOGICAL_SRC_SHADOW_C
] = retype(src
, BRW_REGISTER_TYPE_F
);
4954 case nir_tex_src_coord
:
4955 switch (instr
->op
) {
4957 case nir_texop_txf_ms
:
4958 case nir_texop_txf_ms_mcs
:
4959 case nir_texop_samples_identical
:
4960 srcs
[TEX_LOGICAL_SRC_COORDINATE
] = retype(src
, BRW_REGISTER_TYPE_D
);
4963 srcs
[TEX_LOGICAL_SRC_COORDINATE
] = retype(src
, BRW_REGISTER_TYPE_F
);
4967 case nir_tex_src_ddx
:
4968 srcs
[TEX_LOGICAL_SRC_LOD
] = retype(src
, BRW_REGISTER_TYPE_F
);
4969 lod_components
= nir_tex_instr_src_size(instr
, i
);
4971 case nir_tex_src_ddy
:
4972 srcs
[TEX_LOGICAL_SRC_LOD2
] = retype(src
, BRW_REGISTER_TYPE_F
);
4974 case nir_tex_src_lod
:
4975 switch (instr
->op
) {
4977 srcs
[TEX_LOGICAL_SRC_LOD
] =
4978 retype(get_nir_src_imm(instr
->src
[i
].src
), BRW_REGISTER_TYPE_UD
);
4981 srcs
[TEX_LOGICAL_SRC_LOD
] =
4982 retype(get_nir_src_imm(instr
->src
[i
].src
), BRW_REGISTER_TYPE_D
);
4985 srcs
[TEX_LOGICAL_SRC_LOD
] =
4986 retype(get_nir_src_imm(instr
->src
[i
].src
), BRW_REGISTER_TYPE_F
);
4990 case nir_tex_src_ms_index
:
4991 srcs
[TEX_LOGICAL_SRC_SAMPLE_INDEX
] = retype(src
, BRW_REGISTER_TYPE_UD
);
4994 case nir_tex_src_offset
: {
4995 nir_const_value
*const_offset
=
4996 nir_src_as_const_value(instr
->src
[i
].src
);
4997 unsigned offset_bits
= 0;
4999 brw_texture_offset(const_offset
->i32
,
5000 nir_tex_instr_src_size(instr
, i
),
5002 header_bits
|= offset_bits
;
5004 srcs
[TEX_LOGICAL_SRC_TG4_OFFSET
] =
5005 retype(src
, BRW_REGISTER_TYPE_D
);
5010 case nir_tex_src_projector
:
5011 unreachable("should be lowered");
5013 case nir_tex_src_texture_offset
: {
5014 /* Figure out the highest possible texture index and mark it as used */
5015 uint32_t max_used
= texture
+ instr
->texture_array_size
- 1;
5016 if (instr
->op
== nir_texop_tg4
&& devinfo
->gen
< 8) {
5017 max_used
+= stage_prog_data
->binding_table
.gather_texture_start
;
5019 max_used
+= stage_prog_data
->binding_table
.texture_start
;
5021 brw_mark_surface_used(prog_data
, max_used
);
5023 /* Emit code to evaluate the actual indexing expression */
5024 fs_reg tmp
= vgrf(glsl_type::uint_type
);
5025 bld
.ADD(tmp
, src
, brw_imm_ud(texture
));
5026 srcs
[TEX_LOGICAL_SRC_SURFACE
] = bld
.emit_uniformize(tmp
);
5030 case nir_tex_src_sampler_offset
: {
5031 /* Emit code to evaluate the actual indexing expression */
5032 fs_reg tmp
= vgrf(glsl_type::uint_type
);
5033 bld
.ADD(tmp
, src
, brw_imm_ud(sampler
));
5034 srcs
[TEX_LOGICAL_SRC_SAMPLER
] = bld
.emit_uniformize(tmp
);
5038 case nir_tex_src_ms_mcs
:
5039 assert(instr
->op
== nir_texop_txf_ms
);
5040 srcs
[TEX_LOGICAL_SRC_MCS
] = retype(src
, BRW_REGISTER_TYPE_D
);
5043 case nir_tex_src_plane
: {
5044 nir_const_value
*const_plane
=
5045 nir_src_as_const_value(instr
->src
[i
].src
);
5046 const uint32_t plane
= const_plane
->u32
[0];
5047 const uint32_t texture_index
=
5048 instr
->texture_index
+
5049 stage_prog_data
->binding_table
.plane_start
[plane
] -
5050 stage_prog_data
->binding_table
.texture_start
;
5052 srcs
[TEX_LOGICAL_SRC_SURFACE
] = brw_imm_ud(texture_index
);
5057 unreachable("unknown texture source");
5061 if (srcs
[TEX_LOGICAL_SRC_MCS
].file
== BAD_FILE
&&
5062 (instr
->op
== nir_texop_txf_ms
||
5063 instr
->op
== nir_texop_samples_identical
)) {
5064 if (devinfo
->gen
>= 7 &&
5065 key_tex
->compressed_multisample_layout_mask
& (1 << texture
)) {
5066 srcs
[TEX_LOGICAL_SRC_MCS
] =
5067 emit_mcs_fetch(srcs
[TEX_LOGICAL_SRC_COORDINATE
],
5068 instr
->coord_components
,
5069 srcs
[TEX_LOGICAL_SRC_SURFACE
]);
5071 srcs
[TEX_LOGICAL_SRC_MCS
] = brw_imm_ud(0u);
5075 srcs
[TEX_LOGICAL_SRC_COORD_COMPONENTS
] = brw_imm_d(instr
->coord_components
);
5076 srcs
[TEX_LOGICAL_SRC_GRAD_COMPONENTS
] = brw_imm_d(lod_components
);
5079 switch (instr
->op
) {
5081 opcode
= (stage
== MESA_SHADER_FRAGMENT
? SHADER_OPCODE_TEX_LOGICAL
:
5082 SHADER_OPCODE_TXL_LOGICAL
);
5085 opcode
= FS_OPCODE_TXB_LOGICAL
;
5088 opcode
= SHADER_OPCODE_TXL_LOGICAL
;
5091 opcode
= SHADER_OPCODE_TXD_LOGICAL
;
5094 opcode
= SHADER_OPCODE_TXF_LOGICAL
;
5096 case nir_texop_txf_ms
:
5097 if ((key_tex
->msaa_16
& (1 << sampler
)))
5098 opcode
= SHADER_OPCODE_TXF_CMS_W_LOGICAL
;
5100 opcode
= SHADER_OPCODE_TXF_CMS_LOGICAL
;
5102 case nir_texop_txf_ms_mcs
:
5103 opcode
= SHADER_OPCODE_TXF_MCS_LOGICAL
;
5105 case nir_texop_query_levels
:
5107 opcode
= SHADER_OPCODE_TXS_LOGICAL
;
5110 opcode
= SHADER_OPCODE_LOD_LOGICAL
;
5113 if (srcs
[TEX_LOGICAL_SRC_TG4_OFFSET
].file
!= BAD_FILE
)
5114 opcode
= SHADER_OPCODE_TG4_OFFSET_LOGICAL
;
5116 opcode
= SHADER_OPCODE_TG4_LOGICAL
;
5118 case nir_texop_texture_samples
:
5119 opcode
= SHADER_OPCODE_SAMPLEINFO_LOGICAL
;
5121 case nir_texop_samples_identical
: {
5122 fs_reg dst
= retype(get_nir_dest(instr
->dest
), BRW_REGISTER_TYPE_D
);
5124 /* If mcs is an immediate value, it means there is no MCS. In that case
5125 * just return false.
5127 if (srcs
[TEX_LOGICAL_SRC_MCS
].file
== BRW_IMMEDIATE_VALUE
) {
5128 bld
.MOV(dst
, brw_imm_ud(0u));
5129 } else if ((key_tex
->msaa_16
& (1 << sampler
))) {
5130 fs_reg tmp
= vgrf(glsl_type::uint_type
);
5131 bld
.OR(tmp
, srcs
[TEX_LOGICAL_SRC_MCS
],
5132 offset(srcs
[TEX_LOGICAL_SRC_MCS
], bld
, 1));
5133 bld
.CMP(dst
, tmp
, brw_imm_ud(0u), BRW_CONDITIONAL_EQ
);
5135 bld
.CMP(dst
, srcs
[TEX_LOGICAL_SRC_MCS
], brw_imm_ud(0u),
5136 BRW_CONDITIONAL_EQ
);
5141 unreachable("unknown texture opcode");
5144 if (instr
->op
== nir_texop_tg4
) {
5145 if (instr
->component
== 1 &&
5146 key_tex
->gather_channel_quirk_mask
& (1 << texture
)) {
5147 /* gather4 sampler is broken for green channel on RG32F --
5148 * we must ask for blue instead.
5150 header_bits
|= 2 << 16;
5152 header_bits
|= instr
->component
<< 16;
5156 fs_reg dst
= bld
.vgrf(brw_type_for_nir_type(devinfo
, instr
->dest_type
), 4);
5157 fs_inst
*inst
= bld
.emit(opcode
, dst
, srcs
, ARRAY_SIZE(srcs
));
5158 inst
->offset
= header_bits
;
5160 const unsigned dest_size
= nir_tex_instr_dest_size(instr
);
5161 if (devinfo
->gen
>= 9 &&
5162 instr
->op
!= nir_texop_tg4
&& instr
->op
!= nir_texop_query_levels
) {
5163 unsigned write_mask
= instr
->dest
.is_ssa
?
5164 nir_ssa_def_components_read(&instr
->dest
.ssa
):
5165 (1 << dest_size
) - 1;
5166 assert(write_mask
!= 0); /* dead code should have been eliminated */
5167 inst
->size_written
= util_last_bit(write_mask
) *
5168 inst
->dst
.component_size(inst
->exec_size
);
5170 inst
->size_written
= 4 * inst
->dst
.component_size(inst
->exec_size
);
5173 if (srcs
[TEX_LOGICAL_SRC_SHADOW_C
].file
!= BAD_FILE
)
5174 inst
->shadow_compare
= true;
5176 if (instr
->op
== nir_texop_tg4
&& devinfo
->gen
== 6)
5177 emit_gen6_gather_wa(key_tex
->gen6_gather_wa
[texture
], dst
);
5180 for (unsigned i
= 0; i
< dest_size
; i
++)
5181 nir_dest
[i
] = offset(dst
, bld
, i
);
5183 if (instr
->op
== nir_texop_query_levels
) {
5184 /* # levels is in .w */
5185 nir_dest
[0] = offset(dst
, bld
, 3);
5186 } else if (instr
->op
== nir_texop_txs
&&
5187 dest_size
>= 3 && devinfo
->gen
< 7) {
5188 /* Gen4-6 return 0 instead of 1 for single layer surfaces. */
5189 fs_reg depth
= offset(dst
, bld
, 2);
5190 nir_dest
[2] = vgrf(glsl_type::int_type
);
5191 bld
.emit_minmax(nir_dest
[2], depth
, brw_imm_d(1), BRW_CONDITIONAL_GE
);
5194 bld
.LOAD_PAYLOAD(get_nir_dest(instr
->dest
), nir_dest
, dest_size
, 0);
5198 fs_visitor::nir_emit_jump(const fs_builder
&bld
, nir_jump_instr
*instr
)
5200 switch (instr
->type
) {
5201 case nir_jump_break
:
5202 bld
.emit(BRW_OPCODE_BREAK
);
5204 case nir_jump_continue
:
5205 bld
.emit(BRW_OPCODE_CONTINUE
);
5207 case nir_jump_return
:
5209 unreachable("unknown jump");
5214 * This helper takes the result of a load operation that reads 32-bit elements
5222 * and shuffles the data to get this:
5229 * Which is exactly what we want if the load is reading 64-bit components
5230 * like doubles, where x represents the low 32-bit of the x double component
5231 * and y represents the high 32-bit of the x double component (likewise with
5232 * z and w for double component y). The parameter @components represents
5233 * the number of 64-bit components present in @src. This would typically be
5234 * 2 at most, since we can only fit 2 double elements in the result of a
5237 * Notice that @dst and @src can be the same register.
5240 shuffle_32bit_load_result_to_64bit_data(const fs_builder
&bld
,
5243 uint32_t components
)
5245 assert(type_sz(src
.type
) == 4);
5246 assert(type_sz(dst
.type
) == 8);
5248 /* A temporary that we will use to shuffle the 32-bit data of each
5249 * component in the vector into valid 64-bit data. We can't write directly
5250 * to dst because dst can be (and would usually be) the same as src
5251 * and in that case the first MOV in the loop below would overwrite the
5252 * data read in the second MOV.
5254 fs_reg tmp
= bld
.vgrf(dst
.type
);
5256 for (unsigned i
= 0; i
< components
; i
++) {
5257 const fs_reg component_i
= offset(src
, bld
, 2 * i
);
5259 bld
.MOV(subscript(tmp
, src
.type
, 0), component_i
);
5260 bld
.MOV(subscript(tmp
, src
.type
, 1), offset(component_i
, bld
, 1));
5262 bld
.MOV(offset(dst
, bld
, i
), tmp
);
5267 shuffle_32bit_load_result_to_16bit_data(const fs_builder
&bld
,
5270 uint32_t first_component
,
5271 uint32_t components
)
5273 assert(type_sz(src
.type
) == 4);
5274 assert(type_sz(dst
.type
) == 2);
5276 /* A temporary is used to un-shuffle the 32-bit data of each component in
5277 * into a valid 16-bit vector. We can't write directly to dst because it
5278 * can be the same register as src and in that case the first MOV in the
5279 * loop below would overwrite the data read in the second MOV.
5281 fs_reg tmp
= retype(bld
.vgrf(src
.type
), dst
.type
);
5283 for (unsigned i
= 0; i
< components
; i
++) {
5284 const fs_reg component_i
=
5285 subscript(offset(src
, bld
, (first_component
+ i
) / 2), dst
.type
,
5286 (first_component
+ i
) % 2);
5288 bld
.MOV(offset(tmp
, bld
, i
% 2), component_i
);
5291 bld
.MOV(offset(dst
, bld
, i
-1), offset(tmp
, bld
, 0));
5292 bld
.MOV(offset(dst
, bld
, i
), offset(tmp
, bld
, 1));
5295 if (components
% 2) {
5296 bld
.MOV(offset(dst
, bld
, components
- 1), tmp
);
5301 * This helper does the inverse operation of
5302 * SHUFFLE_32BIT_LOAD_RESULT_TO_64BIT_DATA.
5304 * We need to do this when we are going to use untyped write messsages that
5305 * operate with 32-bit components in order to arrange our 64-bit data to be
5306 * in the expected layout.
5308 * Notice that callers of this function, unlike in the case of the inverse
5309 * operation, would typically need to call this with dst and src being
5310 * different registers, since they would otherwise corrupt the original
5311 * 64-bit data they are about to write. Because of this the function checks
5312 * that the src and dst regions involved in the operation do not overlap.
5315 shuffle_64bit_data_for_32bit_write(const fs_builder
&bld
,
5317 uint32_t components
)
5319 assert(type_sz(src
.type
) == 8);
5321 fs_reg dst
= bld
.vgrf(BRW_REGISTER_TYPE_D
, 2 * components
);
5323 for (unsigned i
= 0; i
< components
; i
++) {
5324 const fs_reg component_i
= offset(src
, bld
, i
);
5325 bld
.MOV(offset(dst
, bld
, 2 * i
), subscript(component_i
, dst
.type
, 0));
5326 bld
.MOV(offset(dst
, bld
, 2 * i
+ 1), subscript(component_i
, dst
.type
, 1));
5333 shuffle_16bit_data_for_32bit_write(const fs_builder
&bld
,
5336 uint32_t components
)
5338 assert(type_sz(src
.type
) == 2);
5339 assert(type_sz(dst
.type
) == 4);
5341 /* A temporary is used to shuffle the 16-bit data of each component in the
5342 * 32-bit data vector. We can't write directly to dst because it can be the
5343 * same register as src and in that case the first MOV in the loop below
5344 * would overwrite the data read in the second MOV.
5346 fs_reg tmp
= bld
.vgrf(dst
.type
);
5348 for (unsigned i
= 0; i
< components
; i
++) {
5349 const fs_reg component_i
= offset(src
, bld
, i
);
5350 bld
.MOV(subscript(tmp
, src
.type
, i
% 2), component_i
);
5352 bld
.MOV(offset(dst
, bld
, i
/ 2), tmp
);
5355 if (components
% 2) {
5356 bld
.MOV(offset(dst
, bld
, components
/ 2), tmp
);
5361 setup_imm_df(const fs_builder
&bld
, double v
)
5363 const struct gen_device_info
*devinfo
= bld
.shader
->devinfo
;
5364 assert(devinfo
->gen
>= 7);
5366 if (devinfo
->gen
>= 8)
5367 return brw_imm_df(v
);
5369 /* gen7.5 does not support DF immediates straighforward but the DIM
5370 * instruction allows to set the 64-bit immediate value.
5372 if (devinfo
->is_haswell
) {
5373 const fs_builder ubld
= bld
.exec_all().group(1, 0);
5374 fs_reg dst
= ubld
.vgrf(BRW_REGISTER_TYPE_DF
, 1);
5375 ubld
.DIM(dst
, brw_imm_df(v
));
5376 return component(dst
, 0);
5379 /* gen7 does not support DF immediates, so we generate a 64-bit constant by
5380 * writing the low 32-bit of the constant to suboffset 0 of a VGRF and
5381 * the high 32-bit to suboffset 4 and then applying a stride of 0.
5383 * Alternatively, we could also produce a normal VGRF (without stride 0)
5384 * by writing to all the channels in the VGRF, however, that would hit the
5385 * gen7 bug where we have to split writes that span more than 1 register
5386 * into instructions with a width of 4 (otherwise the write to the second
5387 * register written runs into an execmask hardware bug) which isn't very
5400 const fs_builder ubld
= bld
.exec_all().group(1, 0);
5401 const fs_reg tmp
= ubld
.vgrf(BRW_REGISTER_TYPE_UD
, 2);
5402 ubld
.MOV(tmp
, brw_imm_ud(di
.i1
));
5403 ubld
.MOV(horiz_offset(tmp
, 1), brw_imm_ud(di
.i2
));
5405 return component(retype(tmp
, BRW_REGISTER_TYPE_DF
), 0);