2 * Copyright © 2010 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 #include "compiler/glsl/ir.h"
27 #include "nir_search_helpers.h"
28 #include "util/u_math.h"
29 #include "util/bitscan.h"
34 fs_visitor::emit_nir_code()
36 /* emit the arrays used for inputs and outputs - load/store intrinsics will
37 * be converted to reads/writes of these arrays
41 nir_emit_system_values();
43 nir_emit_impl(nir_shader_get_entrypoint((nir_shader
*)nir
));
47 fs_visitor::nir_setup_outputs()
49 if (stage
== MESA_SHADER_TESS_CTRL
|| stage
== MESA_SHADER_FRAGMENT
)
52 unsigned vec4s
[VARYING_SLOT_TESS_MAX
] = { 0, };
54 /* Calculate the size of output registers in a separate pass, before
55 * allocating them. With ARB_enhanced_layouts, multiple output variables
56 * may occupy the same slot, but have different type sizes.
58 nir_foreach_variable(var
, &nir
->outputs
) {
59 const int loc
= var
->data
.driver_location
;
60 const unsigned var_vec4s
=
61 var
->data
.compact
? DIV_ROUND_UP(glsl_get_length(var
->type
), 4)
62 : type_size_vec4(var
->type
, true);
63 vec4s
[loc
] = MAX2(vec4s
[loc
], var_vec4s
);
66 for (unsigned loc
= 0; loc
< ARRAY_SIZE(vec4s
);) {
67 if (vec4s
[loc
] == 0) {
72 unsigned reg_size
= vec4s
[loc
];
74 /* Check if there are any ranges that start within this range and extend
75 * past it. If so, include them in this allocation.
77 for (unsigned i
= 1; i
< reg_size
; i
++)
78 reg_size
= MAX2(vec4s
[i
+ loc
] + i
, reg_size
);
80 fs_reg reg
= bld
.vgrf(BRW_REGISTER_TYPE_F
, 4 * reg_size
);
81 for (unsigned i
= 0; i
< reg_size
; i
++)
82 outputs
[loc
+ i
] = offset(reg
, bld
, 4 * i
);
89 fs_visitor::nir_setup_uniforms()
91 /* Only the first compile gets to set up uniforms. */
92 if (push_constant_loc
) {
93 assert(pull_constant_loc
);
97 uniforms
= nir
->num_uniforms
/ 4;
99 if (stage
== MESA_SHADER_COMPUTE
) {
100 /* Add a uniform for the thread local id. It must be the last uniform
103 assert(uniforms
== prog_data
->nr_params
);
104 uint32_t *param
= brw_stage_prog_data_add_params(prog_data
, 1);
105 *param
= BRW_PARAM_BUILTIN_SUBGROUP_ID
;
106 subgroup_id
= fs_reg(UNIFORM
, uniforms
++, BRW_REGISTER_TYPE_UD
);
111 emit_system_values_block(nir_block
*block
, fs_visitor
*v
)
115 nir_foreach_instr(instr
, block
) {
116 if (instr
->type
!= nir_instr_type_intrinsic
)
119 nir_intrinsic_instr
*intrin
= nir_instr_as_intrinsic(instr
);
120 switch (intrin
->intrinsic
) {
121 case nir_intrinsic_load_vertex_id
:
122 case nir_intrinsic_load_base_vertex
:
123 unreachable("should be lowered by nir_lower_system_values().");
125 case nir_intrinsic_load_vertex_id_zero_base
:
126 case nir_intrinsic_load_is_indexed_draw
:
127 case nir_intrinsic_load_first_vertex
:
128 case nir_intrinsic_load_instance_id
:
129 case nir_intrinsic_load_base_instance
:
130 case nir_intrinsic_load_draw_id
:
131 unreachable("should be lowered by brw_nir_lower_vs_inputs().");
133 case nir_intrinsic_load_invocation_id
:
134 if (v
->stage
== MESA_SHADER_TESS_CTRL
)
136 assert(v
->stage
== MESA_SHADER_GEOMETRY
);
137 reg
= &v
->nir_system_values
[SYSTEM_VALUE_INVOCATION_ID
];
138 if (reg
->file
== BAD_FILE
) {
139 const fs_builder abld
= v
->bld
.annotate("gl_InvocationID", NULL
);
140 fs_reg
g1(retype(brw_vec8_grf(1, 0), BRW_REGISTER_TYPE_UD
));
141 fs_reg iid
= abld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
142 abld
.SHR(iid
, g1
, brw_imm_ud(27u));
147 case nir_intrinsic_load_sample_pos
:
148 assert(v
->stage
== MESA_SHADER_FRAGMENT
);
149 reg
= &v
->nir_system_values
[SYSTEM_VALUE_SAMPLE_POS
];
150 if (reg
->file
== BAD_FILE
)
151 *reg
= *v
->emit_samplepos_setup();
154 case nir_intrinsic_load_sample_id
:
155 assert(v
->stage
== MESA_SHADER_FRAGMENT
);
156 reg
= &v
->nir_system_values
[SYSTEM_VALUE_SAMPLE_ID
];
157 if (reg
->file
== BAD_FILE
)
158 *reg
= *v
->emit_sampleid_setup();
161 case nir_intrinsic_load_sample_mask_in
:
162 assert(v
->stage
== MESA_SHADER_FRAGMENT
);
163 assert(v
->devinfo
->gen
>= 7);
164 reg
= &v
->nir_system_values
[SYSTEM_VALUE_SAMPLE_MASK_IN
];
165 if (reg
->file
== BAD_FILE
)
166 *reg
= *v
->emit_samplemaskin_setup();
169 case nir_intrinsic_load_work_group_id
:
170 assert(v
->stage
== MESA_SHADER_COMPUTE
);
171 reg
= &v
->nir_system_values
[SYSTEM_VALUE_WORK_GROUP_ID
];
172 if (reg
->file
== BAD_FILE
)
173 *reg
= *v
->emit_cs_work_group_id_setup();
176 case nir_intrinsic_load_helper_invocation
:
177 assert(v
->stage
== MESA_SHADER_FRAGMENT
);
178 reg
= &v
->nir_system_values
[SYSTEM_VALUE_HELPER_INVOCATION
];
179 if (reg
->file
== BAD_FILE
) {
180 const fs_builder abld
=
181 v
->bld
.annotate("gl_HelperInvocation", NULL
);
183 /* On Gen6+ (gl_HelperInvocation is only exposed on Gen7+) the
184 * pixel mask is in g1.7 of the thread payload.
186 * We move the per-channel pixel enable bit to the low bit of each
187 * channel by shifting the byte containing the pixel mask by the
188 * vector immediate 0x76543210UV.
190 * The region of <1,8,0> reads only 1 byte (the pixel masks for
191 * subspans 0 and 1) in SIMD8 and an additional byte (the pixel
192 * masks for 2 and 3) in SIMD16.
194 fs_reg shifted
= abld
.vgrf(BRW_REGISTER_TYPE_UW
, 1);
196 for (unsigned i
= 0; i
< DIV_ROUND_UP(v
->dispatch_width
, 16); i
++) {
197 const fs_builder hbld
= abld
.group(MIN2(16, v
->dispatch_width
), i
);
198 hbld
.SHR(offset(shifted
, hbld
, i
),
199 stride(retype(brw_vec1_grf(1 + i
, 7),
200 BRW_REGISTER_TYPE_UB
),
202 brw_imm_v(0x76543210));
205 /* A set bit in the pixel mask means the channel is enabled, but
206 * that is the opposite of gl_HelperInvocation so we need to invert
209 * The negate source-modifier bit of logical instructions on Gen8+
210 * performs 1's complement negation, so we can use that instead of
213 fs_reg inverted
= negate(shifted
);
214 if (v
->devinfo
->gen
< 8) {
215 inverted
= abld
.vgrf(BRW_REGISTER_TYPE_UW
);
216 abld
.NOT(inverted
, shifted
);
219 /* We then resolve the 0/1 result to 0/~0 boolean values by ANDing
220 * with 1 and negating.
222 fs_reg anded
= abld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
223 abld
.AND(anded
, inverted
, brw_imm_uw(1));
225 fs_reg dst
= abld
.vgrf(BRW_REGISTER_TYPE_D
, 1);
226 abld
.MOV(dst
, negate(retype(anded
, BRW_REGISTER_TYPE_D
)));
240 fs_visitor::nir_emit_system_values()
242 nir_system_values
= ralloc_array(mem_ctx
, fs_reg
, SYSTEM_VALUE_MAX
);
243 for (unsigned i
= 0; i
< SYSTEM_VALUE_MAX
; i
++) {
244 nir_system_values
[i
] = fs_reg();
247 /* Always emit SUBGROUP_INVOCATION. Dead code will clean it up if we
248 * never end up using it.
251 const fs_builder abld
= bld
.annotate("gl_SubgroupInvocation", NULL
);
252 fs_reg
®
= nir_system_values
[SYSTEM_VALUE_SUBGROUP_INVOCATION
];
253 reg
= abld
.vgrf(BRW_REGISTER_TYPE_UW
);
255 const fs_builder allbld8
= abld
.group(8, 0).exec_all();
256 allbld8
.MOV(reg
, brw_imm_v(0x76543210));
257 if (dispatch_width
> 8)
258 allbld8
.ADD(byte_offset(reg
, 16), reg
, brw_imm_uw(8u));
259 if (dispatch_width
> 16) {
260 const fs_builder allbld16
= abld
.group(16, 0).exec_all();
261 allbld16
.ADD(byte_offset(reg
, 32), reg
, brw_imm_uw(16u));
265 nir_function_impl
*impl
= nir_shader_get_entrypoint((nir_shader
*)nir
);
266 nir_foreach_block(block
, impl
)
267 emit_system_values_block(block
, this);
271 * Returns a type based on a reference_type (word, float, half-float) and a
274 * Reference BRW_REGISTER_TYPE are HF,F,DF,W,D,UW,UD.
276 * @FIXME: 64-bit return types are always DF on integer types to maintain
277 * compability with uses of DF previously to the introduction of int64
281 brw_reg_type_from_bit_size(const unsigned bit_size
,
282 const brw_reg_type reference_type
)
284 switch(reference_type
) {
285 case BRW_REGISTER_TYPE_HF
:
286 case BRW_REGISTER_TYPE_F
:
287 case BRW_REGISTER_TYPE_DF
:
290 return BRW_REGISTER_TYPE_HF
;
292 return BRW_REGISTER_TYPE_F
;
294 return BRW_REGISTER_TYPE_DF
;
296 unreachable("Invalid bit size");
298 case BRW_REGISTER_TYPE_B
:
299 case BRW_REGISTER_TYPE_W
:
300 case BRW_REGISTER_TYPE_D
:
301 case BRW_REGISTER_TYPE_Q
:
304 return BRW_REGISTER_TYPE_B
;
306 return BRW_REGISTER_TYPE_W
;
308 return BRW_REGISTER_TYPE_D
;
310 return BRW_REGISTER_TYPE_Q
;
312 unreachable("Invalid bit size");
314 case BRW_REGISTER_TYPE_UB
:
315 case BRW_REGISTER_TYPE_UW
:
316 case BRW_REGISTER_TYPE_UD
:
317 case BRW_REGISTER_TYPE_UQ
:
320 return BRW_REGISTER_TYPE_UB
;
322 return BRW_REGISTER_TYPE_UW
;
324 return BRW_REGISTER_TYPE_UD
;
326 return BRW_REGISTER_TYPE_UQ
;
328 unreachable("Invalid bit size");
331 unreachable("Unknown type");
336 fs_visitor::nir_emit_impl(nir_function_impl
*impl
)
338 nir_locals
= ralloc_array(mem_ctx
, fs_reg
, impl
->reg_alloc
);
339 for (unsigned i
= 0; i
< impl
->reg_alloc
; i
++) {
340 nir_locals
[i
] = fs_reg();
343 foreach_list_typed(nir_register
, reg
, node
, &impl
->registers
) {
344 unsigned array_elems
=
345 reg
->num_array_elems
== 0 ? 1 : reg
->num_array_elems
;
346 unsigned size
= array_elems
* reg
->num_components
;
347 const brw_reg_type reg_type
= reg
->bit_size
== 8 ? BRW_REGISTER_TYPE_B
:
348 brw_reg_type_from_bit_size(reg
->bit_size
, BRW_REGISTER_TYPE_F
);
349 nir_locals
[reg
->index
] = bld
.vgrf(reg_type
, size
);
352 nir_ssa_values
= reralloc(mem_ctx
, nir_ssa_values
, fs_reg
,
355 nir_emit_cf_list(&impl
->body
);
359 fs_visitor::nir_emit_cf_list(exec_list
*list
)
361 exec_list_validate(list
);
362 foreach_list_typed(nir_cf_node
, node
, node
, list
) {
363 switch (node
->type
) {
365 nir_emit_if(nir_cf_node_as_if(node
));
368 case nir_cf_node_loop
:
369 nir_emit_loop(nir_cf_node_as_loop(node
));
372 case nir_cf_node_block
:
373 nir_emit_block(nir_cf_node_as_block(node
));
377 unreachable("Invalid CFG node block");
383 fs_visitor::nir_emit_if(nir_if
*if_stmt
)
388 /* If the condition has the form !other_condition, use other_condition as
389 * the source, but invert the predicate on the if instruction.
391 nir_alu_instr
*cond
= nir_src_as_alu_instr(if_stmt
->condition
);
392 if (cond
!= NULL
&& cond
->op
== nir_op_inot
) {
393 assert(!cond
->src
[0].negate
);
394 assert(!cond
->src
[0].abs
);
397 cond_reg
= get_nir_src(cond
->src
[0].src
);
400 cond_reg
= get_nir_src(if_stmt
->condition
);
403 /* first, put the condition into f0 */
404 fs_inst
*inst
= bld
.MOV(bld
.null_reg_d(),
405 retype(cond_reg
, BRW_REGISTER_TYPE_D
));
406 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
408 bld
.IF(BRW_PREDICATE_NORMAL
)->predicate_inverse
= invert
;
410 nir_emit_cf_list(&if_stmt
->then_list
);
412 if (!nir_cf_list_is_empty_block(&if_stmt
->else_list
)) {
413 bld
.emit(BRW_OPCODE_ELSE
);
414 nir_emit_cf_list(&if_stmt
->else_list
);
417 bld
.emit(BRW_OPCODE_ENDIF
);
419 if (devinfo
->gen
< 7)
420 limit_dispatch_width(16, "Non-uniform control flow unsupported "
425 fs_visitor::nir_emit_loop(nir_loop
*loop
)
427 bld
.emit(BRW_OPCODE_DO
);
429 nir_emit_cf_list(&loop
->body
);
431 bld
.emit(BRW_OPCODE_WHILE
);
433 if (devinfo
->gen
< 7)
434 limit_dispatch_width(16, "Non-uniform control flow unsupported "
439 fs_visitor::nir_emit_block(nir_block
*block
)
441 nir_foreach_instr(instr
, block
) {
442 nir_emit_instr(instr
);
447 fs_visitor::nir_emit_instr(nir_instr
*instr
)
449 const fs_builder abld
= bld
.annotate(NULL
, instr
);
451 switch (instr
->type
) {
452 case nir_instr_type_alu
:
453 nir_emit_alu(abld
, nir_instr_as_alu(instr
));
456 case nir_instr_type_deref
:
457 unreachable("All derefs should've been lowered");
460 case nir_instr_type_intrinsic
:
462 case MESA_SHADER_VERTEX
:
463 nir_emit_vs_intrinsic(abld
, nir_instr_as_intrinsic(instr
));
465 case MESA_SHADER_TESS_CTRL
:
466 nir_emit_tcs_intrinsic(abld
, nir_instr_as_intrinsic(instr
));
468 case MESA_SHADER_TESS_EVAL
:
469 nir_emit_tes_intrinsic(abld
, nir_instr_as_intrinsic(instr
));
471 case MESA_SHADER_GEOMETRY
:
472 nir_emit_gs_intrinsic(abld
, nir_instr_as_intrinsic(instr
));
474 case MESA_SHADER_FRAGMENT
:
475 nir_emit_fs_intrinsic(abld
, nir_instr_as_intrinsic(instr
));
477 case MESA_SHADER_COMPUTE
:
478 nir_emit_cs_intrinsic(abld
, nir_instr_as_intrinsic(instr
));
481 unreachable("unsupported shader stage");
485 case nir_instr_type_tex
:
486 nir_emit_texture(abld
, nir_instr_as_tex(instr
));
489 case nir_instr_type_load_const
:
490 nir_emit_load_const(abld
, nir_instr_as_load_const(instr
));
493 case nir_instr_type_ssa_undef
:
494 /* We create a new VGRF for undefs on every use (by handling
495 * them in get_nir_src()), rather than for each definition.
496 * This helps register coalescing eliminate MOVs from undef.
500 case nir_instr_type_jump
:
501 nir_emit_jump(abld
, nir_instr_as_jump(instr
));
505 unreachable("unknown instruction type");
510 * Recognizes a parent instruction of nir_op_extract_* and changes the type to
514 fs_visitor::optimize_extract_to_float(nir_alu_instr
*instr
,
515 const fs_reg
&result
)
517 if (!instr
->src
[0].src
.is_ssa
||
518 !instr
->src
[0].src
.ssa
->parent_instr
)
521 if (instr
->src
[0].src
.ssa
->parent_instr
->type
!= nir_instr_type_alu
)
524 nir_alu_instr
*src0
=
525 nir_instr_as_alu(instr
->src
[0].src
.ssa
->parent_instr
);
527 if (src0
->op
!= nir_op_extract_u8
&& src0
->op
!= nir_op_extract_u16
&&
528 src0
->op
!= nir_op_extract_i8
&& src0
->op
!= nir_op_extract_i16
)
531 /* If either opcode has source modifiers, bail.
533 * TODO: We can potentially handle source modifiers if both of the opcodes
534 * we're combining are signed integers.
536 if (instr
->src
[0].abs
|| instr
->src
[0].negate
||
537 src0
->src
[0].abs
|| src0
->src
[0].negate
)
540 unsigned element
= nir_src_as_uint(src0
->src
[1].src
);
542 /* Element type to extract.*/
543 const brw_reg_type type
= brw_int_type(
544 src0
->op
== nir_op_extract_u16
|| src0
->op
== nir_op_extract_i16
? 2 : 1,
545 src0
->op
== nir_op_extract_i16
|| src0
->op
== nir_op_extract_i8
);
547 fs_reg op0
= get_nir_src(src0
->src
[0].src
);
548 op0
.type
= brw_type_for_nir_type(devinfo
,
549 (nir_alu_type
)(nir_op_infos
[src0
->op
].input_types
[0] |
550 nir_src_bit_size(src0
->src
[0].src
)));
551 op0
= offset(op0
, bld
, src0
->src
[0].swizzle
[0]);
553 set_saturate(instr
->dest
.saturate
,
554 bld
.MOV(result
, subscript(op0
, type
, element
)));
559 fs_visitor::optimize_frontfacing_ternary(nir_alu_instr
*instr
,
560 const fs_reg
&result
)
562 nir_intrinsic_instr
*src0
= nir_src_as_intrinsic(instr
->src
[0].src
);
563 if (src0
== NULL
|| src0
->intrinsic
!= nir_intrinsic_load_front_face
)
566 if (!nir_src_is_const(instr
->src
[1].src
) ||
567 !nir_src_is_const(instr
->src
[2].src
))
570 const float value1
= nir_src_as_float(instr
->src
[1].src
);
571 const float value2
= nir_src_as_float(instr
->src
[2].src
);
572 if (fabsf(value1
) != 1.0f
|| fabsf(value2
) != 1.0f
)
575 /* nir_opt_algebraic should have gotten rid of bcsel(b, a, a) */
576 assert(value1
== -value2
);
578 fs_reg tmp
= vgrf(glsl_type::int_type
);
580 if (devinfo
->gen
>= 6) {
581 /* Bit 15 of g0.0 is 0 if the polygon is front facing. */
582 fs_reg g0
= fs_reg(retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_W
));
584 /* For (gl_FrontFacing ? 1.0 : -1.0), emit:
586 * or(8) tmp.1<2>W g0.0<0,1,0>W 0x00003f80W
587 * and(8) dst<1>D tmp<8,8,1>D 0xbf800000D
589 * and negate g0.0<0,1,0>W for (gl_FrontFacing ? -1.0 : 1.0).
591 * This negation looks like it's safe in practice, because bits 0:4 will
592 * surely be TRIANGLES
595 if (value1
== -1.0f
) {
599 bld
.OR(subscript(tmp
, BRW_REGISTER_TYPE_W
, 1),
600 g0
, brw_imm_uw(0x3f80));
602 /* Bit 31 of g1.6 is 0 if the polygon is front facing. */
603 fs_reg g1_6
= fs_reg(retype(brw_vec1_grf(1, 6), BRW_REGISTER_TYPE_D
));
605 /* For (gl_FrontFacing ? 1.0 : -1.0), emit:
607 * or(8) tmp<1>D g1.6<0,1,0>D 0x3f800000D
608 * and(8) dst<1>D tmp<8,8,1>D 0xbf800000D
610 * and negate g1.6<0,1,0>D for (gl_FrontFacing ? -1.0 : 1.0).
612 * This negation looks like it's safe in practice, because bits 0:4 will
613 * surely be TRIANGLES
616 if (value1
== -1.0f
) {
620 bld
.OR(tmp
, g1_6
, brw_imm_d(0x3f800000));
622 bld
.AND(retype(result
, BRW_REGISTER_TYPE_D
), tmp
, brw_imm_d(0xbf800000));
628 emit_find_msb_using_lzd(const fs_builder
&bld
,
629 const fs_reg
&result
,
637 /* LZD of an absolute value source almost always does the right
638 * thing. There are two problem values:
640 * * 0x80000000. Since abs(0x80000000) == 0x80000000, LZD returns
641 * 0. However, findMSB(int(0x80000000)) == 30.
643 * * 0xffffffff. Since abs(0xffffffff) == 1, LZD returns
644 * 31. Section 8.8 (Integer Functions) of the GLSL 4.50 spec says:
646 * For a value of zero or negative one, -1 will be returned.
648 * * Negative powers of two. LZD(abs(-(1<<x))) returns x, but
649 * findMSB(-(1<<x)) should return x-1.
651 * For all negative number cases, including 0x80000000 and
652 * 0xffffffff, the correct value is obtained from LZD if instead of
653 * negating the (already negative) value the logical-not is used. A
654 * conditonal logical-not can be achieved in two instructions.
656 temp
= bld
.vgrf(BRW_REGISTER_TYPE_D
);
658 bld
.ASR(temp
, src
, brw_imm_d(31));
659 bld
.XOR(temp
, temp
, src
);
662 bld
.LZD(retype(result
, BRW_REGISTER_TYPE_UD
),
663 retype(temp
, BRW_REGISTER_TYPE_UD
));
665 /* LZD counts from the MSB side, while GLSL's findMSB() wants the count
666 * from the LSB side. Subtract the result from 31 to convert the MSB
667 * count into an LSB count. If no bits are set, LZD will return 32.
668 * 31-32 = -1, which is exactly what findMSB() is supposed to return.
670 inst
= bld
.ADD(result
, retype(result
, BRW_REGISTER_TYPE_D
), brw_imm_d(31));
671 inst
->src
[0].negate
= true;
675 brw_rnd_mode_from_nir_op (const nir_op op
) {
677 case nir_op_f2f16_rtz
:
678 return BRW_RND_MODE_RTZ
;
679 case nir_op_f2f16_rtne
:
680 return BRW_RND_MODE_RTNE
;
682 unreachable("Operation doesn't support rounding mode");
687 fs_visitor::prepare_alu_destination_and_sources(const fs_builder
&bld
,
688 nir_alu_instr
*instr
,
693 need_dest
? get_nir_dest(instr
->dest
.dest
) : bld
.null_reg_ud();
695 result
.type
= brw_type_for_nir_type(devinfo
,
696 (nir_alu_type
)(nir_op_infos
[instr
->op
].output_type
|
697 nir_dest_bit_size(instr
->dest
.dest
)));
699 for (unsigned i
= 0; i
< nir_op_infos
[instr
->op
].num_inputs
; i
++) {
700 op
[i
] = get_nir_src(instr
->src
[i
].src
);
701 op
[i
].type
= brw_type_for_nir_type(devinfo
,
702 (nir_alu_type
)(nir_op_infos
[instr
->op
].input_types
[i
] |
703 nir_src_bit_size(instr
->src
[i
].src
)));
704 op
[i
].abs
= instr
->src
[i
].abs
;
705 op
[i
].negate
= instr
->src
[i
].negate
;
708 /* Move and vecN instrutions may still be vectored. Return the raw,
709 * vectored source and destination so that fs_visitor::nir_emit_alu can
710 * handle it. Other callers should not have to handle these kinds of
724 /* At this point, we have dealt with any instruction that operates on
725 * more than a single channel. Therefore, we can just adjust the source
726 * and destination registers for that channel and emit the instruction.
728 unsigned channel
= 0;
729 if (nir_op_infos
[instr
->op
].output_size
== 0) {
730 /* Since NIR is doing the scalarizing for us, we should only ever see
731 * vectorized operations with a single channel.
733 assert(util_bitcount(instr
->dest
.write_mask
) == 1);
734 channel
= ffs(instr
->dest
.write_mask
) - 1;
736 result
= offset(result
, bld
, channel
);
739 for (unsigned i
= 0; i
< nir_op_infos
[instr
->op
].num_inputs
; i
++) {
740 assert(nir_op_infos
[instr
->op
].input_sizes
[i
] < 2);
741 op
[i
] = offset(op
[i
], bld
, instr
->src
[i
].swizzle
[channel
]);
748 fs_visitor::resolve_inot_sources(const fs_builder
&bld
, nir_alu_instr
*instr
,
751 for (unsigned i
= 0; i
< 2; i
++) {
752 nir_alu_instr
*inot_instr
= nir_src_as_alu_instr(instr
->src
[i
].src
);
754 if (inot_instr
!= NULL
&& inot_instr
->op
== nir_op_inot
&&
755 !inot_instr
->src
[0].abs
&& !inot_instr
->src
[0].negate
) {
756 /* The source of the inot is now the source of instr. */
757 prepare_alu_destination_and_sources(bld
, inot_instr
, &op
[i
], false);
759 assert(!op
[i
].negate
);
762 op
[i
] = resolve_source_modifiers(op
[i
]);
768 fs_visitor::try_emit_b2fi_of_inot(const fs_builder
&bld
,
770 nir_alu_instr
*instr
)
772 if (devinfo
->gen
< 6 || devinfo
->gen
>= 12)
775 nir_alu_instr
*inot_instr
= nir_src_as_alu_instr(instr
->src
[0].src
);
777 if (inot_instr
== NULL
|| inot_instr
->op
!= nir_op_inot
)
780 /* HF is also possible as a destination on BDW+. For nir_op_b2i, the set
781 * of valid size-changing combinations is a bit more complex.
783 * The source restriction is just because I was lazy about generating the
786 if (nir_dest_bit_size(instr
->dest
.dest
) != 32 ||
787 nir_src_bit_size(inot_instr
->src
[0].src
) != 32)
790 /* b2[fi](inot(a)) maps a=0 => 1, a=-1 => 0. Since a can only be 0 or -1,
791 * this is float(1 + a).
795 prepare_alu_destination_and_sources(bld
, inot_instr
, &op
, false);
797 /* Ignore the saturate modifier, if there is one. The result of the
798 * arithmetic can only be 0 or 1, so the clamping will do nothing anyway.
800 bld
.ADD(result
, op
, brw_imm_d(1));
806 * Emit code for nir_op_fsign possibly fused with a nir_op_fmul
808 * If \c instr is not the \c nir_op_fsign, then \c fsign_src is the index of
809 * the source of \c instr that is a \c nir_op_fsign.
812 fs_visitor::emit_fsign(const fs_builder
&bld
, const nir_alu_instr
*instr
,
813 fs_reg result
, fs_reg
*op
, unsigned fsign_src
)
817 assert(instr
->op
== nir_op_fsign
|| instr
->op
== nir_op_fmul
);
818 assert(fsign_src
< nir_op_infos
[instr
->op
].num_inputs
);
820 if (instr
->op
!= nir_op_fsign
) {
821 const nir_alu_instr
*const fsign_instr
=
822 nir_src_as_alu_instr(instr
->src
[fsign_src
].src
);
824 assert(!fsign_instr
->dest
.saturate
);
826 /* op[fsign_src] has the nominal result of the fsign, and op[1 -
827 * fsign_src] has the other multiply source. This must be rearranged so
828 * that op[0] is the source of the fsign op[1] is the other multiply
834 op
[0] = get_nir_src(fsign_instr
->src
[0].src
);
836 const nir_alu_type t
=
837 (nir_alu_type
)(nir_op_infos
[instr
->op
].input_types
[0] |
838 nir_src_bit_size(fsign_instr
->src
[0].src
));
840 op
[0].type
= brw_type_for_nir_type(devinfo
, t
);
841 op
[0].abs
= fsign_instr
->src
[0].abs
;
842 op
[0].negate
= fsign_instr
->src
[0].negate
;
844 unsigned channel
= 0;
845 if (nir_op_infos
[instr
->op
].output_size
== 0) {
846 /* Since NIR is doing the scalarizing for us, we should only ever see
847 * vectorized operations with a single channel.
849 assert(util_bitcount(instr
->dest
.write_mask
) == 1);
850 channel
= ffs(instr
->dest
.write_mask
) - 1;
853 op
[0] = offset(op
[0], bld
, fsign_instr
->src
[0].swizzle
[channel
]);
855 assert(!instr
->dest
.saturate
);
859 /* Straightforward since the source can be assumed to be either strictly
860 * >= 0 or strictly <= 0 depending on the setting of the negate flag.
862 set_condmod(BRW_CONDITIONAL_NZ
, bld
.MOV(result
, op
[0]));
864 if (instr
->op
== nir_op_fsign
) {
865 inst
= (op
[0].negate
)
866 ? bld
.MOV(result
, brw_imm_f(-1.0f
))
867 : bld
.MOV(result
, brw_imm_f(1.0f
));
869 op
[1].negate
= (op
[0].negate
!= op
[1].negate
);
870 inst
= bld
.MOV(result
, op
[1]);
873 set_predicate(BRW_PREDICATE_NORMAL
, inst
);
874 } else if (type_sz(op
[0].type
) == 2) {
875 /* AND(val, 0x8000) gives the sign bit.
877 * Predicated OR ORs 1.0 (0x3c00) with the sign bit if val is not zero.
879 fs_reg zero
= retype(brw_imm_uw(0), BRW_REGISTER_TYPE_HF
);
880 bld
.CMP(bld
.null_reg_f(), op
[0], zero
, BRW_CONDITIONAL_NZ
);
882 op
[0].type
= BRW_REGISTER_TYPE_UW
;
883 result
.type
= BRW_REGISTER_TYPE_UW
;
884 bld
.AND(result
, op
[0], brw_imm_uw(0x8000u
));
886 if (instr
->op
== nir_op_fsign
)
887 inst
= bld
.OR(result
, result
, brw_imm_uw(0x3c00u
));
889 /* Use XOR here to get the result sign correct. */
890 inst
= bld
.XOR(result
, result
, retype(op
[1], BRW_REGISTER_TYPE_UW
));
893 inst
->predicate
= BRW_PREDICATE_NORMAL
;
894 } else if (type_sz(op
[0].type
) == 4) {
895 /* AND(val, 0x80000000) gives the sign bit.
897 * Predicated OR ORs 1.0 (0x3f800000) with the sign bit if val is not
900 bld
.CMP(bld
.null_reg_f(), op
[0], brw_imm_f(0.0f
), BRW_CONDITIONAL_NZ
);
902 op
[0].type
= BRW_REGISTER_TYPE_UD
;
903 result
.type
= BRW_REGISTER_TYPE_UD
;
904 bld
.AND(result
, op
[0], brw_imm_ud(0x80000000u
));
906 if (instr
->op
== nir_op_fsign
)
907 inst
= bld
.OR(result
, result
, brw_imm_ud(0x3f800000u
));
909 /* Use XOR here to get the result sign correct. */
910 inst
= bld
.XOR(result
, result
, retype(op
[1], BRW_REGISTER_TYPE_UD
));
913 inst
->predicate
= BRW_PREDICATE_NORMAL
;
915 /* For doubles we do the same but we need to consider:
917 * - 2-src instructions can't operate with 64-bit immediates
918 * - The sign is encoded in the high 32-bit of each DF
919 * - We need to produce a DF result.
922 fs_reg zero
= vgrf(glsl_type::double_type
);
923 bld
.MOV(zero
, setup_imm_df(bld
, 0.0));
924 bld
.CMP(bld
.null_reg_df(), op
[0], zero
, BRW_CONDITIONAL_NZ
);
926 bld
.MOV(result
, zero
);
928 fs_reg r
= subscript(result
, BRW_REGISTER_TYPE_UD
, 1);
929 bld
.AND(r
, subscript(op
[0], BRW_REGISTER_TYPE_UD
, 1),
930 brw_imm_ud(0x80000000u
));
932 if (instr
->op
== nir_op_fsign
) {
933 set_predicate(BRW_PREDICATE_NORMAL
,
934 bld
.OR(r
, r
, brw_imm_ud(0x3ff00000u
)));
936 /* This could be done better in some cases. If the scale is an
937 * immediate with the low 32-bits all 0, emitting a separate XOR and
938 * OR would allow an algebraic optimization to remove the OR. There
939 * are currently zero instances of fsign(double(x))*IMM in shader-db
940 * or any test suite, so it is hard to care at this time.
942 fs_reg result_int64
= retype(result
, BRW_REGISTER_TYPE_UQ
);
943 inst
= bld
.XOR(result_int64
, result_int64
,
944 retype(op
[1], BRW_REGISTER_TYPE_UQ
));
950 * Deteremine whether sources of a nir_op_fmul can be fused with a nir_op_fsign
952 * Checks the operands of a \c nir_op_fmul to determine whether or not
953 * \c emit_fsign could fuse the multiplication with the \c sign() calculation.
955 * \param instr The multiplication instruction
957 * \param fsign_src The source of \c instr that may or may not be a
961 can_fuse_fmul_fsign(nir_alu_instr
*instr
, unsigned fsign_src
)
963 assert(instr
->op
== nir_op_fmul
);
965 nir_alu_instr
*const fsign_instr
=
966 nir_src_as_alu_instr(instr
->src
[fsign_src
].src
);
970 * 1. instr->src[fsign_src] must be a nir_op_fsign.
971 * 2. The nir_op_fsign can only be used by this multiplication.
972 * 3. The source that is the nir_op_fsign does not have source modifiers.
973 * \c emit_fsign only examines the source modifiers of the source of the
976 * The nir_op_fsign must also not have the saturate modifier, but steps
977 * have already been taken (in nir_opt_algebraic) to ensure that.
979 return fsign_instr
!= NULL
&& fsign_instr
->op
== nir_op_fsign
&&
980 is_used_once(fsign_instr
) &&
981 !instr
->src
[fsign_src
].abs
&& !instr
->src
[fsign_src
].negate
;
985 fs_visitor::nir_emit_alu(const fs_builder
&bld
, nir_alu_instr
*instr
)
987 struct brw_wm_prog_key
*fs_key
= (struct brw_wm_prog_key
*) this->key
;
991 fs_reg result
= prepare_alu_destination_and_sources(bld
, instr
, op
, true);
999 fs_reg temp
= result
;
1000 bool need_extra_copy
= false;
1001 for (unsigned i
= 0; i
< nir_op_infos
[instr
->op
].num_inputs
; i
++) {
1002 if (!instr
->src
[i
].src
.is_ssa
&&
1003 instr
->dest
.dest
.reg
.reg
== instr
->src
[i
].src
.reg
.reg
) {
1004 need_extra_copy
= true;
1005 temp
= bld
.vgrf(result
.type
, 4);
1010 for (unsigned i
= 0; i
< 4; i
++) {
1011 if (!(instr
->dest
.write_mask
& (1 << i
)))
1014 if (instr
->op
== nir_op_imov
|| instr
->op
== nir_op_fmov
) {
1015 inst
= bld
.MOV(offset(temp
, bld
, i
),
1016 offset(op
[0], bld
, instr
->src
[0].swizzle
[i
]));
1018 inst
= bld
.MOV(offset(temp
, bld
, i
),
1019 offset(op
[i
], bld
, instr
->src
[i
].swizzle
[0]));
1021 inst
->saturate
= instr
->dest
.saturate
;
1024 /* In this case the source and destination registers were the same,
1025 * so we need to insert an extra set of moves in order to deal with
1028 if (need_extra_copy
) {
1029 for (unsigned i
= 0; i
< 4; i
++) {
1030 if (!(instr
->dest
.write_mask
& (1 << i
)))
1033 bld
.MOV(offset(result
, bld
, i
), offset(temp
, bld
, i
));
1041 if (optimize_extract_to_float(instr
, result
))
1043 inst
= bld
.MOV(result
, op
[0]);
1044 inst
->saturate
= instr
->dest
.saturate
;
1047 case nir_op_f2f16_rtne
:
1048 case nir_op_f2f16_rtz
:
1049 bld
.emit(SHADER_OPCODE_RND_MODE
, bld
.null_reg_ud(),
1050 brw_imm_d(brw_rnd_mode_from_nir_op(instr
->op
)));
1053 /* In theory, it would be better to use BRW_OPCODE_F32TO16. Depending
1054 * on the HW gen, it is a special hw opcode or just a MOV, and
1055 * brw_F32TO16 (at brw_eu_emit) would do the work to chose.
1057 * But if we want to use that opcode, we need to provide support on
1058 * different optimizations and lowerings. As right now HF support is
1059 * only for gen8+, it will be better to use directly the MOV, and use
1060 * BRW_OPCODE_F32TO16 when/if we work for HF support on gen7.
1062 assert(type_sz(op
[0].type
) < 8); /* brw_nir_lower_conversions */
1063 inst
= bld
.MOV(result
, op
[0]);
1064 inst
->saturate
= instr
->dest
.saturate
;
1074 if (try_emit_b2fi_of_inot(bld
, result
, instr
))
1076 op
[0].type
= BRW_REGISTER_TYPE_D
;
1077 op
[0].negate
= !op
[0].negate
;
1101 if (result
.type
== BRW_REGISTER_TYPE_B
||
1102 result
.type
== BRW_REGISTER_TYPE_UB
||
1103 result
.type
== BRW_REGISTER_TYPE_HF
)
1104 assert(type_sz(op
[0].type
) < 8); /* brw_nir_lower_conversions */
1106 if (op
[0].type
== BRW_REGISTER_TYPE_B
||
1107 op
[0].type
== BRW_REGISTER_TYPE_UB
||
1108 op
[0].type
== BRW_REGISTER_TYPE_HF
)
1109 assert(type_sz(result
.type
) < 8); /* brw_nir_lower_conversions */
1111 inst
= bld
.MOV(result
, op
[0]);
1112 inst
->saturate
= instr
->dest
.saturate
;
1116 emit_fsign(bld
, instr
, result
, op
, 0);
1120 inst
= bld
.emit(SHADER_OPCODE_RCP
, result
, op
[0]);
1121 inst
->saturate
= instr
->dest
.saturate
;
1125 inst
= bld
.emit(SHADER_OPCODE_EXP2
, result
, op
[0]);
1126 inst
->saturate
= instr
->dest
.saturate
;
1130 inst
= bld
.emit(SHADER_OPCODE_LOG2
, result
, op
[0]);
1131 inst
->saturate
= instr
->dest
.saturate
;
1135 inst
= bld
.emit(SHADER_OPCODE_SIN
, result
, op
[0]);
1136 inst
->saturate
= instr
->dest
.saturate
;
1140 inst
= bld
.emit(SHADER_OPCODE_COS
, result
, op
[0]);
1141 inst
->saturate
= instr
->dest
.saturate
;
1145 if (fs_key
->high_quality_derivatives
) {
1146 inst
= bld
.emit(FS_OPCODE_DDX_FINE
, result
, op
[0]);
1148 inst
= bld
.emit(FS_OPCODE_DDX_COARSE
, result
, op
[0]);
1150 inst
->saturate
= instr
->dest
.saturate
;
1152 case nir_op_fddx_fine
:
1153 inst
= bld
.emit(FS_OPCODE_DDX_FINE
, result
, op
[0]);
1154 inst
->saturate
= instr
->dest
.saturate
;
1156 case nir_op_fddx_coarse
:
1157 inst
= bld
.emit(FS_OPCODE_DDX_COARSE
, result
, op
[0]);
1158 inst
->saturate
= instr
->dest
.saturate
;
1161 if (fs_key
->high_quality_derivatives
) {
1162 inst
= bld
.emit(FS_OPCODE_DDY_FINE
, result
, op
[0]);
1164 inst
= bld
.emit(FS_OPCODE_DDY_COARSE
, result
, op
[0]);
1166 inst
->saturate
= instr
->dest
.saturate
;
1168 case nir_op_fddy_fine
:
1169 inst
= bld
.emit(FS_OPCODE_DDY_FINE
, result
, op
[0]);
1170 inst
->saturate
= instr
->dest
.saturate
;
1172 case nir_op_fddy_coarse
:
1173 inst
= bld
.emit(FS_OPCODE_DDY_COARSE
, result
, op
[0]);
1174 inst
->saturate
= instr
->dest
.saturate
;
1179 inst
= bld
.ADD(result
, op
[0], op
[1]);
1180 inst
->saturate
= instr
->dest
.saturate
;
1183 case nir_op_uadd_sat
:
1184 inst
= bld
.ADD(result
, op
[0], op
[1]);
1185 inst
->saturate
= true;
1189 for (unsigned i
= 0; i
< 2; i
++) {
1190 if (can_fuse_fmul_fsign(instr
, i
)) {
1191 emit_fsign(bld
, instr
, result
, op
, i
);
1196 inst
= bld
.MUL(result
, op
[0], op
[1]);
1197 inst
->saturate
= instr
->dest
.saturate
;
1200 case nir_op_imul_2x32_64
:
1201 case nir_op_umul_2x32_64
:
1202 bld
.MUL(result
, op
[0], op
[1]);
1206 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1207 bld
.MUL(result
, op
[0], op
[1]);
1210 case nir_op_imul_high
:
1211 case nir_op_umul_high
:
1212 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1213 bld
.emit(SHADER_OPCODE_MULH
, result
, op
[0], op
[1]);
1218 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1219 bld
.emit(SHADER_OPCODE_INT_QUOTIENT
, result
, op
[0], op
[1]);
1222 case nir_op_uadd_carry
:
1223 unreachable("Should have been lowered by carry_to_arith().");
1225 case nir_op_usub_borrow
:
1226 unreachable("Should have been lowered by borrow_to_arith().");
1230 /* According to the sign table for INT DIV in the Ivy Bridge PRM, it
1231 * appears that our hardware just does the right thing for signed
1234 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1235 bld
.emit(SHADER_OPCODE_INT_REMAINDER
, result
, op
[0], op
[1]);
1239 /* Get a regular C-style remainder. If a % b == 0, set the predicate. */
1240 bld
.emit(SHADER_OPCODE_INT_REMAINDER
, result
, op
[0], op
[1]);
1242 /* Math instructions don't support conditional mod */
1243 inst
= bld
.MOV(bld
.null_reg_d(), result
);
1244 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
1246 /* Now, we need to determine if signs of the sources are different.
1247 * When we XOR the sources, the top bit is 0 if they are the same and 1
1248 * if they are different. We can then use a conditional modifier to
1249 * turn that into a predicate. This leads us to an XOR.l instruction.
1251 * Technically, according to the PRM, you're not allowed to use .l on a
1252 * XOR instruction. However, emperical experiments and Curro's reading
1253 * of the simulator source both indicate that it's safe.
1255 fs_reg tmp
= bld
.vgrf(BRW_REGISTER_TYPE_D
);
1256 inst
= bld
.XOR(tmp
, op
[0], op
[1]);
1257 inst
->predicate
= BRW_PREDICATE_NORMAL
;
1258 inst
->conditional_mod
= BRW_CONDITIONAL_L
;
1260 /* If the result of the initial remainder operation is non-zero and the
1261 * two sources have different signs, add in a copy of op[1] to get the
1262 * final integer modulus value.
1264 inst
= bld
.ADD(result
, result
, op
[1]);
1265 inst
->predicate
= BRW_PREDICATE_NORMAL
;
1272 case nir_op_fne32
: {
1273 fs_reg dest
= result
;
1275 const uint32_t bit_size
= nir_src_bit_size(instr
->src
[0].src
);
1277 dest
= bld
.vgrf(op
[0].type
, 1);
1279 brw_conditional_mod cond
;
1280 switch (instr
->op
) {
1282 cond
= BRW_CONDITIONAL_L
;
1285 cond
= BRW_CONDITIONAL_GE
;
1288 cond
= BRW_CONDITIONAL_Z
;
1291 cond
= BRW_CONDITIONAL_NZ
;
1294 unreachable("bad opcode");
1297 bld
.CMP(dest
, op
[0], op
[1], cond
);
1299 if (bit_size
> 32) {
1300 bld
.MOV(result
, subscript(dest
, BRW_REGISTER_TYPE_UD
, 0));
1301 } else if(bit_size
< 32) {
1302 /* When we convert the result to 32-bit we need to be careful and do
1303 * it as a signed conversion to get sign extension (for 32-bit true)
1305 const brw_reg_type src_type
=
1306 brw_reg_type_from_bit_size(bit_size
, BRW_REGISTER_TYPE_D
);
1308 bld
.MOV(retype(result
, BRW_REGISTER_TYPE_D
), retype(dest
, src_type
));
1318 case nir_op_ine32
: {
1319 fs_reg dest
= result
;
1321 const uint32_t bit_size
= nir_src_bit_size(instr
->src
[0].src
);
1323 dest
= bld
.vgrf(op
[0].type
, 1);
1325 brw_conditional_mod cond
;
1326 switch (instr
->op
) {
1329 cond
= BRW_CONDITIONAL_L
;
1333 cond
= BRW_CONDITIONAL_GE
;
1336 cond
= BRW_CONDITIONAL_Z
;
1339 cond
= BRW_CONDITIONAL_NZ
;
1342 unreachable("bad opcode");
1344 bld
.CMP(dest
, op
[0], op
[1], cond
);
1346 if (bit_size
> 32) {
1347 bld
.MOV(result
, subscript(dest
, BRW_REGISTER_TYPE_UD
, 0));
1348 } else if (bit_size
< 32) {
1349 /* When we convert the result to 32-bit we need to be careful and do
1350 * it as a signed conversion to get sign extension (for 32-bit true)
1352 const brw_reg_type src_type
=
1353 brw_reg_type_from_bit_size(bit_size
, BRW_REGISTER_TYPE_D
);
1355 bld
.MOV(retype(result
, BRW_REGISTER_TYPE_D
), retype(dest
, src_type
));
1361 if (devinfo
->gen
>= 8) {
1362 nir_alu_instr
*inot_src_instr
= nir_src_as_alu_instr(instr
->src
[0].src
);
1364 if (inot_src_instr
!= NULL
&&
1365 (inot_src_instr
->op
== nir_op_ior
||
1366 inot_src_instr
->op
== nir_op_ixor
||
1367 inot_src_instr
->op
== nir_op_iand
) &&
1368 !inot_src_instr
->src
[0].abs
&&
1369 !inot_src_instr
->src
[0].negate
&&
1370 !inot_src_instr
->src
[1].abs
&&
1371 !inot_src_instr
->src
[1].negate
) {
1372 /* The sources of the source logical instruction are now the
1373 * sources of the instruction that will be generated.
1375 prepare_alu_destination_and_sources(bld
, inot_src_instr
, op
, false);
1376 resolve_inot_sources(bld
, inot_src_instr
, op
);
1378 /* Smash all of the sources and destination to be signed. This
1379 * doesn't matter for the operation of the instruction, but cmod
1380 * propagation fails on unsigned sources with negation (due to
1381 * fs_inst::can_do_cmod returning false).
1384 brw_type_for_nir_type(devinfo
,
1385 (nir_alu_type
)(nir_type_int
|
1386 nir_dest_bit_size(instr
->dest
.dest
)));
1388 brw_type_for_nir_type(devinfo
,
1389 (nir_alu_type
)(nir_type_int
|
1390 nir_src_bit_size(inot_src_instr
->src
[0].src
)));
1392 brw_type_for_nir_type(devinfo
,
1393 (nir_alu_type
)(nir_type_int
|
1394 nir_src_bit_size(inot_src_instr
->src
[1].src
)));
1396 /* For XOR, only invert one of the sources. Arbitrarily choose
1399 op
[0].negate
= !op
[0].negate
;
1400 if (inot_src_instr
->op
!= nir_op_ixor
)
1401 op
[1].negate
= !op
[1].negate
;
1403 switch (inot_src_instr
->op
) {
1405 bld
.AND(result
, op
[0], op
[1]);
1409 bld
.OR(result
, op
[0], op
[1]);
1413 bld
.XOR(result
, op
[0], op
[1]);
1417 unreachable("impossible opcode");
1420 op
[0] = resolve_source_modifiers(op
[0]);
1422 bld
.NOT(result
, op
[0]);
1425 if (devinfo
->gen
>= 8) {
1426 resolve_inot_sources(bld
, instr
, op
);
1428 bld
.XOR(result
, op
[0], op
[1]);
1431 if (devinfo
->gen
>= 8) {
1432 resolve_inot_sources(bld
, instr
, op
);
1434 bld
.OR(result
, op
[0], op
[1]);
1437 if (devinfo
->gen
>= 8) {
1438 resolve_inot_sources(bld
, instr
, op
);
1440 bld
.AND(result
, op
[0], op
[1]);
1446 case nir_op_b32all_fequal2
:
1447 case nir_op_b32all_iequal2
:
1448 case nir_op_b32all_fequal3
:
1449 case nir_op_b32all_iequal3
:
1450 case nir_op_b32all_fequal4
:
1451 case nir_op_b32all_iequal4
:
1452 case nir_op_b32any_fnequal2
:
1453 case nir_op_b32any_inequal2
:
1454 case nir_op_b32any_fnequal3
:
1455 case nir_op_b32any_inequal3
:
1456 case nir_op_b32any_fnequal4
:
1457 case nir_op_b32any_inequal4
:
1458 unreachable("Lowered by nir_lower_alu_reductions");
1460 case nir_op_fnoise1_1
:
1461 case nir_op_fnoise1_2
:
1462 case nir_op_fnoise1_3
:
1463 case nir_op_fnoise1_4
:
1464 case nir_op_fnoise2_1
:
1465 case nir_op_fnoise2_2
:
1466 case nir_op_fnoise2_3
:
1467 case nir_op_fnoise2_4
:
1468 case nir_op_fnoise3_1
:
1469 case nir_op_fnoise3_2
:
1470 case nir_op_fnoise3_3
:
1471 case nir_op_fnoise3_4
:
1472 case nir_op_fnoise4_1
:
1473 case nir_op_fnoise4_2
:
1474 case nir_op_fnoise4_3
:
1475 case nir_op_fnoise4_4
:
1476 unreachable("not reached: should be handled by lower_noise");
1479 unreachable("not reached: should be handled by ldexp_to_arith()");
1482 inst
= bld
.emit(SHADER_OPCODE_SQRT
, result
, op
[0]);
1483 inst
->saturate
= instr
->dest
.saturate
;
1487 inst
= bld
.emit(SHADER_OPCODE_RSQ
, result
, op
[0]);
1488 inst
->saturate
= instr
->dest
.saturate
;
1492 case nir_op_f2b32
: {
1493 uint32_t bit_size
= nir_src_bit_size(instr
->src
[0].src
);
1494 if (bit_size
== 64) {
1495 /* two-argument instructions can't take 64-bit immediates */
1499 if (instr
->op
== nir_op_f2b32
) {
1500 zero
= vgrf(glsl_type::double_type
);
1501 tmp
= vgrf(glsl_type::double_type
);
1502 bld
.MOV(zero
, setup_imm_df(bld
, 0.0));
1504 zero
= vgrf(glsl_type::int64_t_type
);
1505 tmp
= vgrf(glsl_type::int64_t_type
);
1506 bld
.MOV(zero
, brw_imm_q(0));
1509 /* A SIMD16 execution needs to be split in two instructions, so use
1510 * a vgrf instead of the flag register as dst so instruction splitting
1513 bld
.CMP(tmp
, op
[0], zero
, BRW_CONDITIONAL_NZ
);
1514 bld
.MOV(result
, subscript(tmp
, BRW_REGISTER_TYPE_UD
, 0));
1517 if (bit_size
== 32) {
1518 zero
= instr
->op
== nir_op_f2b32
? brw_imm_f(0.0f
) : brw_imm_d(0);
1520 assert(bit_size
== 16);
1521 zero
= instr
->op
== nir_op_f2b32
?
1522 retype(brw_imm_w(0), BRW_REGISTER_TYPE_HF
) : brw_imm_w(0);
1524 bld
.CMP(result
, op
[0], zero
, BRW_CONDITIONAL_NZ
);
1530 inst
= bld
.RNDZ(result
, op
[0]);
1531 inst
->saturate
= instr
->dest
.saturate
;
1534 case nir_op_fceil
: {
1535 op
[0].negate
= !op
[0].negate
;
1536 fs_reg temp
= vgrf(glsl_type::float_type
);
1537 bld
.RNDD(temp
, op
[0]);
1539 inst
= bld
.MOV(result
, temp
);
1540 inst
->saturate
= instr
->dest
.saturate
;
1544 inst
= bld
.RNDD(result
, op
[0]);
1545 inst
->saturate
= instr
->dest
.saturate
;
1548 inst
= bld
.FRC(result
, op
[0]);
1549 inst
->saturate
= instr
->dest
.saturate
;
1551 case nir_op_fround_even
:
1552 inst
= bld
.RNDE(result
, op
[0]);
1553 inst
->saturate
= instr
->dest
.saturate
;
1556 case nir_op_fquantize2f16
: {
1557 fs_reg tmp16
= bld
.vgrf(BRW_REGISTER_TYPE_D
);
1558 fs_reg tmp32
= bld
.vgrf(BRW_REGISTER_TYPE_F
);
1559 fs_reg zero
= bld
.vgrf(BRW_REGISTER_TYPE_F
);
1561 /* The destination stride must be at least as big as the source stride. */
1562 tmp16
.type
= BRW_REGISTER_TYPE_W
;
1565 /* Check for denormal */
1566 fs_reg abs_src0
= op
[0];
1567 abs_src0
.abs
= true;
1568 bld
.CMP(bld
.null_reg_f(), abs_src0
, brw_imm_f(ldexpf(1.0, -14)),
1570 /* Get the appropriately signed zero */
1571 bld
.AND(retype(zero
, BRW_REGISTER_TYPE_UD
),
1572 retype(op
[0], BRW_REGISTER_TYPE_UD
),
1573 brw_imm_ud(0x80000000));
1574 /* Do the actual F32 -> F16 -> F32 conversion */
1575 bld
.emit(BRW_OPCODE_F32TO16
, tmp16
, op
[0]);
1576 bld
.emit(BRW_OPCODE_F16TO32
, tmp32
, tmp16
);
1577 /* Select that or zero based on normal status */
1578 inst
= bld
.SEL(result
, zero
, tmp32
);
1579 inst
->predicate
= BRW_PREDICATE_NORMAL
;
1580 inst
->saturate
= instr
->dest
.saturate
;
1587 inst
= bld
.emit_minmax(result
, op
[0], op
[1], BRW_CONDITIONAL_L
);
1588 inst
->saturate
= instr
->dest
.saturate
;
1594 inst
= bld
.emit_minmax(result
, op
[0], op
[1], BRW_CONDITIONAL_GE
);
1595 inst
->saturate
= instr
->dest
.saturate
;
1598 case nir_op_pack_snorm_2x16
:
1599 case nir_op_pack_snorm_4x8
:
1600 case nir_op_pack_unorm_2x16
:
1601 case nir_op_pack_unorm_4x8
:
1602 case nir_op_unpack_snorm_2x16
:
1603 case nir_op_unpack_snorm_4x8
:
1604 case nir_op_unpack_unorm_2x16
:
1605 case nir_op_unpack_unorm_4x8
:
1606 case nir_op_unpack_half_2x16
:
1607 case nir_op_pack_half_2x16
:
1608 unreachable("not reached: should be handled by lower_packing_builtins");
1610 case nir_op_unpack_half_2x16_split_x
:
1611 inst
= bld
.emit(BRW_OPCODE_F16TO32
, result
,
1612 subscript(op
[0], BRW_REGISTER_TYPE_UW
, 0));
1613 inst
->saturate
= instr
->dest
.saturate
;
1615 case nir_op_unpack_half_2x16_split_y
:
1616 inst
= bld
.emit(BRW_OPCODE_F16TO32
, result
,
1617 subscript(op
[0], BRW_REGISTER_TYPE_UW
, 1));
1618 inst
->saturate
= instr
->dest
.saturate
;
1621 case nir_op_pack_64_2x32_split
:
1622 case nir_op_pack_32_2x16_split
:
1623 bld
.emit(FS_OPCODE_PACK
, result
, op
[0], op
[1]);
1626 case nir_op_unpack_64_2x32_split_x
:
1627 case nir_op_unpack_64_2x32_split_y
: {
1628 if (instr
->op
== nir_op_unpack_64_2x32_split_x
)
1629 bld
.MOV(result
, subscript(op
[0], BRW_REGISTER_TYPE_UD
, 0));
1631 bld
.MOV(result
, subscript(op
[0], BRW_REGISTER_TYPE_UD
, 1));
1635 case nir_op_unpack_32_2x16_split_x
:
1636 case nir_op_unpack_32_2x16_split_y
: {
1637 if (instr
->op
== nir_op_unpack_32_2x16_split_x
)
1638 bld
.MOV(result
, subscript(op
[0], BRW_REGISTER_TYPE_UW
, 0));
1640 bld
.MOV(result
, subscript(op
[0], BRW_REGISTER_TYPE_UW
, 1));
1645 inst
= bld
.emit(SHADER_OPCODE_POW
, result
, op
[0], op
[1]);
1646 inst
->saturate
= instr
->dest
.saturate
;
1649 case nir_op_bitfield_reverse
:
1650 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1651 bld
.BFREV(result
, op
[0]);
1654 case nir_op_bit_count
:
1655 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1656 bld
.CBIT(result
, op
[0]);
1659 case nir_op_ufind_msb
: {
1660 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1661 emit_find_msb_using_lzd(bld
, result
, op
[0], false);
1665 case nir_op_ifind_msb
: {
1666 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1668 if (devinfo
->gen
< 7) {
1669 emit_find_msb_using_lzd(bld
, result
, op
[0], true);
1671 bld
.FBH(retype(result
, BRW_REGISTER_TYPE_UD
), op
[0]);
1673 /* FBH counts from the MSB side, while GLSL's findMSB() wants the
1674 * count from the LSB side. If FBH didn't return an error
1675 * (0xFFFFFFFF), then subtract the result from 31 to convert the MSB
1676 * count into an LSB count.
1678 bld
.CMP(bld
.null_reg_d(), result
, brw_imm_d(-1), BRW_CONDITIONAL_NZ
);
1680 inst
= bld
.ADD(result
, result
, brw_imm_d(31));
1681 inst
->predicate
= BRW_PREDICATE_NORMAL
;
1682 inst
->src
[0].negate
= true;
1687 case nir_op_find_lsb
:
1688 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1690 if (devinfo
->gen
< 7) {
1691 fs_reg temp
= vgrf(glsl_type::int_type
);
1693 /* (x & -x) generates a value that consists of only the LSB of x.
1694 * For all powers of 2, findMSB(y) == findLSB(y).
1696 fs_reg src
= retype(op
[0], BRW_REGISTER_TYPE_D
);
1697 fs_reg negated_src
= src
;
1699 /* One must be negated, and the other must be non-negated. It
1700 * doesn't matter which is which.
1702 negated_src
.negate
= true;
1705 bld
.AND(temp
, src
, negated_src
);
1706 emit_find_msb_using_lzd(bld
, result
, temp
, false);
1708 bld
.FBL(result
, op
[0]);
1712 case nir_op_ubitfield_extract
:
1713 case nir_op_ibitfield_extract
:
1714 unreachable("should have been lowered");
1717 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1718 bld
.BFE(result
, op
[2], op
[1], op
[0]);
1721 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1722 bld
.BFI1(result
, op
[0], op
[1]);
1725 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1726 bld
.BFI2(result
, op
[0], op
[1], op
[2]);
1729 case nir_op_bitfield_insert
:
1730 unreachable("not reached: should have been lowered");
1733 bld
.SHL(result
, op
[0], op
[1]);
1736 bld
.ASR(result
, op
[0], op
[1]);
1739 bld
.SHR(result
, op
[0], op
[1]);
1742 case nir_op_pack_half_2x16_split
:
1743 bld
.emit(FS_OPCODE_PACK_HALF_2x16_SPLIT
, result
, op
[0], op
[1]);
1747 inst
= bld
.MAD(result
, op
[2], op
[1], op
[0]);
1748 inst
->saturate
= instr
->dest
.saturate
;
1752 inst
= bld
.LRP(result
, op
[0], op
[1], op
[2]);
1753 inst
->saturate
= instr
->dest
.saturate
;
1756 case nir_op_b32csel
:
1757 if (optimize_frontfacing_ternary(instr
, result
))
1760 bld
.CMP(bld
.null_reg_d(), op
[0], brw_imm_d(0), BRW_CONDITIONAL_NZ
);
1761 inst
= bld
.SEL(result
, op
[1], op
[2]);
1762 inst
->predicate
= BRW_PREDICATE_NORMAL
;
1765 case nir_op_extract_u8
:
1766 case nir_op_extract_i8
: {
1767 unsigned byte
= nir_src_as_uint(instr
->src
[1].src
);
1772 * There is no direct conversion from B/UB to Q/UQ or Q/UQ to B/UB.
1773 * Use two instructions and a word or DWord intermediate integer type.
1775 if (nir_dest_bit_size(instr
->dest
.dest
) == 64) {
1776 const brw_reg_type type
= brw_int_type(1, instr
->op
== nir_op_extract_i8
);
1778 if (instr
->op
== nir_op_extract_i8
) {
1779 /* If we need to sign extend, extract to a word first */
1780 fs_reg w_temp
= bld
.vgrf(BRW_REGISTER_TYPE_W
);
1781 bld
.MOV(w_temp
, subscript(op
[0], type
, byte
));
1782 bld
.MOV(result
, w_temp
);
1783 } else if (byte
& 1) {
1784 /* Extract the high byte from the word containing the desired byte
1788 subscript(op
[0], BRW_REGISTER_TYPE_UW
, byte
/ 2),
1791 /* Otherwise use an AND with 0xff and a word type */
1793 subscript(op
[0], BRW_REGISTER_TYPE_UW
, byte
/ 2),
1797 const brw_reg_type type
= brw_int_type(1, instr
->op
== nir_op_extract_i8
);
1798 bld
.MOV(result
, subscript(op
[0], type
, byte
));
1803 case nir_op_extract_u16
:
1804 case nir_op_extract_i16
: {
1805 const brw_reg_type type
= brw_int_type(2, instr
->op
== nir_op_extract_i16
);
1806 unsigned word
= nir_src_as_uint(instr
->src
[1].src
);
1807 bld
.MOV(result
, subscript(op
[0], type
, word
));
1812 unreachable("unhandled instruction");
1815 /* If we need to do a boolean resolve, replace the result with -(x & 1)
1816 * to sign extend the low bit to 0/~0
1818 if (devinfo
->gen
<= 5 &&
1819 (instr
->instr
.pass_flags
& BRW_NIR_BOOLEAN_MASK
) == BRW_NIR_BOOLEAN_NEEDS_RESOLVE
) {
1820 fs_reg masked
= vgrf(glsl_type::int_type
);
1821 bld
.AND(masked
, result
, brw_imm_d(1));
1822 masked
.negate
= true;
1823 bld
.MOV(retype(result
, BRW_REGISTER_TYPE_D
), masked
);
1828 fs_visitor::nir_emit_load_const(const fs_builder
&bld
,
1829 nir_load_const_instr
*instr
)
1831 const brw_reg_type reg_type
=
1832 brw_reg_type_from_bit_size(instr
->def
.bit_size
, BRW_REGISTER_TYPE_D
);
1833 fs_reg reg
= bld
.vgrf(reg_type
, instr
->def
.num_components
);
1835 switch (instr
->def
.bit_size
) {
1837 for (unsigned i
= 0; i
< instr
->def
.num_components
; i
++)
1838 bld
.MOV(offset(reg
, bld
, i
), setup_imm_b(bld
, instr
->value
[i
].i8
));
1842 for (unsigned i
= 0; i
< instr
->def
.num_components
; i
++)
1843 bld
.MOV(offset(reg
, bld
, i
), brw_imm_w(instr
->value
[i
].i16
));
1847 for (unsigned i
= 0; i
< instr
->def
.num_components
; i
++)
1848 bld
.MOV(offset(reg
, bld
, i
), brw_imm_d(instr
->value
[i
].i32
));
1852 assert(devinfo
->gen
>= 7);
1853 if (devinfo
->gen
== 7) {
1854 /* We don't get 64-bit integer types until gen8 */
1855 for (unsigned i
= 0; i
< instr
->def
.num_components
; i
++) {
1856 bld
.MOV(retype(offset(reg
, bld
, i
), BRW_REGISTER_TYPE_DF
),
1857 setup_imm_df(bld
, instr
->value
[i
].f64
));
1860 for (unsigned i
= 0; i
< instr
->def
.num_components
; i
++)
1861 bld
.MOV(offset(reg
, bld
, i
), brw_imm_q(instr
->value
[i
].i64
));
1866 unreachable("Invalid bit size");
1869 nir_ssa_values
[instr
->def
.index
] = reg
;
1873 fs_visitor::get_nir_src(const nir_src
&src
)
1877 if (src
.ssa
->parent_instr
->type
== nir_instr_type_ssa_undef
) {
1878 const brw_reg_type reg_type
=
1879 brw_reg_type_from_bit_size(src
.ssa
->bit_size
, BRW_REGISTER_TYPE_D
);
1880 reg
= bld
.vgrf(reg_type
, src
.ssa
->num_components
);
1882 reg
= nir_ssa_values
[src
.ssa
->index
];
1885 /* We don't handle indirects on locals */
1886 assert(src
.reg
.indirect
== NULL
);
1887 reg
= offset(nir_locals
[src
.reg
.reg
->index
], bld
,
1888 src
.reg
.base_offset
* src
.reg
.reg
->num_components
);
1891 if (nir_src_bit_size(src
) == 64 && devinfo
->gen
== 7) {
1892 /* The only 64-bit type available on gen7 is DF, so use that. */
1893 reg
.type
= BRW_REGISTER_TYPE_DF
;
1895 /* To avoid floating-point denorm flushing problems, set the type by
1896 * default to an integer type - instructions that need floating point
1897 * semantics will set this to F if they need to
1899 reg
.type
= brw_reg_type_from_bit_size(nir_src_bit_size(src
),
1900 BRW_REGISTER_TYPE_D
);
1907 * Return an IMM for constants; otherwise call get_nir_src() as normal.
1909 * This function should not be called on any value which may be 64 bits.
1910 * We could theoretically support 64-bit on gen8+ but we choose not to
1911 * because it wouldn't work in general (no gen7 support) and there are
1912 * enough restrictions in 64-bit immediates that you can't take the return
1913 * value and treat it the same as the result of get_nir_src().
1916 fs_visitor::get_nir_src_imm(const nir_src
&src
)
1918 assert(nir_src_bit_size(src
) == 32);
1919 return nir_src_is_const(src
) ?
1920 fs_reg(brw_imm_d(nir_src_as_int(src
))) : get_nir_src(src
);
1924 fs_visitor::get_nir_dest(const nir_dest
&dest
)
1927 const brw_reg_type reg_type
=
1928 brw_reg_type_from_bit_size(dest
.ssa
.bit_size
,
1929 dest
.ssa
.bit_size
== 8 ?
1930 BRW_REGISTER_TYPE_D
:
1931 BRW_REGISTER_TYPE_F
);
1932 nir_ssa_values
[dest
.ssa
.index
] =
1933 bld
.vgrf(reg_type
, dest
.ssa
.num_components
);
1934 return nir_ssa_values
[dest
.ssa
.index
];
1936 /* We don't handle indirects on locals */
1937 assert(dest
.reg
.indirect
== NULL
);
1938 return offset(nir_locals
[dest
.reg
.reg
->index
], bld
,
1939 dest
.reg
.base_offset
* dest
.reg
.reg
->num_components
);
1944 fs_visitor::emit_percomp(const fs_builder
&bld
, const fs_inst
&inst
,
1947 for (unsigned i
= 0; i
< 4; i
++) {
1948 if (!((wr_mask
>> i
) & 1))
1951 fs_inst
*new_inst
= new(mem_ctx
) fs_inst(inst
);
1952 new_inst
->dst
= offset(new_inst
->dst
, bld
, i
);
1953 for (unsigned j
= 0; j
< new_inst
->sources
; j
++)
1954 if (new_inst
->src
[j
].file
== VGRF
)
1955 new_inst
->src
[j
] = offset(new_inst
->src
[j
], bld
, i
);
1962 emit_pixel_interpolater_send(const fs_builder
&bld
,
1967 glsl_interp_mode interpolation
)
1969 struct brw_wm_prog_data
*wm_prog_data
=
1970 brw_wm_prog_data(bld
.shader
->stage_prog_data
);
1972 fs_inst
*inst
= bld
.emit(opcode
, dst
, src
, desc
);
1973 /* 2 floats per slot returned */
1974 inst
->size_written
= 2 * dst
.component_size(inst
->exec_size
);
1975 inst
->pi_noperspective
= interpolation
== INTERP_MODE_NOPERSPECTIVE
;
1977 wm_prog_data
->pulls_bary
= true;
1983 * Computes 1 << x, given a D/UD register containing some value x.
1986 intexp2(const fs_builder
&bld
, const fs_reg
&x
)
1988 assert(x
.type
== BRW_REGISTER_TYPE_UD
|| x
.type
== BRW_REGISTER_TYPE_D
);
1990 fs_reg result
= bld
.vgrf(x
.type
, 1);
1991 fs_reg one
= bld
.vgrf(x
.type
, 1);
1993 bld
.MOV(one
, retype(brw_imm_d(1), one
.type
));
1994 bld
.SHL(result
, one
, x
);
1999 fs_visitor::emit_gs_end_primitive(const nir_src
&vertex_count_nir_src
)
2001 assert(stage
== MESA_SHADER_GEOMETRY
);
2003 struct brw_gs_prog_data
*gs_prog_data
= brw_gs_prog_data(prog_data
);
2005 if (gs_compile
->control_data_header_size_bits
== 0)
2008 /* We can only do EndPrimitive() functionality when the control data
2009 * consists of cut bits. Fortunately, the only time it isn't is when the
2010 * output type is points, in which case EndPrimitive() is a no-op.
2012 if (gs_prog_data
->control_data_format
!=
2013 GEN7_GS_CONTROL_DATA_FORMAT_GSCTL_CUT
) {
2017 /* Cut bits use one bit per vertex. */
2018 assert(gs_compile
->control_data_bits_per_vertex
== 1);
2020 fs_reg vertex_count
= get_nir_src(vertex_count_nir_src
);
2021 vertex_count
.type
= BRW_REGISTER_TYPE_UD
;
2023 /* Cut bit n should be set to 1 if EndPrimitive() was called after emitting
2024 * vertex n, 0 otherwise. So all we need to do here is mark bit
2025 * (vertex_count - 1) % 32 in the cut_bits register to indicate that
2026 * EndPrimitive() was called after emitting vertex (vertex_count - 1);
2027 * vec4_gs_visitor::emit_control_data_bits() will take care of the rest.
2029 * Note that if EndPrimitive() is called before emitting any vertices, this
2030 * will cause us to set bit 31 of the control_data_bits register to 1.
2031 * That's fine because:
2033 * - If max_vertices < 32, then vertex number 31 (zero-based) will never be
2034 * output, so the hardware will ignore cut bit 31.
2036 * - If max_vertices == 32, then vertex number 31 is guaranteed to be the
2037 * last vertex, so setting cut bit 31 has no effect (since the primitive
2038 * is automatically ended when the GS terminates).
2040 * - If max_vertices > 32, then the ir_emit_vertex visitor will reset the
2041 * control_data_bits register to 0 when the first vertex is emitted.
2044 const fs_builder abld
= bld
.annotate("end primitive");
2046 /* control_data_bits |= 1 << ((vertex_count - 1) % 32) */
2047 fs_reg prev_count
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2048 abld
.ADD(prev_count
, vertex_count
, brw_imm_ud(0xffffffffu
));
2049 fs_reg mask
= intexp2(abld
, prev_count
);
2050 /* Note: we're relying on the fact that the GEN SHL instruction only pays
2051 * attention to the lower 5 bits of its second source argument, so on this
2052 * architecture, 1 << (vertex_count - 1) is equivalent to 1 <<
2053 * ((vertex_count - 1) % 32).
2055 abld
.OR(this->control_data_bits
, this->control_data_bits
, mask
);
2059 fs_visitor::emit_gs_control_data_bits(const fs_reg
&vertex_count
)
2061 assert(stage
== MESA_SHADER_GEOMETRY
);
2062 assert(gs_compile
->control_data_bits_per_vertex
!= 0);
2064 struct brw_gs_prog_data
*gs_prog_data
= brw_gs_prog_data(prog_data
);
2066 const fs_builder abld
= bld
.annotate("emit control data bits");
2067 const fs_builder fwa_bld
= bld
.exec_all();
2069 /* We use a single UD register to accumulate control data bits (32 bits
2070 * for each of the SIMD8 channels). So we need to write a DWord (32 bits)
2073 * Unfortunately, the URB_WRITE_SIMD8 message uses 128-bit (OWord) offsets.
2074 * We have select a 128-bit group via the Global and Per-Slot Offsets, then
2075 * use the Channel Mask phase to enable/disable which DWord within that
2076 * group to write. (Remember, different SIMD8 channels may have emitted
2077 * different numbers of vertices, so we may need per-slot offsets.)
2079 * Channel masking presents an annoying problem: we may have to replicate
2080 * the data up to 4 times:
2082 * Msg = Handles, Per-Slot Offsets, Channel Masks, Data, Data, Data, Data.
2084 * To avoid penalizing shaders that emit a small number of vertices, we
2085 * can avoid these sometimes: if the size of the control data header is
2086 * <= 128 bits, then there is only 1 OWord. All SIMD8 channels will land
2087 * land in the same 128-bit group, so we can skip per-slot offsets.
2089 * Similarly, if the control data header is <= 32 bits, there is only one
2090 * DWord, so we can skip channel masks.
2092 enum opcode opcode
= SHADER_OPCODE_URB_WRITE_SIMD8
;
2094 fs_reg channel_mask
, per_slot_offset
;
2096 if (gs_compile
->control_data_header_size_bits
> 32) {
2097 opcode
= SHADER_OPCODE_URB_WRITE_SIMD8_MASKED
;
2098 channel_mask
= vgrf(glsl_type::uint_type
);
2101 if (gs_compile
->control_data_header_size_bits
> 128) {
2102 opcode
= SHADER_OPCODE_URB_WRITE_SIMD8_MASKED_PER_SLOT
;
2103 per_slot_offset
= vgrf(glsl_type::uint_type
);
2106 /* Figure out which DWord we're trying to write to using the formula:
2108 * dword_index = (vertex_count - 1) * bits_per_vertex / 32
2110 * Since bits_per_vertex is a power of two, and is known at compile
2111 * time, this can be optimized to:
2113 * dword_index = (vertex_count - 1) >> (6 - log2(bits_per_vertex))
2115 if (opcode
!= SHADER_OPCODE_URB_WRITE_SIMD8
) {
2116 fs_reg dword_index
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2117 fs_reg prev_count
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2118 abld
.ADD(prev_count
, vertex_count
, brw_imm_ud(0xffffffffu
));
2119 unsigned log2_bits_per_vertex
=
2120 util_last_bit(gs_compile
->control_data_bits_per_vertex
);
2121 abld
.SHR(dword_index
, prev_count
, brw_imm_ud(6u - log2_bits_per_vertex
));
2123 if (per_slot_offset
.file
!= BAD_FILE
) {
2124 /* Set the per-slot offset to dword_index / 4, so that we'll write to
2125 * the appropriate OWord within the control data header.
2127 abld
.SHR(per_slot_offset
, dword_index
, brw_imm_ud(2u));
2130 /* Set the channel masks to 1 << (dword_index % 4), so that we'll
2131 * write to the appropriate DWORD within the OWORD.
2133 fs_reg channel
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2134 fwa_bld
.AND(channel
, dword_index
, brw_imm_ud(3u));
2135 channel_mask
= intexp2(fwa_bld
, channel
);
2136 /* Then the channel masks need to be in bits 23:16. */
2137 fwa_bld
.SHL(channel_mask
, channel_mask
, brw_imm_ud(16u));
2140 /* Store the control data bits in the message payload and send it. */
2142 if (channel_mask
.file
!= BAD_FILE
)
2143 mlen
+= 4; /* channel masks, plus 3 extra copies of the data */
2144 if (per_slot_offset
.file
!= BAD_FILE
)
2147 fs_reg payload
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, mlen
);
2148 fs_reg
*sources
= ralloc_array(mem_ctx
, fs_reg
, mlen
);
2150 sources
[i
++] = fs_reg(retype(brw_vec8_grf(1, 0), BRW_REGISTER_TYPE_UD
));
2151 if (per_slot_offset
.file
!= BAD_FILE
)
2152 sources
[i
++] = per_slot_offset
;
2153 if (channel_mask
.file
!= BAD_FILE
)
2154 sources
[i
++] = channel_mask
;
2156 sources
[i
++] = this->control_data_bits
;
2159 abld
.LOAD_PAYLOAD(payload
, sources
, mlen
, mlen
);
2160 fs_inst
*inst
= abld
.emit(opcode
, reg_undef
, payload
);
2162 /* We need to increment Global Offset by 256-bits to make room for
2163 * Broadwell's extra "Vertex Count" payload at the beginning of the
2164 * URB entry. Since this is an OWord message, Global Offset is counted
2165 * in 128-bit units, so we must set it to 2.
2167 if (gs_prog_data
->static_vertex_count
== -1)
2172 fs_visitor::set_gs_stream_control_data_bits(const fs_reg
&vertex_count
,
2175 /* control_data_bits |= stream_id << ((2 * (vertex_count - 1)) % 32) */
2177 /* Note: we are calling this *before* increasing vertex_count, so
2178 * this->vertex_count == vertex_count - 1 in the formula above.
2181 /* Stream mode uses 2 bits per vertex */
2182 assert(gs_compile
->control_data_bits_per_vertex
== 2);
2184 /* Must be a valid stream */
2185 assert(stream_id
< MAX_VERTEX_STREAMS
);
2187 /* Control data bits are initialized to 0 so we don't have to set any
2188 * bits when sending vertices to stream 0.
2193 const fs_builder abld
= bld
.annotate("set stream control data bits", NULL
);
2195 /* reg::sid = stream_id */
2196 fs_reg sid
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2197 abld
.MOV(sid
, brw_imm_ud(stream_id
));
2199 /* reg:shift_count = 2 * (vertex_count - 1) */
2200 fs_reg shift_count
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2201 abld
.SHL(shift_count
, vertex_count
, brw_imm_ud(1u));
2203 /* Note: we're relying on the fact that the GEN SHL instruction only pays
2204 * attention to the lower 5 bits of its second source argument, so on this
2205 * architecture, stream_id << 2 * (vertex_count - 1) is equivalent to
2206 * stream_id << ((2 * (vertex_count - 1)) % 32).
2208 fs_reg mask
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2209 abld
.SHL(mask
, sid
, shift_count
);
2210 abld
.OR(this->control_data_bits
, this->control_data_bits
, mask
);
2214 fs_visitor::emit_gs_vertex(const nir_src
&vertex_count_nir_src
,
2217 assert(stage
== MESA_SHADER_GEOMETRY
);
2219 struct brw_gs_prog_data
*gs_prog_data
= brw_gs_prog_data(prog_data
);
2221 fs_reg vertex_count
= get_nir_src(vertex_count_nir_src
);
2222 vertex_count
.type
= BRW_REGISTER_TYPE_UD
;
2224 /* Haswell and later hardware ignores the "Render Stream Select" bits
2225 * from the 3DSTATE_STREAMOUT packet when the SOL stage is disabled,
2226 * and instead sends all primitives down the pipeline for rasterization.
2227 * If the SOL stage is enabled, "Render Stream Select" is honored and
2228 * primitives bound to non-zero streams are discarded after stream output.
2230 * Since the only purpose of primives sent to non-zero streams is to
2231 * be recorded by transform feedback, we can simply discard all geometry
2232 * bound to these streams when transform feedback is disabled.
2234 if (stream_id
> 0 && !nir
->info
.has_transform_feedback_varyings
)
2237 /* If we're outputting 32 control data bits or less, then we can wait
2238 * until the shader is over to output them all. Otherwise we need to
2239 * output them as we go. Now is the time to do it, since we're about to
2240 * output the vertex_count'th vertex, so it's guaranteed that the
2241 * control data bits associated with the (vertex_count - 1)th vertex are
2244 if (gs_compile
->control_data_header_size_bits
> 32) {
2245 const fs_builder abld
=
2246 bld
.annotate("emit vertex: emit control data bits");
2248 /* Only emit control data bits if we've finished accumulating a batch
2249 * of 32 bits. This is the case when:
2251 * (vertex_count * bits_per_vertex) % 32 == 0
2253 * (in other words, when the last 5 bits of vertex_count *
2254 * bits_per_vertex are 0). Assuming bits_per_vertex == 2^n for some
2255 * integer n (which is always the case, since bits_per_vertex is
2256 * always 1 or 2), this is equivalent to requiring that the last 5-n
2257 * bits of vertex_count are 0:
2259 * vertex_count & (2^(5-n) - 1) == 0
2261 * 2^(5-n) == 2^5 / 2^n == 32 / bits_per_vertex, so this is
2264 * vertex_count & (32 / bits_per_vertex - 1) == 0
2266 * TODO: If vertex_count is an immediate, we could do some of this math
2267 * at compile time...
2270 abld
.AND(bld
.null_reg_d(), vertex_count
,
2271 brw_imm_ud(32u / gs_compile
->control_data_bits_per_vertex
- 1u));
2272 inst
->conditional_mod
= BRW_CONDITIONAL_Z
;
2274 abld
.IF(BRW_PREDICATE_NORMAL
);
2275 /* If vertex_count is 0, then no control data bits have been
2276 * accumulated yet, so we can skip emitting them.
2278 abld
.CMP(bld
.null_reg_d(), vertex_count
, brw_imm_ud(0u),
2279 BRW_CONDITIONAL_NEQ
);
2280 abld
.IF(BRW_PREDICATE_NORMAL
);
2281 emit_gs_control_data_bits(vertex_count
);
2282 abld
.emit(BRW_OPCODE_ENDIF
);
2284 /* Reset control_data_bits to 0 so we can start accumulating a new
2287 * Note: in the case where vertex_count == 0, this neutralizes the
2288 * effect of any call to EndPrimitive() that the shader may have
2289 * made before outputting its first vertex.
2291 inst
= abld
.MOV(this->control_data_bits
, brw_imm_ud(0u));
2292 inst
->force_writemask_all
= true;
2293 abld
.emit(BRW_OPCODE_ENDIF
);
2296 emit_urb_writes(vertex_count
);
2298 /* In stream mode we have to set control data bits for all vertices
2299 * unless we have disabled control data bits completely (which we do
2300 * do for GL_POINTS outputs that don't use streams).
2302 if (gs_compile
->control_data_header_size_bits
> 0 &&
2303 gs_prog_data
->control_data_format
==
2304 GEN7_GS_CONTROL_DATA_FORMAT_GSCTL_SID
) {
2305 set_gs_stream_control_data_bits(vertex_count
, stream_id
);
2310 fs_visitor::emit_gs_input_load(const fs_reg
&dst
,
2311 const nir_src
&vertex_src
,
2312 unsigned base_offset
,
2313 const nir_src
&offset_src
,
2314 unsigned num_components
,
2315 unsigned first_component
)
2317 struct brw_gs_prog_data
*gs_prog_data
= brw_gs_prog_data(prog_data
);
2318 const unsigned push_reg_count
= gs_prog_data
->base
.urb_read_length
* 8;
2320 /* TODO: figure out push input layout for invocations == 1 */
2321 /* TODO: make this work with 64-bit inputs */
2322 if (gs_prog_data
->invocations
== 1 &&
2323 type_sz(dst
.type
) <= 4 &&
2324 nir_src_is_const(offset_src
) && nir_src_is_const(vertex_src
) &&
2325 4 * (base_offset
+ nir_src_as_uint(offset_src
)) < push_reg_count
) {
2326 int imm_offset
= (base_offset
+ nir_src_as_uint(offset_src
)) * 4 +
2327 nir_src_as_uint(vertex_src
) * push_reg_count
;
2328 for (unsigned i
= 0; i
< num_components
; i
++) {
2329 bld
.MOV(offset(dst
, bld
, i
),
2330 fs_reg(ATTR
, imm_offset
+ i
+ first_component
, dst
.type
));
2335 /* Resort to the pull model. Ensure the VUE handles are provided. */
2336 assert(gs_prog_data
->base
.include_vue_handles
);
2338 unsigned first_icp_handle
= gs_prog_data
->include_primitive_id
? 3 : 2;
2339 fs_reg icp_handle
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2341 if (gs_prog_data
->invocations
== 1) {
2342 if (nir_src_is_const(vertex_src
)) {
2343 /* The vertex index is constant; just select the proper URB handle. */
2345 retype(brw_vec8_grf(first_icp_handle
+ nir_src_as_uint(vertex_src
), 0),
2346 BRW_REGISTER_TYPE_UD
);
2348 /* The vertex index is non-constant. We need to use indirect
2349 * addressing to fetch the proper URB handle.
2351 * First, we start with the sequence <7, 6, 5, 4, 3, 2, 1, 0>
2352 * indicating that channel <n> should read the handle from
2353 * DWord <n>. We convert that to bytes by multiplying by 4.
2355 * Next, we convert the vertex index to bytes by multiplying
2356 * by 32 (shifting by 5), and add the two together. This is
2357 * the final indirect byte offset.
2359 fs_reg sequence
= bld
.vgrf(BRW_REGISTER_TYPE_UW
, 1);
2360 fs_reg channel_offsets
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2361 fs_reg vertex_offset_bytes
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2362 fs_reg icp_offset_bytes
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2364 /* sequence = <7, 6, 5, 4, 3, 2, 1, 0> */
2365 bld
.MOV(sequence
, fs_reg(brw_imm_v(0x76543210)));
2366 /* channel_offsets = 4 * sequence = <28, 24, 20, 16, 12, 8, 4, 0> */
2367 bld
.SHL(channel_offsets
, sequence
, brw_imm_ud(2u));
2368 /* Convert vertex_index to bytes (multiply by 32) */
2369 bld
.SHL(vertex_offset_bytes
,
2370 retype(get_nir_src(vertex_src
), BRW_REGISTER_TYPE_UD
),
2372 bld
.ADD(icp_offset_bytes
, vertex_offset_bytes
, channel_offsets
);
2374 /* Use first_icp_handle as the base offset. There is one register
2375 * of URB handles per vertex, so inform the register allocator that
2376 * we might read up to nir->info.gs.vertices_in registers.
2378 bld
.emit(SHADER_OPCODE_MOV_INDIRECT
, icp_handle
,
2379 retype(brw_vec8_grf(first_icp_handle
, 0), icp_handle
.type
),
2380 fs_reg(icp_offset_bytes
),
2381 brw_imm_ud(nir
->info
.gs
.vertices_in
* REG_SIZE
));
2384 assert(gs_prog_data
->invocations
> 1);
2386 if (nir_src_is_const(vertex_src
)) {
2387 unsigned vertex
= nir_src_as_uint(vertex_src
);
2388 assert(devinfo
->gen
>= 9 || vertex
<= 5);
2390 retype(brw_vec1_grf(first_icp_handle
+ vertex
/ 8, vertex
% 8),
2391 BRW_REGISTER_TYPE_UD
));
2393 /* The vertex index is non-constant. We need to use indirect
2394 * addressing to fetch the proper URB handle.
2397 fs_reg icp_offset_bytes
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2399 /* Convert vertex_index to bytes (multiply by 4) */
2400 bld
.SHL(icp_offset_bytes
,
2401 retype(get_nir_src(vertex_src
), BRW_REGISTER_TYPE_UD
),
2404 /* Use first_icp_handle as the base offset. There is one DWord
2405 * of URB handles per vertex, so inform the register allocator that
2406 * we might read up to ceil(nir->info.gs.vertices_in / 8) registers.
2408 bld
.emit(SHADER_OPCODE_MOV_INDIRECT
, icp_handle
,
2409 retype(brw_vec8_grf(first_icp_handle
, 0), icp_handle
.type
),
2410 fs_reg(icp_offset_bytes
),
2411 brw_imm_ud(DIV_ROUND_UP(nir
->info
.gs
.vertices_in
, 8) *
2418 fs_reg tmp_dst
= dst
;
2419 fs_reg indirect_offset
= get_nir_src(offset_src
);
2420 unsigned num_iterations
= 1;
2421 unsigned orig_num_components
= num_components
;
2423 if (type_sz(dst
.type
) == 8) {
2424 if (num_components
> 2) {
2428 fs_reg tmp
= fs_reg(VGRF
, alloc
.allocate(4), dst
.type
);
2430 first_component
= first_component
/ 2;
2433 for (unsigned iter
= 0; iter
< num_iterations
; iter
++) {
2434 if (nir_src_is_const(offset_src
)) {
2435 /* Constant indexing - use global offset. */
2436 if (first_component
!= 0) {
2437 unsigned read_components
= num_components
+ first_component
;
2438 fs_reg tmp
= bld
.vgrf(dst
.type
, read_components
);
2439 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8
, tmp
, icp_handle
);
2440 inst
->size_written
= read_components
*
2441 tmp
.component_size(inst
->exec_size
);
2442 for (unsigned i
= 0; i
< num_components
; i
++) {
2443 bld
.MOV(offset(tmp_dst
, bld
, i
),
2444 offset(tmp
, bld
, i
+ first_component
));
2447 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8
, tmp_dst
,
2449 inst
->size_written
= num_components
*
2450 tmp_dst
.component_size(inst
->exec_size
);
2452 inst
->offset
= base_offset
+ nir_src_as_uint(offset_src
);
2455 /* Indirect indexing - use per-slot offsets as well. */
2456 const fs_reg srcs
[] = { icp_handle
, indirect_offset
};
2457 unsigned read_components
= num_components
+ first_component
;
2458 fs_reg tmp
= bld
.vgrf(dst
.type
, read_components
);
2459 fs_reg payload
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 2);
2460 bld
.LOAD_PAYLOAD(payload
, srcs
, ARRAY_SIZE(srcs
), 0);
2461 if (first_component
!= 0) {
2462 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT
, tmp
,
2464 inst
->size_written
= read_components
*
2465 tmp
.component_size(inst
->exec_size
);
2466 for (unsigned i
= 0; i
< num_components
; i
++) {
2467 bld
.MOV(offset(tmp_dst
, bld
, i
),
2468 offset(tmp
, bld
, i
+ first_component
));
2471 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT
, tmp_dst
,
2473 inst
->size_written
= num_components
*
2474 tmp_dst
.component_size(inst
->exec_size
);
2476 inst
->offset
= base_offset
;
2480 if (type_sz(dst
.type
) == 8) {
2481 shuffle_from_32bit_read(bld
,
2482 offset(dst
, bld
, iter
* 2),
2483 retype(tmp_dst
, BRW_REGISTER_TYPE_D
),
2488 if (num_iterations
> 1) {
2489 num_components
= orig_num_components
- 2;
2490 if(nir_src_is_const(offset_src
)) {
2493 fs_reg new_indirect
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2494 bld
.ADD(new_indirect
, indirect_offset
, brw_imm_ud(1u));
2495 indirect_offset
= new_indirect
;
2502 fs_visitor::get_indirect_offset(nir_intrinsic_instr
*instr
)
2504 nir_src
*offset_src
= nir_get_io_offset_src(instr
);
2506 if (nir_src_is_const(*offset_src
)) {
2507 /* The only constant offset we should find is 0. brw_nir.c's
2508 * add_const_offset_to_base() will fold other constant offsets
2509 * into instr->const_index[0].
2511 assert(nir_src_as_uint(*offset_src
) == 0);
2515 return get_nir_src(*offset_src
);
2519 fs_visitor::nir_emit_vs_intrinsic(const fs_builder
&bld
,
2520 nir_intrinsic_instr
*instr
)
2522 assert(stage
== MESA_SHADER_VERTEX
);
2525 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
2526 dest
= get_nir_dest(instr
->dest
);
2528 switch (instr
->intrinsic
) {
2529 case nir_intrinsic_load_vertex_id
:
2530 case nir_intrinsic_load_base_vertex
:
2531 unreachable("should be lowered by nir_lower_system_values()");
2533 case nir_intrinsic_load_input
: {
2534 fs_reg src
= fs_reg(ATTR
, nir_intrinsic_base(instr
) * 4, dest
.type
);
2535 unsigned first_component
= nir_intrinsic_component(instr
);
2536 unsigned num_components
= instr
->num_components
;
2538 src
= offset(src
, bld
, nir_src_as_uint(instr
->src
[0]));
2540 if (type_sz(dest
.type
) == 8)
2541 first_component
/= 2;
2543 /* For 16-bit support maybe a temporary will be needed to copy from
2546 shuffle_from_32bit_read(bld
, dest
, retype(src
, BRW_REGISTER_TYPE_D
),
2547 first_component
, num_components
);
2551 case nir_intrinsic_load_vertex_id_zero_base
:
2552 case nir_intrinsic_load_instance_id
:
2553 case nir_intrinsic_load_base_instance
:
2554 case nir_intrinsic_load_draw_id
:
2555 case nir_intrinsic_load_first_vertex
:
2556 case nir_intrinsic_load_is_indexed_draw
:
2557 unreachable("lowered by brw_nir_lower_vs_inputs");
2560 nir_emit_intrinsic(bld
, instr
);
2566 fs_visitor::nir_emit_tcs_intrinsic(const fs_builder
&bld
,
2567 nir_intrinsic_instr
*instr
)
2569 assert(stage
== MESA_SHADER_TESS_CTRL
);
2570 struct brw_tcs_prog_key
*tcs_key
= (struct brw_tcs_prog_key
*) key
;
2571 struct brw_tcs_prog_data
*tcs_prog_data
= brw_tcs_prog_data(prog_data
);
2574 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
2575 dst
= get_nir_dest(instr
->dest
);
2577 switch (instr
->intrinsic
) {
2578 case nir_intrinsic_load_primitive_id
:
2579 bld
.MOV(dst
, fs_reg(brw_vec1_grf(0, 1)));
2581 case nir_intrinsic_load_invocation_id
:
2582 bld
.MOV(retype(dst
, invocation_id
.type
), invocation_id
);
2584 case nir_intrinsic_load_patch_vertices_in
:
2585 bld
.MOV(retype(dst
, BRW_REGISTER_TYPE_D
),
2586 brw_imm_d(tcs_key
->input_vertices
));
2589 case nir_intrinsic_barrier
: {
2590 if (tcs_prog_data
->instances
== 1)
2593 fs_reg m0
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2594 fs_reg m0_2
= component(m0
, 2);
2596 const fs_builder chanbld
= bld
.exec_all().group(1, 0);
2598 /* Zero the message header */
2599 bld
.exec_all().MOV(m0
, brw_imm_ud(0u));
2601 if (devinfo
->gen
< 11) {
2602 /* Copy "Barrier ID" from r0.2, bits 16:13 */
2603 chanbld
.AND(m0_2
, retype(brw_vec1_grf(0, 2), BRW_REGISTER_TYPE_UD
),
2604 brw_imm_ud(INTEL_MASK(16, 13)));
2606 /* Shift it up to bits 27:24. */
2607 chanbld
.SHL(m0_2
, m0_2
, brw_imm_ud(11));
2609 chanbld
.AND(m0_2
, retype(brw_vec1_grf(0, 2), BRW_REGISTER_TYPE_UD
),
2610 brw_imm_ud(INTEL_MASK(30, 24)));
2613 /* Set the Barrier Count and the enable bit */
2614 if (devinfo
->gen
< 11) {
2615 chanbld
.OR(m0_2
, m0_2
,
2616 brw_imm_ud(tcs_prog_data
->instances
<< 9 | (1 << 15)));
2618 chanbld
.OR(m0_2
, m0_2
,
2619 brw_imm_ud(tcs_prog_data
->instances
<< 8 | (1 << 15)));
2622 bld
.emit(SHADER_OPCODE_BARRIER
, bld
.null_reg_ud(), m0
);
2626 case nir_intrinsic_load_input
:
2627 unreachable("nir_lower_io should never give us these.");
2630 case nir_intrinsic_load_per_vertex_input
: {
2631 fs_reg indirect_offset
= get_indirect_offset(instr
);
2632 unsigned imm_offset
= instr
->const_index
[0];
2634 const nir_src
&vertex_src
= instr
->src
[0];
2640 if (nir_src_is_const(vertex_src
)) {
2641 /* Emit a MOV to resolve <0,1,0> regioning. */
2642 icp_handle
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2643 unsigned vertex
= nir_src_as_uint(vertex_src
);
2645 retype(brw_vec1_grf(1 + (vertex
>> 3), vertex
& 7),
2646 BRW_REGISTER_TYPE_UD
));
2647 } else if (tcs_prog_data
->instances
== 1 &&
2648 nir_src_as_intrinsic(vertex_src
) != NULL
&&
2649 nir_src_as_intrinsic(vertex_src
)->intrinsic
== nir_intrinsic_load_invocation_id
) {
2650 /* For the common case of only 1 instance, an array index of
2651 * gl_InvocationID means reading g1. Skip all the indirect work.
2653 icp_handle
= retype(brw_vec8_grf(1, 0), BRW_REGISTER_TYPE_UD
);
2655 /* The vertex index is non-constant. We need to use indirect
2656 * addressing to fetch the proper URB handle.
2658 icp_handle
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2660 /* Each ICP handle is a single DWord (4 bytes) */
2661 fs_reg vertex_offset_bytes
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2662 bld
.SHL(vertex_offset_bytes
,
2663 retype(get_nir_src(vertex_src
), BRW_REGISTER_TYPE_UD
),
2666 /* Start at g1. We might read up to 4 registers. */
2667 bld
.emit(SHADER_OPCODE_MOV_INDIRECT
, icp_handle
,
2668 retype(brw_vec8_grf(1, 0), icp_handle
.type
), vertex_offset_bytes
,
2669 brw_imm_ud(4 * REG_SIZE
));
2672 /* We can only read two double components with each URB read, so
2673 * we send two read messages in that case, each one loading up to
2674 * two double components.
2676 unsigned num_iterations
= 1;
2677 unsigned num_components
= instr
->num_components
;
2678 unsigned first_component
= nir_intrinsic_component(instr
);
2679 fs_reg orig_dst
= dst
;
2680 if (type_sz(dst
.type
) == 8) {
2681 first_component
= first_component
/ 2;
2682 if (instr
->num_components
> 2) {
2687 fs_reg tmp
= fs_reg(VGRF
, alloc
.allocate(4), dst
.type
);
2691 for (unsigned iter
= 0; iter
< num_iterations
; iter
++) {
2692 if (indirect_offset
.file
== BAD_FILE
) {
2693 /* Constant indexing - use global offset. */
2694 if (first_component
!= 0) {
2695 unsigned read_components
= num_components
+ first_component
;
2696 fs_reg tmp
= bld
.vgrf(dst
.type
, read_components
);
2697 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8
, tmp
, icp_handle
);
2698 for (unsigned i
= 0; i
< num_components
; i
++) {
2699 bld
.MOV(offset(dst
, bld
, i
),
2700 offset(tmp
, bld
, i
+ first_component
));
2703 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8
, dst
, icp_handle
);
2705 inst
->offset
= imm_offset
;
2708 /* Indirect indexing - use per-slot offsets as well. */
2709 const fs_reg srcs
[] = { icp_handle
, indirect_offset
};
2710 fs_reg payload
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 2);
2711 bld
.LOAD_PAYLOAD(payload
, srcs
, ARRAY_SIZE(srcs
), 0);
2712 if (first_component
!= 0) {
2713 unsigned read_components
= num_components
+ first_component
;
2714 fs_reg tmp
= bld
.vgrf(dst
.type
, read_components
);
2715 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT
, tmp
,
2717 for (unsigned i
= 0; i
< num_components
; i
++) {
2718 bld
.MOV(offset(dst
, bld
, i
),
2719 offset(tmp
, bld
, i
+ first_component
));
2722 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT
, dst
,
2725 inst
->offset
= imm_offset
;
2728 inst
->size_written
= (num_components
+ first_component
) *
2729 inst
->dst
.component_size(inst
->exec_size
);
2731 /* If we are reading 64-bit data using 32-bit read messages we need
2732 * build proper 64-bit data elements by shuffling the low and high
2733 * 32-bit components around like we do for other things like UBOs
2736 if (type_sz(dst
.type
) == 8) {
2737 shuffle_from_32bit_read(bld
,
2738 offset(orig_dst
, bld
, iter
* 2),
2739 retype(dst
, BRW_REGISTER_TYPE_D
),
2743 /* Copy the temporary to the destination to deal with writemasking.
2745 * Also attempt to deal with gl_PointSize being in the .w component.
2747 if (inst
->offset
== 0 && indirect_offset
.file
== BAD_FILE
) {
2748 assert(type_sz(dst
.type
) < 8);
2749 inst
->dst
= bld
.vgrf(dst
.type
, 4);
2750 inst
->size_written
= 4 * REG_SIZE
;
2751 bld
.MOV(dst
, offset(inst
->dst
, bld
, 3));
2754 /* If we are loading double data and we need a second read message
2755 * adjust the write offset
2757 if (num_iterations
> 1) {
2758 num_components
= instr
->num_components
- 2;
2765 case nir_intrinsic_load_output
:
2766 case nir_intrinsic_load_per_vertex_output
: {
2767 fs_reg indirect_offset
= get_indirect_offset(instr
);
2768 unsigned imm_offset
= instr
->const_index
[0];
2769 unsigned first_component
= nir_intrinsic_component(instr
);
2772 if (indirect_offset
.file
== BAD_FILE
) {
2773 /* Replicate the patch handle to all enabled channels */
2774 fs_reg patch_handle
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2775 bld
.MOV(patch_handle
,
2776 retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_UD
));
2779 if (first_component
!= 0) {
2780 unsigned read_components
=
2781 instr
->num_components
+ first_component
;
2782 fs_reg tmp
= bld
.vgrf(dst
.type
, read_components
);
2783 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8
, tmp
,
2785 inst
->size_written
= read_components
* REG_SIZE
;
2786 for (unsigned i
= 0; i
< instr
->num_components
; i
++) {
2787 bld
.MOV(offset(dst
, bld
, i
),
2788 offset(tmp
, bld
, i
+ first_component
));
2791 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8
, dst
,
2793 inst
->size_written
= instr
->num_components
* REG_SIZE
;
2795 inst
->offset
= imm_offset
;
2799 /* Indirect indexing - use per-slot offsets as well. */
2800 const fs_reg srcs
[] = {
2801 retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_UD
),
2804 fs_reg payload
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 2);
2805 bld
.LOAD_PAYLOAD(payload
, srcs
, ARRAY_SIZE(srcs
), 0);
2806 if (first_component
!= 0) {
2807 unsigned read_components
=
2808 instr
->num_components
+ first_component
;
2809 fs_reg tmp
= bld
.vgrf(dst
.type
, read_components
);
2810 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT
, tmp
,
2812 inst
->size_written
= read_components
* REG_SIZE
;
2813 for (unsigned i
= 0; i
< instr
->num_components
; i
++) {
2814 bld
.MOV(offset(dst
, bld
, i
),
2815 offset(tmp
, bld
, i
+ first_component
));
2818 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT
, dst
,
2820 inst
->size_written
= instr
->num_components
* REG_SIZE
;
2822 inst
->offset
= imm_offset
;
2828 case nir_intrinsic_store_output
:
2829 case nir_intrinsic_store_per_vertex_output
: {
2830 fs_reg value
= get_nir_src(instr
->src
[0]);
2831 bool is_64bit
= (instr
->src
[0].is_ssa
?
2832 instr
->src
[0].ssa
->bit_size
: instr
->src
[0].reg
.reg
->bit_size
) == 64;
2833 fs_reg indirect_offset
= get_indirect_offset(instr
);
2834 unsigned imm_offset
= instr
->const_index
[0];
2835 unsigned mask
= instr
->const_index
[1];
2836 unsigned header_regs
= 0;
2838 srcs
[header_regs
++] = retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_UD
);
2840 if (indirect_offset
.file
!= BAD_FILE
) {
2841 srcs
[header_regs
++] = indirect_offset
;
2847 unsigned num_components
= util_last_bit(mask
);
2850 /* We can only pack two 64-bit components in a single message, so send
2851 * 2 messages if we have more components
2853 unsigned num_iterations
= 1;
2854 unsigned iter_components
= num_components
;
2855 unsigned first_component
= nir_intrinsic_component(instr
);
2857 first_component
= first_component
/ 2;
2858 if (instr
->num_components
> 2) {
2860 iter_components
= 2;
2864 mask
= mask
<< first_component
;
2866 for (unsigned iter
= 0; iter
< num_iterations
; iter
++) {
2867 if (!is_64bit
&& mask
!= WRITEMASK_XYZW
) {
2868 srcs
[header_regs
++] = brw_imm_ud(mask
<< 16);
2869 opcode
= indirect_offset
.file
!= BAD_FILE
?
2870 SHADER_OPCODE_URB_WRITE_SIMD8_MASKED_PER_SLOT
:
2871 SHADER_OPCODE_URB_WRITE_SIMD8_MASKED
;
2872 } else if (is_64bit
&& ((mask
& WRITEMASK_XY
) != WRITEMASK_XY
)) {
2873 /* Expand the 64-bit mask to 32-bit channels. We only handle
2874 * two channels in each iteration, so we only care about X/Y.
2876 unsigned mask32
= 0;
2877 if (mask
& WRITEMASK_X
)
2878 mask32
|= WRITEMASK_XY
;
2879 if (mask
& WRITEMASK_Y
)
2880 mask32
|= WRITEMASK_ZW
;
2882 /* If the mask does not include any of the channels X or Y there
2883 * is nothing to do in this iteration. Move on to the next couple
2884 * of 64-bit channels.
2892 srcs
[header_regs
++] = brw_imm_ud(mask32
<< 16);
2893 opcode
= indirect_offset
.file
!= BAD_FILE
?
2894 SHADER_OPCODE_URB_WRITE_SIMD8_MASKED_PER_SLOT
:
2895 SHADER_OPCODE_URB_WRITE_SIMD8_MASKED
;
2897 opcode
= indirect_offset
.file
!= BAD_FILE
?
2898 SHADER_OPCODE_URB_WRITE_SIMD8_PER_SLOT
:
2899 SHADER_OPCODE_URB_WRITE_SIMD8
;
2902 for (unsigned i
= 0; i
< iter_components
; i
++) {
2903 if (!(mask
& (1 << (i
+ first_component
))))
2907 srcs
[header_regs
+ i
+ first_component
] = offset(value
, bld
, i
);
2909 /* We need to shuffle the 64-bit data to match the layout
2910 * expected by our 32-bit URB write messages. We use a temporary
2913 unsigned channel
= iter
* 2 + i
;
2914 fs_reg dest
= shuffle_for_32bit_write(bld
, value
, channel
, 1);
2916 srcs
[header_regs
+ (i
+ first_component
) * 2] = dest
;
2917 srcs
[header_regs
+ (i
+ first_component
) * 2 + 1] =
2918 offset(dest
, bld
, 1);
2923 header_regs
+ (is_64bit
? 2 * iter_components
: iter_components
) +
2924 (is_64bit
? 2 * first_component
: first_component
);
2926 bld
.vgrf(BRW_REGISTER_TYPE_UD
, mlen
);
2927 bld
.LOAD_PAYLOAD(payload
, srcs
, mlen
, header_regs
);
2929 fs_inst
*inst
= bld
.emit(opcode
, bld
.null_reg_ud(), payload
);
2930 inst
->offset
= imm_offset
;
2933 /* If this is a 64-bit attribute, select the next two 64-bit channels
2934 * to be handled in the next iteration.
2945 nir_emit_intrinsic(bld
, instr
);
2951 fs_visitor::nir_emit_tes_intrinsic(const fs_builder
&bld
,
2952 nir_intrinsic_instr
*instr
)
2954 assert(stage
== MESA_SHADER_TESS_EVAL
);
2955 struct brw_tes_prog_data
*tes_prog_data
= brw_tes_prog_data(prog_data
);
2958 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
2959 dest
= get_nir_dest(instr
->dest
);
2961 switch (instr
->intrinsic
) {
2962 case nir_intrinsic_load_primitive_id
:
2963 bld
.MOV(dest
, fs_reg(brw_vec1_grf(0, 1)));
2965 case nir_intrinsic_load_tess_coord
:
2966 /* gl_TessCoord is part of the payload in g1-3 */
2967 for (unsigned i
= 0; i
< 3; i
++) {
2968 bld
.MOV(offset(dest
, bld
, i
), fs_reg(brw_vec8_grf(1 + i
, 0)));
2972 case nir_intrinsic_load_input
:
2973 case nir_intrinsic_load_per_vertex_input
: {
2974 fs_reg indirect_offset
= get_indirect_offset(instr
);
2975 unsigned imm_offset
= instr
->const_index
[0];
2976 unsigned first_component
= nir_intrinsic_component(instr
);
2978 if (type_sz(dest
.type
) == 8) {
2979 first_component
= first_component
/ 2;
2983 if (indirect_offset
.file
== BAD_FILE
) {
2984 /* Arbitrarily only push up to 32 vec4 slots worth of data,
2985 * which is 16 registers (since each holds 2 vec4 slots).
2987 unsigned slot_count
= 1;
2988 if (type_sz(dest
.type
) == 8 && instr
->num_components
> 2)
2991 const unsigned max_push_slots
= 32;
2992 if (imm_offset
+ slot_count
<= max_push_slots
) {
2993 fs_reg src
= fs_reg(ATTR
, imm_offset
/ 2, dest
.type
);
2994 for (int i
= 0; i
< instr
->num_components
; i
++) {
2995 unsigned comp
= 16 / type_sz(dest
.type
) * (imm_offset
% 2) +
2996 i
+ first_component
;
2997 bld
.MOV(offset(dest
, bld
, i
), component(src
, comp
));
3000 tes_prog_data
->base
.urb_read_length
=
3001 MAX2(tes_prog_data
->base
.urb_read_length
,
3002 DIV_ROUND_UP(imm_offset
+ slot_count
, 2));
3004 /* Replicate the patch handle to all enabled channels */
3005 const fs_reg srcs
[] = {
3006 retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_UD
)
3008 fs_reg patch_handle
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
3009 bld
.LOAD_PAYLOAD(patch_handle
, srcs
, ARRAY_SIZE(srcs
), 0);
3011 if (first_component
!= 0) {
3012 unsigned read_components
=
3013 instr
->num_components
+ first_component
;
3014 fs_reg tmp
= bld
.vgrf(dest
.type
, read_components
);
3015 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8
, tmp
,
3017 inst
->size_written
= read_components
* REG_SIZE
;
3018 for (unsigned i
= 0; i
< instr
->num_components
; i
++) {
3019 bld
.MOV(offset(dest
, bld
, i
),
3020 offset(tmp
, bld
, i
+ first_component
));
3023 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8
, dest
,
3025 inst
->size_written
= instr
->num_components
* REG_SIZE
;
3028 inst
->offset
= imm_offset
;
3031 /* Indirect indexing - use per-slot offsets as well. */
3033 /* We can only read two double components with each URB read, so
3034 * we send two read messages in that case, each one loading up to
3035 * two double components.
3037 unsigned num_iterations
= 1;
3038 unsigned num_components
= instr
->num_components
;
3039 fs_reg orig_dest
= dest
;
3040 if (type_sz(dest
.type
) == 8) {
3041 if (instr
->num_components
> 2) {
3045 fs_reg tmp
= fs_reg(VGRF
, alloc
.allocate(4), dest
.type
);
3049 for (unsigned iter
= 0; iter
< num_iterations
; iter
++) {
3050 const fs_reg srcs
[] = {
3051 retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_UD
),
3054 fs_reg payload
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 2);
3055 bld
.LOAD_PAYLOAD(payload
, srcs
, ARRAY_SIZE(srcs
), 0);
3057 if (first_component
!= 0) {
3058 unsigned read_components
=
3059 num_components
+ first_component
;
3060 fs_reg tmp
= bld
.vgrf(dest
.type
, read_components
);
3061 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT
, tmp
,
3063 for (unsigned i
= 0; i
< num_components
; i
++) {
3064 bld
.MOV(offset(dest
, bld
, i
),
3065 offset(tmp
, bld
, i
+ first_component
));
3068 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT
, dest
,
3072 inst
->offset
= imm_offset
;
3073 inst
->size_written
= (num_components
+ first_component
) *
3074 inst
->dst
.component_size(inst
->exec_size
);
3076 /* If we are reading 64-bit data using 32-bit read messages we need
3077 * build proper 64-bit data elements by shuffling the low and high
3078 * 32-bit components around like we do for other things like UBOs
3081 if (type_sz(dest
.type
) == 8) {
3082 shuffle_from_32bit_read(bld
,
3083 offset(orig_dest
, bld
, iter
* 2),
3084 retype(dest
, BRW_REGISTER_TYPE_D
),
3088 /* If we are loading double data and we need a second read message
3091 if (num_iterations
> 1) {
3092 num_components
= instr
->num_components
- 2;
3100 nir_emit_intrinsic(bld
, instr
);
3106 fs_visitor::nir_emit_gs_intrinsic(const fs_builder
&bld
,
3107 nir_intrinsic_instr
*instr
)
3109 assert(stage
== MESA_SHADER_GEOMETRY
);
3110 fs_reg indirect_offset
;
3113 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
3114 dest
= get_nir_dest(instr
->dest
);
3116 switch (instr
->intrinsic
) {
3117 case nir_intrinsic_load_primitive_id
:
3118 assert(stage
== MESA_SHADER_GEOMETRY
);
3119 assert(brw_gs_prog_data(prog_data
)->include_primitive_id
);
3120 bld
.MOV(retype(dest
, BRW_REGISTER_TYPE_UD
),
3121 retype(fs_reg(brw_vec8_grf(2, 0)), BRW_REGISTER_TYPE_UD
));
3124 case nir_intrinsic_load_input
:
3125 unreachable("load_input intrinsics are invalid for the GS stage");
3127 case nir_intrinsic_load_per_vertex_input
:
3128 emit_gs_input_load(dest
, instr
->src
[0], instr
->const_index
[0],
3129 instr
->src
[1], instr
->num_components
,
3130 nir_intrinsic_component(instr
));
3133 case nir_intrinsic_emit_vertex_with_counter
:
3134 emit_gs_vertex(instr
->src
[0], instr
->const_index
[0]);
3137 case nir_intrinsic_end_primitive_with_counter
:
3138 emit_gs_end_primitive(instr
->src
[0]);
3141 case nir_intrinsic_set_vertex_count
:
3142 bld
.MOV(this->final_gs_vertex_count
, get_nir_src(instr
->src
[0]));
3145 case nir_intrinsic_load_invocation_id
: {
3146 fs_reg val
= nir_system_values
[SYSTEM_VALUE_INVOCATION_ID
];
3147 assert(val
.file
!= BAD_FILE
);
3148 dest
.type
= val
.type
;
3154 nir_emit_intrinsic(bld
, instr
);
3160 * Fetch the current render target layer index.
3163 fetch_render_target_array_index(const fs_builder
&bld
)
3165 if (bld
.shader
->devinfo
->gen
>= 6) {
3166 /* The render target array index is provided in the thread payload as
3167 * bits 26:16 of r0.0.
3169 const fs_reg idx
= bld
.vgrf(BRW_REGISTER_TYPE_UD
);
3170 bld
.AND(idx
, brw_uw1_reg(BRW_GENERAL_REGISTER_FILE
, 0, 1),
3174 /* Pre-SNB we only ever render into the first layer of the framebuffer
3175 * since layered rendering is not implemented.
3177 return brw_imm_ud(0);
3182 * Fake non-coherent framebuffer read implemented using TXF to fetch from the
3183 * framebuffer at the current fragment coordinates and sample index.
3186 fs_visitor::emit_non_coherent_fb_read(const fs_builder
&bld
, const fs_reg
&dst
,
3189 const struct gen_device_info
*devinfo
= bld
.shader
->devinfo
;
3191 assert(bld
.shader
->stage
== MESA_SHADER_FRAGMENT
);
3192 const brw_wm_prog_key
*wm_key
=
3193 reinterpret_cast<const brw_wm_prog_key
*>(key
);
3194 assert(!wm_key
->coherent_fb_fetch
);
3195 const struct brw_wm_prog_data
*wm_prog_data
=
3196 brw_wm_prog_data(stage_prog_data
);
3198 /* Calculate the surface index relative to the start of the texture binding
3199 * table block, since that's what the texturing messages expect.
3201 const unsigned surface
= target
+
3202 wm_prog_data
->binding_table
.render_target_read_start
-
3203 wm_prog_data
->base
.binding_table
.texture_start
;
3205 /* Calculate the fragment coordinates. */
3206 const fs_reg coords
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 3);
3207 bld
.MOV(offset(coords
, bld
, 0), pixel_x
);
3208 bld
.MOV(offset(coords
, bld
, 1), pixel_y
);
3209 bld
.MOV(offset(coords
, bld
, 2), fetch_render_target_array_index(bld
));
3211 /* Calculate the sample index and MCS payload when multisampling. Luckily
3212 * the MCS fetch message behaves deterministically for UMS surfaces, so it
3213 * shouldn't be necessary to recompile based on whether the framebuffer is
3216 if (wm_key
->multisample_fbo
&&
3217 nir_system_values
[SYSTEM_VALUE_SAMPLE_ID
].file
== BAD_FILE
)
3218 nir_system_values
[SYSTEM_VALUE_SAMPLE_ID
] = *emit_sampleid_setup();
3220 const fs_reg sample
= nir_system_values
[SYSTEM_VALUE_SAMPLE_ID
];
3221 const fs_reg mcs
= wm_key
->multisample_fbo
?
3222 emit_mcs_fetch(coords
, 3, brw_imm_ud(surface
), fs_reg()) : fs_reg();
3224 /* Use either a normal or a CMS texel fetch message depending on whether
3225 * the framebuffer is single or multisample. On SKL+ use the wide CMS
3226 * message just in case the framebuffer uses 16x multisampling, it should
3227 * be equivalent to the normal CMS fetch for lower multisampling modes.
3229 const opcode op
= !wm_key
->multisample_fbo
? SHADER_OPCODE_TXF_LOGICAL
:
3230 devinfo
->gen
>= 9 ? SHADER_OPCODE_TXF_CMS_W_LOGICAL
:
3231 SHADER_OPCODE_TXF_CMS_LOGICAL
;
3233 /* Emit the instruction. */
3234 fs_reg srcs
[TEX_LOGICAL_NUM_SRCS
];
3235 srcs
[TEX_LOGICAL_SRC_COORDINATE
] = coords
;
3236 srcs
[TEX_LOGICAL_SRC_LOD
] = brw_imm_ud(0);
3237 srcs
[TEX_LOGICAL_SRC_SAMPLE_INDEX
] = sample
;
3238 srcs
[TEX_LOGICAL_SRC_MCS
] = mcs
;
3239 srcs
[TEX_LOGICAL_SRC_SURFACE
] = brw_imm_ud(surface
);
3240 srcs
[TEX_LOGICAL_SRC_SAMPLER
] = brw_imm_ud(0);
3241 srcs
[TEX_LOGICAL_SRC_COORD_COMPONENTS
] = brw_imm_ud(3);
3242 srcs
[TEX_LOGICAL_SRC_GRAD_COMPONENTS
] = brw_imm_ud(0);
3244 fs_inst
*inst
= bld
.emit(op
, dst
, srcs
, ARRAY_SIZE(srcs
));
3245 inst
->size_written
= 4 * inst
->dst
.component_size(inst
->exec_size
);
3251 * Actual coherent framebuffer read implemented using the native render target
3252 * read message. Requires SKL+.
3255 emit_coherent_fb_read(const fs_builder
&bld
, const fs_reg
&dst
, unsigned target
)
3257 assert(bld
.shader
->devinfo
->gen
>= 9);
3258 fs_inst
*inst
= bld
.emit(FS_OPCODE_FB_READ_LOGICAL
, dst
);
3259 inst
->target
= target
;
3260 inst
->size_written
= 4 * inst
->dst
.component_size(inst
->exec_size
);
3266 alloc_temporary(const fs_builder
&bld
, unsigned size
, fs_reg
*regs
, unsigned n
)
3268 if (n
&& regs
[0].file
!= BAD_FILE
) {
3272 const fs_reg tmp
= bld
.vgrf(BRW_REGISTER_TYPE_F
, size
);
3274 for (unsigned i
= 0; i
< n
; i
++)
3282 alloc_frag_output(fs_visitor
*v
, unsigned location
)
3284 assert(v
->stage
== MESA_SHADER_FRAGMENT
);
3285 const brw_wm_prog_key
*const key
=
3286 reinterpret_cast<const brw_wm_prog_key
*>(v
->key
);
3287 const unsigned l
= GET_FIELD(location
, BRW_NIR_FRAG_OUTPUT_LOCATION
);
3288 const unsigned i
= GET_FIELD(location
, BRW_NIR_FRAG_OUTPUT_INDEX
);
3290 if (i
> 0 || (key
->force_dual_color_blend
&& l
== FRAG_RESULT_DATA1
))
3291 return alloc_temporary(v
->bld
, 4, &v
->dual_src_output
, 1);
3293 else if (l
== FRAG_RESULT_COLOR
)
3294 return alloc_temporary(v
->bld
, 4, v
->outputs
,
3295 MAX2(key
->nr_color_regions
, 1));
3297 else if (l
== FRAG_RESULT_DEPTH
)
3298 return alloc_temporary(v
->bld
, 1, &v
->frag_depth
, 1);
3300 else if (l
== FRAG_RESULT_STENCIL
)
3301 return alloc_temporary(v
->bld
, 1, &v
->frag_stencil
, 1);
3303 else if (l
== FRAG_RESULT_SAMPLE_MASK
)
3304 return alloc_temporary(v
->bld
, 1, &v
->sample_mask
, 1);
3306 else if (l
>= FRAG_RESULT_DATA0
&&
3307 l
< FRAG_RESULT_DATA0
+ BRW_MAX_DRAW_BUFFERS
)
3308 return alloc_temporary(v
->bld
, 4,
3309 &v
->outputs
[l
- FRAG_RESULT_DATA0
], 1);
3312 unreachable("Invalid location");
3316 fs_visitor::nir_emit_fs_intrinsic(const fs_builder
&bld
,
3317 nir_intrinsic_instr
*instr
)
3319 assert(stage
== MESA_SHADER_FRAGMENT
);
3322 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
3323 dest
= get_nir_dest(instr
->dest
);
3325 switch (instr
->intrinsic
) {
3326 case nir_intrinsic_load_front_face
:
3327 bld
.MOV(retype(dest
, BRW_REGISTER_TYPE_D
),
3328 *emit_frontfacing_interpolation());
3331 case nir_intrinsic_load_sample_pos
: {
3332 fs_reg sample_pos
= nir_system_values
[SYSTEM_VALUE_SAMPLE_POS
];
3333 assert(sample_pos
.file
!= BAD_FILE
);
3334 dest
.type
= sample_pos
.type
;
3335 bld
.MOV(dest
, sample_pos
);
3336 bld
.MOV(offset(dest
, bld
, 1), offset(sample_pos
, bld
, 1));
3340 case nir_intrinsic_load_layer_id
:
3341 dest
.type
= BRW_REGISTER_TYPE_UD
;
3342 bld
.MOV(dest
, fetch_render_target_array_index(bld
));
3345 case nir_intrinsic_load_helper_invocation
:
3346 case nir_intrinsic_load_sample_mask_in
:
3347 case nir_intrinsic_load_sample_id
: {
3348 gl_system_value sv
= nir_system_value_from_intrinsic(instr
->intrinsic
);
3349 fs_reg val
= nir_system_values
[sv
];
3350 assert(val
.file
!= BAD_FILE
);
3351 dest
.type
= val
.type
;
3356 case nir_intrinsic_store_output
: {
3357 const fs_reg src
= get_nir_src(instr
->src
[0]);
3358 const unsigned store_offset
= nir_src_as_uint(instr
->src
[1]);
3359 const unsigned location
= nir_intrinsic_base(instr
) +
3360 SET_FIELD(store_offset
, BRW_NIR_FRAG_OUTPUT_LOCATION
);
3361 const fs_reg new_dest
= retype(alloc_frag_output(this, location
),
3364 for (unsigned j
= 0; j
< instr
->num_components
; j
++)
3365 bld
.MOV(offset(new_dest
, bld
, nir_intrinsic_component(instr
) + j
),
3366 offset(src
, bld
, j
));
3371 case nir_intrinsic_load_output
: {
3372 const unsigned l
= GET_FIELD(nir_intrinsic_base(instr
),
3373 BRW_NIR_FRAG_OUTPUT_LOCATION
);
3374 assert(l
>= FRAG_RESULT_DATA0
);
3375 const unsigned load_offset
= nir_src_as_uint(instr
->src
[0]);
3376 const unsigned target
= l
- FRAG_RESULT_DATA0
+ load_offset
;
3377 const fs_reg tmp
= bld
.vgrf(dest
.type
, 4);
3379 if (reinterpret_cast<const brw_wm_prog_key
*>(key
)->coherent_fb_fetch
)
3380 emit_coherent_fb_read(bld
, tmp
, target
);
3382 emit_non_coherent_fb_read(bld
, tmp
, target
);
3384 for (unsigned j
= 0; j
< instr
->num_components
; j
++) {
3385 bld
.MOV(offset(dest
, bld
, j
),
3386 offset(tmp
, bld
, nir_intrinsic_component(instr
) + j
));
3392 case nir_intrinsic_discard
:
3393 case nir_intrinsic_discard_if
: {
3394 /* We track our discarded pixels in f0.1. By predicating on it, we can
3395 * update just the flag bits that aren't yet discarded. If there's no
3396 * condition, we emit a CMP of g0 != g0, so all currently executing
3397 * channels will get turned off.
3400 if (instr
->intrinsic
== nir_intrinsic_discard_if
) {
3401 cmp
= bld
.CMP(bld
.null_reg_f(), get_nir_src(instr
->src
[0]),
3402 brw_imm_d(0), BRW_CONDITIONAL_Z
);
3404 fs_reg some_reg
= fs_reg(retype(brw_vec8_grf(0, 0),
3405 BRW_REGISTER_TYPE_UW
));
3406 cmp
= bld
.CMP(bld
.null_reg_f(), some_reg
, some_reg
, BRW_CONDITIONAL_NZ
);
3408 cmp
->predicate
= BRW_PREDICATE_NORMAL
;
3409 cmp
->flag_subreg
= 1;
3411 if (devinfo
->gen
>= 6) {
3412 emit_discard_jump();
3415 limit_dispatch_width(16, "Fragment discard not implemented in SIMD32 mode.");
3419 case nir_intrinsic_load_input
: {
3420 /* load_input is only used for flat inputs */
3421 unsigned base
= nir_intrinsic_base(instr
);
3422 unsigned comp
= nir_intrinsic_component(instr
);
3423 unsigned num_components
= instr
->num_components
;
3424 fs_reg orig_dest
= dest
;
3425 enum brw_reg_type type
= dest
.type
;
3427 /* Special case fields in the VUE header */
3428 if (base
== VARYING_SLOT_LAYER
)
3430 else if (base
== VARYING_SLOT_VIEWPORT
)
3433 if (nir_dest_bit_size(instr
->dest
) == 64) {
3434 /* const_index is in 32-bit type size units that could not be aligned
3435 * with DF. We need to read the double vector as if it was a float
3436 * vector of twice the number of components to fetch the right data.
3438 type
= BRW_REGISTER_TYPE_F
;
3439 num_components
*= 2;
3440 dest
= bld
.vgrf(type
, num_components
);
3443 for (unsigned int i
= 0; i
< num_components
; i
++) {
3444 bld
.MOV(offset(retype(dest
, type
), bld
, i
),
3445 retype(component(interp_reg(base
, comp
+ i
), 3), type
));
3448 if (nir_dest_bit_size(instr
->dest
) == 64) {
3449 shuffle_from_32bit_read(bld
, orig_dest
, dest
, 0,
3450 instr
->num_components
);
3455 case nir_intrinsic_load_barycentric_pixel
:
3456 case nir_intrinsic_load_barycentric_centroid
:
3457 case nir_intrinsic_load_barycentric_sample
:
3458 /* Do nothing - load_interpolated_input handling will handle it later. */
3461 case nir_intrinsic_load_barycentric_at_sample
: {
3462 const glsl_interp_mode interpolation
=
3463 (enum glsl_interp_mode
) nir_intrinsic_interp_mode(instr
);
3465 if (nir_src_is_const(instr
->src
[0])) {
3466 unsigned msg_data
= nir_src_as_uint(instr
->src
[0]) << 4;
3468 emit_pixel_interpolater_send(bld
,
3469 FS_OPCODE_INTERPOLATE_AT_SAMPLE
,
3472 brw_imm_ud(msg_data
),
3475 const fs_reg sample_src
= retype(get_nir_src(instr
->src
[0]),
3476 BRW_REGISTER_TYPE_UD
);
3478 if (nir_src_is_dynamically_uniform(instr
->src
[0])) {
3479 const fs_reg sample_id
= bld
.emit_uniformize(sample_src
);
3480 const fs_reg msg_data
= vgrf(glsl_type::uint_type
);
3481 bld
.exec_all().group(1, 0)
3482 .SHL(msg_data
, sample_id
, brw_imm_ud(4u));
3483 emit_pixel_interpolater_send(bld
,
3484 FS_OPCODE_INTERPOLATE_AT_SAMPLE
,
3490 /* Make a loop that sends a message to the pixel interpolater
3491 * for the sample number in each live channel. If there are
3492 * multiple channels with the same sample number then these
3493 * will be handled simultaneously with a single interation of
3496 bld
.emit(BRW_OPCODE_DO
);
3498 /* Get the next live sample number into sample_id_reg */
3499 const fs_reg sample_id
= bld
.emit_uniformize(sample_src
);
3501 /* Set the flag register so that we can perform the send
3502 * message on all channels that have the same sample number
3504 bld
.CMP(bld
.null_reg_ud(),
3505 sample_src
, sample_id
,
3506 BRW_CONDITIONAL_EQ
);
3507 const fs_reg msg_data
= vgrf(glsl_type::uint_type
);
3508 bld
.exec_all().group(1, 0)
3509 .SHL(msg_data
, sample_id
, brw_imm_ud(4u));
3511 emit_pixel_interpolater_send(bld
,
3512 FS_OPCODE_INTERPOLATE_AT_SAMPLE
,
3515 component(msg_data
, 0),
3517 set_predicate(BRW_PREDICATE_NORMAL
, inst
);
3519 /* Continue the loop if there are any live channels left */
3520 set_predicate_inv(BRW_PREDICATE_NORMAL
,
3522 bld
.emit(BRW_OPCODE_WHILE
));
3528 case nir_intrinsic_load_barycentric_at_offset
: {
3529 const glsl_interp_mode interpolation
=
3530 (enum glsl_interp_mode
) nir_intrinsic_interp_mode(instr
);
3532 nir_const_value
*const_offset
= nir_src_as_const_value(instr
->src
[0]);
3535 assert(nir_src_bit_size(instr
->src
[0]) == 32);
3536 unsigned off_x
= MIN2((int)(const_offset
[0].f32
* 16), 7) & 0xf;
3537 unsigned off_y
= MIN2((int)(const_offset
[1].f32
* 16), 7) & 0xf;
3539 emit_pixel_interpolater_send(bld
,
3540 FS_OPCODE_INTERPOLATE_AT_SHARED_OFFSET
,
3543 brw_imm_ud(off_x
| (off_y
<< 4)),
3546 fs_reg src
= vgrf(glsl_type::ivec2_type
);
3547 fs_reg offset_src
= retype(get_nir_src(instr
->src
[0]),
3548 BRW_REGISTER_TYPE_F
);
3549 for (int i
= 0; i
< 2; i
++) {
3550 fs_reg temp
= vgrf(glsl_type::float_type
);
3551 bld
.MUL(temp
, offset(offset_src
, bld
, i
), brw_imm_f(16.0f
));
3552 fs_reg itemp
= vgrf(glsl_type::int_type
);
3554 bld
.MOV(itemp
, temp
);
3556 /* Clamp the upper end of the range to +7/16.
3557 * ARB_gpu_shader5 requires that we support a maximum offset
3558 * of +0.5, which isn't representable in a S0.4 value -- if
3559 * we didn't clamp it, we'd end up with -8/16, which is the
3560 * opposite of what the shader author wanted.
3562 * This is legal due to ARB_gpu_shader5's quantization
3565 * "Not all values of <offset> may be supported; x and y
3566 * offsets may be rounded to fixed-point values with the
3567 * number of fraction bits given by the
3568 * implementation-dependent constant
3569 * FRAGMENT_INTERPOLATION_OFFSET_BITS"
3571 set_condmod(BRW_CONDITIONAL_L
,
3572 bld
.SEL(offset(src
, bld
, i
), itemp
, brw_imm_d(7)));
3575 const enum opcode opcode
= FS_OPCODE_INTERPOLATE_AT_PER_SLOT_OFFSET
;
3576 emit_pixel_interpolater_send(bld
,
3586 case nir_intrinsic_load_interpolated_input
: {
3587 if (nir_intrinsic_base(instr
) == VARYING_SLOT_POS
) {
3588 emit_fragcoord_interpolation(dest
);
3592 assert(instr
->src
[0].ssa
&&
3593 instr
->src
[0].ssa
->parent_instr
->type
== nir_instr_type_intrinsic
);
3594 nir_intrinsic_instr
*bary_intrinsic
=
3595 nir_instr_as_intrinsic(instr
->src
[0].ssa
->parent_instr
);
3596 nir_intrinsic_op bary_intrin
= bary_intrinsic
->intrinsic
;
3597 enum glsl_interp_mode interp_mode
=
3598 (enum glsl_interp_mode
) nir_intrinsic_interp_mode(bary_intrinsic
);
3601 if (bary_intrin
== nir_intrinsic_load_barycentric_at_offset
||
3602 bary_intrin
== nir_intrinsic_load_barycentric_at_sample
) {
3603 /* Use the result of the PI message */
3604 dst_xy
= retype(get_nir_src(instr
->src
[0]), BRW_REGISTER_TYPE_F
);
3606 /* Use the delta_xy values computed from the payload */
3607 enum brw_barycentric_mode bary
=
3608 brw_barycentric_mode(interp_mode
, bary_intrin
);
3610 dst_xy
= this->delta_xy
[bary
];
3613 for (unsigned int i
= 0; i
< instr
->num_components
; i
++) {
3615 interp_reg(nir_intrinsic_base(instr
),
3616 nir_intrinsic_component(instr
) + i
);
3617 interp
.type
= BRW_REGISTER_TYPE_F
;
3618 dest
.type
= BRW_REGISTER_TYPE_F
;
3620 if (devinfo
->gen
< 6 && interp_mode
== INTERP_MODE_SMOOTH
) {
3621 fs_reg tmp
= vgrf(glsl_type::float_type
);
3622 bld
.emit(FS_OPCODE_LINTERP
, tmp
, dst_xy
, interp
);
3623 bld
.MUL(offset(dest
, bld
, i
), tmp
, this->pixel_w
);
3625 bld
.emit(FS_OPCODE_LINTERP
, offset(dest
, bld
, i
), dst_xy
, interp
);
3632 nir_emit_intrinsic(bld
, instr
);
3638 get_op_for_atomic_add(nir_intrinsic_instr
*instr
, unsigned src
)
3640 if (nir_src_is_const(instr
->src
[src
])) {
3641 int64_t add_val
= nir_src_as_int(instr
->src
[src
]);
3644 else if (add_val
== -1)
3652 fs_visitor::nir_emit_cs_intrinsic(const fs_builder
&bld
,
3653 nir_intrinsic_instr
*instr
)
3655 assert(stage
== MESA_SHADER_COMPUTE
);
3656 struct brw_cs_prog_data
*cs_prog_data
= brw_cs_prog_data(prog_data
);
3659 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
3660 dest
= get_nir_dest(instr
->dest
);
3662 switch (instr
->intrinsic
) {
3663 case nir_intrinsic_barrier
:
3665 cs_prog_data
->uses_barrier
= true;
3668 case nir_intrinsic_load_subgroup_id
:
3669 bld
.MOV(retype(dest
, BRW_REGISTER_TYPE_UD
), subgroup_id
);
3672 case nir_intrinsic_load_local_invocation_id
:
3673 case nir_intrinsic_load_work_group_id
: {
3674 gl_system_value sv
= nir_system_value_from_intrinsic(instr
->intrinsic
);
3675 fs_reg val
= nir_system_values
[sv
];
3676 assert(val
.file
!= BAD_FILE
);
3677 dest
.type
= val
.type
;
3678 for (unsigned i
= 0; i
< 3; i
++)
3679 bld
.MOV(offset(dest
, bld
, i
), offset(val
, bld
, i
));
3683 case nir_intrinsic_load_num_work_groups
: {
3684 const unsigned surface
=
3685 cs_prog_data
->binding_table
.work_groups_start
;
3687 cs_prog_data
->uses_num_work_groups
= true;
3689 fs_reg srcs
[SURFACE_LOGICAL_NUM_SRCS
];
3690 srcs
[SURFACE_LOGICAL_SRC_SURFACE
] = brw_imm_ud(surface
);
3691 srcs
[SURFACE_LOGICAL_SRC_IMM_DIMS
] = brw_imm_ud(1);
3692 srcs
[SURFACE_LOGICAL_SRC_IMM_ARG
] = brw_imm_ud(1); /* num components */
3694 /* Read the 3 GLuint components of gl_NumWorkGroups */
3695 for (unsigned i
= 0; i
< 3; i
++) {
3696 srcs
[SURFACE_LOGICAL_SRC_ADDRESS
] = brw_imm_ud(i
<< 2);
3697 bld
.emit(SHADER_OPCODE_UNTYPED_SURFACE_READ_LOGICAL
,
3698 offset(dest
, bld
, i
), srcs
, SURFACE_LOGICAL_NUM_SRCS
);
3703 case nir_intrinsic_shared_atomic_add
:
3704 nir_emit_shared_atomic(bld
, get_op_for_atomic_add(instr
, 1), instr
);
3706 case nir_intrinsic_shared_atomic_imin
:
3707 nir_emit_shared_atomic(bld
, BRW_AOP_IMIN
, instr
);
3709 case nir_intrinsic_shared_atomic_umin
:
3710 nir_emit_shared_atomic(bld
, BRW_AOP_UMIN
, instr
);
3712 case nir_intrinsic_shared_atomic_imax
:
3713 nir_emit_shared_atomic(bld
, BRW_AOP_IMAX
, instr
);
3715 case nir_intrinsic_shared_atomic_umax
:
3716 nir_emit_shared_atomic(bld
, BRW_AOP_UMAX
, instr
);
3718 case nir_intrinsic_shared_atomic_and
:
3719 nir_emit_shared_atomic(bld
, BRW_AOP_AND
, instr
);
3721 case nir_intrinsic_shared_atomic_or
:
3722 nir_emit_shared_atomic(bld
, BRW_AOP_OR
, instr
);
3724 case nir_intrinsic_shared_atomic_xor
:
3725 nir_emit_shared_atomic(bld
, BRW_AOP_XOR
, instr
);
3727 case nir_intrinsic_shared_atomic_exchange
:
3728 nir_emit_shared_atomic(bld
, BRW_AOP_MOV
, instr
);
3730 case nir_intrinsic_shared_atomic_comp_swap
:
3731 nir_emit_shared_atomic(bld
, BRW_AOP_CMPWR
, instr
);
3733 case nir_intrinsic_shared_atomic_fmin
:
3734 nir_emit_shared_atomic_float(bld
, BRW_AOP_FMIN
, instr
);
3736 case nir_intrinsic_shared_atomic_fmax
:
3737 nir_emit_shared_atomic_float(bld
, BRW_AOP_FMAX
, instr
);
3739 case nir_intrinsic_shared_atomic_fcomp_swap
:
3740 nir_emit_shared_atomic_float(bld
, BRW_AOP_FCMPWR
, instr
);
3743 case nir_intrinsic_load_shared
: {
3744 assert(devinfo
->gen
>= 7);
3745 assert(stage
== MESA_SHADER_COMPUTE
);
3747 const unsigned bit_size
= nir_dest_bit_size(instr
->dest
);
3748 fs_reg srcs
[SURFACE_LOGICAL_NUM_SRCS
];
3749 srcs
[SURFACE_LOGICAL_SRC_SURFACE
] = brw_imm_ud(GEN7_BTI_SLM
);
3750 srcs
[SURFACE_LOGICAL_SRC_ADDRESS
] = get_nir_src(instr
->src
[0]);
3751 srcs
[SURFACE_LOGICAL_SRC_IMM_DIMS
] = brw_imm_ud(1);
3753 /* Make dest unsigned because that's what the temporary will be */
3754 dest
.type
= brw_reg_type_from_bit_size(bit_size
, BRW_REGISTER_TYPE_UD
);
3756 /* Read the vector */
3757 if (nir_intrinsic_align(instr
) >= 4) {
3758 assert(nir_dest_bit_size(instr
->dest
) == 32);
3759 srcs
[SURFACE_LOGICAL_SRC_IMM_ARG
] = brw_imm_ud(instr
->num_components
);
3761 bld
.emit(SHADER_OPCODE_UNTYPED_SURFACE_READ_LOGICAL
,
3762 dest
, srcs
, SURFACE_LOGICAL_NUM_SRCS
);
3763 inst
->size_written
= instr
->num_components
* dispatch_width
* 4;
3765 assert(nir_dest_bit_size(instr
->dest
) <= 32);
3766 assert(nir_dest_num_components(instr
->dest
) == 1);
3767 srcs
[SURFACE_LOGICAL_SRC_IMM_ARG
] = brw_imm_ud(bit_size
);
3769 fs_reg read_result
= bld
.vgrf(BRW_REGISTER_TYPE_UD
);
3770 bld
.emit(SHADER_OPCODE_BYTE_SCATTERED_READ_LOGICAL
,
3771 read_result
, srcs
, SURFACE_LOGICAL_NUM_SRCS
);
3772 bld
.MOV(dest
, read_result
);
3777 case nir_intrinsic_store_shared
: {
3778 assert(devinfo
->gen
>= 7);
3779 assert(stage
== MESA_SHADER_COMPUTE
);
3781 const unsigned bit_size
= nir_src_bit_size(instr
->src
[0]);
3782 fs_reg srcs
[SURFACE_LOGICAL_NUM_SRCS
];
3783 srcs
[SURFACE_LOGICAL_SRC_SURFACE
] = brw_imm_ud(GEN7_BTI_SLM
);
3784 srcs
[SURFACE_LOGICAL_SRC_ADDRESS
] = get_nir_src(instr
->src
[1]);
3785 srcs
[SURFACE_LOGICAL_SRC_IMM_DIMS
] = brw_imm_ud(1);
3787 fs_reg data
= get_nir_src(instr
->src
[0]);
3788 data
.type
= brw_reg_type_from_bit_size(bit_size
, BRW_REGISTER_TYPE_UD
);
3790 assert(nir_intrinsic_write_mask(instr
) ==
3791 (1u << instr
->num_components
) - 1);
3792 if (nir_intrinsic_align(instr
) >= 4) {
3793 assert(nir_src_bit_size(instr
->src
[0]) == 32);
3794 assert(nir_src_num_components(instr
->src
[0]) <= 4);
3795 srcs
[SURFACE_LOGICAL_SRC_DATA
] = data
;
3796 srcs
[SURFACE_LOGICAL_SRC_IMM_ARG
] = brw_imm_ud(instr
->num_components
);
3797 bld
.emit(SHADER_OPCODE_UNTYPED_SURFACE_WRITE_LOGICAL
,
3798 fs_reg(), srcs
, SURFACE_LOGICAL_NUM_SRCS
);
3800 assert(nir_src_bit_size(instr
->src
[0]) <= 32);
3801 assert(nir_src_num_components(instr
->src
[0]) == 1);
3802 srcs
[SURFACE_LOGICAL_SRC_IMM_ARG
] = brw_imm_ud(bit_size
);
3804 srcs
[SURFACE_LOGICAL_SRC_DATA
] = bld
.vgrf(BRW_REGISTER_TYPE_UD
);
3805 bld
.MOV(srcs
[SURFACE_LOGICAL_SRC_DATA
], data
);
3807 bld
.emit(SHADER_OPCODE_BYTE_SCATTERED_WRITE_LOGICAL
,
3808 fs_reg(), srcs
, SURFACE_LOGICAL_NUM_SRCS
);
3814 nir_emit_intrinsic(bld
, instr
);
3820 brw_nir_reduction_op_identity(const fs_builder
&bld
,
3821 nir_op op
, brw_reg_type type
)
3823 nir_const_value value
= nir_alu_binop_identity(op
, type_sz(type
) * 8);
3824 switch (type_sz(type
)) {
3826 assert(type
!= BRW_REGISTER_TYPE_HF
);
3827 return retype(brw_imm_uw(value
.u16
), type
);
3829 return retype(brw_imm_ud(value
.u32
), type
);
3831 if (type
== BRW_REGISTER_TYPE_DF
)
3832 return setup_imm_df(bld
, value
.f64
);
3834 return retype(brw_imm_u64(value
.u64
), type
);
3836 unreachable("Invalid type size");
3841 brw_op_for_nir_reduction_op(nir_op op
)
3844 case nir_op_iadd
: return BRW_OPCODE_ADD
;
3845 case nir_op_fadd
: return BRW_OPCODE_ADD
;
3846 case nir_op_imul
: return BRW_OPCODE_MUL
;
3847 case nir_op_fmul
: return BRW_OPCODE_MUL
;
3848 case nir_op_imin
: return BRW_OPCODE_SEL
;
3849 case nir_op_umin
: return BRW_OPCODE_SEL
;
3850 case nir_op_fmin
: return BRW_OPCODE_SEL
;
3851 case nir_op_imax
: return BRW_OPCODE_SEL
;
3852 case nir_op_umax
: return BRW_OPCODE_SEL
;
3853 case nir_op_fmax
: return BRW_OPCODE_SEL
;
3854 case nir_op_iand
: return BRW_OPCODE_AND
;
3855 case nir_op_ior
: return BRW_OPCODE_OR
;
3856 case nir_op_ixor
: return BRW_OPCODE_XOR
;
3858 unreachable("Invalid reduction operation");
3862 static brw_conditional_mod
3863 brw_cond_mod_for_nir_reduction_op(nir_op op
)
3866 case nir_op_iadd
: return BRW_CONDITIONAL_NONE
;
3867 case nir_op_fadd
: return BRW_CONDITIONAL_NONE
;
3868 case nir_op_imul
: return BRW_CONDITIONAL_NONE
;
3869 case nir_op_fmul
: return BRW_CONDITIONAL_NONE
;
3870 case nir_op_imin
: return BRW_CONDITIONAL_L
;
3871 case nir_op_umin
: return BRW_CONDITIONAL_L
;
3872 case nir_op_fmin
: return BRW_CONDITIONAL_L
;
3873 case nir_op_imax
: return BRW_CONDITIONAL_GE
;
3874 case nir_op_umax
: return BRW_CONDITIONAL_GE
;
3875 case nir_op_fmax
: return BRW_CONDITIONAL_GE
;
3876 case nir_op_iand
: return BRW_CONDITIONAL_NONE
;
3877 case nir_op_ior
: return BRW_CONDITIONAL_NONE
;
3878 case nir_op_ixor
: return BRW_CONDITIONAL_NONE
;
3880 unreachable("Invalid reduction operation");
3885 fs_visitor::get_nir_image_intrinsic_image(const brw::fs_builder
&bld
,
3886 nir_intrinsic_instr
*instr
)
3888 fs_reg image
= retype(get_nir_src_imm(instr
->src
[0]), BRW_REGISTER_TYPE_UD
);
3890 if (stage_prog_data
->binding_table
.image_start
> 0) {
3891 if (image
.file
== BRW_IMMEDIATE_VALUE
) {
3892 image
.d
+= stage_prog_data
->binding_table
.image_start
;
3894 bld
.ADD(image
, image
,
3895 brw_imm_d(stage_prog_data
->binding_table
.image_start
));
3899 return bld
.emit_uniformize(image
);
3903 fs_visitor::get_nir_ssbo_intrinsic_index(const brw::fs_builder
&bld
,
3904 nir_intrinsic_instr
*instr
)
3906 /* SSBO stores are weird in that their index is in src[1] */
3907 const unsigned src
= instr
->intrinsic
== nir_intrinsic_store_ssbo
? 1 : 0;
3910 if (nir_src_is_const(instr
->src
[src
])) {
3911 unsigned index
= stage_prog_data
->binding_table
.ssbo_start
+
3912 nir_src_as_uint(instr
->src
[src
]);
3913 surf_index
= brw_imm_ud(index
);
3915 surf_index
= vgrf(glsl_type::uint_type
);
3916 bld
.ADD(surf_index
, get_nir_src(instr
->src
[src
]),
3917 brw_imm_ud(stage_prog_data
->binding_table
.ssbo_start
));
3920 return bld
.emit_uniformize(surf_index
);
3924 image_intrinsic_coord_components(nir_intrinsic_instr
*instr
)
3926 switch (nir_intrinsic_image_dim(instr
)) {
3927 case GLSL_SAMPLER_DIM_1D
:
3928 return 1 + nir_intrinsic_image_array(instr
);
3929 case GLSL_SAMPLER_DIM_2D
:
3930 case GLSL_SAMPLER_DIM_RECT
:
3931 return 2 + nir_intrinsic_image_array(instr
);
3932 case GLSL_SAMPLER_DIM_3D
:
3933 case GLSL_SAMPLER_DIM_CUBE
:
3935 case GLSL_SAMPLER_DIM_BUF
:
3937 case GLSL_SAMPLER_DIM_MS
:
3938 return 2 + nir_intrinsic_image_array(instr
);
3940 unreachable("Invalid image dimension");
3945 fs_visitor::nir_emit_intrinsic(const fs_builder
&bld
, nir_intrinsic_instr
*instr
)
3948 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
3949 dest
= get_nir_dest(instr
->dest
);
3951 switch (instr
->intrinsic
) {
3952 case nir_intrinsic_image_load
:
3953 case nir_intrinsic_image_store
:
3954 case nir_intrinsic_image_atomic_add
:
3955 case nir_intrinsic_image_atomic_min
:
3956 case nir_intrinsic_image_atomic_max
:
3957 case nir_intrinsic_image_atomic_and
:
3958 case nir_intrinsic_image_atomic_or
:
3959 case nir_intrinsic_image_atomic_xor
:
3960 case nir_intrinsic_image_atomic_exchange
:
3961 case nir_intrinsic_image_atomic_comp_swap
:
3962 case nir_intrinsic_bindless_image_load
:
3963 case nir_intrinsic_bindless_image_store
:
3964 case nir_intrinsic_bindless_image_atomic_add
:
3965 case nir_intrinsic_bindless_image_atomic_min
:
3966 case nir_intrinsic_bindless_image_atomic_max
:
3967 case nir_intrinsic_bindless_image_atomic_and
:
3968 case nir_intrinsic_bindless_image_atomic_or
:
3969 case nir_intrinsic_bindless_image_atomic_xor
:
3970 case nir_intrinsic_bindless_image_atomic_exchange
:
3971 case nir_intrinsic_bindless_image_atomic_comp_swap
: {
3972 if (stage
== MESA_SHADER_FRAGMENT
&&
3973 instr
->intrinsic
!= nir_intrinsic_image_load
)
3974 brw_wm_prog_data(prog_data
)->has_side_effects
= true;
3976 /* Get some metadata from the image intrinsic. */
3977 const nir_intrinsic_info
*info
= &nir_intrinsic_infos
[instr
->intrinsic
];
3978 const GLenum format
= nir_intrinsic_format(instr
);
3980 fs_reg srcs
[SURFACE_LOGICAL_NUM_SRCS
];
3982 switch (instr
->intrinsic
) {
3983 case nir_intrinsic_image_load
:
3984 case nir_intrinsic_image_store
:
3985 case nir_intrinsic_image_atomic_add
:
3986 case nir_intrinsic_image_atomic_min
:
3987 case nir_intrinsic_image_atomic_max
:
3988 case nir_intrinsic_image_atomic_and
:
3989 case nir_intrinsic_image_atomic_or
:
3990 case nir_intrinsic_image_atomic_xor
:
3991 case nir_intrinsic_image_atomic_exchange
:
3992 case nir_intrinsic_image_atomic_comp_swap
:
3993 srcs
[SURFACE_LOGICAL_SRC_SURFACE
] =
3994 get_nir_image_intrinsic_image(bld
, instr
);
3999 srcs
[SURFACE_LOGICAL_SRC_SURFACE_HANDLE
] =
4000 bld
.emit_uniformize(get_nir_src(instr
->src
[0]));
4004 srcs
[SURFACE_LOGICAL_SRC_ADDRESS
] = get_nir_src(instr
->src
[1]);
4005 srcs
[SURFACE_LOGICAL_SRC_IMM_DIMS
] =
4006 brw_imm_ud(image_intrinsic_coord_components(instr
));
4008 /* Emit an image load, store or atomic op. */
4009 if (instr
->intrinsic
== nir_intrinsic_image_load
||
4010 instr
->intrinsic
== nir_intrinsic_bindless_image_load
) {
4011 srcs
[SURFACE_LOGICAL_SRC_IMM_ARG
] = brw_imm_ud(instr
->num_components
);
4013 bld
.emit(SHADER_OPCODE_TYPED_SURFACE_READ_LOGICAL
,
4014 dest
, srcs
, SURFACE_LOGICAL_NUM_SRCS
);
4015 inst
->size_written
= instr
->num_components
* dispatch_width
* 4;
4016 } else if (instr
->intrinsic
== nir_intrinsic_image_store
||
4017 instr
->intrinsic
== nir_intrinsic_bindless_image_store
) {
4018 srcs
[SURFACE_LOGICAL_SRC_IMM_ARG
] = brw_imm_ud(instr
->num_components
);
4019 srcs
[SURFACE_LOGICAL_SRC_DATA
] = get_nir_src(instr
->src
[3]);
4020 bld
.emit(SHADER_OPCODE_TYPED_SURFACE_WRITE_LOGICAL
,
4021 fs_reg(), srcs
, SURFACE_LOGICAL_NUM_SRCS
);
4024 unsigned num_srcs
= info
->num_srcs
;
4026 switch (instr
->intrinsic
) {
4027 case nir_intrinsic_image_atomic_add
:
4028 case nir_intrinsic_bindless_image_atomic_add
:
4029 assert(num_srcs
== 4);
4031 op
= get_op_for_atomic_add(instr
, 3);
4033 if (op
!= BRW_AOP_ADD
)
4036 case nir_intrinsic_image_atomic_min
:
4037 case nir_intrinsic_bindless_image_atomic_min
:
4038 assert(format
== GL_R32UI
|| format
== GL_R32I
);
4039 op
= (format
== GL_R32I
) ? BRW_AOP_IMIN
: BRW_AOP_UMIN
;
4041 case nir_intrinsic_image_atomic_max
:
4042 case nir_intrinsic_bindless_image_atomic_max
:
4043 assert(format
== GL_R32UI
|| format
== GL_R32I
);
4044 op
= (format
== GL_R32I
) ? BRW_AOP_IMAX
: BRW_AOP_UMAX
;
4046 case nir_intrinsic_image_atomic_and
:
4047 case nir_intrinsic_bindless_image_atomic_and
:
4050 case nir_intrinsic_image_atomic_or
:
4051 case nir_intrinsic_bindless_image_atomic_or
:
4054 case nir_intrinsic_image_atomic_xor
:
4055 case nir_intrinsic_bindless_image_atomic_xor
:
4058 case nir_intrinsic_image_atomic_exchange
:
4059 case nir_intrinsic_bindless_image_atomic_exchange
:
4062 case nir_intrinsic_image_atomic_comp_swap
:
4063 case nir_intrinsic_bindless_image_atomic_comp_swap
:
4067 unreachable("Not reachable.");
4070 srcs
[SURFACE_LOGICAL_SRC_IMM_ARG
] = brw_imm_ud(op
);
4074 data
= get_nir_src(instr
->src
[3]);
4075 if (num_srcs
>= 5) {
4076 fs_reg tmp
= bld
.vgrf(data
.type
, 2);
4077 fs_reg sources
[2] = { data
, get_nir_src(instr
->src
[4]) };
4078 bld
.LOAD_PAYLOAD(tmp
, sources
, 2, 0);
4081 srcs
[SURFACE_LOGICAL_SRC_DATA
] = data
;
4083 bld
.emit(SHADER_OPCODE_TYPED_ATOMIC_LOGICAL
,
4084 dest
, srcs
, SURFACE_LOGICAL_NUM_SRCS
);
4089 case nir_intrinsic_image_size
:
4090 case nir_intrinsic_bindless_image_size
: {
4091 /* Unlike the [un]typed load and store opcodes, the TXS that this turns
4092 * into will handle the binding table index for us in the geneerator.
4093 * Incidentally, this means that we can handle bindless with exactly the
4096 fs_reg image
= retype(get_nir_src_imm(instr
->src
[0]),
4097 BRW_REGISTER_TYPE_UD
);
4098 image
= bld
.emit_uniformize(image
);
4100 fs_reg srcs
[TEX_LOGICAL_NUM_SRCS
];
4101 if (instr
->intrinsic
== nir_intrinsic_image_size
)
4102 srcs
[TEX_LOGICAL_SRC_SURFACE
] = image
;
4104 srcs
[TEX_LOGICAL_SRC_SURFACE_HANDLE
] = image
;
4105 srcs
[TEX_LOGICAL_SRC_SAMPLER
] = brw_imm_d(0);
4106 srcs
[TEX_LOGICAL_SRC_COORD_COMPONENTS
] = brw_imm_d(0);
4107 srcs
[TEX_LOGICAL_SRC_GRAD_COMPONENTS
] = brw_imm_d(0);
4109 /* Since the image size is always uniform, we can just emit a SIMD8
4110 * query instruction and splat the result out.
4112 const fs_builder ubld
= bld
.exec_all().group(8, 0);
4114 fs_reg tmp
= ubld
.vgrf(BRW_REGISTER_TYPE_UD
, 4);
4115 fs_inst
*inst
= ubld
.emit(SHADER_OPCODE_IMAGE_SIZE_LOGICAL
,
4116 tmp
, srcs
, ARRAY_SIZE(srcs
));
4117 inst
->size_written
= 4 * REG_SIZE
;
4119 for (unsigned c
= 0; c
< instr
->dest
.ssa
.num_components
; ++c
) {
4120 if (c
== 2 && nir_intrinsic_image_dim(instr
) == GLSL_SAMPLER_DIM_CUBE
) {
4121 bld
.emit(SHADER_OPCODE_INT_QUOTIENT
,
4122 offset(retype(dest
, tmp
.type
), bld
, c
),
4123 component(offset(tmp
, ubld
, c
), 0), brw_imm_ud(6));
4125 bld
.MOV(offset(retype(dest
, tmp
.type
), bld
, c
),
4126 component(offset(tmp
, ubld
, c
), 0));
4132 case nir_intrinsic_image_load_raw_intel
: {
4133 fs_reg srcs
[SURFACE_LOGICAL_NUM_SRCS
];
4134 srcs
[SURFACE_LOGICAL_SRC_SURFACE
] =
4135 get_nir_image_intrinsic_image(bld
, instr
);
4136 srcs
[SURFACE_LOGICAL_SRC_ADDRESS
] = get_nir_src(instr
->src
[1]);
4137 srcs
[SURFACE_LOGICAL_SRC_IMM_DIMS
] = brw_imm_ud(1);
4138 srcs
[SURFACE_LOGICAL_SRC_IMM_ARG
] = brw_imm_ud(instr
->num_components
);
4141 bld
.emit(SHADER_OPCODE_UNTYPED_SURFACE_READ_LOGICAL
,
4142 dest
, srcs
, SURFACE_LOGICAL_NUM_SRCS
);
4143 inst
->size_written
= instr
->num_components
* dispatch_width
* 4;
4147 case nir_intrinsic_image_store_raw_intel
: {
4148 if (stage
== MESA_SHADER_FRAGMENT
)
4149 brw_wm_prog_data(prog_data
)->has_side_effects
= true;
4151 fs_reg srcs
[SURFACE_LOGICAL_NUM_SRCS
];
4152 srcs
[SURFACE_LOGICAL_SRC_SURFACE
] =
4153 get_nir_image_intrinsic_image(bld
, instr
);
4154 srcs
[SURFACE_LOGICAL_SRC_ADDRESS
] = get_nir_src(instr
->src
[1]);
4155 srcs
[SURFACE_LOGICAL_SRC_DATA
] = get_nir_src(instr
->src
[2]);
4156 srcs
[SURFACE_LOGICAL_SRC_IMM_DIMS
] = brw_imm_ud(1);
4157 srcs
[SURFACE_LOGICAL_SRC_IMM_ARG
] = brw_imm_ud(instr
->num_components
);
4159 bld
.emit(SHADER_OPCODE_UNTYPED_SURFACE_WRITE_LOGICAL
,
4160 fs_reg(), srcs
, SURFACE_LOGICAL_NUM_SRCS
);
4164 case nir_intrinsic_group_memory_barrier
:
4165 case nir_intrinsic_memory_barrier_shared
:
4166 case nir_intrinsic_memory_barrier_atomic_counter
:
4167 case nir_intrinsic_memory_barrier_buffer
:
4168 case nir_intrinsic_memory_barrier_image
:
4169 case nir_intrinsic_memory_barrier
: {
4170 const fs_builder ubld
= bld
.group(8, 0);
4171 const fs_reg tmp
= ubld
.vgrf(BRW_REGISTER_TYPE_UD
, 2);
4172 ubld
.emit(SHADER_OPCODE_MEMORY_FENCE
, tmp
)
4173 ->size_written
= 2 * REG_SIZE
;
4177 case nir_intrinsic_shader_clock
: {
4178 /* We cannot do anything if there is an event, so ignore it for now */
4179 const fs_reg shader_clock
= get_timestamp(bld
);
4180 const fs_reg srcs
[] = { component(shader_clock
, 0),
4181 component(shader_clock
, 1) };
4182 bld
.LOAD_PAYLOAD(dest
, srcs
, ARRAY_SIZE(srcs
), 0);
4186 case nir_intrinsic_image_samples
:
4187 /* The driver does not support multi-sampled images. */
4188 bld
.MOV(retype(dest
, BRW_REGISTER_TYPE_D
), brw_imm_d(1));
4191 case nir_intrinsic_load_uniform
: {
4192 /* Offsets are in bytes but they should always aligned to
4195 assert(instr
->const_index
[0] % 4 == 0 ||
4196 instr
->const_index
[0] % type_sz(dest
.type
) == 0);
4198 fs_reg
src(UNIFORM
, instr
->const_index
[0] / 4, dest
.type
);
4200 if (nir_src_is_const(instr
->src
[0])) {
4201 unsigned load_offset
= nir_src_as_uint(instr
->src
[0]);
4202 assert(load_offset
% type_sz(dest
.type
) == 0);
4203 /* For 16-bit types we add the module of the const_index[0]
4204 * offset to access to not 32-bit aligned element
4206 src
.offset
= load_offset
+ instr
->const_index
[0] % 4;
4208 for (unsigned j
= 0; j
< instr
->num_components
; j
++) {
4209 bld
.MOV(offset(dest
, bld
, j
), offset(src
, bld
, j
));
4212 fs_reg indirect
= retype(get_nir_src(instr
->src
[0]),
4213 BRW_REGISTER_TYPE_UD
);
4215 /* We need to pass a size to the MOV_INDIRECT but we don't want it to
4216 * go past the end of the uniform. In order to keep the n'th
4217 * component from running past, we subtract off the size of all but
4218 * one component of the vector.
4220 assert(instr
->const_index
[1] >=
4221 instr
->num_components
* (int) type_sz(dest
.type
));
4222 unsigned read_size
= instr
->const_index
[1] -
4223 (instr
->num_components
- 1) * type_sz(dest
.type
);
4225 bool supports_64bit_indirects
=
4226 !devinfo
->is_cherryview
&& !gen_device_info_is_9lp(devinfo
);
4228 if (type_sz(dest
.type
) != 8 || supports_64bit_indirects
) {
4229 for (unsigned j
= 0; j
< instr
->num_components
; j
++) {
4230 bld
.emit(SHADER_OPCODE_MOV_INDIRECT
,
4231 offset(dest
, bld
, j
), offset(src
, bld
, j
),
4232 indirect
, brw_imm_ud(read_size
));
4235 const unsigned num_mov_indirects
=
4236 type_sz(dest
.type
) / type_sz(BRW_REGISTER_TYPE_UD
);
4237 /* We read a little bit less per MOV INDIRECT, as they are now
4238 * 32-bits ones instead of 64-bit. Fix read_size then.
4240 const unsigned read_size_32bit
= read_size
-
4241 (num_mov_indirects
- 1) * type_sz(BRW_REGISTER_TYPE_UD
);
4242 for (unsigned j
= 0; j
< instr
->num_components
; j
++) {
4243 for (unsigned i
= 0; i
< num_mov_indirects
; i
++) {
4244 bld
.emit(SHADER_OPCODE_MOV_INDIRECT
,
4245 subscript(offset(dest
, bld
, j
), BRW_REGISTER_TYPE_UD
, i
),
4246 subscript(offset(src
, bld
, j
), BRW_REGISTER_TYPE_UD
, i
),
4247 indirect
, brw_imm_ud(read_size_32bit
));
4255 case nir_intrinsic_load_ubo
: {
4257 if (nir_src_is_const(instr
->src
[0])) {
4258 const unsigned index
= stage_prog_data
->binding_table
.ubo_start
+
4259 nir_src_as_uint(instr
->src
[0]);
4260 surf_index
= brw_imm_ud(index
);
4262 /* The block index is not a constant. Evaluate the index expression
4263 * per-channel and add the base UBO index; we have to select a value
4264 * from any live channel.
4266 surf_index
= vgrf(glsl_type::uint_type
);
4267 bld
.ADD(surf_index
, get_nir_src(instr
->src
[0]),
4268 brw_imm_ud(stage_prog_data
->binding_table
.ubo_start
));
4269 surf_index
= bld
.emit_uniformize(surf_index
);
4272 if (!nir_src_is_const(instr
->src
[1])) {
4273 fs_reg base_offset
= retype(get_nir_src(instr
->src
[1]),
4274 BRW_REGISTER_TYPE_UD
);
4276 for (int i
= 0; i
< instr
->num_components
; i
++)
4277 VARYING_PULL_CONSTANT_LOAD(bld
, offset(dest
, bld
, i
), surf_index
,
4278 base_offset
, i
* type_sz(dest
.type
));
4280 /* Even if we are loading doubles, a pull constant load will load
4281 * a 32-bit vec4, so should only reserve vgrf space for that. If we
4282 * need to load a full dvec4 we will have to emit 2 loads. This is
4283 * similar to demote_pull_constants(), except that in that case we
4284 * see individual accesses to each component of the vector and then
4285 * we let CSE deal with duplicate loads. Here we see a vector access
4286 * and we have to split it if necessary.
4288 const unsigned type_size
= type_sz(dest
.type
);
4289 const unsigned load_offset
= nir_src_as_uint(instr
->src
[1]);
4291 /* See if we've selected this as a push constant candidate */
4292 if (nir_src_is_const(instr
->src
[0])) {
4293 const unsigned ubo_block
= nir_src_as_uint(instr
->src
[0]);
4294 const unsigned offset_256b
= load_offset
/ 32;
4297 for (int i
= 0; i
< 4; i
++) {
4298 const struct brw_ubo_range
*range
= &prog_data
->ubo_ranges
[i
];
4299 if (range
->block
== ubo_block
&&
4300 offset_256b
>= range
->start
&&
4301 offset_256b
< range
->start
+ range
->length
) {
4303 push_reg
= fs_reg(UNIFORM
, UBO_START
+ i
, dest
.type
);
4304 push_reg
.offset
= load_offset
- 32 * range
->start
;
4309 if (push_reg
.file
!= BAD_FILE
) {
4310 for (unsigned i
= 0; i
< instr
->num_components
; i
++) {
4311 bld
.MOV(offset(dest
, bld
, i
),
4312 byte_offset(push_reg
, i
* type_size
));
4318 const unsigned block_sz
= 64; /* Fetch one cacheline at a time. */
4319 const fs_builder ubld
= bld
.exec_all().group(block_sz
/ 4, 0);
4320 const fs_reg packed_consts
= ubld
.vgrf(BRW_REGISTER_TYPE_UD
);
4322 for (unsigned c
= 0; c
< instr
->num_components
;) {
4323 const unsigned base
= load_offset
+ c
* type_size
;
4324 /* Number of usable components in the next block-aligned load. */
4325 const unsigned count
= MIN2(instr
->num_components
- c
,
4326 (block_sz
- base
% block_sz
) / type_size
);
4328 ubld
.emit(FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD
,
4329 packed_consts
, surf_index
,
4330 brw_imm_ud(base
& ~(block_sz
- 1)));
4332 const fs_reg consts
=
4333 retype(byte_offset(packed_consts
, base
& (block_sz
- 1)),
4336 for (unsigned d
= 0; d
< count
; d
++)
4337 bld
.MOV(offset(dest
, bld
, c
+ d
), component(consts
, d
));
4345 case nir_intrinsic_load_global
: {
4346 assert(devinfo
->gen
>= 8);
4348 if (nir_intrinsic_align(instr
) >= 4) {
4349 assert(nir_dest_bit_size(instr
->dest
) == 32);
4350 fs_inst
*inst
= bld
.emit(SHADER_OPCODE_A64_UNTYPED_READ_LOGICAL
,
4352 get_nir_src(instr
->src
[0]), /* Address */
4353 fs_reg(), /* No source data */
4354 brw_imm_ud(instr
->num_components
));
4355 inst
->size_written
= instr
->num_components
*
4356 inst
->dst
.component_size(inst
->exec_size
);
4358 const unsigned bit_size
= nir_dest_bit_size(instr
->dest
);
4359 assert(bit_size
<= 32);
4360 assert(nir_dest_num_components(instr
->dest
) == 1);
4361 brw_reg_type data_type
=
4362 brw_reg_type_from_bit_size(bit_size
, BRW_REGISTER_TYPE_UD
);
4363 fs_reg tmp
= bld
.vgrf(BRW_REGISTER_TYPE_UD
);
4364 bld
.emit(SHADER_OPCODE_A64_BYTE_SCATTERED_READ_LOGICAL
,
4366 get_nir_src(instr
->src
[0]), /* Address */
4367 fs_reg(), /* No source data */
4368 brw_imm_ud(bit_size
));
4369 bld
.MOV(retype(dest
, data_type
), tmp
);
4374 case nir_intrinsic_store_global
:
4375 assert(devinfo
->gen
>= 8);
4377 if (stage
== MESA_SHADER_FRAGMENT
)
4378 brw_wm_prog_data(prog_data
)->has_side_effects
= true;
4380 if (nir_intrinsic_align(instr
) >= 4) {
4381 assert(nir_src_bit_size(instr
->src
[0]) == 32);
4382 bld
.emit(SHADER_OPCODE_A64_UNTYPED_WRITE_LOGICAL
,
4384 get_nir_src(instr
->src
[1]), /* Address */
4385 get_nir_src(instr
->src
[0]), /* Data */
4386 brw_imm_ud(instr
->num_components
));
4388 const unsigned bit_size
= nir_src_bit_size(instr
->src
[0]);
4389 assert(bit_size
<= 32);
4390 assert(nir_src_num_components(instr
->src
[0]) == 1);
4391 brw_reg_type data_type
=
4392 brw_reg_type_from_bit_size(bit_size
, BRW_REGISTER_TYPE_UD
);
4393 fs_reg tmp
= bld
.vgrf(BRW_REGISTER_TYPE_UD
);
4394 bld
.MOV(tmp
, retype(get_nir_src(instr
->src
[0]), data_type
));
4395 bld
.emit(SHADER_OPCODE_A64_BYTE_SCATTERED_WRITE_LOGICAL
,
4397 get_nir_src(instr
->src
[1]), /* Address */
4399 brw_imm_ud(nir_src_bit_size(instr
->src
[0])));
4403 case nir_intrinsic_global_atomic_add
:
4404 nir_emit_global_atomic(bld
, get_op_for_atomic_add(instr
, 1), instr
);
4406 case nir_intrinsic_global_atomic_imin
:
4407 nir_emit_global_atomic(bld
, BRW_AOP_IMIN
, instr
);
4409 case nir_intrinsic_global_atomic_umin
:
4410 nir_emit_global_atomic(bld
, BRW_AOP_UMIN
, instr
);
4412 case nir_intrinsic_global_atomic_imax
:
4413 nir_emit_global_atomic(bld
, BRW_AOP_IMAX
, instr
);
4415 case nir_intrinsic_global_atomic_umax
:
4416 nir_emit_global_atomic(bld
, BRW_AOP_UMAX
, instr
);
4418 case nir_intrinsic_global_atomic_and
:
4419 nir_emit_global_atomic(bld
, BRW_AOP_AND
, instr
);
4421 case nir_intrinsic_global_atomic_or
:
4422 nir_emit_global_atomic(bld
, BRW_AOP_OR
, instr
);
4424 case nir_intrinsic_global_atomic_xor
:
4425 nir_emit_global_atomic(bld
, BRW_AOP_XOR
, instr
);
4427 case nir_intrinsic_global_atomic_exchange
:
4428 nir_emit_global_atomic(bld
, BRW_AOP_MOV
, instr
);
4430 case nir_intrinsic_global_atomic_comp_swap
:
4431 nir_emit_global_atomic(bld
, BRW_AOP_CMPWR
, instr
);
4433 case nir_intrinsic_global_atomic_fmin
:
4434 nir_emit_global_atomic_float(bld
, BRW_AOP_FMIN
, instr
);
4436 case nir_intrinsic_global_atomic_fmax
:
4437 nir_emit_global_atomic_float(bld
, BRW_AOP_FMAX
, instr
);
4439 case nir_intrinsic_global_atomic_fcomp_swap
:
4440 nir_emit_global_atomic_float(bld
, BRW_AOP_FCMPWR
, instr
);
4443 case nir_intrinsic_load_ssbo
: {
4444 assert(devinfo
->gen
>= 7);
4446 const unsigned bit_size
= nir_dest_bit_size(instr
->dest
);
4447 fs_reg srcs
[SURFACE_LOGICAL_NUM_SRCS
];
4448 srcs
[SURFACE_LOGICAL_SRC_SURFACE
] =
4449 get_nir_ssbo_intrinsic_index(bld
, instr
);
4450 srcs
[SURFACE_LOGICAL_SRC_ADDRESS
] = get_nir_src(instr
->src
[1]);
4451 srcs
[SURFACE_LOGICAL_SRC_IMM_DIMS
] = brw_imm_ud(1);
4453 /* Make dest unsigned because that's what the temporary will be */
4454 dest
.type
= brw_reg_type_from_bit_size(bit_size
, BRW_REGISTER_TYPE_UD
);
4456 /* Read the vector */
4457 if (nir_intrinsic_align(instr
) >= 4) {
4458 assert(nir_dest_bit_size(instr
->dest
) == 32);
4459 srcs
[SURFACE_LOGICAL_SRC_IMM_ARG
] = brw_imm_ud(instr
->num_components
);
4461 bld
.emit(SHADER_OPCODE_UNTYPED_SURFACE_READ_LOGICAL
,
4462 dest
, srcs
, SURFACE_LOGICAL_NUM_SRCS
);
4463 inst
->size_written
= instr
->num_components
* dispatch_width
* 4;
4465 assert(nir_dest_bit_size(instr
->dest
) <= 32);
4466 assert(nir_dest_num_components(instr
->dest
) == 1);
4467 srcs
[SURFACE_LOGICAL_SRC_IMM_ARG
] = brw_imm_ud(bit_size
);
4469 fs_reg read_result
= bld
.vgrf(BRW_REGISTER_TYPE_UD
);
4470 bld
.emit(SHADER_OPCODE_BYTE_SCATTERED_READ_LOGICAL
,
4471 read_result
, srcs
, SURFACE_LOGICAL_NUM_SRCS
);
4472 bld
.MOV(dest
, read_result
);
4477 case nir_intrinsic_store_ssbo
: {
4478 assert(devinfo
->gen
>= 7);
4480 if (stage
== MESA_SHADER_FRAGMENT
)
4481 brw_wm_prog_data(prog_data
)->has_side_effects
= true;
4483 const unsigned bit_size
= nir_src_bit_size(instr
->src
[0]);
4484 fs_reg srcs
[SURFACE_LOGICAL_NUM_SRCS
];
4485 srcs
[SURFACE_LOGICAL_SRC_SURFACE
] =
4486 get_nir_ssbo_intrinsic_index(bld
, instr
);
4487 srcs
[SURFACE_LOGICAL_SRC_ADDRESS
] = get_nir_src(instr
->src
[2]);
4488 srcs
[SURFACE_LOGICAL_SRC_IMM_DIMS
] = brw_imm_ud(1);
4490 fs_reg data
= get_nir_src(instr
->src
[0]);
4491 data
.type
= brw_reg_type_from_bit_size(bit_size
, BRW_REGISTER_TYPE_UD
);
4493 assert(nir_intrinsic_write_mask(instr
) ==
4494 (1u << instr
->num_components
) - 1);
4495 if (nir_intrinsic_align(instr
) >= 4) {
4496 assert(nir_src_bit_size(instr
->src
[0]) == 32);
4497 assert(nir_src_num_components(instr
->src
[0]) <= 4);
4498 srcs
[SURFACE_LOGICAL_SRC_DATA
] = data
;
4499 srcs
[SURFACE_LOGICAL_SRC_IMM_ARG
] = brw_imm_ud(instr
->num_components
);
4500 bld
.emit(SHADER_OPCODE_UNTYPED_SURFACE_WRITE_LOGICAL
,
4501 fs_reg(), srcs
, SURFACE_LOGICAL_NUM_SRCS
);
4503 assert(nir_src_bit_size(instr
->src
[0]) <= 32);
4504 assert(nir_src_num_components(instr
->src
[0]) == 1);
4505 srcs
[SURFACE_LOGICAL_SRC_IMM_ARG
] = brw_imm_ud(bit_size
);
4507 srcs
[SURFACE_LOGICAL_SRC_DATA
] = bld
.vgrf(BRW_REGISTER_TYPE_UD
);
4508 bld
.MOV(srcs
[SURFACE_LOGICAL_SRC_DATA
], data
);
4510 bld
.emit(SHADER_OPCODE_BYTE_SCATTERED_WRITE_LOGICAL
,
4511 fs_reg(), srcs
, SURFACE_LOGICAL_NUM_SRCS
);
4516 case nir_intrinsic_store_output
: {
4517 fs_reg src
= get_nir_src(instr
->src
[0]);
4519 unsigned store_offset
= nir_src_as_uint(instr
->src
[1]);
4520 unsigned num_components
= instr
->num_components
;
4521 unsigned first_component
= nir_intrinsic_component(instr
);
4522 if (nir_src_bit_size(instr
->src
[0]) == 64) {
4523 src
= shuffle_for_32bit_write(bld
, src
, 0, num_components
);
4524 num_components
*= 2;
4527 fs_reg new_dest
= retype(offset(outputs
[instr
->const_index
[0]], bld
,
4528 4 * store_offset
), src
.type
);
4529 for (unsigned j
= 0; j
< num_components
; j
++) {
4530 bld
.MOV(offset(new_dest
, bld
, j
+ first_component
),
4531 offset(src
, bld
, j
));
4536 case nir_intrinsic_ssbo_atomic_add
:
4537 nir_emit_ssbo_atomic(bld
, get_op_for_atomic_add(instr
, 2), instr
);
4539 case nir_intrinsic_ssbo_atomic_imin
:
4540 nir_emit_ssbo_atomic(bld
, BRW_AOP_IMIN
, instr
);
4542 case nir_intrinsic_ssbo_atomic_umin
:
4543 nir_emit_ssbo_atomic(bld
, BRW_AOP_UMIN
, instr
);
4545 case nir_intrinsic_ssbo_atomic_imax
:
4546 nir_emit_ssbo_atomic(bld
, BRW_AOP_IMAX
, instr
);
4548 case nir_intrinsic_ssbo_atomic_umax
:
4549 nir_emit_ssbo_atomic(bld
, BRW_AOP_UMAX
, instr
);
4551 case nir_intrinsic_ssbo_atomic_and
:
4552 nir_emit_ssbo_atomic(bld
, BRW_AOP_AND
, instr
);
4554 case nir_intrinsic_ssbo_atomic_or
:
4555 nir_emit_ssbo_atomic(bld
, BRW_AOP_OR
, instr
);
4557 case nir_intrinsic_ssbo_atomic_xor
:
4558 nir_emit_ssbo_atomic(bld
, BRW_AOP_XOR
, instr
);
4560 case nir_intrinsic_ssbo_atomic_exchange
:
4561 nir_emit_ssbo_atomic(bld
, BRW_AOP_MOV
, instr
);
4563 case nir_intrinsic_ssbo_atomic_comp_swap
:
4564 nir_emit_ssbo_atomic(bld
, BRW_AOP_CMPWR
, instr
);
4566 case nir_intrinsic_ssbo_atomic_fmin
:
4567 nir_emit_ssbo_atomic_float(bld
, BRW_AOP_FMIN
, instr
);
4569 case nir_intrinsic_ssbo_atomic_fmax
:
4570 nir_emit_ssbo_atomic_float(bld
, BRW_AOP_FMAX
, instr
);
4572 case nir_intrinsic_ssbo_atomic_fcomp_swap
:
4573 nir_emit_ssbo_atomic_float(bld
, BRW_AOP_FCMPWR
, instr
);
4576 case nir_intrinsic_get_buffer_size
: {
4577 assert(nir_src_num_components(instr
->src
[0]) == 1);
4578 unsigned ssbo_index
= nir_src_is_const(instr
->src
[0]) ?
4579 nir_src_as_uint(instr
->src
[0]) : 0;
4581 /* A resinfo's sampler message is used to get the buffer size. The
4582 * SIMD8's writeback message consists of four registers and SIMD16's
4583 * writeback message consists of 8 destination registers (two per each
4584 * component). Because we are only interested on the first channel of
4585 * the first returned component, where resinfo returns the buffer size
4586 * for SURFTYPE_BUFFER, we can just use the SIMD8 variant regardless of
4587 * the dispatch width.
4589 const fs_builder ubld
= bld
.exec_all().group(8, 0);
4590 fs_reg src_payload
= ubld
.vgrf(BRW_REGISTER_TYPE_UD
);
4591 fs_reg ret_payload
= ubld
.vgrf(BRW_REGISTER_TYPE_UD
, 4);
4594 ubld
.MOV(src_payload
, brw_imm_d(0));
4596 const unsigned index
= prog_data
->binding_table
.ssbo_start
+ ssbo_index
;
4597 fs_inst
*inst
= ubld
.emit(SHADER_OPCODE_GET_BUFFER_SIZE
, ret_payload
,
4598 src_payload
, brw_imm_ud(index
));
4599 inst
->header_size
= 0;
4601 inst
->size_written
= 4 * REG_SIZE
;
4603 /* SKL PRM, vol07, 3D Media GPGPU Engine, Bounds Checking and Faulting:
4605 * "Out-of-bounds checking is always performed at a DWord granularity. If
4606 * any part of the DWord is out-of-bounds then the whole DWord is
4607 * considered out-of-bounds."
4609 * This implies that types with size smaller than 4-bytes need to be
4610 * padded if they don't complete the last dword of the buffer. But as we
4611 * need to maintain the original size we need to reverse the padding
4612 * calculation to return the correct size to know the number of elements
4613 * of an unsized array. As we stored in the last two bits of the surface
4614 * size the needed padding for the buffer, we calculate here the
4615 * original buffer_size reversing the surface_size calculation:
4617 * surface_size = isl_align(buffer_size, 4) +
4618 * (isl_align(buffer_size) - buffer_size)
4620 * buffer_size = surface_size & ~3 - surface_size & 3
4623 fs_reg size_aligned4
= ubld
.vgrf(BRW_REGISTER_TYPE_UD
);
4624 fs_reg size_padding
= ubld
.vgrf(BRW_REGISTER_TYPE_UD
);
4625 fs_reg buffer_size
= ubld
.vgrf(BRW_REGISTER_TYPE_UD
);
4627 ubld
.AND(size_padding
, ret_payload
, brw_imm_ud(3));
4628 ubld
.AND(size_aligned4
, ret_payload
, brw_imm_ud(~3));
4629 ubld
.ADD(buffer_size
, size_aligned4
, negate(size_padding
));
4631 bld
.MOV(retype(dest
, ret_payload
.type
), component(buffer_size
, 0));
4635 case nir_intrinsic_load_subgroup_invocation
:
4636 bld
.MOV(retype(dest
, BRW_REGISTER_TYPE_D
),
4637 nir_system_values
[SYSTEM_VALUE_SUBGROUP_INVOCATION
]);
4640 case nir_intrinsic_load_subgroup_eq_mask
:
4641 case nir_intrinsic_load_subgroup_ge_mask
:
4642 case nir_intrinsic_load_subgroup_gt_mask
:
4643 case nir_intrinsic_load_subgroup_le_mask
:
4644 case nir_intrinsic_load_subgroup_lt_mask
:
4645 unreachable("not reached");
4647 case nir_intrinsic_vote_any
: {
4648 const fs_builder ubld
= bld
.exec_all().group(1, 0);
4650 /* The any/all predicates do not consider channel enables. To prevent
4651 * dead channels from affecting the result, we initialize the flag with
4652 * with the identity value for the logical operation.
4654 if (dispatch_width
== 32) {
4655 /* For SIMD32, we use a UD type so we fill both f0.0 and f0.1. */
4656 ubld
.MOV(retype(brw_flag_reg(0, 0), BRW_REGISTER_TYPE_UD
),
4659 ubld
.MOV(brw_flag_reg(0, 0), brw_imm_uw(0));
4661 bld
.CMP(bld
.null_reg_d(), get_nir_src(instr
->src
[0]), brw_imm_d(0), BRW_CONDITIONAL_NZ
);
4663 /* For some reason, the any/all predicates don't work properly with
4664 * SIMD32. In particular, it appears that a SEL with a QtrCtrl of 2H
4665 * doesn't read the correct subset of the flag register and you end up
4666 * getting garbage in the second half. Work around this by using a pair
4667 * of 1-wide MOVs and scattering the result.
4669 fs_reg res1
= ubld
.vgrf(BRW_REGISTER_TYPE_D
);
4670 ubld
.MOV(res1
, brw_imm_d(0));
4671 set_predicate(dispatch_width
== 8 ? BRW_PREDICATE_ALIGN1_ANY8H
:
4672 dispatch_width
== 16 ? BRW_PREDICATE_ALIGN1_ANY16H
:
4673 BRW_PREDICATE_ALIGN1_ANY32H
,
4674 ubld
.MOV(res1
, brw_imm_d(-1)));
4676 bld
.MOV(retype(dest
, BRW_REGISTER_TYPE_D
), component(res1
, 0));
4679 case nir_intrinsic_vote_all
: {
4680 const fs_builder ubld
= bld
.exec_all().group(1, 0);
4682 /* The any/all predicates do not consider channel enables. To prevent
4683 * dead channels from affecting the result, we initialize the flag with
4684 * with the identity value for the logical operation.
4686 if (dispatch_width
== 32) {
4687 /* For SIMD32, we use a UD type so we fill both f0.0 and f0.1. */
4688 ubld
.MOV(retype(brw_flag_reg(0, 0), BRW_REGISTER_TYPE_UD
),
4689 brw_imm_ud(0xffffffff));
4691 ubld
.MOV(brw_flag_reg(0, 0), brw_imm_uw(0xffff));
4693 bld
.CMP(bld
.null_reg_d(), get_nir_src(instr
->src
[0]), brw_imm_d(0), BRW_CONDITIONAL_NZ
);
4695 /* For some reason, the any/all predicates don't work properly with
4696 * SIMD32. In particular, it appears that a SEL with a QtrCtrl of 2H
4697 * doesn't read the correct subset of the flag register and you end up
4698 * getting garbage in the second half. Work around this by using a pair
4699 * of 1-wide MOVs and scattering the result.
4701 fs_reg res1
= ubld
.vgrf(BRW_REGISTER_TYPE_D
);
4702 ubld
.MOV(res1
, brw_imm_d(0));
4703 set_predicate(dispatch_width
== 8 ? BRW_PREDICATE_ALIGN1_ALL8H
:
4704 dispatch_width
== 16 ? BRW_PREDICATE_ALIGN1_ALL16H
:
4705 BRW_PREDICATE_ALIGN1_ALL32H
,
4706 ubld
.MOV(res1
, brw_imm_d(-1)));
4708 bld
.MOV(retype(dest
, BRW_REGISTER_TYPE_D
), component(res1
, 0));
4711 case nir_intrinsic_vote_feq
:
4712 case nir_intrinsic_vote_ieq
: {
4713 fs_reg value
= get_nir_src(instr
->src
[0]);
4714 if (instr
->intrinsic
== nir_intrinsic_vote_feq
) {
4715 const unsigned bit_size
= nir_src_bit_size(instr
->src
[0]);
4716 value
.type
= bit_size
== 8 ? BRW_REGISTER_TYPE_B
:
4717 brw_reg_type_from_bit_size(bit_size
, BRW_REGISTER_TYPE_F
);
4720 fs_reg uniformized
= bld
.emit_uniformize(value
);
4721 const fs_builder ubld
= bld
.exec_all().group(1, 0);
4723 /* The any/all predicates do not consider channel enables. To prevent
4724 * dead channels from affecting the result, we initialize the flag with
4725 * with the identity value for the logical operation.
4727 if (dispatch_width
== 32) {
4728 /* For SIMD32, we use a UD type so we fill both f0.0 and f0.1. */
4729 ubld
.MOV(retype(brw_flag_reg(0, 0), BRW_REGISTER_TYPE_UD
),
4730 brw_imm_ud(0xffffffff));
4732 ubld
.MOV(brw_flag_reg(0, 0), brw_imm_uw(0xffff));
4734 bld
.CMP(bld
.null_reg_d(), value
, uniformized
, BRW_CONDITIONAL_Z
);
4736 /* For some reason, the any/all predicates don't work properly with
4737 * SIMD32. In particular, it appears that a SEL with a QtrCtrl of 2H
4738 * doesn't read the correct subset of the flag register and you end up
4739 * getting garbage in the second half. Work around this by using a pair
4740 * of 1-wide MOVs and scattering the result.
4742 fs_reg res1
= ubld
.vgrf(BRW_REGISTER_TYPE_D
);
4743 ubld
.MOV(res1
, brw_imm_d(0));
4744 set_predicate(dispatch_width
== 8 ? BRW_PREDICATE_ALIGN1_ALL8H
:
4745 dispatch_width
== 16 ? BRW_PREDICATE_ALIGN1_ALL16H
:
4746 BRW_PREDICATE_ALIGN1_ALL32H
,
4747 ubld
.MOV(res1
, brw_imm_d(-1)));
4749 bld
.MOV(retype(dest
, BRW_REGISTER_TYPE_D
), component(res1
, 0));
4753 case nir_intrinsic_ballot
: {
4754 const fs_reg value
= retype(get_nir_src(instr
->src
[0]),
4755 BRW_REGISTER_TYPE_UD
);
4756 struct brw_reg flag
= brw_flag_reg(0, 0);
4757 /* FIXME: For SIMD32 programs, this causes us to stomp on f0.1 as well
4758 * as f0.0. This is a problem for fragment programs as we currently use
4759 * f0.1 for discards. Fortunately, we don't support SIMD32 fragment
4760 * programs yet so this isn't a problem. When we do, something will
4763 if (dispatch_width
== 32)
4764 flag
.type
= BRW_REGISTER_TYPE_UD
;
4766 bld
.exec_all().group(1, 0).MOV(flag
, brw_imm_ud(0u));
4767 bld
.CMP(bld
.null_reg_ud(), value
, brw_imm_ud(0u), BRW_CONDITIONAL_NZ
);
4769 if (instr
->dest
.ssa
.bit_size
> 32) {
4770 dest
.type
= BRW_REGISTER_TYPE_UQ
;
4772 dest
.type
= BRW_REGISTER_TYPE_UD
;
4774 bld
.MOV(dest
, flag
);
4778 case nir_intrinsic_read_invocation
: {
4779 const fs_reg value
= get_nir_src(instr
->src
[0]);
4780 const fs_reg invocation
= get_nir_src(instr
->src
[1]);
4781 fs_reg tmp
= bld
.vgrf(value
.type
);
4783 bld
.exec_all().emit(SHADER_OPCODE_BROADCAST
, tmp
, value
,
4784 bld
.emit_uniformize(invocation
));
4786 bld
.MOV(retype(dest
, value
.type
), fs_reg(component(tmp
, 0)));
4790 case nir_intrinsic_read_first_invocation
: {
4791 const fs_reg value
= get_nir_src(instr
->src
[0]);
4792 bld
.MOV(retype(dest
, value
.type
), bld
.emit_uniformize(value
));
4796 case nir_intrinsic_shuffle
: {
4797 const fs_reg value
= get_nir_src(instr
->src
[0]);
4798 const fs_reg index
= get_nir_src(instr
->src
[1]);
4800 bld
.emit(SHADER_OPCODE_SHUFFLE
, retype(dest
, value
.type
), value
, index
);
4804 case nir_intrinsic_first_invocation
: {
4805 fs_reg tmp
= bld
.vgrf(BRW_REGISTER_TYPE_UD
);
4806 bld
.exec_all().emit(SHADER_OPCODE_FIND_LIVE_CHANNEL
, tmp
);
4807 bld
.MOV(retype(dest
, BRW_REGISTER_TYPE_UD
),
4808 fs_reg(component(tmp
, 0)));
4812 case nir_intrinsic_quad_broadcast
: {
4813 const fs_reg value
= get_nir_src(instr
->src
[0]);
4814 const unsigned index
= nir_src_as_uint(instr
->src
[1]);
4816 bld
.emit(SHADER_OPCODE_CLUSTER_BROADCAST
, retype(dest
, value
.type
),
4817 value
, brw_imm_ud(index
), brw_imm_ud(4));
4821 case nir_intrinsic_quad_swap_horizontal
: {
4822 const fs_reg value
= get_nir_src(instr
->src
[0]);
4823 const fs_reg tmp
= bld
.vgrf(value
.type
);
4824 const fs_builder ubld
= bld
.exec_all().group(dispatch_width
/ 2, 0);
4826 const fs_reg src_left
= horiz_stride(value
, 2);
4827 const fs_reg src_right
= horiz_stride(horiz_offset(value
, 1), 2);
4828 const fs_reg tmp_left
= horiz_stride(tmp
, 2);
4829 const fs_reg tmp_right
= horiz_stride(horiz_offset(tmp
, 1), 2);
4831 ubld
.MOV(tmp_left
, src_right
);
4832 ubld
.MOV(tmp_right
, src_left
);
4834 bld
.MOV(retype(dest
, value
.type
), tmp
);
4838 case nir_intrinsic_quad_swap_vertical
: {
4839 const fs_reg value
= get_nir_src(instr
->src
[0]);
4840 if (nir_src_bit_size(instr
->src
[0]) == 32) {
4841 /* For 32-bit, we can use a SIMD4x2 instruction to do this easily */
4842 const fs_reg tmp
= bld
.vgrf(value
.type
);
4843 const fs_builder ubld
= bld
.exec_all();
4844 ubld
.emit(SHADER_OPCODE_QUAD_SWIZZLE
, tmp
, value
,
4845 brw_imm_ud(BRW_SWIZZLE4(2,3,0,1)));
4846 bld
.MOV(retype(dest
, value
.type
), tmp
);
4848 /* For larger data types, we have to either emit dispatch_width many
4849 * MOVs or else fall back to doing indirects.
4851 fs_reg idx
= bld
.vgrf(BRW_REGISTER_TYPE_W
);
4852 bld
.XOR(idx
, nir_system_values
[SYSTEM_VALUE_SUBGROUP_INVOCATION
],
4854 bld
.emit(SHADER_OPCODE_SHUFFLE
, retype(dest
, value
.type
), value
, idx
);
4859 case nir_intrinsic_quad_swap_diagonal
: {
4860 const fs_reg value
= get_nir_src(instr
->src
[0]);
4861 if (nir_src_bit_size(instr
->src
[0]) == 32) {
4862 /* For 32-bit, we can use a SIMD4x2 instruction to do this easily */
4863 const fs_reg tmp
= bld
.vgrf(value
.type
);
4864 const fs_builder ubld
= bld
.exec_all();
4865 ubld
.emit(SHADER_OPCODE_QUAD_SWIZZLE
, tmp
, value
,
4866 brw_imm_ud(BRW_SWIZZLE4(3,2,1,0)));
4867 bld
.MOV(retype(dest
, value
.type
), tmp
);
4869 /* For larger data types, we have to either emit dispatch_width many
4870 * MOVs or else fall back to doing indirects.
4872 fs_reg idx
= bld
.vgrf(BRW_REGISTER_TYPE_W
);
4873 bld
.XOR(idx
, nir_system_values
[SYSTEM_VALUE_SUBGROUP_INVOCATION
],
4875 bld
.emit(SHADER_OPCODE_SHUFFLE
, retype(dest
, value
.type
), value
, idx
);
4880 case nir_intrinsic_reduce
: {
4881 fs_reg src
= get_nir_src(instr
->src
[0]);
4882 nir_op redop
= (nir_op
)nir_intrinsic_reduction_op(instr
);
4883 unsigned cluster_size
= nir_intrinsic_cluster_size(instr
);
4884 if (cluster_size
== 0 || cluster_size
> dispatch_width
)
4885 cluster_size
= dispatch_width
;
4887 /* Figure out the source type */
4888 src
.type
= brw_type_for_nir_type(devinfo
,
4889 (nir_alu_type
)(nir_op_infos
[redop
].input_types
[0] |
4890 nir_src_bit_size(instr
->src
[0])));
4892 fs_reg identity
= brw_nir_reduction_op_identity(bld
, redop
, src
.type
);
4893 opcode brw_op
= brw_op_for_nir_reduction_op(redop
);
4894 brw_conditional_mod cond_mod
= brw_cond_mod_for_nir_reduction_op(redop
);
4896 /* Set up a register for all of our scratching around and initialize it
4897 * to reduction operation's identity value.
4899 fs_reg scan
= bld
.vgrf(src
.type
);
4900 bld
.exec_all().emit(SHADER_OPCODE_SEL_EXEC
, scan
, src
, identity
);
4902 bld
.emit_scan(brw_op
, scan
, cluster_size
, cond_mod
);
4904 dest
.type
= src
.type
;
4905 if (cluster_size
* type_sz(src
.type
) >= REG_SIZE
* 2) {
4906 /* In this case, CLUSTER_BROADCAST instruction isn't needed because
4907 * the distance between clusters is at least 2 GRFs. In this case,
4908 * we don't need the weird striding of the CLUSTER_BROADCAST
4909 * instruction and can just do regular MOVs.
4911 assert((cluster_size
* type_sz(src
.type
)) % (REG_SIZE
* 2) == 0);
4912 const unsigned groups
=
4913 (dispatch_width
* type_sz(src
.type
)) / (REG_SIZE
* 2);
4914 const unsigned group_size
= dispatch_width
/ groups
;
4915 for (unsigned i
= 0; i
< groups
; i
++) {
4916 const unsigned cluster
= (i
* group_size
) / cluster_size
;
4917 const unsigned comp
= cluster
* cluster_size
+ (cluster_size
- 1);
4918 bld
.group(group_size
, i
).MOV(horiz_offset(dest
, i
* group_size
),
4919 component(scan
, comp
));
4922 bld
.emit(SHADER_OPCODE_CLUSTER_BROADCAST
, dest
, scan
,
4923 brw_imm_ud(cluster_size
- 1), brw_imm_ud(cluster_size
));
4928 case nir_intrinsic_inclusive_scan
:
4929 case nir_intrinsic_exclusive_scan
: {
4930 fs_reg src
= get_nir_src(instr
->src
[0]);
4931 nir_op redop
= (nir_op
)nir_intrinsic_reduction_op(instr
);
4933 /* Figure out the source type */
4934 src
.type
= brw_type_for_nir_type(devinfo
,
4935 (nir_alu_type
)(nir_op_infos
[redop
].input_types
[0] |
4936 nir_src_bit_size(instr
->src
[0])));
4938 fs_reg identity
= brw_nir_reduction_op_identity(bld
, redop
, src
.type
);
4939 opcode brw_op
= brw_op_for_nir_reduction_op(redop
);
4940 brw_conditional_mod cond_mod
= brw_cond_mod_for_nir_reduction_op(redop
);
4942 /* Set up a register for all of our scratching around and initialize it
4943 * to reduction operation's identity value.
4945 fs_reg scan
= bld
.vgrf(src
.type
);
4946 const fs_builder allbld
= bld
.exec_all();
4947 allbld
.emit(SHADER_OPCODE_SEL_EXEC
, scan
, src
, identity
);
4949 if (instr
->intrinsic
== nir_intrinsic_exclusive_scan
) {
4950 /* Exclusive scan is a bit harder because we have to do an annoying
4951 * shift of the contents before we can begin. To make things worse,
4952 * we can't do this with a normal stride; we have to use indirects.
4954 fs_reg shifted
= bld
.vgrf(src
.type
);
4955 fs_reg idx
= bld
.vgrf(BRW_REGISTER_TYPE_W
);
4956 allbld
.ADD(idx
, nir_system_values
[SYSTEM_VALUE_SUBGROUP_INVOCATION
],
4958 allbld
.emit(SHADER_OPCODE_SHUFFLE
, shifted
, scan
, idx
);
4959 allbld
.group(1, 0).MOV(component(shifted
, 0), identity
);
4963 bld
.emit_scan(brw_op
, scan
, dispatch_width
, cond_mod
);
4965 bld
.MOV(retype(dest
, src
.type
), scan
);
4969 case nir_intrinsic_begin_invocation_interlock
: {
4970 const fs_builder ubld
= bld
.group(8, 0);
4971 const fs_reg tmp
= ubld
.vgrf(BRW_REGISTER_TYPE_UD
, 2);
4973 ubld
.emit(SHADER_OPCODE_INTERLOCK
, tmp
)->size_written
= 2 *
4979 case nir_intrinsic_end_invocation_interlock
: {
4980 /* We don't need to do anything here */
4985 unreachable("unknown intrinsic");
4990 fs_visitor::nir_emit_ssbo_atomic(const fs_builder
&bld
,
4991 int op
, nir_intrinsic_instr
*instr
)
4993 if (stage
== MESA_SHADER_FRAGMENT
)
4994 brw_wm_prog_data(prog_data
)->has_side_effects
= true;
4996 /* The BTI untyped atomic messages only support 32-bit atomics. If you
4997 * just look at the big table of messages in the Vol 7 of the SKL PRM, they
4998 * appear to exist. However, if you look at Vol 2a, there are no message
4999 * descriptors provided for Qword atomic ops except for A64 messages.
5001 assert(nir_dest_bit_size(instr
->dest
) == 32);
5004 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
5005 dest
= get_nir_dest(instr
->dest
);
5007 fs_reg srcs
[SURFACE_LOGICAL_NUM_SRCS
];
5008 srcs
[SURFACE_LOGICAL_SRC_SURFACE
] = get_nir_ssbo_intrinsic_index(bld
, instr
);
5009 srcs
[SURFACE_LOGICAL_SRC_ADDRESS
] = get_nir_src(instr
->src
[1]);
5010 srcs
[SURFACE_LOGICAL_SRC_IMM_DIMS
] = brw_imm_ud(1);
5011 srcs
[SURFACE_LOGICAL_SRC_IMM_ARG
] = brw_imm_ud(op
);
5014 if (op
!= BRW_AOP_INC
&& op
!= BRW_AOP_DEC
&& op
!= BRW_AOP_PREDEC
)
5015 data
= get_nir_src(instr
->src
[2]);
5017 if (op
== BRW_AOP_CMPWR
) {
5018 fs_reg tmp
= bld
.vgrf(data
.type
, 2);
5019 fs_reg sources
[2] = { data
, get_nir_src(instr
->src
[3]) };
5020 bld
.LOAD_PAYLOAD(tmp
, sources
, 2, 0);
5023 srcs
[SURFACE_LOGICAL_SRC_DATA
] = data
;
5025 /* Emit the actual atomic operation */
5027 bld
.emit(SHADER_OPCODE_UNTYPED_ATOMIC_LOGICAL
,
5028 dest
, srcs
, SURFACE_LOGICAL_NUM_SRCS
);
5032 fs_visitor::nir_emit_ssbo_atomic_float(const fs_builder
&bld
,
5033 int op
, nir_intrinsic_instr
*instr
)
5035 if (stage
== MESA_SHADER_FRAGMENT
)
5036 brw_wm_prog_data(prog_data
)->has_side_effects
= true;
5039 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
5040 dest
= get_nir_dest(instr
->dest
);
5042 fs_reg srcs
[SURFACE_LOGICAL_NUM_SRCS
];
5043 srcs
[SURFACE_LOGICAL_SRC_SURFACE
] = get_nir_ssbo_intrinsic_index(bld
, instr
);
5044 srcs
[SURFACE_LOGICAL_SRC_ADDRESS
] = get_nir_src(instr
->src
[1]);
5045 srcs
[SURFACE_LOGICAL_SRC_IMM_DIMS
] = brw_imm_ud(1);
5046 srcs
[SURFACE_LOGICAL_SRC_IMM_ARG
] = brw_imm_ud(op
);
5048 fs_reg data
= get_nir_src(instr
->src
[2]);
5049 if (op
== BRW_AOP_FCMPWR
) {
5050 fs_reg tmp
= bld
.vgrf(data
.type
, 2);
5051 fs_reg sources
[2] = { data
, get_nir_src(instr
->src
[3]) };
5052 bld
.LOAD_PAYLOAD(tmp
, sources
, 2, 0);
5055 srcs
[SURFACE_LOGICAL_SRC_DATA
] = data
;
5057 /* Emit the actual atomic operation */
5059 bld
.emit(SHADER_OPCODE_UNTYPED_ATOMIC_FLOAT_LOGICAL
,
5060 dest
, srcs
, SURFACE_LOGICAL_NUM_SRCS
);
5064 fs_visitor::nir_emit_shared_atomic(const fs_builder
&bld
,
5065 int op
, nir_intrinsic_instr
*instr
)
5068 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
5069 dest
= get_nir_dest(instr
->dest
);
5071 fs_reg srcs
[SURFACE_LOGICAL_NUM_SRCS
];
5072 srcs
[SURFACE_LOGICAL_SRC_SURFACE
] = brw_imm_ud(GEN7_BTI_SLM
);
5073 srcs
[SURFACE_LOGICAL_SRC_IMM_DIMS
] = brw_imm_ud(1);
5074 srcs
[SURFACE_LOGICAL_SRC_IMM_ARG
] = brw_imm_ud(op
);
5077 if (op
!= BRW_AOP_INC
&& op
!= BRW_AOP_DEC
&& op
!= BRW_AOP_PREDEC
)
5078 data
= get_nir_src(instr
->src
[1]);
5079 if (op
== BRW_AOP_CMPWR
) {
5080 fs_reg tmp
= bld
.vgrf(data
.type
, 2);
5081 fs_reg sources
[2] = { data
, get_nir_src(instr
->src
[2]) };
5082 bld
.LOAD_PAYLOAD(tmp
, sources
, 2, 0);
5085 srcs
[SURFACE_LOGICAL_SRC_DATA
] = data
;
5087 /* Get the offset */
5088 if (nir_src_is_const(instr
->src
[0])) {
5089 srcs
[SURFACE_LOGICAL_SRC_ADDRESS
] =
5090 brw_imm_ud(instr
->const_index
[0] + nir_src_as_uint(instr
->src
[0]));
5092 srcs
[SURFACE_LOGICAL_SRC_ADDRESS
] = vgrf(glsl_type::uint_type
);
5093 bld
.ADD(srcs
[SURFACE_LOGICAL_SRC_ADDRESS
],
5094 retype(get_nir_src(instr
->src
[0]), BRW_REGISTER_TYPE_UD
),
5095 brw_imm_ud(instr
->const_index
[0]));
5098 /* Emit the actual atomic operation operation */
5100 bld
.emit(SHADER_OPCODE_UNTYPED_ATOMIC_LOGICAL
,
5101 dest
, srcs
, SURFACE_LOGICAL_NUM_SRCS
);
5105 fs_visitor::nir_emit_shared_atomic_float(const fs_builder
&bld
,
5106 int op
, nir_intrinsic_instr
*instr
)
5109 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
5110 dest
= get_nir_dest(instr
->dest
);
5112 fs_reg srcs
[SURFACE_LOGICAL_NUM_SRCS
];
5113 srcs
[SURFACE_LOGICAL_SRC_SURFACE
] = brw_imm_ud(GEN7_BTI_SLM
);
5114 srcs
[SURFACE_LOGICAL_SRC_IMM_DIMS
] = brw_imm_ud(1);
5115 srcs
[SURFACE_LOGICAL_SRC_IMM_ARG
] = brw_imm_ud(op
);
5117 fs_reg data
= get_nir_src(instr
->src
[1]);
5118 if (op
== BRW_AOP_FCMPWR
) {
5119 fs_reg tmp
= bld
.vgrf(data
.type
, 2);
5120 fs_reg sources
[2] = { data
, get_nir_src(instr
->src
[2]) };
5121 bld
.LOAD_PAYLOAD(tmp
, sources
, 2, 0);
5124 srcs
[SURFACE_LOGICAL_SRC_DATA
] = data
;
5126 /* Get the offset */
5127 if (nir_src_is_const(instr
->src
[0])) {
5128 srcs
[SURFACE_LOGICAL_SRC_ADDRESS
] =
5129 brw_imm_ud(instr
->const_index
[0] + nir_src_as_uint(instr
->src
[0]));
5131 srcs
[SURFACE_LOGICAL_SRC_ADDRESS
] = vgrf(glsl_type::uint_type
);
5132 bld
.ADD(srcs
[SURFACE_LOGICAL_SRC_ADDRESS
],
5133 retype(get_nir_src(instr
->src
[0]), BRW_REGISTER_TYPE_UD
),
5134 brw_imm_ud(instr
->const_index
[0]));
5137 /* Emit the actual atomic operation operation */
5139 bld
.emit(SHADER_OPCODE_UNTYPED_ATOMIC_FLOAT_LOGICAL
,
5140 dest
, srcs
, SURFACE_LOGICAL_NUM_SRCS
);
5144 fs_visitor::nir_emit_global_atomic(const fs_builder
&bld
,
5145 int op
, nir_intrinsic_instr
*instr
)
5147 if (stage
== MESA_SHADER_FRAGMENT
)
5148 brw_wm_prog_data(prog_data
)->has_side_effects
= true;
5151 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
5152 dest
= get_nir_dest(instr
->dest
);
5154 fs_reg addr
= get_nir_src(instr
->src
[0]);
5157 if (op
!= BRW_AOP_INC
&& op
!= BRW_AOP_DEC
&& op
!= BRW_AOP_PREDEC
)
5158 data
= get_nir_src(instr
->src
[1]);
5160 if (op
== BRW_AOP_CMPWR
) {
5161 fs_reg tmp
= bld
.vgrf(data
.type
, 2);
5162 fs_reg sources
[2] = { data
, get_nir_src(instr
->src
[2]) };
5163 bld
.LOAD_PAYLOAD(tmp
, sources
, 2, 0);
5167 if (nir_dest_bit_size(instr
->dest
) == 64) {
5168 bld
.emit(SHADER_OPCODE_A64_UNTYPED_ATOMIC_INT64_LOGICAL
,
5169 dest
, addr
, data
, brw_imm_ud(op
));
5171 assert(nir_dest_bit_size(instr
->dest
) == 32);
5172 bld
.emit(SHADER_OPCODE_A64_UNTYPED_ATOMIC_LOGICAL
,
5173 dest
, addr
, data
, brw_imm_ud(op
));
5178 fs_visitor::nir_emit_global_atomic_float(const fs_builder
&bld
,
5179 int op
, nir_intrinsic_instr
*instr
)
5181 if (stage
== MESA_SHADER_FRAGMENT
)
5182 brw_wm_prog_data(prog_data
)->has_side_effects
= true;
5184 assert(nir_intrinsic_infos
[instr
->intrinsic
].has_dest
);
5185 fs_reg dest
= get_nir_dest(instr
->dest
);
5187 fs_reg addr
= get_nir_src(instr
->src
[0]);
5189 assert(op
!= BRW_AOP_INC
&& op
!= BRW_AOP_DEC
&& op
!= BRW_AOP_PREDEC
);
5190 fs_reg data
= get_nir_src(instr
->src
[1]);
5192 if (op
== BRW_AOP_FCMPWR
) {
5193 fs_reg tmp
= bld
.vgrf(data
.type
, 2);
5194 fs_reg sources
[2] = { data
, get_nir_src(instr
->src
[2]) };
5195 bld
.LOAD_PAYLOAD(tmp
, sources
, 2, 0);
5199 bld
.emit(SHADER_OPCODE_A64_UNTYPED_ATOMIC_LOGICAL
,
5200 dest
, addr
, data
, brw_imm_ud(op
));
5204 fs_visitor::nir_emit_texture(const fs_builder
&bld
, nir_tex_instr
*instr
)
5206 unsigned texture
= instr
->texture_index
;
5207 unsigned sampler
= instr
->sampler_index
;
5209 fs_reg srcs
[TEX_LOGICAL_NUM_SRCS
];
5211 srcs
[TEX_LOGICAL_SRC_SURFACE
] = brw_imm_ud(texture
);
5212 srcs
[TEX_LOGICAL_SRC_SAMPLER
] = brw_imm_ud(sampler
);
5214 int lod_components
= 0;
5216 /* The hardware requires a LOD for buffer textures */
5217 if (instr
->sampler_dim
== GLSL_SAMPLER_DIM_BUF
)
5218 srcs
[TEX_LOGICAL_SRC_LOD
] = brw_imm_d(0);
5220 uint32_t header_bits
= 0;
5221 for (unsigned i
= 0; i
< instr
->num_srcs
; i
++) {
5222 fs_reg src
= get_nir_src(instr
->src
[i
].src
);
5223 switch (instr
->src
[i
].src_type
) {
5224 case nir_tex_src_bias
:
5225 srcs
[TEX_LOGICAL_SRC_LOD
] =
5226 retype(get_nir_src_imm(instr
->src
[i
].src
), BRW_REGISTER_TYPE_F
);
5228 case nir_tex_src_comparator
:
5229 srcs
[TEX_LOGICAL_SRC_SHADOW_C
] = retype(src
, BRW_REGISTER_TYPE_F
);
5231 case nir_tex_src_coord
:
5232 switch (instr
->op
) {
5234 case nir_texop_txf_ms
:
5235 case nir_texop_txf_ms_mcs
:
5236 case nir_texop_samples_identical
:
5237 srcs
[TEX_LOGICAL_SRC_COORDINATE
] = retype(src
, BRW_REGISTER_TYPE_D
);
5240 srcs
[TEX_LOGICAL_SRC_COORDINATE
] = retype(src
, BRW_REGISTER_TYPE_F
);
5244 case nir_tex_src_ddx
:
5245 srcs
[TEX_LOGICAL_SRC_LOD
] = retype(src
, BRW_REGISTER_TYPE_F
);
5246 lod_components
= nir_tex_instr_src_size(instr
, i
);
5248 case nir_tex_src_ddy
:
5249 srcs
[TEX_LOGICAL_SRC_LOD2
] = retype(src
, BRW_REGISTER_TYPE_F
);
5251 case nir_tex_src_lod
:
5252 switch (instr
->op
) {
5254 srcs
[TEX_LOGICAL_SRC_LOD
] =
5255 retype(get_nir_src_imm(instr
->src
[i
].src
), BRW_REGISTER_TYPE_UD
);
5258 srcs
[TEX_LOGICAL_SRC_LOD
] =
5259 retype(get_nir_src_imm(instr
->src
[i
].src
), BRW_REGISTER_TYPE_D
);
5262 srcs
[TEX_LOGICAL_SRC_LOD
] =
5263 retype(get_nir_src_imm(instr
->src
[i
].src
), BRW_REGISTER_TYPE_F
);
5267 case nir_tex_src_min_lod
:
5268 srcs
[TEX_LOGICAL_SRC_MIN_LOD
] =
5269 retype(get_nir_src_imm(instr
->src
[i
].src
), BRW_REGISTER_TYPE_F
);
5271 case nir_tex_src_ms_index
:
5272 srcs
[TEX_LOGICAL_SRC_SAMPLE_INDEX
] = retype(src
, BRW_REGISTER_TYPE_UD
);
5275 case nir_tex_src_offset
: {
5276 uint32_t offset_bits
= 0;
5277 if (brw_texture_offset(instr
, i
, &offset_bits
)) {
5278 header_bits
|= offset_bits
;
5280 srcs
[TEX_LOGICAL_SRC_TG4_OFFSET
] =
5281 retype(src
, BRW_REGISTER_TYPE_D
);
5286 case nir_tex_src_projector
:
5287 unreachable("should be lowered");
5289 case nir_tex_src_texture_offset
: {
5290 /* Emit code to evaluate the actual indexing expression */
5291 fs_reg tmp
= vgrf(glsl_type::uint_type
);
5292 bld
.ADD(tmp
, src
, brw_imm_ud(texture
));
5293 srcs
[TEX_LOGICAL_SRC_SURFACE
] = bld
.emit_uniformize(tmp
);
5297 case nir_tex_src_sampler_offset
: {
5298 /* Emit code to evaluate the actual indexing expression */
5299 fs_reg tmp
= vgrf(glsl_type::uint_type
);
5300 bld
.ADD(tmp
, src
, brw_imm_ud(sampler
));
5301 srcs
[TEX_LOGICAL_SRC_SAMPLER
] = bld
.emit_uniformize(tmp
);
5305 case nir_tex_src_texture_handle
:
5306 assert(nir_tex_instr_src_index(instr
, nir_tex_src_texture_offset
) == -1);
5307 srcs
[TEX_LOGICAL_SRC_SURFACE
] = fs_reg();
5308 srcs
[TEX_LOGICAL_SRC_SURFACE_HANDLE
] = bld
.emit_uniformize(src
);
5311 case nir_tex_src_sampler_handle
:
5312 assert(nir_tex_instr_src_index(instr
, nir_tex_src_sampler_offset
) == -1);
5313 srcs
[TEX_LOGICAL_SRC_SAMPLER
] = fs_reg();
5314 srcs
[TEX_LOGICAL_SRC_SAMPLER_HANDLE
] = bld
.emit_uniformize(src
);
5317 case nir_tex_src_ms_mcs
:
5318 assert(instr
->op
== nir_texop_txf_ms
);
5319 srcs
[TEX_LOGICAL_SRC_MCS
] = retype(src
, BRW_REGISTER_TYPE_D
);
5322 case nir_tex_src_plane
: {
5323 const uint32_t plane
= nir_src_as_uint(instr
->src
[i
].src
);
5324 const uint32_t texture_index
=
5325 instr
->texture_index
+
5326 stage_prog_data
->binding_table
.plane_start
[plane
] -
5327 stage_prog_data
->binding_table
.texture_start
;
5329 srcs
[TEX_LOGICAL_SRC_SURFACE
] = brw_imm_ud(texture_index
);
5334 unreachable("unknown texture source");
5338 if (srcs
[TEX_LOGICAL_SRC_MCS
].file
== BAD_FILE
&&
5339 (instr
->op
== nir_texop_txf_ms
||
5340 instr
->op
== nir_texop_samples_identical
)) {
5341 if (devinfo
->gen
>= 7 &&
5342 key_tex
->compressed_multisample_layout_mask
& (1 << texture
)) {
5343 srcs
[TEX_LOGICAL_SRC_MCS
] =
5344 emit_mcs_fetch(srcs
[TEX_LOGICAL_SRC_COORDINATE
],
5345 instr
->coord_components
,
5346 srcs
[TEX_LOGICAL_SRC_SURFACE
],
5347 srcs
[TEX_LOGICAL_SRC_SURFACE_HANDLE
]);
5349 srcs
[TEX_LOGICAL_SRC_MCS
] = brw_imm_ud(0u);
5353 srcs
[TEX_LOGICAL_SRC_COORD_COMPONENTS
] = brw_imm_d(instr
->coord_components
);
5354 srcs
[TEX_LOGICAL_SRC_GRAD_COMPONENTS
] = brw_imm_d(lod_components
);
5357 switch (instr
->op
) {
5359 opcode
= SHADER_OPCODE_TEX_LOGICAL
;
5362 opcode
= FS_OPCODE_TXB_LOGICAL
;
5365 opcode
= SHADER_OPCODE_TXL_LOGICAL
;
5368 opcode
= SHADER_OPCODE_TXD_LOGICAL
;
5371 opcode
= SHADER_OPCODE_TXF_LOGICAL
;
5373 case nir_texop_txf_ms
:
5374 if ((key_tex
->msaa_16
& (1 << sampler
)))
5375 opcode
= SHADER_OPCODE_TXF_CMS_W_LOGICAL
;
5377 opcode
= SHADER_OPCODE_TXF_CMS_LOGICAL
;
5379 case nir_texop_txf_ms_mcs
:
5380 opcode
= SHADER_OPCODE_TXF_MCS_LOGICAL
;
5382 case nir_texop_query_levels
:
5384 opcode
= SHADER_OPCODE_TXS_LOGICAL
;
5387 opcode
= SHADER_OPCODE_LOD_LOGICAL
;
5390 if (srcs
[TEX_LOGICAL_SRC_TG4_OFFSET
].file
!= BAD_FILE
)
5391 opcode
= SHADER_OPCODE_TG4_OFFSET_LOGICAL
;
5393 opcode
= SHADER_OPCODE_TG4_LOGICAL
;
5395 case nir_texop_texture_samples
:
5396 opcode
= SHADER_OPCODE_SAMPLEINFO_LOGICAL
;
5398 case nir_texop_samples_identical
: {
5399 fs_reg dst
= retype(get_nir_dest(instr
->dest
), BRW_REGISTER_TYPE_D
);
5401 /* If mcs is an immediate value, it means there is no MCS. In that case
5402 * just return false.
5404 if (srcs
[TEX_LOGICAL_SRC_MCS
].file
== BRW_IMMEDIATE_VALUE
) {
5405 bld
.MOV(dst
, brw_imm_ud(0u));
5406 } else if ((key_tex
->msaa_16
& (1 << sampler
))) {
5407 fs_reg tmp
= vgrf(glsl_type::uint_type
);
5408 bld
.OR(tmp
, srcs
[TEX_LOGICAL_SRC_MCS
],
5409 offset(srcs
[TEX_LOGICAL_SRC_MCS
], bld
, 1));
5410 bld
.CMP(dst
, tmp
, brw_imm_ud(0u), BRW_CONDITIONAL_EQ
);
5412 bld
.CMP(dst
, srcs
[TEX_LOGICAL_SRC_MCS
], brw_imm_ud(0u),
5413 BRW_CONDITIONAL_EQ
);
5418 unreachable("unknown texture opcode");
5421 if (instr
->op
== nir_texop_tg4
) {
5422 if (instr
->component
== 1 &&
5423 key_tex
->gather_channel_quirk_mask
& (1 << texture
)) {
5424 /* gather4 sampler is broken for green channel on RG32F --
5425 * we must ask for blue instead.
5427 header_bits
|= 2 << 16;
5429 header_bits
|= instr
->component
<< 16;
5433 fs_reg dst
= bld
.vgrf(brw_type_for_nir_type(devinfo
, instr
->dest_type
), 4);
5434 fs_inst
*inst
= bld
.emit(opcode
, dst
, srcs
, ARRAY_SIZE(srcs
));
5435 inst
->offset
= header_bits
;
5437 const unsigned dest_size
= nir_tex_instr_dest_size(instr
);
5438 if (devinfo
->gen
>= 9 &&
5439 instr
->op
!= nir_texop_tg4
&& instr
->op
!= nir_texop_query_levels
) {
5440 unsigned write_mask
= instr
->dest
.is_ssa
?
5441 nir_ssa_def_components_read(&instr
->dest
.ssa
):
5442 (1 << dest_size
) - 1;
5443 assert(write_mask
!= 0); /* dead code should have been eliminated */
5444 inst
->size_written
= util_last_bit(write_mask
) *
5445 inst
->dst
.component_size(inst
->exec_size
);
5447 inst
->size_written
= 4 * inst
->dst
.component_size(inst
->exec_size
);
5450 if (srcs
[TEX_LOGICAL_SRC_SHADOW_C
].file
!= BAD_FILE
)
5451 inst
->shadow_compare
= true;
5453 if (instr
->op
== nir_texop_tg4
&& devinfo
->gen
== 6)
5454 emit_gen6_gather_wa(key_tex
->gen6_gather_wa
[texture
], dst
);
5457 for (unsigned i
= 0; i
< dest_size
; i
++)
5458 nir_dest
[i
] = offset(dst
, bld
, i
);
5460 if (instr
->op
== nir_texop_query_levels
) {
5461 /* # levels is in .w */
5462 nir_dest
[0] = offset(dst
, bld
, 3);
5463 } else if (instr
->op
== nir_texop_txs
&&
5464 dest_size
>= 3 && devinfo
->gen
< 7) {
5465 /* Gen4-6 return 0 instead of 1 for single layer surfaces. */
5466 fs_reg depth
= offset(dst
, bld
, 2);
5467 nir_dest
[2] = vgrf(glsl_type::int_type
);
5468 bld
.emit_minmax(nir_dest
[2], depth
, brw_imm_d(1), BRW_CONDITIONAL_GE
);
5471 bld
.LOAD_PAYLOAD(get_nir_dest(instr
->dest
), nir_dest
, dest_size
, 0);
5475 fs_visitor::nir_emit_jump(const fs_builder
&bld
, nir_jump_instr
*instr
)
5477 switch (instr
->type
) {
5478 case nir_jump_break
:
5479 bld
.emit(BRW_OPCODE_BREAK
);
5481 case nir_jump_continue
:
5482 bld
.emit(BRW_OPCODE_CONTINUE
);
5484 case nir_jump_return
:
5486 unreachable("unknown jump");
5491 * This helper takes a source register and un/shuffles it into the destination
5494 * If source type size is smaller than destination type size the operation
5495 * needed is a component shuffle. The opposite case would be an unshuffle. If
5496 * source/destination type size is equal a shuffle is done that would be
5497 * equivalent to a simple MOV.
5499 * For example, if source is a 16-bit type and destination is 32-bit. A 3
5500 * components .xyz 16-bit vector on SIMD8 would be.
5502 * |x1|x2|x3|x4|x5|x6|x7|x8|y1|y2|y3|y4|y5|y6|y7|y8|
5503 * |z1|z2|z3|z4|z5|z6|z7|z8| | | | | | | | |
5505 * This helper will return the following 2 32-bit components with the 16-bit
5508 * |x1 y1|x2 y2|x3 y3|x4 y4|x5 y5|x6 y6|x7 y7|x8 y8|
5509 * |z1 |z2 |z3 |z4 |z5 |z6 |z7 |z8 |
5511 * For unshuffle, the example would be the opposite, a 64-bit type source
5512 * and a 32-bit destination. A 2 component .xy 64-bit vector on SIMD8
5515 * | x1l x1h | x2l x2h | x3l x3h | x4l x4h |
5516 * | x5l x5h | x6l x6h | x7l x7h | x8l x8h |
5517 * | y1l y1h | y2l y2h | y3l y3h | y4l y4h |
5518 * | y5l y5h | y6l y6h | y7l y7h | y8l y8h |
5520 * The returned result would be the following 4 32-bit components unshuffled:
5522 * | x1l | x2l | x3l | x4l | x5l | x6l | x7l | x8l |
5523 * | x1h | x2h | x3h | x4h | x5h | x6h | x7h | x8h |
5524 * | y1l | y2l | y3l | y4l | y5l | y6l | y7l | y8l |
5525 * | y1h | y2h | y3h | y4h | y5h | y6h | y7h | y8h |
5527 * - Source and destination register must not be overlapped.
5528 * - components units are measured in terms of the smaller type between
5529 * source and destination because we are un/shuffling the smaller
5530 * components from/into the bigger ones.
5531 * - first_component parameter allows skipping source components.
5534 shuffle_src_to_dst(const fs_builder
&bld
,
5537 uint32_t first_component
,
5538 uint32_t components
)
5540 if (type_sz(src
.type
) == type_sz(dst
.type
)) {
5541 assert(!regions_overlap(dst
,
5542 type_sz(dst
.type
) * bld
.dispatch_width() * components
,
5543 offset(src
, bld
, first_component
),
5544 type_sz(src
.type
) * bld
.dispatch_width() * components
));
5545 for (unsigned i
= 0; i
< components
; i
++) {
5546 bld
.MOV(retype(offset(dst
, bld
, i
), src
.type
),
5547 offset(src
, bld
, i
+ first_component
));
5549 } else if (type_sz(src
.type
) < type_sz(dst
.type
)) {
5550 /* Source is shuffled into destination */
5551 unsigned size_ratio
= type_sz(dst
.type
) / type_sz(src
.type
);
5552 assert(!regions_overlap(dst
,
5553 type_sz(dst
.type
) * bld
.dispatch_width() *
5554 DIV_ROUND_UP(components
, size_ratio
),
5555 offset(src
, bld
, first_component
),
5556 type_sz(src
.type
) * bld
.dispatch_width() * components
));
5558 brw_reg_type shuffle_type
=
5559 brw_reg_type_from_bit_size(8 * type_sz(src
.type
),
5560 BRW_REGISTER_TYPE_D
);
5561 for (unsigned i
= 0; i
< components
; i
++) {
5562 fs_reg shuffle_component_i
=
5563 subscript(offset(dst
, bld
, i
/ size_ratio
),
5564 shuffle_type
, i
% size_ratio
);
5565 bld
.MOV(shuffle_component_i
,
5566 retype(offset(src
, bld
, i
+ first_component
), shuffle_type
));
5569 /* Source is unshuffled into destination */
5570 unsigned size_ratio
= type_sz(src
.type
) / type_sz(dst
.type
);
5571 assert(!regions_overlap(dst
,
5572 type_sz(dst
.type
) * bld
.dispatch_width() * components
,
5573 offset(src
, bld
, first_component
/ size_ratio
),
5574 type_sz(src
.type
) * bld
.dispatch_width() *
5575 DIV_ROUND_UP(components
+ (first_component
% size_ratio
),
5578 brw_reg_type shuffle_type
=
5579 brw_reg_type_from_bit_size(8 * type_sz(dst
.type
),
5580 BRW_REGISTER_TYPE_D
);
5581 for (unsigned i
= 0; i
< components
; i
++) {
5582 fs_reg shuffle_component_i
=
5583 subscript(offset(src
, bld
, (first_component
+ i
) / size_ratio
),
5584 shuffle_type
, (first_component
+ i
) % size_ratio
);
5585 bld
.MOV(retype(offset(dst
, bld
, i
), shuffle_type
),
5586 shuffle_component_i
);
5592 shuffle_from_32bit_read(const fs_builder
&bld
,
5595 uint32_t first_component
,
5596 uint32_t components
)
5598 assert(type_sz(src
.type
) == 4);
5600 /* This function takes components in units of the destination type while
5601 * shuffle_src_to_dst takes components in units of the smallest type
5603 if (type_sz(dst
.type
) > 4) {
5604 assert(type_sz(dst
.type
) == 8);
5605 first_component
*= 2;
5609 shuffle_src_to_dst(bld
, dst
, src
, first_component
, components
);
5613 shuffle_for_32bit_write(const fs_builder
&bld
,
5615 uint32_t first_component
,
5616 uint32_t components
)
5618 fs_reg dst
= bld
.vgrf(BRW_REGISTER_TYPE_D
,
5619 DIV_ROUND_UP (components
* type_sz(src
.type
), 4));
5620 /* This function takes components in units of the source type while
5621 * shuffle_src_to_dst takes components in units of the smallest type
5623 if (type_sz(src
.type
) > 4) {
5624 assert(type_sz(src
.type
) == 8);
5625 first_component
*= 2;
5629 shuffle_src_to_dst(bld
, dst
, src
, first_component
, components
);
5635 setup_imm_df(const fs_builder
&bld
, double v
)
5637 const struct gen_device_info
*devinfo
= bld
.shader
->devinfo
;
5638 assert(devinfo
->gen
>= 7);
5640 if (devinfo
->gen
>= 8)
5641 return brw_imm_df(v
);
5643 /* gen7.5 does not support DF immediates straighforward but the DIM
5644 * instruction allows to set the 64-bit immediate value.
5646 if (devinfo
->is_haswell
) {
5647 const fs_builder ubld
= bld
.exec_all().group(1, 0);
5648 fs_reg dst
= ubld
.vgrf(BRW_REGISTER_TYPE_DF
, 1);
5649 ubld
.DIM(dst
, brw_imm_df(v
));
5650 return component(dst
, 0);
5653 /* gen7 does not support DF immediates, so we generate a 64-bit constant by
5654 * writing the low 32-bit of the constant to suboffset 0 of a VGRF and
5655 * the high 32-bit to suboffset 4 and then applying a stride of 0.
5657 * Alternatively, we could also produce a normal VGRF (without stride 0)
5658 * by writing to all the channels in the VGRF, however, that would hit the
5659 * gen7 bug where we have to split writes that span more than 1 register
5660 * into instructions with a width of 4 (otherwise the write to the second
5661 * register written runs into an execmask hardware bug) which isn't very
5674 const fs_builder ubld
= bld
.exec_all().group(1, 0);
5675 const fs_reg tmp
= ubld
.vgrf(BRW_REGISTER_TYPE_UD
, 2);
5676 ubld
.MOV(tmp
, brw_imm_ud(di
.i1
));
5677 ubld
.MOV(horiz_offset(tmp
, 1), brw_imm_ud(di
.i2
));
5679 return component(retype(tmp
, BRW_REGISTER_TYPE_DF
), 0);
5683 setup_imm_b(const fs_builder
&bld
, int8_t v
)
5685 const fs_reg tmp
= bld
.vgrf(BRW_REGISTER_TYPE_B
);
5686 bld
.MOV(tmp
, brw_imm_w(v
));
5691 setup_imm_ub(const fs_builder
&bld
, uint8_t v
)
5693 const fs_reg tmp
= bld
.vgrf(BRW_REGISTER_TYPE_UB
);
5694 bld
.MOV(tmp
, brw_imm_uw(v
));