2 * Copyright © 2010 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 #include "compiler/glsl/ir.h"
26 #include "brw_fs_surface_builder.h"
30 using namespace brw::surface_access
;
33 fs_visitor::emit_nir_code()
35 /* emit the arrays used for inputs and outputs - load/store intrinsics will
36 * be converted to reads/writes of these arrays
40 nir_emit_system_values();
42 /* get the main function and emit it */
43 nir_foreach_function(function
, nir
) {
44 assert(strcmp(function
->name
, "main") == 0);
45 assert(function
->impl
);
46 nir_emit_impl(function
->impl
);
51 fs_visitor::nir_setup_outputs()
53 if (stage
== MESA_SHADER_TESS_CTRL
|| stage
== MESA_SHADER_FRAGMENT
)
56 unsigned vec4s
[VARYING_SLOT_TESS_MAX
] = { 0, };
58 /* Calculate the size of output registers in a separate pass, before
59 * allocating them. With ARB_enhanced_layouts, multiple output variables
60 * may occupy the same slot, but have different type sizes.
62 nir_foreach_variable(var
, &nir
->outputs
) {
63 const int loc
= var
->data
.driver_location
;
64 const unsigned var_vec4s
=
65 var
->data
.compact
? DIV_ROUND_UP(glsl_get_length(var
->type
), 4)
66 : type_size_vec4(var
->type
);
67 vec4s
[loc
] = MAX2(vec4s
[loc
], var_vec4s
);
70 nir_foreach_variable(var
, &nir
->outputs
) {
71 const int loc
= var
->data
.driver_location
;
72 if (outputs
[loc
].file
== BAD_FILE
) {
73 fs_reg reg
= bld
.vgrf(BRW_REGISTER_TYPE_F
, 4 * vec4s
[loc
]);
74 for (unsigned i
= 0; i
< vec4s
[loc
]; i
++) {
75 outputs
[loc
+ i
] = offset(reg
, bld
, 4 * i
);
82 fs_visitor::nir_setup_uniforms()
84 /* Only the first compile gets to set up uniforms. */
85 if (push_constant_loc
) {
86 assert(pull_constant_loc
);
90 uniforms
= nir
->num_uniforms
/ 4;
92 if (stage
== MESA_SHADER_COMPUTE
) {
93 /* Add a uniform for the thread local id. It must be the last uniform
96 assert(uniforms
== prog_data
->nr_params
);
97 uint32_t *param
= brw_stage_prog_data_add_params(prog_data
, 1);
98 *param
= BRW_PARAM_BUILTIN_SUBGROUP_ID
;
99 subgroup_id
= fs_reg(UNIFORM
, uniforms
++, BRW_REGISTER_TYPE_UD
);
104 emit_system_values_block(nir_block
*block
, fs_visitor
*v
)
108 nir_foreach_instr(instr
, block
) {
109 if (instr
->type
!= nir_instr_type_intrinsic
)
112 nir_intrinsic_instr
*intrin
= nir_instr_as_intrinsic(instr
);
113 switch (intrin
->intrinsic
) {
114 case nir_intrinsic_load_vertex_id
:
115 unreachable("should be lowered by lower_vertex_id().");
117 case nir_intrinsic_load_vertex_id_zero_base
:
118 case nir_intrinsic_load_base_vertex
:
119 case nir_intrinsic_load_instance_id
:
120 case nir_intrinsic_load_base_instance
:
121 case nir_intrinsic_load_draw_id
:
122 unreachable("should be lowered by brw_nir_lower_vs_inputs().");
124 case nir_intrinsic_load_invocation_id
:
125 if (v
->stage
== MESA_SHADER_TESS_CTRL
)
127 assert(v
->stage
== MESA_SHADER_GEOMETRY
);
128 reg
= &v
->nir_system_values
[SYSTEM_VALUE_INVOCATION_ID
];
129 if (reg
->file
== BAD_FILE
) {
130 const fs_builder abld
= v
->bld
.annotate("gl_InvocationID", NULL
);
131 fs_reg
g1(retype(brw_vec8_grf(1, 0), BRW_REGISTER_TYPE_UD
));
132 fs_reg iid
= abld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
133 abld
.SHR(iid
, g1
, brw_imm_ud(27u));
138 case nir_intrinsic_load_sample_pos
:
139 assert(v
->stage
== MESA_SHADER_FRAGMENT
);
140 reg
= &v
->nir_system_values
[SYSTEM_VALUE_SAMPLE_POS
];
141 if (reg
->file
== BAD_FILE
)
142 *reg
= *v
->emit_samplepos_setup();
145 case nir_intrinsic_load_sample_id
:
146 assert(v
->stage
== MESA_SHADER_FRAGMENT
);
147 reg
= &v
->nir_system_values
[SYSTEM_VALUE_SAMPLE_ID
];
148 if (reg
->file
== BAD_FILE
)
149 *reg
= *v
->emit_sampleid_setup();
152 case nir_intrinsic_load_sample_mask_in
:
153 assert(v
->stage
== MESA_SHADER_FRAGMENT
);
154 assert(v
->devinfo
->gen
>= 7);
155 reg
= &v
->nir_system_values
[SYSTEM_VALUE_SAMPLE_MASK_IN
];
156 if (reg
->file
== BAD_FILE
)
157 *reg
= *v
->emit_samplemaskin_setup();
160 case nir_intrinsic_load_work_group_id
:
161 assert(v
->stage
== MESA_SHADER_COMPUTE
);
162 reg
= &v
->nir_system_values
[SYSTEM_VALUE_WORK_GROUP_ID
];
163 if (reg
->file
== BAD_FILE
)
164 *reg
= *v
->emit_cs_work_group_id_setup();
167 case nir_intrinsic_load_helper_invocation
:
168 assert(v
->stage
== MESA_SHADER_FRAGMENT
);
169 reg
= &v
->nir_system_values
[SYSTEM_VALUE_HELPER_INVOCATION
];
170 if (reg
->file
== BAD_FILE
) {
171 const fs_builder abld
=
172 v
->bld
.annotate("gl_HelperInvocation", NULL
);
174 /* On Gen6+ (gl_HelperInvocation is only exposed on Gen7+) the
175 * pixel mask is in g1.7 of the thread payload.
177 * We move the per-channel pixel enable bit to the low bit of each
178 * channel by shifting the byte containing the pixel mask by the
179 * vector immediate 0x76543210UV.
181 * The region of <1,8,0> reads only 1 byte (the pixel masks for
182 * subspans 0 and 1) in SIMD8 and an additional byte (the pixel
183 * masks for 2 and 3) in SIMD16.
185 fs_reg shifted
= abld
.vgrf(BRW_REGISTER_TYPE_UW
, 1);
187 stride(byte_offset(retype(brw_vec1_grf(1, 0),
188 BRW_REGISTER_TYPE_UB
), 28),
190 brw_imm_v(0x76543210));
192 /* A set bit in the pixel mask means the channel is enabled, but
193 * that is the opposite of gl_HelperInvocation so we need to invert
196 * The negate source-modifier bit of logical instructions on Gen8+
197 * performs 1's complement negation, so we can use that instead of
200 fs_reg inverted
= negate(shifted
);
201 if (v
->devinfo
->gen
< 8) {
202 inverted
= abld
.vgrf(BRW_REGISTER_TYPE_UW
);
203 abld
.NOT(inverted
, shifted
);
206 /* We then resolve the 0/1 result to 0/~0 boolean values by ANDing
207 * with 1 and negating.
209 fs_reg anded
= abld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
210 abld
.AND(anded
, inverted
, brw_imm_uw(1));
212 fs_reg dst
= abld
.vgrf(BRW_REGISTER_TYPE_D
, 1);
213 abld
.MOV(dst
, negate(retype(anded
, BRW_REGISTER_TYPE_D
)));
227 fs_visitor::nir_emit_system_values()
229 nir_system_values
= ralloc_array(mem_ctx
, fs_reg
, SYSTEM_VALUE_MAX
);
230 for (unsigned i
= 0; i
< SYSTEM_VALUE_MAX
; i
++) {
231 nir_system_values
[i
] = fs_reg();
234 /* Always emit SUBGROUP_INVOCATION. Dead code will clean it up if we
235 * never end up using it.
238 const fs_builder abld
= bld
.annotate("gl_SubgroupInvocation", NULL
);
239 fs_reg
®
= nir_system_values
[SYSTEM_VALUE_SUBGROUP_INVOCATION
];
240 reg
= abld
.vgrf(BRW_REGISTER_TYPE_W
);
242 const fs_builder allbld8
= abld
.group(8, 0).exec_all();
243 allbld8
.MOV(reg
, brw_imm_v(0x76543210));
244 if (dispatch_width
> 8)
245 allbld8
.ADD(byte_offset(reg
, 16), reg
, brw_imm_uw(8u));
246 if (dispatch_width
> 16) {
247 const fs_builder allbld16
= abld
.group(16, 0).exec_all();
248 allbld16
.ADD(byte_offset(reg
, 32), reg
, brw_imm_uw(16u));
252 nir_foreach_function(function
, nir
) {
253 assert(strcmp(function
->name
, "main") == 0);
254 assert(function
->impl
);
255 nir_foreach_block(block
, function
->impl
) {
256 emit_system_values_block(block
, this);
262 * Returns a type based on a reference_type (word, float, half-float) and a
265 * Reference BRW_REGISTER_TYPE are HF,F,DF,W,D,UW,UD.
267 * @FIXME: 64-bit return types are always DF on integer types to maintain
268 * compability with uses of DF previously to the introduction of int64
272 brw_reg_type_from_bit_size(const unsigned bit_size
,
273 const brw_reg_type reference_type
)
275 switch(reference_type
) {
276 case BRW_REGISTER_TYPE_HF
:
277 case BRW_REGISTER_TYPE_F
:
278 case BRW_REGISTER_TYPE_DF
:
281 return BRW_REGISTER_TYPE_HF
;
283 return BRW_REGISTER_TYPE_F
;
285 return BRW_REGISTER_TYPE_DF
;
287 unreachable("Invalid bit size");
289 case BRW_REGISTER_TYPE_W
:
290 case BRW_REGISTER_TYPE_D
:
291 case BRW_REGISTER_TYPE_Q
:
294 return BRW_REGISTER_TYPE_W
;
296 return BRW_REGISTER_TYPE_D
;
298 return BRW_REGISTER_TYPE_DF
;
300 unreachable("Invalid bit size");
302 case BRW_REGISTER_TYPE_UW
:
303 case BRW_REGISTER_TYPE_UD
:
304 case BRW_REGISTER_TYPE_UQ
:
307 return BRW_REGISTER_TYPE_UW
;
309 return BRW_REGISTER_TYPE_UD
;
311 return BRW_REGISTER_TYPE_DF
;
313 unreachable("Invalid bit size");
316 unreachable("Unknown type");
321 fs_visitor::nir_emit_impl(nir_function_impl
*impl
)
323 nir_locals
= ralloc_array(mem_ctx
, fs_reg
, impl
->reg_alloc
);
324 for (unsigned i
= 0; i
< impl
->reg_alloc
; i
++) {
325 nir_locals
[i
] = fs_reg();
328 foreach_list_typed(nir_register
, reg
, node
, &impl
->registers
) {
329 unsigned array_elems
=
330 reg
->num_array_elems
== 0 ? 1 : reg
->num_array_elems
;
331 unsigned size
= array_elems
* reg
->num_components
;
332 const brw_reg_type reg_type
=
333 brw_reg_type_from_bit_size(reg
->bit_size
, BRW_REGISTER_TYPE_F
);
334 nir_locals
[reg
->index
] = bld
.vgrf(reg_type
, size
);
337 nir_ssa_values
= reralloc(mem_ctx
, nir_ssa_values
, fs_reg
,
340 nir_emit_cf_list(&impl
->body
);
344 fs_visitor::nir_emit_cf_list(exec_list
*list
)
346 exec_list_validate(list
);
347 foreach_list_typed(nir_cf_node
, node
, node
, list
) {
348 switch (node
->type
) {
350 nir_emit_if(nir_cf_node_as_if(node
));
353 case nir_cf_node_loop
:
354 nir_emit_loop(nir_cf_node_as_loop(node
));
357 case nir_cf_node_block
:
358 nir_emit_block(nir_cf_node_as_block(node
));
362 unreachable("Invalid CFG node block");
368 fs_visitor::nir_emit_if(nir_if
*if_stmt
)
370 /* first, put the condition into f0 */
371 fs_inst
*inst
= bld
.MOV(bld
.null_reg_d(),
372 retype(get_nir_src(if_stmt
->condition
),
373 BRW_REGISTER_TYPE_D
));
374 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
376 bld
.IF(BRW_PREDICATE_NORMAL
);
378 nir_emit_cf_list(&if_stmt
->then_list
);
380 /* note: if the else is empty, dead CF elimination will remove it */
381 bld
.emit(BRW_OPCODE_ELSE
);
383 nir_emit_cf_list(&if_stmt
->else_list
);
385 bld
.emit(BRW_OPCODE_ENDIF
);
389 fs_visitor::nir_emit_loop(nir_loop
*loop
)
391 bld
.emit(BRW_OPCODE_DO
);
393 nir_emit_cf_list(&loop
->body
);
395 bld
.emit(BRW_OPCODE_WHILE
);
399 fs_visitor::nir_emit_block(nir_block
*block
)
401 nir_foreach_instr(instr
, block
) {
402 nir_emit_instr(instr
);
407 fs_visitor::nir_emit_instr(nir_instr
*instr
)
409 const fs_builder abld
= bld
.annotate(NULL
, instr
);
411 switch (instr
->type
) {
412 case nir_instr_type_alu
:
413 nir_emit_alu(abld
, nir_instr_as_alu(instr
));
416 case nir_instr_type_intrinsic
:
418 case MESA_SHADER_VERTEX
:
419 nir_emit_vs_intrinsic(abld
, nir_instr_as_intrinsic(instr
));
421 case MESA_SHADER_TESS_CTRL
:
422 nir_emit_tcs_intrinsic(abld
, nir_instr_as_intrinsic(instr
));
424 case MESA_SHADER_TESS_EVAL
:
425 nir_emit_tes_intrinsic(abld
, nir_instr_as_intrinsic(instr
));
427 case MESA_SHADER_GEOMETRY
:
428 nir_emit_gs_intrinsic(abld
, nir_instr_as_intrinsic(instr
));
430 case MESA_SHADER_FRAGMENT
:
431 nir_emit_fs_intrinsic(abld
, nir_instr_as_intrinsic(instr
));
433 case MESA_SHADER_COMPUTE
:
434 nir_emit_cs_intrinsic(abld
, nir_instr_as_intrinsic(instr
));
437 unreachable("unsupported shader stage");
441 case nir_instr_type_tex
:
442 nir_emit_texture(abld
, nir_instr_as_tex(instr
));
445 case nir_instr_type_load_const
:
446 nir_emit_load_const(abld
, nir_instr_as_load_const(instr
));
449 case nir_instr_type_ssa_undef
:
450 /* We create a new VGRF for undefs on every use (by handling
451 * them in get_nir_src()), rather than for each definition.
452 * This helps register coalescing eliminate MOVs from undef.
456 case nir_instr_type_jump
:
457 nir_emit_jump(abld
, nir_instr_as_jump(instr
));
461 unreachable("unknown instruction type");
466 * Recognizes a parent instruction of nir_op_extract_* and changes the type to
470 fs_visitor::optimize_extract_to_float(nir_alu_instr
*instr
,
471 const fs_reg
&result
)
473 if (!instr
->src
[0].src
.is_ssa
||
474 !instr
->src
[0].src
.ssa
->parent_instr
)
477 if (instr
->src
[0].src
.ssa
->parent_instr
->type
!= nir_instr_type_alu
)
480 nir_alu_instr
*src0
=
481 nir_instr_as_alu(instr
->src
[0].src
.ssa
->parent_instr
);
483 if (src0
->op
!= nir_op_extract_u8
&& src0
->op
!= nir_op_extract_u16
&&
484 src0
->op
!= nir_op_extract_i8
&& src0
->op
!= nir_op_extract_i16
)
487 nir_const_value
*element
= nir_src_as_const_value(src0
->src
[1].src
);
488 assert(element
!= NULL
);
490 /* Element type to extract.*/
491 const brw_reg_type type
= brw_int_type(
492 src0
->op
== nir_op_extract_u16
|| src0
->op
== nir_op_extract_i16
? 2 : 1,
493 src0
->op
== nir_op_extract_i16
|| src0
->op
== nir_op_extract_i8
);
495 fs_reg op0
= get_nir_src(src0
->src
[0].src
);
496 op0
.type
= brw_type_for_nir_type(devinfo
,
497 (nir_alu_type
)(nir_op_infos
[src0
->op
].input_types
[0] |
498 nir_src_bit_size(src0
->src
[0].src
)));
499 op0
= offset(op0
, bld
, src0
->src
[0].swizzle
[0]);
501 set_saturate(instr
->dest
.saturate
,
502 bld
.MOV(result
, subscript(op0
, type
, element
->u32
[0])));
507 fs_visitor::optimize_frontfacing_ternary(nir_alu_instr
*instr
,
508 const fs_reg
&result
)
510 if (!instr
->src
[0].src
.is_ssa
||
511 instr
->src
[0].src
.ssa
->parent_instr
->type
!= nir_instr_type_intrinsic
)
514 nir_intrinsic_instr
*src0
=
515 nir_instr_as_intrinsic(instr
->src
[0].src
.ssa
->parent_instr
);
517 if (src0
->intrinsic
!= nir_intrinsic_load_front_face
)
520 nir_const_value
*value1
= nir_src_as_const_value(instr
->src
[1].src
);
521 if (!value1
|| fabsf(value1
->f32
[0]) != 1.0f
)
524 nir_const_value
*value2
= nir_src_as_const_value(instr
->src
[2].src
);
525 if (!value2
|| fabsf(value2
->f32
[0]) != 1.0f
)
528 fs_reg tmp
= vgrf(glsl_type::int_type
);
530 if (devinfo
->gen
>= 6) {
531 /* Bit 15 of g0.0 is 0 if the polygon is front facing. */
532 fs_reg g0
= fs_reg(retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_W
));
534 /* For (gl_FrontFacing ? 1.0 : -1.0), emit:
536 * or(8) tmp.1<2>W g0.0<0,1,0>W 0x00003f80W
537 * and(8) dst<1>D tmp<8,8,1>D 0xbf800000D
539 * and negate g0.0<0,1,0>W for (gl_FrontFacing ? -1.0 : 1.0).
541 * This negation looks like it's safe in practice, because bits 0:4 will
542 * surely be TRIANGLES
545 if (value1
->f32
[0] == -1.0f
) {
549 bld
.OR(subscript(tmp
, BRW_REGISTER_TYPE_W
, 1),
550 g0
, brw_imm_uw(0x3f80));
552 /* Bit 31 of g1.6 is 0 if the polygon is front facing. */
553 fs_reg g1_6
= fs_reg(retype(brw_vec1_grf(1, 6), BRW_REGISTER_TYPE_D
));
555 /* For (gl_FrontFacing ? 1.0 : -1.0), emit:
557 * or(8) tmp<1>D g1.6<0,1,0>D 0x3f800000D
558 * and(8) dst<1>D tmp<8,8,1>D 0xbf800000D
560 * and negate g1.6<0,1,0>D for (gl_FrontFacing ? -1.0 : 1.0).
562 * This negation looks like it's safe in practice, because bits 0:4 will
563 * surely be TRIANGLES
566 if (value1
->f32
[0] == -1.0f
) {
570 bld
.OR(tmp
, g1_6
, brw_imm_d(0x3f800000));
572 bld
.AND(retype(result
, BRW_REGISTER_TYPE_D
), tmp
, brw_imm_d(0xbf800000));
578 emit_find_msb_using_lzd(const fs_builder
&bld
,
579 const fs_reg
&result
,
587 /* LZD of an absolute value source almost always does the right
588 * thing. There are two problem values:
590 * * 0x80000000. Since abs(0x80000000) == 0x80000000, LZD returns
591 * 0. However, findMSB(int(0x80000000)) == 30.
593 * * 0xffffffff. Since abs(0xffffffff) == 1, LZD returns
594 * 31. Section 8.8 (Integer Functions) of the GLSL 4.50 spec says:
596 * For a value of zero or negative one, -1 will be returned.
598 * * Negative powers of two. LZD(abs(-(1<<x))) returns x, but
599 * findMSB(-(1<<x)) should return x-1.
601 * For all negative number cases, including 0x80000000 and
602 * 0xffffffff, the correct value is obtained from LZD if instead of
603 * negating the (already negative) value the logical-not is used. A
604 * conditonal logical-not can be achieved in two instructions.
606 temp
= bld
.vgrf(BRW_REGISTER_TYPE_D
);
608 bld
.ASR(temp
, src
, brw_imm_d(31));
609 bld
.XOR(temp
, temp
, src
);
612 bld
.LZD(retype(result
, BRW_REGISTER_TYPE_UD
),
613 retype(temp
, BRW_REGISTER_TYPE_UD
));
615 /* LZD counts from the MSB side, while GLSL's findMSB() wants the count
616 * from the LSB side. Subtract the result from 31 to convert the MSB
617 * count into an LSB count. If no bits are set, LZD will return 32.
618 * 31-32 = -1, which is exactly what findMSB() is supposed to return.
620 inst
= bld
.ADD(result
, retype(result
, BRW_REGISTER_TYPE_D
), brw_imm_d(31));
621 inst
->src
[0].negate
= true;
625 fs_visitor::nir_emit_alu(const fs_builder
&bld
, nir_alu_instr
*instr
)
627 struct brw_wm_prog_key
*fs_key
= (struct brw_wm_prog_key
*) this->key
;
630 fs_reg result
= get_nir_dest(instr
->dest
.dest
);
631 result
.type
= brw_type_for_nir_type(devinfo
,
632 (nir_alu_type
)(nir_op_infos
[instr
->op
].output_type
|
633 nir_dest_bit_size(instr
->dest
.dest
)));
636 for (unsigned i
= 0; i
< nir_op_infos
[instr
->op
].num_inputs
; i
++) {
637 op
[i
] = get_nir_src(instr
->src
[i
].src
);
638 op
[i
].type
= brw_type_for_nir_type(devinfo
,
639 (nir_alu_type
)(nir_op_infos
[instr
->op
].input_types
[i
] |
640 nir_src_bit_size(instr
->src
[i
].src
)));
641 op
[i
].abs
= instr
->src
[i
].abs
;
642 op
[i
].negate
= instr
->src
[i
].negate
;
645 /* We get a bunch of mov's out of the from_ssa pass and they may still
646 * be vectorized. We'll handle them as a special-case. We'll also
647 * handle vecN here because it's basically the same thing.
655 fs_reg temp
= result
;
656 bool need_extra_copy
= false;
657 for (unsigned i
= 0; i
< nir_op_infos
[instr
->op
].num_inputs
; i
++) {
658 if (!instr
->src
[i
].src
.is_ssa
&&
659 instr
->dest
.dest
.reg
.reg
== instr
->src
[i
].src
.reg
.reg
) {
660 need_extra_copy
= true;
661 temp
= bld
.vgrf(result
.type
, 4);
666 for (unsigned i
= 0; i
< 4; i
++) {
667 if (!(instr
->dest
.write_mask
& (1 << i
)))
670 if (instr
->op
== nir_op_imov
|| instr
->op
== nir_op_fmov
) {
671 inst
= bld
.MOV(offset(temp
, bld
, i
),
672 offset(op
[0], bld
, instr
->src
[0].swizzle
[i
]));
674 inst
= bld
.MOV(offset(temp
, bld
, i
),
675 offset(op
[i
], bld
, instr
->src
[i
].swizzle
[0]));
677 inst
->saturate
= instr
->dest
.saturate
;
680 /* In this case the source and destination registers were the same,
681 * so we need to insert an extra set of moves in order to deal with
684 if (need_extra_copy
) {
685 for (unsigned i
= 0; i
< 4; i
++) {
686 if (!(instr
->dest
.write_mask
& (1 << i
)))
689 bld
.MOV(offset(result
, bld
, i
), offset(temp
, bld
, i
));
698 /* At this point, we have dealt with any instruction that operates on
699 * more than a single channel. Therefore, we can just adjust the source
700 * and destination registers for that channel and emit the instruction.
702 unsigned channel
= 0;
703 if (nir_op_infos
[instr
->op
].output_size
== 0) {
704 /* Since NIR is doing the scalarizing for us, we should only ever see
705 * vectorized operations with a single channel.
707 assert(_mesa_bitcount(instr
->dest
.write_mask
) == 1);
708 channel
= ffs(instr
->dest
.write_mask
) - 1;
710 result
= offset(result
, bld
, channel
);
713 for (unsigned i
= 0; i
< nir_op_infos
[instr
->op
].num_inputs
; i
++) {
714 assert(nir_op_infos
[instr
->op
].input_sizes
[i
] < 2);
715 op
[i
] = offset(op
[i
], bld
, instr
->src
[i
].swizzle
[channel
]);
721 if (optimize_extract_to_float(instr
, result
))
723 inst
= bld
.MOV(result
, op
[0]);
724 inst
->saturate
= instr
->dest
.saturate
;
730 /* CHV PRM, vol07, 3D Media GPGPU Engine, Register Region Restrictions:
732 * "When source or destination is 64b (...), regioning in Align1
733 * must follow these rules:
735 * 1. Source and destination horizontal stride must be aligned to
739 * This means that 32-bit to 64-bit conversions need to have the 32-bit
740 * data elements aligned to 64-bit. This restriction does not apply to
743 if (nir_dest_bit_size(instr
->dest
.dest
) == 64 &&
744 nir_src_bit_size(instr
->src
[0].src
) == 32 &&
745 (devinfo
->is_cherryview
|| gen_device_info_is_9lp(devinfo
))) {
746 fs_reg tmp
= bld
.vgrf(result
.type
, 1);
747 tmp
= subscript(tmp
, op
[0].type
, 0);
748 inst
= bld
.MOV(tmp
, op
[0]);
749 inst
= bld
.MOV(result
, tmp
);
750 inst
->saturate
= instr
->dest
.saturate
;
763 inst
= bld
.MOV(result
, op
[0]);
764 inst
->saturate
= instr
->dest
.saturate
;
769 /* Straightforward since the source can be assumed to be
772 set_condmod(BRW_CONDITIONAL_NZ
, bld
.MOV(result
, op
[0]));
773 set_predicate(BRW_PREDICATE_NORMAL
, bld
.MOV(result
, brw_imm_f(1.0f
)));
775 } else if (type_sz(op
[0].type
) < 8) {
776 /* AND(val, 0x80000000) gives the sign bit.
778 * Predicated OR ORs 1.0 (0x3f800000) with the sign bit if val is not
781 bld
.CMP(bld
.null_reg_f(), op
[0], brw_imm_f(0.0f
), BRW_CONDITIONAL_NZ
);
783 fs_reg result_int
= retype(result
, BRW_REGISTER_TYPE_UD
);
784 op
[0].type
= BRW_REGISTER_TYPE_UD
;
785 result
.type
= BRW_REGISTER_TYPE_UD
;
786 bld
.AND(result_int
, op
[0], brw_imm_ud(0x80000000u
));
788 inst
= bld
.OR(result_int
, result_int
, brw_imm_ud(0x3f800000u
));
789 inst
->predicate
= BRW_PREDICATE_NORMAL
;
790 if (instr
->dest
.saturate
) {
791 inst
= bld
.MOV(result
, result
);
792 inst
->saturate
= true;
795 /* For doubles we do the same but we need to consider:
797 * - 2-src instructions can't operate with 64-bit immediates
798 * - The sign is encoded in the high 32-bit of each DF
799 * - We need to produce a DF result.
802 fs_reg zero
= vgrf(glsl_type::double_type
);
803 bld
.MOV(zero
, setup_imm_df(bld
, 0.0));
804 bld
.CMP(bld
.null_reg_df(), op
[0], zero
, BRW_CONDITIONAL_NZ
);
806 bld
.MOV(result
, zero
);
808 fs_reg r
= subscript(result
, BRW_REGISTER_TYPE_UD
, 1);
809 bld
.AND(r
, subscript(op
[0], BRW_REGISTER_TYPE_UD
, 1),
810 brw_imm_ud(0x80000000u
));
812 set_predicate(BRW_PREDICATE_NORMAL
,
813 bld
.OR(r
, r
, brw_imm_ud(0x3ff00000u
)));
815 if (instr
->dest
.saturate
) {
816 inst
= bld
.MOV(result
, result
);
817 inst
->saturate
= true;
824 /* ASR(val, 31) -> negative val generates 0xffffffff (signed -1).
825 * -> non-negative val generates 0x00000000.
826 * Predicated OR sets 1 if val is positive.
828 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
829 bld
.CMP(bld
.null_reg_d(), op
[0], brw_imm_d(0), BRW_CONDITIONAL_G
);
830 bld
.ASR(result
, op
[0], brw_imm_d(31));
831 inst
= bld
.OR(result
, result
, brw_imm_d(1));
832 inst
->predicate
= BRW_PREDICATE_NORMAL
;
836 inst
= bld
.emit(SHADER_OPCODE_RCP
, result
, op
[0]);
837 inst
->saturate
= instr
->dest
.saturate
;
841 inst
= bld
.emit(SHADER_OPCODE_EXP2
, result
, op
[0]);
842 inst
->saturate
= instr
->dest
.saturate
;
846 inst
= bld
.emit(SHADER_OPCODE_LOG2
, result
, op
[0]);
847 inst
->saturate
= instr
->dest
.saturate
;
851 inst
= bld
.emit(SHADER_OPCODE_SIN
, result
, op
[0]);
852 inst
->saturate
= instr
->dest
.saturate
;
856 inst
= bld
.emit(SHADER_OPCODE_COS
, result
, op
[0]);
857 inst
->saturate
= instr
->dest
.saturate
;
861 if (fs_key
->high_quality_derivatives
) {
862 inst
= bld
.emit(FS_OPCODE_DDX_FINE
, result
, op
[0]);
864 inst
= bld
.emit(FS_OPCODE_DDX_COARSE
, result
, op
[0]);
866 inst
->saturate
= instr
->dest
.saturate
;
868 case nir_op_fddx_fine
:
869 inst
= bld
.emit(FS_OPCODE_DDX_FINE
, result
, op
[0]);
870 inst
->saturate
= instr
->dest
.saturate
;
872 case nir_op_fddx_coarse
:
873 inst
= bld
.emit(FS_OPCODE_DDX_COARSE
, result
, op
[0]);
874 inst
->saturate
= instr
->dest
.saturate
;
877 if (fs_key
->high_quality_derivatives
) {
878 inst
= bld
.emit(FS_OPCODE_DDY_FINE
, result
, op
[0]);
880 inst
= bld
.emit(FS_OPCODE_DDY_COARSE
, result
, op
[0]);
882 inst
->saturate
= instr
->dest
.saturate
;
884 case nir_op_fddy_fine
:
885 inst
= bld
.emit(FS_OPCODE_DDY_FINE
, result
, op
[0]);
886 inst
->saturate
= instr
->dest
.saturate
;
888 case nir_op_fddy_coarse
:
889 inst
= bld
.emit(FS_OPCODE_DDY_COARSE
, result
, op
[0]);
890 inst
->saturate
= instr
->dest
.saturate
;
895 inst
= bld
.ADD(result
, op
[0], op
[1]);
896 inst
->saturate
= instr
->dest
.saturate
;
900 inst
= bld
.MUL(result
, op
[0], op
[1]);
901 inst
->saturate
= instr
->dest
.saturate
;
905 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
906 bld
.MUL(result
, op
[0], op
[1]);
909 case nir_op_imul_high
:
910 case nir_op_umul_high
:
911 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
912 bld
.emit(SHADER_OPCODE_MULH
, result
, op
[0], op
[1]);
917 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
918 bld
.emit(SHADER_OPCODE_INT_QUOTIENT
, result
, op
[0], op
[1]);
921 case nir_op_uadd_carry
:
922 unreachable("Should have been lowered by carry_to_arith().");
924 case nir_op_usub_borrow
:
925 unreachable("Should have been lowered by borrow_to_arith().");
929 /* According to the sign table for INT DIV in the Ivy Bridge PRM, it
930 * appears that our hardware just does the right thing for signed
933 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
934 bld
.emit(SHADER_OPCODE_INT_REMAINDER
, result
, op
[0], op
[1]);
938 /* Get a regular C-style remainder. If a % b == 0, set the predicate. */
939 bld
.emit(SHADER_OPCODE_INT_REMAINDER
, result
, op
[0], op
[1]);
941 /* Math instructions don't support conditional mod */
942 inst
= bld
.MOV(bld
.null_reg_d(), result
);
943 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
945 /* Now, we need to determine if signs of the sources are different.
946 * When we XOR the sources, the top bit is 0 if they are the same and 1
947 * if they are different. We can then use a conditional modifier to
948 * turn that into a predicate. This leads us to an XOR.l instruction.
950 * Technically, according to the PRM, you're not allowed to use .l on a
951 * XOR instruction. However, emperical experiments and Curro's reading
952 * of the simulator source both indicate that it's safe.
954 fs_reg tmp
= bld
.vgrf(BRW_REGISTER_TYPE_D
);
955 inst
= bld
.XOR(tmp
, op
[0], op
[1]);
956 inst
->predicate
= BRW_PREDICATE_NORMAL
;
957 inst
->conditional_mod
= BRW_CONDITIONAL_L
;
959 /* If the result of the initial remainder operation is non-zero and the
960 * two sources have different signs, add in a copy of op[1] to get the
961 * final integer modulus value.
963 inst
= bld
.ADD(result
, result
, op
[1]);
964 inst
->predicate
= BRW_PREDICATE_NORMAL
;
972 fs_reg dest
= result
;
973 if (nir_src_bit_size(instr
->src
[0].src
) > 32) {
974 dest
= bld
.vgrf(BRW_REGISTER_TYPE_DF
, 1);
976 brw_conditional_mod cond
;
979 cond
= BRW_CONDITIONAL_L
;
982 cond
= BRW_CONDITIONAL_GE
;
985 cond
= BRW_CONDITIONAL_Z
;
988 cond
= BRW_CONDITIONAL_NZ
;
991 unreachable("bad opcode");
993 bld
.CMP(dest
, op
[0], op
[1], cond
);
994 if (nir_src_bit_size(instr
->src
[0].src
) > 32) {
995 bld
.MOV(result
, subscript(dest
, BRW_REGISTER_TYPE_UD
, 0));
1006 fs_reg dest
= result
;
1007 if (nir_src_bit_size(instr
->src
[0].src
) > 32) {
1008 dest
= bld
.vgrf(BRW_REGISTER_TYPE_UQ
, 1);
1011 brw_conditional_mod cond
;
1012 switch (instr
->op
) {
1015 cond
= BRW_CONDITIONAL_L
;
1019 cond
= BRW_CONDITIONAL_GE
;
1022 cond
= BRW_CONDITIONAL_Z
;
1025 cond
= BRW_CONDITIONAL_NZ
;
1028 unreachable("bad opcode");
1030 bld
.CMP(dest
, op
[0], op
[1], cond
);
1031 if (nir_src_bit_size(instr
->src
[0].src
) > 32) {
1032 bld
.MOV(result
, subscript(dest
, BRW_REGISTER_TYPE_UD
, 0));
1038 if (devinfo
->gen
>= 8) {
1039 op
[0] = resolve_source_modifiers(op
[0]);
1041 bld
.NOT(result
, op
[0]);
1044 if (devinfo
->gen
>= 8) {
1045 op
[0] = resolve_source_modifiers(op
[0]);
1046 op
[1] = resolve_source_modifiers(op
[1]);
1048 bld
.XOR(result
, op
[0], op
[1]);
1051 if (devinfo
->gen
>= 8) {
1052 op
[0] = resolve_source_modifiers(op
[0]);
1053 op
[1] = resolve_source_modifiers(op
[1]);
1055 bld
.OR(result
, op
[0], op
[1]);
1058 if (devinfo
->gen
>= 8) {
1059 op
[0] = resolve_source_modifiers(op
[0]);
1060 op
[1] = resolve_source_modifiers(op
[1]);
1062 bld
.AND(result
, op
[0], op
[1]);
1068 case nir_op_ball_fequal2
:
1069 case nir_op_ball_iequal2
:
1070 case nir_op_ball_fequal3
:
1071 case nir_op_ball_iequal3
:
1072 case nir_op_ball_fequal4
:
1073 case nir_op_ball_iequal4
:
1074 case nir_op_bany_fnequal2
:
1075 case nir_op_bany_inequal2
:
1076 case nir_op_bany_fnequal3
:
1077 case nir_op_bany_inequal3
:
1078 case nir_op_bany_fnequal4
:
1079 case nir_op_bany_inequal4
:
1080 unreachable("Lowered by nir_lower_alu_reductions");
1082 case nir_op_fnoise1_1
:
1083 case nir_op_fnoise1_2
:
1084 case nir_op_fnoise1_3
:
1085 case nir_op_fnoise1_4
:
1086 case nir_op_fnoise2_1
:
1087 case nir_op_fnoise2_2
:
1088 case nir_op_fnoise2_3
:
1089 case nir_op_fnoise2_4
:
1090 case nir_op_fnoise3_1
:
1091 case nir_op_fnoise3_2
:
1092 case nir_op_fnoise3_3
:
1093 case nir_op_fnoise3_4
:
1094 case nir_op_fnoise4_1
:
1095 case nir_op_fnoise4_2
:
1096 case nir_op_fnoise4_3
:
1097 case nir_op_fnoise4_4
:
1098 unreachable("not reached: should be handled by lower_noise");
1101 unreachable("not reached: should be handled by ldexp_to_arith()");
1104 inst
= bld
.emit(SHADER_OPCODE_SQRT
, result
, op
[0]);
1105 inst
->saturate
= instr
->dest
.saturate
;
1109 inst
= bld
.emit(SHADER_OPCODE_RSQ
, result
, op
[0]);
1110 inst
->saturate
= instr
->dest
.saturate
;
1115 bld
.MOV(result
, negate(op
[0]));
1120 if (nir_src_bit_size(instr
->src
[0].src
) == 64) {
1121 /* two-argument instructions can't take 64-bit immediates */
1125 if (instr
->op
== nir_op_f2b
) {
1126 zero
= vgrf(glsl_type::double_type
);
1127 tmp
= vgrf(glsl_type::double_type
);
1129 zero
= vgrf(glsl_type::int64_t_type
);
1130 tmp
= vgrf(glsl_type::int64_t_type
);
1133 bld
.MOV(zero
, setup_imm_df(bld
, 0.0));
1134 /* A SIMD16 execution needs to be split in two instructions, so use
1135 * a vgrf instead of the flag register as dst so instruction splitting
1138 bld
.CMP(tmp
, op
[0], zero
, BRW_CONDITIONAL_NZ
);
1139 bld
.MOV(result
, subscript(tmp
, BRW_REGISTER_TYPE_UD
, 0));
1141 if (instr
->op
== nir_op_f2b
) {
1142 bld
.CMP(result
, op
[0], brw_imm_f(0.0f
), BRW_CONDITIONAL_NZ
);
1144 bld
.CMP(result
, op
[0], brw_imm_d(0), BRW_CONDITIONAL_NZ
);
1150 inst
= bld
.RNDZ(result
, op
[0]);
1151 inst
->saturate
= instr
->dest
.saturate
;
1154 case nir_op_fceil
: {
1155 op
[0].negate
= !op
[0].negate
;
1156 fs_reg temp
= vgrf(glsl_type::float_type
);
1157 bld
.RNDD(temp
, op
[0]);
1159 inst
= bld
.MOV(result
, temp
);
1160 inst
->saturate
= instr
->dest
.saturate
;
1164 inst
= bld
.RNDD(result
, op
[0]);
1165 inst
->saturate
= instr
->dest
.saturate
;
1168 inst
= bld
.FRC(result
, op
[0]);
1169 inst
->saturate
= instr
->dest
.saturate
;
1171 case nir_op_fround_even
:
1172 inst
= bld
.RNDE(result
, op
[0]);
1173 inst
->saturate
= instr
->dest
.saturate
;
1176 case nir_op_fquantize2f16
: {
1177 fs_reg tmp16
= bld
.vgrf(BRW_REGISTER_TYPE_D
);
1178 fs_reg tmp32
= bld
.vgrf(BRW_REGISTER_TYPE_F
);
1179 fs_reg zero
= bld
.vgrf(BRW_REGISTER_TYPE_F
);
1181 /* The destination stride must be at least as big as the source stride. */
1182 tmp16
.type
= BRW_REGISTER_TYPE_W
;
1185 /* Check for denormal */
1186 fs_reg abs_src0
= op
[0];
1187 abs_src0
.abs
= true;
1188 bld
.CMP(bld
.null_reg_f(), abs_src0
, brw_imm_f(ldexpf(1.0, -14)),
1190 /* Get the appropriately signed zero */
1191 bld
.AND(retype(zero
, BRW_REGISTER_TYPE_UD
),
1192 retype(op
[0], BRW_REGISTER_TYPE_UD
),
1193 brw_imm_ud(0x80000000));
1194 /* Do the actual F32 -> F16 -> F32 conversion */
1195 bld
.emit(BRW_OPCODE_F32TO16
, tmp16
, op
[0]);
1196 bld
.emit(BRW_OPCODE_F16TO32
, tmp32
, tmp16
);
1197 /* Select that or zero based on normal status */
1198 inst
= bld
.SEL(result
, zero
, tmp32
);
1199 inst
->predicate
= BRW_PREDICATE_NORMAL
;
1200 inst
->saturate
= instr
->dest
.saturate
;
1207 inst
= bld
.emit_minmax(result
, op
[0], op
[1], BRW_CONDITIONAL_L
);
1208 inst
->saturate
= instr
->dest
.saturate
;
1214 inst
= bld
.emit_minmax(result
, op
[0], op
[1], BRW_CONDITIONAL_GE
);
1215 inst
->saturate
= instr
->dest
.saturate
;
1218 case nir_op_pack_snorm_2x16
:
1219 case nir_op_pack_snorm_4x8
:
1220 case nir_op_pack_unorm_2x16
:
1221 case nir_op_pack_unorm_4x8
:
1222 case nir_op_unpack_snorm_2x16
:
1223 case nir_op_unpack_snorm_4x8
:
1224 case nir_op_unpack_unorm_2x16
:
1225 case nir_op_unpack_unorm_4x8
:
1226 case nir_op_unpack_half_2x16
:
1227 case nir_op_pack_half_2x16
:
1228 unreachable("not reached: should be handled by lower_packing_builtins");
1230 case nir_op_unpack_half_2x16_split_x
:
1231 inst
= bld
.emit(FS_OPCODE_UNPACK_HALF_2x16_SPLIT_X
, result
, op
[0]);
1232 inst
->saturate
= instr
->dest
.saturate
;
1234 case nir_op_unpack_half_2x16_split_y
:
1235 inst
= bld
.emit(FS_OPCODE_UNPACK_HALF_2x16_SPLIT_Y
, result
, op
[0]);
1236 inst
->saturate
= instr
->dest
.saturate
;
1239 case nir_op_pack_64_2x32_split
:
1240 bld
.emit(FS_OPCODE_PACK
, result
, op
[0], op
[1]);
1243 case nir_op_unpack_64_2x32_split_x
:
1244 case nir_op_unpack_64_2x32_split_y
: {
1245 if (instr
->op
== nir_op_unpack_64_2x32_split_x
)
1246 bld
.MOV(result
, subscript(op
[0], BRW_REGISTER_TYPE_UD
, 0));
1248 bld
.MOV(result
, subscript(op
[0], BRW_REGISTER_TYPE_UD
, 1));
1253 inst
= bld
.emit(SHADER_OPCODE_POW
, result
, op
[0], op
[1]);
1254 inst
->saturate
= instr
->dest
.saturate
;
1257 case nir_op_bitfield_reverse
:
1258 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1259 bld
.BFREV(result
, op
[0]);
1262 case nir_op_bit_count
:
1263 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1264 bld
.CBIT(result
, op
[0]);
1267 case nir_op_ufind_msb
: {
1268 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1269 emit_find_msb_using_lzd(bld
, result
, op
[0], false);
1273 case nir_op_ifind_msb
: {
1274 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1276 if (devinfo
->gen
< 7) {
1277 emit_find_msb_using_lzd(bld
, result
, op
[0], true);
1279 bld
.FBH(retype(result
, BRW_REGISTER_TYPE_UD
), op
[0]);
1281 /* FBH counts from the MSB side, while GLSL's findMSB() wants the
1282 * count from the LSB side. If FBH didn't return an error
1283 * (0xFFFFFFFF), then subtract the result from 31 to convert the MSB
1284 * count into an LSB count.
1286 bld
.CMP(bld
.null_reg_d(), result
, brw_imm_d(-1), BRW_CONDITIONAL_NZ
);
1288 inst
= bld
.ADD(result
, result
, brw_imm_d(31));
1289 inst
->predicate
= BRW_PREDICATE_NORMAL
;
1290 inst
->src
[0].negate
= true;
1295 case nir_op_find_lsb
:
1296 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1298 if (devinfo
->gen
< 7) {
1299 fs_reg temp
= vgrf(glsl_type::int_type
);
1301 /* (x & -x) generates a value that consists of only the LSB of x.
1302 * For all powers of 2, findMSB(y) == findLSB(y).
1304 fs_reg src
= retype(op
[0], BRW_REGISTER_TYPE_D
);
1305 fs_reg negated_src
= src
;
1307 /* One must be negated, and the other must be non-negated. It
1308 * doesn't matter which is which.
1310 negated_src
.negate
= true;
1313 bld
.AND(temp
, src
, negated_src
);
1314 emit_find_msb_using_lzd(bld
, result
, temp
, false);
1316 bld
.FBL(result
, op
[0]);
1320 case nir_op_ubitfield_extract
:
1321 case nir_op_ibitfield_extract
:
1322 unreachable("should have been lowered");
1325 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1326 bld
.BFE(result
, op
[2], op
[1], op
[0]);
1329 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1330 bld
.BFI1(result
, op
[0], op
[1]);
1333 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1334 bld
.BFI2(result
, op
[0], op
[1], op
[2]);
1337 case nir_op_bitfield_insert
:
1338 unreachable("not reached: should have been lowered");
1343 fs_reg shift_count
= op
[1];
1345 if (devinfo
->is_cherryview
|| gen_device_info_is_9lp(devinfo
)) {
1346 if (op
[1].file
== VGRF
&&
1347 (result
.type
== BRW_REGISTER_TYPE_Q
||
1348 result
.type
== BRW_REGISTER_TYPE_UQ
)) {
1349 shift_count
= fs_reg(VGRF
, alloc
.allocate(dispatch_width
/ 4),
1350 BRW_REGISTER_TYPE_UD
);
1351 shift_count
.stride
= 2;
1352 bld
.MOV(shift_count
, op
[1]);
1356 switch (instr
->op
) {
1358 bld
.SHL(result
, op
[0], shift_count
);
1361 bld
.ASR(result
, op
[0], shift_count
);
1364 bld
.SHR(result
, op
[0], shift_count
);
1367 unreachable("not reached");
1372 case nir_op_pack_half_2x16_split
:
1373 bld
.emit(FS_OPCODE_PACK_HALF_2x16_SPLIT
, result
, op
[0], op
[1]);
1377 inst
= bld
.MAD(result
, op
[2], op
[1], op
[0]);
1378 inst
->saturate
= instr
->dest
.saturate
;
1382 inst
= bld
.LRP(result
, op
[0], op
[1], op
[2]);
1383 inst
->saturate
= instr
->dest
.saturate
;
1387 if (optimize_frontfacing_ternary(instr
, result
))
1390 bld
.CMP(bld
.null_reg_d(), op
[0], brw_imm_d(0), BRW_CONDITIONAL_NZ
);
1391 inst
= bld
.SEL(result
, op
[1], op
[2]);
1392 inst
->predicate
= BRW_PREDICATE_NORMAL
;
1395 case nir_op_extract_u8
:
1396 case nir_op_extract_i8
: {
1397 const brw_reg_type type
= brw_int_type(1, instr
->op
== nir_op_extract_i8
);
1398 nir_const_value
*byte
= nir_src_as_const_value(instr
->src
[1].src
);
1399 assert(byte
!= NULL
);
1400 bld
.MOV(result
, subscript(op
[0], type
, byte
->u32
[0]));
1404 case nir_op_extract_u16
:
1405 case nir_op_extract_i16
: {
1406 const brw_reg_type type
= brw_int_type(2, instr
->op
== nir_op_extract_i16
);
1407 nir_const_value
*word
= nir_src_as_const_value(instr
->src
[1].src
);
1408 assert(word
!= NULL
);
1409 bld
.MOV(result
, subscript(op
[0], type
, word
->u32
[0]));
1414 unreachable("unhandled instruction");
1417 /* If we need to do a boolean resolve, replace the result with -(x & 1)
1418 * to sign extend the low bit to 0/~0
1420 if (devinfo
->gen
<= 5 &&
1421 (instr
->instr
.pass_flags
& BRW_NIR_BOOLEAN_MASK
) == BRW_NIR_BOOLEAN_NEEDS_RESOLVE
) {
1422 fs_reg masked
= vgrf(glsl_type::int_type
);
1423 bld
.AND(masked
, result
, brw_imm_d(1));
1424 masked
.negate
= true;
1425 bld
.MOV(retype(result
, BRW_REGISTER_TYPE_D
), masked
);
1430 fs_visitor::nir_emit_load_const(const fs_builder
&bld
,
1431 nir_load_const_instr
*instr
)
1433 const brw_reg_type reg_type
=
1434 brw_reg_type_from_bit_size(instr
->def
.bit_size
, BRW_REGISTER_TYPE_D
);
1435 fs_reg reg
= bld
.vgrf(reg_type
, instr
->def
.num_components
);
1437 switch (instr
->def
.bit_size
) {
1439 for (unsigned i
= 0; i
< instr
->def
.num_components
; i
++)
1440 bld
.MOV(offset(reg
, bld
, i
), brw_imm_d(instr
->value
.i32
[i
]));
1444 for (unsigned i
= 0; i
< instr
->def
.num_components
; i
++)
1445 bld
.MOV(offset(reg
, bld
, i
),
1446 setup_imm_df(bld
, instr
->value
.f64
[i
]));
1450 unreachable("Invalid bit size");
1453 nir_ssa_values
[instr
->def
.index
] = reg
;
1457 fs_visitor::get_nir_src(const nir_src
&src
)
1461 if (src
.ssa
->parent_instr
->type
== nir_instr_type_ssa_undef
) {
1462 const brw_reg_type reg_type
=
1463 brw_reg_type_from_bit_size(src
.ssa
->bit_size
, BRW_REGISTER_TYPE_D
);
1464 reg
= bld
.vgrf(reg_type
, src
.ssa
->num_components
);
1466 reg
= nir_ssa_values
[src
.ssa
->index
];
1469 /* We don't handle indirects on locals */
1470 assert(src
.reg
.indirect
== NULL
);
1471 reg
= offset(nir_locals
[src
.reg
.reg
->index
], bld
,
1472 src
.reg
.base_offset
* src
.reg
.reg
->num_components
);
1475 if (nir_src_bit_size(src
) == 64 && devinfo
->gen
== 7) {
1476 /* The only 64-bit type available on gen7 is DF, so use that. */
1477 reg
.type
= BRW_REGISTER_TYPE_DF
;
1479 /* To avoid floating-point denorm flushing problems, set the type by
1480 * default to an integer type - instructions that need floating point
1481 * semantics will set this to F if they need to
1483 reg
.type
= brw_reg_type_from_bit_size(nir_src_bit_size(src
),
1484 BRW_REGISTER_TYPE_D
);
1491 * Return an IMM for constants; otherwise call get_nir_src() as normal.
1493 * This function should not be called on any value which may be 64 bits.
1494 * We could theoretically support 64-bit on gen8+ but we choose not to
1495 * because it wouldn't work in general (no gen7 support) and there are
1496 * enough restrictions in 64-bit immediates that you can't take the return
1497 * value and treat it the same as the result of get_nir_src().
1500 fs_visitor::get_nir_src_imm(const nir_src
&src
)
1502 nir_const_value
*val
= nir_src_as_const_value(src
);
1503 assert(nir_src_bit_size(src
) == 32);
1504 return val
? fs_reg(brw_imm_d(val
->i32
[0])) : get_nir_src(src
);
1508 fs_visitor::get_nir_dest(const nir_dest
&dest
)
1511 const brw_reg_type reg_type
=
1512 brw_reg_type_from_bit_size(dest
.ssa
.bit_size
, BRW_REGISTER_TYPE_F
);
1513 nir_ssa_values
[dest
.ssa
.index
] =
1514 bld
.vgrf(reg_type
, dest
.ssa
.num_components
);
1515 return nir_ssa_values
[dest
.ssa
.index
];
1517 /* We don't handle indirects on locals */
1518 assert(dest
.reg
.indirect
== NULL
);
1519 return offset(nir_locals
[dest
.reg
.reg
->index
], bld
,
1520 dest
.reg
.base_offset
* dest
.reg
.reg
->num_components
);
1525 fs_visitor::get_nir_image_deref(const nir_deref_var
*deref
)
1527 fs_reg
image(UNIFORM
, deref
->var
->data
.driver_location
/ 4,
1528 BRW_REGISTER_TYPE_UD
);
1530 unsigned indirect_max
= 0;
1532 for (const nir_deref
*tail
= &deref
->deref
; tail
->child
;
1533 tail
= tail
->child
) {
1534 const nir_deref_array
*deref_array
= nir_deref_as_array(tail
->child
);
1535 assert(tail
->child
->deref_type
== nir_deref_type_array
);
1536 const unsigned size
= glsl_get_length(tail
->type
);
1537 const unsigned element_size
= type_size_scalar(deref_array
->deref
.type
);
1538 const unsigned base
= MIN2(deref_array
->base_offset
, size
- 1);
1539 image
= offset(image
, bld
, base
* element_size
);
1541 if (deref_array
->deref_array_type
== nir_deref_array_type_indirect
) {
1542 fs_reg tmp
= vgrf(glsl_type::uint_type
);
1544 /* Accessing an invalid surface index with the dataport can result
1545 * in a hang. According to the spec "if the index used to
1546 * select an individual element is negative or greater than or
1547 * equal to the size of the array, the results of the operation
1548 * are undefined but may not lead to termination" -- which is one
1549 * of the possible outcomes of the hang. Clamp the index to
1550 * prevent access outside of the array bounds.
1552 bld
.emit_minmax(tmp
, retype(get_nir_src(deref_array
->indirect
),
1553 BRW_REGISTER_TYPE_UD
),
1554 brw_imm_ud(size
- base
- 1), BRW_CONDITIONAL_L
);
1556 indirect_max
+= element_size
* (tail
->type
->length
- 1);
1558 bld
.MUL(tmp
, tmp
, brw_imm_ud(element_size
* 4));
1559 if (indirect
.file
== BAD_FILE
) {
1562 bld
.ADD(indirect
, indirect
, tmp
);
1567 if (indirect
.file
== BAD_FILE
) {
1570 /* Emit a pile of MOVs to load the uniform into a temporary. The
1571 * dead-code elimination pass will get rid of what we don't use.
1573 fs_reg tmp
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, BRW_IMAGE_PARAM_SIZE
);
1574 for (unsigned j
= 0; j
< BRW_IMAGE_PARAM_SIZE
; j
++) {
1575 bld
.emit(SHADER_OPCODE_MOV_INDIRECT
,
1576 offset(tmp
, bld
, j
), offset(image
, bld
, j
),
1577 indirect
, brw_imm_ud((indirect_max
+ 1) * 4));
1584 fs_visitor::emit_percomp(const fs_builder
&bld
, const fs_inst
&inst
,
1587 for (unsigned i
= 0; i
< 4; i
++) {
1588 if (!((wr_mask
>> i
) & 1))
1591 fs_inst
*new_inst
= new(mem_ctx
) fs_inst(inst
);
1592 new_inst
->dst
= offset(new_inst
->dst
, bld
, i
);
1593 for (unsigned j
= 0; j
< new_inst
->sources
; j
++)
1594 if (new_inst
->src
[j
].file
== VGRF
)
1595 new_inst
->src
[j
] = offset(new_inst
->src
[j
], bld
, i
);
1602 * Get the matching channel register datatype for an image intrinsic of the
1603 * specified GLSL image type.
1606 get_image_base_type(const glsl_type
*type
)
1608 switch ((glsl_base_type
)type
->sampled_type
) {
1609 case GLSL_TYPE_UINT
:
1610 return BRW_REGISTER_TYPE_UD
;
1612 return BRW_REGISTER_TYPE_D
;
1613 case GLSL_TYPE_FLOAT
:
1614 return BRW_REGISTER_TYPE_F
;
1616 unreachable("Not reached.");
1621 * Get the appropriate atomic op for an image atomic intrinsic.
1624 get_image_atomic_op(nir_intrinsic_op op
, const glsl_type
*type
)
1627 case nir_intrinsic_image_atomic_add
:
1629 case nir_intrinsic_image_atomic_min
:
1630 return (get_image_base_type(type
) == BRW_REGISTER_TYPE_D
?
1631 BRW_AOP_IMIN
: BRW_AOP_UMIN
);
1632 case nir_intrinsic_image_atomic_max
:
1633 return (get_image_base_type(type
) == BRW_REGISTER_TYPE_D
?
1634 BRW_AOP_IMAX
: BRW_AOP_UMAX
);
1635 case nir_intrinsic_image_atomic_and
:
1637 case nir_intrinsic_image_atomic_or
:
1639 case nir_intrinsic_image_atomic_xor
:
1641 case nir_intrinsic_image_atomic_exchange
:
1643 case nir_intrinsic_image_atomic_comp_swap
:
1644 return BRW_AOP_CMPWR
;
1646 unreachable("Not reachable.");
1651 emit_pixel_interpolater_send(const fs_builder
&bld
,
1656 glsl_interp_mode interpolation
)
1658 struct brw_wm_prog_data
*wm_prog_data
=
1659 brw_wm_prog_data(bld
.shader
->stage_prog_data
);
1664 if (src
.file
== BAD_FILE
) {
1666 payload
= bld
.vgrf(BRW_REGISTER_TYPE_F
, 1);
1670 mlen
= 2 * bld
.dispatch_width() / 8;
1673 inst
= bld
.emit(opcode
, dst
, payload
, desc
);
1675 /* 2 floats per slot returned */
1676 inst
->size_written
= 2 * dst
.component_size(inst
->exec_size
);
1677 inst
->pi_noperspective
= interpolation
== INTERP_MODE_NOPERSPECTIVE
;
1679 wm_prog_data
->pulls_bary
= true;
1685 * Computes 1 << x, given a D/UD register containing some value x.
1688 intexp2(const fs_builder
&bld
, const fs_reg
&x
)
1690 assert(x
.type
== BRW_REGISTER_TYPE_UD
|| x
.type
== BRW_REGISTER_TYPE_D
);
1692 fs_reg result
= bld
.vgrf(x
.type
, 1);
1693 fs_reg one
= bld
.vgrf(x
.type
, 1);
1695 bld
.MOV(one
, retype(brw_imm_d(1), one
.type
));
1696 bld
.SHL(result
, one
, x
);
1701 fs_visitor::emit_gs_end_primitive(const nir_src
&vertex_count_nir_src
)
1703 assert(stage
== MESA_SHADER_GEOMETRY
);
1705 struct brw_gs_prog_data
*gs_prog_data
= brw_gs_prog_data(prog_data
);
1707 if (gs_compile
->control_data_header_size_bits
== 0)
1710 /* We can only do EndPrimitive() functionality when the control data
1711 * consists of cut bits. Fortunately, the only time it isn't is when the
1712 * output type is points, in which case EndPrimitive() is a no-op.
1714 if (gs_prog_data
->control_data_format
!=
1715 GEN7_GS_CONTROL_DATA_FORMAT_GSCTL_CUT
) {
1719 /* Cut bits use one bit per vertex. */
1720 assert(gs_compile
->control_data_bits_per_vertex
== 1);
1722 fs_reg vertex_count
= get_nir_src(vertex_count_nir_src
);
1723 vertex_count
.type
= BRW_REGISTER_TYPE_UD
;
1725 /* Cut bit n should be set to 1 if EndPrimitive() was called after emitting
1726 * vertex n, 0 otherwise. So all we need to do here is mark bit
1727 * (vertex_count - 1) % 32 in the cut_bits register to indicate that
1728 * EndPrimitive() was called after emitting vertex (vertex_count - 1);
1729 * vec4_gs_visitor::emit_control_data_bits() will take care of the rest.
1731 * Note that if EndPrimitive() is called before emitting any vertices, this
1732 * will cause us to set bit 31 of the control_data_bits register to 1.
1733 * That's fine because:
1735 * - If max_vertices < 32, then vertex number 31 (zero-based) will never be
1736 * output, so the hardware will ignore cut bit 31.
1738 * - If max_vertices == 32, then vertex number 31 is guaranteed to be the
1739 * last vertex, so setting cut bit 31 has no effect (since the primitive
1740 * is automatically ended when the GS terminates).
1742 * - If max_vertices > 32, then the ir_emit_vertex visitor will reset the
1743 * control_data_bits register to 0 when the first vertex is emitted.
1746 const fs_builder abld
= bld
.annotate("end primitive");
1748 /* control_data_bits |= 1 << ((vertex_count - 1) % 32) */
1749 fs_reg prev_count
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
1750 abld
.ADD(prev_count
, vertex_count
, brw_imm_ud(0xffffffffu
));
1751 fs_reg mask
= intexp2(abld
, prev_count
);
1752 /* Note: we're relying on the fact that the GEN SHL instruction only pays
1753 * attention to the lower 5 bits of its second source argument, so on this
1754 * architecture, 1 << (vertex_count - 1) is equivalent to 1 <<
1755 * ((vertex_count - 1) % 32).
1757 abld
.OR(this->control_data_bits
, this->control_data_bits
, mask
);
1761 fs_visitor::emit_gs_control_data_bits(const fs_reg
&vertex_count
)
1763 assert(stage
== MESA_SHADER_GEOMETRY
);
1764 assert(gs_compile
->control_data_bits_per_vertex
!= 0);
1766 struct brw_gs_prog_data
*gs_prog_data
= brw_gs_prog_data(prog_data
);
1768 const fs_builder abld
= bld
.annotate("emit control data bits");
1769 const fs_builder fwa_bld
= bld
.exec_all();
1771 /* We use a single UD register to accumulate control data bits (32 bits
1772 * for each of the SIMD8 channels). So we need to write a DWord (32 bits)
1775 * Unfortunately, the URB_WRITE_SIMD8 message uses 128-bit (OWord) offsets.
1776 * We have select a 128-bit group via the Global and Per-Slot Offsets, then
1777 * use the Channel Mask phase to enable/disable which DWord within that
1778 * group to write. (Remember, different SIMD8 channels may have emitted
1779 * different numbers of vertices, so we may need per-slot offsets.)
1781 * Channel masking presents an annoying problem: we may have to replicate
1782 * the data up to 4 times:
1784 * Msg = Handles, Per-Slot Offsets, Channel Masks, Data, Data, Data, Data.
1786 * To avoid penalizing shaders that emit a small number of vertices, we
1787 * can avoid these sometimes: if the size of the control data header is
1788 * <= 128 bits, then there is only 1 OWord. All SIMD8 channels will land
1789 * land in the same 128-bit group, so we can skip per-slot offsets.
1791 * Similarly, if the control data header is <= 32 bits, there is only one
1792 * DWord, so we can skip channel masks.
1794 enum opcode opcode
= SHADER_OPCODE_URB_WRITE_SIMD8
;
1796 fs_reg channel_mask
, per_slot_offset
;
1798 if (gs_compile
->control_data_header_size_bits
> 32) {
1799 opcode
= SHADER_OPCODE_URB_WRITE_SIMD8_MASKED
;
1800 channel_mask
= vgrf(glsl_type::uint_type
);
1803 if (gs_compile
->control_data_header_size_bits
> 128) {
1804 opcode
= SHADER_OPCODE_URB_WRITE_SIMD8_MASKED_PER_SLOT
;
1805 per_slot_offset
= vgrf(glsl_type::uint_type
);
1808 /* Figure out which DWord we're trying to write to using the formula:
1810 * dword_index = (vertex_count - 1) * bits_per_vertex / 32
1812 * Since bits_per_vertex is a power of two, and is known at compile
1813 * time, this can be optimized to:
1815 * dword_index = (vertex_count - 1) >> (6 - log2(bits_per_vertex))
1817 if (opcode
!= SHADER_OPCODE_URB_WRITE_SIMD8
) {
1818 fs_reg dword_index
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
1819 fs_reg prev_count
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
1820 abld
.ADD(prev_count
, vertex_count
, brw_imm_ud(0xffffffffu
));
1821 unsigned log2_bits_per_vertex
=
1822 util_last_bit(gs_compile
->control_data_bits_per_vertex
);
1823 abld
.SHR(dword_index
, prev_count
, brw_imm_ud(6u - log2_bits_per_vertex
));
1825 if (per_slot_offset
.file
!= BAD_FILE
) {
1826 /* Set the per-slot offset to dword_index / 4, so that we'll write to
1827 * the appropriate OWord within the control data header.
1829 abld
.SHR(per_slot_offset
, dword_index
, brw_imm_ud(2u));
1832 /* Set the channel masks to 1 << (dword_index % 4), so that we'll
1833 * write to the appropriate DWORD within the OWORD.
1835 fs_reg channel
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
1836 fwa_bld
.AND(channel
, dword_index
, brw_imm_ud(3u));
1837 channel_mask
= intexp2(fwa_bld
, channel
);
1838 /* Then the channel masks need to be in bits 23:16. */
1839 fwa_bld
.SHL(channel_mask
, channel_mask
, brw_imm_ud(16u));
1842 /* Store the control data bits in the message payload and send it. */
1844 if (channel_mask
.file
!= BAD_FILE
)
1845 mlen
+= 4; /* channel masks, plus 3 extra copies of the data */
1846 if (per_slot_offset
.file
!= BAD_FILE
)
1849 fs_reg payload
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, mlen
);
1850 fs_reg
*sources
= ralloc_array(mem_ctx
, fs_reg
, mlen
);
1852 sources
[i
++] = fs_reg(retype(brw_vec8_grf(1, 0), BRW_REGISTER_TYPE_UD
));
1853 if (per_slot_offset
.file
!= BAD_FILE
)
1854 sources
[i
++] = per_slot_offset
;
1855 if (channel_mask
.file
!= BAD_FILE
)
1856 sources
[i
++] = channel_mask
;
1858 sources
[i
++] = this->control_data_bits
;
1861 abld
.LOAD_PAYLOAD(payload
, sources
, mlen
, mlen
);
1862 fs_inst
*inst
= abld
.emit(opcode
, reg_undef
, payload
);
1864 /* We need to increment Global Offset by 256-bits to make room for
1865 * Broadwell's extra "Vertex Count" payload at the beginning of the
1866 * URB entry. Since this is an OWord message, Global Offset is counted
1867 * in 128-bit units, so we must set it to 2.
1869 if (gs_prog_data
->static_vertex_count
== -1)
1874 fs_visitor::set_gs_stream_control_data_bits(const fs_reg
&vertex_count
,
1877 /* control_data_bits |= stream_id << ((2 * (vertex_count - 1)) % 32) */
1879 /* Note: we are calling this *before* increasing vertex_count, so
1880 * this->vertex_count == vertex_count - 1 in the formula above.
1883 /* Stream mode uses 2 bits per vertex */
1884 assert(gs_compile
->control_data_bits_per_vertex
== 2);
1886 /* Must be a valid stream */
1887 assert(stream_id
< MAX_VERTEX_STREAMS
);
1889 /* Control data bits are initialized to 0 so we don't have to set any
1890 * bits when sending vertices to stream 0.
1895 const fs_builder abld
= bld
.annotate("set stream control data bits", NULL
);
1897 /* reg::sid = stream_id */
1898 fs_reg sid
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
1899 abld
.MOV(sid
, brw_imm_ud(stream_id
));
1901 /* reg:shift_count = 2 * (vertex_count - 1) */
1902 fs_reg shift_count
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
1903 abld
.SHL(shift_count
, vertex_count
, brw_imm_ud(1u));
1905 /* Note: we're relying on the fact that the GEN SHL instruction only pays
1906 * attention to the lower 5 bits of its second source argument, so on this
1907 * architecture, stream_id << 2 * (vertex_count - 1) is equivalent to
1908 * stream_id << ((2 * (vertex_count - 1)) % 32).
1910 fs_reg mask
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
1911 abld
.SHL(mask
, sid
, shift_count
);
1912 abld
.OR(this->control_data_bits
, this->control_data_bits
, mask
);
1916 fs_visitor::emit_gs_vertex(const nir_src
&vertex_count_nir_src
,
1919 assert(stage
== MESA_SHADER_GEOMETRY
);
1921 struct brw_gs_prog_data
*gs_prog_data
= brw_gs_prog_data(prog_data
);
1923 fs_reg vertex_count
= get_nir_src(vertex_count_nir_src
);
1924 vertex_count
.type
= BRW_REGISTER_TYPE_UD
;
1926 /* Haswell and later hardware ignores the "Render Stream Select" bits
1927 * from the 3DSTATE_STREAMOUT packet when the SOL stage is disabled,
1928 * and instead sends all primitives down the pipeline for rasterization.
1929 * If the SOL stage is enabled, "Render Stream Select" is honored and
1930 * primitives bound to non-zero streams are discarded after stream output.
1932 * Since the only purpose of primives sent to non-zero streams is to
1933 * be recorded by transform feedback, we can simply discard all geometry
1934 * bound to these streams when transform feedback is disabled.
1936 if (stream_id
> 0 && !nir
->info
.has_transform_feedback_varyings
)
1939 /* If we're outputting 32 control data bits or less, then we can wait
1940 * until the shader is over to output them all. Otherwise we need to
1941 * output them as we go. Now is the time to do it, since we're about to
1942 * output the vertex_count'th vertex, so it's guaranteed that the
1943 * control data bits associated with the (vertex_count - 1)th vertex are
1946 if (gs_compile
->control_data_header_size_bits
> 32) {
1947 const fs_builder abld
=
1948 bld
.annotate("emit vertex: emit control data bits");
1950 /* Only emit control data bits if we've finished accumulating a batch
1951 * of 32 bits. This is the case when:
1953 * (vertex_count * bits_per_vertex) % 32 == 0
1955 * (in other words, when the last 5 bits of vertex_count *
1956 * bits_per_vertex are 0). Assuming bits_per_vertex == 2^n for some
1957 * integer n (which is always the case, since bits_per_vertex is
1958 * always 1 or 2), this is equivalent to requiring that the last 5-n
1959 * bits of vertex_count are 0:
1961 * vertex_count & (2^(5-n) - 1) == 0
1963 * 2^(5-n) == 2^5 / 2^n == 32 / bits_per_vertex, so this is
1966 * vertex_count & (32 / bits_per_vertex - 1) == 0
1968 * TODO: If vertex_count is an immediate, we could do some of this math
1969 * at compile time...
1972 abld
.AND(bld
.null_reg_d(), vertex_count
,
1973 brw_imm_ud(32u / gs_compile
->control_data_bits_per_vertex
- 1u));
1974 inst
->conditional_mod
= BRW_CONDITIONAL_Z
;
1976 abld
.IF(BRW_PREDICATE_NORMAL
);
1977 /* If vertex_count is 0, then no control data bits have been
1978 * accumulated yet, so we can skip emitting them.
1980 abld
.CMP(bld
.null_reg_d(), vertex_count
, brw_imm_ud(0u),
1981 BRW_CONDITIONAL_NEQ
);
1982 abld
.IF(BRW_PREDICATE_NORMAL
);
1983 emit_gs_control_data_bits(vertex_count
);
1984 abld
.emit(BRW_OPCODE_ENDIF
);
1986 /* Reset control_data_bits to 0 so we can start accumulating a new
1989 * Note: in the case where vertex_count == 0, this neutralizes the
1990 * effect of any call to EndPrimitive() that the shader may have
1991 * made before outputting its first vertex.
1993 inst
= abld
.MOV(this->control_data_bits
, brw_imm_ud(0u));
1994 inst
->force_writemask_all
= true;
1995 abld
.emit(BRW_OPCODE_ENDIF
);
1998 emit_urb_writes(vertex_count
);
2000 /* In stream mode we have to set control data bits for all vertices
2001 * unless we have disabled control data bits completely (which we do
2002 * do for GL_POINTS outputs that don't use streams).
2004 if (gs_compile
->control_data_header_size_bits
> 0 &&
2005 gs_prog_data
->control_data_format
==
2006 GEN7_GS_CONTROL_DATA_FORMAT_GSCTL_SID
) {
2007 set_gs_stream_control_data_bits(vertex_count
, stream_id
);
2012 fs_visitor::emit_gs_input_load(const fs_reg
&dst
,
2013 const nir_src
&vertex_src
,
2014 unsigned base_offset
,
2015 const nir_src
&offset_src
,
2016 unsigned num_components
,
2017 unsigned first_component
)
2019 struct brw_gs_prog_data
*gs_prog_data
= brw_gs_prog_data(prog_data
);
2021 nir_const_value
*vertex_const
= nir_src_as_const_value(vertex_src
);
2022 nir_const_value
*offset_const
= nir_src_as_const_value(offset_src
);
2023 const unsigned push_reg_count
= gs_prog_data
->base
.urb_read_length
* 8;
2025 /* TODO: figure out push input layout for invocations == 1 */
2026 /* TODO: make this work with 64-bit inputs */
2027 if (gs_prog_data
->invocations
== 1 &&
2028 type_sz(dst
.type
) <= 4 &&
2029 offset_const
!= NULL
&& vertex_const
!= NULL
&&
2030 4 * (base_offset
+ offset_const
->u32
[0]) < push_reg_count
) {
2031 int imm_offset
= (base_offset
+ offset_const
->u32
[0]) * 4 +
2032 vertex_const
->u32
[0] * push_reg_count
;
2033 for (unsigned i
= 0; i
< num_components
; i
++) {
2034 bld
.MOV(offset(dst
, bld
, i
),
2035 fs_reg(ATTR
, imm_offset
+ i
+ first_component
, dst
.type
));
2040 /* Resort to the pull model. Ensure the VUE handles are provided. */
2041 assert(gs_prog_data
->base
.include_vue_handles
);
2043 unsigned first_icp_handle
= gs_prog_data
->include_primitive_id
? 3 : 2;
2044 fs_reg icp_handle
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2046 if (gs_prog_data
->invocations
== 1) {
2048 /* The vertex index is constant; just select the proper URB handle. */
2050 retype(brw_vec8_grf(first_icp_handle
+ vertex_const
->i32
[0], 0),
2051 BRW_REGISTER_TYPE_UD
);
2053 /* The vertex index is non-constant. We need to use indirect
2054 * addressing to fetch the proper URB handle.
2056 * First, we start with the sequence <7, 6, 5, 4, 3, 2, 1, 0>
2057 * indicating that channel <n> should read the handle from
2058 * DWord <n>. We convert that to bytes by multiplying by 4.
2060 * Next, we convert the vertex index to bytes by multiplying
2061 * by 32 (shifting by 5), and add the two together. This is
2062 * the final indirect byte offset.
2064 fs_reg sequence
= bld
.vgrf(BRW_REGISTER_TYPE_W
, 1);
2065 fs_reg channel_offsets
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2066 fs_reg vertex_offset_bytes
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2067 fs_reg icp_offset_bytes
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2069 /* sequence = <7, 6, 5, 4, 3, 2, 1, 0> */
2070 bld
.MOV(sequence
, fs_reg(brw_imm_v(0x76543210)));
2071 /* channel_offsets = 4 * sequence = <28, 24, 20, 16, 12, 8, 4, 0> */
2072 bld
.SHL(channel_offsets
, sequence
, brw_imm_ud(2u));
2073 /* Convert vertex_index to bytes (multiply by 32) */
2074 bld
.SHL(vertex_offset_bytes
,
2075 retype(get_nir_src(vertex_src
), BRW_REGISTER_TYPE_UD
),
2077 bld
.ADD(icp_offset_bytes
, vertex_offset_bytes
, channel_offsets
);
2079 /* Use first_icp_handle as the base offset. There is one register
2080 * of URB handles per vertex, so inform the register allocator that
2081 * we might read up to nir->info.gs.vertices_in registers.
2083 bld
.emit(SHADER_OPCODE_MOV_INDIRECT
, icp_handle
,
2084 retype(brw_vec8_grf(first_icp_handle
, 0), icp_handle
.type
),
2085 fs_reg(icp_offset_bytes
),
2086 brw_imm_ud(nir
->info
.gs
.vertices_in
* REG_SIZE
));
2089 assert(gs_prog_data
->invocations
> 1);
2092 assert(devinfo
->gen
>= 9 || vertex_const
->i32
[0] <= 5);
2094 retype(brw_vec1_grf(first_icp_handle
+
2095 vertex_const
->i32
[0] / 8,
2096 vertex_const
->i32
[0] % 8),
2097 BRW_REGISTER_TYPE_UD
));
2099 /* The vertex index is non-constant. We need to use indirect
2100 * addressing to fetch the proper URB handle.
2103 fs_reg icp_offset_bytes
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2105 /* Convert vertex_index to bytes (multiply by 4) */
2106 bld
.SHL(icp_offset_bytes
,
2107 retype(get_nir_src(vertex_src
), BRW_REGISTER_TYPE_UD
),
2110 /* Use first_icp_handle as the base offset. There is one DWord
2111 * of URB handles per vertex, so inform the register allocator that
2112 * we might read up to ceil(nir->info.gs.vertices_in / 8) registers.
2114 bld
.emit(SHADER_OPCODE_MOV_INDIRECT
, icp_handle
,
2115 retype(brw_vec8_grf(first_icp_handle
, 0), icp_handle
.type
),
2116 fs_reg(icp_offset_bytes
),
2117 brw_imm_ud(DIV_ROUND_UP(nir
->info
.gs
.vertices_in
, 8) *
2124 fs_reg tmp_dst
= dst
;
2125 fs_reg indirect_offset
= get_nir_src(offset_src
);
2126 unsigned num_iterations
= 1;
2127 unsigned orig_num_components
= num_components
;
2129 if (type_sz(dst
.type
) == 8) {
2130 if (num_components
> 2) {
2134 fs_reg tmp
= fs_reg(VGRF
, alloc
.allocate(4), dst
.type
);
2136 first_component
= first_component
/ 2;
2139 for (unsigned iter
= 0; iter
< num_iterations
; iter
++) {
2141 /* Constant indexing - use global offset. */
2142 if (first_component
!= 0) {
2143 unsigned read_components
= num_components
+ first_component
;
2144 fs_reg tmp
= bld
.vgrf(dst
.type
, read_components
);
2145 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8
, tmp
, icp_handle
);
2146 inst
->size_written
= read_components
*
2147 tmp
.component_size(inst
->exec_size
);
2148 for (unsigned i
= 0; i
< num_components
; i
++) {
2149 bld
.MOV(offset(tmp_dst
, bld
, i
),
2150 offset(tmp
, bld
, i
+ first_component
));
2153 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8
, tmp_dst
,
2155 inst
->size_written
= num_components
*
2156 tmp_dst
.component_size(inst
->exec_size
);
2158 inst
->offset
= base_offset
+ offset_const
->u32
[0];
2161 /* Indirect indexing - use per-slot offsets as well. */
2162 const fs_reg srcs
[] = { icp_handle
, indirect_offset
};
2163 unsigned read_components
= num_components
+ first_component
;
2164 fs_reg tmp
= bld
.vgrf(dst
.type
, read_components
);
2165 fs_reg payload
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 2);
2166 bld
.LOAD_PAYLOAD(payload
, srcs
, ARRAY_SIZE(srcs
), 0);
2167 if (first_component
!= 0) {
2168 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT
, tmp
,
2170 inst
->size_written
= read_components
*
2171 tmp
.component_size(inst
->exec_size
);
2172 for (unsigned i
= 0; i
< num_components
; i
++) {
2173 bld
.MOV(offset(tmp_dst
, bld
, i
),
2174 offset(tmp
, bld
, i
+ first_component
));
2177 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT
, tmp_dst
,
2179 inst
->size_written
= num_components
*
2180 tmp_dst
.component_size(inst
->exec_size
);
2182 inst
->offset
= base_offset
;
2186 if (type_sz(dst
.type
) == 8) {
2187 shuffle_32bit_load_result_to_64bit_data(
2188 bld
, tmp_dst
, retype(tmp_dst
, BRW_REGISTER_TYPE_F
), num_components
);
2190 for (unsigned c
= 0; c
< num_components
; c
++)
2191 bld
.MOV(offset(dst
, bld
, iter
* 2 + c
), offset(tmp_dst
, bld
, c
));
2194 if (num_iterations
> 1) {
2195 num_components
= orig_num_components
- 2;
2199 fs_reg new_indirect
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2200 bld
.ADD(new_indirect
, indirect_offset
, brw_imm_ud(1u));
2201 indirect_offset
= new_indirect
;
2208 fs_visitor::get_indirect_offset(nir_intrinsic_instr
*instr
)
2210 nir_src
*offset_src
= nir_get_io_offset_src(instr
);
2211 nir_const_value
*const_value
= nir_src_as_const_value(*offset_src
);
2214 /* The only constant offset we should find is 0. brw_nir.c's
2215 * add_const_offset_to_base() will fold other constant offsets
2216 * into instr->const_index[0].
2218 assert(const_value
->u32
[0] == 0);
2222 return get_nir_src(*offset_src
);
2226 do_untyped_vector_read(const fs_builder
&bld
,
2228 const fs_reg surf_index
,
2229 const fs_reg offset_reg
,
2230 unsigned num_components
)
2232 if (type_sz(dest
.type
) == 4) {
2233 fs_reg read_result
= emit_untyped_read(bld
, surf_index
, offset_reg
,
2236 BRW_PREDICATE_NONE
);
2237 read_result
.type
= dest
.type
;
2238 for (unsigned i
= 0; i
< num_components
; i
++)
2239 bld
.MOV(offset(dest
, bld
, i
), offset(read_result
, bld
, i
));
2240 } else if (type_sz(dest
.type
) == 8) {
2241 /* Reading a dvec, so we need to:
2243 * 1. Multiply num_components by 2, to account for the fact that we
2244 * need to read 64-bit components.
2245 * 2. Shuffle the result of the load to form valid 64-bit elements
2246 * 3. Emit a second load (for components z/w) if needed.
2248 fs_reg read_offset
= bld
.vgrf(BRW_REGISTER_TYPE_UD
);
2249 bld
.MOV(read_offset
, offset_reg
);
2251 int iters
= num_components
<= 2 ? 1 : 2;
2253 /* Load the dvec, the first iteration loads components x/y, the second
2254 * iteration, if needed, loads components z/w
2256 for (int it
= 0; it
< iters
; it
++) {
2257 /* Compute number of components to read in this iteration */
2258 int iter_components
= MIN2(2, num_components
);
2259 num_components
-= iter_components
;
2261 /* Read. Since this message reads 32-bit components, we need to
2262 * read twice as many components.
2264 fs_reg read_result
= emit_untyped_read(bld
, surf_index
, read_offset
,
2266 iter_components
* 2,
2267 BRW_PREDICATE_NONE
);
2269 /* Shuffle the 32-bit load result into valid 64-bit data */
2270 const fs_reg packed_result
= bld
.vgrf(dest
.type
, iter_components
);
2271 shuffle_32bit_load_result_to_64bit_data(
2272 bld
, packed_result
, read_result
, iter_components
);
2274 /* Move each component to its destination */
2275 read_result
= retype(read_result
, BRW_REGISTER_TYPE_DF
);
2276 for (int c
= 0; c
< iter_components
; c
++) {
2277 bld
.MOV(offset(dest
, bld
, it
* 2 + c
),
2278 offset(packed_result
, bld
, c
));
2281 bld
.ADD(read_offset
, read_offset
, brw_imm_ud(16));
2284 unreachable("Unsupported type");
2289 fs_visitor::nir_emit_vs_intrinsic(const fs_builder
&bld
,
2290 nir_intrinsic_instr
*instr
)
2292 assert(stage
== MESA_SHADER_VERTEX
);
2295 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
2296 dest
= get_nir_dest(instr
->dest
);
2298 switch (instr
->intrinsic
) {
2299 case nir_intrinsic_load_vertex_id
:
2300 unreachable("should be lowered by lower_vertex_id()");
2302 case nir_intrinsic_load_vertex_id_zero_base
:
2303 case nir_intrinsic_load_base_vertex
:
2304 case nir_intrinsic_load_instance_id
:
2305 case nir_intrinsic_load_base_instance
:
2306 case nir_intrinsic_load_draw_id
: {
2307 gl_system_value sv
= nir_system_value_from_intrinsic(instr
->intrinsic
);
2308 fs_reg val
= nir_system_values
[sv
];
2309 assert(val
.file
!= BAD_FILE
);
2310 dest
.type
= val
.type
;
2315 case nir_intrinsic_load_input
: {
2316 fs_reg src
= fs_reg(ATTR
, nir_intrinsic_base(instr
) * 4, dest
.type
);
2317 unsigned first_component
= nir_intrinsic_component(instr
);
2318 unsigned num_components
= instr
->num_components
;
2319 enum brw_reg_type type
= dest
.type
;
2321 nir_const_value
*const_offset
= nir_src_as_const_value(instr
->src
[0]);
2322 assert(const_offset
&& "Indirect input loads not allowed");
2323 src
= offset(src
, bld
, const_offset
->u32
[0]);
2325 for (unsigned j
= 0; j
< num_components
; j
++) {
2326 bld
.MOV(offset(dest
, bld
, j
), offset(src
, bld
, j
+ first_component
));
2329 if (type
== BRW_REGISTER_TYPE_DF
) {
2330 /* Once the double vector is read, set again its original register
2331 * type to continue with normal execution.
2333 src
= retype(src
, type
);
2334 dest
= retype(dest
, type
);
2337 if (type_sz(src
.type
) == 8) {
2338 shuffle_32bit_load_result_to_64bit_data(bld
,
2340 retype(dest
, BRW_REGISTER_TYPE_F
),
2341 instr
->num_components
);
2347 nir_emit_intrinsic(bld
, instr
);
2353 fs_visitor::nir_emit_tcs_intrinsic(const fs_builder
&bld
,
2354 nir_intrinsic_instr
*instr
)
2356 assert(stage
== MESA_SHADER_TESS_CTRL
);
2357 struct brw_tcs_prog_key
*tcs_key
= (struct brw_tcs_prog_key
*) key
;
2358 struct brw_tcs_prog_data
*tcs_prog_data
= brw_tcs_prog_data(prog_data
);
2361 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
2362 dst
= get_nir_dest(instr
->dest
);
2364 switch (instr
->intrinsic
) {
2365 case nir_intrinsic_load_primitive_id
:
2366 bld
.MOV(dst
, fs_reg(brw_vec1_grf(0, 1)));
2368 case nir_intrinsic_load_invocation_id
:
2369 bld
.MOV(retype(dst
, invocation_id
.type
), invocation_id
);
2371 case nir_intrinsic_load_patch_vertices_in
:
2372 bld
.MOV(retype(dst
, BRW_REGISTER_TYPE_D
),
2373 brw_imm_d(tcs_key
->input_vertices
));
2376 case nir_intrinsic_barrier
: {
2377 if (tcs_prog_data
->instances
== 1)
2380 fs_reg m0
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2381 fs_reg m0_2
= component(m0
, 2);
2383 const fs_builder chanbld
= bld
.exec_all().group(1, 0);
2385 /* Zero the message header */
2386 bld
.exec_all().MOV(m0
, brw_imm_ud(0u));
2388 /* Copy "Barrier ID" from r0.2, bits 16:13 */
2389 chanbld
.AND(m0_2
, retype(brw_vec1_grf(0, 2), BRW_REGISTER_TYPE_UD
),
2390 brw_imm_ud(INTEL_MASK(16, 13)));
2392 /* Shift it up to bits 27:24. */
2393 chanbld
.SHL(m0_2
, m0_2
, brw_imm_ud(11));
2395 /* Set the Barrier Count and the enable bit */
2396 chanbld
.OR(m0_2
, m0_2
,
2397 brw_imm_ud(tcs_prog_data
->instances
<< 9 | (1 << 15)));
2399 bld
.emit(SHADER_OPCODE_BARRIER
, bld
.null_reg_ud(), m0
);
2403 case nir_intrinsic_load_input
:
2404 unreachable("nir_lower_io should never give us these.");
2407 case nir_intrinsic_load_per_vertex_input
: {
2408 fs_reg indirect_offset
= get_indirect_offset(instr
);
2409 unsigned imm_offset
= instr
->const_index
[0];
2411 const nir_src
&vertex_src
= instr
->src
[0];
2412 nir_const_value
*vertex_const
= nir_src_as_const_value(vertex_src
);
2419 /* Emit a MOV to resolve <0,1,0> regioning. */
2420 icp_handle
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2422 retype(brw_vec1_grf(1 + (vertex_const
->i32
[0] >> 3),
2423 vertex_const
->i32
[0] & 7),
2424 BRW_REGISTER_TYPE_UD
));
2425 } else if (tcs_prog_data
->instances
== 1 &&
2426 vertex_src
.is_ssa
&&
2427 vertex_src
.ssa
->parent_instr
->type
== nir_instr_type_intrinsic
&&
2428 nir_instr_as_intrinsic(vertex_src
.ssa
->parent_instr
)->intrinsic
== nir_intrinsic_load_invocation_id
) {
2429 /* For the common case of only 1 instance, an array index of
2430 * gl_InvocationID means reading g1. Skip all the indirect work.
2432 icp_handle
= retype(brw_vec8_grf(1, 0), BRW_REGISTER_TYPE_UD
);
2434 /* The vertex index is non-constant. We need to use indirect
2435 * addressing to fetch the proper URB handle.
2437 icp_handle
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2439 /* Each ICP handle is a single DWord (4 bytes) */
2440 fs_reg vertex_offset_bytes
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2441 bld
.SHL(vertex_offset_bytes
,
2442 retype(get_nir_src(vertex_src
), BRW_REGISTER_TYPE_UD
),
2445 /* Start at g1. We might read up to 4 registers. */
2446 bld
.emit(SHADER_OPCODE_MOV_INDIRECT
, icp_handle
,
2447 retype(brw_vec8_grf(1, 0), icp_handle
.type
), vertex_offset_bytes
,
2448 brw_imm_ud(4 * REG_SIZE
));
2451 /* We can only read two double components with each URB read, so
2452 * we send two read messages in that case, each one loading up to
2453 * two double components.
2455 unsigned num_iterations
= 1;
2456 unsigned num_components
= instr
->num_components
;
2457 unsigned first_component
= nir_intrinsic_component(instr
);
2458 fs_reg orig_dst
= dst
;
2459 if (type_sz(dst
.type
) == 8) {
2460 first_component
= first_component
/ 2;
2461 if (instr
->num_components
> 2) {
2466 fs_reg tmp
= fs_reg(VGRF
, alloc
.allocate(4), dst
.type
);
2470 for (unsigned iter
= 0; iter
< num_iterations
; iter
++) {
2471 if (indirect_offset
.file
== BAD_FILE
) {
2472 /* Constant indexing - use global offset. */
2473 if (first_component
!= 0) {
2474 unsigned read_components
= num_components
+ first_component
;
2475 fs_reg tmp
= bld
.vgrf(dst
.type
, read_components
);
2476 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8
, tmp
, icp_handle
);
2477 for (unsigned i
= 0; i
< num_components
; i
++) {
2478 bld
.MOV(offset(dst
, bld
, i
),
2479 offset(tmp
, bld
, i
+ first_component
));
2482 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8
, dst
, icp_handle
);
2484 inst
->offset
= imm_offset
;
2487 /* Indirect indexing - use per-slot offsets as well. */
2488 const fs_reg srcs
[] = { icp_handle
, indirect_offset
};
2489 fs_reg payload
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 2);
2490 bld
.LOAD_PAYLOAD(payload
, srcs
, ARRAY_SIZE(srcs
), 0);
2491 if (first_component
!= 0) {
2492 unsigned read_components
= num_components
+ first_component
;
2493 fs_reg tmp
= bld
.vgrf(dst
.type
, read_components
);
2494 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT
, tmp
,
2496 for (unsigned i
= 0; i
< num_components
; i
++) {
2497 bld
.MOV(offset(dst
, bld
, i
),
2498 offset(tmp
, bld
, i
+ first_component
));
2501 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT
, dst
,
2504 inst
->offset
= imm_offset
;
2507 inst
->size_written
= (num_components
+ first_component
) *
2508 inst
->dst
.component_size(inst
->exec_size
);
2510 /* If we are reading 64-bit data using 32-bit read messages we need
2511 * build proper 64-bit data elements by shuffling the low and high
2512 * 32-bit components around like we do for other things like UBOs
2515 if (type_sz(dst
.type
) == 8) {
2516 shuffle_32bit_load_result_to_64bit_data(
2517 bld
, dst
, retype(dst
, BRW_REGISTER_TYPE_F
), num_components
);
2519 for (unsigned c
= 0; c
< num_components
; c
++) {
2520 bld
.MOV(offset(orig_dst
, bld
, iter
* 2 + c
),
2521 offset(dst
, bld
, c
));
2525 /* Copy the temporary to the destination to deal with writemasking.
2527 * Also attempt to deal with gl_PointSize being in the .w component.
2529 if (inst
->offset
== 0 && indirect_offset
.file
== BAD_FILE
) {
2530 assert(type_sz(dst
.type
) < 8);
2531 inst
->dst
= bld
.vgrf(dst
.type
, 4);
2532 inst
->size_written
= 4 * REG_SIZE
;
2533 bld
.MOV(dst
, offset(inst
->dst
, bld
, 3));
2536 /* If we are loading double data and we need a second read message
2537 * adjust the write offset
2539 if (num_iterations
> 1) {
2540 num_components
= instr
->num_components
- 2;
2547 case nir_intrinsic_load_output
:
2548 case nir_intrinsic_load_per_vertex_output
: {
2549 fs_reg indirect_offset
= get_indirect_offset(instr
);
2550 unsigned imm_offset
= instr
->const_index
[0];
2551 unsigned first_component
= nir_intrinsic_component(instr
);
2554 if (indirect_offset
.file
== BAD_FILE
) {
2555 /* Replicate the patch handle to all enabled channels */
2556 fs_reg patch_handle
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2557 bld
.MOV(patch_handle
,
2558 retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_UD
));
2561 if (first_component
!= 0) {
2562 unsigned read_components
=
2563 instr
->num_components
+ first_component
;
2564 fs_reg tmp
= bld
.vgrf(dst
.type
, read_components
);
2565 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8
, tmp
,
2567 inst
->size_written
= read_components
* REG_SIZE
;
2568 for (unsigned i
= 0; i
< instr
->num_components
; i
++) {
2569 bld
.MOV(offset(dst
, bld
, i
),
2570 offset(tmp
, bld
, i
+ first_component
));
2573 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8
, dst
,
2575 inst
->size_written
= instr
->num_components
* REG_SIZE
;
2577 inst
->offset
= imm_offset
;
2581 /* Indirect indexing - use per-slot offsets as well. */
2582 const fs_reg srcs
[] = {
2583 retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_UD
),
2586 fs_reg payload
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 2);
2587 bld
.LOAD_PAYLOAD(payload
, srcs
, ARRAY_SIZE(srcs
), 0);
2588 if (first_component
!= 0) {
2589 unsigned read_components
=
2590 instr
->num_components
+ first_component
;
2591 fs_reg tmp
= bld
.vgrf(dst
.type
, read_components
);
2592 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT
, tmp
,
2594 inst
->size_written
= read_components
* REG_SIZE
;
2595 for (unsigned i
= 0; i
< instr
->num_components
; i
++) {
2596 bld
.MOV(offset(dst
, bld
, i
),
2597 offset(tmp
, bld
, i
+ first_component
));
2600 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT
, dst
,
2602 inst
->size_written
= instr
->num_components
* REG_SIZE
;
2604 inst
->offset
= imm_offset
;
2610 case nir_intrinsic_store_output
:
2611 case nir_intrinsic_store_per_vertex_output
: {
2612 fs_reg value
= get_nir_src(instr
->src
[0]);
2613 bool is_64bit
= (instr
->src
[0].is_ssa
?
2614 instr
->src
[0].ssa
->bit_size
: instr
->src
[0].reg
.reg
->bit_size
) == 64;
2615 fs_reg indirect_offset
= get_indirect_offset(instr
);
2616 unsigned imm_offset
= instr
->const_index
[0];
2617 unsigned mask
= instr
->const_index
[1];
2618 unsigned header_regs
= 0;
2620 srcs
[header_regs
++] = retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_UD
);
2622 if (indirect_offset
.file
!= BAD_FILE
) {
2623 srcs
[header_regs
++] = indirect_offset
;
2629 unsigned num_components
= util_last_bit(mask
);
2632 /* We can only pack two 64-bit components in a single message, so send
2633 * 2 messages if we have more components
2635 unsigned num_iterations
= 1;
2636 unsigned iter_components
= num_components
;
2637 unsigned first_component
= nir_intrinsic_component(instr
);
2639 first_component
= first_component
/ 2;
2640 if (instr
->num_components
> 2) {
2642 iter_components
= 2;
2646 mask
= mask
<< first_component
;
2648 for (unsigned iter
= 0; iter
< num_iterations
; iter
++) {
2649 if (!is_64bit
&& mask
!= WRITEMASK_XYZW
) {
2650 srcs
[header_regs
++] = brw_imm_ud(mask
<< 16);
2651 opcode
= indirect_offset
.file
!= BAD_FILE
?
2652 SHADER_OPCODE_URB_WRITE_SIMD8_MASKED_PER_SLOT
:
2653 SHADER_OPCODE_URB_WRITE_SIMD8_MASKED
;
2654 } else if (is_64bit
&& ((mask
& WRITEMASK_XY
) != WRITEMASK_XY
)) {
2655 /* Expand the 64-bit mask to 32-bit channels. We only handle
2656 * two channels in each iteration, so we only care about X/Y.
2658 unsigned mask32
= 0;
2659 if (mask
& WRITEMASK_X
)
2660 mask32
|= WRITEMASK_XY
;
2661 if (mask
& WRITEMASK_Y
)
2662 mask32
|= WRITEMASK_ZW
;
2664 /* If the mask does not include any of the channels X or Y there
2665 * is nothing to do in this iteration. Move on to the next couple
2666 * of 64-bit channels.
2674 srcs
[header_regs
++] = brw_imm_ud(mask32
<< 16);
2675 opcode
= indirect_offset
.file
!= BAD_FILE
?
2676 SHADER_OPCODE_URB_WRITE_SIMD8_MASKED_PER_SLOT
:
2677 SHADER_OPCODE_URB_WRITE_SIMD8_MASKED
;
2679 opcode
= indirect_offset
.file
!= BAD_FILE
?
2680 SHADER_OPCODE_URB_WRITE_SIMD8_PER_SLOT
:
2681 SHADER_OPCODE_URB_WRITE_SIMD8
;
2684 for (unsigned i
= 0; i
< iter_components
; i
++) {
2685 if (!(mask
& (1 << (i
+ first_component
))))
2689 srcs
[header_regs
+ i
+ first_component
] = offset(value
, bld
, i
);
2691 /* We need to shuffle the 64-bit data to match the layout
2692 * expected by our 32-bit URB write messages. We use a temporary
2695 unsigned channel
= iter
* 2 + i
;
2696 fs_reg dest
= shuffle_64bit_data_for_32bit_write(bld
,
2697 offset(value
, bld
, channel
), 1);
2699 srcs
[header_regs
+ (i
+ first_component
) * 2] = dest
;
2700 srcs
[header_regs
+ (i
+ first_component
) * 2 + 1] =
2701 offset(dest
, bld
, 1);
2706 header_regs
+ (is_64bit
? 2 * iter_components
: iter_components
) +
2707 (is_64bit
? 2 * first_component
: first_component
);
2709 bld
.vgrf(BRW_REGISTER_TYPE_UD
, mlen
);
2710 bld
.LOAD_PAYLOAD(payload
, srcs
, mlen
, header_regs
);
2712 fs_inst
*inst
= bld
.emit(opcode
, bld
.null_reg_ud(), payload
);
2713 inst
->offset
= imm_offset
;
2716 /* If this is a 64-bit attribute, select the next two 64-bit channels
2717 * to be handled in the next iteration.
2728 nir_emit_intrinsic(bld
, instr
);
2734 fs_visitor::nir_emit_tes_intrinsic(const fs_builder
&bld
,
2735 nir_intrinsic_instr
*instr
)
2737 assert(stage
== MESA_SHADER_TESS_EVAL
);
2738 struct brw_tes_prog_data
*tes_prog_data
= brw_tes_prog_data(prog_data
);
2741 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
2742 dest
= get_nir_dest(instr
->dest
);
2744 switch (instr
->intrinsic
) {
2745 case nir_intrinsic_load_primitive_id
:
2746 bld
.MOV(dest
, fs_reg(brw_vec1_grf(0, 1)));
2748 case nir_intrinsic_load_tess_coord
:
2749 /* gl_TessCoord is part of the payload in g1-3 */
2750 for (unsigned i
= 0; i
< 3; i
++) {
2751 bld
.MOV(offset(dest
, bld
, i
), fs_reg(brw_vec8_grf(1 + i
, 0)));
2755 case nir_intrinsic_load_input
:
2756 case nir_intrinsic_load_per_vertex_input
: {
2757 fs_reg indirect_offset
= get_indirect_offset(instr
);
2758 unsigned imm_offset
= instr
->const_index
[0];
2759 unsigned first_component
= nir_intrinsic_component(instr
);
2761 if (type_sz(dest
.type
) == 8) {
2762 first_component
= first_component
/ 2;
2766 if (indirect_offset
.file
== BAD_FILE
) {
2767 /* Arbitrarily only push up to 32 vec4 slots worth of data,
2768 * which is 16 registers (since each holds 2 vec4 slots).
2770 unsigned slot_count
= 1;
2771 if (type_sz(dest
.type
) == 8 && instr
->num_components
> 2)
2774 const unsigned max_push_slots
= 32;
2775 if (imm_offset
+ slot_count
<= max_push_slots
) {
2776 fs_reg src
= fs_reg(ATTR
, imm_offset
/ 2, dest
.type
);
2777 for (int i
= 0; i
< instr
->num_components
; i
++) {
2778 unsigned comp
= 16 / type_sz(dest
.type
) * (imm_offset
% 2) +
2779 i
+ first_component
;
2780 bld
.MOV(offset(dest
, bld
, i
), component(src
, comp
));
2783 tes_prog_data
->base
.urb_read_length
=
2784 MAX2(tes_prog_data
->base
.urb_read_length
,
2785 DIV_ROUND_UP(imm_offset
+ slot_count
, 2));
2787 /* Replicate the patch handle to all enabled channels */
2788 const fs_reg srcs
[] = {
2789 retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_UD
)
2791 fs_reg patch_handle
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2792 bld
.LOAD_PAYLOAD(patch_handle
, srcs
, ARRAY_SIZE(srcs
), 0);
2794 if (first_component
!= 0) {
2795 unsigned read_components
=
2796 instr
->num_components
+ first_component
;
2797 fs_reg tmp
= bld
.vgrf(dest
.type
, read_components
);
2798 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8
, tmp
,
2800 inst
->size_written
= read_components
* REG_SIZE
;
2801 for (unsigned i
= 0; i
< instr
->num_components
; i
++) {
2802 bld
.MOV(offset(dest
, bld
, i
),
2803 offset(tmp
, bld
, i
+ first_component
));
2806 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8
, dest
,
2808 inst
->size_written
= instr
->num_components
* REG_SIZE
;
2811 inst
->offset
= imm_offset
;
2814 /* Indirect indexing - use per-slot offsets as well. */
2816 /* We can only read two double components with each URB read, so
2817 * we send two read messages in that case, each one loading up to
2818 * two double components.
2820 unsigned num_iterations
= 1;
2821 unsigned num_components
= instr
->num_components
;
2822 fs_reg orig_dest
= dest
;
2823 if (type_sz(dest
.type
) == 8) {
2824 if (instr
->num_components
> 2) {
2828 fs_reg tmp
= fs_reg(VGRF
, alloc
.allocate(4), dest
.type
);
2832 for (unsigned iter
= 0; iter
< num_iterations
; iter
++) {
2833 const fs_reg srcs
[] = {
2834 retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_UD
),
2837 fs_reg payload
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 2);
2838 bld
.LOAD_PAYLOAD(payload
, srcs
, ARRAY_SIZE(srcs
), 0);
2840 if (first_component
!= 0) {
2841 unsigned read_components
=
2842 num_components
+ first_component
;
2843 fs_reg tmp
= bld
.vgrf(dest
.type
, read_components
);
2844 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT
, tmp
,
2846 for (unsigned i
= 0; i
< num_components
; i
++) {
2847 bld
.MOV(offset(dest
, bld
, i
),
2848 offset(tmp
, bld
, i
+ first_component
));
2851 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT
, dest
,
2855 inst
->offset
= imm_offset
;
2856 inst
->size_written
= (num_components
+ first_component
) *
2857 inst
->dst
.component_size(inst
->exec_size
);
2859 /* If we are reading 64-bit data using 32-bit read messages we need
2860 * build proper 64-bit data elements by shuffling the low and high
2861 * 32-bit components around like we do for other things like UBOs
2864 if (type_sz(dest
.type
) == 8) {
2865 shuffle_32bit_load_result_to_64bit_data(
2866 bld
, dest
, retype(dest
, BRW_REGISTER_TYPE_F
), num_components
);
2868 for (unsigned c
= 0; c
< num_components
; c
++) {
2869 bld
.MOV(offset(orig_dest
, bld
, iter
* 2 + c
),
2870 offset(dest
, bld
, c
));
2874 /* If we are loading double data and we need a second read message
2877 if (num_iterations
> 1) {
2878 num_components
= instr
->num_components
- 2;
2886 nir_emit_intrinsic(bld
, instr
);
2892 fs_visitor::nir_emit_gs_intrinsic(const fs_builder
&bld
,
2893 nir_intrinsic_instr
*instr
)
2895 assert(stage
== MESA_SHADER_GEOMETRY
);
2896 fs_reg indirect_offset
;
2899 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
2900 dest
= get_nir_dest(instr
->dest
);
2902 switch (instr
->intrinsic
) {
2903 case nir_intrinsic_load_primitive_id
:
2904 assert(stage
== MESA_SHADER_GEOMETRY
);
2905 assert(brw_gs_prog_data(prog_data
)->include_primitive_id
);
2906 bld
.MOV(retype(dest
, BRW_REGISTER_TYPE_UD
),
2907 retype(fs_reg(brw_vec8_grf(2, 0)), BRW_REGISTER_TYPE_UD
));
2910 case nir_intrinsic_load_input
:
2911 unreachable("load_input intrinsics are invalid for the GS stage");
2913 case nir_intrinsic_load_per_vertex_input
:
2914 emit_gs_input_load(dest
, instr
->src
[0], instr
->const_index
[0],
2915 instr
->src
[1], instr
->num_components
,
2916 nir_intrinsic_component(instr
));
2919 case nir_intrinsic_emit_vertex_with_counter
:
2920 emit_gs_vertex(instr
->src
[0], instr
->const_index
[0]);
2923 case nir_intrinsic_end_primitive_with_counter
:
2924 emit_gs_end_primitive(instr
->src
[0]);
2927 case nir_intrinsic_set_vertex_count
:
2928 bld
.MOV(this->final_gs_vertex_count
, get_nir_src(instr
->src
[0]));
2931 case nir_intrinsic_load_invocation_id
: {
2932 fs_reg val
= nir_system_values
[SYSTEM_VALUE_INVOCATION_ID
];
2933 assert(val
.file
!= BAD_FILE
);
2934 dest
.type
= val
.type
;
2940 nir_emit_intrinsic(bld
, instr
);
2946 * Fetch the current render target layer index.
2949 fetch_render_target_array_index(const fs_builder
&bld
)
2951 if (bld
.shader
->devinfo
->gen
>= 6) {
2952 /* The render target array index is provided in the thread payload as
2953 * bits 26:16 of r0.0.
2955 const fs_reg idx
= bld
.vgrf(BRW_REGISTER_TYPE_UD
);
2956 bld
.AND(idx
, brw_uw1_reg(BRW_GENERAL_REGISTER_FILE
, 0, 1),
2960 /* Pre-SNB we only ever render into the first layer of the framebuffer
2961 * since layered rendering is not implemented.
2963 return brw_imm_ud(0);
2968 * Fake non-coherent framebuffer read implemented using TXF to fetch from the
2969 * framebuffer at the current fragment coordinates and sample index.
2972 fs_visitor::emit_non_coherent_fb_read(const fs_builder
&bld
, const fs_reg
&dst
,
2975 const struct gen_device_info
*devinfo
= bld
.shader
->devinfo
;
2977 assert(bld
.shader
->stage
== MESA_SHADER_FRAGMENT
);
2978 const brw_wm_prog_key
*wm_key
=
2979 reinterpret_cast<const brw_wm_prog_key
*>(key
);
2980 assert(!wm_key
->coherent_fb_fetch
);
2981 const struct brw_wm_prog_data
*wm_prog_data
=
2982 brw_wm_prog_data(stage_prog_data
);
2984 /* Calculate the surface index relative to the start of the texture binding
2985 * table block, since that's what the texturing messages expect.
2987 const unsigned surface
= target
+
2988 wm_prog_data
->binding_table
.render_target_read_start
-
2989 wm_prog_data
->base
.binding_table
.texture_start
;
2991 brw_mark_surface_used(
2992 bld
.shader
->stage_prog_data
,
2993 wm_prog_data
->binding_table
.render_target_read_start
+ target
);
2995 /* Calculate the fragment coordinates. */
2996 const fs_reg coords
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 3);
2997 bld
.MOV(offset(coords
, bld
, 0), pixel_x
);
2998 bld
.MOV(offset(coords
, bld
, 1), pixel_y
);
2999 bld
.MOV(offset(coords
, bld
, 2), fetch_render_target_array_index(bld
));
3001 /* Calculate the sample index and MCS payload when multisampling. Luckily
3002 * the MCS fetch message behaves deterministically for UMS surfaces, so it
3003 * shouldn't be necessary to recompile based on whether the framebuffer is
3006 if (wm_key
->multisample_fbo
&&
3007 nir_system_values
[SYSTEM_VALUE_SAMPLE_ID
].file
== BAD_FILE
)
3008 nir_system_values
[SYSTEM_VALUE_SAMPLE_ID
] = *emit_sampleid_setup();
3010 const fs_reg sample
= nir_system_values
[SYSTEM_VALUE_SAMPLE_ID
];
3011 const fs_reg mcs
= wm_key
->multisample_fbo
?
3012 emit_mcs_fetch(coords
, 3, brw_imm_ud(surface
)) : fs_reg();
3014 /* Use either a normal or a CMS texel fetch message depending on whether
3015 * the framebuffer is single or multisample. On SKL+ use the wide CMS
3016 * message just in case the framebuffer uses 16x multisampling, it should
3017 * be equivalent to the normal CMS fetch for lower multisampling modes.
3019 const opcode op
= !wm_key
->multisample_fbo
? SHADER_OPCODE_TXF_LOGICAL
:
3020 devinfo
->gen
>= 9 ? SHADER_OPCODE_TXF_CMS_W_LOGICAL
:
3021 SHADER_OPCODE_TXF_CMS_LOGICAL
;
3023 /* Emit the instruction. */
3024 const fs_reg srcs
[] = { coords
, fs_reg(), brw_imm_ud(0), fs_reg(),
3026 brw_imm_ud(surface
), brw_imm_ud(0),
3027 fs_reg(), brw_imm_ud(3), brw_imm_ud(0) };
3028 STATIC_ASSERT(ARRAY_SIZE(srcs
) == TEX_LOGICAL_NUM_SRCS
);
3030 fs_inst
*inst
= bld
.emit(op
, dst
, srcs
, ARRAY_SIZE(srcs
));
3031 inst
->size_written
= 4 * inst
->dst
.component_size(inst
->exec_size
);
3037 * Actual coherent framebuffer read implemented using the native render target
3038 * read message. Requires SKL+.
3041 emit_coherent_fb_read(const fs_builder
&bld
, const fs_reg
&dst
, unsigned target
)
3043 assert(bld
.shader
->devinfo
->gen
>= 9);
3044 fs_inst
*inst
= bld
.emit(FS_OPCODE_FB_READ_LOGICAL
, dst
);
3045 inst
->target
= target
;
3046 inst
->size_written
= 4 * inst
->dst
.component_size(inst
->exec_size
);
3052 alloc_temporary(const fs_builder
&bld
, unsigned size
, fs_reg
*regs
, unsigned n
)
3054 if (n
&& regs
[0].file
!= BAD_FILE
) {
3058 const fs_reg tmp
= bld
.vgrf(BRW_REGISTER_TYPE_F
, size
);
3060 for (unsigned i
= 0; i
< n
; i
++)
3068 alloc_frag_output(fs_visitor
*v
, unsigned location
)
3070 assert(v
->stage
== MESA_SHADER_FRAGMENT
);
3071 const brw_wm_prog_key
*const key
=
3072 reinterpret_cast<const brw_wm_prog_key
*>(v
->key
);
3073 const unsigned l
= GET_FIELD(location
, BRW_NIR_FRAG_OUTPUT_LOCATION
);
3074 const unsigned i
= GET_FIELD(location
, BRW_NIR_FRAG_OUTPUT_INDEX
);
3076 if (i
> 0 || (key
->force_dual_color_blend
&& l
== FRAG_RESULT_DATA1
))
3077 return alloc_temporary(v
->bld
, 4, &v
->dual_src_output
, 1);
3079 else if (l
== FRAG_RESULT_COLOR
)
3080 return alloc_temporary(v
->bld
, 4, v
->outputs
,
3081 MAX2(key
->nr_color_regions
, 1));
3083 else if (l
== FRAG_RESULT_DEPTH
)
3084 return alloc_temporary(v
->bld
, 1, &v
->frag_depth
, 1);
3086 else if (l
== FRAG_RESULT_STENCIL
)
3087 return alloc_temporary(v
->bld
, 1, &v
->frag_stencil
, 1);
3089 else if (l
== FRAG_RESULT_SAMPLE_MASK
)
3090 return alloc_temporary(v
->bld
, 1, &v
->sample_mask
, 1);
3092 else if (l
>= FRAG_RESULT_DATA0
&&
3093 l
< FRAG_RESULT_DATA0
+ BRW_MAX_DRAW_BUFFERS
)
3094 return alloc_temporary(v
->bld
, 4,
3095 &v
->outputs
[l
- FRAG_RESULT_DATA0
], 1);
3098 unreachable("Invalid location");
3102 fs_visitor::nir_emit_fs_intrinsic(const fs_builder
&bld
,
3103 nir_intrinsic_instr
*instr
)
3105 assert(stage
== MESA_SHADER_FRAGMENT
);
3108 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
3109 dest
= get_nir_dest(instr
->dest
);
3111 switch (instr
->intrinsic
) {
3112 case nir_intrinsic_load_front_face
:
3113 bld
.MOV(retype(dest
, BRW_REGISTER_TYPE_D
),
3114 *emit_frontfacing_interpolation());
3117 case nir_intrinsic_load_sample_pos
: {
3118 fs_reg sample_pos
= nir_system_values
[SYSTEM_VALUE_SAMPLE_POS
];
3119 assert(sample_pos
.file
!= BAD_FILE
);
3120 dest
.type
= sample_pos
.type
;
3121 bld
.MOV(dest
, sample_pos
);
3122 bld
.MOV(offset(dest
, bld
, 1), offset(sample_pos
, bld
, 1));
3126 case nir_intrinsic_load_layer_id
:
3127 dest
.type
= BRW_REGISTER_TYPE_UD
;
3128 bld
.MOV(dest
, fetch_render_target_array_index(bld
));
3131 case nir_intrinsic_load_helper_invocation
:
3132 case nir_intrinsic_load_sample_mask_in
:
3133 case nir_intrinsic_load_sample_id
: {
3134 gl_system_value sv
= nir_system_value_from_intrinsic(instr
->intrinsic
);
3135 fs_reg val
= nir_system_values
[sv
];
3136 assert(val
.file
!= BAD_FILE
);
3137 dest
.type
= val
.type
;
3142 case nir_intrinsic_store_output
: {
3143 const fs_reg src
= get_nir_src(instr
->src
[0]);
3144 const nir_const_value
*const_offset
= nir_src_as_const_value(instr
->src
[1]);
3145 assert(const_offset
&& "Indirect output stores not allowed");
3146 const unsigned location
= nir_intrinsic_base(instr
) +
3147 SET_FIELD(const_offset
->u32
[0], BRW_NIR_FRAG_OUTPUT_LOCATION
);
3148 const fs_reg new_dest
= retype(alloc_frag_output(this, location
),
3151 for (unsigned j
= 0; j
< instr
->num_components
; j
++)
3152 bld
.MOV(offset(new_dest
, bld
, nir_intrinsic_component(instr
) + j
),
3153 offset(src
, bld
, j
));
3158 case nir_intrinsic_load_output
: {
3159 const unsigned l
= GET_FIELD(nir_intrinsic_base(instr
),
3160 BRW_NIR_FRAG_OUTPUT_LOCATION
);
3161 assert(l
>= FRAG_RESULT_DATA0
);
3162 nir_const_value
*const_offset
= nir_src_as_const_value(instr
->src
[0]);
3163 assert(const_offset
&& "Indirect output loads not allowed");
3164 const unsigned target
= l
- FRAG_RESULT_DATA0
+ const_offset
->u32
[0];
3165 const fs_reg tmp
= bld
.vgrf(dest
.type
, 4);
3167 if (reinterpret_cast<const brw_wm_prog_key
*>(key
)->coherent_fb_fetch
)
3168 emit_coherent_fb_read(bld
, tmp
, target
);
3170 emit_non_coherent_fb_read(bld
, tmp
, target
);
3172 for (unsigned j
= 0; j
< instr
->num_components
; j
++) {
3173 bld
.MOV(offset(dest
, bld
, j
),
3174 offset(tmp
, bld
, nir_intrinsic_component(instr
) + j
));
3180 case nir_intrinsic_discard
:
3181 case nir_intrinsic_discard_if
: {
3182 /* We track our discarded pixels in f0.1. By predicating on it, we can
3183 * update just the flag bits that aren't yet discarded. If there's no
3184 * condition, we emit a CMP of g0 != g0, so all currently executing
3185 * channels will get turned off.
3188 if (instr
->intrinsic
== nir_intrinsic_discard_if
) {
3189 cmp
= bld
.CMP(bld
.null_reg_f(), get_nir_src(instr
->src
[0]),
3190 brw_imm_d(0), BRW_CONDITIONAL_Z
);
3192 fs_reg some_reg
= fs_reg(retype(brw_vec8_grf(0, 0),
3193 BRW_REGISTER_TYPE_UW
));
3194 cmp
= bld
.CMP(bld
.null_reg_f(), some_reg
, some_reg
, BRW_CONDITIONAL_NZ
);
3196 cmp
->predicate
= BRW_PREDICATE_NORMAL
;
3197 cmp
->flag_subreg
= 1;
3199 if (devinfo
->gen
>= 6) {
3200 emit_discard_jump();
3205 case nir_intrinsic_load_input
: {
3206 /* load_input is only used for flat inputs */
3207 unsigned base
= nir_intrinsic_base(instr
);
3208 unsigned component
= nir_intrinsic_component(instr
);
3209 unsigned num_components
= instr
->num_components
;
3210 enum brw_reg_type type
= dest
.type
;
3212 /* Special case fields in the VUE header */
3213 if (base
== VARYING_SLOT_LAYER
)
3215 else if (base
== VARYING_SLOT_VIEWPORT
)
3218 if (nir_dest_bit_size(instr
->dest
) == 64) {
3219 /* const_index is in 32-bit type size units that could not be aligned
3220 * with DF. We need to read the double vector as if it was a float
3221 * vector of twice the number of components to fetch the right data.
3223 type
= BRW_REGISTER_TYPE_F
;
3224 num_components
*= 2;
3227 for (unsigned int i
= 0; i
< num_components
; i
++) {
3228 struct brw_reg interp
= interp_reg(base
, component
+ i
);
3229 interp
= suboffset(interp
, 3);
3230 bld
.emit(FS_OPCODE_CINTERP
, offset(retype(dest
, type
), bld
, i
),
3231 retype(fs_reg(interp
), type
));
3234 if (nir_dest_bit_size(instr
->dest
) == 64) {
3235 shuffle_32bit_load_result_to_64bit_data(bld
,
3238 instr
->num_components
);
3243 case nir_intrinsic_load_barycentric_pixel
:
3244 case nir_intrinsic_load_barycentric_centroid
:
3245 case nir_intrinsic_load_barycentric_sample
:
3246 /* Do nothing - load_interpolated_input handling will handle it later. */
3249 case nir_intrinsic_load_barycentric_at_sample
: {
3250 const glsl_interp_mode interpolation
=
3251 (enum glsl_interp_mode
) nir_intrinsic_interp_mode(instr
);
3253 nir_const_value
*const_sample
= nir_src_as_const_value(instr
->src
[0]);
3256 unsigned msg_data
= const_sample
->i32
[0] << 4;
3258 emit_pixel_interpolater_send(bld
,
3259 FS_OPCODE_INTERPOLATE_AT_SAMPLE
,
3262 brw_imm_ud(msg_data
),
3265 const fs_reg sample_src
= retype(get_nir_src(instr
->src
[0]),
3266 BRW_REGISTER_TYPE_UD
);
3268 if (nir_src_is_dynamically_uniform(instr
->src
[0])) {
3269 const fs_reg sample_id
= bld
.emit_uniformize(sample_src
);
3270 const fs_reg msg_data
= vgrf(glsl_type::uint_type
);
3271 bld
.exec_all().group(1, 0)
3272 .SHL(msg_data
, sample_id
, brw_imm_ud(4u));
3273 emit_pixel_interpolater_send(bld
,
3274 FS_OPCODE_INTERPOLATE_AT_SAMPLE
,
3280 /* Make a loop that sends a message to the pixel interpolater
3281 * for the sample number in each live channel. If there are
3282 * multiple channels with the same sample number then these
3283 * will be handled simultaneously with a single interation of
3286 bld
.emit(BRW_OPCODE_DO
);
3288 /* Get the next live sample number into sample_id_reg */
3289 const fs_reg sample_id
= bld
.emit_uniformize(sample_src
);
3291 /* Set the flag register so that we can perform the send
3292 * message on all channels that have the same sample number
3294 bld
.CMP(bld
.null_reg_ud(),
3295 sample_src
, sample_id
,
3296 BRW_CONDITIONAL_EQ
);
3297 const fs_reg msg_data
= vgrf(glsl_type::uint_type
);
3298 bld
.exec_all().group(1, 0)
3299 .SHL(msg_data
, sample_id
, brw_imm_ud(4u));
3301 emit_pixel_interpolater_send(bld
,
3302 FS_OPCODE_INTERPOLATE_AT_SAMPLE
,
3307 set_predicate(BRW_PREDICATE_NORMAL
, inst
);
3309 /* Continue the loop if there are any live channels left */
3310 set_predicate_inv(BRW_PREDICATE_NORMAL
,
3312 bld
.emit(BRW_OPCODE_WHILE
));
3318 case nir_intrinsic_load_barycentric_at_offset
: {
3319 const glsl_interp_mode interpolation
=
3320 (enum glsl_interp_mode
) nir_intrinsic_interp_mode(instr
);
3322 nir_const_value
*const_offset
= nir_src_as_const_value(instr
->src
[0]);
3325 unsigned off_x
= MIN2((int)(const_offset
->f32
[0] * 16), 7) & 0xf;
3326 unsigned off_y
= MIN2((int)(const_offset
->f32
[1] * 16), 7) & 0xf;
3328 emit_pixel_interpolater_send(bld
,
3329 FS_OPCODE_INTERPOLATE_AT_SHARED_OFFSET
,
3332 brw_imm_ud(off_x
| (off_y
<< 4)),
3335 fs_reg src
= vgrf(glsl_type::ivec2_type
);
3336 fs_reg offset_src
= retype(get_nir_src(instr
->src
[0]),
3337 BRW_REGISTER_TYPE_F
);
3338 for (int i
= 0; i
< 2; i
++) {
3339 fs_reg temp
= vgrf(glsl_type::float_type
);
3340 bld
.MUL(temp
, offset(offset_src
, bld
, i
), brw_imm_f(16.0f
));
3341 fs_reg itemp
= vgrf(glsl_type::int_type
);
3343 bld
.MOV(itemp
, temp
);
3345 /* Clamp the upper end of the range to +7/16.
3346 * ARB_gpu_shader5 requires that we support a maximum offset
3347 * of +0.5, which isn't representable in a S0.4 value -- if
3348 * we didn't clamp it, we'd end up with -8/16, which is the
3349 * opposite of what the shader author wanted.
3351 * This is legal due to ARB_gpu_shader5's quantization
3354 * "Not all values of <offset> may be supported; x and y
3355 * offsets may be rounded to fixed-point values with the
3356 * number of fraction bits given by the
3357 * implementation-dependent constant
3358 * FRAGMENT_INTERPOLATION_OFFSET_BITS"
3360 set_condmod(BRW_CONDITIONAL_L
,
3361 bld
.SEL(offset(src
, bld
, i
), itemp
, brw_imm_d(7)));
3364 const enum opcode opcode
= FS_OPCODE_INTERPOLATE_AT_PER_SLOT_OFFSET
;
3365 emit_pixel_interpolater_send(bld
,
3375 case nir_intrinsic_load_interpolated_input
: {
3376 if (nir_intrinsic_base(instr
) == VARYING_SLOT_POS
) {
3377 emit_fragcoord_interpolation(dest
);
3381 assert(instr
->src
[0].ssa
&&
3382 instr
->src
[0].ssa
->parent_instr
->type
== nir_instr_type_intrinsic
);
3383 nir_intrinsic_instr
*bary_intrinsic
=
3384 nir_instr_as_intrinsic(instr
->src
[0].ssa
->parent_instr
);
3385 nir_intrinsic_op bary_intrin
= bary_intrinsic
->intrinsic
;
3386 enum glsl_interp_mode interp_mode
=
3387 (enum glsl_interp_mode
) nir_intrinsic_interp_mode(bary_intrinsic
);
3390 if (bary_intrin
== nir_intrinsic_load_barycentric_at_offset
||
3391 bary_intrin
== nir_intrinsic_load_barycentric_at_sample
) {
3392 /* Use the result of the PI message */
3393 dst_xy
= retype(get_nir_src(instr
->src
[0]), BRW_REGISTER_TYPE_F
);
3395 /* Use the delta_xy values computed from the payload */
3396 enum brw_barycentric_mode bary
=
3397 brw_barycentric_mode(interp_mode
, bary_intrin
);
3399 dst_xy
= this->delta_xy
[bary
];
3402 for (unsigned int i
= 0; i
< instr
->num_components
; i
++) {
3404 fs_reg(interp_reg(nir_intrinsic_base(instr
),
3405 nir_intrinsic_component(instr
) + i
));
3406 interp
.type
= BRW_REGISTER_TYPE_F
;
3407 dest
.type
= BRW_REGISTER_TYPE_F
;
3409 if (devinfo
->gen
< 6 && interp_mode
== INTERP_MODE_SMOOTH
) {
3410 fs_reg tmp
= vgrf(glsl_type::float_type
);
3411 bld
.emit(FS_OPCODE_LINTERP
, tmp
, dst_xy
, interp
);
3412 bld
.MUL(offset(dest
, bld
, i
), tmp
, this->pixel_w
);
3414 bld
.emit(FS_OPCODE_LINTERP
, offset(dest
, bld
, i
), dst_xy
, interp
);
3421 nir_emit_intrinsic(bld
, instr
);
3427 fs_visitor::nir_emit_cs_intrinsic(const fs_builder
&bld
,
3428 nir_intrinsic_instr
*instr
)
3430 assert(stage
== MESA_SHADER_COMPUTE
);
3431 struct brw_cs_prog_data
*cs_prog_data
= brw_cs_prog_data(prog_data
);
3434 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
3435 dest
= get_nir_dest(instr
->dest
);
3437 switch (instr
->intrinsic
) {
3438 case nir_intrinsic_barrier
:
3440 cs_prog_data
->uses_barrier
= true;
3443 case nir_intrinsic_load_subgroup_id
:
3444 bld
.MOV(retype(dest
, BRW_REGISTER_TYPE_UD
), subgroup_id
);
3447 case nir_intrinsic_load_local_invocation_id
:
3448 case nir_intrinsic_load_work_group_id
: {
3449 gl_system_value sv
= nir_system_value_from_intrinsic(instr
->intrinsic
);
3450 fs_reg val
= nir_system_values
[sv
];
3451 assert(val
.file
!= BAD_FILE
);
3452 dest
.type
= val
.type
;
3453 for (unsigned i
= 0; i
< 3; i
++)
3454 bld
.MOV(offset(dest
, bld
, i
), offset(val
, bld
, i
));
3458 case nir_intrinsic_load_num_work_groups
: {
3459 const unsigned surface
=
3460 cs_prog_data
->binding_table
.work_groups_start
;
3462 cs_prog_data
->uses_num_work_groups
= true;
3464 fs_reg surf_index
= brw_imm_ud(surface
);
3465 brw_mark_surface_used(prog_data
, surface
);
3467 /* Read the 3 GLuint components of gl_NumWorkGroups */
3468 for (unsigned i
= 0; i
< 3; i
++) {
3469 fs_reg read_result
=
3470 emit_untyped_read(bld
, surf_index
,
3472 1 /* dims */, 1 /* size */,
3473 BRW_PREDICATE_NONE
);
3474 read_result
.type
= dest
.type
;
3475 bld
.MOV(dest
, read_result
);
3476 dest
= offset(dest
, bld
, 1);
3481 case nir_intrinsic_shared_atomic_add
:
3482 nir_emit_shared_atomic(bld
, BRW_AOP_ADD
, instr
);
3484 case nir_intrinsic_shared_atomic_imin
:
3485 nir_emit_shared_atomic(bld
, BRW_AOP_IMIN
, instr
);
3487 case nir_intrinsic_shared_atomic_umin
:
3488 nir_emit_shared_atomic(bld
, BRW_AOP_UMIN
, instr
);
3490 case nir_intrinsic_shared_atomic_imax
:
3491 nir_emit_shared_atomic(bld
, BRW_AOP_IMAX
, instr
);
3493 case nir_intrinsic_shared_atomic_umax
:
3494 nir_emit_shared_atomic(bld
, BRW_AOP_UMAX
, instr
);
3496 case nir_intrinsic_shared_atomic_and
:
3497 nir_emit_shared_atomic(bld
, BRW_AOP_AND
, instr
);
3499 case nir_intrinsic_shared_atomic_or
:
3500 nir_emit_shared_atomic(bld
, BRW_AOP_OR
, instr
);
3502 case nir_intrinsic_shared_atomic_xor
:
3503 nir_emit_shared_atomic(bld
, BRW_AOP_XOR
, instr
);
3505 case nir_intrinsic_shared_atomic_exchange
:
3506 nir_emit_shared_atomic(bld
, BRW_AOP_MOV
, instr
);
3508 case nir_intrinsic_shared_atomic_comp_swap
:
3509 nir_emit_shared_atomic(bld
, BRW_AOP_CMPWR
, instr
);
3512 case nir_intrinsic_load_shared
: {
3513 assert(devinfo
->gen
>= 7);
3515 fs_reg surf_index
= brw_imm_ud(GEN7_BTI_SLM
);
3517 /* Get the offset to read from */
3519 nir_const_value
*const_offset
= nir_src_as_const_value(instr
->src
[0]);
3521 offset_reg
= brw_imm_ud(instr
->const_index
[0] + const_offset
->u32
[0]);
3523 offset_reg
= vgrf(glsl_type::uint_type
);
3525 retype(get_nir_src(instr
->src
[0]), BRW_REGISTER_TYPE_UD
),
3526 brw_imm_ud(instr
->const_index
[0]));
3529 /* Read the vector */
3530 do_untyped_vector_read(bld
, dest
, surf_index
, offset_reg
,
3531 instr
->num_components
);
3535 case nir_intrinsic_store_shared
: {
3536 assert(devinfo
->gen
>= 7);
3539 fs_reg surf_index
= brw_imm_ud(GEN7_BTI_SLM
);
3542 fs_reg val_reg
= get_nir_src(instr
->src
[0]);
3545 unsigned writemask
= instr
->const_index
[1];
3547 /* get_nir_src() retypes to integer. Be wary of 64-bit types though
3548 * since the untyped writes below operate in units of 32-bits, which
3549 * means that we need to write twice as many components each time.
3550 * Also, we have to suffle 64-bit data to be in the appropriate layout
3551 * expected by our 32-bit write messages.
3553 unsigned type_size
= 4;
3554 if (nir_src_bit_size(instr
->src
[0]) == 64) {
3556 val_reg
= shuffle_64bit_data_for_32bit_write(bld
,
3557 val_reg
, instr
->num_components
);
3560 unsigned type_slots
= type_size
/ 4;
3562 /* Combine groups of consecutive enabled channels in one write
3563 * message. We use ffs to find the first enabled channel and then ffs on
3564 * the bit-inverse, down-shifted writemask to determine the length of
3565 * the block of enabled bits.
3568 unsigned first_component
= ffs(writemask
) - 1;
3569 unsigned length
= ffs(~(writemask
>> first_component
)) - 1;
3571 /* We can't write more than 2 64-bit components at once. Limit the
3572 * length of the write to what we can do and let the next iteration
3576 length
= MIN2(2, length
);
3579 nir_const_value
*const_offset
= nir_src_as_const_value(instr
->src
[1]);
3581 offset_reg
= brw_imm_ud(instr
->const_index
[0] + const_offset
->u32
[0] +
3582 type_size
* first_component
);
3584 offset_reg
= vgrf(glsl_type::uint_type
);
3586 retype(get_nir_src(instr
->src
[1]), BRW_REGISTER_TYPE_UD
),
3587 brw_imm_ud(instr
->const_index
[0] + type_size
* first_component
));
3590 emit_untyped_write(bld
, surf_index
, offset_reg
,
3591 offset(val_reg
, bld
, first_component
* type_slots
),
3592 1 /* dims */, length
* type_slots
,
3593 BRW_PREDICATE_NONE
);
3595 /* Clear the bits in the writemask that we just wrote, then try
3596 * again to see if more channels are left.
3598 writemask
&= (15 << (first_component
+ length
));
3605 nir_emit_intrinsic(bld
, instr
);
3611 fs_visitor::nir_emit_intrinsic(const fs_builder
&bld
, nir_intrinsic_instr
*instr
)
3614 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
3615 dest
= get_nir_dest(instr
->dest
);
3617 switch (instr
->intrinsic
) {
3618 case nir_intrinsic_atomic_counter_inc
:
3619 case nir_intrinsic_atomic_counter_dec
:
3620 case nir_intrinsic_atomic_counter_read
:
3621 case nir_intrinsic_atomic_counter_add
:
3622 case nir_intrinsic_atomic_counter_min
:
3623 case nir_intrinsic_atomic_counter_max
:
3624 case nir_intrinsic_atomic_counter_and
:
3625 case nir_intrinsic_atomic_counter_or
:
3626 case nir_intrinsic_atomic_counter_xor
:
3627 case nir_intrinsic_atomic_counter_exchange
:
3628 case nir_intrinsic_atomic_counter_comp_swap
: {
3629 if (stage
== MESA_SHADER_FRAGMENT
&&
3630 instr
->intrinsic
!= nir_intrinsic_atomic_counter_read
)
3631 brw_wm_prog_data(prog_data
)->has_side_effects
= true;
3633 /* Get some metadata from the image intrinsic. */
3634 const nir_intrinsic_info
*info
= &nir_intrinsic_infos
[instr
->intrinsic
];
3636 /* Get the arguments of the atomic intrinsic. */
3637 const fs_reg offset
= get_nir_src(instr
->src
[0]);
3638 const unsigned surface
= (stage_prog_data
->binding_table
.abo_start
+
3639 instr
->const_index
[0]);
3640 const fs_reg src0
= (info
->num_srcs
>= 2
3641 ? get_nir_src(instr
->src
[1]) : fs_reg());
3642 const fs_reg src1
= (info
->num_srcs
>= 3
3643 ? get_nir_src(instr
->src
[2]) : fs_reg());
3646 assert(info
->num_srcs
<= 3);
3648 /* Emit a surface read or atomic op. */
3649 if (instr
->intrinsic
== nir_intrinsic_atomic_counter_read
) {
3650 tmp
= emit_untyped_read(bld
, brw_imm_ud(surface
), offset
, 1, 1);
3652 tmp
= emit_untyped_atomic(bld
, brw_imm_ud(surface
), offset
, src0
,
3654 get_atomic_counter_op(instr
->intrinsic
));
3657 /* Assign the result. */
3658 bld
.MOV(retype(dest
, BRW_REGISTER_TYPE_UD
), tmp
);
3660 /* Mark the surface as used. */
3661 brw_mark_surface_used(stage_prog_data
, surface
);
3665 case nir_intrinsic_image_load
:
3666 case nir_intrinsic_image_store
:
3667 case nir_intrinsic_image_atomic_add
:
3668 case nir_intrinsic_image_atomic_min
:
3669 case nir_intrinsic_image_atomic_max
:
3670 case nir_intrinsic_image_atomic_and
:
3671 case nir_intrinsic_image_atomic_or
:
3672 case nir_intrinsic_image_atomic_xor
:
3673 case nir_intrinsic_image_atomic_exchange
:
3674 case nir_intrinsic_image_atomic_comp_swap
: {
3675 using namespace image_access
;
3677 if (stage
== MESA_SHADER_FRAGMENT
&&
3678 instr
->intrinsic
!= nir_intrinsic_image_load
)
3679 brw_wm_prog_data(prog_data
)->has_side_effects
= true;
3681 /* Get the referenced image variable and type. */
3682 const nir_variable
*var
= instr
->variables
[0]->var
;
3683 const glsl_type
*type
= var
->type
->without_array();
3684 const brw_reg_type base_type
= get_image_base_type(type
);
3686 /* Get some metadata from the image intrinsic. */
3687 const nir_intrinsic_info
*info
= &nir_intrinsic_infos
[instr
->intrinsic
];
3688 const unsigned arr_dims
= type
->sampler_array
? 1 : 0;
3689 const unsigned surf_dims
= type
->coordinate_components() - arr_dims
;
3690 const unsigned format
= var
->data
.image
.format
;
3692 /* Get the arguments of the image intrinsic. */
3693 const fs_reg image
= get_nir_image_deref(instr
->variables
[0]);
3694 const fs_reg addr
= retype(get_nir_src(instr
->src
[0]),
3695 BRW_REGISTER_TYPE_UD
);
3696 const fs_reg src0
= (info
->num_srcs
>= 3 ?
3697 retype(get_nir_src(instr
->src
[2]), base_type
) :
3699 const fs_reg src1
= (info
->num_srcs
>= 4 ?
3700 retype(get_nir_src(instr
->src
[3]), base_type
) :
3704 /* Emit an image load, store or atomic op. */
3705 if (instr
->intrinsic
== nir_intrinsic_image_load
)
3706 tmp
= emit_image_load(bld
, image
, addr
, surf_dims
, arr_dims
, format
);
3708 else if (instr
->intrinsic
== nir_intrinsic_image_store
)
3709 emit_image_store(bld
, image
, addr
, src0
, surf_dims
, arr_dims
,
3710 var
->data
.image
.write_only
? GL_NONE
: format
);
3713 tmp
= emit_image_atomic(bld
, image
, addr
, src0
, src1
,
3714 surf_dims
, arr_dims
, info
->dest_components
,
3715 get_image_atomic_op(instr
->intrinsic
, type
));
3717 /* Assign the result. */
3718 for (unsigned c
= 0; c
< info
->dest_components
; ++c
)
3719 bld
.MOV(offset(retype(dest
, base_type
), bld
, c
),
3720 offset(tmp
, bld
, c
));
3724 case nir_intrinsic_memory_barrier_atomic_counter
:
3725 case nir_intrinsic_memory_barrier_buffer
:
3726 case nir_intrinsic_memory_barrier_image
:
3727 case nir_intrinsic_memory_barrier
: {
3728 const fs_builder ubld
= bld
.group(8, 0);
3729 const fs_reg tmp
= ubld
.vgrf(BRW_REGISTER_TYPE_UD
, 2);
3730 ubld
.emit(SHADER_OPCODE_MEMORY_FENCE
, tmp
)
3731 ->size_written
= 2 * REG_SIZE
;
3735 case nir_intrinsic_group_memory_barrier
:
3736 case nir_intrinsic_memory_barrier_shared
:
3737 /* We treat these workgroup-level barriers as no-ops. This should be
3738 * safe at present and as long as:
3740 * - Memory access instructions are not subsequently reordered by the
3741 * compiler back-end.
3743 * - All threads from a given compute shader workgroup fit within a
3744 * single subslice and therefore talk to the same HDC shared unit
3745 * what supposedly guarantees ordering and coherency between threads
3746 * from the same workgroup. This may change in the future when we
3747 * start splitting workgroups across multiple subslices.
3749 * - The context is not in fault-and-stream mode, which could cause
3750 * memory transactions (including to SLM) prior to the barrier to be
3751 * replayed after the barrier if a pagefault occurs. This shouldn't
3752 * be a problem up to and including SKL because fault-and-stream is
3753 * not usable due to hardware issues, but that's likely to change in
3758 case nir_intrinsic_shader_clock
: {
3759 /* We cannot do anything if there is an event, so ignore it for now */
3760 const fs_reg shader_clock
= get_timestamp(bld
);
3761 const fs_reg srcs
[] = { component(shader_clock
, 0),
3762 component(shader_clock
, 1) };
3763 bld
.LOAD_PAYLOAD(dest
, srcs
, ARRAY_SIZE(srcs
), 0);
3767 case nir_intrinsic_image_size
: {
3768 /* Get the referenced image variable and type. */
3769 const nir_variable
*var
= instr
->variables
[0]->var
;
3770 const glsl_type
*type
= var
->type
->without_array();
3772 /* Get the size of the image. */
3773 const fs_reg image
= get_nir_image_deref(instr
->variables
[0]);
3774 const fs_reg size
= offset(image
, bld
, BRW_IMAGE_PARAM_SIZE_OFFSET
);
3776 /* For 1DArray image types, the array index is stored in the Z component.
3777 * Fix this by swizzling the Z component to the Y component.
3779 const bool is_1d_array_image
=
3780 type
->sampler_dimensionality
== GLSL_SAMPLER_DIM_1D
&&
3781 type
->sampler_array
;
3783 /* For CubeArray images, we should count the number of cubes instead
3784 * of the number of faces. Fix it by dividing the (Z component) by 6.
3786 const bool is_cube_array_image
=
3787 type
->sampler_dimensionality
== GLSL_SAMPLER_DIM_CUBE
&&
3788 type
->sampler_array
;
3790 /* Copy all the components. */
3791 for (unsigned c
= 0; c
< instr
->dest
.ssa
.num_components
; ++c
) {
3792 if ((int)c
>= type
->coordinate_components()) {
3793 bld
.MOV(offset(retype(dest
, BRW_REGISTER_TYPE_D
), bld
, c
),
3795 } else if (c
== 1 && is_1d_array_image
) {
3796 bld
.MOV(offset(retype(dest
, BRW_REGISTER_TYPE_D
), bld
, c
),
3797 offset(size
, bld
, 2));
3798 } else if (c
== 2 && is_cube_array_image
) {
3799 bld
.emit(SHADER_OPCODE_INT_QUOTIENT
,
3800 offset(retype(dest
, BRW_REGISTER_TYPE_D
), bld
, c
),
3801 offset(size
, bld
, c
), brw_imm_d(6));
3803 bld
.MOV(offset(retype(dest
, BRW_REGISTER_TYPE_D
), bld
, c
),
3804 offset(size
, bld
, c
));
3811 case nir_intrinsic_image_samples
:
3812 /* The driver does not support multi-sampled images. */
3813 bld
.MOV(retype(dest
, BRW_REGISTER_TYPE_D
), brw_imm_d(1));
3816 case nir_intrinsic_load_uniform
: {
3817 /* Offsets are in bytes but they should always be multiples of 4 */
3818 assert(instr
->const_index
[0] % 4 == 0);
3820 fs_reg
src(UNIFORM
, instr
->const_index
[0] / 4, dest
.type
);
3822 nir_const_value
*const_offset
= nir_src_as_const_value(instr
->src
[0]);
3824 /* Offsets are in bytes but they should always be multiples of 4 */
3825 assert(const_offset
->u32
[0] % 4 == 0);
3826 src
.offset
= const_offset
->u32
[0];
3828 for (unsigned j
= 0; j
< instr
->num_components
; j
++) {
3829 bld
.MOV(offset(dest
, bld
, j
), offset(src
, bld
, j
));
3832 fs_reg indirect
= retype(get_nir_src(instr
->src
[0]),
3833 BRW_REGISTER_TYPE_UD
);
3835 /* We need to pass a size to the MOV_INDIRECT but we don't want it to
3836 * go past the end of the uniform. In order to keep the n'th
3837 * component from running past, we subtract off the size of all but
3838 * one component of the vector.
3840 assert(instr
->const_index
[1] >=
3841 instr
->num_components
* (int) type_sz(dest
.type
));
3842 unsigned read_size
= instr
->const_index
[1] -
3843 (instr
->num_components
- 1) * type_sz(dest
.type
);
3845 bool supports_64bit_indirects
=
3846 !devinfo
->is_cherryview
&& !gen_device_info_is_9lp(devinfo
);
3848 if (type_sz(dest
.type
) != 8 || supports_64bit_indirects
) {
3849 for (unsigned j
= 0; j
< instr
->num_components
; j
++) {
3850 bld
.emit(SHADER_OPCODE_MOV_INDIRECT
,
3851 offset(dest
, bld
, j
), offset(src
, bld
, j
),
3852 indirect
, brw_imm_ud(read_size
));
3855 const unsigned num_mov_indirects
=
3856 type_sz(dest
.type
) / type_sz(BRW_REGISTER_TYPE_UD
);
3857 /* We read a little bit less per MOV INDIRECT, as they are now
3858 * 32-bits ones instead of 64-bit. Fix read_size then.
3860 const unsigned read_size_32bit
= read_size
-
3861 (num_mov_indirects
- 1) * type_sz(BRW_REGISTER_TYPE_UD
);
3862 for (unsigned j
= 0; j
< instr
->num_components
; j
++) {
3863 for (unsigned i
= 0; i
< num_mov_indirects
; i
++) {
3864 bld
.emit(SHADER_OPCODE_MOV_INDIRECT
,
3865 subscript(offset(dest
, bld
, j
), BRW_REGISTER_TYPE_UD
, i
),
3866 subscript(offset(src
, bld
, j
), BRW_REGISTER_TYPE_UD
, i
),
3867 indirect
, brw_imm_ud(read_size_32bit
));
3875 case nir_intrinsic_load_ubo
: {
3876 nir_const_value
*const_index
= nir_src_as_const_value(instr
->src
[0]);
3880 const unsigned index
= stage_prog_data
->binding_table
.ubo_start
+
3881 const_index
->u32
[0];
3882 surf_index
= brw_imm_ud(index
);
3883 brw_mark_surface_used(prog_data
, index
);
3885 /* The block index is not a constant. Evaluate the index expression
3886 * per-channel and add the base UBO index; we have to select a value
3887 * from any live channel.
3889 surf_index
= vgrf(glsl_type::uint_type
);
3890 bld
.ADD(surf_index
, get_nir_src(instr
->src
[0]),
3891 brw_imm_ud(stage_prog_data
->binding_table
.ubo_start
));
3892 surf_index
= bld
.emit_uniformize(surf_index
);
3894 /* Assume this may touch any UBO. It would be nice to provide
3895 * a tighter bound, but the array information is already lowered away.
3897 brw_mark_surface_used(prog_data
,
3898 stage_prog_data
->binding_table
.ubo_start
+
3899 nir
->info
.num_ubos
- 1);
3902 nir_const_value
*const_offset
= nir_src_as_const_value(instr
->src
[1]);
3903 if (const_offset
== NULL
) {
3904 fs_reg base_offset
= retype(get_nir_src(instr
->src
[1]),
3905 BRW_REGISTER_TYPE_UD
);
3907 for (int i
= 0; i
< instr
->num_components
; i
++)
3908 VARYING_PULL_CONSTANT_LOAD(bld
, offset(dest
, bld
, i
), surf_index
,
3909 base_offset
, i
* type_sz(dest
.type
));
3911 /* Even if we are loading doubles, a pull constant load will load
3912 * a 32-bit vec4, so should only reserve vgrf space for that. If we
3913 * need to load a full dvec4 we will have to emit 2 loads. This is
3914 * similar to demote_pull_constants(), except that in that case we
3915 * see individual accesses to each component of the vector and then
3916 * we let CSE deal with duplicate loads. Here we see a vector access
3917 * and we have to split it if necessary.
3919 const unsigned type_size
= type_sz(dest
.type
);
3921 /* See if we've selected this as a push constant candidate */
3923 const unsigned ubo_block
= const_index
->u32
[0];
3924 const unsigned offset_256b
= const_offset
->u32
[0] / 32;
3927 for (int i
= 0; i
< 4; i
++) {
3928 const struct brw_ubo_range
*range
= &prog_data
->ubo_ranges
[i
];
3929 if (range
->block
== ubo_block
&&
3930 offset_256b
>= range
->start
&&
3931 offset_256b
< range
->start
+ range
->length
) {
3933 push_reg
= fs_reg(UNIFORM
, UBO_START
+ i
, dest
.type
);
3934 push_reg
.offset
= const_offset
->u32
[0] - 32 * range
->start
;
3939 if (push_reg
.file
!= BAD_FILE
) {
3940 for (unsigned i
= 0; i
< instr
->num_components
; i
++) {
3941 bld
.MOV(offset(dest
, bld
, i
),
3942 byte_offset(push_reg
, i
* type_size
));
3948 const unsigned block_sz
= 64; /* Fetch one cacheline at a time. */
3949 const fs_builder ubld
= bld
.exec_all().group(block_sz
/ 4, 0);
3950 const fs_reg packed_consts
= ubld
.vgrf(BRW_REGISTER_TYPE_UD
);
3952 for (unsigned c
= 0; c
< instr
->num_components
;) {
3953 const unsigned base
= const_offset
->u32
[0] + c
* type_size
;
3954 /* Number of usable components in the next block-aligned load. */
3955 const unsigned count
= MIN2(instr
->num_components
- c
,
3956 (block_sz
- base
% block_sz
) / type_size
);
3958 ubld
.emit(FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD
,
3959 packed_consts
, surf_index
,
3960 brw_imm_ud(base
& ~(block_sz
- 1)));
3962 const fs_reg consts
=
3963 retype(byte_offset(packed_consts
, base
& (block_sz
- 1)),
3966 for (unsigned d
= 0; d
< count
; d
++)
3967 bld
.MOV(offset(dest
, bld
, c
+ d
), component(consts
, d
));
3975 case nir_intrinsic_load_ssbo
: {
3976 assert(devinfo
->gen
>= 7);
3978 nir_const_value
*const_uniform_block
=
3979 nir_src_as_const_value(instr
->src
[0]);
3982 if (const_uniform_block
) {
3983 unsigned index
= stage_prog_data
->binding_table
.ssbo_start
+
3984 const_uniform_block
->u32
[0];
3985 surf_index
= brw_imm_ud(index
);
3986 brw_mark_surface_used(prog_data
, index
);
3988 surf_index
= vgrf(glsl_type::uint_type
);
3989 bld
.ADD(surf_index
, get_nir_src(instr
->src
[0]),
3990 brw_imm_ud(stage_prog_data
->binding_table
.ssbo_start
));
3992 /* Assume this may touch any UBO. It would be nice to provide
3993 * a tighter bound, but the array information is already lowered away.
3995 brw_mark_surface_used(prog_data
,
3996 stage_prog_data
->binding_table
.ssbo_start
+
3997 nir
->info
.num_ssbos
- 1);
4001 nir_const_value
*const_offset
= nir_src_as_const_value(instr
->src
[1]);
4003 offset_reg
= brw_imm_ud(const_offset
->u32
[0]);
4005 offset_reg
= get_nir_src(instr
->src
[1]);
4008 /* Read the vector */
4009 do_untyped_vector_read(bld
, dest
, surf_index
, offset_reg
,
4010 instr
->num_components
);
4015 case nir_intrinsic_store_ssbo
: {
4016 assert(devinfo
->gen
>= 7);
4018 if (stage
== MESA_SHADER_FRAGMENT
)
4019 brw_wm_prog_data(prog_data
)->has_side_effects
= true;
4023 nir_const_value
*const_uniform_block
=
4024 nir_src_as_const_value(instr
->src
[1]);
4025 if (const_uniform_block
) {
4026 unsigned index
= stage_prog_data
->binding_table
.ssbo_start
+
4027 const_uniform_block
->u32
[0];
4028 surf_index
= brw_imm_ud(index
);
4029 brw_mark_surface_used(prog_data
, index
);
4031 surf_index
= vgrf(glsl_type::uint_type
);
4032 bld
.ADD(surf_index
, get_nir_src(instr
->src
[1]),
4033 brw_imm_ud(stage_prog_data
->binding_table
.ssbo_start
));
4035 brw_mark_surface_used(prog_data
,
4036 stage_prog_data
->binding_table
.ssbo_start
+
4037 nir
->info
.num_ssbos
- 1);
4041 fs_reg val_reg
= get_nir_src(instr
->src
[0]);
4044 unsigned writemask
= instr
->const_index
[0];
4046 /* get_nir_src() retypes to integer. Be wary of 64-bit types though
4047 * since the untyped writes below operate in units of 32-bits, which
4048 * means that we need to write twice as many components each time.
4049 * Also, we have to suffle 64-bit data to be in the appropriate layout
4050 * expected by our 32-bit write messages.
4052 unsigned type_size
= 4;
4053 if (nir_src_bit_size(instr
->src
[0]) == 64) {
4055 val_reg
= shuffle_64bit_data_for_32bit_write(bld
,
4056 val_reg
, instr
->num_components
);
4059 unsigned type_slots
= type_size
/ 4;
4061 /* Combine groups of consecutive enabled channels in one write
4062 * message. We use ffs to find the first enabled channel and then ffs on
4063 * the bit-inverse, down-shifted writemask to determine the length of
4064 * the block of enabled bits.
4067 unsigned first_component
= ffs(writemask
) - 1;
4068 unsigned length
= ffs(~(writemask
>> first_component
)) - 1;
4070 /* We can't write more than 2 64-bit components at once. Limit the
4071 * length of the write to what we can do and let the next iteration
4075 length
= MIN2(2, length
);
4078 nir_const_value
*const_offset
= nir_src_as_const_value(instr
->src
[2]);
4080 offset_reg
= brw_imm_ud(const_offset
->u32
[0] +
4081 type_size
* first_component
);
4083 offset_reg
= vgrf(glsl_type::uint_type
);
4085 retype(get_nir_src(instr
->src
[2]), BRW_REGISTER_TYPE_UD
),
4086 brw_imm_ud(type_size
* first_component
));
4090 emit_untyped_write(bld
, surf_index
, offset_reg
,
4091 offset(val_reg
, bld
, first_component
* type_slots
),
4092 1 /* dims */, length
* type_slots
,
4093 BRW_PREDICATE_NONE
);
4095 /* Clear the bits in the writemask that we just wrote, then try
4096 * again to see if more channels are left.
4098 writemask
&= (15 << (first_component
+ length
));
4103 case nir_intrinsic_store_output
: {
4104 fs_reg src
= get_nir_src(instr
->src
[0]);
4106 nir_const_value
*const_offset
= nir_src_as_const_value(instr
->src
[1]);
4107 assert(const_offset
&& "Indirect output stores not allowed");
4109 unsigned num_components
= instr
->num_components
;
4110 unsigned first_component
= nir_intrinsic_component(instr
);
4111 if (nir_src_bit_size(instr
->src
[0]) == 64) {
4112 src
= shuffle_64bit_data_for_32bit_write(bld
, src
, num_components
);
4113 num_components
*= 2;
4116 fs_reg new_dest
= retype(offset(outputs
[instr
->const_index
[0]], bld
,
4117 4 * const_offset
->u32
[0]), src
.type
);
4118 for (unsigned j
= 0; j
< num_components
; j
++) {
4119 bld
.MOV(offset(new_dest
, bld
, j
+ first_component
),
4120 offset(src
, bld
, j
));
4125 case nir_intrinsic_ssbo_atomic_add
:
4126 nir_emit_ssbo_atomic(bld
, BRW_AOP_ADD
, instr
);
4128 case nir_intrinsic_ssbo_atomic_imin
:
4129 nir_emit_ssbo_atomic(bld
, BRW_AOP_IMIN
, instr
);
4131 case nir_intrinsic_ssbo_atomic_umin
:
4132 nir_emit_ssbo_atomic(bld
, BRW_AOP_UMIN
, instr
);
4134 case nir_intrinsic_ssbo_atomic_imax
:
4135 nir_emit_ssbo_atomic(bld
, BRW_AOP_IMAX
, instr
);
4137 case nir_intrinsic_ssbo_atomic_umax
:
4138 nir_emit_ssbo_atomic(bld
, BRW_AOP_UMAX
, instr
);
4140 case nir_intrinsic_ssbo_atomic_and
:
4141 nir_emit_ssbo_atomic(bld
, BRW_AOP_AND
, instr
);
4143 case nir_intrinsic_ssbo_atomic_or
:
4144 nir_emit_ssbo_atomic(bld
, BRW_AOP_OR
, instr
);
4146 case nir_intrinsic_ssbo_atomic_xor
:
4147 nir_emit_ssbo_atomic(bld
, BRW_AOP_XOR
, instr
);
4149 case nir_intrinsic_ssbo_atomic_exchange
:
4150 nir_emit_ssbo_atomic(bld
, BRW_AOP_MOV
, instr
);
4152 case nir_intrinsic_ssbo_atomic_comp_swap
:
4153 nir_emit_ssbo_atomic(bld
, BRW_AOP_CMPWR
, instr
);
4156 case nir_intrinsic_get_buffer_size
: {
4157 nir_const_value
*const_uniform_block
= nir_src_as_const_value(instr
->src
[0]);
4158 unsigned ssbo_index
= const_uniform_block
? const_uniform_block
->u32
[0] : 0;
4160 /* A resinfo's sampler message is used to get the buffer size. The
4161 * SIMD8's writeback message consists of four registers and SIMD16's
4162 * writeback message consists of 8 destination registers (two per each
4163 * component). Because we are only interested on the first channel of
4164 * the first returned component, where resinfo returns the buffer size
4165 * for SURFTYPE_BUFFER, we can just use the SIMD8 variant regardless of
4166 * the dispatch width.
4168 const fs_builder ubld
= bld
.exec_all().group(8, 0);
4169 fs_reg src_payload
= ubld
.vgrf(BRW_REGISTER_TYPE_UD
);
4170 fs_reg ret_payload
= ubld
.vgrf(BRW_REGISTER_TYPE_UD
, 4);
4173 ubld
.MOV(src_payload
, brw_imm_d(0));
4175 const unsigned index
= prog_data
->binding_table
.ssbo_start
+ ssbo_index
;
4176 fs_inst
*inst
= ubld
.emit(FS_OPCODE_GET_BUFFER_SIZE
, ret_payload
,
4177 src_payload
, brw_imm_ud(index
));
4178 inst
->header_size
= 0;
4180 inst
->size_written
= 4 * REG_SIZE
;
4182 bld
.MOV(retype(dest
, ret_payload
.type
), component(ret_payload
, 0));
4183 brw_mark_surface_used(prog_data
, index
);
4187 case nir_intrinsic_load_subgroup_invocation
:
4188 bld
.MOV(retype(dest
, BRW_REGISTER_TYPE_D
),
4189 nir_system_values
[SYSTEM_VALUE_SUBGROUP_INVOCATION
]);
4192 case nir_intrinsic_load_subgroup_eq_mask
:
4193 case nir_intrinsic_load_subgroup_ge_mask
:
4194 case nir_intrinsic_load_subgroup_gt_mask
:
4195 case nir_intrinsic_load_subgroup_le_mask
:
4196 case nir_intrinsic_load_subgroup_lt_mask
:
4197 unreachable("not reached");
4199 case nir_intrinsic_vote_any
: {
4200 const fs_builder ubld
= bld
.exec_all().group(1, 0);
4202 /* The any/all predicates do not consider channel enables. To prevent
4203 * dead channels from affecting the result, we initialize the flag with
4204 * with the identity value for the logical operation.
4206 if (dispatch_width
== 32) {
4207 /* For SIMD32, we use a UD type so we fill both f0.0 and f0.1. */
4208 ubld
.MOV(retype(brw_flag_reg(0, 0), BRW_REGISTER_TYPE_UD
),
4211 ubld
.MOV(brw_flag_reg(0, 0), brw_imm_uw(0));
4213 bld
.CMP(bld
.null_reg_d(), get_nir_src(instr
->src
[0]), brw_imm_d(0), BRW_CONDITIONAL_NZ
);
4215 /* For some reason, the any/all predicates don't work properly with
4216 * SIMD32. In particular, it appears that a SEL with a QtrCtrl of 2H
4217 * doesn't read the correct subset of the flag register and you end up
4218 * getting garbage in the second half. Work around this by using a pair
4219 * of 1-wide MOVs and scattering the result.
4221 fs_reg res1
= ubld
.vgrf(BRW_REGISTER_TYPE_D
);
4222 ubld
.MOV(res1
, brw_imm_d(0));
4223 set_predicate(dispatch_width
== 8 ? BRW_PREDICATE_ALIGN1_ANY8H
:
4224 dispatch_width
== 16 ? BRW_PREDICATE_ALIGN1_ANY16H
:
4225 BRW_PREDICATE_ALIGN1_ANY32H
,
4226 ubld
.MOV(res1
, brw_imm_d(-1)));
4228 bld
.MOV(retype(dest
, BRW_REGISTER_TYPE_D
), component(res1
, 0));
4231 case nir_intrinsic_vote_all
: {
4232 const fs_builder ubld
= bld
.exec_all().group(1, 0);
4234 /* The any/all predicates do not consider channel enables. To prevent
4235 * dead channels from affecting the result, we initialize the flag with
4236 * with the identity value for the logical operation.
4238 if (dispatch_width
== 32) {
4239 /* For SIMD32, we use a UD type so we fill both f0.0 and f0.1. */
4240 ubld
.MOV(retype(brw_flag_reg(0, 0), BRW_REGISTER_TYPE_UD
),
4241 brw_imm_ud(0xffffffff));
4243 ubld
.MOV(brw_flag_reg(0, 0), brw_imm_uw(0xffff));
4245 bld
.CMP(bld
.null_reg_d(), get_nir_src(instr
->src
[0]), brw_imm_d(0), BRW_CONDITIONAL_NZ
);
4247 /* For some reason, the any/all predicates don't work properly with
4248 * SIMD32. In particular, it appears that a SEL with a QtrCtrl of 2H
4249 * doesn't read the correct subset of the flag register and you end up
4250 * getting garbage in the second half. Work around this by using a pair
4251 * of 1-wide MOVs and scattering the result.
4253 fs_reg res1
= ubld
.vgrf(BRW_REGISTER_TYPE_D
);
4254 ubld
.MOV(res1
, brw_imm_d(0));
4255 set_predicate(dispatch_width
== 8 ? BRW_PREDICATE_ALIGN1_ALL8H
:
4256 dispatch_width
== 16 ? BRW_PREDICATE_ALIGN1_ALL16H
:
4257 BRW_PREDICATE_ALIGN1_ALL32H
,
4258 ubld
.MOV(res1
, brw_imm_d(-1)));
4260 bld
.MOV(retype(dest
, BRW_REGISTER_TYPE_D
), component(res1
, 0));
4263 case nir_intrinsic_vote_eq
: {
4264 fs_reg value
= get_nir_src(instr
->src
[0]);
4265 fs_reg uniformized
= bld
.emit_uniformize(value
);
4266 const fs_builder ubld
= bld
.exec_all().group(1, 0);
4268 /* The any/all predicates do not consider channel enables. To prevent
4269 * dead channels from affecting the result, we initialize the flag with
4270 * with the identity value for the logical operation.
4272 if (dispatch_width
== 32) {
4273 /* For SIMD32, we use a UD type so we fill both f0.0 and f0.1. */
4274 ubld
.MOV(retype(brw_flag_reg(0, 0), BRW_REGISTER_TYPE_UD
),
4275 brw_imm_ud(0xffffffff));
4277 ubld
.MOV(brw_flag_reg(0, 0), brw_imm_uw(0xffff));
4279 bld
.CMP(bld
.null_reg_d(), value
, uniformized
, BRW_CONDITIONAL_Z
);
4281 /* For some reason, the any/all predicates don't work properly with
4282 * SIMD32. In particular, it appears that a SEL with a QtrCtrl of 2H
4283 * doesn't read the correct subset of the flag register and you end up
4284 * getting garbage in the second half. Work around this by using a pair
4285 * of 1-wide MOVs and scattering the result.
4287 fs_reg res1
= ubld
.vgrf(BRW_REGISTER_TYPE_D
);
4288 ubld
.MOV(res1
, brw_imm_d(0));
4289 set_predicate(dispatch_width
== 8 ? BRW_PREDICATE_ALIGN1_ALL8H
:
4290 dispatch_width
== 16 ? BRW_PREDICATE_ALIGN1_ALL16H
:
4291 BRW_PREDICATE_ALIGN1_ALL32H
,
4292 ubld
.MOV(res1
, brw_imm_d(-1)));
4294 bld
.MOV(retype(dest
, BRW_REGISTER_TYPE_D
), component(res1
, 0));
4298 case nir_intrinsic_ballot
: {
4299 const fs_reg value
= retype(get_nir_src(instr
->src
[0]),
4300 BRW_REGISTER_TYPE_UD
);
4301 struct brw_reg flag
= brw_flag_reg(0, 0);
4302 /* FIXME: For SIMD32 programs, this causes us to stomp on f0.1 as well
4303 * as f0.0. This is a problem for fragment programs as we currently use
4304 * f0.1 for discards. Fortunately, we don't support SIMD32 fragment
4305 * programs yet so this isn't a problem. When we do, something will
4308 if (dispatch_width
== 32)
4309 flag
.type
= BRW_REGISTER_TYPE_UD
;
4311 bld
.exec_all().group(1, 0).MOV(flag
, brw_imm_ud(0u));
4312 bld
.CMP(bld
.null_reg_ud(), value
, brw_imm_ud(0u), BRW_CONDITIONAL_NZ
);
4314 if (instr
->dest
.ssa
.bit_size
> 32) {
4315 dest
.type
= BRW_REGISTER_TYPE_UQ
;
4317 dest
.type
= BRW_REGISTER_TYPE_UD
;
4319 bld
.MOV(dest
, flag
);
4323 case nir_intrinsic_read_invocation
: {
4324 const fs_reg value
= get_nir_src(instr
->src
[0]);
4325 const fs_reg invocation
= get_nir_src(instr
->src
[1]);
4326 fs_reg tmp
= bld
.vgrf(value
.type
);
4328 bld
.exec_all().emit(SHADER_OPCODE_BROADCAST
, tmp
, value
,
4329 bld
.emit_uniformize(invocation
));
4331 bld
.MOV(retype(dest
, value
.type
), fs_reg(component(tmp
, 0)));
4335 case nir_intrinsic_read_first_invocation
: {
4336 const fs_reg value
= get_nir_src(instr
->src
[0]);
4337 bld
.MOV(retype(dest
, value
.type
), bld
.emit_uniformize(value
));
4342 unreachable("unknown intrinsic");
4347 fs_visitor::nir_emit_ssbo_atomic(const fs_builder
&bld
,
4348 int op
, nir_intrinsic_instr
*instr
)
4350 if (stage
== MESA_SHADER_FRAGMENT
)
4351 brw_wm_prog_data(prog_data
)->has_side_effects
= true;
4354 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
4355 dest
= get_nir_dest(instr
->dest
);
4358 nir_const_value
*const_surface
= nir_src_as_const_value(instr
->src
[0]);
4359 if (const_surface
) {
4360 unsigned surf_index
= stage_prog_data
->binding_table
.ssbo_start
+
4361 const_surface
->u32
[0];
4362 surface
= brw_imm_ud(surf_index
);
4363 brw_mark_surface_used(prog_data
, surf_index
);
4365 surface
= vgrf(glsl_type::uint_type
);
4366 bld
.ADD(surface
, get_nir_src(instr
->src
[0]),
4367 brw_imm_ud(stage_prog_data
->binding_table
.ssbo_start
));
4369 /* Assume this may touch any SSBO. This is the same we do for other
4370 * UBO/SSBO accesses with non-constant surface.
4372 brw_mark_surface_used(prog_data
,
4373 stage_prog_data
->binding_table
.ssbo_start
+
4374 nir
->info
.num_ssbos
- 1);
4377 fs_reg offset
= get_nir_src(instr
->src
[1]);
4378 fs_reg data1
= get_nir_src(instr
->src
[2]);
4380 if (op
== BRW_AOP_CMPWR
)
4381 data2
= get_nir_src(instr
->src
[3]);
4383 /* Emit the actual atomic operation */
4385 fs_reg atomic_result
= emit_untyped_atomic(bld
, surface
, offset
,
4387 1 /* dims */, 1 /* rsize */,
4389 BRW_PREDICATE_NONE
);
4390 dest
.type
= atomic_result
.type
;
4391 bld
.MOV(dest
, atomic_result
);
4395 fs_visitor::nir_emit_shared_atomic(const fs_builder
&bld
,
4396 int op
, nir_intrinsic_instr
*instr
)
4399 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
4400 dest
= get_nir_dest(instr
->dest
);
4402 fs_reg surface
= brw_imm_ud(GEN7_BTI_SLM
);
4404 fs_reg data1
= get_nir_src(instr
->src
[1]);
4406 if (op
== BRW_AOP_CMPWR
)
4407 data2
= get_nir_src(instr
->src
[2]);
4409 /* Get the offset */
4410 nir_const_value
*const_offset
= nir_src_as_const_value(instr
->src
[0]);
4412 offset
= brw_imm_ud(instr
->const_index
[0] + const_offset
->u32
[0]);
4414 offset
= vgrf(glsl_type::uint_type
);
4416 retype(get_nir_src(instr
->src
[0]), BRW_REGISTER_TYPE_UD
),
4417 brw_imm_ud(instr
->const_index
[0]));
4420 /* Emit the actual atomic operation operation */
4422 fs_reg atomic_result
= emit_untyped_atomic(bld
, surface
, offset
,
4424 1 /* dims */, 1 /* rsize */,
4426 BRW_PREDICATE_NONE
);
4427 dest
.type
= atomic_result
.type
;
4428 bld
.MOV(dest
, atomic_result
);
4432 fs_visitor::nir_emit_texture(const fs_builder
&bld
, nir_tex_instr
*instr
)
4434 unsigned texture
= instr
->texture_index
;
4435 unsigned sampler
= instr
->sampler_index
;
4437 fs_reg srcs
[TEX_LOGICAL_NUM_SRCS
];
4439 srcs
[TEX_LOGICAL_SRC_SURFACE
] = brw_imm_ud(texture
);
4440 srcs
[TEX_LOGICAL_SRC_SAMPLER
] = brw_imm_ud(sampler
);
4442 int lod_components
= 0;
4444 /* The hardware requires a LOD for buffer textures */
4445 if (instr
->sampler_dim
== GLSL_SAMPLER_DIM_BUF
)
4446 srcs
[TEX_LOGICAL_SRC_LOD
] = brw_imm_d(0);
4448 uint32_t header_bits
= 0;
4449 for (unsigned i
= 0; i
< instr
->num_srcs
; i
++) {
4450 fs_reg src
= get_nir_src(instr
->src
[i
].src
);
4451 switch (instr
->src
[i
].src_type
) {
4452 case nir_tex_src_bias
:
4453 srcs
[TEX_LOGICAL_SRC_LOD
] =
4454 retype(get_nir_src_imm(instr
->src
[i
].src
), BRW_REGISTER_TYPE_F
);
4456 case nir_tex_src_comparator
:
4457 srcs
[TEX_LOGICAL_SRC_SHADOW_C
] = retype(src
, BRW_REGISTER_TYPE_F
);
4459 case nir_tex_src_coord
:
4460 switch (instr
->op
) {
4462 case nir_texop_txf_ms
:
4463 case nir_texop_txf_ms_mcs
:
4464 case nir_texop_samples_identical
:
4465 srcs
[TEX_LOGICAL_SRC_COORDINATE
] = retype(src
, BRW_REGISTER_TYPE_D
);
4468 srcs
[TEX_LOGICAL_SRC_COORDINATE
] = retype(src
, BRW_REGISTER_TYPE_F
);
4472 case nir_tex_src_ddx
:
4473 srcs
[TEX_LOGICAL_SRC_LOD
] = retype(src
, BRW_REGISTER_TYPE_F
);
4474 lod_components
= nir_tex_instr_src_size(instr
, i
);
4476 case nir_tex_src_ddy
:
4477 srcs
[TEX_LOGICAL_SRC_LOD2
] = retype(src
, BRW_REGISTER_TYPE_F
);
4479 case nir_tex_src_lod
:
4480 switch (instr
->op
) {
4482 srcs
[TEX_LOGICAL_SRC_LOD
] =
4483 retype(get_nir_src_imm(instr
->src
[i
].src
), BRW_REGISTER_TYPE_UD
);
4486 srcs
[TEX_LOGICAL_SRC_LOD
] =
4487 retype(get_nir_src_imm(instr
->src
[i
].src
), BRW_REGISTER_TYPE_D
);
4490 srcs
[TEX_LOGICAL_SRC_LOD
] =
4491 retype(get_nir_src_imm(instr
->src
[i
].src
), BRW_REGISTER_TYPE_F
);
4495 case nir_tex_src_ms_index
:
4496 srcs
[TEX_LOGICAL_SRC_SAMPLE_INDEX
] = retype(src
, BRW_REGISTER_TYPE_UD
);
4499 case nir_tex_src_offset
: {
4500 nir_const_value
*const_offset
=
4501 nir_src_as_const_value(instr
->src
[i
].src
);
4502 unsigned offset_bits
= 0;
4504 brw_texture_offset(const_offset
->i32
,
4505 nir_tex_instr_src_size(instr
, i
),
4507 header_bits
|= offset_bits
;
4509 srcs
[TEX_LOGICAL_SRC_TG4_OFFSET
] =
4510 retype(src
, BRW_REGISTER_TYPE_D
);
4515 case nir_tex_src_projector
:
4516 unreachable("should be lowered");
4518 case nir_tex_src_texture_offset
: {
4519 /* Figure out the highest possible texture index and mark it as used */
4520 uint32_t max_used
= texture
+ instr
->texture_array_size
- 1;
4521 if (instr
->op
== nir_texop_tg4
&& devinfo
->gen
< 8) {
4522 max_used
+= stage_prog_data
->binding_table
.gather_texture_start
;
4524 max_used
+= stage_prog_data
->binding_table
.texture_start
;
4526 brw_mark_surface_used(prog_data
, max_used
);
4528 /* Emit code to evaluate the actual indexing expression */
4529 fs_reg tmp
= vgrf(glsl_type::uint_type
);
4530 bld
.ADD(tmp
, src
, brw_imm_ud(texture
));
4531 srcs
[TEX_LOGICAL_SRC_SURFACE
] = bld
.emit_uniformize(tmp
);
4535 case nir_tex_src_sampler_offset
: {
4536 /* Emit code to evaluate the actual indexing expression */
4537 fs_reg tmp
= vgrf(glsl_type::uint_type
);
4538 bld
.ADD(tmp
, src
, brw_imm_ud(sampler
));
4539 srcs
[TEX_LOGICAL_SRC_SAMPLER
] = bld
.emit_uniformize(tmp
);
4543 case nir_tex_src_ms_mcs
:
4544 assert(instr
->op
== nir_texop_txf_ms
);
4545 srcs
[TEX_LOGICAL_SRC_MCS
] = retype(src
, BRW_REGISTER_TYPE_D
);
4548 case nir_tex_src_plane
: {
4549 nir_const_value
*const_plane
=
4550 nir_src_as_const_value(instr
->src
[i
].src
);
4551 const uint32_t plane
= const_plane
->u32
[0];
4552 const uint32_t texture_index
=
4553 instr
->texture_index
+
4554 stage_prog_data
->binding_table
.plane_start
[plane
] -
4555 stage_prog_data
->binding_table
.texture_start
;
4557 srcs
[TEX_LOGICAL_SRC_SURFACE
] = brw_imm_ud(texture_index
);
4562 unreachable("unknown texture source");
4566 if (srcs
[TEX_LOGICAL_SRC_MCS
].file
== BAD_FILE
&&
4567 (instr
->op
== nir_texop_txf_ms
||
4568 instr
->op
== nir_texop_samples_identical
)) {
4569 if (devinfo
->gen
>= 7 &&
4570 key_tex
->compressed_multisample_layout_mask
& (1 << texture
)) {
4571 srcs
[TEX_LOGICAL_SRC_MCS
] =
4572 emit_mcs_fetch(srcs
[TEX_LOGICAL_SRC_COORDINATE
],
4573 instr
->coord_components
,
4574 srcs
[TEX_LOGICAL_SRC_SURFACE
]);
4576 srcs
[TEX_LOGICAL_SRC_MCS
] = brw_imm_ud(0u);
4580 srcs
[TEX_LOGICAL_SRC_COORD_COMPONENTS
] = brw_imm_d(instr
->coord_components
);
4581 srcs
[TEX_LOGICAL_SRC_GRAD_COMPONENTS
] = brw_imm_d(lod_components
);
4584 switch (instr
->op
) {
4586 opcode
= (stage
== MESA_SHADER_FRAGMENT
? SHADER_OPCODE_TEX_LOGICAL
:
4587 SHADER_OPCODE_TXL_LOGICAL
);
4590 opcode
= FS_OPCODE_TXB_LOGICAL
;
4593 opcode
= SHADER_OPCODE_TXL_LOGICAL
;
4596 opcode
= SHADER_OPCODE_TXD_LOGICAL
;
4599 opcode
= SHADER_OPCODE_TXF_LOGICAL
;
4601 case nir_texop_txf_ms
:
4602 if ((key_tex
->msaa_16
& (1 << sampler
)))
4603 opcode
= SHADER_OPCODE_TXF_CMS_W_LOGICAL
;
4605 opcode
= SHADER_OPCODE_TXF_CMS_LOGICAL
;
4607 case nir_texop_txf_ms_mcs
:
4608 opcode
= SHADER_OPCODE_TXF_MCS_LOGICAL
;
4610 case nir_texop_query_levels
:
4612 opcode
= SHADER_OPCODE_TXS_LOGICAL
;
4615 opcode
= SHADER_OPCODE_LOD_LOGICAL
;
4618 if (srcs
[TEX_LOGICAL_SRC_TG4_OFFSET
].file
!= BAD_FILE
)
4619 opcode
= SHADER_OPCODE_TG4_OFFSET_LOGICAL
;
4621 opcode
= SHADER_OPCODE_TG4_LOGICAL
;
4623 case nir_texop_texture_samples
:
4624 opcode
= SHADER_OPCODE_SAMPLEINFO_LOGICAL
;
4626 case nir_texop_samples_identical
: {
4627 fs_reg dst
= retype(get_nir_dest(instr
->dest
), BRW_REGISTER_TYPE_D
);
4629 /* If mcs is an immediate value, it means there is no MCS. In that case
4630 * just return false.
4632 if (srcs
[TEX_LOGICAL_SRC_MCS
].file
== BRW_IMMEDIATE_VALUE
) {
4633 bld
.MOV(dst
, brw_imm_ud(0u));
4634 } else if ((key_tex
->msaa_16
& (1 << sampler
))) {
4635 fs_reg tmp
= vgrf(glsl_type::uint_type
);
4636 bld
.OR(tmp
, srcs
[TEX_LOGICAL_SRC_MCS
],
4637 offset(srcs
[TEX_LOGICAL_SRC_MCS
], bld
, 1));
4638 bld
.CMP(dst
, tmp
, brw_imm_ud(0u), BRW_CONDITIONAL_EQ
);
4640 bld
.CMP(dst
, srcs
[TEX_LOGICAL_SRC_MCS
], brw_imm_ud(0u),
4641 BRW_CONDITIONAL_EQ
);
4646 unreachable("unknown texture opcode");
4649 if (instr
->op
== nir_texop_tg4
) {
4650 if (instr
->component
== 1 &&
4651 key_tex
->gather_channel_quirk_mask
& (1 << texture
)) {
4652 /* gather4 sampler is broken for green channel on RG32F --
4653 * we must ask for blue instead.
4655 header_bits
|= 2 << 16;
4657 header_bits
|= instr
->component
<< 16;
4661 fs_reg dst
= bld
.vgrf(brw_type_for_nir_type(devinfo
, instr
->dest_type
), 4);
4662 fs_inst
*inst
= bld
.emit(opcode
, dst
, srcs
, ARRAY_SIZE(srcs
));
4663 inst
->offset
= header_bits
;
4665 const unsigned dest_size
= nir_tex_instr_dest_size(instr
);
4666 if (devinfo
->gen
>= 9 &&
4667 instr
->op
!= nir_texop_tg4
&& instr
->op
!= nir_texop_query_levels
) {
4668 unsigned write_mask
= instr
->dest
.is_ssa
?
4669 nir_ssa_def_components_read(&instr
->dest
.ssa
):
4670 (1 << dest_size
) - 1;
4671 assert(write_mask
!= 0); /* dead code should have been eliminated */
4672 inst
->size_written
= util_last_bit(write_mask
) *
4673 inst
->dst
.component_size(inst
->exec_size
);
4675 inst
->size_written
= 4 * inst
->dst
.component_size(inst
->exec_size
);
4678 if (srcs
[TEX_LOGICAL_SRC_SHADOW_C
].file
!= BAD_FILE
)
4679 inst
->shadow_compare
= true;
4681 if (instr
->op
== nir_texop_tg4
&& devinfo
->gen
== 6)
4682 emit_gen6_gather_wa(key_tex
->gen6_gather_wa
[texture
], dst
);
4685 for (unsigned i
= 0; i
< dest_size
; i
++)
4686 nir_dest
[i
] = offset(dst
, bld
, i
);
4688 if (instr
->op
== nir_texop_query_levels
) {
4689 /* # levels is in .w */
4690 nir_dest
[0] = offset(dst
, bld
, 3);
4691 } else if (instr
->op
== nir_texop_txs
&&
4692 dest_size
>= 3 && devinfo
->gen
< 7) {
4693 /* Gen4-6 return 0 instead of 1 for single layer surfaces. */
4694 fs_reg depth
= offset(dst
, bld
, 2);
4695 nir_dest
[2] = vgrf(glsl_type::int_type
);
4696 bld
.emit_minmax(nir_dest
[2], depth
, brw_imm_d(1), BRW_CONDITIONAL_GE
);
4699 bld
.LOAD_PAYLOAD(get_nir_dest(instr
->dest
), nir_dest
, dest_size
, 0);
4703 fs_visitor::nir_emit_jump(const fs_builder
&bld
, nir_jump_instr
*instr
)
4705 switch (instr
->type
) {
4706 case nir_jump_break
:
4707 bld
.emit(BRW_OPCODE_BREAK
);
4709 case nir_jump_continue
:
4710 bld
.emit(BRW_OPCODE_CONTINUE
);
4712 case nir_jump_return
:
4714 unreachable("unknown jump");
4719 * This helper takes the result of a load operation that reads 32-bit elements
4727 * and shuffles the data to get this:
4734 * Which is exactly what we want if the load is reading 64-bit components
4735 * like doubles, where x represents the low 32-bit of the x double component
4736 * and y represents the high 32-bit of the x double component (likewise with
4737 * z and w for double component y). The parameter @components represents
4738 * the number of 64-bit components present in @src. This would typically be
4739 * 2 at most, since we can only fit 2 double elements in the result of a
4742 * Notice that @dst and @src can be the same register.
4745 shuffle_32bit_load_result_to_64bit_data(const fs_builder
&bld
,
4748 uint32_t components
)
4750 assert(type_sz(src
.type
) == 4);
4751 assert(type_sz(dst
.type
) == 8);
4753 /* A temporary that we will use to shuffle the 32-bit data of each
4754 * component in the vector into valid 64-bit data. We can't write directly
4755 * to dst because dst can be (and would usually be) the same as src
4756 * and in that case the first MOV in the loop below would overwrite the
4757 * data read in the second MOV.
4759 fs_reg tmp
= bld
.vgrf(dst
.type
);
4761 for (unsigned i
= 0; i
< components
; i
++) {
4762 const fs_reg component_i
= offset(src
, bld
, 2 * i
);
4764 bld
.MOV(subscript(tmp
, src
.type
, 0), component_i
);
4765 bld
.MOV(subscript(tmp
, src
.type
, 1), offset(component_i
, bld
, 1));
4767 bld
.MOV(offset(dst
, bld
, i
), tmp
);
4772 * This helper does the inverse operation of
4773 * SHUFFLE_32BIT_LOAD_RESULT_TO_64BIT_DATA.
4775 * We need to do this when we are going to use untyped write messsages that
4776 * operate with 32-bit components in order to arrange our 64-bit data to be
4777 * in the expected layout.
4779 * Notice that callers of this function, unlike in the case of the inverse
4780 * operation, would typically need to call this with dst and src being
4781 * different registers, since they would otherwise corrupt the original
4782 * 64-bit data they are about to write. Because of this the function checks
4783 * that the src and dst regions involved in the operation do not overlap.
4786 shuffle_64bit_data_for_32bit_write(const fs_builder
&bld
,
4788 uint32_t components
)
4790 assert(type_sz(src
.type
) == 8);
4792 fs_reg dst
= bld
.vgrf(BRW_REGISTER_TYPE_D
, 2 * components
);
4794 for (unsigned i
= 0; i
< components
; i
++) {
4795 const fs_reg component_i
= offset(src
, bld
, i
);
4796 bld
.MOV(offset(dst
, bld
, 2 * i
), subscript(component_i
, dst
.type
, 0));
4797 bld
.MOV(offset(dst
, bld
, 2 * i
+ 1), subscript(component_i
, dst
.type
, 1));
4804 setup_imm_df(const fs_builder
&bld
, double v
)
4806 const struct gen_device_info
*devinfo
= bld
.shader
->devinfo
;
4807 assert(devinfo
->gen
>= 7);
4809 if (devinfo
->gen
>= 8)
4810 return brw_imm_df(v
);
4812 /* gen7.5 does not support DF immediates straighforward but the DIM
4813 * instruction allows to set the 64-bit immediate value.
4815 if (devinfo
->is_haswell
) {
4816 const fs_builder ubld
= bld
.exec_all().group(1, 0);
4817 fs_reg dst
= ubld
.vgrf(BRW_REGISTER_TYPE_DF
, 1);
4818 ubld
.DIM(dst
, brw_imm_df(v
));
4819 return component(dst
, 0);
4822 /* gen7 does not support DF immediates, so we generate a 64-bit constant by
4823 * writing the low 32-bit of the constant to suboffset 0 of a VGRF and
4824 * the high 32-bit to suboffset 4 and then applying a stride of 0.
4826 * Alternatively, we could also produce a normal VGRF (without stride 0)
4827 * by writing to all the channels in the VGRF, however, that would hit the
4828 * gen7 bug where we have to split writes that span more than 1 register
4829 * into instructions with a width of 4 (otherwise the write to the second
4830 * register written runs into an execmask hardware bug) which isn't very
4843 const fs_builder ubld
= bld
.exec_all().group(1, 0);
4844 const fs_reg tmp
= ubld
.vgrf(BRW_REGISTER_TYPE_UD
, 2);
4845 ubld
.MOV(tmp
, brw_imm_ud(di
.i1
));
4846 ubld
.MOV(horiz_offset(tmp
, 1), brw_imm_ud(di
.i2
));
4848 return component(retype(tmp
, BRW_REGISTER_TYPE_DF
), 0);