2 * Copyright © 2010 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 #include "compiler/glsl/ir.h"
27 #include "util/u_math.h"
28 #include "util/bitscan.h"
33 fs_visitor::emit_nir_code()
35 /* emit the arrays used for inputs and outputs - load/store intrinsics will
36 * be converted to reads/writes of these arrays
40 nir_emit_system_values();
42 nir_emit_impl(nir_shader_get_entrypoint((nir_shader
*)nir
));
46 fs_visitor::nir_setup_outputs()
48 if (stage
== MESA_SHADER_TESS_CTRL
|| stage
== MESA_SHADER_FRAGMENT
)
51 unsigned vec4s
[VARYING_SLOT_TESS_MAX
] = { 0, };
53 /* Calculate the size of output registers in a separate pass, before
54 * allocating them. With ARB_enhanced_layouts, multiple output variables
55 * may occupy the same slot, but have different type sizes.
57 nir_foreach_variable(var
, &nir
->outputs
) {
58 const int loc
= var
->data
.driver_location
;
59 const unsigned var_vec4s
=
60 var
->data
.compact
? DIV_ROUND_UP(glsl_get_length(var
->type
), 4)
61 : type_size_vec4(var
->type
);
62 vec4s
[loc
] = MAX2(vec4s
[loc
], var_vec4s
);
65 for (unsigned loc
= 0; loc
< ARRAY_SIZE(vec4s
);) {
66 if (vec4s
[loc
] == 0) {
71 unsigned reg_size
= vec4s
[loc
];
73 /* Check if there are any ranges that start within this range and extend
74 * past it. If so, include them in this allocation.
76 for (unsigned i
= 1; i
< reg_size
; i
++)
77 reg_size
= MAX2(vec4s
[i
+ loc
] + i
, reg_size
);
79 fs_reg reg
= bld
.vgrf(BRW_REGISTER_TYPE_F
, 4 * reg_size
);
80 for (unsigned i
= 0; i
< reg_size
; i
++)
81 outputs
[loc
+ i
] = offset(reg
, bld
, 4 * i
);
88 fs_visitor::nir_setup_uniforms()
90 /* Only the first compile gets to set up uniforms. */
91 if (push_constant_loc
) {
92 assert(pull_constant_loc
);
96 uniforms
= nir
->num_uniforms
/ 4;
98 if (stage
== MESA_SHADER_COMPUTE
) {
99 /* Add a uniform for the thread local id. It must be the last uniform
102 assert(uniforms
== prog_data
->nr_params
);
103 uint32_t *param
= brw_stage_prog_data_add_params(prog_data
, 1);
104 *param
= BRW_PARAM_BUILTIN_SUBGROUP_ID
;
105 subgroup_id
= fs_reg(UNIFORM
, uniforms
++, BRW_REGISTER_TYPE_UD
);
110 emit_system_values_block(nir_block
*block
, fs_visitor
*v
)
114 nir_foreach_instr(instr
, block
) {
115 if (instr
->type
!= nir_instr_type_intrinsic
)
118 nir_intrinsic_instr
*intrin
= nir_instr_as_intrinsic(instr
);
119 switch (intrin
->intrinsic
) {
120 case nir_intrinsic_load_vertex_id
:
121 case nir_intrinsic_load_base_vertex
:
122 unreachable("should be lowered by nir_lower_system_values().");
124 case nir_intrinsic_load_vertex_id_zero_base
:
125 case nir_intrinsic_load_is_indexed_draw
:
126 case nir_intrinsic_load_first_vertex
:
127 case nir_intrinsic_load_instance_id
:
128 case nir_intrinsic_load_base_instance
:
129 case nir_intrinsic_load_draw_id
:
130 unreachable("should be lowered by brw_nir_lower_vs_inputs().");
132 case nir_intrinsic_load_invocation_id
:
133 if (v
->stage
== MESA_SHADER_TESS_CTRL
)
135 assert(v
->stage
== MESA_SHADER_GEOMETRY
);
136 reg
= &v
->nir_system_values
[SYSTEM_VALUE_INVOCATION_ID
];
137 if (reg
->file
== BAD_FILE
) {
138 const fs_builder abld
= v
->bld
.annotate("gl_InvocationID", NULL
);
139 fs_reg
g1(retype(brw_vec8_grf(1, 0), BRW_REGISTER_TYPE_UD
));
140 fs_reg iid
= abld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
141 abld
.SHR(iid
, g1
, brw_imm_ud(27u));
146 case nir_intrinsic_load_sample_pos
:
147 assert(v
->stage
== MESA_SHADER_FRAGMENT
);
148 reg
= &v
->nir_system_values
[SYSTEM_VALUE_SAMPLE_POS
];
149 if (reg
->file
== BAD_FILE
)
150 *reg
= *v
->emit_samplepos_setup();
153 case nir_intrinsic_load_sample_id
:
154 assert(v
->stage
== MESA_SHADER_FRAGMENT
);
155 reg
= &v
->nir_system_values
[SYSTEM_VALUE_SAMPLE_ID
];
156 if (reg
->file
== BAD_FILE
)
157 *reg
= *v
->emit_sampleid_setup();
160 case nir_intrinsic_load_sample_mask_in
:
161 assert(v
->stage
== MESA_SHADER_FRAGMENT
);
162 assert(v
->devinfo
->gen
>= 7);
163 reg
= &v
->nir_system_values
[SYSTEM_VALUE_SAMPLE_MASK_IN
];
164 if (reg
->file
== BAD_FILE
)
165 *reg
= *v
->emit_samplemaskin_setup();
168 case nir_intrinsic_load_work_group_id
:
169 assert(v
->stage
== MESA_SHADER_COMPUTE
);
170 reg
= &v
->nir_system_values
[SYSTEM_VALUE_WORK_GROUP_ID
];
171 if (reg
->file
== BAD_FILE
)
172 *reg
= *v
->emit_cs_work_group_id_setup();
175 case nir_intrinsic_load_helper_invocation
:
176 assert(v
->stage
== MESA_SHADER_FRAGMENT
);
177 reg
= &v
->nir_system_values
[SYSTEM_VALUE_HELPER_INVOCATION
];
178 if (reg
->file
== BAD_FILE
) {
179 const fs_builder abld
=
180 v
->bld
.annotate("gl_HelperInvocation", NULL
);
182 /* On Gen6+ (gl_HelperInvocation is only exposed on Gen7+) the
183 * pixel mask is in g1.7 of the thread payload.
185 * We move the per-channel pixel enable bit to the low bit of each
186 * channel by shifting the byte containing the pixel mask by the
187 * vector immediate 0x76543210UV.
189 * The region of <1,8,0> reads only 1 byte (the pixel masks for
190 * subspans 0 and 1) in SIMD8 and an additional byte (the pixel
191 * masks for 2 and 3) in SIMD16.
193 fs_reg shifted
= abld
.vgrf(BRW_REGISTER_TYPE_UW
, 1);
195 for (unsigned i
= 0; i
< DIV_ROUND_UP(v
->dispatch_width
, 16); i
++) {
196 const fs_builder hbld
= abld
.group(MIN2(16, v
->dispatch_width
), i
);
197 hbld
.SHR(offset(shifted
, hbld
, i
),
198 stride(retype(brw_vec1_grf(1 + i
, 7),
199 BRW_REGISTER_TYPE_UB
),
201 brw_imm_v(0x76543210));
204 /* A set bit in the pixel mask means the channel is enabled, but
205 * that is the opposite of gl_HelperInvocation so we need to invert
208 * The negate source-modifier bit of logical instructions on Gen8+
209 * performs 1's complement negation, so we can use that instead of
212 fs_reg inverted
= negate(shifted
);
213 if (v
->devinfo
->gen
< 8) {
214 inverted
= abld
.vgrf(BRW_REGISTER_TYPE_UW
);
215 abld
.NOT(inverted
, shifted
);
218 /* We then resolve the 0/1 result to 0/~0 boolean values by ANDing
219 * with 1 and negating.
221 fs_reg anded
= abld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
222 abld
.AND(anded
, inverted
, brw_imm_uw(1));
224 fs_reg dst
= abld
.vgrf(BRW_REGISTER_TYPE_D
, 1);
225 abld
.MOV(dst
, negate(retype(anded
, BRW_REGISTER_TYPE_D
)));
239 fs_visitor::nir_emit_system_values()
241 nir_system_values
= ralloc_array(mem_ctx
, fs_reg
, SYSTEM_VALUE_MAX
);
242 for (unsigned i
= 0; i
< SYSTEM_VALUE_MAX
; i
++) {
243 nir_system_values
[i
] = fs_reg();
246 /* Always emit SUBGROUP_INVOCATION. Dead code will clean it up if we
247 * never end up using it.
250 const fs_builder abld
= bld
.annotate("gl_SubgroupInvocation", NULL
);
251 fs_reg
®
= nir_system_values
[SYSTEM_VALUE_SUBGROUP_INVOCATION
];
252 reg
= abld
.vgrf(BRW_REGISTER_TYPE_UW
);
254 const fs_builder allbld8
= abld
.group(8, 0).exec_all();
255 allbld8
.MOV(reg
, brw_imm_v(0x76543210));
256 if (dispatch_width
> 8)
257 allbld8
.ADD(byte_offset(reg
, 16), reg
, brw_imm_uw(8u));
258 if (dispatch_width
> 16) {
259 const fs_builder allbld16
= abld
.group(16, 0).exec_all();
260 allbld16
.ADD(byte_offset(reg
, 32), reg
, brw_imm_uw(16u));
264 nir_function_impl
*impl
= nir_shader_get_entrypoint((nir_shader
*)nir
);
265 nir_foreach_block(block
, impl
)
266 emit_system_values_block(block
, this);
270 * Returns a type based on a reference_type (word, float, half-float) and a
273 * Reference BRW_REGISTER_TYPE are HF,F,DF,W,D,UW,UD.
275 * @FIXME: 64-bit return types are always DF on integer types to maintain
276 * compability with uses of DF previously to the introduction of int64
280 brw_reg_type_from_bit_size(const unsigned bit_size
,
281 const brw_reg_type reference_type
)
283 switch(reference_type
) {
284 case BRW_REGISTER_TYPE_HF
:
285 case BRW_REGISTER_TYPE_F
:
286 case BRW_REGISTER_TYPE_DF
:
289 return BRW_REGISTER_TYPE_HF
;
291 return BRW_REGISTER_TYPE_F
;
293 return BRW_REGISTER_TYPE_DF
;
295 unreachable("Invalid bit size");
297 case BRW_REGISTER_TYPE_B
:
298 case BRW_REGISTER_TYPE_W
:
299 case BRW_REGISTER_TYPE_D
:
300 case BRW_REGISTER_TYPE_Q
:
303 return BRW_REGISTER_TYPE_B
;
305 return BRW_REGISTER_TYPE_W
;
307 return BRW_REGISTER_TYPE_D
;
309 return BRW_REGISTER_TYPE_Q
;
311 unreachable("Invalid bit size");
313 case BRW_REGISTER_TYPE_UB
:
314 case BRW_REGISTER_TYPE_UW
:
315 case BRW_REGISTER_TYPE_UD
:
316 case BRW_REGISTER_TYPE_UQ
:
319 return BRW_REGISTER_TYPE_UB
;
321 return BRW_REGISTER_TYPE_UW
;
323 return BRW_REGISTER_TYPE_UD
;
325 return BRW_REGISTER_TYPE_UQ
;
327 unreachable("Invalid bit size");
330 unreachable("Unknown type");
335 fs_visitor::nir_emit_impl(nir_function_impl
*impl
)
337 nir_locals
= ralloc_array(mem_ctx
, fs_reg
, impl
->reg_alloc
);
338 for (unsigned i
= 0; i
< impl
->reg_alloc
; i
++) {
339 nir_locals
[i
] = fs_reg();
342 foreach_list_typed(nir_register
, reg
, node
, &impl
->registers
) {
343 unsigned array_elems
=
344 reg
->num_array_elems
== 0 ? 1 : reg
->num_array_elems
;
345 unsigned size
= array_elems
* reg
->num_components
;
346 const brw_reg_type reg_type
=
347 brw_reg_type_from_bit_size(reg
->bit_size
, BRW_REGISTER_TYPE_F
);
348 nir_locals
[reg
->index
] = bld
.vgrf(reg_type
, size
);
351 nir_ssa_values
= reralloc(mem_ctx
, nir_ssa_values
, fs_reg
,
354 nir_emit_cf_list(&impl
->body
);
358 fs_visitor::nir_emit_cf_list(exec_list
*list
)
360 exec_list_validate(list
);
361 foreach_list_typed(nir_cf_node
, node
, node
, list
) {
362 switch (node
->type
) {
364 nir_emit_if(nir_cf_node_as_if(node
));
367 case nir_cf_node_loop
:
368 nir_emit_loop(nir_cf_node_as_loop(node
));
371 case nir_cf_node_block
:
372 nir_emit_block(nir_cf_node_as_block(node
));
376 unreachable("Invalid CFG node block");
382 fs_visitor::nir_emit_if(nir_if
*if_stmt
)
384 /* first, put the condition into f0 */
385 fs_inst
*inst
= bld
.MOV(bld
.null_reg_d(),
386 retype(get_nir_src(if_stmt
->condition
),
387 BRW_REGISTER_TYPE_D
));
388 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
390 bld
.IF(BRW_PREDICATE_NORMAL
);
392 nir_emit_cf_list(&if_stmt
->then_list
);
394 /* note: if the else is empty, dead CF elimination will remove it */
395 bld
.emit(BRW_OPCODE_ELSE
);
397 nir_emit_cf_list(&if_stmt
->else_list
);
399 bld
.emit(BRW_OPCODE_ENDIF
);
401 if (devinfo
->gen
< 7)
402 limit_dispatch_width(16, "Non-uniform control flow unsupported "
407 fs_visitor::nir_emit_loop(nir_loop
*loop
)
409 bld
.emit(BRW_OPCODE_DO
);
411 nir_emit_cf_list(&loop
->body
);
413 bld
.emit(BRW_OPCODE_WHILE
);
415 if (devinfo
->gen
< 7)
416 limit_dispatch_width(16, "Non-uniform control flow unsupported "
421 fs_visitor::nir_emit_block(nir_block
*block
)
423 nir_foreach_instr(instr
, block
) {
424 nir_emit_instr(instr
);
429 fs_visitor::nir_emit_instr(nir_instr
*instr
)
431 const fs_builder abld
= bld
.annotate(NULL
, instr
);
433 switch (instr
->type
) {
434 case nir_instr_type_alu
:
435 nir_emit_alu(abld
, nir_instr_as_alu(instr
));
438 case nir_instr_type_deref
:
439 /* Derefs can exist for images but they do nothing */
442 case nir_instr_type_intrinsic
:
444 case MESA_SHADER_VERTEX
:
445 nir_emit_vs_intrinsic(abld
, nir_instr_as_intrinsic(instr
));
447 case MESA_SHADER_TESS_CTRL
:
448 nir_emit_tcs_intrinsic(abld
, nir_instr_as_intrinsic(instr
));
450 case MESA_SHADER_TESS_EVAL
:
451 nir_emit_tes_intrinsic(abld
, nir_instr_as_intrinsic(instr
));
453 case MESA_SHADER_GEOMETRY
:
454 nir_emit_gs_intrinsic(abld
, nir_instr_as_intrinsic(instr
));
456 case MESA_SHADER_FRAGMENT
:
457 nir_emit_fs_intrinsic(abld
, nir_instr_as_intrinsic(instr
));
459 case MESA_SHADER_COMPUTE
:
460 nir_emit_cs_intrinsic(abld
, nir_instr_as_intrinsic(instr
));
463 unreachable("unsupported shader stage");
467 case nir_instr_type_tex
:
468 nir_emit_texture(abld
, nir_instr_as_tex(instr
));
471 case nir_instr_type_load_const
:
472 nir_emit_load_const(abld
, nir_instr_as_load_const(instr
));
475 case nir_instr_type_ssa_undef
:
476 /* We create a new VGRF for undefs on every use (by handling
477 * them in get_nir_src()), rather than for each definition.
478 * This helps register coalescing eliminate MOVs from undef.
482 case nir_instr_type_jump
:
483 nir_emit_jump(abld
, nir_instr_as_jump(instr
));
487 unreachable("unknown instruction type");
492 * Recognizes a parent instruction of nir_op_extract_* and changes the type to
496 fs_visitor::optimize_extract_to_float(nir_alu_instr
*instr
,
497 const fs_reg
&result
)
499 if (!instr
->src
[0].src
.is_ssa
||
500 !instr
->src
[0].src
.ssa
->parent_instr
)
503 if (instr
->src
[0].src
.ssa
->parent_instr
->type
!= nir_instr_type_alu
)
506 nir_alu_instr
*src0
=
507 nir_instr_as_alu(instr
->src
[0].src
.ssa
->parent_instr
);
509 if (src0
->op
!= nir_op_extract_u8
&& src0
->op
!= nir_op_extract_u16
&&
510 src0
->op
!= nir_op_extract_i8
&& src0
->op
!= nir_op_extract_i16
)
513 /* If either opcode has source modifiers, bail.
515 * TODO: We can potentially handle source modifiers if both of the opcodes
516 * we're combining are signed integers.
518 if (instr
->src
[0].abs
|| instr
->src
[0].negate
||
519 src0
->src
[0].abs
|| src0
->src
[0].negate
)
522 unsigned element
= nir_src_as_uint(src0
->src
[1].src
);
524 /* Element type to extract.*/
525 const brw_reg_type type
= brw_int_type(
526 src0
->op
== nir_op_extract_u16
|| src0
->op
== nir_op_extract_i16
? 2 : 1,
527 src0
->op
== nir_op_extract_i16
|| src0
->op
== nir_op_extract_i8
);
529 fs_reg op0
= get_nir_src(src0
->src
[0].src
);
530 op0
.type
= brw_type_for_nir_type(devinfo
,
531 (nir_alu_type
)(nir_op_infos
[src0
->op
].input_types
[0] |
532 nir_src_bit_size(src0
->src
[0].src
)));
533 op0
= offset(op0
, bld
, src0
->src
[0].swizzle
[0]);
535 set_saturate(instr
->dest
.saturate
,
536 bld
.MOV(result
, subscript(op0
, type
, element
)));
541 fs_visitor::optimize_frontfacing_ternary(nir_alu_instr
*instr
,
542 const fs_reg
&result
)
544 if (!instr
->src
[0].src
.is_ssa
||
545 instr
->src
[0].src
.ssa
->parent_instr
->type
!= nir_instr_type_intrinsic
)
548 nir_intrinsic_instr
*src0
=
549 nir_instr_as_intrinsic(instr
->src
[0].src
.ssa
->parent_instr
);
551 if (src0
->intrinsic
!= nir_intrinsic_load_front_face
)
554 if (!nir_src_is_const(instr
->src
[1].src
) ||
555 !nir_src_is_const(instr
->src
[2].src
))
558 const float value1
= nir_src_as_float(instr
->src
[1].src
);
559 const float value2
= nir_src_as_float(instr
->src
[2].src
);
560 if (fabsf(value1
) != 1.0f
|| fabsf(value2
) != 1.0f
)
563 /* nir_opt_algebraic should have gotten rid of bcsel(b, a, a) */
564 assert(value1
== -value2
);
566 fs_reg tmp
= vgrf(glsl_type::int_type
);
568 if (devinfo
->gen
>= 6) {
569 /* Bit 15 of g0.0 is 0 if the polygon is front facing. */
570 fs_reg g0
= fs_reg(retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_W
));
572 /* For (gl_FrontFacing ? 1.0 : -1.0), emit:
574 * or(8) tmp.1<2>W g0.0<0,1,0>W 0x00003f80W
575 * and(8) dst<1>D tmp<8,8,1>D 0xbf800000D
577 * and negate g0.0<0,1,0>W for (gl_FrontFacing ? -1.0 : 1.0).
579 * This negation looks like it's safe in practice, because bits 0:4 will
580 * surely be TRIANGLES
583 if (value1
== -1.0f
) {
587 bld
.OR(subscript(tmp
, BRW_REGISTER_TYPE_W
, 1),
588 g0
, brw_imm_uw(0x3f80));
590 /* Bit 31 of g1.6 is 0 if the polygon is front facing. */
591 fs_reg g1_6
= fs_reg(retype(brw_vec1_grf(1, 6), BRW_REGISTER_TYPE_D
));
593 /* For (gl_FrontFacing ? 1.0 : -1.0), emit:
595 * or(8) tmp<1>D g1.6<0,1,0>D 0x3f800000D
596 * and(8) dst<1>D tmp<8,8,1>D 0xbf800000D
598 * and negate g1.6<0,1,0>D for (gl_FrontFacing ? -1.0 : 1.0).
600 * This negation looks like it's safe in practice, because bits 0:4 will
601 * surely be TRIANGLES
604 if (value1
== -1.0f
) {
608 bld
.OR(tmp
, g1_6
, brw_imm_d(0x3f800000));
610 bld
.AND(retype(result
, BRW_REGISTER_TYPE_D
), tmp
, brw_imm_d(0xbf800000));
616 emit_find_msb_using_lzd(const fs_builder
&bld
,
617 const fs_reg
&result
,
625 /* LZD of an absolute value source almost always does the right
626 * thing. There are two problem values:
628 * * 0x80000000. Since abs(0x80000000) == 0x80000000, LZD returns
629 * 0. However, findMSB(int(0x80000000)) == 30.
631 * * 0xffffffff. Since abs(0xffffffff) == 1, LZD returns
632 * 31. Section 8.8 (Integer Functions) of the GLSL 4.50 spec says:
634 * For a value of zero or negative one, -1 will be returned.
636 * * Negative powers of two. LZD(abs(-(1<<x))) returns x, but
637 * findMSB(-(1<<x)) should return x-1.
639 * For all negative number cases, including 0x80000000 and
640 * 0xffffffff, the correct value is obtained from LZD if instead of
641 * negating the (already negative) value the logical-not is used. A
642 * conditonal logical-not can be achieved in two instructions.
644 temp
= bld
.vgrf(BRW_REGISTER_TYPE_D
);
646 bld
.ASR(temp
, src
, brw_imm_d(31));
647 bld
.XOR(temp
, temp
, src
);
650 bld
.LZD(retype(result
, BRW_REGISTER_TYPE_UD
),
651 retype(temp
, BRW_REGISTER_TYPE_UD
));
653 /* LZD counts from the MSB side, while GLSL's findMSB() wants the count
654 * from the LSB side. Subtract the result from 31 to convert the MSB
655 * count into an LSB count. If no bits are set, LZD will return 32.
656 * 31-32 = -1, which is exactly what findMSB() is supposed to return.
658 inst
= bld
.ADD(result
, retype(result
, BRW_REGISTER_TYPE_D
), brw_imm_d(31));
659 inst
->src
[0].negate
= true;
663 brw_rnd_mode_from_nir_op (const nir_op op
) {
665 case nir_op_f2f16_rtz
:
666 return BRW_RND_MODE_RTZ
;
667 case nir_op_f2f16_rtne
:
668 return BRW_RND_MODE_RTNE
;
670 unreachable("Operation doesn't support rounding mode");
675 fs_visitor::prepare_alu_destination_and_sources(const fs_builder
&bld
,
676 nir_alu_instr
*instr
,
681 need_dest
? get_nir_dest(instr
->dest
.dest
) : bld
.null_reg_ud();
683 result
.type
= brw_type_for_nir_type(devinfo
,
684 (nir_alu_type
)(nir_op_infos
[instr
->op
].output_type
|
685 nir_dest_bit_size(instr
->dest
.dest
)));
687 for (unsigned i
= 0; i
< nir_op_infos
[instr
->op
].num_inputs
; i
++) {
688 op
[i
] = get_nir_src(instr
->src
[i
].src
);
689 op
[i
].type
= brw_type_for_nir_type(devinfo
,
690 (nir_alu_type
)(nir_op_infos
[instr
->op
].input_types
[i
] |
691 nir_src_bit_size(instr
->src
[i
].src
)));
692 op
[i
].abs
= instr
->src
[i
].abs
;
693 op
[i
].negate
= instr
->src
[i
].negate
;
696 /* Move and vecN instrutions may still be vectored. Return the raw,
697 * vectored source and destination so that fs_visitor::nir_emit_alu can
698 * handle it. Other callers should not have to handle these kinds of
712 /* At this point, we have dealt with any instruction that operates on
713 * more than a single channel. Therefore, we can just adjust the source
714 * and destination registers for that channel and emit the instruction.
716 unsigned channel
= 0;
717 if (nir_op_infos
[instr
->op
].output_size
== 0) {
718 /* Since NIR is doing the scalarizing for us, we should only ever see
719 * vectorized operations with a single channel.
721 assert(util_bitcount(instr
->dest
.write_mask
) == 1);
722 channel
= ffs(instr
->dest
.write_mask
) - 1;
724 result
= offset(result
, bld
, channel
);
727 for (unsigned i
= 0; i
< nir_op_infos
[instr
->op
].num_inputs
; i
++) {
728 assert(nir_op_infos
[instr
->op
].input_sizes
[i
] < 2);
729 op
[i
] = offset(op
[i
], bld
, instr
->src
[i
].swizzle
[channel
]);
736 fs_visitor::resolve_inot_sources(const fs_builder
&bld
, nir_alu_instr
*instr
,
739 for (unsigned i
= 0; i
< 2; i
++) {
740 nir_alu_instr
*const inot_instr
=
741 nir_src_as_alu_instr(&instr
->src
[i
].src
);
743 if (inot_instr
!= NULL
&& inot_instr
->op
== nir_op_inot
&&
744 !inot_instr
->src
[0].abs
&& !inot_instr
->src
[0].negate
) {
745 /* The source of the inot is now the source of instr. */
746 prepare_alu_destination_and_sources(bld
, inot_instr
, &op
[i
], false);
748 assert(!op
[i
].negate
);
751 op
[i
] = resolve_source_modifiers(op
[i
]);
757 fs_visitor::nir_emit_alu(const fs_builder
&bld
, nir_alu_instr
*instr
)
759 struct brw_wm_prog_key
*fs_key
= (struct brw_wm_prog_key
*) this->key
;
763 fs_reg result
= prepare_alu_destination_and_sources(bld
, instr
, op
, true);
771 fs_reg temp
= result
;
772 bool need_extra_copy
= false;
773 for (unsigned i
= 0; i
< nir_op_infos
[instr
->op
].num_inputs
; i
++) {
774 if (!instr
->src
[i
].src
.is_ssa
&&
775 instr
->dest
.dest
.reg
.reg
== instr
->src
[i
].src
.reg
.reg
) {
776 need_extra_copy
= true;
777 temp
= bld
.vgrf(result
.type
, 4);
782 for (unsigned i
= 0; i
< 4; i
++) {
783 if (!(instr
->dest
.write_mask
& (1 << i
)))
786 if (instr
->op
== nir_op_imov
|| instr
->op
== nir_op_fmov
) {
787 inst
= bld
.MOV(offset(temp
, bld
, i
),
788 offset(op
[0], bld
, instr
->src
[0].swizzle
[i
]));
790 inst
= bld
.MOV(offset(temp
, bld
, i
),
791 offset(op
[i
], bld
, instr
->src
[i
].swizzle
[0]));
793 inst
->saturate
= instr
->dest
.saturate
;
796 /* In this case the source and destination registers were the same,
797 * so we need to insert an extra set of moves in order to deal with
800 if (need_extra_copy
) {
801 for (unsigned i
= 0; i
< 4; i
++) {
802 if (!(instr
->dest
.write_mask
& (1 << i
)))
805 bld
.MOV(offset(result
, bld
, i
), offset(temp
, bld
, i
));
813 if (optimize_extract_to_float(instr
, result
))
815 inst
= bld
.MOV(result
, op
[0]);
816 inst
->saturate
= instr
->dest
.saturate
;
819 case nir_op_f2f16_rtne
:
820 case nir_op_f2f16_rtz
:
821 bld
.emit(SHADER_OPCODE_RND_MODE
, bld
.null_reg_ud(),
822 brw_imm_d(brw_rnd_mode_from_nir_op(instr
->op
)));
825 /* In theory, it would be better to use BRW_OPCODE_F32TO16. Depending
826 * on the HW gen, it is a special hw opcode or just a MOV, and
827 * brw_F32TO16 (at brw_eu_emit) would do the work to chose.
829 * But if we want to use that opcode, we need to provide support on
830 * different optimizations and lowerings. As right now HF support is
831 * only for gen8+, it will be better to use directly the MOV, and use
832 * BRW_OPCODE_F32TO16 when/if we work for HF support on gen7.
836 inst
= bld
.MOV(result
, op
[0]);
837 inst
->saturate
= instr
->dest
.saturate
;
847 op
[0].type
= BRW_REGISTER_TYPE_D
;
848 op
[0].negate
= !op
[0].negate
;
870 inst
= bld
.MOV(result
, op
[0]);
871 inst
->saturate
= instr
->dest
.saturate
;
875 assert(!instr
->dest
.saturate
);
877 /* Straightforward since the source can be assumed to be either
878 * strictly >= 0 or strictly <= 0 depending on the setting of the
881 set_condmod(BRW_CONDITIONAL_NZ
, bld
.MOV(result
, op
[0]));
883 inst
= (op
[0].negate
)
884 ? bld
.MOV(result
, brw_imm_f(-1.0f
))
885 : bld
.MOV(result
, brw_imm_f(1.0f
));
887 set_predicate(BRW_PREDICATE_NORMAL
, inst
);
888 } else if (type_sz(op
[0].type
) < 8) {
889 /* AND(val, 0x80000000) gives the sign bit.
891 * Predicated OR ORs 1.0 (0x3f800000) with the sign bit if val is not
894 bld
.CMP(bld
.null_reg_f(), op
[0], brw_imm_f(0.0f
), BRW_CONDITIONAL_NZ
);
896 fs_reg result_int
= retype(result
, BRW_REGISTER_TYPE_UD
);
897 op
[0].type
= BRW_REGISTER_TYPE_UD
;
898 result
.type
= BRW_REGISTER_TYPE_UD
;
899 bld
.AND(result_int
, op
[0], brw_imm_ud(0x80000000u
));
901 inst
= bld
.OR(result_int
, result_int
, brw_imm_ud(0x3f800000u
));
902 inst
->predicate
= BRW_PREDICATE_NORMAL
;
904 /* For doubles we do the same but we need to consider:
906 * - 2-src instructions can't operate with 64-bit immediates
907 * - The sign is encoded in the high 32-bit of each DF
908 * - We need to produce a DF result.
911 fs_reg zero
= vgrf(glsl_type::double_type
);
912 bld
.MOV(zero
, setup_imm_df(bld
, 0.0));
913 bld
.CMP(bld
.null_reg_df(), op
[0], zero
, BRW_CONDITIONAL_NZ
);
915 bld
.MOV(result
, zero
);
917 fs_reg r
= subscript(result
, BRW_REGISTER_TYPE_UD
, 1);
918 bld
.AND(r
, subscript(op
[0], BRW_REGISTER_TYPE_UD
, 1),
919 brw_imm_ud(0x80000000u
));
921 set_predicate(BRW_PREDICATE_NORMAL
,
922 bld
.OR(r
, r
, brw_imm_ud(0x3ff00000u
)));
928 inst
= bld
.emit(SHADER_OPCODE_RCP
, result
, op
[0]);
929 inst
->saturate
= instr
->dest
.saturate
;
933 inst
= bld
.emit(SHADER_OPCODE_EXP2
, result
, op
[0]);
934 inst
->saturate
= instr
->dest
.saturate
;
938 inst
= bld
.emit(SHADER_OPCODE_LOG2
, result
, op
[0]);
939 inst
->saturate
= instr
->dest
.saturate
;
943 inst
= bld
.emit(SHADER_OPCODE_SIN
, result
, op
[0]);
944 inst
->saturate
= instr
->dest
.saturate
;
948 inst
= bld
.emit(SHADER_OPCODE_COS
, result
, op
[0]);
949 inst
->saturate
= instr
->dest
.saturate
;
953 if (fs_key
->high_quality_derivatives
) {
954 inst
= bld
.emit(FS_OPCODE_DDX_FINE
, result
, op
[0]);
956 inst
= bld
.emit(FS_OPCODE_DDX_COARSE
, result
, op
[0]);
958 inst
->saturate
= instr
->dest
.saturate
;
960 case nir_op_fddx_fine
:
961 inst
= bld
.emit(FS_OPCODE_DDX_FINE
, result
, op
[0]);
962 inst
->saturate
= instr
->dest
.saturate
;
964 case nir_op_fddx_coarse
:
965 inst
= bld
.emit(FS_OPCODE_DDX_COARSE
, result
, op
[0]);
966 inst
->saturate
= instr
->dest
.saturate
;
969 if (fs_key
->high_quality_derivatives
) {
970 inst
= bld
.emit(FS_OPCODE_DDY_FINE
, result
, op
[0]);
972 inst
= bld
.emit(FS_OPCODE_DDY_COARSE
, result
, op
[0]);
974 inst
->saturate
= instr
->dest
.saturate
;
976 case nir_op_fddy_fine
:
977 inst
= bld
.emit(FS_OPCODE_DDY_FINE
, result
, op
[0]);
978 inst
->saturate
= instr
->dest
.saturate
;
980 case nir_op_fddy_coarse
:
981 inst
= bld
.emit(FS_OPCODE_DDY_COARSE
, result
, op
[0]);
982 inst
->saturate
= instr
->dest
.saturate
;
987 inst
= bld
.ADD(result
, op
[0], op
[1]);
988 inst
->saturate
= instr
->dest
.saturate
;
991 case nir_op_uadd_sat
:
992 inst
= bld
.ADD(result
, op
[0], op
[1]);
993 inst
->saturate
= true;
997 inst
= bld
.MUL(result
, op
[0], op
[1]);
998 inst
->saturate
= instr
->dest
.saturate
;
1002 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1003 bld
.MUL(result
, op
[0], op
[1]);
1006 case nir_op_imul_high
:
1007 case nir_op_umul_high
:
1008 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1009 bld
.emit(SHADER_OPCODE_MULH
, result
, op
[0], op
[1]);
1014 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1015 bld
.emit(SHADER_OPCODE_INT_QUOTIENT
, result
, op
[0], op
[1]);
1018 case nir_op_uadd_carry
:
1019 unreachable("Should have been lowered by carry_to_arith().");
1021 case nir_op_usub_borrow
:
1022 unreachable("Should have been lowered by borrow_to_arith().");
1026 /* According to the sign table for INT DIV in the Ivy Bridge PRM, it
1027 * appears that our hardware just does the right thing for signed
1030 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1031 bld
.emit(SHADER_OPCODE_INT_REMAINDER
, result
, op
[0], op
[1]);
1035 /* Get a regular C-style remainder. If a % b == 0, set the predicate. */
1036 bld
.emit(SHADER_OPCODE_INT_REMAINDER
, result
, op
[0], op
[1]);
1038 /* Math instructions don't support conditional mod */
1039 inst
= bld
.MOV(bld
.null_reg_d(), result
);
1040 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
1042 /* Now, we need to determine if signs of the sources are different.
1043 * When we XOR the sources, the top bit is 0 if they are the same and 1
1044 * if they are different. We can then use a conditional modifier to
1045 * turn that into a predicate. This leads us to an XOR.l instruction.
1047 * Technically, according to the PRM, you're not allowed to use .l on a
1048 * XOR instruction. However, emperical experiments and Curro's reading
1049 * of the simulator source both indicate that it's safe.
1051 fs_reg tmp
= bld
.vgrf(BRW_REGISTER_TYPE_D
);
1052 inst
= bld
.XOR(tmp
, op
[0], op
[1]);
1053 inst
->predicate
= BRW_PREDICATE_NORMAL
;
1054 inst
->conditional_mod
= BRW_CONDITIONAL_L
;
1056 /* If the result of the initial remainder operation is non-zero and the
1057 * two sources have different signs, add in a copy of op[1] to get the
1058 * final integer modulus value.
1060 inst
= bld
.ADD(result
, result
, op
[1]);
1061 inst
->predicate
= BRW_PREDICATE_NORMAL
;
1068 case nir_op_fne32
: {
1069 fs_reg dest
= result
;
1071 const uint32_t bit_size
= nir_src_bit_size(instr
->src
[0].src
);
1073 dest
= bld
.vgrf(op
[0].type
, 1);
1075 brw_conditional_mod cond
;
1076 switch (instr
->op
) {
1078 cond
= BRW_CONDITIONAL_L
;
1081 cond
= BRW_CONDITIONAL_GE
;
1084 cond
= BRW_CONDITIONAL_Z
;
1087 cond
= BRW_CONDITIONAL_NZ
;
1090 unreachable("bad opcode");
1093 bld
.CMP(dest
, op
[0], op
[1], cond
);
1095 if (bit_size
> 32) {
1096 bld
.MOV(result
, subscript(dest
, BRW_REGISTER_TYPE_UD
, 0));
1097 } else if(bit_size
< 32) {
1098 /* When we convert the result to 32-bit we need to be careful and do
1099 * it as a signed conversion to get sign extension (for 32-bit true)
1101 const brw_reg_type src_type
=
1102 brw_reg_type_from_bit_size(bit_size
, BRW_REGISTER_TYPE_D
);
1104 bld
.MOV(retype(result
, BRW_REGISTER_TYPE_D
), retype(dest
, src_type
));
1114 case nir_op_ine32
: {
1115 fs_reg dest
= result
;
1117 const uint32_t bit_size
= nir_src_bit_size(instr
->src
[0].src
);
1119 dest
= bld
.vgrf(op
[0].type
, 1);
1121 brw_conditional_mod cond
;
1122 switch (instr
->op
) {
1125 cond
= BRW_CONDITIONAL_L
;
1129 cond
= BRW_CONDITIONAL_GE
;
1132 cond
= BRW_CONDITIONAL_Z
;
1135 cond
= BRW_CONDITIONAL_NZ
;
1138 unreachable("bad opcode");
1140 bld
.CMP(dest
, op
[0], op
[1], cond
);
1142 if (bit_size
> 32) {
1143 bld
.MOV(result
, subscript(dest
, BRW_REGISTER_TYPE_UD
, 0));
1144 } else if (bit_size
< 32) {
1145 /* When we convert the result to 32-bit we need to be careful and do
1146 * it as a signed conversion to get sign extension (for 32-bit true)
1148 const brw_reg_type src_type
=
1149 brw_reg_type_from_bit_size(bit_size
, BRW_REGISTER_TYPE_D
);
1151 bld
.MOV(retype(result
, BRW_REGISTER_TYPE_D
), retype(dest
, src_type
));
1157 if (devinfo
->gen
>= 8) {
1158 nir_alu_instr
*const inot_src_instr
=
1159 nir_src_as_alu_instr(&instr
->src
[0].src
);
1161 if (inot_src_instr
!= NULL
&&
1162 (inot_src_instr
->op
== nir_op_ior
||
1163 inot_src_instr
->op
== nir_op_ixor
||
1164 inot_src_instr
->op
== nir_op_iand
) &&
1165 !inot_src_instr
->src
[0].abs
&&
1166 !inot_src_instr
->src
[0].negate
&&
1167 !inot_src_instr
->src
[1].abs
&&
1168 !inot_src_instr
->src
[1].negate
) {
1169 /* The sources of the source logical instruction are now the
1170 * sources of the instruction that will be generated.
1172 prepare_alu_destination_and_sources(bld
, inot_src_instr
, op
, false);
1173 resolve_inot_sources(bld
, inot_src_instr
, op
);
1175 /* Smash all of the sources and destination to be signed. This
1176 * doesn't matter for the operation of the instruction, but cmod
1177 * propagation fails on unsigned sources with negation (due to
1178 * fs_inst::can_do_cmod returning false).
1181 brw_type_for_nir_type(devinfo
,
1182 (nir_alu_type
)(nir_type_int
|
1183 nir_dest_bit_size(instr
->dest
.dest
)));
1185 brw_type_for_nir_type(devinfo
,
1186 (nir_alu_type
)(nir_type_int
|
1187 nir_src_bit_size(inot_src_instr
->src
[0].src
)));
1189 brw_type_for_nir_type(devinfo
,
1190 (nir_alu_type
)(nir_type_int
|
1191 nir_src_bit_size(inot_src_instr
->src
[1].src
)));
1193 /* For XOR, only invert one of the sources. Arbitrarily choose
1196 op
[0].negate
= !op
[0].negate
;
1197 if (inot_src_instr
->op
!= nir_op_ixor
)
1198 op
[1].negate
= !op
[1].negate
;
1200 switch (inot_src_instr
->op
) {
1202 bld
.AND(result
, op
[0], op
[1]);
1206 bld
.OR(result
, op
[0], op
[1]);
1210 bld
.XOR(result
, op
[0], op
[1]);
1214 unreachable("impossible opcode");
1217 op
[0] = resolve_source_modifiers(op
[0]);
1219 bld
.NOT(result
, op
[0]);
1222 if (devinfo
->gen
>= 8) {
1223 resolve_inot_sources(bld
, instr
, op
);
1225 bld
.XOR(result
, op
[0], op
[1]);
1228 if (devinfo
->gen
>= 8) {
1229 resolve_inot_sources(bld
, instr
, op
);
1231 bld
.OR(result
, op
[0], op
[1]);
1234 if (devinfo
->gen
>= 8) {
1235 resolve_inot_sources(bld
, instr
, op
);
1237 bld
.AND(result
, op
[0], op
[1]);
1243 case nir_op_b32all_fequal2
:
1244 case nir_op_b32all_iequal2
:
1245 case nir_op_b32all_fequal3
:
1246 case nir_op_b32all_iequal3
:
1247 case nir_op_b32all_fequal4
:
1248 case nir_op_b32all_iequal4
:
1249 case nir_op_b32any_fnequal2
:
1250 case nir_op_b32any_inequal2
:
1251 case nir_op_b32any_fnequal3
:
1252 case nir_op_b32any_inequal3
:
1253 case nir_op_b32any_fnequal4
:
1254 case nir_op_b32any_inequal4
:
1255 unreachable("Lowered by nir_lower_alu_reductions");
1257 case nir_op_fnoise1_1
:
1258 case nir_op_fnoise1_2
:
1259 case nir_op_fnoise1_3
:
1260 case nir_op_fnoise1_4
:
1261 case nir_op_fnoise2_1
:
1262 case nir_op_fnoise2_2
:
1263 case nir_op_fnoise2_3
:
1264 case nir_op_fnoise2_4
:
1265 case nir_op_fnoise3_1
:
1266 case nir_op_fnoise3_2
:
1267 case nir_op_fnoise3_3
:
1268 case nir_op_fnoise3_4
:
1269 case nir_op_fnoise4_1
:
1270 case nir_op_fnoise4_2
:
1271 case nir_op_fnoise4_3
:
1272 case nir_op_fnoise4_4
:
1273 unreachable("not reached: should be handled by lower_noise");
1276 unreachable("not reached: should be handled by ldexp_to_arith()");
1279 inst
= bld
.emit(SHADER_OPCODE_SQRT
, result
, op
[0]);
1280 inst
->saturate
= instr
->dest
.saturate
;
1284 inst
= bld
.emit(SHADER_OPCODE_RSQ
, result
, op
[0]);
1285 inst
->saturate
= instr
->dest
.saturate
;
1289 case nir_op_f2b32
: {
1290 uint32_t bit_size
= nir_src_bit_size(instr
->src
[0].src
);
1291 if (bit_size
== 64) {
1292 /* two-argument instructions can't take 64-bit immediates */
1296 if (instr
->op
== nir_op_f2b32
) {
1297 zero
= vgrf(glsl_type::double_type
);
1298 tmp
= vgrf(glsl_type::double_type
);
1299 bld
.MOV(zero
, setup_imm_df(bld
, 0.0));
1301 zero
= vgrf(glsl_type::int64_t_type
);
1302 tmp
= vgrf(glsl_type::int64_t_type
);
1303 bld
.MOV(zero
, brw_imm_q(0));
1306 /* A SIMD16 execution needs to be split in two instructions, so use
1307 * a vgrf instead of the flag register as dst so instruction splitting
1310 bld
.CMP(tmp
, op
[0], zero
, BRW_CONDITIONAL_NZ
);
1311 bld
.MOV(result
, subscript(tmp
, BRW_REGISTER_TYPE_UD
, 0));
1314 if (bit_size
== 32) {
1315 zero
= instr
->op
== nir_op_f2b32
? brw_imm_f(0.0f
) : brw_imm_d(0);
1317 assert(bit_size
== 16);
1318 zero
= instr
->op
== nir_op_f2b32
?
1319 retype(brw_imm_w(0), BRW_REGISTER_TYPE_HF
) : brw_imm_w(0);
1321 bld
.CMP(result
, op
[0], zero
, BRW_CONDITIONAL_NZ
);
1327 inst
= bld
.RNDZ(result
, op
[0]);
1328 inst
->saturate
= instr
->dest
.saturate
;
1331 case nir_op_fceil
: {
1332 op
[0].negate
= !op
[0].negate
;
1333 fs_reg temp
= vgrf(glsl_type::float_type
);
1334 bld
.RNDD(temp
, op
[0]);
1336 inst
= bld
.MOV(result
, temp
);
1337 inst
->saturate
= instr
->dest
.saturate
;
1341 inst
= bld
.RNDD(result
, op
[0]);
1342 inst
->saturate
= instr
->dest
.saturate
;
1345 inst
= bld
.FRC(result
, op
[0]);
1346 inst
->saturate
= instr
->dest
.saturate
;
1348 case nir_op_fround_even
:
1349 inst
= bld
.RNDE(result
, op
[0]);
1350 inst
->saturate
= instr
->dest
.saturate
;
1353 case nir_op_fquantize2f16
: {
1354 fs_reg tmp16
= bld
.vgrf(BRW_REGISTER_TYPE_D
);
1355 fs_reg tmp32
= bld
.vgrf(BRW_REGISTER_TYPE_F
);
1356 fs_reg zero
= bld
.vgrf(BRW_REGISTER_TYPE_F
);
1358 /* The destination stride must be at least as big as the source stride. */
1359 tmp16
.type
= BRW_REGISTER_TYPE_W
;
1362 /* Check for denormal */
1363 fs_reg abs_src0
= op
[0];
1364 abs_src0
.abs
= true;
1365 bld
.CMP(bld
.null_reg_f(), abs_src0
, brw_imm_f(ldexpf(1.0, -14)),
1367 /* Get the appropriately signed zero */
1368 bld
.AND(retype(zero
, BRW_REGISTER_TYPE_UD
),
1369 retype(op
[0], BRW_REGISTER_TYPE_UD
),
1370 brw_imm_ud(0x80000000));
1371 /* Do the actual F32 -> F16 -> F32 conversion */
1372 bld
.emit(BRW_OPCODE_F32TO16
, tmp16
, op
[0]);
1373 bld
.emit(BRW_OPCODE_F16TO32
, tmp32
, tmp16
);
1374 /* Select that or zero based on normal status */
1375 inst
= bld
.SEL(result
, zero
, tmp32
);
1376 inst
->predicate
= BRW_PREDICATE_NORMAL
;
1377 inst
->saturate
= instr
->dest
.saturate
;
1384 inst
= bld
.emit_minmax(result
, op
[0], op
[1], BRW_CONDITIONAL_L
);
1385 inst
->saturate
= instr
->dest
.saturate
;
1391 inst
= bld
.emit_minmax(result
, op
[0], op
[1], BRW_CONDITIONAL_GE
);
1392 inst
->saturate
= instr
->dest
.saturate
;
1395 case nir_op_pack_snorm_2x16
:
1396 case nir_op_pack_snorm_4x8
:
1397 case nir_op_pack_unorm_2x16
:
1398 case nir_op_pack_unorm_4x8
:
1399 case nir_op_unpack_snorm_2x16
:
1400 case nir_op_unpack_snorm_4x8
:
1401 case nir_op_unpack_unorm_2x16
:
1402 case nir_op_unpack_unorm_4x8
:
1403 case nir_op_unpack_half_2x16
:
1404 case nir_op_pack_half_2x16
:
1405 unreachable("not reached: should be handled by lower_packing_builtins");
1407 case nir_op_unpack_half_2x16_split_x
:
1408 inst
= bld
.emit(BRW_OPCODE_F16TO32
, result
,
1409 subscript(op
[0], BRW_REGISTER_TYPE_UW
, 0));
1410 inst
->saturate
= instr
->dest
.saturate
;
1412 case nir_op_unpack_half_2x16_split_y
:
1413 inst
= bld
.emit(BRW_OPCODE_F16TO32
, result
,
1414 subscript(op
[0], BRW_REGISTER_TYPE_UW
, 1));
1415 inst
->saturate
= instr
->dest
.saturate
;
1418 case nir_op_pack_64_2x32_split
:
1419 case nir_op_pack_32_2x16_split
:
1420 bld
.emit(FS_OPCODE_PACK
, result
, op
[0], op
[1]);
1423 case nir_op_unpack_64_2x32_split_x
:
1424 case nir_op_unpack_64_2x32_split_y
: {
1425 if (instr
->op
== nir_op_unpack_64_2x32_split_x
)
1426 bld
.MOV(result
, subscript(op
[0], BRW_REGISTER_TYPE_UD
, 0));
1428 bld
.MOV(result
, subscript(op
[0], BRW_REGISTER_TYPE_UD
, 1));
1432 case nir_op_unpack_32_2x16_split_x
:
1433 case nir_op_unpack_32_2x16_split_y
: {
1434 if (instr
->op
== nir_op_unpack_32_2x16_split_x
)
1435 bld
.MOV(result
, subscript(op
[0], BRW_REGISTER_TYPE_UW
, 0));
1437 bld
.MOV(result
, subscript(op
[0], BRW_REGISTER_TYPE_UW
, 1));
1442 inst
= bld
.emit(SHADER_OPCODE_POW
, result
, op
[0], op
[1]);
1443 inst
->saturate
= instr
->dest
.saturate
;
1446 case nir_op_bitfield_reverse
:
1447 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1448 bld
.BFREV(result
, op
[0]);
1451 case nir_op_bit_count
:
1452 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1453 bld
.CBIT(result
, op
[0]);
1456 case nir_op_ufind_msb
: {
1457 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1458 emit_find_msb_using_lzd(bld
, result
, op
[0], false);
1462 case nir_op_ifind_msb
: {
1463 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1465 if (devinfo
->gen
< 7) {
1466 emit_find_msb_using_lzd(bld
, result
, op
[0], true);
1468 bld
.FBH(retype(result
, BRW_REGISTER_TYPE_UD
), op
[0]);
1470 /* FBH counts from the MSB side, while GLSL's findMSB() wants the
1471 * count from the LSB side. If FBH didn't return an error
1472 * (0xFFFFFFFF), then subtract the result from 31 to convert the MSB
1473 * count into an LSB count.
1475 bld
.CMP(bld
.null_reg_d(), result
, brw_imm_d(-1), BRW_CONDITIONAL_NZ
);
1477 inst
= bld
.ADD(result
, result
, brw_imm_d(31));
1478 inst
->predicate
= BRW_PREDICATE_NORMAL
;
1479 inst
->src
[0].negate
= true;
1484 case nir_op_find_lsb
:
1485 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1487 if (devinfo
->gen
< 7) {
1488 fs_reg temp
= vgrf(glsl_type::int_type
);
1490 /* (x & -x) generates a value that consists of only the LSB of x.
1491 * For all powers of 2, findMSB(y) == findLSB(y).
1493 fs_reg src
= retype(op
[0], BRW_REGISTER_TYPE_D
);
1494 fs_reg negated_src
= src
;
1496 /* One must be negated, and the other must be non-negated. It
1497 * doesn't matter which is which.
1499 negated_src
.negate
= true;
1502 bld
.AND(temp
, src
, negated_src
);
1503 emit_find_msb_using_lzd(bld
, result
, temp
, false);
1505 bld
.FBL(result
, op
[0]);
1509 case nir_op_ubitfield_extract
:
1510 case nir_op_ibitfield_extract
:
1511 unreachable("should have been lowered");
1514 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1515 bld
.BFE(result
, op
[2], op
[1], op
[0]);
1518 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1519 bld
.BFI1(result
, op
[0], op
[1]);
1522 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1523 bld
.BFI2(result
, op
[0], op
[1], op
[2]);
1526 case nir_op_bitfield_insert
:
1527 unreachable("not reached: should have been lowered");
1530 bld
.SHL(result
, op
[0], op
[1]);
1533 bld
.ASR(result
, op
[0], op
[1]);
1536 bld
.SHR(result
, op
[0], op
[1]);
1539 case nir_op_pack_half_2x16_split
:
1540 bld
.emit(FS_OPCODE_PACK_HALF_2x16_SPLIT
, result
, op
[0], op
[1]);
1544 inst
= bld
.MAD(result
, op
[2], op
[1], op
[0]);
1545 inst
->saturate
= instr
->dest
.saturate
;
1549 inst
= bld
.LRP(result
, op
[0], op
[1], op
[2]);
1550 inst
->saturate
= instr
->dest
.saturate
;
1553 case nir_op_b32csel
:
1554 if (optimize_frontfacing_ternary(instr
, result
))
1557 bld
.CMP(bld
.null_reg_d(), op
[0], brw_imm_d(0), BRW_CONDITIONAL_NZ
);
1558 inst
= bld
.SEL(result
, op
[1], op
[2]);
1559 inst
->predicate
= BRW_PREDICATE_NORMAL
;
1562 case nir_op_extract_u8
:
1563 case nir_op_extract_i8
: {
1564 unsigned byte
= nir_src_as_uint(instr
->src
[1].src
);
1569 * There is no direct conversion from B/UB to Q/UQ or Q/UQ to B/UB.
1570 * Use two instructions and a word or DWord intermediate integer type.
1572 if (nir_dest_bit_size(instr
->dest
.dest
) == 64) {
1573 const brw_reg_type type
= brw_int_type(2, instr
->op
== nir_op_extract_i8
);
1575 if (instr
->op
== nir_op_extract_i8
) {
1576 /* If we need to sign extend, extract to a word first */
1577 fs_reg w_temp
= bld
.vgrf(BRW_REGISTER_TYPE_W
);
1578 bld
.MOV(w_temp
, subscript(op
[0], type
, byte
));
1579 bld
.MOV(result
, w_temp
);
1581 /* Otherwise use an AND with 0xff and a word type */
1582 bld
.AND(result
, subscript(op
[0], type
, byte
/ 2), brw_imm_uw(0xff));
1585 const brw_reg_type type
= brw_int_type(1, instr
->op
== nir_op_extract_i8
);
1586 bld
.MOV(result
, subscript(op
[0], type
, byte
));
1591 case nir_op_extract_u16
:
1592 case nir_op_extract_i16
: {
1593 const brw_reg_type type
= brw_int_type(2, instr
->op
== nir_op_extract_i16
);
1594 unsigned word
= nir_src_as_uint(instr
->src
[1].src
);
1595 bld
.MOV(result
, subscript(op
[0], type
, word
));
1600 unreachable("unhandled instruction");
1603 /* If we need to do a boolean resolve, replace the result with -(x & 1)
1604 * to sign extend the low bit to 0/~0
1606 if (devinfo
->gen
<= 5 &&
1607 (instr
->instr
.pass_flags
& BRW_NIR_BOOLEAN_MASK
) == BRW_NIR_BOOLEAN_NEEDS_RESOLVE
) {
1608 fs_reg masked
= vgrf(glsl_type::int_type
);
1609 bld
.AND(masked
, result
, brw_imm_d(1));
1610 masked
.negate
= true;
1611 bld
.MOV(retype(result
, BRW_REGISTER_TYPE_D
), masked
);
1616 fs_visitor::nir_emit_load_const(const fs_builder
&bld
,
1617 nir_load_const_instr
*instr
)
1619 const brw_reg_type reg_type
=
1620 brw_reg_type_from_bit_size(instr
->def
.bit_size
, BRW_REGISTER_TYPE_D
);
1621 fs_reg reg
= bld
.vgrf(reg_type
, instr
->def
.num_components
);
1623 switch (instr
->def
.bit_size
) {
1625 for (unsigned i
= 0; i
< instr
->def
.num_components
; i
++)
1626 bld
.MOV(offset(reg
, bld
, i
), setup_imm_b(bld
, instr
->value
.i8
[i
]));
1630 for (unsigned i
= 0; i
< instr
->def
.num_components
; i
++)
1631 bld
.MOV(offset(reg
, bld
, i
), brw_imm_w(instr
->value
.i16
[i
]));
1635 for (unsigned i
= 0; i
< instr
->def
.num_components
; i
++)
1636 bld
.MOV(offset(reg
, bld
, i
), brw_imm_d(instr
->value
.i32
[i
]));
1640 assert(devinfo
->gen
>= 7);
1641 if (devinfo
->gen
== 7) {
1642 /* We don't get 64-bit integer types until gen8 */
1643 for (unsigned i
= 0; i
< instr
->def
.num_components
; i
++) {
1644 bld
.MOV(retype(offset(reg
, bld
, i
), BRW_REGISTER_TYPE_DF
),
1645 setup_imm_df(bld
, instr
->value
.f64
[i
]));
1648 for (unsigned i
= 0; i
< instr
->def
.num_components
; i
++)
1649 bld
.MOV(offset(reg
, bld
, i
), brw_imm_q(instr
->value
.i64
[i
]));
1654 unreachable("Invalid bit size");
1657 nir_ssa_values
[instr
->def
.index
] = reg
;
1661 fs_visitor::get_nir_src(const nir_src
&src
)
1665 if (src
.ssa
->parent_instr
->type
== nir_instr_type_ssa_undef
) {
1666 const brw_reg_type reg_type
=
1667 brw_reg_type_from_bit_size(src
.ssa
->bit_size
, BRW_REGISTER_TYPE_D
);
1668 reg
= bld
.vgrf(reg_type
, src
.ssa
->num_components
);
1670 reg
= nir_ssa_values
[src
.ssa
->index
];
1673 /* We don't handle indirects on locals */
1674 assert(src
.reg
.indirect
== NULL
);
1675 reg
= offset(nir_locals
[src
.reg
.reg
->index
], bld
,
1676 src
.reg
.base_offset
* src
.reg
.reg
->num_components
);
1679 if (nir_src_bit_size(src
) == 64 && devinfo
->gen
== 7) {
1680 /* The only 64-bit type available on gen7 is DF, so use that. */
1681 reg
.type
= BRW_REGISTER_TYPE_DF
;
1683 /* To avoid floating-point denorm flushing problems, set the type by
1684 * default to an integer type - instructions that need floating point
1685 * semantics will set this to F if they need to
1687 reg
.type
= brw_reg_type_from_bit_size(nir_src_bit_size(src
),
1688 BRW_REGISTER_TYPE_D
);
1695 * Return an IMM for constants; otherwise call get_nir_src() as normal.
1697 * This function should not be called on any value which may be 64 bits.
1698 * We could theoretically support 64-bit on gen8+ but we choose not to
1699 * because it wouldn't work in general (no gen7 support) and there are
1700 * enough restrictions in 64-bit immediates that you can't take the return
1701 * value and treat it the same as the result of get_nir_src().
1704 fs_visitor::get_nir_src_imm(const nir_src
&src
)
1706 assert(nir_src_bit_size(src
) == 32);
1707 return nir_src_is_const(src
) ?
1708 fs_reg(brw_imm_d(nir_src_as_int(src
))) : get_nir_src(src
);
1712 fs_visitor::get_nir_dest(const nir_dest
&dest
)
1715 const brw_reg_type reg_type
=
1716 brw_reg_type_from_bit_size(dest
.ssa
.bit_size
,
1717 dest
.ssa
.bit_size
== 8 ?
1718 BRW_REGISTER_TYPE_D
:
1719 BRW_REGISTER_TYPE_F
);
1720 nir_ssa_values
[dest
.ssa
.index
] =
1721 bld
.vgrf(reg_type
, dest
.ssa
.num_components
);
1722 return nir_ssa_values
[dest
.ssa
.index
];
1724 /* We don't handle indirects on locals */
1725 assert(dest
.reg
.indirect
== NULL
);
1726 return offset(nir_locals
[dest
.reg
.reg
->index
], bld
,
1727 dest
.reg
.base_offset
* dest
.reg
.reg
->num_components
);
1732 fs_visitor::emit_percomp(const fs_builder
&bld
, const fs_inst
&inst
,
1735 for (unsigned i
= 0; i
< 4; i
++) {
1736 if (!((wr_mask
>> i
) & 1))
1739 fs_inst
*new_inst
= new(mem_ctx
) fs_inst(inst
);
1740 new_inst
->dst
= offset(new_inst
->dst
, bld
, i
);
1741 for (unsigned j
= 0; j
< new_inst
->sources
; j
++)
1742 if (new_inst
->src
[j
].file
== VGRF
)
1743 new_inst
->src
[j
] = offset(new_inst
->src
[j
], bld
, i
);
1750 emit_pixel_interpolater_send(const fs_builder
&bld
,
1755 glsl_interp_mode interpolation
)
1757 struct brw_wm_prog_data
*wm_prog_data
=
1758 brw_wm_prog_data(bld
.shader
->stage_prog_data
);
1760 fs_inst
*inst
= bld
.emit(opcode
, dst
, src
, desc
);
1761 /* 2 floats per slot returned */
1762 inst
->size_written
= 2 * dst
.component_size(inst
->exec_size
);
1763 inst
->pi_noperspective
= interpolation
== INTERP_MODE_NOPERSPECTIVE
;
1765 wm_prog_data
->pulls_bary
= true;
1771 * Computes 1 << x, given a D/UD register containing some value x.
1774 intexp2(const fs_builder
&bld
, const fs_reg
&x
)
1776 assert(x
.type
== BRW_REGISTER_TYPE_UD
|| x
.type
== BRW_REGISTER_TYPE_D
);
1778 fs_reg result
= bld
.vgrf(x
.type
, 1);
1779 fs_reg one
= bld
.vgrf(x
.type
, 1);
1781 bld
.MOV(one
, retype(brw_imm_d(1), one
.type
));
1782 bld
.SHL(result
, one
, x
);
1787 fs_visitor::emit_gs_end_primitive(const nir_src
&vertex_count_nir_src
)
1789 assert(stage
== MESA_SHADER_GEOMETRY
);
1791 struct brw_gs_prog_data
*gs_prog_data
= brw_gs_prog_data(prog_data
);
1793 if (gs_compile
->control_data_header_size_bits
== 0)
1796 /* We can only do EndPrimitive() functionality when the control data
1797 * consists of cut bits. Fortunately, the only time it isn't is when the
1798 * output type is points, in which case EndPrimitive() is a no-op.
1800 if (gs_prog_data
->control_data_format
!=
1801 GEN7_GS_CONTROL_DATA_FORMAT_GSCTL_CUT
) {
1805 /* Cut bits use one bit per vertex. */
1806 assert(gs_compile
->control_data_bits_per_vertex
== 1);
1808 fs_reg vertex_count
= get_nir_src(vertex_count_nir_src
);
1809 vertex_count
.type
= BRW_REGISTER_TYPE_UD
;
1811 /* Cut bit n should be set to 1 if EndPrimitive() was called after emitting
1812 * vertex n, 0 otherwise. So all we need to do here is mark bit
1813 * (vertex_count - 1) % 32 in the cut_bits register to indicate that
1814 * EndPrimitive() was called after emitting vertex (vertex_count - 1);
1815 * vec4_gs_visitor::emit_control_data_bits() will take care of the rest.
1817 * Note that if EndPrimitive() is called before emitting any vertices, this
1818 * will cause us to set bit 31 of the control_data_bits register to 1.
1819 * That's fine because:
1821 * - If max_vertices < 32, then vertex number 31 (zero-based) will never be
1822 * output, so the hardware will ignore cut bit 31.
1824 * - If max_vertices == 32, then vertex number 31 is guaranteed to be the
1825 * last vertex, so setting cut bit 31 has no effect (since the primitive
1826 * is automatically ended when the GS terminates).
1828 * - If max_vertices > 32, then the ir_emit_vertex visitor will reset the
1829 * control_data_bits register to 0 when the first vertex is emitted.
1832 const fs_builder abld
= bld
.annotate("end primitive");
1834 /* control_data_bits |= 1 << ((vertex_count - 1) % 32) */
1835 fs_reg prev_count
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
1836 abld
.ADD(prev_count
, vertex_count
, brw_imm_ud(0xffffffffu
));
1837 fs_reg mask
= intexp2(abld
, prev_count
);
1838 /* Note: we're relying on the fact that the GEN SHL instruction only pays
1839 * attention to the lower 5 bits of its second source argument, so on this
1840 * architecture, 1 << (vertex_count - 1) is equivalent to 1 <<
1841 * ((vertex_count - 1) % 32).
1843 abld
.OR(this->control_data_bits
, this->control_data_bits
, mask
);
1847 fs_visitor::emit_gs_control_data_bits(const fs_reg
&vertex_count
)
1849 assert(stage
== MESA_SHADER_GEOMETRY
);
1850 assert(gs_compile
->control_data_bits_per_vertex
!= 0);
1852 struct brw_gs_prog_data
*gs_prog_data
= brw_gs_prog_data(prog_data
);
1854 const fs_builder abld
= bld
.annotate("emit control data bits");
1855 const fs_builder fwa_bld
= bld
.exec_all();
1857 /* We use a single UD register to accumulate control data bits (32 bits
1858 * for each of the SIMD8 channels). So we need to write a DWord (32 bits)
1861 * Unfortunately, the URB_WRITE_SIMD8 message uses 128-bit (OWord) offsets.
1862 * We have select a 128-bit group via the Global and Per-Slot Offsets, then
1863 * use the Channel Mask phase to enable/disable which DWord within that
1864 * group to write. (Remember, different SIMD8 channels may have emitted
1865 * different numbers of vertices, so we may need per-slot offsets.)
1867 * Channel masking presents an annoying problem: we may have to replicate
1868 * the data up to 4 times:
1870 * Msg = Handles, Per-Slot Offsets, Channel Masks, Data, Data, Data, Data.
1872 * To avoid penalizing shaders that emit a small number of vertices, we
1873 * can avoid these sometimes: if the size of the control data header is
1874 * <= 128 bits, then there is only 1 OWord. All SIMD8 channels will land
1875 * land in the same 128-bit group, so we can skip per-slot offsets.
1877 * Similarly, if the control data header is <= 32 bits, there is only one
1878 * DWord, so we can skip channel masks.
1880 enum opcode opcode
= SHADER_OPCODE_URB_WRITE_SIMD8
;
1882 fs_reg channel_mask
, per_slot_offset
;
1884 if (gs_compile
->control_data_header_size_bits
> 32) {
1885 opcode
= SHADER_OPCODE_URB_WRITE_SIMD8_MASKED
;
1886 channel_mask
= vgrf(glsl_type::uint_type
);
1889 if (gs_compile
->control_data_header_size_bits
> 128) {
1890 opcode
= SHADER_OPCODE_URB_WRITE_SIMD8_MASKED_PER_SLOT
;
1891 per_slot_offset
= vgrf(glsl_type::uint_type
);
1894 /* Figure out which DWord we're trying to write to using the formula:
1896 * dword_index = (vertex_count - 1) * bits_per_vertex / 32
1898 * Since bits_per_vertex is a power of two, and is known at compile
1899 * time, this can be optimized to:
1901 * dword_index = (vertex_count - 1) >> (6 - log2(bits_per_vertex))
1903 if (opcode
!= SHADER_OPCODE_URB_WRITE_SIMD8
) {
1904 fs_reg dword_index
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
1905 fs_reg prev_count
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
1906 abld
.ADD(prev_count
, vertex_count
, brw_imm_ud(0xffffffffu
));
1907 unsigned log2_bits_per_vertex
=
1908 util_last_bit(gs_compile
->control_data_bits_per_vertex
);
1909 abld
.SHR(dword_index
, prev_count
, brw_imm_ud(6u - log2_bits_per_vertex
));
1911 if (per_slot_offset
.file
!= BAD_FILE
) {
1912 /* Set the per-slot offset to dword_index / 4, so that we'll write to
1913 * the appropriate OWord within the control data header.
1915 abld
.SHR(per_slot_offset
, dword_index
, brw_imm_ud(2u));
1918 /* Set the channel masks to 1 << (dword_index % 4), so that we'll
1919 * write to the appropriate DWORD within the OWORD.
1921 fs_reg channel
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
1922 fwa_bld
.AND(channel
, dword_index
, brw_imm_ud(3u));
1923 channel_mask
= intexp2(fwa_bld
, channel
);
1924 /* Then the channel masks need to be in bits 23:16. */
1925 fwa_bld
.SHL(channel_mask
, channel_mask
, brw_imm_ud(16u));
1928 /* Store the control data bits in the message payload and send it. */
1930 if (channel_mask
.file
!= BAD_FILE
)
1931 mlen
+= 4; /* channel masks, plus 3 extra copies of the data */
1932 if (per_slot_offset
.file
!= BAD_FILE
)
1935 fs_reg payload
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, mlen
);
1936 fs_reg
*sources
= ralloc_array(mem_ctx
, fs_reg
, mlen
);
1938 sources
[i
++] = fs_reg(retype(brw_vec8_grf(1, 0), BRW_REGISTER_TYPE_UD
));
1939 if (per_slot_offset
.file
!= BAD_FILE
)
1940 sources
[i
++] = per_slot_offset
;
1941 if (channel_mask
.file
!= BAD_FILE
)
1942 sources
[i
++] = channel_mask
;
1944 sources
[i
++] = this->control_data_bits
;
1947 abld
.LOAD_PAYLOAD(payload
, sources
, mlen
, mlen
);
1948 fs_inst
*inst
= abld
.emit(opcode
, reg_undef
, payload
);
1950 /* We need to increment Global Offset by 256-bits to make room for
1951 * Broadwell's extra "Vertex Count" payload at the beginning of the
1952 * URB entry. Since this is an OWord message, Global Offset is counted
1953 * in 128-bit units, so we must set it to 2.
1955 if (gs_prog_data
->static_vertex_count
== -1)
1960 fs_visitor::set_gs_stream_control_data_bits(const fs_reg
&vertex_count
,
1963 /* control_data_bits |= stream_id << ((2 * (vertex_count - 1)) % 32) */
1965 /* Note: we are calling this *before* increasing vertex_count, so
1966 * this->vertex_count == vertex_count - 1 in the formula above.
1969 /* Stream mode uses 2 bits per vertex */
1970 assert(gs_compile
->control_data_bits_per_vertex
== 2);
1972 /* Must be a valid stream */
1973 assert(stream_id
< MAX_VERTEX_STREAMS
);
1975 /* Control data bits are initialized to 0 so we don't have to set any
1976 * bits when sending vertices to stream 0.
1981 const fs_builder abld
= bld
.annotate("set stream control data bits", NULL
);
1983 /* reg::sid = stream_id */
1984 fs_reg sid
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
1985 abld
.MOV(sid
, brw_imm_ud(stream_id
));
1987 /* reg:shift_count = 2 * (vertex_count - 1) */
1988 fs_reg shift_count
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
1989 abld
.SHL(shift_count
, vertex_count
, brw_imm_ud(1u));
1991 /* Note: we're relying on the fact that the GEN SHL instruction only pays
1992 * attention to the lower 5 bits of its second source argument, so on this
1993 * architecture, stream_id << 2 * (vertex_count - 1) is equivalent to
1994 * stream_id << ((2 * (vertex_count - 1)) % 32).
1996 fs_reg mask
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
1997 abld
.SHL(mask
, sid
, shift_count
);
1998 abld
.OR(this->control_data_bits
, this->control_data_bits
, mask
);
2002 fs_visitor::emit_gs_vertex(const nir_src
&vertex_count_nir_src
,
2005 assert(stage
== MESA_SHADER_GEOMETRY
);
2007 struct brw_gs_prog_data
*gs_prog_data
= brw_gs_prog_data(prog_data
);
2009 fs_reg vertex_count
= get_nir_src(vertex_count_nir_src
);
2010 vertex_count
.type
= BRW_REGISTER_TYPE_UD
;
2012 /* Haswell and later hardware ignores the "Render Stream Select" bits
2013 * from the 3DSTATE_STREAMOUT packet when the SOL stage is disabled,
2014 * and instead sends all primitives down the pipeline for rasterization.
2015 * If the SOL stage is enabled, "Render Stream Select" is honored and
2016 * primitives bound to non-zero streams are discarded after stream output.
2018 * Since the only purpose of primives sent to non-zero streams is to
2019 * be recorded by transform feedback, we can simply discard all geometry
2020 * bound to these streams when transform feedback is disabled.
2022 if (stream_id
> 0 && !nir
->info
.has_transform_feedback_varyings
)
2025 /* If we're outputting 32 control data bits or less, then we can wait
2026 * until the shader is over to output them all. Otherwise we need to
2027 * output them as we go. Now is the time to do it, since we're about to
2028 * output the vertex_count'th vertex, so it's guaranteed that the
2029 * control data bits associated with the (vertex_count - 1)th vertex are
2032 if (gs_compile
->control_data_header_size_bits
> 32) {
2033 const fs_builder abld
=
2034 bld
.annotate("emit vertex: emit control data bits");
2036 /* Only emit control data bits if we've finished accumulating a batch
2037 * of 32 bits. This is the case when:
2039 * (vertex_count * bits_per_vertex) % 32 == 0
2041 * (in other words, when the last 5 bits of vertex_count *
2042 * bits_per_vertex are 0). Assuming bits_per_vertex == 2^n for some
2043 * integer n (which is always the case, since bits_per_vertex is
2044 * always 1 or 2), this is equivalent to requiring that the last 5-n
2045 * bits of vertex_count are 0:
2047 * vertex_count & (2^(5-n) - 1) == 0
2049 * 2^(5-n) == 2^5 / 2^n == 32 / bits_per_vertex, so this is
2052 * vertex_count & (32 / bits_per_vertex - 1) == 0
2054 * TODO: If vertex_count is an immediate, we could do some of this math
2055 * at compile time...
2058 abld
.AND(bld
.null_reg_d(), vertex_count
,
2059 brw_imm_ud(32u / gs_compile
->control_data_bits_per_vertex
- 1u));
2060 inst
->conditional_mod
= BRW_CONDITIONAL_Z
;
2062 abld
.IF(BRW_PREDICATE_NORMAL
);
2063 /* If vertex_count is 0, then no control data bits have been
2064 * accumulated yet, so we can skip emitting them.
2066 abld
.CMP(bld
.null_reg_d(), vertex_count
, brw_imm_ud(0u),
2067 BRW_CONDITIONAL_NEQ
);
2068 abld
.IF(BRW_PREDICATE_NORMAL
);
2069 emit_gs_control_data_bits(vertex_count
);
2070 abld
.emit(BRW_OPCODE_ENDIF
);
2072 /* Reset control_data_bits to 0 so we can start accumulating a new
2075 * Note: in the case where vertex_count == 0, this neutralizes the
2076 * effect of any call to EndPrimitive() that the shader may have
2077 * made before outputting its first vertex.
2079 inst
= abld
.MOV(this->control_data_bits
, brw_imm_ud(0u));
2080 inst
->force_writemask_all
= true;
2081 abld
.emit(BRW_OPCODE_ENDIF
);
2084 emit_urb_writes(vertex_count
);
2086 /* In stream mode we have to set control data bits for all vertices
2087 * unless we have disabled control data bits completely (which we do
2088 * do for GL_POINTS outputs that don't use streams).
2090 if (gs_compile
->control_data_header_size_bits
> 0 &&
2091 gs_prog_data
->control_data_format
==
2092 GEN7_GS_CONTROL_DATA_FORMAT_GSCTL_SID
) {
2093 set_gs_stream_control_data_bits(vertex_count
, stream_id
);
2098 fs_visitor::emit_gs_input_load(const fs_reg
&dst
,
2099 const nir_src
&vertex_src
,
2100 unsigned base_offset
,
2101 const nir_src
&offset_src
,
2102 unsigned num_components
,
2103 unsigned first_component
)
2105 struct brw_gs_prog_data
*gs_prog_data
= brw_gs_prog_data(prog_data
);
2106 const unsigned push_reg_count
= gs_prog_data
->base
.urb_read_length
* 8;
2108 /* TODO: figure out push input layout for invocations == 1 */
2109 /* TODO: make this work with 64-bit inputs */
2110 if (gs_prog_data
->invocations
== 1 &&
2111 type_sz(dst
.type
) <= 4 &&
2112 nir_src_is_const(offset_src
) && nir_src_is_const(vertex_src
) &&
2113 4 * (base_offset
+ nir_src_as_uint(offset_src
)) < push_reg_count
) {
2114 int imm_offset
= (base_offset
+ nir_src_as_uint(offset_src
)) * 4 +
2115 nir_src_as_uint(vertex_src
) * push_reg_count
;
2116 for (unsigned i
= 0; i
< num_components
; i
++) {
2117 bld
.MOV(offset(dst
, bld
, i
),
2118 fs_reg(ATTR
, imm_offset
+ i
+ first_component
, dst
.type
));
2123 /* Resort to the pull model. Ensure the VUE handles are provided. */
2124 assert(gs_prog_data
->base
.include_vue_handles
);
2126 unsigned first_icp_handle
= gs_prog_data
->include_primitive_id
? 3 : 2;
2127 fs_reg icp_handle
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2129 if (gs_prog_data
->invocations
== 1) {
2130 if (nir_src_is_const(vertex_src
)) {
2131 /* The vertex index is constant; just select the proper URB handle. */
2133 retype(brw_vec8_grf(first_icp_handle
+ nir_src_as_uint(vertex_src
), 0),
2134 BRW_REGISTER_TYPE_UD
);
2136 /* The vertex index is non-constant. We need to use indirect
2137 * addressing to fetch the proper URB handle.
2139 * First, we start with the sequence <7, 6, 5, 4, 3, 2, 1, 0>
2140 * indicating that channel <n> should read the handle from
2141 * DWord <n>. We convert that to bytes by multiplying by 4.
2143 * Next, we convert the vertex index to bytes by multiplying
2144 * by 32 (shifting by 5), and add the two together. This is
2145 * the final indirect byte offset.
2147 fs_reg sequence
= bld
.vgrf(BRW_REGISTER_TYPE_UW
, 1);
2148 fs_reg channel_offsets
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2149 fs_reg vertex_offset_bytes
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2150 fs_reg icp_offset_bytes
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2152 /* sequence = <7, 6, 5, 4, 3, 2, 1, 0> */
2153 bld
.MOV(sequence
, fs_reg(brw_imm_v(0x76543210)));
2154 /* channel_offsets = 4 * sequence = <28, 24, 20, 16, 12, 8, 4, 0> */
2155 bld
.SHL(channel_offsets
, sequence
, brw_imm_ud(2u));
2156 /* Convert vertex_index to bytes (multiply by 32) */
2157 bld
.SHL(vertex_offset_bytes
,
2158 retype(get_nir_src(vertex_src
), BRW_REGISTER_TYPE_UD
),
2160 bld
.ADD(icp_offset_bytes
, vertex_offset_bytes
, channel_offsets
);
2162 /* Use first_icp_handle as the base offset. There is one register
2163 * of URB handles per vertex, so inform the register allocator that
2164 * we might read up to nir->info.gs.vertices_in registers.
2166 bld
.emit(SHADER_OPCODE_MOV_INDIRECT
, icp_handle
,
2167 retype(brw_vec8_grf(first_icp_handle
, 0), icp_handle
.type
),
2168 fs_reg(icp_offset_bytes
),
2169 brw_imm_ud(nir
->info
.gs
.vertices_in
* REG_SIZE
));
2172 assert(gs_prog_data
->invocations
> 1);
2174 if (nir_src_is_const(vertex_src
)) {
2175 unsigned vertex
= nir_src_as_uint(vertex_src
);
2176 assert(devinfo
->gen
>= 9 || vertex
<= 5);
2178 retype(brw_vec1_grf(first_icp_handle
+ vertex
/ 8, vertex
% 8),
2179 BRW_REGISTER_TYPE_UD
));
2181 /* The vertex index is non-constant. We need to use indirect
2182 * addressing to fetch the proper URB handle.
2185 fs_reg icp_offset_bytes
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2187 /* Convert vertex_index to bytes (multiply by 4) */
2188 bld
.SHL(icp_offset_bytes
,
2189 retype(get_nir_src(vertex_src
), BRW_REGISTER_TYPE_UD
),
2192 /* Use first_icp_handle as the base offset. There is one DWord
2193 * of URB handles per vertex, so inform the register allocator that
2194 * we might read up to ceil(nir->info.gs.vertices_in / 8) registers.
2196 bld
.emit(SHADER_OPCODE_MOV_INDIRECT
, icp_handle
,
2197 retype(brw_vec8_grf(first_icp_handle
, 0), icp_handle
.type
),
2198 fs_reg(icp_offset_bytes
),
2199 brw_imm_ud(DIV_ROUND_UP(nir
->info
.gs
.vertices_in
, 8) *
2206 fs_reg tmp_dst
= dst
;
2207 fs_reg indirect_offset
= get_nir_src(offset_src
);
2208 unsigned num_iterations
= 1;
2209 unsigned orig_num_components
= num_components
;
2211 if (type_sz(dst
.type
) == 8) {
2212 if (num_components
> 2) {
2216 fs_reg tmp
= fs_reg(VGRF
, alloc
.allocate(4), dst
.type
);
2218 first_component
= first_component
/ 2;
2221 for (unsigned iter
= 0; iter
< num_iterations
; iter
++) {
2222 if (nir_src_is_const(offset_src
)) {
2223 /* Constant indexing - use global offset. */
2224 if (first_component
!= 0) {
2225 unsigned read_components
= num_components
+ first_component
;
2226 fs_reg tmp
= bld
.vgrf(dst
.type
, read_components
);
2227 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8
, tmp
, icp_handle
);
2228 inst
->size_written
= read_components
*
2229 tmp
.component_size(inst
->exec_size
);
2230 for (unsigned i
= 0; i
< num_components
; i
++) {
2231 bld
.MOV(offset(tmp_dst
, bld
, i
),
2232 offset(tmp
, bld
, i
+ first_component
));
2235 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8
, tmp_dst
,
2237 inst
->size_written
= num_components
*
2238 tmp_dst
.component_size(inst
->exec_size
);
2240 inst
->offset
= base_offset
+ nir_src_as_uint(offset_src
);
2243 /* Indirect indexing - use per-slot offsets as well. */
2244 const fs_reg srcs
[] = { icp_handle
, indirect_offset
};
2245 unsigned read_components
= num_components
+ first_component
;
2246 fs_reg tmp
= bld
.vgrf(dst
.type
, read_components
);
2247 fs_reg payload
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 2);
2248 bld
.LOAD_PAYLOAD(payload
, srcs
, ARRAY_SIZE(srcs
), 0);
2249 if (first_component
!= 0) {
2250 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT
, tmp
,
2252 inst
->size_written
= read_components
*
2253 tmp
.component_size(inst
->exec_size
);
2254 for (unsigned i
= 0; i
< num_components
; i
++) {
2255 bld
.MOV(offset(tmp_dst
, bld
, i
),
2256 offset(tmp
, bld
, i
+ first_component
));
2259 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT
, tmp_dst
,
2261 inst
->size_written
= num_components
*
2262 tmp_dst
.component_size(inst
->exec_size
);
2264 inst
->offset
= base_offset
;
2268 if (type_sz(dst
.type
) == 8) {
2269 shuffle_from_32bit_read(bld
,
2270 offset(dst
, bld
, iter
* 2),
2271 retype(tmp_dst
, BRW_REGISTER_TYPE_D
),
2276 if (num_iterations
> 1) {
2277 num_components
= orig_num_components
- 2;
2278 if(nir_src_is_const(offset_src
)) {
2281 fs_reg new_indirect
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2282 bld
.ADD(new_indirect
, indirect_offset
, brw_imm_ud(1u));
2283 indirect_offset
= new_indirect
;
2290 fs_visitor::get_indirect_offset(nir_intrinsic_instr
*instr
)
2292 nir_src
*offset_src
= nir_get_io_offset_src(instr
);
2294 if (nir_src_is_const(*offset_src
)) {
2295 /* The only constant offset we should find is 0. brw_nir.c's
2296 * add_const_offset_to_base() will fold other constant offsets
2297 * into instr->const_index[0].
2299 assert(nir_src_as_uint(*offset_src
) == 0);
2303 return get_nir_src(*offset_src
);
2307 fs_visitor::nir_emit_vs_intrinsic(const fs_builder
&bld
,
2308 nir_intrinsic_instr
*instr
)
2310 assert(stage
== MESA_SHADER_VERTEX
);
2313 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
2314 dest
= get_nir_dest(instr
->dest
);
2316 switch (instr
->intrinsic
) {
2317 case nir_intrinsic_load_vertex_id
:
2318 case nir_intrinsic_load_base_vertex
:
2319 unreachable("should be lowered by nir_lower_system_values()");
2321 case nir_intrinsic_load_input
: {
2322 fs_reg src
= fs_reg(ATTR
, nir_intrinsic_base(instr
) * 4, dest
.type
);
2323 unsigned first_component
= nir_intrinsic_component(instr
);
2324 unsigned num_components
= instr
->num_components
;
2326 src
= offset(src
, bld
, nir_src_as_uint(instr
->src
[0]));
2328 if (type_sz(dest
.type
) == 8)
2329 first_component
/= 2;
2331 /* For 16-bit support maybe a temporary will be needed to copy from
2334 shuffle_from_32bit_read(bld
, dest
, retype(src
, BRW_REGISTER_TYPE_D
),
2335 first_component
, num_components
);
2339 case nir_intrinsic_load_vertex_id_zero_base
:
2340 case nir_intrinsic_load_instance_id
:
2341 case nir_intrinsic_load_base_instance
:
2342 case nir_intrinsic_load_draw_id
:
2343 case nir_intrinsic_load_first_vertex
:
2344 case nir_intrinsic_load_is_indexed_draw
:
2345 unreachable("lowered by brw_nir_lower_vs_inputs");
2348 nir_emit_intrinsic(bld
, instr
);
2354 fs_visitor::nir_emit_tcs_intrinsic(const fs_builder
&bld
,
2355 nir_intrinsic_instr
*instr
)
2357 assert(stage
== MESA_SHADER_TESS_CTRL
);
2358 struct brw_tcs_prog_key
*tcs_key
= (struct brw_tcs_prog_key
*) key
;
2359 struct brw_tcs_prog_data
*tcs_prog_data
= brw_tcs_prog_data(prog_data
);
2362 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
2363 dst
= get_nir_dest(instr
->dest
);
2365 switch (instr
->intrinsic
) {
2366 case nir_intrinsic_load_primitive_id
:
2367 bld
.MOV(dst
, fs_reg(brw_vec1_grf(0, 1)));
2369 case nir_intrinsic_load_invocation_id
:
2370 bld
.MOV(retype(dst
, invocation_id
.type
), invocation_id
);
2372 case nir_intrinsic_load_patch_vertices_in
:
2373 bld
.MOV(retype(dst
, BRW_REGISTER_TYPE_D
),
2374 brw_imm_d(tcs_key
->input_vertices
));
2377 case nir_intrinsic_barrier
: {
2378 if (tcs_prog_data
->instances
== 1)
2381 fs_reg m0
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2382 fs_reg m0_2
= component(m0
, 2);
2384 const fs_builder chanbld
= bld
.exec_all().group(1, 0);
2386 /* Zero the message header */
2387 bld
.exec_all().MOV(m0
, brw_imm_ud(0u));
2389 /* Copy "Barrier ID" from r0.2, bits 16:13 */
2390 chanbld
.AND(m0_2
, retype(brw_vec1_grf(0, 2), BRW_REGISTER_TYPE_UD
),
2391 brw_imm_ud(INTEL_MASK(16, 13)));
2393 /* Shift it up to bits 27:24. */
2394 chanbld
.SHL(m0_2
, m0_2
, brw_imm_ud(11));
2396 /* Set the Barrier Count and the enable bit */
2397 chanbld
.OR(m0_2
, m0_2
,
2398 brw_imm_ud(tcs_prog_data
->instances
<< 9 | (1 << 15)));
2400 bld
.emit(SHADER_OPCODE_BARRIER
, bld
.null_reg_ud(), m0
);
2404 case nir_intrinsic_load_input
:
2405 unreachable("nir_lower_io should never give us these.");
2408 case nir_intrinsic_load_per_vertex_input
: {
2409 fs_reg indirect_offset
= get_indirect_offset(instr
);
2410 unsigned imm_offset
= instr
->const_index
[0];
2412 const nir_src
&vertex_src
= instr
->src
[0];
2418 if (nir_src_is_const(vertex_src
)) {
2419 /* Emit a MOV to resolve <0,1,0> regioning. */
2420 icp_handle
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2421 unsigned vertex
= nir_src_as_uint(vertex_src
);
2423 retype(brw_vec1_grf(1 + (vertex
>> 3), vertex
& 7),
2424 BRW_REGISTER_TYPE_UD
));
2425 } else if (tcs_prog_data
->instances
== 1 &&
2426 vertex_src
.is_ssa
&&
2427 vertex_src
.ssa
->parent_instr
->type
== nir_instr_type_intrinsic
&&
2428 nir_instr_as_intrinsic(vertex_src
.ssa
->parent_instr
)->intrinsic
== nir_intrinsic_load_invocation_id
) {
2429 /* For the common case of only 1 instance, an array index of
2430 * gl_InvocationID means reading g1. Skip all the indirect work.
2432 icp_handle
= retype(brw_vec8_grf(1, 0), BRW_REGISTER_TYPE_UD
);
2434 /* The vertex index is non-constant. We need to use indirect
2435 * addressing to fetch the proper URB handle.
2437 icp_handle
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2439 /* Each ICP handle is a single DWord (4 bytes) */
2440 fs_reg vertex_offset_bytes
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2441 bld
.SHL(vertex_offset_bytes
,
2442 retype(get_nir_src(vertex_src
), BRW_REGISTER_TYPE_UD
),
2445 /* Start at g1. We might read up to 4 registers. */
2446 bld
.emit(SHADER_OPCODE_MOV_INDIRECT
, icp_handle
,
2447 retype(brw_vec8_grf(1, 0), icp_handle
.type
), vertex_offset_bytes
,
2448 brw_imm_ud(4 * REG_SIZE
));
2451 /* We can only read two double components with each URB read, so
2452 * we send two read messages in that case, each one loading up to
2453 * two double components.
2455 unsigned num_iterations
= 1;
2456 unsigned num_components
= instr
->num_components
;
2457 unsigned first_component
= nir_intrinsic_component(instr
);
2458 fs_reg orig_dst
= dst
;
2459 if (type_sz(dst
.type
) == 8) {
2460 first_component
= first_component
/ 2;
2461 if (instr
->num_components
> 2) {
2466 fs_reg tmp
= fs_reg(VGRF
, alloc
.allocate(4), dst
.type
);
2470 for (unsigned iter
= 0; iter
< num_iterations
; iter
++) {
2471 if (indirect_offset
.file
== BAD_FILE
) {
2472 /* Constant indexing - use global offset. */
2473 if (first_component
!= 0) {
2474 unsigned read_components
= num_components
+ first_component
;
2475 fs_reg tmp
= bld
.vgrf(dst
.type
, read_components
);
2476 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8
, tmp
, icp_handle
);
2477 for (unsigned i
= 0; i
< num_components
; i
++) {
2478 bld
.MOV(offset(dst
, bld
, i
),
2479 offset(tmp
, bld
, i
+ first_component
));
2482 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8
, dst
, icp_handle
);
2484 inst
->offset
= imm_offset
;
2487 /* Indirect indexing - use per-slot offsets as well. */
2488 const fs_reg srcs
[] = { icp_handle
, indirect_offset
};
2489 fs_reg payload
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 2);
2490 bld
.LOAD_PAYLOAD(payload
, srcs
, ARRAY_SIZE(srcs
), 0);
2491 if (first_component
!= 0) {
2492 unsigned read_components
= num_components
+ first_component
;
2493 fs_reg tmp
= bld
.vgrf(dst
.type
, read_components
);
2494 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT
, tmp
,
2496 for (unsigned i
= 0; i
< num_components
; i
++) {
2497 bld
.MOV(offset(dst
, bld
, i
),
2498 offset(tmp
, bld
, i
+ first_component
));
2501 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT
, dst
,
2504 inst
->offset
= imm_offset
;
2507 inst
->size_written
= (num_components
+ first_component
) *
2508 inst
->dst
.component_size(inst
->exec_size
);
2510 /* If we are reading 64-bit data using 32-bit read messages we need
2511 * build proper 64-bit data elements by shuffling the low and high
2512 * 32-bit components around like we do for other things like UBOs
2515 if (type_sz(dst
.type
) == 8) {
2516 shuffle_from_32bit_read(bld
,
2517 offset(orig_dst
, bld
, iter
* 2),
2518 retype(dst
, BRW_REGISTER_TYPE_D
),
2522 /* Copy the temporary to the destination to deal with writemasking.
2524 * Also attempt to deal with gl_PointSize being in the .w component.
2526 if (inst
->offset
== 0 && indirect_offset
.file
== BAD_FILE
) {
2527 assert(type_sz(dst
.type
) < 8);
2528 inst
->dst
= bld
.vgrf(dst
.type
, 4);
2529 inst
->size_written
= 4 * REG_SIZE
;
2530 bld
.MOV(dst
, offset(inst
->dst
, bld
, 3));
2533 /* If we are loading double data and we need a second read message
2534 * adjust the write offset
2536 if (num_iterations
> 1) {
2537 num_components
= instr
->num_components
- 2;
2544 case nir_intrinsic_load_output
:
2545 case nir_intrinsic_load_per_vertex_output
: {
2546 fs_reg indirect_offset
= get_indirect_offset(instr
);
2547 unsigned imm_offset
= instr
->const_index
[0];
2548 unsigned first_component
= nir_intrinsic_component(instr
);
2551 if (indirect_offset
.file
== BAD_FILE
) {
2552 /* Replicate the patch handle to all enabled channels */
2553 fs_reg patch_handle
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2554 bld
.MOV(patch_handle
,
2555 retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_UD
));
2558 if (first_component
!= 0) {
2559 unsigned read_components
=
2560 instr
->num_components
+ first_component
;
2561 fs_reg tmp
= bld
.vgrf(dst
.type
, read_components
);
2562 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8
, tmp
,
2564 inst
->size_written
= read_components
* REG_SIZE
;
2565 for (unsigned i
= 0; i
< instr
->num_components
; i
++) {
2566 bld
.MOV(offset(dst
, bld
, i
),
2567 offset(tmp
, bld
, i
+ first_component
));
2570 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8
, dst
,
2572 inst
->size_written
= instr
->num_components
* REG_SIZE
;
2574 inst
->offset
= imm_offset
;
2578 /* Indirect indexing - use per-slot offsets as well. */
2579 const fs_reg srcs
[] = {
2580 retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_UD
),
2583 fs_reg payload
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 2);
2584 bld
.LOAD_PAYLOAD(payload
, srcs
, ARRAY_SIZE(srcs
), 0);
2585 if (first_component
!= 0) {
2586 unsigned read_components
=
2587 instr
->num_components
+ first_component
;
2588 fs_reg tmp
= bld
.vgrf(dst
.type
, read_components
);
2589 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT
, tmp
,
2591 inst
->size_written
= read_components
* REG_SIZE
;
2592 for (unsigned i
= 0; i
< instr
->num_components
; i
++) {
2593 bld
.MOV(offset(dst
, bld
, i
),
2594 offset(tmp
, bld
, i
+ first_component
));
2597 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT
, dst
,
2599 inst
->size_written
= instr
->num_components
* REG_SIZE
;
2601 inst
->offset
= imm_offset
;
2607 case nir_intrinsic_store_output
:
2608 case nir_intrinsic_store_per_vertex_output
: {
2609 fs_reg value
= get_nir_src(instr
->src
[0]);
2610 bool is_64bit
= (instr
->src
[0].is_ssa
?
2611 instr
->src
[0].ssa
->bit_size
: instr
->src
[0].reg
.reg
->bit_size
) == 64;
2612 fs_reg indirect_offset
= get_indirect_offset(instr
);
2613 unsigned imm_offset
= instr
->const_index
[0];
2614 unsigned mask
= instr
->const_index
[1];
2615 unsigned header_regs
= 0;
2617 srcs
[header_regs
++] = retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_UD
);
2619 if (indirect_offset
.file
!= BAD_FILE
) {
2620 srcs
[header_regs
++] = indirect_offset
;
2626 unsigned num_components
= util_last_bit(mask
);
2629 /* We can only pack two 64-bit components in a single message, so send
2630 * 2 messages if we have more components
2632 unsigned num_iterations
= 1;
2633 unsigned iter_components
= num_components
;
2634 unsigned first_component
= nir_intrinsic_component(instr
);
2636 first_component
= first_component
/ 2;
2637 if (instr
->num_components
> 2) {
2639 iter_components
= 2;
2643 mask
= mask
<< first_component
;
2645 for (unsigned iter
= 0; iter
< num_iterations
; iter
++) {
2646 if (!is_64bit
&& mask
!= WRITEMASK_XYZW
) {
2647 srcs
[header_regs
++] = brw_imm_ud(mask
<< 16);
2648 opcode
= indirect_offset
.file
!= BAD_FILE
?
2649 SHADER_OPCODE_URB_WRITE_SIMD8_MASKED_PER_SLOT
:
2650 SHADER_OPCODE_URB_WRITE_SIMD8_MASKED
;
2651 } else if (is_64bit
&& ((mask
& WRITEMASK_XY
) != WRITEMASK_XY
)) {
2652 /* Expand the 64-bit mask to 32-bit channels. We only handle
2653 * two channels in each iteration, so we only care about X/Y.
2655 unsigned mask32
= 0;
2656 if (mask
& WRITEMASK_X
)
2657 mask32
|= WRITEMASK_XY
;
2658 if (mask
& WRITEMASK_Y
)
2659 mask32
|= WRITEMASK_ZW
;
2661 /* If the mask does not include any of the channels X or Y there
2662 * is nothing to do in this iteration. Move on to the next couple
2663 * of 64-bit channels.
2671 srcs
[header_regs
++] = brw_imm_ud(mask32
<< 16);
2672 opcode
= indirect_offset
.file
!= BAD_FILE
?
2673 SHADER_OPCODE_URB_WRITE_SIMD8_MASKED_PER_SLOT
:
2674 SHADER_OPCODE_URB_WRITE_SIMD8_MASKED
;
2676 opcode
= indirect_offset
.file
!= BAD_FILE
?
2677 SHADER_OPCODE_URB_WRITE_SIMD8_PER_SLOT
:
2678 SHADER_OPCODE_URB_WRITE_SIMD8
;
2681 for (unsigned i
= 0; i
< iter_components
; i
++) {
2682 if (!(mask
& (1 << (i
+ first_component
))))
2686 srcs
[header_regs
+ i
+ first_component
] = offset(value
, bld
, i
);
2688 /* We need to shuffle the 64-bit data to match the layout
2689 * expected by our 32-bit URB write messages. We use a temporary
2692 unsigned channel
= iter
* 2 + i
;
2693 fs_reg dest
= shuffle_for_32bit_write(bld
, value
, channel
, 1);
2695 srcs
[header_regs
+ (i
+ first_component
) * 2] = dest
;
2696 srcs
[header_regs
+ (i
+ first_component
) * 2 + 1] =
2697 offset(dest
, bld
, 1);
2702 header_regs
+ (is_64bit
? 2 * iter_components
: iter_components
) +
2703 (is_64bit
? 2 * first_component
: first_component
);
2705 bld
.vgrf(BRW_REGISTER_TYPE_UD
, mlen
);
2706 bld
.LOAD_PAYLOAD(payload
, srcs
, mlen
, header_regs
);
2708 fs_inst
*inst
= bld
.emit(opcode
, bld
.null_reg_ud(), payload
);
2709 inst
->offset
= imm_offset
;
2712 /* If this is a 64-bit attribute, select the next two 64-bit channels
2713 * to be handled in the next iteration.
2724 nir_emit_intrinsic(bld
, instr
);
2730 fs_visitor::nir_emit_tes_intrinsic(const fs_builder
&bld
,
2731 nir_intrinsic_instr
*instr
)
2733 assert(stage
== MESA_SHADER_TESS_EVAL
);
2734 struct brw_tes_prog_data
*tes_prog_data
= brw_tes_prog_data(prog_data
);
2737 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
2738 dest
= get_nir_dest(instr
->dest
);
2740 switch (instr
->intrinsic
) {
2741 case nir_intrinsic_load_primitive_id
:
2742 bld
.MOV(dest
, fs_reg(brw_vec1_grf(0, 1)));
2744 case nir_intrinsic_load_tess_coord
:
2745 /* gl_TessCoord is part of the payload in g1-3 */
2746 for (unsigned i
= 0; i
< 3; i
++) {
2747 bld
.MOV(offset(dest
, bld
, i
), fs_reg(brw_vec8_grf(1 + i
, 0)));
2751 case nir_intrinsic_load_input
:
2752 case nir_intrinsic_load_per_vertex_input
: {
2753 fs_reg indirect_offset
= get_indirect_offset(instr
);
2754 unsigned imm_offset
= instr
->const_index
[0];
2755 unsigned first_component
= nir_intrinsic_component(instr
);
2757 if (type_sz(dest
.type
) == 8) {
2758 first_component
= first_component
/ 2;
2762 if (indirect_offset
.file
== BAD_FILE
) {
2763 /* Arbitrarily only push up to 32 vec4 slots worth of data,
2764 * which is 16 registers (since each holds 2 vec4 slots).
2766 unsigned slot_count
= 1;
2767 if (type_sz(dest
.type
) == 8 && instr
->num_components
> 2)
2770 const unsigned max_push_slots
= 32;
2771 if (imm_offset
+ slot_count
<= max_push_slots
) {
2772 fs_reg src
= fs_reg(ATTR
, imm_offset
/ 2, dest
.type
);
2773 for (int i
= 0; i
< instr
->num_components
; i
++) {
2774 unsigned comp
= 16 / type_sz(dest
.type
) * (imm_offset
% 2) +
2775 i
+ first_component
;
2776 bld
.MOV(offset(dest
, bld
, i
), component(src
, comp
));
2779 tes_prog_data
->base
.urb_read_length
=
2780 MAX2(tes_prog_data
->base
.urb_read_length
,
2781 DIV_ROUND_UP(imm_offset
+ slot_count
, 2));
2783 /* Replicate the patch handle to all enabled channels */
2784 const fs_reg srcs
[] = {
2785 retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_UD
)
2787 fs_reg patch_handle
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2788 bld
.LOAD_PAYLOAD(patch_handle
, srcs
, ARRAY_SIZE(srcs
), 0);
2790 if (first_component
!= 0) {
2791 unsigned read_components
=
2792 instr
->num_components
+ first_component
;
2793 fs_reg tmp
= bld
.vgrf(dest
.type
, read_components
);
2794 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8
, tmp
,
2796 inst
->size_written
= read_components
* REG_SIZE
;
2797 for (unsigned i
= 0; i
< instr
->num_components
; i
++) {
2798 bld
.MOV(offset(dest
, bld
, i
),
2799 offset(tmp
, bld
, i
+ first_component
));
2802 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8
, dest
,
2804 inst
->size_written
= instr
->num_components
* REG_SIZE
;
2807 inst
->offset
= imm_offset
;
2810 /* Indirect indexing - use per-slot offsets as well. */
2812 /* We can only read two double components with each URB read, so
2813 * we send two read messages in that case, each one loading up to
2814 * two double components.
2816 unsigned num_iterations
= 1;
2817 unsigned num_components
= instr
->num_components
;
2818 fs_reg orig_dest
= dest
;
2819 if (type_sz(dest
.type
) == 8) {
2820 if (instr
->num_components
> 2) {
2824 fs_reg tmp
= fs_reg(VGRF
, alloc
.allocate(4), dest
.type
);
2828 for (unsigned iter
= 0; iter
< num_iterations
; iter
++) {
2829 const fs_reg srcs
[] = {
2830 retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_UD
),
2833 fs_reg payload
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 2);
2834 bld
.LOAD_PAYLOAD(payload
, srcs
, ARRAY_SIZE(srcs
), 0);
2836 if (first_component
!= 0) {
2837 unsigned read_components
=
2838 num_components
+ first_component
;
2839 fs_reg tmp
= bld
.vgrf(dest
.type
, read_components
);
2840 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT
, tmp
,
2842 for (unsigned i
= 0; i
< num_components
; i
++) {
2843 bld
.MOV(offset(dest
, bld
, i
),
2844 offset(tmp
, bld
, i
+ first_component
));
2847 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT
, dest
,
2851 inst
->offset
= imm_offset
;
2852 inst
->size_written
= (num_components
+ first_component
) *
2853 inst
->dst
.component_size(inst
->exec_size
);
2855 /* If we are reading 64-bit data using 32-bit read messages we need
2856 * build proper 64-bit data elements by shuffling the low and high
2857 * 32-bit components around like we do for other things like UBOs
2860 if (type_sz(dest
.type
) == 8) {
2861 shuffle_from_32bit_read(bld
,
2862 offset(orig_dest
, bld
, iter
* 2),
2863 retype(dest
, BRW_REGISTER_TYPE_D
),
2867 /* If we are loading double data and we need a second read message
2870 if (num_iterations
> 1) {
2871 num_components
= instr
->num_components
- 2;
2879 nir_emit_intrinsic(bld
, instr
);
2885 fs_visitor::nir_emit_gs_intrinsic(const fs_builder
&bld
,
2886 nir_intrinsic_instr
*instr
)
2888 assert(stage
== MESA_SHADER_GEOMETRY
);
2889 fs_reg indirect_offset
;
2892 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
2893 dest
= get_nir_dest(instr
->dest
);
2895 switch (instr
->intrinsic
) {
2896 case nir_intrinsic_load_primitive_id
:
2897 assert(stage
== MESA_SHADER_GEOMETRY
);
2898 assert(brw_gs_prog_data(prog_data
)->include_primitive_id
);
2899 bld
.MOV(retype(dest
, BRW_REGISTER_TYPE_UD
),
2900 retype(fs_reg(brw_vec8_grf(2, 0)), BRW_REGISTER_TYPE_UD
));
2903 case nir_intrinsic_load_input
:
2904 unreachable("load_input intrinsics are invalid for the GS stage");
2906 case nir_intrinsic_load_per_vertex_input
:
2907 emit_gs_input_load(dest
, instr
->src
[0], instr
->const_index
[0],
2908 instr
->src
[1], instr
->num_components
,
2909 nir_intrinsic_component(instr
));
2912 case nir_intrinsic_emit_vertex_with_counter
:
2913 emit_gs_vertex(instr
->src
[0], instr
->const_index
[0]);
2916 case nir_intrinsic_end_primitive_with_counter
:
2917 emit_gs_end_primitive(instr
->src
[0]);
2920 case nir_intrinsic_set_vertex_count
:
2921 bld
.MOV(this->final_gs_vertex_count
, get_nir_src(instr
->src
[0]));
2924 case nir_intrinsic_load_invocation_id
: {
2925 fs_reg val
= nir_system_values
[SYSTEM_VALUE_INVOCATION_ID
];
2926 assert(val
.file
!= BAD_FILE
);
2927 dest
.type
= val
.type
;
2933 nir_emit_intrinsic(bld
, instr
);
2939 * Fetch the current render target layer index.
2942 fetch_render_target_array_index(const fs_builder
&bld
)
2944 if (bld
.shader
->devinfo
->gen
>= 6) {
2945 /* The render target array index is provided in the thread payload as
2946 * bits 26:16 of r0.0.
2948 const fs_reg idx
= bld
.vgrf(BRW_REGISTER_TYPE_UD
);
2949 bld
.AND(idx
, brw_uw1_reg(BRW_GENERAL_REGISTER_FILE
, 0, 1),
2953 /* Pre-SNB we only ever render into the first layer of the framebuffer
2954 * since layered rendering is not implemented.
2956 return brw_imm_ud(0);
2961 * Fake non-coherent framebuffer read implemented using TXF to fetch from the
2962 * framebuffer at the current fragment coordinates and sample index.
2965 fs_visitor::emit_non_coherent_fb_read(const fs_builder
&bld
, const fs_reg
&dst
,
2968 const struct gen_device_info
*devinfo
= bld
.shader
->devinfo
;
2970 assert(bld
.shader
->stage
== MESA_SHADER_FRAGMENT
);
2971 const brw_wm_prog_key
*wm_key
=
2972 reinterpret_cast<const brw_wm_prog_key
*>(key
);
2973 assert(!wm_key
->coherent_fb_fetch
);
2974 const struct brw_wm_prog_data
*wm_prog_data
=
2975 brw_wm_prog_data(stage_prog_data
);
2977 /* Calculate the surface index relative to the start of the texture binding
2978 * table block, since that's what the texturing messages expect.
2980 const unsigned surface
= target
+
2981 wm_prog_data
->binding_table
.render_target_read_start
-
2982 wm_prog_data
->base
.binding_table
.texture_start
;
2984 /* Calculate the fragment coordinates. */
2985 const fs_reg coords
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 3);
2986 bld
.MOV(offset(coords
, bld
, 0), pixel_x
);
2987 bld
.MOV(offset(coords
, bld
, 1), pixel_y
);
2988 bld
.MOV(offset(coords
, bld
, 2), fetch_render_target_array_index(bld
));
2990 /* Calculate the sample index and MCS payload when multisampling. Luckily
2991 * the MCS fetch message behaves deterministically for UMS surfaces, so it
2992 * shouldn't be necessary to recompile based on whether the framebuffer is
2995 if (wm_key
->multisample_fbo
&&
2996 nir_system_values
[SYSTEM_VALUE_SAMPLE_ID
].file
== BAD_FILE
)
2997 nir_system_values
[SYSTEM_VALUE_SAMPLE_ID
] = *emit_sampleid_setup();
2999 const fs_reg sample
= nir_system_values
[SYSTEM_VALUE_SAMPLE_ID
];
3000 const fs_reg mcs
= wm_key
->multisample_fbo
?
3001 emit_mcs_fetch(coords
, 3, brw_imm_ud(surface
)) : fs_reg();
3003 /* Use either a normal or a CMS texel fetch message depending on whether
3004 * the framebuffer is single or multisample. On SKL+ use the wide CMS
3005 * message just in case the framebuffer uses 16x multisampling, it should
3006 * be equivalent to the normal CMS fetch for lower multisampling modes.
3008 const opcode op
= !wm_key
->multisample_fbo
? SHADER_OPCODE_TXF_LOGICAL
:
3009 devinfo
->gen
>= 9 ? SHADER_OPCODE_TXF_CMS_W_LOGICAL
:
3010 SHADER_OPCODE_TXF_CMS_LOGICAL
;
3012 /* Emit the instruction. */
3013 fs_reg srcs
[TEX_LOGICAL_NUM_SRCS
];
3014 srcs
[TEX_LOGICAL_SRC_COORDINATE
] = coords
;
3015 srcs
[TEX_LOGICAL_SRC_LOD
] = brw_imm_ud(0);
3016 srcs
[TEX_LOGICAL_SRC_SAMPLE_INDEX
] = sample
;
3017 srcs
[TEX_LOGICAL_SRC_MCS
] = mcs
;
3018 srcs
[TEX_LOGICAL_SRC_SURFACE
] = brw_imm_ud(surface
);
3019 srcs
[TEX_LOGICAL_SRC_SAMPLER
] = brw_imm_ud(0);
3020 srcs
[TEX_LOGICAL_SRC_COORD_COMPONENTS
] = brw_imm_ud(3);
3021 srcs
[TEX_LOGICAL_SRC_GRAD_COMPONENTS
] = brw_imm_ud(0);
3023 fs_inst
*inst
= bld
.emit(op
, dst
, srcs
, ARRAY_SIZE(srcs
));
3024 inst
->size_written
= 4 * inst
->dst
.component_size(inst
->exec_size
);
3030 * Actual coherent framebuffer read implemented using the native render target
3031 * read message. Requires SKL+.
3034 emit_coherent_fb_read(const fs_builder
&bld
, const fs_reg
&dst
, unsigned target
)
3036 assert(bld
.shader
->devinfo
->gen
>= 9);
3037 fs_inst
*inst
= bld
.emit(FS_OPCODE_FB_READ_LOGICAL
, dst
);
3038 inst
->target
= target
;
3039 inst
->size_written
= 4 * inst
->dst
.component_size(inst
->exec_size
);
3045 alloc_temporary(const fs_builder
&bld
, unsigned size
, fs_reg
*regs
, unsigned n
)
3047 if (n
&& regs
[0].file
!= BAD_FILE
) {
3051 const fs_reg tmp
= bld
.vgrf(BRW_REGISTER_TYPE_F
, size
);
3053 for (unsigned i
= 0; i
< n
; i
++)
3061 alloc_frag_output(fs_visitor
*v
, unsigned location
)
3063 assert(v
->stage
== MESA_SHADER_FRAGMENT
);
3064 const brw_wm_prog_key
*const key
=
3065 reinterpret_cast<const brw_wm_prog_key
*>(v
->key
);
3066 const unsigned l
= GET_FIELD(location
, BRW_NIR_FRAG_OUTPUT_LOCATION
);
3067 const unsigned i
= GET_FIELD(location
, BRW_NIR_FRAG_OUTPUT_INDEX
);
3069 if (i
> 0 || (key
->force_dual_color_blend
&& l
== FRAG_RESULT_DATA1
))
3070 return alloc_temporary(v
->bld
, 4, &v
->dual_src_output
, 1);
3072 else if (l
== FRAG_RESULT_COLOR
)
3073 return alloc_temporary(v
->bld
, 4, v
->outputs
,
3074 MAX2(key
->nr_color_regions
, 1));
3076 else if (l
== FRAG_RESULT_DEPTH
)
3077 return alloc_temporary(v
->bld
, 1, &v
->frag_depth
, 1);
3079 else if (l
== FRAG_RESULT_STENCIL
)
3080 return alloc_temporary(v
->bld
, 1, &v
->frag_stencil
, 1);
3082 else if (l
== FRAG_RESULT_SAMPLE_MASK
)
3083 return alloc_temporary(v
->bld
, 1, &v
->sample_mask
, 1);
3085 else if (l
>= FRAG_RESULT_DATA0
&&
3086 l
< FRAG_RESULT_DATA0
+ BRW_MAX_DRAW_BUFFERS
)
3087 return alloc_temporary(v
->bld
, 4,
3088 &v
->outputs
[l
- FRAG_RESULT_DATA0
], 1);
3091 unreachable("Invalid location");
3095 fs_visitor::nir_emit_fs_intrinsic(const fs_builder
&bld
,
3096 nir_intrinsic_instr
*instr
)
3098 assert(stage
== MESA_SHADER_FRAGMENT
);
3101 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
3102 dest
= get_nir_dest(instr
->dest
);
3104 switch (instr
->intrinsic
) {
3105 case nir_intrinsic_load_front_face
:
3106 bld
.MOV(retype(dest
, BRW_REGISTER_TYPE_D
),
3107 *emit_frontfacing_interpolation());
3110 case nir_intrinsic_load_sample_pos
: {
3111 fs_reg sample_pos
= nir_system_values
[SYSTEM_VALUE_SAMPLE_POS
];
3112 assert(sample_pos
.file
!= BAD_FILE
);
3113 dest
.type
= sample_pos
.type
;
3114 bld
.MOV(dest
, sample_pos
);
3115 bld
.MOV(offset(dest
, bld
, 1), offset(sample_pos
, bld
, 1));
3119 case nir_intrinsic_load_layer_id
:
3120 dest
.type
= BRW_REGISTER_TYPE_UD
;
3121 bld
.MOV(dest
, fetch_render_target_array_index(bld
));
3124 case nir_intrinsic_load_helper_invocation
:
3125 case nir_intrinsic_load_sample_mask_in
:
3126 case nir_intrinsic_load_sample_id
: {
3127 gl_system_value sv
= nir_system_value_from_intrinsic(instr
->intrinsic
);
3128 fs_reg val
= nir_system_values
[sv
];
3129 assert(val
.file
!= BAD_FILE
);
3130 dest
.type
= val
.type
;
3135 case nir_intrinsic_store_output
: {
3136 const fs_reg src
= get_nir_src(instr
->src
[0]);
3137 const unsigned store_offset
= nir_src_as_uint(instr
->src
[1]);
3138 const unsigned location
= nir_intrinsic_base(instr
) +
3139 SET_FIELD(store_offset
, BRW_NIR_FRAG_OUTPUT_LOCATION
);
3140 const fs_reg new_dest
= retype(alloc_frag_output(this, location
),
3143 for (unsigned j
= 0; j
< instr
->num_components
; j
++)
3144 bld
.MOV(offset(new_dest
, bld
, nir_intrinsic_component(instr
) + j
),
3145 offset(src
, bld
, j
));
3150 case nir_intrinsic_load_output
: {
3151 const unsigned l
= GET_FIELD(nir_intrinsic_base(instr
),
3152 BRW_NIR_FRAG_OUTPUT_LOCATION
);
3153 assert(l
>= FRAG_RESULT_DATA0
);
3154 const unsigned load_offset
= nir_src_as_uint(instr
->src
[0]);
3155 const unsigned target
= l
- FRAG_RESULT_DATA0
+ load_offset
;
3156 const fs_reg tmp
= bld
.vgrf(dest
.type
, 4);
3158 if (reinterpret_cast<const brw_wm_prog_key
*>(key
)->coherent_fb_fetch
)
3159 emit_coherent_fb_read(bld
, tmp
, target
);
3161 emit_non_coherent_fb_read(bld
, tmp
, target
);
3163 for (unsigned j
= 0; j
< instr
->num_components
; j
++) {
3164 bld
.MOV(offset(dest
, bld
, j
),
3165 offset(tmp
, bld
, nir_intrinsic_component(instr
) + j
));
3171 case nir_intrinsic_discard
:
3172 case nir_intrinsic_discard_if
: {
3173 /* We track our discarded pixels in f0.1. By predicating on it, we can
3174 * update just the flag bits that aren't yet discarded. If there's no
3175 * condition, we emit a CMP of g0 != g0, so all currently executing
3176 * channels will get turned off.
3179 if (instr
->intrinsic
== nir_intrinsic_discard_if
) {
3180 cmp
= bld
.CMP(bld
.null_reg_f(), get_nir_src(instr
->src
[0]),
3181 brw_imm_d(0), BRW_CONDITIONAL_Z
);
3183 fs_reg some_reg
= fs_reg(retype(brw_vec8_grf(0, 0),
3184 BRW_REGISTER_TYPE_UW
));
3185 cmp
= bld
.CMP(bld
.null_reg_f(), some_reg
, some_reg
, BRW_CONDITIONAL_NZ
);
3187 cmp
->predicate
= BRW_PREDICATE_NORMAL
;
3188 cmp
->flag_subreg
= 1;
3190 if (devinfo
->gen
>= 6) {
3191 emit_discard_jump();
3194 limit_dispatch_width(16, "Fragment discard not implemented in SIMD32 mode.");
3198 case nir_intrinsic_load_input
: {
3199 /* load_input is only used for flat inputs */
3200 unsigned base
= nir_intrinsic_base(instr
);
3201 unsigned comp
= nir_intrinsic_component(instr
);
3202 unsigned num_components
= instr
->num_components
;
3203 fs_reg orig_dest
= dest
;
3204 enum brw_reg_type type
= dest
.type
;
3206 /* Special case fields in the VUE header */
3207 if (base
== VARYING_SLOT_LAYER
)
3209 else if (base
== VARYING_SLOT_VIEWPORT
)
3212 if (nir_dest_bit_size(instr
->dest
) == 64) {
3213 /* const_index is in 32-bit type size units that could not be aligned
3214 * with DF. We need to read the double vector as if it was a float
3215 * vector of twice the number of components to fetch the right data.
3217 type
= BRW_REGISTER_TYPE_F
;
3218 num_components
*= 2;
3219 dest
= bld
.vgrf(type
, num_components
);
3222 for (unsigned int i
= 0; i
< num_components
; i
++) {
3223 bld
.MOV(offset(retype(dest
, type
), bld
, i
),
3224 retype(component(interp_reg(base
, comp
+ i
), 3), type
));
3227 if (nir_dest_bit_size(instr
->dest
) == 64) {
3228 shuffle_from_32bit_read(bld
, orig_dest
, dest
, 0,
3229 instr
->num_components
);
3234 case nir_intrinsic_load_barycentric_pixel
:
3235 case nir_intrinsic_load_barycentric_centroid
:
3236 case nir_intrinsic_load_barycentric_sample
:
3237 /* Do nothing - load_interpolated_input handling will handle it later. */
3240 case nir_intrinsic_load_barycentric_at_sample
: {
3241 const glsl_interp_mode interpolation
=
3242 (enum glsl_interp_mode
) nir_intrinsic_interp_mode(instr
);
3244 if (nir_src_is_const(instr
->src
[0])) {
3245 unsigned msg_data
= nir_src_as_uint(instr
->src
[0]) << 4;
3247 emit_pixel_interpolater_send(bld
,
3248 FS_OPCODE_INTERPOLATE_AT_SAMPLE
,
3251 brw_imm_ud(msg_data
),
3254 const fs_reg sample_src
= retype(get_nir_src(instr
->src
[0]),
3255 BRW_REGISTER_TYPE_UD
);
3257 if (nir_src_is_dynamically_uniform(instr
->src
[0])) {
3258 const fs_reg sample_id
= bld
.emit_uniformize(sample_src
);
3259 const fs_reg msg_data
= vgrf(glsl_type::uint_type
);
3260 bld
.exec_all().group(1, 0)
3261 .SHL(msg_data
, sample_id
, brw_imm_ud(4u));
3262 emit_pixel_interpolater_send(bld
,
3263 FS_OPCODE_INTERPOLATE_AT_SAMPLE
,
3269 /* Make a loop that sends a message to the pixel interpolater
3270 * for the sample number in each live channel. If there are
3271 * multiple channels with the same sample number then these
3272 * will be handled simultaneously with a single interation of
3275 bld
.emit(BRW_OPCODE_DO
);
3277 /* Get the next live sample number into sample_id_reg */
3278 const fs_reg sample_id
= bld
.emit_uniformize(sample_src
);
3280 /* Set the flag register so that we can perform the send
3281 * message on all channels that have the same sample number
3283 bld
.CMP(bld
.null_reg_ud(),
3284 sample_src
, sample_id
,
3285 BRW_CONDITIONAL_EQ
);
3286 const fs_reg msg_data
= vgrf(glsl_type::uint_type
);
3287 bld
.exec_all().group(1, 0)
3288 .SHL(msg_data
, sample_id
, brw_imm_ud(4u));
3290 emit_pixel_interpolater_send(bld
,
3291 FS_OPCODE_INTERPOLATE_AT_SAMPLE
,
3294 component(msg_data
, 0),
3296 set_predicate(BRW_PREDICATE_NORMAL
, inst
);
3298 /* Continue the loop if there are any live channels left */
3299 set_predicate_inv(BRW_PREDICATE_NORMAL
,
3301 bld
.emit(BRW_OPCODE_WHILE
));
3307 case nir_intrinsic_load_barycentric_at_offset
: {
3308 const glsl_interp_mode interpolation
=
3309 (enum glsl_interp_mode
) nir_intrinsic_interp_mode(instr
);
3311 nir_const_value
*const_offset
= nir_src_as_const_value(instr
->src
[0]);
3314 assert(nir_src_bit_size(instr
->src
[0]) == 32);
3315 unsigned off_x
= MIN2((int)(const_offset
->f32
[0] * 16), 7) & 0xf;
3316 unsigned off_y
= MIN2((int)(const_offset
->f32
[1] * 16), 7) & 0xf;
3318 emit_pixel_interpolater_send(bld
,
3319 FS_OPCODE_INTERPOLATE_AT_SHARED_OFFSET
,
3322 brw_imm_ud(off_x
| (off_y
<< 4)),
3325 fs_reg src
= vgrf(glsl_type::ivec2_type
);
3326 fs_reg offset_src
= retype(get_nir_src(instr
->src
[0]),
3327 BRW_REGISTER_TYPE_F
);
3328 for (int i
= 0; i
< 2; i
++) {
3329 fs_reg temp
= vgrf(glsl_type::float_type
);
3330 bld
.MUL(temp
, offset(offset_src
, bld
, i
), brw_imm_f(16.0f
));
3331 fs_reg itemp
= vgrf(glsl_type::int_type
);
3333 bld
.MOV(itemp
, temp
);
3335 /* Clamp the upper end of the range to +7/16.
3336 * ARB_gpu_shader5 requires that we support a maximum offset
3337 * of +0.5, which isn't representable in a S0.4 value -- if
3338 * we didn't clamp it, we'd end up with -8/16, which is the
3339 * opposite of what the shader author wanted.
3341 * This is legal due to ARB_gpu_shader5's quantization
3344 * "Not all values of <offset> may be supported; x and y
3345 * offsets may be rounded to fixed-point values with the
3346 * number of fraction bits given by the
3347 * implementation-dependent constant
3348 * FRAGMENT_INTERPOLATION_OFFSET_BITS"
3350 set_condmod(BRW_CONDITIONAL_L
,
3351 bld
.SEL(offset(src
, bld
, i
), itemp
, brw_imm_d(7)));
3354 const enum opcode opcode
= FS_OPCODE_INTERPOLATE_AT_PER_SLOT_OFFSET
;
3355 emit_pixel_interpolater_send(bld
,
3365 case nir_intrinsic_load_interpolated_input
: {
3366 if (nir_intrinsic_base(instr
) == VARYING_SLOT_POS
) {
3367 emit_fragcoord_interpolation(dest
);
3371 assert(instr
->src
[0].ssa
&&
3372 instr
->src
[0].ssa
->parent_instr
->type
== nir_instr_type_intrinsic
);
3373 nir_intrinsic_instr
*bary_intrinsic
=
3374 nir_instr_as_intrinsic(instr
->src
[0].ssa
->parent_instr
);
3375 nir_intrinsic_op bary_intrin
= bary_intrinsic
->intrinsic
;
3376 enum glsl_interp_mode interp_mode
=
3377 (enum glsl_interp_mode
) nir_intrinsic_interp_mode(bary_intrinsic
);
3380 if (bary_intrin
== nir_intrinsic_load_barycentric_at_offset
||
3381 bary_intrin
== nir_intrinsic_load_barycentric_at_sample
) {
3382 /* Use the result of the PI message */
3383 dst_xy
= retype(get_nir_src(instr
->src
[0]), BRW_REGISTER_TYPE_F
);
3385 /* Use the delta_xy values computed from the payload */
3386 enum brw_barycentric_mode bary
=
3387 brw_barycentric_mode(interp_mode
, bary_intrin
);
3389 dst_xy
= this->delta_xy
[bary
];
3392 for (unsigned int i
= 0; i
< instr
->num_components
; i
++) {
3394 component(interp_reg(nir_intrinsic_base(instr
),
3395 nir_intrinsic_component(instr
) + i
), 0);
3396 interp
.type
= BRW_REGISTER_TYPE_F
;
3397 dest
.type
= BRW_REGISTER_TYPE_F
;
3399 if (devinfo
->gen
< 6 && interp_mode
== INTERP_MODE_SMOOTH
) {
3400 fs_reg tmp
= vgrf(glsl_type::float_type
);
3401 bld
.emit(FS_OPCODE_LINTERP
, tmp
, dst_xy
, interp
);
3402 bld
.MUL(offset(dest
, bld
, i
), tmp
, this->pixel_w
);
3404 bld
.emit(FS_OPCODE_LINTERP
, offset(dest
, bld
, i
), dst_xy
, interp
);
3411 nir_emit_intrinsic(bld
, instr
);
3417 get_op_for_atomic_add(nir_intrinsic_instr
*instr
, unsigned src
)
3419 if (nir_src_is_const(instr
->src
[src
])) {
3420 int64_t add_val
= nir_src_as_int(instr
->src
[src
]);
3423 else if (add_val
== -1)
3431 fs_visitor::nir_emit_cs_intrinsic(const fs_builder
&bld
,
3432 nir_intrinsic_instr
*instr
)
3434 assert(stage
== MESA_SHADER_COMPUTE
);
3435 struct brw_cs_prog_data
*cs_prog_data
= brw_cs_prog_data(prog_data
);
3438 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
3439 dest
= get_nir_dest(instr
->dest
);
3441 switch (instr
->intrinsic
) {
3442 case nir_intrinsic_barrier
:
3444 cs_prog_data
->uses_barrier
= true;
3447 case nir_intrinsic_load_subgroup_id
:
3448 bld
.MOV(retype(dest
, BRW_REGISTER_TYPE_UD
), subgroup_id
);
3451 case nir_intrinsic_load_local_invocation_id
:
3452 case nir_intrinsic_load_work_group_id
: {
3453 gl_system_value sv
= nir_system_value_from_intrinsic(instr
->intrinsic
);
3454 fs_reg val
= nir_system_values
[sv
];
3455 assert(val
.file
!= BAD_FILE
);
3456 dest
.type
= val
.type
;
3457 for (unsigned i
= 0; i
< 3; i
++)
3458 bld
.MOV(offset(dest
, bld
, i
), offset(val
, bld
, i
));
3462 case nir_intrinsic_load_num_work_groups
: {
3463 const unsigned surface
=
3464 cs_prog_data
->binding_table
.work_groups_start
;
3466 cs_prog_data
->uses_num_work_groups
= true;
3468 fs_reg srcs
[SURFACE_LOGICAL_NUM_SRCS
];
3469 srcs
[SURFACE_LOGICAL_SRC_SURFACE
] = brw_imm_ud(surface
);
3470 srcs
[SURFACE_LOGICAL_SRC_IMM_DIMS
] = brw_imm_ud(1);
3471 srcs
[SURFACE_LOGICAL_SRC_IMM_ARG
] = brw_imm_ud(1); /* num components */
3473 /* Read the 3 GLuint components of gl_NumWorkGroups */
3474 for (unsigned i
= 0; i
< 3; i
++) {
3475 srcs
[SURFACE_LOGICAL_SRC_ADDRESS
] = brw_imm_ud(i
<< 2);
3476 bld
.emit(SHADER_OPCODE_UNTYPED_SURFACE_READ_LOGICAL
,
3477 offset(dest
, bld
, i
), srcs
, SURFACE_LOGICAL_NUM_SRCS
);
3482 case nir_intrinsic_shared_atomic_add
:
3483 nir_emit_shared_atomic(bld
, get_op_for_atomic_add(instr
, 1), instr
);
3485 case nir_intrinsic_shared_atomic_imin
:
3486 nir_emit_shared_atomic(bld
, BRW_AOP_IMIN
, instr
);
3488 case nir_intrinsic_shared_atomic_umin
:
3489 nir_emit_shared_atomic(bld
, BRW_AOP_UMIN
, instr
);
3491 case nir_intrinsic_shared_atomic_imax
:
3492 nir_emit_shared_atomic(bld
, BRW_AOP_IMAX
, instr
);
3494 case nir_intrinsic_shared_atomic_umax
:
3495 nir_emit_shared_atomic(bld
, BRW_AOP_UMAX
, instr
);
3497 case nir_intrinsic_shared_atomic_and
:
3498 nir_emit_shared_atomic(bld
, BRW_AOP_AND
, instr
);
3500 case nir_intrinsic_shared_atomic_or
:
3501 nir_emit_shared_atomic(bld
, BRW_AOP_OR
, instr
);
3503 case nir_intrinsic_shared_atomic_xor
:
3504 nir_emit_shared_atomic(bld
, BRW_AOP_XOR
, instr
);
3506 case nir_intrinsic_shared_atomic_exchange
:
3507 nir_emit_shared_atomic(bld
, BRW_AOP_MOV
, instr
);
3509 case nir_intrinsic_shared_atomic_comp_swap
:
3510 nir_emit_shared_atomic(bld
, BRW_AOP_CMPWR
, instr
);
3512 case nir_intrinsic_shared_atomic_fmin
:
3513 nir_emit_shared_atomic_float(bld
, BRW_AOP_FMIN
, instr
);
3515 case nir_intrinsic_shared_atomic_fmax
:
3516 nir_emit_shared_atomic_float(bld
, BRW_AOP_FMAX
, instr
);
3518 case nir_intrinsic_shared_atomic_fcomp_swap
:
3519 nir_emit_shared_atomic_float(bld
, BRW_AOP_FCMPWR
, instr
);
3522 case nir_intrinsic_load_shared
: {
3523 assert(devinfo
->gen
>= 7);
3524 assert(stage
== MESA_SHADER_COMPUTE
);
3526 const unsigned bit_size
= nir_dest_bit_size(instr
->dest
);
3527 fs_reg srcs
[SURFACE_LOGICAL_NUM_SRCS
];
3528 srcs
[SURFACE_LOGICAL_SRC_SURFACE
] = brw_imm_ud(GEN7_BTI_SLM
);
3529 srcs
[SURFACE_LOGICAL_SRC_ADDRESS
] = get_nir_src(instr
->src
[0]);
3530 srcs
[SURFACE_LOGICAL_SRC_IMM_DIMS
] = brw_imm_ud(1);
3532 /* Make dest unsigned because that's what the temporary will be */
3533 dest
.type
= brw_reg_type_from_bit_size(bit_size
, BRW_REGISTER_TYPE_UD
);
3535 /* Read the vector */
3536 if (nir_intrinsic_align(instr
) >= 4) {
3537 assert(nir_dest_bit_size(instr
->dest
) == 32);
3538 srcs
[SURFACE_LOGICAL_SRC_IMM_ARG
] = brw_imm_ud(instr
->num_components
);
3540 bld
.emit(SHADER_OPCODE_UNTYPED_SURFACE_READ_LOGICAL
,
3541 dest
, srcs
, SURFACE_LOGICAL_NUM_SRCS
);
3542 inst
->size_written
= instr
->num_components
* dispatch_width
* 4;
3544 assert(nir_dest_bit_size(instr
->dest
) <= 32);
3545 assert(nir_dest_num_components(instr
->dest
) == 1);
3546 srcs
[SURFACE_LOGICAL_SRC_IMM_ARG
] = brw_imm_ud(bit_size
);
3548 fs_reg read_result
= bld
.vgrf(BRW_REGISTER_TYPE_UD
);
3549 bld
.emit(SHADER_OPCODE_BYTE_SCATTERED_READ_LOGICAL
,
3550 read_result
, srcs
, SURFACE_LOGICAL_NUM_SRCS
);
3551 bld
.MOV(dest
, read_result
);
3556 case nir_intrinsic_store_shared
: {
3557 assert(devinfo
->gen
>= 7);
3558 assert(stage
== MESA_SHADER_COMPUTE
);
3560 const unsigned bit_size
= nir_src_bit_size(instr
->src
[0]);
3561 fs_reg srcs
[SURFACE_LOGICAL_NUM_SRCS
];
3562 srcs
[SURFACE_LOGICAL_SRC_SURFACE
] = brw_imm_ud(GEN7_BTI_SLM
);
3563 srcs
[SURFACE_LOGICAL_SRC_ADDRESS
] = get_nir_src(instr
->src
[1]);
3564 srcs
[SURFACE_LOGICAL_SRC_IMM_DIMS
] = brw_imm_ud(1);
3566 fs_reg data
= get_nir_src(instr
->src
[0]);
3567 data
.type
= brw_reg_type_from_bit_size(bit_size
, BRW_REGISTER_TYPE_UD
);
3569 assert(nir_intrinsic_write_mask(instr
) ==
3570 (1u << instr
->num_components
) - 1);
3571 if (nir_intrinsic_align(instr
) >= 4) {
3572 assert(nir_src_bit_size(instr
->src
[0]) == 32);
3573 assert(nir_src_num_components(instr
->src
[0]) <= 4);
3574 srcs
[SURFACE_LOGICAL_SRC_DATA
] = data
;
3575 srcs
[SURFACE_LOGICAL_SRC_IMM_ARG
] = brw_imm_ud(instr
->num_components
);
3576 bld
.emit(SHADER_OPCODE_UNTYPED_SURFACE_WRITE_LOGICAL
,
3577 fs_reg(), srcs
, SURFACE_LOGICAL_NUM_SRCS
);
3579 assert(nir_src_bit_size(instr
->src
[0]) <= 32);
3580 assert(nir_src_num_components(instr
->src
[0]) == 1);
3581 srcs
[SURFACE_LOGICAL_SRC_IMM_ARG
] = brw_imm_ud(bit_size
);
3583 srcs
[SURFACE_LOGICAL_SRC_DATA
] = bld
.vgrf(BRW_REGISTER_TYPE_UD
);
3584 bld
.MOV(srcs
[SURFACE_LOGICAL_SRC_DATA
], data
);
3586 bld
.emit(SHADER_OPCODE_BYTE_SCATTERED_WRITE_LOGICAL
,
3587 fs_reg(), srcs
, SURFACE_LOGICAL_NUM_SRCS
);
3593 nir_emit_intrinsic(bld
, instr
);
3599 brw_nir_reduction_op_identity(const fs_builder
&bld
,
3600 nir_op op
, brw_reg_type type
)
3602 nir_const_value value
= nir_alu_binop_identity(op
, type_sz(type
) * 8);
3603 switch (type_sz(type
)) {
3605 assert(type
!= BRW_REGISTER_TYPE_HF
);
3606 return retype(brw_imm_uw(value
.u16
[0]), type
);
3608 return retype(brw_imm_ud(value
.u32
[0]), type
);
3610 if (type
== BRW_REGISTER_TYPE_DF
)
3611 return setup_imm_df(bld
, value
.f64
[0]);
3613 return retype(brw_imm_u64(value
.u64
[0]), type
);
3615 unreachable("Invalid type size");
3620 brw_op_for_nir_reduction_op(nir_op op
)
3623 case nir_op_iadd
: return BRW_OPCODE_ADD
;
3624 case nir_op_fadd
: return BRW_OPCODE_ADD
;
3625 case nir_op_imul
: return BRW_OPCODE_MUL
;
3626 case nir_op_fmul
: return BRW_OPCODE_MUL
;
3627 case nir_op_imin
: return BRW_OPCODE_SEL
;
3628 case nir_op_umin
: return BRW_OPCODE_SEL
;
3629 case nir_op_fmin
: return BRW_OPCODE_SEL
;
3630 case nir_op_imax
: return BRW_OPCODE_SEL
;
3631 case nir_op_umax
: return BRW_OPCODE_SEL
;
3632 case nir_op_fmax
: return BRW_OPCODE_SEL
;
3633 case nir_op_iand
: return BRW_OPCODE_AND
;
3634 case nir_op_ior
: return BRW_OPCODE_OR
;
3635 case nir_op_ixor
: return BRW_OPCODE_XOR
;
3637 unreachable("Invalid reduction operation");
3641 static brw_conditional_mod
3642 brw_cond_mod_for_nir_reduction_op(nir_op op
)
3645 case nir_op_iadd
: return BRW_CONDITIONAL_NONE
;
3646 case nir_op_fadd
: return BRW_CONDITIONAL_NONE
;
3647 case nir_op_imul
: return BRW_CONDITIONAL_NONE
;
3648 case nir_op_fmul
: return BRW_CONDITIONAL_NONE
;
3649 case nir_op_imin
: return BRW_CONDITIONAL_L
;
3650 case nir_op_umin
: return BRW_CONDITIONAL_L
;
3651 case nir_op_fmin
: return BRW_CONDITIONAL_L
;
3652 case nir_op_imax
: return BRW_CONDITIONAL_GE
;
3653 case nir_op_umax
: return BRW_CONDITIONAL_GE
;
3654 case nir_op_fmax
: return BRW_CONDITIONAL_GE
;
3655 case nir_op_iand
: return BRW_CONDITIONAL_NONE
;
3656 case nir_op_ior
: return BRW_CONDITIONAL_NONE
;
3657 case nir_op_ixor
: return BRW_CONDITIONAL_NONE
;
3659 unreachable("Invalid reduction operation");
3664 fs_visitor::get_nir_image_intrinsic_image(const brw::fs_builder
&bld
,
3665 nir_intrinsic_instr
*instr
)
3667 fs_reg image
= retype(get_nir_src_imm(instr
->src
[0]), BRW_REGISTER_TYPE_UD
);
3669 if (stage_prog_data
->binding_table
.image_start
> 0) {
3670 if (image
.file
== BRW_IMMEDIATE_VALUE
) {
3671 image
.d
+= stage_prog_data
->binding_table
.image_start
;
3673 bld
.ADD(image
, image
,
3674 brw_imm_d(stage_prog_data
->binding_table
.image_start
));
3678 return bld
.emit_uniformize(image
);
3682 fs_visitor::get_nir_ssbo_intrinsic_index(const brw::fs_builder
&bld
,
3683 nir_intrinsic_instr
*instr
)
3685 /* SSBO stores are weird in that their index is in src[1] */
3686 const unsigned src
= instr
->intrinsic
== nir_intrinsic_store_ssbo
? 1 : 0;
3689 if (nir_src_is_const(instr
->src
[src
])) {
3690 unsigned index
= stage_prog_data
->binding_table
.ssbo_start
+
3691 nir_src_as_uint(instr
->src
[src
]);
3692 surf_index
= brw_imm_ud(index
);
3694 surf_index
= vgrf(glsl_type::uint_type
);
3695 bld
.ADD(surf_index
, get_nir_src(instr
->src
[src
]),
3696 brw_imm_ud(stage_prog_data
->binding_table
.ssbo_start
));
3699 return bld
.emit_uniformize(surf_index
);
3703 image_intrinsic_coord_components(nir_intrinsic_instr
*instr
)
3705 switch (nir_intrinsic_image_dim(instr
)) {
3706 case GLSL_SAMPLER_DIM_1D
:
3707 return 1 + nir_intrinsic_image_array(instr
);
3708 case GLSL_SAMPLER_DIM_2D
:
3709 case GLSL_SAMPLER_DIM_RECT
:
3710 return 2 + nir_intrinsic_image_array(instr
);
3711 case GLSL_SAMPLER_DIM_3D
:
3712 case GLSL_SAMPLER_DIM_CUBE
:
3714 case GLSL_SAMPLER_DIM_BUF
:
3716 case GLSL_SAMPLER_DIM_MS
:
3717 return 2 + nir_intrinsic_image_array(instr
);
3719 unreachable("Invalid image dimension");
3724 fs_visitor::nir_emit_intrinsic(const fs_builder
&bld
, nir_intrinsic_instr
*instr
)
3727 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
3728 dest
= get_nir_dest(instr
->dest
);
3730 switch (instr
->intrinsic
) {
3731 case nir_intrinsic_image_load
:
3732 case nir_intrinsic_image_store
:
3733 case nir_intrinsic_image_atomic_add
:
3734 case nir_intrinsic_image_atomic_min
:
3735 case nir_intrinsic_image_atomic_max
:
3736 case nir_intrinsic_image_atomic_and
:
3737 case nir_intrinsic_image_atomic_or
:
3738 case nir_intrinsic_image_atomic_xor
:
3739 case nir_intrinsic_image_atomic_exchange
:
3740 case nir_intrinsic_image_atomic_comp_swap
: {
3741 if (stage
== MESA_SHADER_FRAGMENT
&&
3742 instr
->intrinsic
!= nir_intrinsic_image_load
)
3743 brw_wm_prog_data(prog_data
)->has_side_effects
= true;
3745 /* Get some metadata from the image intrinsic. */
3746 const nir_intrinsic_info
*info
= &nir_intrinsic_infos
[instr
->intrinsic
];
3747 const GLenum format
= nir_intrinsic_format(instr
);
3749 fs_reg srcs
[SURFACE_LOGICAL_NUM_SRCS
];
3750 srcs
[SURFACE_LOGICAL_SRC_SURFACE
] =
3751 get_nir_image_intrinsic_image(bld
, instr
);
3752 srcs
[SURFACE_LOGICAL_SRC_ADDRESS
] = get_nir_src(instr
->src
[1]);
3753 srcs
[SURFACE_LOGICAL_SRC_IMM_DIMS
] =
3754 brw_imm_ud(image_intrinsic_coord_components(instr
));
3756 /* Emit an image load, store or atomic op. */
3757 if (instr
->intrinsic
== nir_intrinsic_image_load
) {
3758 srcs
[SURFACE_LOGICAL_SRC_IMM_ARG
] = brw_imm_ud(instr
->num_components
);
3760 bld
.emit(SHADER_OPCODE_TYPED_SURFACE_READ_LOGICAL
,
3761 dest
, srcs
, SURFACE_LOGICAL_NUM_SRCS
);
3762 inst
->size_written
= instr
->num_components
* dispatch_width
* 4;
3763 } else if (instr
->intrinsic
== nir_intrinsic_image_store
) {
3764 srcs
[SURFACE_LOGICAL_SRC_IMM_ARG
] = brw_imm_ud(instr
->num_components
);
3765 srcs
[SURFACE_LOGICAL_SRC_DATA
] = get_nir_src(instr
->src
[3]);
3766 bld
.emit(SHADER_OPCODE_TYPED_SURFACE_WRITE_LOGICAL
,
3767 fs_reg(), srcs
, SURFACE_LOGICAL_NUM_SRCS
);
3770 unsigned num_srcs
= info
->num_srcs
;
3772 switch (instr
->intrinsic
) {
3773 case nir_intrinsic_image_atomic_add
:
3774 assert(num_srcs
== 4);
3776 op
= get_op_for_atomic_add(instr
, 3);
3778 if (op
!= BRW_AOP_ADD
)
3781 case nir_intrinsic_image_atomic_min
:
3782 assert(format
== GL_R32UI
|| format
== GL_R32I
);
3783 op
= (format
== GL_R32I
) ? BRW_AOP_IMIN
: BRW_AOP_UMIN
;
3785 case nir_intrinsic_image_atomic_max
:
3786 assert(format
== GL_R32UI
|| format
== GL_R32I
);
3787 op
= (format
== GL_R32I
) ? BRW_AOP_IMAX
: BRW_AOP_UMAX
;
3789 case nir_intrinsic_image_atomic_and
:
3792 case nir_intrinsic_image_atomic_or
:
3795 case nir_intrinsic_image_atomic_xor
:
3798 case nir_intrinsic_image_atomic_exchange
:
3801 case nir_intrinsic_image_atomic_comp_swap
:
3805 unreachable("Not reachable.");
3808 srcs
[SURFACE_LOGICAL_SRC_IMM_ARG
] = brw_imm_ud(op
);
3812 data
= get_nir_src(instr
->src
[3]);
3813 if (num_srcs
>= 5) {
3814 fs_reg tmp
= bld
.vgrf(data
.type
, 2);
3815 fs_reg sources
[2] = { data
, get_nir_src(instr
->src
[4]) };
3816 bld
.LOAD_PAYLOAD(tmp
, sources
, 2, 0);
3819 srcs
[SURFACE_LOGICAL_SRC_DATA
] = data
;
3821 bld
.emit(SHADER_OPCODE_TYPED_ATOMIC_LOGICAL
,
3822 dest
, srcs
, SURFACE_LOGICAL_NUM_SRCS
);
3827 case nir_intrinsic_image_size
: {
3828 /* Unlike the [un]typed load and store opcodes, the TXS that this turns
3829 * into will handle the binding table index for us in the geneerator.
3831 fs_reg image
= retype(get_nir_src_imm(instr
->src
[0]),
3832 BRW_REGISTER_TYPE_UD
);
3833 image
= bld
.emit_uniformize(image
);
3835 fs_reg srcs
[TEX_LOGICAL_NUM_SRCS
];
3836 srcs
[TEX_LOGICAL_SRC_SURFACE
] = image
;
3837 srcs
[TEX_LOGICAL_SRC_SAMPLER
] = brw_imm_d(0);
3838 srcs
[TEX_LOGICAL_SRC_COORD_COMPONENTS
] = brw_imm_d(0);
3839 srcs
[TEX_LOGICAL_SRC_GRAD_COMPONENTS
] = brw_imm_d(0);
3841 /* Since the image size is always uniform, we can just emit a SIMD8
3842 * query instruction and splat the result out.
3844 const fs_builder ubld
= bld
.exec_all().group(8, 0);
3846 fs_reg tmp
= ubld
.vgrf(BRW_REGISTER_TYPE_UD
, 4);
3847 fs_inst
*inst
= ubld
.emit(SHADER_OPCODE_IMAGE_SIZE_LOGICAL
,
3848 tmp
, srcs
, ARRAY_SIZE(srcs
));
3849 inst
->size_written
= 4 * REG_SIZE
;
3851 for (unsigned c
= 0; c
< instr
->dest
.ssa
.num_components
; ++c
) {
3852 if (c
== 2 && nir_intrinsic_image_dim(instr
) == GLSL_SAMPLER_DIM_CUBE
) {
3853 bld
.emit(SHADER_OPCODE_INT_QUOTIENT
,
3854 offset(retype(dest
, tmp
.type
), bld
, c
),
3855 component(offset(tmp
, ubld
, c
), 0), brw_imm_ud(6));
3857 bld
.MOV(offset(retype(dest
, tmp
.type
), bld
, c
),
3858 component(offset(tmp
, ubld
, c
), 0));
3864 case nir_intrinsic_image_load_raw_intel
: {
3865 fs_reg srcs
[SURFACE_LOGICAL_NUM_SRCS
];
3866 srcs
[SURFACE_LOGICAL_SRC_SURFACE
] =
3867 get_nir_image_intrinsic_image(bld
, instr
);
3868 srcs
[SURFACE_LOGICAL_SRC_ADDRESS
] = get_nir_src(instr
->src
[1]);
3869 srcs
[SURFACE_LOGICAL_SRC_IMM_DIMS
] = brw_imm_ud(1);
3870 srcs
[SURFACE_LOGICAL_SRC_IMM_ARG
] = brw_imm_ud(instr
->num_components
);
3873 bld
.emit(SHADER_OPCODE_UNTYPED_SURFACE_READ_LOGICAL
,
3874 dest
, srcs
, SURFACE_LOGICAL_NUM_SRCS
);
3875 inst
->size_written
= instr
->num_components
* dispatch_width
* 4;
3879 case nir_intrinsic_image_store_raw_intel
: {
3880 if (stage
== MESA_SHADER_FRAGMENT
)
3881 brw_wm_prog_data(prog_data
)->has_side_effects
= true;
3883 fs_reg srcs
[SURFACE_LOGICAL_NUM_SRCS
];
3884 srcs
[SURFACE_LOGICAL_SRC_SURFACE
] =
3885 get_nir_image_intrinsic_image(bld
, instr
);
3886 srcs
[SURFACE_LOGICAL_SRC_ADDRESS
] = get_nir_src(instr
->src
[1]);
3887 srcs
[SURFACE_LOGICAL_SRC_DATA
] = get_nir_src(instr
->src
[2]);
3888 srcs
[SURFACE_LOGICAL_SRC_IMM_DIMS
] = brw_imm_ud(1);
3889 srcs
[SURFACE_LOGICAL_SRC_IMM_ARG
] = brw_imm_ud(instr
->num_components
);
3891 bld
.emit(SHADER_OPCODE_UNTYPED_SURFACE_WRITE_LOGICAL
,
3892 fs_reg(), srcs
, SURFACE_LOGICAL_NUM_SRCS
);
3896 case nir_intrinsic_group_memory_barrier
:
3897 case nir_intrinsic_memory_barrier_shared
:
3898 case nir_intrinsic_memory_barrier_atomic_counter
:
3899 case nir_intrinsic_memory_barrier_buffer
:
3900 case nir_intrinsic_memory_barrier_image
:
3901 case nir_intrinsic_memory_barrier
: {
3902 const fs_builder ubld
= bld
.group(8, 0);
3903 const fs_reg tmp
= ubld
.vgrf(BRW_REGISTER_TYPE_UD
, 2);
3904 ubld
.emit(SHADER_OPCODE_MEMORY_FENCE
, tmp
)
3905 ->size_written
= 2 * REG_SIZE
;
3909 case nir_intrinsic_shader_clock
: {
3910 /* We cannot do anything if there is an event, so ignore it for now */
3911 const fs_reg shader_clock
= get_timestamp(bld
);
3912 const fs_reg srcs
[] = { component(shader_clock
, 0),
3913 component(shader_clock
, 1) };
3914 bld
.LOAD_PAYLOAD(dest
, srcs
, ARRAY_SIZE(srcs
), 0);
3918 case nir_intrinsic_image_samples
:
3919 /* The driver does not support multi-sampled images. */
3920 bld
.MOV(retype(dest
, BRW_REGISTER_TYPE_D
), brw_imm_d(1));
3923 case nir_intrinsic_load_uniform
: {
3924 /* Offsets are in bytes but they should always aligned to
3927 assert(instr
->const_index
[0] % 4 == 0 ||
3928 instr
->const_index
[0] % type_sz(dest
.type
) == 0);
3930 fs_reg
src(UNIFORM
, instr
->const_index
[0] / 4, dest
.type
);
3932 if (nir_src_is_const(instr
->src
[0])) {
3933 unsigned load_offset
= nir_src_as_uint(instr
->src
[0]);
3934 assert(load_offset
% type_sz(dest
.type
) == 0);
3935 /* For 16-bit types we add the module of the const_index[0]
3936 * offset to access to not 32-bit aligned element
3938 src
.offset
= load_offset
+ instr
->const_index
[0] % 4;
3940 for (unsigned j
= 0; j
< instr
->num_components
; j
++) {
3941 bld
.MOV(offset(dest
, bld
, j
), offset(src
, bld
, j
));
3944 fs_reg indirect
= retype(get_nir_src(instr
->src
[0]),
3945 BRW_REGISTER_TYPE_UD
);
3947 /* We need to pass a size to the MOV_INDIRECT but we don't want it to
3948 * go past the end of the uniform. In order to keep the n'th
3949 * component from running past, we subtract off the size of all but
3950 * one component of the vector.
3952 assert(instr
->const_index
[1] >=
3953 instr
->num_components
* (int) type_sz(dest
.type
));
3954 unsigned read_size
= instr
->const_index
[1] -
3955 (instr
->num_components
- 1) * type_sz(dest
.type
);
3957 bool supports_64bit_indirects
=
3958 !devinfo
->is_cherryview
&& !gen_device_info_is_9lp(devinfo
);
3960 if (type_sz(dest
.type
) != 8 || supports_64bit_indirects
) {
3961 for (unsigned j
= 0; j
< instr
->num_components
; j
++) {
3962 bld
.emit(SHADER_OPCODE_MOV_INDIRECT
,
3963 offset(dest
, bld
, j
), offset(src
, bld
, j
),
3964 indirect
, brw_imm_ud(read_size
));
3967 const unsigned num_mov_indirects
=
3968 type_sz(dest
.type
) / type_sz(BRW_REGISTER_TYPE_UD
);
3969 /* We read a little bit less per MOV INDIRECT, as they are now
3970 * 32-bits ones instead of 64-bit. Fix read_size then.
3972 const unsigned read_size_32bit
= read_size
-
3973 (num_mov_indirects
- 1) * type_sz(BRW_REGISTER_TYPE_UD
);
3974 for (unsigned j
= 0; j
< instr
->num_components
; j
++) {
3975 for (unsigned i
= 0; i
< num_mov_indirects
; i
++) {
3976 bld
.emit(SHADER_OPCODE_MOV_INDIRECT
,
3977 subscript(offset(dest
, bld
, j
), BRW_REGISTER_TYPE_UD
, i
),
3978 subscript(offset(src
, bld
, j
), BRW_REGISTER_TYPE_UD
, i
),
3979 indirect
, brw_imm_ud(read_size_32bit
));
3987 case nir_intrinsic_load_ubo
: {
3989 if (nir_src_is_const(instr
->src
[0])) {
3990 const unsigned index
= stage_prog_data
->binding_table
.ubo_start
+
3991 nir_src_as_uint(instr
->src
[0]);
3992 surf_index
= brw_imm_ud(index
);
3994 /* The block index is not a constant. Evaluate the index expression
3995 * per-channel and add the base UBO index; we have to select a value
3996 * from any live channel.
3998 surf_index
= vgrf(glsl_type::uint_type
);
3999 bld
.ADD(surf_index
, get_nir_src(instr
->src
[0]),
4000 brw_imm_ud(stage_prog_data
->binding_table
.ubo_start
));
4001 surf_index
= bld
.emit_uniformize(surf_index
);
4004 if (!nir_src_is_const(instr
->src
[1])) {
4005 fs_reg base_offset
= retype(get_nir_src(instr
->src
[1]),
4006 BRW_REGISTER_TYPE_UD
);
4008 for (int i
= 0; i
< instr
->num_components
; i
++)
4009 VARYING_PULL_CONSTANT_LOAD(bld
, offset(dest
, bld
, i
), surf_index
,
4010 base_offset
, i
* type_sz(dest
.type
));
4012 /* Even if we are loading doubles, a pull constant load will load
4013 * a 32-bit vec4, so should only reserve vgrf space for that. If we
4014 * need to load a full dvec4 we will have to emit 2 loads. This is
4015 * similar to demote_pull_constants(), except that in that case we
4016 * see individual accesses to each component of the vector and then
4017 * we let CSE deal with duplicate loads. Here we see a vector access
4018 * and we have to split it if necessary.
4020 const unsigned type_size
= type_sz(dest
.type
);
4021 const unsigned load_offset
= nir_src_as_uint(instr
->src
[1]);
4023 /* See if we've selected this as a push constant candidate */
4024 if (nir_src_is_const(instr
->src
[0])) {
4025 const unsigned ubo_block
= nir_src_as_uint(instr
->src
[0]);
4026 const unsigned offset_256b
= load_offset
/ 32;
4029 for (int i
= 0; i
< 4; i
++) {
4030 const struct brw_ubo_range
*range
= &prog_data
->ubo_ranges
[i
];
4031 if (range
->block
== ubo_block
&&
4032 offset_256b
>= range
->start
&&
4033 offset_256b
< range
->start
+ range
->length
) {
4035 push_reg
= fs_reg(UNIFORM
, UBO_START
+ i
, dest
.type
);
4036 push_reg
.offset
= load_offset
- 32 * range
->start
;
4041 if (push_reg
.file
!= BAD_FILE
) {
4042 for (unsigned i
= 0; i
< instr
->num_components
; i
++) {
4043 bld
.MOV(offset(dest
, bld
, i
),
4044 byte_offset(push_reg
, i
* type_size
));
4050 const unsigned block_sz
= 64; /* Fetch one cacheline at a time. */
4051 const fs_builder ubld
= bld
.exec_all().group(block_sz
/ 4, 0);
4052 const fs_reg packed_consts
= ubld
.vgrf(BRW_REGISTER_TYPE_UD
);
4054 for (unsigned c
= 0; c
< instr
->num_components
;) {
4055 const unsigned base
= load_offset
+ c
* type_size
;
4056 /* Number of usable components in the next block-aligned load. */
4057 const unsigned count
= MIN2(instr
->num_components
- c
,
4058 (block_sz
- base
% block_sz
) / type_size
);
4060 ubld
.emit(FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD
,
4061 packed_consts
, surf_index
,
4062 brw_imm_ud(base
& ~(block_sz
- 1)));
4064 const fs_reg consts
=
4065 retype(byte_offset(packed_consts
, base
& (block_sz
- 1)),
4068 for (unsigned d
= 0; d
< count
; d
++)
4069 bld
.MOV(offset(dest
, bld
, c
+ d
), component(consts
, d
));
4077 case nir_intrinsic_load_global
: {
4078 assert(devinfo
->gen
>= 8);
4080 if (nir_intrinsic_align(instr
) >= 4) {
4081 assert(nir_dest_bit_size(instr
->dest
) == 32);
4082 fs_inst
*inst
= bld
.emit(SHADER_OPCODE_A64_UNTYPED_READ_LOGICAL
,
4084 get_nir_src(instr
->src
[0]), /* Address */
4085 fs_reg(), /* No source data */
4086 brw_imm_ud(instr
->num_components
));
4087 inst
->size_written
= instr
->num_components
*
4088 inst
->dst
.component_size(inst
->exec_size
);
4090 const unsigned bit_size
= nir_dest_bit_size(instr
->dest
);
4091 assert(bit_size
<= 32);
4092 assert(nir_dest_num_components(instr
->dest
) == 1);
4093 brw_reg_type data_type
=
4094 brw_reg_type_from_bit_size(bit_size
, BRW_REGISTER_TYPE_UD
);
4095 fs_reg tmp
= bld
.vgrf(BRW_REGISTER_TYPE_UD
);
4096 bld
.emit(SHADER_OPCODE_A64_BYTE_SCATTERED_READ_LOGICAL
,
4098 get_nir_src(instr
->src
[0]), /* Address */
4099 fs_reg(), /* No source data */
4100 brw_imm_ud(bit_size
));
4101 bld
.MOV(retype(dest
, data_type
), tmp
);
4106 case nir_intrinsic_store_global
:
4107 assert(devinfo
->gen
>= 8);
4109 if (stage
== MESA_SHADER_FRAGMENT
)
4110 brw_wm_prog_data(prog_data
)->has_side_effects
= true;
4112 if (nir_intrinsic_align(instr
) >= 4) {
4113 assert(nir_src_bit_size(instr
->src
[0]) == 32);
4114 bld
.emit(SHADER_OPCODE_A64_UNTYPED_WRITE_LOGICAL
,
4116 get_nir_src(instr
->src
[1]), /* Address */
4117 get_nir_src(instr
->src
[0]), /* Data */
4118 brw_imm_ud(instr
->num_components
));
4120 const unsigned bit_size
= nir_src_bit_size(instr
->src
[0]);
4121 assert(bit_size
<= 32);
4122 assert(nir_src_num_components(instr
->src
[0]) == 1);
4123 brw_reg_type data_type
=
4124 brw_reg_type_from_bit_size(bit_size
, BRW_REGISTER_TYPE_UD
);
4125 fs_reg tmp
= bld
.vgrf(BRW_REGISTER_TYPE_UD
);
4126 bld
.MOV(tmp
, retype(get_nir_src(instr
->src
[0]), data_type
));
4127 bld
.emit(SHADER_OPCODE_A64_BYTE_SCATTERED_WRITE_LOGICAL
,
4129 get_nir_src(instr
->src
[1]), /* Address */
4131 brw_imm_ud(nir_src_bit_size(instr
->src
[0])));
4135 case nir_intrinsic_global_atomic_add
:
4136 nir_emit_global_atomic(bld
, get_op_for_atomic_add(instr
, 1), instr
);
4138 case nir_intrinsic_global_atomic_imin
:
4139 nir_emit_global_atomic(bld
, BRW_AOP_IMIN
, instr
);
4141 case nir_intrinsic_global_atomic_umin
:
4142 nir_emit_global_atomic(bld
, BRW_AOP_UMIN
, instr
);
4144 case nir_intrinsic_global_atomic_imax
:
4145 nir_emit_global_atomic(bld
, BRW_AOP_IMAX
, instr
);
4147 case nir_intrinsic_global_atomic_umax
:
4148 nir_emit_global_atomic(bld
, BRW_AOP_UMAX
, instr
);
4150 case nir_intrinsic_global_atomic_and
:
4151 nir_emit_global_atomic(bld
, BRW_AOP_AND
, instr
);
4153 case nir_intrinsic_global_atomic_or
:
4154 nir_emit_global_atomic(bld
, BRW_AOP_OR
, instr
);
4156 case nir_intrinsic_global_atomic_xor
:
4157 nir_emit_global_atomic(bld
, BRW_AOP_XOR
, instr
);
4159 case nir_intrinsic_global_atomic_exchange
:
4160 nir_emit_global_atomic(bld
, BRW_AOP_MOV
, instr
);
4162 case nir_intrinsic_global_atomic_comp_swap
:
4163 nir_emit_global_atomic(bld
, BRW_AOP_CMPWR
, instr
);
4165 case nir_intrinsic_global_atomic_fmin
:
4166 nir_emit_global_atomic_float(bld
, BRW_AOP_FMIN
, instr
);
4168 case nir_intrinsic_global_atomic_fmax
:
4169 nir_emit_global_atomic_float(bld
, BRW_AOP_FMAX
, instr
);
4171 case nir_intrinsic_global_atomic_fcomp_swap
:
4172 nir_emit_global_atomic_float(bld
, BRW_AOP_FCMPWR
, instr
);
4175 case nir_intrinsic_load_ssbo
: {
4176 assert(devinfo
->gen
>= 7);
4178 const unsigned bit_size
= nir_dest_bit_size(instr
->dest
);
4179 fs_reg srcs
[SURFACE_LOGICAL_NUM_SRCS
];
4180 srcs
[SURFACE_LOGICAL_SRC_SURFACE
] =
4181 get_nir_ssbo_intrinsic_index(bld
, instr
);
4182 srcs
[SURFACE_LOGICAL_SRC_ADDRESS
] = get_nir_src(instr
->src
[1]);
4183 srcs
[SURFACE_LOGICAL_SRC_IMM_DIMS
] = brw_imm_ud(1);
4185 /* Make dest unsigned because that's what the temporary will be */
4186 dest
.type
= brw_reg_type_from_bit_size(bit_size
, BRW_REGISTER_TYPE_UD
);
4188 /* Read the vector */
4189 if (nir_intrinsic_align(instr
) >= 4) {
4190 assert(nir_dest_bit_size(instr
->dest
) == 32);
4191 srcs
[SURFACE_LOGICAL_SRC_IMM_ARG
] = brw_imm_ud(instr
->num_components
);
4193 bld
.emit(SHADER_OPCODE_UNTYPED_SURFACE_READ_LOGICAL
,
4194 dest
, srcs
, SURFACE_LOGICAL_NUM_SRCS
);
4195 inst
->size_written
= instr
->num_components
* dispatch_width
* 4;
4197 assert(nir_dest_bit_size(instr
->dest
) <= 32);
4198 assert(nir_dest_num_components(instr
->dest
) == 1);
4199 srcs
[SURFACE_LOGICAL_SRC_IMM_ARG
] = brw_imm_ud(bit_size
);
4201 fs_reg read_result
= bld
.vgrf(BRW_REGISTER_TYPE_UD
);
4202 bld
.emit(SHADER_OPCODE_BYTE_SCATTERED_READ_LOGICAL
,
4203 read_result
, srcs
, SURFACE_LOGICAL_NUM_SRCS
);
4204 bld
.MOV(dest
, read_result
);
4209 case nir_intrinsic_store_ssbo
: {
4210 assert(devinfo
->gen
>= 7);
4212 if (stage
== MESA_SHADER_FRAGMENT
)
4213 brw_wm_prog_data(prog_data
)->has_side_effects
= true;
4215 const unsigned bit_size
= nir_src_bit_size(instr
->src
[0]);
4216 fs_reg srcs
[SURFACE_LOGICAL_NUM_SRCS
];
4217 srcs
[SURFACE_LOGICAL_SRC_SURFACE
] =
4218 get_nir_ssbo_intrinsic_index(bld
, instr
);
4219 srcs
[SURFACE_LOGICAL_SRC_ADDRESS
] = get_nir_src(instr
->src
[2]);
4220 srcs
[SURFACE_LOGICAL_SRC_IMM_DIMS
] = brw_imm_ud(1);
4222 fs_reg data
= get_nir_src(instr
->src
[0]);
4223 data
.type
= brw_reg_type_from_bit_size(bit_size
, BRW_REGISTER_TYPE_UD
);
4225 assert(nir_intrinsic_write_mask(instr
) ==
4226 (1u << instr
->num_components
) - 1);
4227 if (nir_intrinsic_align(instr
) >= 4) {
4228 assert(nir_src_bit_size(instr
->src
[0]) == 32);
4229 assert(nir_src_num_components(instr
->src
[0]) <= 4);
4230 srcs
[SURFACE_LOGICAL_SRC_DATA
] = data
;
4231 srcs
[SURFACE_LOGICAL_SRC_IMM_ARG
] = brw_imm_ud(instr
->num_components
);
4232 bld
.emit(SHADER_OPCODE_UNTYPED_SURFACE_WRITE_LOGICAL
,
4233 fs_reg(), srcs
, SURFACE_LOGICAL_NUM_SRCS
);
4235 assert(nir_src_bit_size(instr
->src
[0]) <= 32);
4236 assert(nir_src_num_components(instr
->src
[0]) == 1);
4237 srcs
[SURFACE_LOGICAL_SRC_IMM_ARG
] = brw_imm_ud(bit_size
);
4239 srcs
[SURFACE_LOGICAL_SRC_DATA
] = bld
.vgrf(BRW_REGISTER_TYPE_UD
);
4240 bld
.MOV(srcs
[SURFACE_LOGICAL_SRC_DATA
], data
);
4242 bld
.emit(SHADER_OPCODE_BYTE_SCATTERED_WRITE_LOGICAL
,
4243 fs_reg(), srcs
, SURFACE_LOGICAL_NUM_SRCS
);
4248 case nir_intrinsic_store_output
: {
4249 fs_reg src
= get_nir_src(instr
->src
[0]);
4251 unsigned store_offset
= nir_src_as_uint(instr
->src
[1]);
4252 unsigned num_components
= instr
->num_components
;
4253 unsigned first_component
= nir_intrinsic_component(instr
);
4254 if (nir_src_bit_size(instr
->src
[0]) == 64) {
4255 src
= shuffle_for_32bit_write(bld
, src
, 0, num_components
);
4256 num_components
*= 2;
4259 fs_reg new_dest
= retype(offset(outputs
[instr
->const_index
[0]], bld
,
4260 4 * store_offset
), src
.type
);
4261 for (unsigned j
= 0; j
< num_components
; j
++) {
4262 bld
.MOV(offset(new_dest
, bld
, j
+ first_component
),
4263 offset(src
, bld
, j
));
4268 case nir_intrinsic_ssbo_atomic_add
:
4269 nir_emit_ssbo_atomic(bld
, get_op_for_atomic_add(instr
, 2), instr
);
4271 case nir_intrinsic_ssbo_atomic_imin
:
4272 nir_emit_ssbo_atomic(bld
, BRW_AOP_IMIN
, instr
);
4274 case nir_intrinsic_ssbo_atomic_umin
:
4275 nir_emit_ssbo_atomic(bld
, BRW_AOP_UMIN
, instr
);
4277 case nir_intrinsic_ssbo_atomic_imax
:
4278 nir_emit_ssbo_atomic(bld
, BRW_AOP_IMAX
, instr
);
4280 case nir_intrinsic_ssbo_atomic_umax
:
4281 nir_emit_ssbo_atomic(bld
, BRW_AOP_UMAX
, instr
);
4283 case nir_intrinsic_ssbo_atomic_and
:
4284 nir_emit_ssbo_atomic(bld
, BRW_AOP_AND
, instr
);
4286 case nir_intrinsic_ssbo_atomic_or
:
4287 nir_emit_ssbo_atomic(bld
, BRW_AOP_OR
, instr
);
4289 case nir_intrinsic_ssbo_atomic_xor
:
4290 nir_emit_ssbo_atomic(bld
, BRW_AOP_XOR
, instr
);
4292 case nir_intrinsic_ssbo_atomic_exchange
:
4293 nir_emit_ssbo_atomic(bld
, BRW_AOP_MOV
, instr
);
4295 case nir_intrinsic_ssbo_atomic_comp_swap
:
4296 nir_emit_ssbo_atomic(bld
, BRW_AOP_CMPWR
, instr
);
4298 case nir_intrinsic_ssbo_atomic_fmin
:
4299 nir_emit_ssbo_atomic_float(bld
, BRW_AOP_FMIN
, instr
);
4301 case nir_intrinsic_ssbo_atomic_fmax
:
4302 nir_emit_ssbo_atomic_float(bld
, BRW_AOP_FMAX
, instr
);
4304 case nir_intrinsic_ssbo_atomic_fcomp_swap
:
4305 nir_emit_ssbo_atomic_float(bld
, BRW_AOP_FCMPWR
, instr
);
4308 case nir_intrinsic_get_buffer_size
: {
4309 unsigned ssbo_index
= nir_src_is_const(instr
->src
[0]) ?
4310 nir_src_as_uint(instr
->src
[0]) : 0;
4312 /* A resinfo's sampler message is used to get the buffer size. The
4313 * SIMD8's writeback message consists of four registers and SIMD16's
4314 * writeback message consists of 8 destination registers (two per each
4315 * component). Because we are only interested on the first channel of
4316 * the first returned component, where resinfo returns the buffer size
4317 * for SURFTYPE_BUFFER, we can just use the SIMD8 variant regardless of
4318 * the dispatch width.
4320 const fs_builder ubld
= bld
.exec_all().group(8, 0);
4321 fs_reg src_payload
= ubld
.vgrf(BRW_REGISTER_TYPE_UD
);
4322 fs_reg ret_payload
= ubld
.vgrf(BRW_REGISTER_TYPE_UD
, 4);
4325 ubld
.MOV(src_payload
, brw_imm_d(0));
4327 const unsigned index
= prog_data
->binding_table
.ssbo_start
+ ssbo_index
;
4328 fs_inst
*inst
= ubld
.emit(SHADER_OPCODE_GET_BUFFER_SIZE
, ret_payload
,
4329 src_payload
, brw_imm_ud(index
));
4330 inst
->header_size
= 0;
4332 inst
->size_written
= 4 * REG_SIZE
;
4334 /* SKL PRM, vol07, 3D Media GPGPU Engine, Bounds Checking and Faulting:
4336 * "Out-of-bounds checking is always performed at a DWord granularity. If
4337 * any part of the DWord is out-of-bounds then the whole DWord is
4338 * considered out-of-bounds."
4340 * This implies that types with size smaller than 4-bytes need to be
4341 * padded if they don't complete the last dword of the buffer. But as we
4342 * need to maintain the original size we need to reverse the padding
4343 * calculation to return the correct size to know the number of elements
4344 * of an unsized array. As we stored in the last two bits of the surface
4345 * size the needed padding for the buffer, we calculate here the
4346 * original buffer_size reversing the surface_size calculation:
4348 * surface_size = isl_align(buffer_size, 4) +
4349 * (isl_align(buffer_size) - buffer_size)
4351 * buffer_size = surface_size & ~3 - surface_size & 3
4354 fs_reg size_aligned4
= ubld
.vgrf(BRW_REGISTER_TYPE_UD
);
4355 fs_reg size_padding
= ubld
.vgrf(BRW_REGISTER_TYPE_UD
);
4356 fs_reg buffer_size
= ubld
.vgrf(BRW_REGISTER_TYPE_UD
);
4358 ubld
.AND(size_padding
, ret_payload
, brw_imm_ud(3));
4359 ubld
.AND(size_aligned4
, ret_payload
, brw_imm_ud(~3));
4360 ubld
.ADD(buffer_size
, size_aligned4
, negate(size_padding
));
4362 bld
.MOV(retype(dest
, ret_payload
.type
), component(buffer_size
, 0));
4366 case nir_intrinsic_load_subgroup_invocation
:
4367 bld
.MOV(retype(dest
, BRW_REGISTER_TYPE_D
),
4368 nir_system_values
[SYSTEM_VALUE_SUBGROUP_INVOCATION
]);
4371 case nir_intrinsic_load_subgroup_eq_mask
:
4372 case nir_intrinsic_load_subgroup_ge_mask
:
4373 case nir_intrinsic_load_subgroup_gt_mask
:
4374 case nir_intrinsic_load_subgroup_le_mask
:
4375 case nir_intrinsic_load_subgroup_lt_mask
:
4376 unreachable("not reached");
4378 case nir_intrinsic_vote_any
: {
4379 const fs_builder ubld
= bld
.exec_all().group(1, 0);
4381 /* The any/all predicates do not consider channel enables. To prevent
4382 * dead channels from affecting the result, we initialize the flag with
4383 * with the identity value for the logical operation.
4385 if (dispatch_width
== 32) {
4386 /* For SIMD32, we use a UD type so we fill both f0.0 and f0.1. */
4387 ubld
.MOV(retype(brw_flag_reg(0, 0), BRW_REGISTER_TYPE_UD
),
4390 ubld
.MOV(brw_flag_reg(0, 0), brw_imm_uw(0));
4392 bld
.CMP(bld
.null_reg_d(), get_nir_src(instr
->src
[0]), brw_imm_d(0), BRW_CONDITIONAL_NZ
);
4394 /* For some reason, the any/all predicates don't work properly with
4395 * SIMD32. In particular, it appears that a SEL with a QtrCtrl of 2H
4396 * doesn't read the correct subset of the flag register and you end up
4397 * getting garbage in the second half. Work around this by using a pair
4398 * of 1-wide MOVs and scattering the result.
4400 fs_reg res1
= ubld
.vgrf(BRW_REGISTER_TYPE_D
);
4401 ubld
.MOV(res1
, brw_imm_d(0));
4402 set_predicate(dispatch_width
== 8 ? BRW_PREDICATE_ALIGN1_ANY8H
:
4403 dispatch_width
== 16 ? BRW_PREDICATE_ALIGN1_ANY16H
:
4404 BRW_PREDICATE_ALIGN1_ANY32H
,
4405 ubld
.MOV(res1
, brw_imm_d(-1)));
4407 bld
.MOV(retype(dest
, BRW_REGISTER_TYPE_D
), component(res1
, 0));
4410 case nir_intrinsic_vote_all
: {
4411 const fs_builder ubld
= bld
.exec_all().group(1, 0);
4413 /* The any/all predicates do not consider channel enables. To prevent
4414 * dead channels from affecting the result, we initialize the flag with
4415 * with the identity value for the logical operation.
4417 if (dispatch_width
== 32) {
4418 /* For SIMD32, we use a UD type so we fill both f0.0 and f0.1. */
4419 ubld
.MOV(retype(brw_flag_reg(0, 0), BRW_REGISTER_TYPE_UD
),
4420 brw_imm_ud(0xffffffff));
4422 ubld
.MOV(brw_flag_reg(0, 0), brw_imm_uw(0xffff));
4424 bld
.CMP(bld
.null_reg_d(), get_nir_src(instr
->src
[0]), brw_imm_d(0), BRW_CONDITIONAL_NZ
);
4426 /* For some reason, the any/all predicates don't work properly with
4427 * SIMD32. In particular, it appears that a SEL with a QtrCtrl of 2H
4428 * doesn't read the correct subset of the flag register and you end up
4429 * getting garbage in the second half. Work around this by using a pair
4430 * of 1-wide MOVs and scattering the result.
4432 fs_reg res1
= ubld
.vgrf(BRW_REGISTER_TYPE_D
);
4433 ubld
.MOV(res1
, brw_imm_d(0));
4434 set_predicate(dispatch_width
== 8 ? BRW_PREDICATE_ALIGN1_ALL8H
:
4435 dispatch_width
== 16 ? BRW_PREDICATE_ALIGN1_ALL16H
:
4436 BRW_PREDICATE_ALIGN1_ALL32H
,
4437 ubld
.MOV(res1
, brw_imm_d(-1)));
4439 bld
.MOV(retype(dest
, BRW_REGISTER_TYPE_D
), component(res1
, 0));
4442 case nir_intrinsic_vote_feq
:
4443 case nir_intrinsic_vote_ieq
: {
4444 fs_reg value
= get_nir_src(instr
->src
[0]);
4445 if (instr
->intrinsic
== nir_intrinsic_vote_feq
) {
4446 const unsigned bit_size
= nir_src_bit_size(instr
->src
[0]);
4447 value
.type
= brw_reg_type_from_bit_size(bit_size
, BRW_REGISTER_TYPE_F
);
4450 fs_reg uniformized
= bld
.emit_uniformize(value
);
4451 const fs_builder ubld
= bld
.exec_all().group(1, 0);
4453 /* The any/all predicates do not consider channel enables. To prevent
4454 * dead channels from affecting the result, we initialize the flag with
4455 * with the identity value for the logical operation.
4457 if (dispatch_width
== 32) {
4458 /* For SIMD32, we use a UD type so we fill both f0.0 and f0.1. */
4459 ubld
.MOV(retype(brw_flag_reg(0, 0), BRW_REGISTER_TYPE_UD
),
4460 brw_imm_ud(0xffffffff));
4462 ubld
.MOV(brw_flag_reg(0, 0), brw_imm_uw(0xffff));
4464 bld
.CMP(bld
.null_reg_d(), value
, uniformized
, BRW_CONDITIONAL_Z
);
4466 /* For some reason, the any/all predicates don't work properly with
4467 * SIMD32. In particular, it appears that a SEL with a QtrCtrl of 2H
4468 * doesn't read the correct subset of the flag register and you end up
4469 * getting garbage in the second half. Work around this by using a pair
4470 * of 1-wide MOVs and scattering the result.
4472 fs_reg res1
= ubld
.vgrf(BRW_REGISTER_TYPE_D
);
4473 ubld
.MOV(res1
, brw_imm_d(0));
4474 set_predicate(dispatch_width
== 8 ? BRW_PREDICATE_ALIGN1_ALL8H
:
4475 dispatch_width
== 16 ? BRW_PREDICATE_ALIGN1_ALL16H
:
4476 BRW_PREDICATE_ALIGN1_ALL32H
,
4477 ubld
.MOV(res1
, brw_imm_d(-1)));
4479 bld
.MOV(retype(dest
, BRW_REGISTER_TYPE_D
), component(res1
, 0));
4483 case nir_intrinsic_ballot
: {
4484 const fs_reg value
= retype(get_nir_src(instr
->src
[0]),
4485 BRW_REGISTER_TYPE_UD
);
4486 struct brw_reg flag
= brw_flag_reg(0, 0);
4487 /* FIXME: For SIMD32 programs, this causes us to stomp on f0.1 as well
4488 * as f0.0. This is a problem for fragment programs as we currently use
4489 * f0.1 for discards. Fortunately, we don't support SIMD32 fragment
4490 * programs yet so this isn't a problem. When we do, something will
4493 if (dispatch_width
== 32)
4494 flag
.type
= BRW_REGISTER_TYPE_UD
;
4496 bld
.exec_all().group(1, 0).MOV(flag
, brw_imm_ud(0u));
4497 bld
.CMP(bld
.null_reg_ud(), value
, brw_imm_ud(0u), BRW_CONDITIONAL_NZ
);
4499 if (instr
->dest
.ssa
.bit_size
> 32) {
4500 dest
.type
= BRW_REGISTER_TYPE_UQ
;
4502 dest
.type
= BRW_REGISTER_TYPE_UD
;
4504 bld
.MOV(dest
, flag
);
4508 case nir_intrinsic_read_invocation
: {
4509 const fs_reg value
= get_nir_src(instr
->src
[0]);
4510 const fs_reg invocation
= get_nir_src(instr
->src
[1]);
4511 fs_reg tmp
= bld
.vgrf(value
.type
);
4513 bld
.exec_all().emit(SHADER_OPCODE_BROADCAST
, tmp
, value
,
4514 bld
.emit_uniformize(invocation
));
4516 bld
.MOV(retype(dest
, value
.type
), fs_reg(component(tmp
, 0)));
4520 case nir_intrinsic_read_first_invocation
: {
4521 const fs_reg value
= get_nir_src(instr
->src
[0]);
4522 bld
.MOV(retype(dest
, value
.type
), bld
.emit_uniformize(value
));
4526 case nir_intrinsic_shuffle
: {
4527 const fs_reg value
= get_nir_src(instr
->src
[0]);
4528 const fs_reg index
= get_nir_src(instr
->src
[1]);
4530 bld
.emit(SHADER_OPCODE_SHUFFLE
, retype(dest
, value
.type
), value
, index
);
4534 case nir_intrinsic_first_invocation
: {
4535 fs_reg tmp
= bld
.vgrf(BRW_REGISTER_TYPE_UD
);
4536 bld
.exec_all().emit(SHADER_OPCODE_FIND_LIVE_CHANNEL
, tmp
);
4537 bld
.MOV(retype(dest
, BRW_REGISTER_TYPE_UD
),
4538 fs_reg(component(tmp
, 0)));
4542 case nir_intrinsic_quad_broadcast
: {
4543 const fs_reg value
= get_nir_src(instr
->src
[0]);
4544 const unsigned index
= nir_src_as_uint(instr
->src
[1]);
4546 bld
.emit(SHADER_OPCODE_CLUSTER_BROADCAST
, retype(dest
, value
.type
),
4547 value
, brw_imm_ud(index
), brw_imm_ud(4));
4551 case nir_intrinsic_quad_swap_horizontal
: {
4552 const fs_reg value
= get_nir_src(instr
->src
[0]);
4553 const fs_reg tmp
= bld
.vgrf(value
.type
);
4554 const fs_builder ubld
= bld
.exec_all().group(dispatch_width
/ 2, 0);
4556 const fs_reg src_left
= horiz_stride(value
, 2);
4557 const fs_reg src_right
= horiz_stride(horiz_offset(value
, 1), 2);
4558 const fs_reg tmp_left
= horiz_stride(tmp
, 2);
4559 const fs_reg tmp_right
= horiz_stride(horiz_offset(tmp
, 1), 2);
4561 ubld
.MOV(tmp_left
, src_right
);
4562 ubld
.MOV(tmp_right
, src_left
);
4564 bld
.MOV(retype(dest
, value
.type
), tmp
);
4568 case nir_intrinsic_quad_swap_vertical
: {
4569 const fs_reg value
= get_nir_src(instr
->src
[0]);
4570 if (nir_src_bit_size(instr
->src
[0]) == 32) {
4571 /* For 32-bit, we can use a SIMD4x2 instruction to do this easily */
4572 const fs_reg tmp
= bld
.vgrf(value
.type
);
4573 const fs_builder ubld
= bld
.exec_all();
4574 ubld
.emit(SHADER_OPCODE_QUAD_SWIZZLE
, tmp
, value
,
4575 brw_imm_ud(BRW_SWIZZLE4(2,3,0,1)));
4576 bld
.MOV(retype(dest
, value
.type
), tmp
);
4578 /* For larger data types, we have to either emit dispatch_width many
4579 * MOVs or else fall back to doing indirects.
4581 fs_reg idx
= bld
.vgrf(BRW_REGISTER_TYPE_W
);
4582 bld
.XOR(idx
, nir_system_values
[SYSTEM_VALUE_SUBGROUP_INVOCATION
],
4584 bld
.emit(SHADER_OPCODE_SHUFFLE
, retype(dest
, value
.type
), value
, idx
);
4589 case nir_intrinsic_quad_swap_diagonal
: {
4590 const fs_reg value
= get_nir_src(instr
->src
[0]);
4591 if (nir_src_bit_size(instr
->src
[0]) == 32) {
4592 /* For 32-bit, we can use a SIMD4x2 instruction to do this easily */
4593 const fs_reg tmp
= bld
.vgrf(value
.type
);
4594 const fs_builder ubld
= bld
.exec_all();
4595 ubld
.emit(SHADER_OPCODE_QUAD_SWIZZLE
, tmp
, value
,
4596 brw_imm_ud(BRW_SWIZZLE4(3,2,1,0)));
4597 bld
.MOV(retype(dest
, value
.type
), tmp
);
4599 /* For larger data types, we have to either emit dispatch_width many
4600 * MOVs or else fall back to doing indirects.
4602 fs_reg idx
= bld
.vgrf(BRW_REGISTER_TYPE_W
);
4603 bld
.XOR(idx
, nir_system_values
[SYSTEM_VALUE_SUBGROUP_INVOCATION
],
4605 bld
.emit(SHADER_OPCODE_SHUFFLE
, retype(dest
, value
.type
), value
, idx
);
4610 case nir_intrinsic_reduce
: {
4611 fs_reg src
= get_nir_src(instr
->src
[0]);
4612 nir_op redop
= (nir_op
)nir_intrinsic_reduction_op(instr
);
4613 unsigned cluster_size
= nir_intrinsic_cluster_size(instr
);
4614 if (cluster_size
== 0 || cluster_size
> dispatch_width
)
4615 cluster_size
= dispatch_width
;
4617 /* Figure out the source type */
4618 src
.type
= brw_type_for_nir_type(devinfo
,
4619 (nir_alu_type
)(nir_op_infos
[redop
].input_types
[0] |
4620 nir_src_bit_size(instr
->src
[0])));
4622 fs_reg identity
= brw_nir_reduction_op_identity(bld
, redop
, src
.type
);
4623 opcode brw_op
= brw_op_for_nir_reduction_op(redop
);
4624 brw_conditional_mod cond_mod
= brw_cond_mod_for_nir_reduction_op(redop
);
4626 /* Set up a register for all of our scratching around and initialize it
4627 * to reduction operation's identity value.
4629 fs_reg scan
= bld
.vgrf(src
.type
);
4630 bld
.exec_all().emit(SHADER_OPCODE_SEL_EXEC
, scan
, src
, identity
);
4632 bld
.emit_scan(brw_op
, scan
, cluster_size
, cond_mod
);
4634 dest
.type
= src
.type
;
4635 if (cluster_size
* type_sz(src
.type
) >= REG_SIZE
* 2) {
4636 /* In this case, CLUSTER_BROADCAST instruction isn't needed because
4637 * the distance between clusters is at least 2 GRFs. In this case,
4638 * we don't need the weird striding of the CLUSTER_BROADCAST
4639 * instruction and can just do regular MOVs.
4641 assert((cluster_size
* type_sz(src
.type
)) % (REG_SIZE
* 2) == 0);
4642 const unsigned groups
=
4643 (dispatch_width
* type_sz(src
.type
)) / (REG_SIZE
* 2);
4644 const unsigned group_size
= dispatch_width
/ groups
;
4645 for (unsigned i
= 0; i
< groups
; i
++) {
4646 const unsigned cluster
= (i
* group_size
) / cluster_size
;
4647 const unsigned comp
= cluster
* cluster_size
+ (cluster_size
- 1);
4648 bld
.group(group_size
, i
).MOV(horiz_offset(dest
, i
* group_size
),
4649 component(scan
, comp
));
4652 bld
.emit(SHADER_OPCODE_CLUSTER_BROADCAST
, dest
, scan
,
4653 brw_imm_ud(cluster_size
- 1), brw_imm_ud(cluster_size
));
4658 case nir_intrinsic_inclusive_scan
:
4659 case nir_intrinsic_exclusive_scan
: {
4660 fs_reg src
= get_nir_src(instr
->src
[0]);
4661 nir_op redop
= (nir_op
)nir_intrinsic_reduction_op(instr
);
4663 /* Figure out the source type */
4664 src
.type
= brw_type_for_nir_type(devinfo
,
4665 (nir_alu_type
)(nir_op_infos
[redop
].input_types
[0] |
4666 nir_src_bit_size(instr
->src
[0])));
4668 fs_reg identity
= brw_nir_reduction_op_identity(bld
, redop
, src
.type
);
4669 opcode brw_op
= brw_op_for_nir_reduction_op(redop
);
4670 brw_conditional_mod cond_mod
= brw_cond_mod_for_nir_reduction_op(redop
);
4672 /* Set up a register for all of our scratching around and initialize it
4673 * to reduction operation's identity value.
4675 fs_reg scan
= bld
.vgrf(src
.type
);
4676 const fs_builder allbld
= bld
.exec_all();
4677 allbld
.emit(SHADER_OPCODE_SEL_EXEC
, scan
, src
, identity
);
4679 if (instr
->intrinsic
== nir_intrinsic_exclusive_scan
) {
4680 /* Exclusive scan is a bit harder because we have to do an annoying
4681 * shift of the contents before we can begin. To make things worse,
4682 * we can't do this with a normal stride; we have to use indirects.
4684 fs_reg shifted
= bld
.vgrf(src
.type
);
4685 fs_reg idx
= bld
.vgrf(BRW_REGISTER_TYPE_W
);
4686 allbld
.ADD(idx
, nir_system_values
[SYSTEM_VALUE_SUBGROUP_INVOCATION
],
4688 allbld
.emit(SHADER_OPCODE_SHUFFLE
, shifted
, scan
, idx
);
4689 allbld
.group(1, 0).MOV(component(shifted
, 0), identity
);
4693 bld
.emit_scan(brw_op
, scan
, dispatch_width
, cond_mod
);
4695 bld
.MOV(retype(dest
, src
.type
), scan
);
4699 case nir_intrinsic_begin_invocation_interlock
: {
4700 const fs_builder ubld
= bld
.group(8, 0);
4701 const fs_reg tmp
= ubld
.vgrf(BRW_REGISTER_TYPE_UD
, 2);
4703 ubld
.emit(SHADER_OPCODE_INTERLOCK
, tmp
)->size_written
= 2 *
4709 case nir_intrinsic_end_invocation_interlock
: {
4710 /* We don't need to do anything here */
4715 unreachable("unknown intrinsic");
4720 fs_visitor::nir_emit_ssbo_atomic(const fs_builder
&bld
,
4721 int op
, nir_intrinsic_instr
*instr
)
4723 if (stage
== MESA_SHADER_FRAGMENT
)
4724 brw_wm_prog_data(prog_data
)->has_side_effects
= true;
4727 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
4728 dest
= get_nir_dest(instr
->dest
);
4730 fs_reg srcs
[SURFACE_LOGICAL_NUM_SRCS
];
4731 srcs
[SURFACE_LOGICAL_SRC_SURFACE
] = get_nir_ssbo_intrinsic_index(bld
, instr
);
4732 srcs
[SURFACE_LOGICAL_SRC_ADDRESS
] = get_nir_src(instr
->src
[1]);
4733 srcs
[SURFACE_LOGICAL_SRC_IMM_DIMS
] = brw_imm_ud(1);
4734 srcs
[SURFACE_LOGICAL_SRC_IMM_ARG
] = brw_imm_ud(op
);
4737 if (op
!= BRW_AOP_INC
&& op
!= BRW_AOP_DEC
&& op
!= BRW_AOP_PREDEC
)
4738 data
= get_nir_src(instr
->src
[2]);
4740 if (op
== BRW_AOP_CMPWR
) {
4741 fs_reg tmp
= bld
.vgrf(data
.type
, 2);
4742 fs_reg sources
[2] = { data
, get_nir_src(instr
->src
[3]) };
4743 bld
.LOAD_PAYLOAD(tmp
, sources
, 2, 0);
4746 srcs
[SURFACE_LOGICAL_SRC_DATA
] = data
;
4748 /* Emit the actual atomic operation */
4750 bld
.emit(SHADER_OPCODE_UNTYPED_ATOMIC_LOGICAL
,
4751 dest
, srcs
, SURFACE_LOGICAL_NUM_SRCS
);
4755 fs_visitor::nir_emit_ssbo_atomic_float(const fs_builder
&bld
,
4756 int op
, nir_intrinsic_instr
*instr
)
4758 if (stage
== MESA_SHADER_FRAGMENT
)
4759 brw_wm_prog_data(prog_data
)->has_side_effects
= true;
4762 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
4763 dest
= get_nir_dest(instr
->dest
);
4765 fs_reg srcs
[SURFACE_LOGICAL_NUM_SRCS
];
4766 srcs
[SURFACE_LOGICAL_SRC_SURFACE
] = get_nir_ssbo_intrinsic_index(bld
, instr
);
4767 srcs
[SURFACE_LOGICAL_SRC_ADDRESS
] = get_nir_src(instr
->src
[1]);
4768 srcs
[SURFACE_LOGICAL_SRC_IMM_DIMS
] = brw_imm_ud(1);
4769 srcs
[SURFACE_LOGICAL_SRC_IMM_ARG
] = brw_imm_ud(op
);
4771 fs_reg data
= get_nir_src(instr
->src
[2]);
4772 if (op
== BRW_AOP_FCMPWR
) {
4773 fs_reg tmp
= bld
.vgrf(data
.type
, 2);
4774 fs_reg sources
[2] = { data
, get_nir_src(instr
->src
[3]) };
4775 bld
.LOAD_PAYLOAD(tmp
, sources
, 2, 0);
4778 srcs
[SURFACE_LOGICAL_SRC_DATA
] = data
;
4780 /* Emit the actual atomic operation */
4782 bld
.emit(SHADER_OPCODE_UNTYPED_ATOMIC_FLOAT_LOGICAL
,
4783 dest
, srcs
, SURFACE_LOGICAL_NUM_SRCS
);
4787 fs_visitor::nir_emit_shared_atomic(const fs_builder
&bld
,
4788 int op
, nir_intrinsic_instr
*instr
)
4791 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
4792 dest
= get_nir_dest(instr
->dest
);
4794 fs_reg srcs
[SURFACE_LOGICAL_NUM_SRCS
];
4795 srcs
[SURFACE_LOGICAL_SRC_SURFACE
] = brw_imm_ud(GEN7_BTI_SLM
);
4796 srcs
[SURFACE_LOGICAL_SRC_IMM_DIMS
] = brw_imm_ud(1);
4797 srcs
[SURFACE_LOGICAL_SRC_IMM_ARG
] = brw_imm_ud(op
);
4800 if (op
!= BRW_AOP_INC
&& op
!= BRW_AOP_DEC
&& op
!= BRW_AOP_PREDEC
)
4801 data
= get_nir_src(instr
->src
[1]);
4802 if (op
== BRW_AOP_CMPWR
) {
4803 fs_reg tmp
= bld
.vgrf(data
.type
, 2);
4804 fs_reg sources
[2] = { data
, get_nir_src(instr
->src
[2]) };
4805 bld
.LOAD_PAYLOAD(tmp
, sources
, 2, 0);
4808 srcs
[SURFACE_LOGICAL_SRC_DATA
] = data
;
4810 /* Get the offset */
4811 if (nir_src_is_const(instr
->src
[0])) {
4812 srcs
[SURFACE_LOGICAL_SRC_ADDRESS
] =
4813 brw_imm_ud(instr
->const_index
[0] + nir_src_as_uint(instr
->src
[0]));
4815 srcs
[SURFACE_LOGICAL_SRC_ADDRESS
] = vgrf(glsl_type::uint_type
);
4816 bld
.ADD(srcs
[SURFACE_LOGICAL_SRC_ADDRESS
],
4817 retype(get_nir_src(instr
->src
[0]), BRW_REGISTER_TYPE_UD
),
4818 brw_imm_ud(instr
->const_index
[0]));
4821 /* Emit the actual atomic operation operation */
4823 bld
.emit(SHADER_OPCODE_UNTYPED_ATOMIC_LOGICAL
,
4824 dest
, srcs
, SURFACE_LOGICAL_NUM_SRCS
);
4828 fs_visitor::nir_emit_shared_atomic_float(const fs_builder
&bld
,
4829 int op
, nir_intrinsic_instr
*instr
)
4832 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
4833 dest
= get_nir_dest(instr
->dest
);
4835 fs_reg srcs
[SURFACE_LOGICAL_NUM_SRCS
];
4836 srcs
[SURFACE_LOGICAL_SRC_SURFACE
] = brw_imm_ud(GEN7_BTI_SLM
);
4837 srcs
[SURFACE_LOGICAL_SRC_IMM_DIMS
] = brw_imm_ud(1);
4838 srcs
[SURFACE_LOGICAL_SRC_IMM_ARG
] = brw_imm_ud(op
);
4840 fs_reg data
= get_nir_src(instr
->src
[1]);
4841 if (op
== BRW_AOP_FCMPWR
) {
4842 fs_reg tmp
= bld
.vgrf(data
.type
, 2);
4843 fs_reg sources
[2] = { data
, get_nir_src(instr
->src
[2]) };
4844 bld
.LOAD_PAYLOAD(tmp
, sources
, 2, 0);
4847 srcs
[SURFACE_LOGICAL_SRC_DATA
] = data
;
4849 /* Get the offset */
4850 if (nir_src_is_const(instr
->src
[0])) {
4851 srcs
[SURFACE_LOGICAL_SRC_ADDRESS
] =
4852 brw_imm_ud(instr
->const_index
[0] + nir_src_as_uint(instr
->src
[0]));
4854 srcs
[SURFACE_LOGICAL_SRC_ADDRESS
] = vgrf(glsl_type::uint_type
);
4855 bld
.ADD(srcs
[SURFACE_LOGICAL_SRC_ADDRESS
],
4856 retype(get_nir_src(instr
->src
[0]), BRW_REGISTER_TYPE_UD
),
4857 brw_imm_ud(instr
->const_index
[0]));
4860 /* Emit the actual atomic operation operation */
4862 bld
.emit(SHADER_OPCODE_UNTYPED_ATOMIC_FLOAT_LOGICAL
,
4863 dest
, srcs
, SURFACE_LOGICAL_NUM_SRCS
);
4867 fs_visitor::nir_emit_global_atomic(const fs_builder
&bld
,
4868 int op
, nir_intrinsic_instr
*instr
)
4870 if (stage
== MESA_SHADER_FRAGMENT
)
4871 brw_wm_prog_data(prog_data
)->has_side_effects
= true;
4874 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
4875 dest
= get_nir_dest(instr
->dest
);
4877 fs_reg addr
= get_nir_src(instr
->src
[0]);
4880 if (op
!= BRW_AOP_INC
&& op
!= BRW_AOP_DEC
&& op
!= BRW_AOP_PREDEC
)
4881 data
= get_nir_src(instr
->src
[1]);
4883 if (op
== BRW_AOP_CMPWR
) {
4884 fs_reg tmp
= bld
.vgrf(data
.type
, 2);
4885 fs_reg sources
[2] = { data
, get_nir_src(instr
->src
[2]) };
4886 bld
.LOAD_PAYLOAD(tmp
, sources
, 2, 0);
4890 bld
.emit(SHADER_OPCODE_A64_UNTYPED_ATOMIC_LOGICAL
,
4891 dest
, addr
, data
, brw_imm_ud(op
));
4895 fs_visitor::nir_emit_global_atomic_float(const fs_builder
&bld
,
4896 int op
, nir_intrinsic_instr
*instr
)
4898 if (stage
== MESA_SHADER_FRAGMENT
)
4899 brw_wm_prog_data(prog_data
)->has_side_effects
= true;
4901 assert(nir_intrinsic_infos
[instr
->intrinsic
].has_dest
);
4902 fs_reg dest
= get_nir_dest(instr
->dest
);
4904 fs_reg addr
= get_nir_src(instr
->src
[0]);
4906 assert(op
!= BRW_AOP_INC
&& op
!= BRW_AOP_DEC
&& op
!= BRW_AOP_PREDEC
);
4907 fs_reg data
= get_nir_src(instr
->src
[1]);
4909 if (op
== BRW_AOP_FCMPWR
) {
4910 fs_reg tmp
= bld
.vgrf(data
.type
, 2);
4911 fs_reg sources
[2] = { data
, get_nir_src(instr
->src
[2]) };
4912 bld
.LOAD_PAYLOAD(tmp
, sources
, 2, 0);
4916 bld
.emit(SHADER_OPCODE_A64_UNTYPED_ATOMIC_LOGICAL
,
4917 dest
, addr
, data
, brw_imm_ud(op
));
4921 fs_visitor::nir_emit_texture(const fs_builder
&bld
, nir_tex_instr
*instr
)
4923 unsigned texture
= instr
->texture_index
;
4924 unsigned sampler
= instr
->sampler_index
;
4926 fs_reg srcs
[TEX_LOGICAL_NUM_SRCS
];
4928 srcs
[TEX_LOGICAL_SRC_SURFACE
] = brw_imm_ud(texture
);
4929 srcs
[TEX_LOGICAL_SRC_SAMPLER
] = brw_imm_ud(sampler
);
4931 int lod_components
= 0;
4933 /* The hardware requires a LOD for buffer textures */
4934 if (instr
->sampler_dim
== GLSL_SAMPLER_DIM_BUF
)
4935 srcs
[TEX_LOGICAL_SRC_LOD
] = brw_imm_d(0);
4937 uint32_t header_bits
= 0;
4938 for (unsigned i
= 0; i
< instr
->num_srcs
; i
++) {
4939 fs_reg src
= get_nir_src(instr
->src
[i
].src
);
4940 switch (instr
->src
[i
].src_type
) {
4941 case nir_tex_src_bias
:
4942 srcs
[TEX_LOGICAL_SRC_LOD
] =
4943 retype(get_nir_src_imm(instr
->src
[i
].src
), BRW_REGISTER_TYPE_F
);
4945 case nir_tex_src_comparator
:
4946 srcs
[TEX_LOGICAL_SRC_SHADOW_C
] = retype(src
, BRW_REGISTER_TYPE_F
);
4948 case nir_tex_src_coord
:
4949 switch (instr
->op
) {
4951 case nir_texop_txf_ms
:
4952 case nir_texop_txf_ms_mcs
:
4953 case nir_texop_samples_identical
:
4954 srcs
[TEX_LOGICAL_SRC_COORDINATE
] = retype(src
, BRW_REGISTER_TYPE_D
);
4957 srcs
[TEX_LOGICAL_SRC_COORDINATE
] = retype(src
, BRW_REGISTER_TYPE_F
);
4961 case nir_tex_src_ddx
:
4962 srcs
[TEX_LOGICAL_SRC_LOD
] = retype(src
, BRW_REGISTER_TYPE_F
);
4963 lod_components
= nir_tex_instr_src_size(instr
, i
);
4965 case nir_tex_src_ddy
:
4966 srcs
[TEX_LOGICAL_SRC_LOD2
] = retype(src
, BRW_REGISTER_TYPE_F
);
4968 case nir_tex_src_lod
:
4969 switch (instr
->op
) {
4971 srcs
[TEX_LOGICAL_SRC_LOD
] =
4972 retype(get_nir_src_imm(instr
->src
[i
].src
), BRW_REGISTER_TYPE_UD
);
4975 srcs
[TEX_LOGICAL_SRC_LOD
] =
4976 retype(get_nir_src_imm(instr
->src
[i
].src
), BRW_REGISTER_TYPE_D
);
4979 srcs
[TEX_LOGICAL_SRC_LOD
] =
4980 retype(get_nir_src_imm(instr
->src
[i
].src
), BRW_REGISTER_TYPE_F
);
4984 case nir_tex_src_min_lod
:
4985 srcs
[TEX_LOGICAL_SRC_MIN_LOD
] =
4986 retype(get_nir_src_imm(instr
->src
[i
].src
), BRW_REGISTER_TYPE_F
);
4988 case nir_tex_src_ms_index
:
4989 srcs
[TEX_LOGICAL_SRC_SAMPLE_INDEX
] = retype(src
, BRW_REGISTER_TYPE_UD
);
4992 case nir_tex_src_offset
: {
4993 nir_const_value
*const_offset
=
4994 nir_src_as_const_value(instr
->src
[i
].src
);
4995 assert(nir_src_bit_size(instr
->src
[i
].src
) == 32);
4996 unsigned offset_bits
= 0;
4998 brw_texture_offset(const_offset
->i32
,
4999 nir_tex_instr_src_size(instr
, i
),
5001 header_bits
|= offset_bits
;
5003 srcs
[TEX_LOGICAL_SRC_TG4_OFFSET
] =
5004 retype(src
, BRW_REGISTER_TYPE_D
);
5009 case nir_tex_src_projector
:
5010 unreachable("should be lowered");
5012 case nir_tex_src_texture_offset
: {
5013 /* Emit code to evaluate the actual indexing expression */
5014 fs_reg tmp
= vgrf(glsl_type::uint_type
);
5015 bld
.ADD(tmp
, src
, brw_imm_ud(texture
));
5016 srcs
[TEX_LOGICAL_SRC_SURFACE
] = bld
.emit_uniformize(tmp
);
5020 case nir_tex_src_sampler_offset
: {
5021 /* Emit code to evaluate the actual indexing expression */
5022 fs_reg tmp
= vgrf(glsl_type::uint_type
);
5023 bld
.ADD(tmp
, src
, brw_imm_ud(sampler
));
5024 srcs
[TEX_LOGICAL_SRC_SAMPLER
] = bld
.emit_uniformize(tmp
);
5028 case nir_tex_src_ms_mcs
:
5029 assert(instr
->op
== nir_texop_txf_ms
);
5030 srcs
[TEX_LOGICAL_SRC_MCS
] = retype(src
, BRW_REGISTER_TYPE_D
);
5033 case nir_tex_src_plane
: {
5034 const uint32_t plane
= nir_src_as_uint(instr
->src
[i
].src
);
5035 const uint32_t texture_index
=
5036 instr
->texture_index
+
5037 stage_prog_data
->binding_table
.plane_start
[plane
] -
5038 stage_prog_data
->binding_table
.texture_start
;
5040 srcs
[TEX_LOGICAL_SRC_SURFACE
] = brw_imm_ud(texture_index
);
5045 unreachable("unknown texture source");
5049 if (srcs
[TEX_LOGICAL_SRC_MCS
].file
== BAD_FILE
&&
5050 (instr
->op
== nir_texop_txf_ms
||
5051 instr
->op
== nir_texop_samples_identical
)) {
5052 if (devinfo
->gen
>= 7 &&
5053 key_tex
->compressed_multisample_layout_mask
& (1 << texture
)) {
5054 srcs
[TEX_LOGICAL_SRC_MCS
] =
5055 emit_mcs_fetch(srcs
[TEX_LOGICAL_SRC_COORDINATE
],
5056 instr
->coord_components
,
5057 srcs
[TEX_LOGICAL_SRC_SURFACE
]);
5059 srcs
[TEX_LOGICAL_SRC_MCS
] = brw_imm_ud(0u);
5063 srcs
[TEX_LOGICAL_SRC_COORD_COMPONENTS
] = brw_imm_d(instr
->coord_components
);
5064 srcs
[TEX_LOGICAL_SRC_GRAD_COMPONENTS
] = brw_imm_d(lod_components
);
5067 switch (instr
->op
) {
5069 opcode
= (stage
== MESA_SHADER_FRAGMENT
? SHADER_OPCODE_TEX_LOGICAL
:
5070 SHADER_OPCODE_TXL_LOGICAL
);
5073 opcode
= FS_OPCODE_TXB_LOGICAL
;
5076 opcode
= SHADER_OPCODE_TXL_LOGICAL
;
5079 opcode
= SHADER_OPCODE_TXD_LOGICAL
;
5082 opcode
= SHADER_OPCODE_TXF_LOGICAL
;
5084 case nir_texop_txf_ms
:
5085 if ((key_tex
->msaa_16
& (1 << sampler
)))
5086 opcode
= SHADER_OPCODE_TXF_CMS_W_LOGICAL
;
5088 opcode
= SHADER_OPCODE_TXF_CMS_LOGICAL
;
5090 case nir_texop_txf_ms_mcs
:
5091 opcode
= SHADER_OPCODE_TXF_MCS_LOGICAL
;
5093 case nir_texop_query_levels
:
5095 opcode
= SHADER_OPCODE_TXS_LOGICAL
;
5098 opcode
= SHADER_OPCODE_LOD_LOGICAL
;
5101 if (srcs
[TEX_LOGICAL_SRC_TG4_OFFSET
].file
!= BAD_FILE
)
5102 opcode
= SHADER_OPCODE_TG4_OFFSET_LOGICAL
;
5104 opcode
= SHADER_OPCODE_TG4_LOGICAL
;
5106 case nir_texop_texture_samples
:
5107 opcode
= SHADER_OPCODE_SAMPLEINFO_LOGICAL
;
5109 case nir_texop_samples_identical
: {
5110 fs_reg dst
= retype(get_nir_dest(instr
->dest
), BRW_REGISTER_TYPE_D
);
5112 /* If mcs is an immediate value, it means there is no MCS. In that case
5113 * just return false.
5115 if (srcs
[TEX_LOGICAL_SRC_MCS
].file
== BRW_IMMEDIATE_VALUE
) {
5116 bld
.MOV(dst
, brw_imm_ud(0u));
5117 } else if ((key_tex
->msaa_16
& (1 << sampler
))) {
5118 fs_reg tmp
= vgrf(glsl_type::uint_type
);
5119 bld
.OR(tmp
, srcs
[TEX_LOGICAL_SRC_MCS
],
5120 offset(srcs
[TEX_LOGICAL_SRC_MCS
], bld
, 1));
5121 bld
.CMP(dst
, tmp
, brw_imm_ud(0u), BRW_CONDITIONAL_EQ
);
5123 bld
.CMP(dst
, srcs
[TEX_LOGICAL_SRC_MCS
], brw_imm_ud(0u),
5124 BRW_CONDITIONAL_EQ
);
5129 unreachable("unknown texture opcode");
5132 if (instr
->op
== nir_texop_tg4
) {
5133 if (instr
->component
== 1 &&
5134 key_tex
->gather_channel_quirk_mask
& (1 << texture
)) {
5135 /* gather4 sampler is broken for green channel on RG32F --
5136 * we must ask for blue instead.
5138 header_bits
|= 2 << 16;
5140 header_bits
|= instr
->component
<< 16;
5144 fs_reg dst
= bld
.vgrf(brw_type_for_nir_type(devinfo
, instr
->dest_type
), 4);
5145 fs_inst
*inst
= bld
.emit(opcode
, dst
, srcs
, ARRAY_SIZE(srcs
));
5146 inst
->offset
= header_bits
;
5148 const unsigned dest_size
= nir_tex_instr_dest_size(instr
);
5149 if (devinfo
->gen
>= 9 &&
5150 instr
->op
!= nir_texop_tg4
&& instr
->op
!= nir_texop_query_levels
) {
5151 unsigned write_mask
= instr
->dest
.is_ssa
?
5152 nir_ssa_def_components_read(&instr
->dest
.ssa
):
5153 (1 << dest_size
) - 1;
5154 assert(write_mask
!= 0); /* dead code should have been eliminated */
5155 inst
->size_written
= util_last_bit(write_mask
) *
5156 inst
->dst
.component_size(inst
->exec_size
);
5158 inst
->size_written
= 4 * inst
->dst
.component_size(inst
->exec_size
);
5161 if (srcs
[TEX_LOGICAL_SRC_SHADOW_C
].file
!= BAD_FILE
)
5162 inst
->shadow_compare
= true;
5164 if (instr
->op
== nir_texop_tg4
&& devinfo
->gen
== 6)
5165 emit_gen6_gather_wa(key_tex
->gen6_gather_wa
[texture
], dst
);
5168 for (unsigned i
= 0; i
< dest_size
; i
++)
5169 nir_dest
[i
] = offset(dst
, bld
, i
);
5171 if (instr
->op
== nir_texop_query_levels
) {
5172 /* # levels is in .w */
5173 nir_dest
[0] = offset(dst
, bld
, 3);
5174 } else if (instr
->op
== nir_texop_txs
&&
5175 dest_size
>= 3 && devinfo
->gen
< 7) {
5176 /* Gen4-6 return 0 instead of 1 for single layer surfaces. */
5177 fs_reg depth
= offset(dst
, bld
, 2);
5178 nir_dest
[2] = vgrf(glsl_type::int_type
);
5179 bld
.emit_minmax(nir_dest
[2], depth
, brw_imm_d(1), BRW_CONDITIONAL_GE
);
5182 bld
.LOAD_PAYLOAD(get_nir_dest(instr
->dest
), nir_dest
, dest_size
, 0);
5186 fs_visitor::nir_emit_jump(const fs_builder
&bld
, nir_jump_instr
*instr
)
5188 switch (instr
->type
) {
5189 case nir_jump_break
:
5190 bld
.emit(BRW_OPCODE_BREAK
);
5192 case nir_jump_continue
:
5193 bld
.emit(BRW_OPCODE_CONTINUE
);
5195 case nir_jump_return
:
5197 unreachable("unknown jump");
5202 * This helper takes a source register and un/shuffles it into the destination
5205 * If source type size is smaller than destination type size the operation
5206 * needed is a component shuffle. The opposite case would be an unshuffle. If
5207 * source/destination type size is equal a shuffle is done that would be
5208 * equivalent to a simple MOV.
5210 * For example, if source is a 16-bit type and destination is 32-bit. A 3
5211 * components .xyz 16-bit vector on SIMD8 would be.
5213 * |x1|x2|x3|x4|x5|x6|x7|x8|y1|y2|y3|y4|y5|y6|y7|y8|
5214 * |z1|z2|z3|z4|z5|z6|z7|z8| | | | | | | | |
5216 * This helper will return the following 2 32-bit components with the 16-bit
5219 * |x1 y1|x2 y2|x3 y3|x4 y4|x5 y5|x6 y6|x7 y7|x8 y8|
5220 * |z1 |z2 |z3 |z4 |z5 |z6 |z7 |z8 |
5222 * For unshuffle, the example would be the opposite, a 64-bit type source
5223 * and a 32-bit destination. A 2 component .xy 64-bit vector on SIMD8
5226 * | x1l x1h | x2l x2h | x3l x3h | x4l x4h |
5227 * | x5l x5h | x6l x6h | x7l x7h | x8l x8h |
5228 * | y1l y1h | y2l y2h | y3l y3h | y4l y4h |
5229 * | y5l y5h | y6l y6h | y7l y7h | y8l y8h |
5231 * The returned result would be the following 4 32-bit components unshuffled:
5233 * | x1l | x2l | x3l | x4l | x5l | x6l | x7l | x8l |
5234 * | x1h | x2h | x3h | x4h | x5h | x6h | x7h | x8h |
5235 * | y1l | y2l | y3l | y4l | y5l | y6l | y7l | y8l |
5236 * | y1h | y2h | y3h | y4h | y5h | y6h | y7h | y8h |
5238 * - Source and destination register must not be overlapped.
5239 * - components units are measured in terms of the smaller type between
5240 * source and destination because we are un/shuffling the smaller
5241 * components from/into the bigger ones.
5242 * - first_component parameter allows skipping source components.
5245 shuffle_src_to_dst(const fs_builder
&bld
,
5248 uint32_t first_component
,
5249 uint32_t components
)
5251 if (type_sz(src
.type
) == type_sz(dst
.type
)) {
5252 assert(!regions_overlap(dst
,
5253 type_sz(dst
.type
) * bld
.dispatch_width() * components
,
5254 offset(src
, bld
, first_component
),
5255 type_sz(src
.type
) * bld
.dispatch_width() * components
));
5256 for (unsigned i
= 0; i
< components
; i
++) {
5257 bld
.MOV(retype(offset(dst
, bld
, i
), src
.type
),
5258 offset(src
, bld
, i
+ first_component
));
5260 } else if (type_sz(src
.type
) < type_sz(dst
.type
)) {
5261 /* Source is shuffled into destination */
5262 unsigned size_ratio
= type_sz(dst
.type
) / type_sz(src
.type
);
5263 assert(!regions_overlap(dst
,
5264 type_sz(dst
.type
) * bld
.dispatch_width() *
5265 DIV_ROUND_UP(components
, size_ratio
),
5266 offset(src
, bld
, first_component
),
5267 type_sz(src
.type
) * bld
.dispatch_width() * components
));
5269 brw_reg_type shuffle_type
=
5270 brw_reg_type_from_bit_size(8 * type_sz(src
.type
),
5271 BRW_REGISTER_TYPE_D
);
5272 for (unsigned i
= 0; i
< components
; i
++) {
5273 fs_reg shuffle_component_i
=
5274 subscript(offset(dst
, bld
, i
/ size_ratio
),
5275 shuffle_type
, i
% size_ratio
);
5276 bld
.MOV(shuffle_component_i
,
5277 retype(offset(src
, bld
, i
+ first_component
), shuffle_type
));
5280 /* Source is unshuffled into destination */
5281 unsigned size_ratio
= type_sz(src
.type
) / type_sz(dst
.type
);
5282 assert(!regions_overlap(dst
,
5283 type_sz(dst
.type
) * bld
.dispatch_width() * components
,
5284 offset(src
, bld
, first_component
/ size_ratio
),
5285 type_sz(src
.type
) * bld
.dispatch_width() *
5286 DIV_ROUND_UP(components
+ (first_component
% size_ratio
),
5289 brw_reg_type shuffle_type
=
5290 brw_reg_type_from_bit_size(8 * type_sz(dst
.type
),
5291 BRW_REGISTER_TYPE_D
);
5292 for (unsigned i
= 0; i
< components
; i
++) {
5293 fs_reg shuffle_component_i
=
5294 subscript(offset(src
, bld
, (first_component
+ i
) / size_ratio
),
5295 shuffle_type
, (first_component
+ i
) % size_ratio
);
5296 bld
.MOV(retype(offset(dst
, bld
, i
), shuffle_type
),
5297 shuffle_component_i
);
5303 shuffle_from_32bit_read(const fs_builder
&bld
,
5306 uint32_t first_component
,
5307 uint32_t components
)
5309 assert(type_sz(src
.type
) == 4);
5311 /* This function takes components in units of the destination type while
5312 * shuffle_src_to_dst takes components in units of the smallest type
5314 if (type_sz(dst
.type
) > 4) {
5315 assert(type_sz(dst
.type
) == 8);
5316 first_component
*= 2;
5320 shuffle_src_to_dst(bld
, dst
, src
, first_component
, components
);
5324 shuffle_for_32bit_write(const fs_builder
&bld
,
5326 uint32_t first_component
,
5327 uint32_t components
)
5329 fs_reg dst
= bld
.vgrf(BRW_REGISTER_TYPE_D
,
5330 DIV_ROUND_UP (components
* type_sz(src
.type
), 4));
5331 /* This function takes components in units of the source type while
5332 * shuffle_src_to_dst takes components in units of the smallest type
5334 if (type_sz(src
.type
) > 4) {
5335 assert(type_sz(src
.type
) == 8);
5336 first_component
*= 2;
5340 shuffle_src_to_dst(bld
, dst
, src
, first_component
, components
);
5346 setup_imm_df(const fs_builder
&bld
, double v
)
5348 const struct gen_device_info
*devinfo
= bld
.shader
->devinfo
;
5349 assert(devinfo
->gen
>= 7);
5351 if (devinfo
->gen
>= 8)
5352 return brw_imm_df(v
);
5354 /* gen7.5 does not support DF immediates straighforward but the DIM
5355 * instruction allows to set the 64-bit immediate value.
5357 if (devinfo
->is_haswell
) {
5358 const fs_builder ubld
= bld
.exec_all().group(1, 0);
5359 fs_reg dst
= ubld
.vgrf(BRW_REGISTER_TYPE_DF
, 1);
5360 ubld
.DIM(dst
, brw_imm_df(v
));
5361 return component(dst
, 0);
5364 /* gen7 does not support DF immediates, so we generate a 64-bit constant by
5365 * writing the low 32-bit of the constant to suboffset 0 of a VGRF and
5366 * the high 32-bit to suboffset 4 and then applying a stride of 0.
5368 * Alternatively, we could also produce a normal VGRF (without stride 0)
5369 * by writing to all the channels in the VGRF, however, that would hit the
5370 * gen7 bug where we have to split writes that span more than 1 register
5371 * into instructions with a width of 4 (otherwise the write to the second
5372 * register written runs into an execmask hardware bug) which isn't very
5385 const fs_builder ubld
= bld
.exec_all().group(1, 0);
5386 const fs_reg tmp
= ubld
.vgrf(BRW_REGISTER_TYPE_UD
, 2);
5387 ubld
.MOV(tmp
, brw_imm_ud(di
.i1
));
5388 ubld
.MOV(horiz_offset(tmp
, 1), brw_imm_ud(di
.i2
));
5390 return component(retype(tmp
, BRW_REGISTER_TYPE_DF
), 0);
5394 setup_imm_b(const fs_builder
&bld
, int8_t v
)
5396 const fs_reg tmp
= bld
.vgrf(BRW_REGISTER_TYPE_B
);
5397 bld
.MOV(tmp
, brw_imm_w(v
));
5402 setup_imm_ub(const fs_builder
&bld
, uint8_t v
)
5404 const fs_reg tmp
= bld
.vgrf(BRW_REGISTER_TYPE_UB
);
5405 bld
.MOV(tmp
, brw_imm_uw(v
));