2 * Copyright © 2010 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 #include "compiler/glsl/ir.h"
28 #include "nir_search_helpers.h"
29 #include "util/u_math.h"
30 #include "util/bitscan.h"
35 fs_visitor::emit_nir_code()
37 /* emit the arrays used for inputs and outputs - load/store intrinsics will
38 * be converted to reads/writes of these arrays
42 nir_emit_system_values();
44 nir_emit_impl(nir_shader_get_entrypoint((nir_shader
*)nir
));
48 fs_visitor::nir_setup_outputs()
50 if (stage
== MESA_SHADER_TESS_CTRL
|| stage
== MESA_SHADER_FRAGMENT
)
53 unsigned vec4s
[VARYING_SLOT_TESS_MAX
] = { 0, };
55 /* Calculate the size of output registers in a separate pass, before
56 * allocating them. With ARB_enhanced_layouts, multiple output variables
57 * may occupy the same slot, but have different type sizes.
59 nir_foreach_variable(var
, &nir
->outputs
) {
60 const int loc
= var
->data
.driver_location
;
61 const unsigned var_vec4s
=
62 var
->data
.compact
? DIV_ROUND_UP(glsl_get_length(var
->type
), 4)
63 : type_size_vec4(var
->type
, true);
64 vec4s
[loc
] = MAX2(vec4s
[loc
], var_vec4s
);
67 for (unsigned loc
= 0; loc
< ARRAY_SIZE(vec4s
);) {
68 if (vec4s
[loc
] == 0) {
73 unsigned reg_size
= vec4s
[loc
];
75 /* Check if there are any ranges that start within this range and extend
76 * past it. If so, include them in this allocation.
78 for (unsigned i
= 1; i
< reg_size
; i
++)
79 reg_size
= MAX2(vec4s
[i
+ loc
] + i
, reg_size
);
81 fs_reg reg
= bld
.vgrf(BRW_REGISTER_TYPE_F
, 4 * reg_size
);
82 for (unsigned i
= 0; i
< reg_size
; i
++)
83 outputs
[loc
+ i
] = offset(reg
, bld
, 4 * i
);
90 fs_visitor::nir_setup_uniforms()
92 /* Only the first compile gets to set up uniforms. */
93 if (push_constant_loc
) {
94 assert(pull_constant_loc
);
98 uniforms
= nir
->num_uniforms
/ 4;
100 if (stage
== MESA_SHADER_COMPUTE
) {
101 /* Add a uniform for the thread local id. It must be the last uniform
104 assert(uniforms
== prog_data
->nr_params
);
105 uint32_t *param
= brw_stage_prog_data_add_params(prog_data
, 1);
106 *param
= BRW_PARAM_BUILTIN_SUBGROUP_ID
;
107 subgroup_id
= fs_reg(UNIFORM
, uniforms
++, BRW_REGISTER_TYPE_UD
);
112 emit_system_values_block(nir_block
*block
, fs_visitor
*v
)
116 nir_foreach_instr(instr
, block
) {
117 if (instr
->type
!= nir_instr_type_intrinsic
)
120 nir_intrinsic_instr
*intrin
= nir_instr_as_intrinsic(instr
);
121 switch (intrin
->intrinsic
) {
122 case nir_intrinsic_load_vertex_id
:
123 case nir_intrinsic_load_base_vertex
:
124 unreachable("should be lowered by nir_lower_system_values().");
126 case nir_intrinsic_load_vertex_id_zero_base
:
127 case nir_intrinsic_load_is_indexed_draw
:
128 case nir_intrinsic_load_first_vertex
:
129 case nir_intrinsic_load_instance_id
:
130 case nir_intrinsic_load_base_instance
:
131 case nir_intrinsic_load_draw_id
:
132 unreachable("should be lowered by brw_nir_lower_vs_inputs().");
134 case nir_intrinsic_load_invocation_id
:
135 if (v
->stage
== MESA_SHADER_TESS_CTRL
)
137 assert(v
->stage
== MESA_SHADER_GEOMETRY
);
138 reg
= &v
->nir_system_values
[SYSTEM_VALUE_INVOCATION_ID
];
139 if (reg
->file
== BAD_FILE
) {
140 const fs_builder abld
= v
->bld
.annotate("gl_InvocationID", NULL
);
141 fs_reg
g1(retype(brw_vec8_grf(1, 0), BRW_REGISTER_TYPE_UD
));
142 fs_reg iid
= abld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
143 abld
.SHR(iid
, g1
, brw_imm_ud(27u));
148 case nir_intrinsic_load_sample_pos
:
149 assert(v
->stage
== MESA_SHADER_FRAGMENT
);
150 reg
= &v
->nir_system_values
[SYSTEM_VALUE_SAMPLE_POS
];
151 if (reg
->file
== BAD_FILE
)
152 *reg
= *v
->emit_samplepos_setup();
155 case nir_intrinsic_load_sample_id
:
156 assert(v
->stage
== MESA_SHADER_FRAGMENT
);
157 reg
= &v
->nir_system_values
[SYSTEM_VALUE_SAMPLE_ID
];
158 if (reg
->file
== BAD_FILE
)
159 *reg
= *v
->emit_sampleid_setup();
162 case nir_intrinsic_load_sample_mask_in
:
163 assert(v
->stage
== MESA_SHADER_FRAGMENT
);
164 assert(v
->devinfo
->gen
>= 7);
165 reg
= &v
->nir_system_values
[SYSTEM_VALUE_SAMPLE_MASK_IN
];
166 if (reg
->file
== BAD_FILE
)
167 *reg
= *v
->emit_samplemaskin_setup();
170 case nir_intrinsic_load_work_group_id
:
171 assert(v
->stage
== MESA_SHADER_COMPUTE
);
172 reg
= &v
->nir_system_values
[SYSTEM_VALUE_WORK_GROUP_ID
];
173 if (reg
->file
== BAD_FILE
)
174 *reg
= *v
->emit_cs_work_group_id_setup();
177 case nir_intrinsic_load_helper_invocation
:
178 assert(v
->stage
== MESA_SHADER_FRAGMENT
);
179 reg
= &v
->nir_system_values
[SYSTEM_VALUE_HELPER_INVOCATION
];
180 if (reg
->file
== BAD_FILE
) {
181 const fs_builder abld
=
182 v
->bld
.annotate("gl_HelperInvocation", NULL
);
184 /* On Gen6+ (gl_HelperInvocation is only exposed on Gen7+) the
185 * pixel mask is in g1.7 of the thread payload.
187 * We move the per-channel pixel enable bit to the low bit of each
188 * channel by shifting the byte containing the pixel mask by the
189 * vector immediate 0x76543210UV.
191 * The region of <1,8,0> reads only 1 byte (the pixel masks for
192 * subspans 0 and 1) in SIMD8 and an additional byte (the pixel
193 * masks for 2 and 3) in SIMD16.
195 fs_reg shifted
= abld
.vgrf(BRW_REGISTER_TYPE_UW
, 1);
197 for (unsigned i
= 0; i
< DIV_ROUND_UP(v
->dispatch_width
, 16); i
++) {
198 const fs_builder hbld
= abld
.group(MIN2(16, v
->dispatch_width
), i
);
199 hbld
.SHR(offset(shifted
, hbld
, i
),
200 stride(retype(brw_vec1_grf(1 + i
, 7),
201 BRW_REGISTER_TYPE_UB
),
203 brw_imm_v(0x76543210));
206 /* A set bit in the pixel mask means the channel is enabled, but
207 * that is the opposite of gl_HelperInvocation so we need to invert
210 * The negate source-modifier bit of logical instructions on Gen8+
211 * performs 1's complement negation, so we can use that instead of
214 fs_reg inverted
= negate(shifted
);
215 if (v
->devinfo
->gen
< 8) {
216 inverted
= abld
.vgrf(BRW_REGISTER_TYPE_UW
);
217 abld
.NOT(inverted
, shifted
);
220 /* We then resolve the 0/1 result to 0/~0 boolean values by ANDing
221 * with 1 and negating.
223 fs_reg anded
= abld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
224 abld
.AND(anded
, inverted
, brw_imm_uw(1));
226 fs_reg dst
= abld
.vgrf(BRW_REGISTER_TYPE_D
, 1);
227 abld
.MOV(dst
, negate(retype(anded
, BRW_REGISTER_TYPE_D
)));
241 fs_visitor::nir_emit_system_values()
243 nir_system_values
= ralloc_array(mem_ctx
, fs_reg
, SYSTEM_VALUE_MAX
);
244 for (unsigned i
= 0; i
< SYSTEM_VALUE_MAX
; i
++) {
245 nir_system_values
[i
] = fs_reg();
248 /* Always emit SUBGROUP_INVOCATION. Dead code will clean it up if we
249 * never end up using it.
252 const fs_builder abld
= bld
.annotate("gl_SubgroupInvocation", NULL
);
253 fs_reg
®
= nir_system_values
[SYSTEM_VALUE_SUBGROUP_INVOCATION
];
254 reg
= abld
.vgrf(BRW_REGISTER_TYPE_UW
);
256 const fs_builder allbld8
= abld
.group(8, 0).exec_all();
257 allbld8
.MOV(reg
, brw_imm_v(0x76543210));
258 if (dispatch_width
> 8)
259 allbld8
.ADD(byte_offset(reg
, 16), reg
, brw_imm_uw(8u));
260 if (dispatch_width
> 16) {
261 const fs_builder allbld16
= abld
.group(16, 0).exec_all();
262 allbld16
.ADD(byte_offset(reg
, 32), reg
, brw_imm_uw(16u));
266 nir_function_impl
*impl
= nir_shader_get_entrypoint((nir_shader
*)nir
);
267 nir_foreach_block(block
, impl
)
268 emit_system_values_block(block
, this);
272 * Returns a type based on a reference_type (word, float, half-float) and a
275 * Reference BRW_REGISTER_TYPE are HF,F,DF,W,D,UW,UD.
277 * @FIXME: 64-bit return types are always DF on integer types to maintain
278 * compability with uses of DF previously to the introduction of int64
282 brw_reg_type_from_bit_size(const unsigned bit_size
,
283 const brw_reg_type reference_type
)
285 switch(reference_type
) {
286 case BRW_REGISTER_TYPE_HF
:
287 case BRW_REGISTER_TYPE_F
:
288 case BRW_REGISTER_TYPE_DF
:
291 return BRW_REGISTER_TYPE_HF
;
293 return BRW_REGISTER_TYPE_F
;
295 return BRW_REGISTER_TYPE_DF
;
297 unreachable("Invalid bit size");
299 case BRW_REGISTER_TYPE_B
:
300 case BRW_REGISTER_TYPE_W
:
301 case BRW_REGISTER_TYPE_D
:
302 case BRW_REGISTER_TYPE_Q
:
305 return BRW_REGISTER_TYPE_B
;
307 return BRW_REGISTER_TYPE_W
;
309 return BRW_REGISTER_TYPE_D
;
311 return BRW_REGISTER_TYPE_Q
;
313 unreachable("Invalid bit size");
315 case BRW_REGISTER_TYPE_UB
:
316 case BRW_REGISTER_TYPE_UW
:
317 case BRW_REGISTER_TYPE_UD
:
318 case BRW_REGISTER_TYPE_UQ
:
321 return BRW_REGISTER_TYPE_UB
;
323 return BRW_REGISTER_TYPE_UW
;
325 return BRW_REGISTER_TYPE_UD
;
327 return BRW_REGISTER_TYPE_UQ
;
329 unreachable("Invalid bit size");
332 unreachable("Unknown type");
337 fs_visitor::nir_emit_impl(nir_function_impl
*impl
)
339 nir_locals
= ralloc_array(mem_ctx
, fs_reg
, impl
->reg_alloc
);
340 for (unsigned i
= 0; i
< impl
->reg_alloc
; i
++) {
341 nir_locals
[i
] = fs_reg();
344 foreach_list_typed(nir_register
, reg
, node
, &impl
->registers
) {
345 unsigned array_elems
=
346 reg
->num_array_elems
== 0 ? 1 : reg
->num_array_elems
;
347 unsigned size
= array_elems
* reg
->num_components
;
348 const brw_reg_type reg_type
= reg
->bit_size
== 8 ? BRW_REGISTER_TYPE_B
:
349 brw_reg_type_from_bit_size(reg
->bit_size
, BRW_REGISTER_TYPE_F
);
350 nir_locals
[reg
->index
] = bld
.vgrf(reg_type
, size
);
353 nir_ssa_values
= reralloc(mem_ctx
, nir_ssa_values
, fs_reg
,
356 nir_emit_cf_list(&impl
->body
);
360 fs_visitor::nir_emit_cf_list(exec_list
*list
)
362 exec_list_validate(list
);
363 foreach_list_typed(nir_cf_node
, node
, node
, list
) {
364 switch (node
->type
) {
366 nir_emit_if(nir_cf_node_as_if(node
));
369 case nir_cf_node_loop
:
370 nir_emit_loop(nir_cf_node_as_loop(node
));
373 case nir_cf_node_block
:
374 nir_emit_block(nir_cf_node_as_block(node
));
378 unreachable("Invalid CFG node block");
384 fs_visitor::nir_emit_if(nir_if
*if_stmt
)
389 /* If the condition has the form !other_condition, use other_condition as
390 * the source, but invert the predicate on the if instruction.
392 nir_alu_instr
*cond
= nir_src_as_alu_instr(if_stmt
->condition
);
393 if (cond
!= NULL
&& cond
->op
== nir_op_inot
) {
394 assert(!cond
->src
[0].negate
);
395 assert(!cond
->src
[0].abs
);
398 cond_reg
= get_nir_src(cond
->src
[0].src
);
401 cond_reg
= get_nir_src(if_stmt
->condition
);
404 /* first, put the condition into f0 */
405 fs_inst
*inst
= bld
.MOV(bld
.null_reg_d(),
406 retype(cond_reg
, BRW_REGISTER_TYPE_D
));
407 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
409 bld
.IF(BRW_PREDICATE_NORMAL
)->predicate_inverse
= invert
;
411 nir_emit_cf_list(&if_stmt
->then_list
);
413 if (!nir_cf_list_is_empty_block(&if_stmt
->else_list
)) {
414 bld
.emit(BRW_OPCODE_ELSE
);
415 nir_emit_cf_list(&if_stmt
->else_list
);
418 bld
.emit(BRW_OPCODE_ENDIF
);
420 if (devinfo
->gen
< 7)
421 limit_dispatch_width(16, "Non-uniform control flow unsupported "
426 fs_visitor::nir_emit_loop(nir_loop
*loop
)
428 bld
.emit(BRW_OPCODE_DO
);
430 nir_emit_cf_list(&loop
->body
);
432 bld
.emit(BRW_OPCODE_WHILE
);
434 if (devinfo
->gen
< 7)
435 limit_dispatch_width(16, "Non-uniform control flow unsupported "
440 fs_visitor::nir_emit_block(nir_block
*block
)
442 nir_foreach_instr(instr
, block
) {
443 nir_emit_instr(instr
);
448 fs_visitor::nir_emit_instr(nir_instr
*instr
)
450 const fs_builder abld
= bld
.annotate(NULL
, instr
);
452 switch (instr
->type
) {
453 case nir_instr_type_alu
:
454 nir_emit_alu(abld
, nir_instr_as_alu(instr
), true);
457 case nir_instr_type_deref
:
458 unreachable("All derefs should've been lowered");
461 case nir_instr_type_intrinsic
:
463 case MESA_SHADER_VERTEX
:
464 nir_emit_vs_intrinsic(abld
, nir_instr_as_intrinsic(instr
));
466 case MESA_SHADER_TESS_CTRL
:
467 nir_emit_tcs_intrinsic(abld
, nir_instr_as_intrinsic(instr
));
469 case MESA_SHADER_TESS_EVAL
:
470 nir_emit_tes_intrinsic(abld
, nir_instr_as_intrinsic(instr
));
472 case MESA_SHADER_GEOMETRY
:
473 nir_emit_gs_intrinsic(abld
, nir_instr_as_intrinsic(instr
));
475 case MESA_SHADER_FRAGMENT
:
476 nir_emit_fs_intrinsic(abld
, nir_instr_as_intrinsic(instr
));
478 case MESA_SHADER_COMPUTE
:
479 nir_emit_cs_intrinsic(abld
, nir_instr_as_intrinsic(instr
));
482 unreachable("unsupported shader stage");
486 case nir_instr_type_tex
:
487 nir_emit_texture(abld
, nir_instr_as_tex(instr
));
490 case nir_instr_type_load_const
:
491 nir_emit_load_const(abld
, nir_instr_as_load_const(instr
));
494 case nir_instr_type_ssa_undef
:
495 /* We create a new VGRF for undefs on every use (by handling
496 * them in get_nir_src()), rather than for each definition.
497 * This helps register coalescing eliminate MOVs from undef.
501 case nir_instr_type_jump
:
502 nir_emit_jump(abld
, nir_instr_as_jump(instr
));
506 unreachable("unknown instruction type");
511 * Recognizes a parent instruction of nir_op_extract_* and changes the type to
515 fs_visitor::optimize_extract_to_float(nir_alu_instr
*instr
,
516 const fs_reg
&result
)
518 if (!instr
->src
[0].src
.is_ssa
||
519 !instr
->src
[0].src
.ssa
->parent_instr
)
522 if (instr
->src
[0].src
.ssa
->parent_instr
->type
!= nir_instr_type_alu
)
525 nir_alu_instr
*src0
=
526 nir_instr_as_alu(instr
->src
[0].src
.ssa
->parent_instr
);
528 if (src0
->op
!= nir_op_extract_u8
&& src0
->op
!= nir_op_extract_u16
&&
529 src0
->op
!= nir_op_extract_i8
&& src0
->op
!= nir_op_extract_i16
)
532 /* If either opcode has source modifiers, bail.
534 * TODO: We can potentially handle source modifiers if both of the opcodes
535 * we're combining are signed integers.
537 if (instr
->src
[0].abs
|| instr
->src
[0].negate
||
538 src0
->src
[0].abs
|| src0
->src
[0].negate
)
541 unsigned element
= nir_src_as_uint(src0
->src
[1].src
);
543 /* Element type to extract.*/
544 const brw_reg_type type
= brw_int_type(
545 src0
->op
== nir_op_extract_u16
|| src0
->op
== nir_op_extract_i16
? 2 : 1,
546 src0
->op
== nir_op_extract_i16
|| src0
->op
== nir_op_extract_i8
);
548 fs_reg op0
= get_nir_src(src0
->src
[0].src
);
549 op0
.type
= brw_type_for_nir_type(devinfo
,
550 (nir_alu_type
)(nir_op_infos
[src0
->op
].input_types
[0] |
551 nir_src_bit_size(src0
->src
[0].src
)));
552 op0
= offset(op0
, bld
, src0
->src
[0].swizzle
[0]);
554 set_saturate(instr
->dest
.saturate
,
555 bld
.MOV(result
, subscript(op0
, type
, element
)));
560 fs_visitor::optimize_frontfacing_ternary(nir_alu_instr
*instr
,
561 const fs_reg
&result
)
563 nir_intrinsic_instr
*src0
= nir_src_as_intrinsic(instr
->src
[0].src
);
564 if (src0
== NULL
|| src0
->intrinsic
!= nir_intrinsic_load_front_face
)
567 if (!nir_src_is_const(instr
->src
[1].src
) ||
568 !nir_src_is_const(instr
->src
[2].src
))
571 const float value1
= nir_src_as_float(instr
->src
[1].src
);
572 const float value2
= nir_src_as_float(instr
->src
[2].src
);
573 if (fabsf(value1
) != 1.0f
|| fabsf(value2
) != 1.0f
)
576 /* nir_opt_algebraic should have gotten rid of bcsel(b, a, a) */
577 assert(value1
== -value2
);
579 fs_reg tmp
= vgrf(glsl_type::int_type
);
581 if (devinfo
->gen
>= 6) {
582 /* Bit 15 of g0.0 is 0 if the polygon is front facing. */
583 fs_reg g0
= fs_reg(retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_W
));
585 /* For (gl_FrontFacing ? 1.0 : -1.0), emit:
587 * or(8) tmp.1<2>W g0.0<0,1,0>W 0x00003f80W
588 * and(8) dst<1>D tmp<8,8,1>D 0xbf800000D
590 * and negate g0.0<0,1,0>W for (gl_FrontFacing ? -1.0 : 1.0).
592 * This negation looks like it's safe in practice, because bits 0:4 will
593 * surely be TRIANGLES
596 if (value1
== -1.0f
) {
600 bld
.OR(subscript(tmp
, BRW_REGISTER_TYPE_W
, 1),
601 g0
, brw_imm_uw(0x3f80));
603 /* Bit 31 of g1.6 is 0 if the polygon is front facing. */
604 fs_reg g1_6
= fs_reg(retype(brw_vec1_grf(1, 6), BRW_REGISTER_TYPE_D
));
606 /* For (gl_FrontFacing ? 1.0 : -1.0), emit:
608 * or(8) tmp<1>D g1.6<0,1,0>D 0x3f800000D
609 * and(8) dst<1>D tmp<8,8,1>D 0xbf800000D
611 * and negate g1.6<0,1,0>D for (gl_FrontFacing ? -1.0 : 1.0).
613 * This negation looks like it's safe in practice, because bits 0:4 will
614 * surely be TRIANGLES
617 if (value1
== -1.0f
) {
621 bld
.OR(tmp
, g1_6
, brw_imm_d(0x3f800000));
623 bld
.AND(retype(result
, BRW_REGISTER_TYPE_D
), tmp
, brw_imm_d(0xbf800000));
629 emit_find_msb_using_lzd(const fs_builder
&bld
,
630 const fs_reg
&result
,
638 /* LZD of an absolute value source almost always does the right
639 * thing. There are two problem values:
641 * * 0x80000000. Since abs(0x80000000) == 0x80000000, LZD returns
642 * 0. However, findMSB(int(0x80000000)) == 30.
644 * * 0xffffffff. Since abs(0xffffffff) == 1, LZD returns
645 * 31. Section 8.8 (Integer Functions) of the GLSL 4.50 spec says:
647 * For a value of zero or negative one, -1 will be returned.
649 * * Negative powers of two. LZD(abs(-(1<<x))) returns x, but
650 * findMSB(-(1<<x)) should return x-1.
652 * For all negative number cases, including 0x80000000 and
653 * 0xffffffff, the correct value is obtained from LZD if instead of
654 * negating the (already negative) value the logical-not is used. A
655 * conditonal logical-not can be achieved in two instructions.
657 temp
= bld
.vgrf(BRW_REGISTER_TYPE_D
);
659 bld
.ASR(temp
, src
, brw_imm_d(31));
660 bld
.XOR(temp
, temp
, src
);
663 bld
.LZD(retype(result
, BRW_REGISTER_TYPE_UD
),
664 retype(temp
, BRW_REGISTER_TYPE_UD
));
666 /* LZD counts from the MSB side, while GLSL's findMSB() wants the count
667 * from the LSB side. Subtract the result from 31 to convert the MSB
668 * count into an LSB count. If no bits are set, LZD will return 32.
669 * 31-32 = -1, which is exactly what findMSB() is supposed to return.
671 inst
= bld
.ADD(result
, retype(result
, BRW_REGISTER_TYPE_D
), brw_imm_d(31));
672 inst
->src
[0].negate
= true;
676 brw_rnd_mode_from_nir_op (const nir_op op
) {
678 case nir_op_f2f16_rtz
:
679 return BRW_RND_MODE_RTZ
;
680 case nir_op_f2f16_rtne
:
681 return BRW_RND_MODE_RTNE
;
683 unreachable("Operation doesn't support rounding mode");
688 fs_visitor::prepare_alu_destination_and_sources(const fs_builder
&bld
,
689 nir_alu_instr
*instr
,
694 need_dest
? get_nir_dest(instr
->dest
.dest
) : bld
.null_reg_ud();
696 result
.type
= brw_type_for_nir_type(devinfo
,
697 (nir_alu_type
)(nir_op_infos
[instr
->op
].output_type
|
698 nir_dest_bit_size(instr
->dest
.dest
)));
700 for (unsigned i
= 0; i
< nir_op_infos
[instr
->op
].num_inputs
; i
++) {
701 op
[i
] = get_nir_src(instr
->src
[i
].src
);
702 op
[i
].type
= brw_type_for_nir_type(devinfo
,
703 (nir_alu_type
)(nir_op_infos
[instr
->op
].input_types
[i
] |
704 nir_src_bit_size(instr
->src
[i
].src
)));
705 op
[i
].abs
= instr
->src
[i
].abs
;
706 op
[i
].negate
= instr
->src
[i
].negate
;
709 /* Move and vecN instrutions may still be vectored. Return the raw,
710 * vectored source and destination so that fs_visitor::nir_emit_alu can
711 * handle it. Other callers should not have to handle these kinds of
724 /* At this point, we have dealt with any instruction that operates on
725 * more than a single channel. Therefore, we can just adjust the source
726 * and destination registers for that channel and emit the instruction.
728 unsigned channel
= 0;
729 if (nir_op_infos
[instr
->op
].output_size
== 0) {
730 /* Since NIR is doing the scalarizing for us, we should only ever see
731 * vectorized operations with a single channel.
733 assert(util_bitcount(instr
->dest
.write_mask
) == 1);
734 channel
= ffs(instr
->dest
.write_mask
) - 1;
736 result
= offset(result
, bld
, channel
);
739 for (unsigned i
= 0; i
< nir_op_infos
[instr
->op
].num_inputs
; i
++) {
740 assert(nir_op_infos
[instr
->op
].input_sizes
[i
] < 2);
741 op
[i
] = offset(op
[i
], bld
, instr
->src
[i
].swizzle
[channel
]);
748 fs_visitor::resolve_inot_sources(const fs_builder
&bld
, nir_alu_instr
*instr
,
751 for (unsigned i
= 0; i
< 2; i
++) {
752 nir_alu_instr
*inot_instr
= nir_src_as_alu_instr(instr
->src
[i
].src
);
754 if (inot_instr
!= NULL
&& inot_instr
->op
== nir_op_inot
&&
755 !inot_instr
->src
[0].abs
&& !inot_instr
->src
[0].negate
) {
756 /* The source of the inot is now the source of instr. */
757 prepare_alu_destination_and_sources(bld
, inot_instr
, &op
[i
], false);
759 assert(!op
[i
].negate
);
762 op
[i
] = resolve_source_modifiers(op
[i
]);
768 fs_visitor::try_emit_b2fi_of_inot(const fs_builder
&bld
,
770 nir_alu_instr
*instr
)
772 if (devinfo
->gen
< 6 || devinfo
->gen
>= 12)
775 nir_alu_instr
*inot_instr
= nir_src_as_alu_instr(instr
->src
[0].src
);
777 if (inot_instr
== NULL
|| inot_instr
->op
!= nir_op_inot
)
780 /* HF is also possible as a destination on BDW+. For nir_op_b2i, the set
781 * of valid size-changing combinations is a bit more complex.
783 * The source restriction is just because I was lazy about generating the
786 if (nir_dest_bit_size(instr
->dest
.dest
) != 32 ||
787 nir_src_bit_size(inot_instr
->src
[0].src
) != 32)
790 /* b2[fi](inot(a)) maps a=0 => 1, a=-1 => 0. Since a can only be 0 or -1,
791 * this is float(1 + a).
795 prepare_alu_destination_and_sources(bld
, inot_instr
, &op
, false);
797 /* Ignore the saturate modifier, if there is one. The result of the
798 * arithmetic can only be 0 or 1, so the clamping will do nothing anyway.
800 bld
.ADD(result
, op
, brw_imm_d(1));
806 * Emit code for nir_op_fsign possibly fused with a nir_op_fmul
808 * If \c instr is not the \c nir_op_fsign, then \c fsign_src is the index of
809 * the source of \c instr that is a \c nir_op_fsign.
812 fs_visitor::emit_fsign(const fs_builder
&bld
, const nir_alu_instr
*instr
,
813 fs_reg result
, fs_reg
*op
, unsigned fsign_src
)
817 assert(instr
->op
== nir_op_fsign
|| instr
->op
== nir_op_fmul
);
818 assert(fsign_src
< nir_op_infos
[instr
->op
].num_inputs
);
820 if (instr
->op
!= nir_op_fsign
) {
821 const nir_alu_instr
*const fsign_instr
=
822 nir_src_as_alu_instr(instr
->src
[fsign_src
].src
);
824 assert(!fsign_instr
->dest
.saturate
);
826 /* op[fsign_src] has the nominal result of the fsign, and op[1 -
827 * fsign_src] has the other multiply source. This must be rearranged so
828 * that op[0] is the source of the fsign op[1] is the other multiply
834 op
[0] = get_nir_src(fsign_instr
->src
[0].src
);
836 const nir_alu_type t
=
837 (nir_alu_type
)(nir_op_infos
[instr
->op
].input_types
[0] |
838 nir_src_bit_size(fsign_instr
->src
[0].src
));
840 op
[0].type
= brw_type_for_nir_type(devinfo
, t
);
841 op
[0].abs
= fsign_instr
->src
[0].abs
;
842 op
[0].negate
= fsign_instr
->src
[0].negate
;
844 unsigned channel
= 0;
845 if (nir_op_infos
[instr
->op
].output_size
== 0) {
846 /* Since NIR is doing the scalarizing for us, we should only ever see
847 * vectorized operations with a single channel.
849 assert(util_bitcount(instr
->dest
.write_mask
) == 1);
850 channel
= ffs(instr
->dest
.write_mask
) - 1;
853 op
[0] = offset(op
[0], bld
, fsign_instr
->src
[0].swizzle
[channel
]);
855 assert(!instr
->dest
.saturate
);
859 /* Straightforward since the source can be assumed to be either strictly
860 * >= 0 or strictly <= 0 depending on the setting of the negate flag.
862 set_condmod(BRW_CONDITIONAL_NZ
, bld
.MOV(result
, op
[0]));
864 if (instr
->op
== nir_op_fsign
) {
865 inst
= (op
[0].negate
)
866 ? bld
.MOV(result
, brw_imm_f(-1.0f
))
867 : bld
.MOV(result
, brw_imm_f(1.0f
));
869 op
[1].negate
= (op
[0].negate
!= op
[1].negate
);
870 inst
= bld
.MOV(result
, op
[1]);
873 set_predicate(BRW_PREDICATE_NORMAL
, inst
);
874 } else if (type_sz(op
[0].type
) == 2) {
875 /* AND(val, 0x8000) gives the sign bit.
877 * Predicated OR ORs 1.0 (0x3c00) with the sign bit if val is not zero.
879 fs_reg zero
= retype(brw_imm_uw(0), BRW_REGISTER_TYPE_HF
);
880 bld
.CMP(bld
.null_reg_f(), op
[0], zero
, BRW_CONDITIONAL_NZ
);
882 op
[0].type
= BRW_REGISTER_TYPE_UW
;
883 result
.type
= BRW_REGISTER_TYPE_UW
;
884 bld
.AND(result
, op
[0], brw_imm_uw(0x8000u
));
886 if (instr
->op
== nir_op_fsign
)
887 inst
= bld
.OR(result
, result
, brw_imm_uw(0x3c00u
));
889 /* Use XOR here to get the result sign correct. */
890 inst
= bld
.XOR(result
, result
, retype(op
[1], BRW_REGISTER_TYPE_UW
));
893 inst
->predicate
= BRW_PREDICATE_NORMAL
;
894 } else if (type_sz(op
[0].type
) == 4) {
895 /* AND(val, 0x80000000) gives the sign bit.
897 * Predicated OR ORs 1.0 (0x3f800000) with the sign bit if val is not
900 bld
.CMP(bld
.null_reg_f(), op
[0], brw_imm_f(0.0f
), BRW_CONDITIONAL_NZ
);
902 op
[0].type
= BRW_REGISTER_TYPE_UD
;
903 result
.type
= BRW_REGISTER_TYPE_UD
;
904 bld
.AND(result
, op
[0], brw_imm_ud(0x80000000u
));
906 if (instr
->op
== nir_op_fsign
)
907 inst
= bld
.OR(result
, result
, brw_imm_ud(0x3f800000u
));
909 /* Use XOR here to get the result sign correct. */
910 inst
= bld
.XOR(result
, result
, retype(op
[1], BRW_REGISTER_TYPE_UD
));
913 inst
->predicate
= BRW_PREDICATE_NORMAL
;
915 /* For doubles we do the same but we need to consider:
917 * - 2-src instructions can't operate with 64-bit immediates
918 * - The sign is encoded in the high 32-bit of each DF
919 * - We need to produce a DF result.
922 fs_reg zero
= vgrf(glsl_type::double_type
);
923 bld
.MOV(zero
, setup_imm_df(bld
, 0.0));
924 bld
.CMP(bld
.null_reg_df(), op
[0], zero
, BRW_CONDITIONAL_NZ
);
926 bld
.MOV(result
, zero
);
928 fs_reg r
= subscript(result
, BRW_REGISTER_TYPE_UD
, 1);
929 bld
.AND(r
, subscript(op
[0], BRW_REGISTER_TYPE_UD
, 1),
930 brw_imm_ud(0x80000000u
));
932 if (instr
->op
== nir_op_fsign
) {
933 set_predicate(BRW_PREDICATE_NORMAL
,
934 bld
.OR(r
, r
, brw_imm_ud(0x3ff00000u
)));
936 /* This could be done better in some cases. If the scale is an
937 * immediate with the low 32-bits all 0, emitting a separate XOR and
938 * OR would allow an algebraic optimization to remove the OR. There
939 * are currently zero instances of fsign(double(x))*IMM in shader-db
940 * or any test suite, so it is hard to care at this time.
942 fs_reg result_int64
= retype(result
, BRW_REGISTER_TYPE_UQ
);
943 inst
= bld
.XOR(result_int64
, result_int64
,
944 retype(op
[1], BRW_REGISTER_TYPE_UQ
));
950 * Deteremine whether sources of a nir_op_fmul can be fused with a nir_op_fsign
952 * Checks the operands of a \c nir_op_fmul to determine whether or not
953 * \c emit_fsign could fuse the multiplication with the \c sign() calculation.
955 * \param instr The multiplication instruction
957 * \param fsign_src The source of \c instr that may or may not be a
961 can_fuse_fmul_fsign(nir_alu_instr
*instr
, unsigned fsign_src
)
963 assert(instr
->op
== nir_op_fmul
);
965 nir_alu_instr
*const fsign_instr
=
966 nir_src_as_alu_instr(instr
->src
[fsign_src
].src
);
970 * 1. instr->src[fsign_src] must be a nir_op_fsign.
971 * 2. The nir_op_fsign can only be used by this multiplication.
972 * 3. The source that is the nir_op_fsign does not have source modifiers.
973 * \c emit_fsign only examines the source modifiers of the source of the
976 * The nir_op_fsign must also not have the saturate modifier, but steps
977 * have already been taken (in nir_opt_algebraic) to ensure that.
979 return fsign_instr
!= NULL
&& fsign_instr
->op
== nir_op_fsign
&&
980 is_used_once(fsign_instr
) &&
981 !instr
->src
[fsign_src
].abs
&& !instr
->src
[fsign_src
].negate
;
985 fs_visitor::nir_emit_alu(const fs_builder
&bld
, nir_alu_instr
*instr
,
988 struct brw_wm_prog_key
*fs_key
= (struct brw_wm_prog_key
*) this->key
;
992 fs_reg result
= prepare_alu_destination_and_sources(bld
, instr
, op
, need_dest
);
999 fs_reg temp
= result
;
1000 bool need_extra_copy
= false;
1001 for (unsigned i
= 0; i
< nir_op_infos
[instr
->op
].num_inputs
; i
++) {
1002 if (!instr
->src
[i
].src
.is_ssa
&&
1003 instr
->dest
.dest
.reg
.reg
== instr
->src
[i
].src
.reg
.reg
) {
1004 need_extra_copy
= true;
1005 temp
= bld
.vgrf(result
.type
, 4);
1010 for (unsigned i
= 0; i
< 4; i
++) {
1011 if (!(instr
->dest
.write_mask
& (1 << i
)))
1014 if (instr
->op
== nir_op_mov
) {
1015 inst
= bld
.MOV(offset(temp
, bld
, i
),
1016 offset(op
[0], bld
, instr
->src
[0].swizzle
[i
]));
1018 inst
= bld
.MOV(offset(temp
, bld
, i
),
1019 offset(op
[i
], bld
, instr
->src
[i
].swizzle
[0]));
1021 inst
->saturate
= instr
->dest
.saturate
;
1024 /* In this case the source and destination registers were the same,
1025 * so we need to insert an extra set of moves in order to deal with
1028 if (need_extra_copy
) {
1029 for (unsigned i
= 0; i
< 4; i
++) {
1030 if (!(instr
->dest
.write_mask
& (1 << i
)))
1033 bld
.MOV(offset(result
, bld
, i
), offset(temp
, bld
, i
));
1041 if (optimize_extract_to_float(instr
, result
))
1043 inst
= bld
.MOV(result
, op
[0]);
1044 inst
->saturate
= instr
->dest
.saturate
;
1047 case nir_op_f2f16_rtne
:
1048 case nir_op_f2f16_rtz
:
1049 bld
.emit(SHADER_OPCODE_RND_MODE
, bld
.null_reg_ud(),
1050 brw_imm_d(brw_rnd_mode_from_nir_op(instr
->op
)));
1053 /* In theory, it would be better to use BRW_OPCODE_F32TO16. Depending
1054 * on the HW gen, it is a special hw opcode or just a MOV, and
1055 * brw_F32TO16 (at brw_eu_emit) would do the work to chose.
1057 * But if we want to use that opcode, we need to provide support on
1058 * different optimizations and lowerings. As right now HF support is
1059 * only for gen8+, it will be better to use directly the MOV, and use
1060 * BRW_OPCODE_F32TO16 when/if we work for HF support on gen7.
1062 assert(type_sz(op
[0].type
) < 8); /* brw_nir_lower_conversions */
1063 inst
= bld
.MOV(result
, op
[0]);
1064 inst
->saturate
= instr
->dest
.saturate
;
1074 if (try_emit_b2fi_of_inot(bld
, result
, instr
))
1076 op
[0].type
= BRW_REGISTER_TYPE_D
;
1077 op
[0].negate
= !op
[0].negate
;
1101 if (result
.type
== BRW_REGISTER_TYPE_B
||
1102 result
.type
== BRW_REGISTER_TYPE_UB
||
1103 result
.type
== BRW_REGISTER_TYPE_HF
)
1104 assert(type_sz(op
[0].type
) < 8); /* brw_nir_lower_conversions */
1106 if (op
[0].type
== BRW_REGISTER_TYPE_B
||
1107 op
[0].type
== BRW_REGISTER_TYPE_UB
||
1108 op
[0].type
== BRW_REGISTER_TYPE_HF
)
1109 assert(type_sz(result
.type
) < 8); /* brw_nir_lower_conversions */
1111 inst
= bld
.MOV(result
, op
[0]);
1112 inst
->saturate
= instr
->dest
.saturate
;
1116 inst
= bld
.MOV(result
, op
[0]);
1117 inst
->saturate
= true;
1122 op
[0].negate
= true;
1123 inst
= bld
.MOV(result
, op
[0]);
1124 if (instr
->op
== nir_op_fneg
)
1125 inst
->saturate
= instr
->dest
.saturate
;
1130 op
[0].negate
= false;
1132 inst
= bld
.MOV(result
, op
[0]);
1133 if (instr
->op
== nir_op_fabs
)
1134 inst
->saturate
= instr
->dest
.saturate
;
1138 emit_fsign(bld
, instr
, result
, op
, 0);
1142 inst
= bld
.emit(SHADER_OPCODE_RCP
, result
, op
[0]);
1143 inst
->saturate
= instr
->dest
.saturate
;
1147 inst
= bld
.emit(SHADER_OPCODE_EXP2
, result
, op
[0]);
1148 inst
->saturate
= instr
->dest
.saturate
;
1152 inst
= bld
.emit(SHADER_OPCODE_LOG2
, result
, op
[0]);
1153 inst
->saturate
= instr
->dest
.saturate
;
1157 inst
= bld
.emit(SHADER_OPCODE_SIN
, result
, op
[0]);
1158 inst
->saturate
= instr
->dest
.saturate
;
1162 inst
= bld
.emit(SHADER_OPCODE_COS
, result
, op
[0]);
1163 inst
->saturate
= instr
->dest
.saturate
;
1167 if (fs_key
->high_quality_derivatives
) {
1168 inst
= bld
.emit(FS_OPCODE_DDX_FINE
, result
, op
[0]);
1170 inst
= bld
.emit(FS_OPCODE_DDX_COARSE
, result
, op
[0]);
1172 inst
->saturate
= instr
->dest
.saturate
;
1174 case nir_op_fddx_fine
:
1175 inst
= bld
.emit(FS_OPCODE_DDX_FINE
, result
, op
[0]);
1176 inst
->saturate
= instr
->dest
.saturate
;
1178 case nir_op_fddx_coarse
:
1179 inst
= bld
.emit(FS_OPCODE_DDX_COARSE
, result
, op
[0]);
1180 inst
->saturate
= instr
->dest
.saturate
;
1183 if (fs_key
->high_quality_derivatives
) {
1184 inst
= bld
.emit(FS_OPCODE_DDY_FINE
, result
, op
[0]);
1186 inst
= bld
.emit(FS_OPCODE_DDY_COARSE
, result
, op
[0]);
1188 inst
->saturate
= instr
->dest
.saturate
;
1190 case nir_op_fddy_fine
:
1191 inst
= bld
.emit(FS_OPCODE_DDY_FINE
, result
, op
[0]);
1192 inst
->saturate
= instr
->dest
.saturate
;
1194 case nir_op_fddy_coarse
:
1195 inst
= bld
.emit(FS_OPCODE_DDY_COARSE
, result
, op
[0]);
1196 inst
->saturate
= instr
->dest
.saturate
;
1201 inst
= bld
.ADD(result
, op
[0], op
[1]);
1202 inst
->saturate
= instr
->dest
.saturate
;
1205 case nir_op_uadd_sat
:
1206 inst
= bld
.ADD(result
, op
[0], op
[1]);
1207 inst
->saturate
= true;
1211 for (unsigned i
= 0; i
< 2; i
++) {
1212 if (can_fuse_fmul_fsign(instr
, i
)) {
1213 emit_fsign(bld
, instr
, result
, op
, i
);
1218 inst
= bld
.MUL(result
, op
[0], op
[1]);
1219 inst
->saturate
= instr
->dest
.saturate
;
1222 case nir_op_imul_2x32_64
:
1223 case nir_op_umul_2x32_64
:
1224 bld
.MUL(result
, op
[0], op
[1]);
1228 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1229 bld
.MUL(result
, op
[0], op
[1]);
1232 case nir_op_imul_high
:
1233 case nir_op_umul_high
:
1234 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1235 bld
.emit(SHADER_OPCODE_MULH
, result
, op
[0], op
[1]);
1240 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1241 bld
.emit(SHADER_OPCODE_INT_QUOTIENT
, result
, op
[0], op
[1]);
1244 case nir_op_uadd_carry
:
1245 unreachable("Should have been lowered by carry_to_arith().");
1247 case nir_op_usub_borrow
:
1248 unreachable("Should have been lowered by borrow_to_arith().");
1252 /* According to the sign table for INT DIV in the Ivy Bridge PRM, it
1253 * appears that our hardware just does the right thing for signed
1256 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1257 bld
.emit(SHADER_OPCODE_INT_REMAINDER
, result
, op
[0], op
[1]);
1261 /* Get a regular C-style remainder. If a % b == 0, set the predicate. */
1262 bld
.emit(SHADER_OPCODE_INT_REMAINDER
, result
, op
[0], op
[1]);
1264 /* Math instructions don't support conditional mod */
1265 inst
= bld
.MOV(bld
.null_reg_d(), result
);
1266 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
1268 /* Now, we need to determine if signs of the sources are different.
1269 * When we XOR the sources, the top bit is 0 if they are the same and 1
1270 * if they are different. We can then use a conditional modifier to
1271 * turn that into a predicate. This leads us to an XOR.l instruction.
1273 * Technically, according to the PRM, you're not allowed to use .l on a
1274 * XOR instruction. However, emperical experiments and Curro's reading
1275 * of the simulator source both indicate that it's safe.
1277 fs_reg tmp
= bld
.vgrf(BRW_REGISTER_TYPE_D
);
1278 inst
= bld
.XOR(tmp
, op
[0], op
[1]);
1279 inst
->predicate
= BRW_PREDICATE_NORMAL
;
1280 inst
->conditional_mod
= BRW_CONDITIONAL_L
;
1282 /* If the result of the initial remainder operation is non-zero and the
1283 * two sources have different signs, add in a copy of op[1] to get the
1284 * final integer modulus value.
1286 inst
= bld
.ADD(result
, result
, op
[1]);
1287 inst
->predicate
= BRW_PREDICATE_NORMAL
;
1294 case nir_op_fne32
: {
1295 fs_reg dest
= result
;
1297 const uint32_t bit_size
= nir_src_bit_size(instr
->src
[0].src
);
1299 dest
= bld
.vgrf(op
[0].type
, 1);
1301 bld
.CMP(dest
, op
[0], op
[1], brw_cmod_for_nir_comparison(instr
->op
));
1303 if (bit_size
> 32) {
1304 bld
.MOV(result
, subscript(dest
, BRW_REGISTER_TYPE_UD
, 0));
1305 } else if(bit_size
< 32) {
1306 /* When we convert the result to 32-bit we need to be careful and do
1307 * it as a signed conversion to get sign extension (for 32-bit true)
1309 const brw_reg_type src_type
=
1310 brw_reg_type_from_bit_size(bit_size
, BRW_REGISTER_TYPE_D
);
1312 bld
.MOV(retype(result
, BRW_REGISTER_TYPE_D
), retype(dest
, src_type
));
1322 case nir_op_ine32
: {
1323 fs_reg dest
= result
;
1325 /* On Gen11 we have an additional issue being that src1 cannot be a byte
1326 * type. So we convert both operands for the comparison.
1329 temp_op
[0] = bld
.fix_byte_src(op
[0]);
1330 temp_op
[1] = bld
.fix_byte_src(op
[1]);
1332 const uint32_t bit_size
= nir_src_bit_size(instr
->src
[0].src
);
1334 dest
= bld
.vgrf(temp_op
[0].type
, 1);
1336 bld
.CMP(dest
, temp_op
[0], temp_op
[1],
1337 brw_cmod_for_nir_comparison(instr
->op
));
1339 if (bit_size
> 32) {
1340 bld
.MOV(result
, subscript(dest
, BRW_REGISTER_TYPE_UD
, 0));
1341 } else if (bit_size
< 32) {
1342 /* When we convert the result to 32-bit we need to be careful and do
1343 * it as a signed conversion to get sign extension (for 32-bit true)
1345 const brw_reg_type src_type
=
1346 brw_reg_type_from_bit_size(bit_size
, BRW_REGISTER_TYPE_D
);
1348 bld
.MOV(retype(result
, BRW_REGISTER_TYPE_D
), retype(dest
, src_type
));
1354 if (devinfo
->gen
>= 8) {
1355 nir_alu_instr
*inot_src_instr
= nir_src_as_alu_instr(instr
->src
[0].src
);
1357 if (inot_src_instr
!= NULL
&&
1358 (inot_src_instr
->op
== nir_op_ior
||
1359 inot_src_instr
->op
== nir_op_ixor
||
1360 inot_src_instr
->op
== nir_op_iand
) &&
1361 !inot_src_instr
->src
[0].abs
&&
1362 !inot_src_instr
->src
[0].negate
&&
1363 !inot_src_instr
->src
[1].abs
&&
1364 !inot_src_instr
->src
[1].negate
) {
1365 /* The sources of the source logical instruction are now the
1366 * sources of the instruction that will be generated.
1368 prepare_alu_destination_and_sources(bld
, inot_src_instr
, op
, false);
1369 resolve_inot_sources(bld
, inot_src_instr
, op
);
1371 /* Smash all of the sources and destination to be signed. This
1372 * doesn't matter for the operation of the instruction, but cmod
1373 * propagation fails on unsigned sources with negation (due to
1374 * fs_inst::can_do_cmod returning false).
1377 brw_type_for_nir_type(devinfo
,
1378 (nir_alu_type
)(nir_type_int
|
1379 nir_dest_bit_size(instr
->dest
.dest
)));
1381 brw_type_for_nir_type(devinfo
,
1382 (nir_alu_type
)(nir_type_int
|
1383 nir_src_bit_size(inot_src_instr
->src
[0].src
)));
1385 brw_type_for_nir_type(devinfo
,
1386 (nir_alu_type
)(nir_type_int
|
1387 nir_src_bit_size(inot_src_instr
->src
[1].src
)));
1389 /* For XOR, only invert one of the sources. Arbitrarily choose
1392 op
[0].negate
= !op
[0].negate
;
1393 if (inot_src_instr
->op
!= nir_op_ixor
)
1394 op
[1].negate
= !op
[1].negate
;
1396 switch (inot_src_instr
->op
) {
1398 bld
.AND(result
, op
[0], op
[1]);
1402 bld
.OR(result
, op
[0], op
[1]);
1406 bld
.XOR(result
, op
[0], op
[1]);
1410 unreachable("impossible opcode");
1413 op
[0] = resolve_source_modifiers(op
[0]);
1415 bld
.NOT(result
, op
[0]);
1418 if (devinfo
->gen
>= 8) {
1419 resolve_inot_sources(bld
, instr
, op
);
1421 bld
.XOR(result
, op
[0], op
[1]);
1424 if (devinfo
->gen
>= 8) {
1425 resolve_inot_sources(bld
, instr
, op
);
1427 bld
.OR(result
, op
[0], op
[1]);
1430 if (devinfo
->gen
>= 8) {
1431 resolve_inot_sources(bld
, instr
, op
);
1433 bld
.AND(result
, op
[0], op
[1]);
1439 case nir_op_b32all_fequal2
:
1440 case nir_op_b32all_iequal2
:
1441 case nir_op_b32all_fequal3
:
1442 case nir_op_b32all_iequal3
:
1443 case nir_op_b32all_fequal4
:
1444 case nir_op_b32all_iequal4
:
1445 case nir_op_b32any_fnequal2
:
1446 case nir_op_b32any_inequal2
:
1447 case nir_op_b32any_fnequal3
:
1448 case nir_op_b32any_inequal3
:
1449 case nir_op_b32any_fnequal4
:
1450 case nir_op_b32any_inequal4
:
1451 unreachable("Lowered by nir_lower_alu_reductions");
1453 case nir_op_fnoise1_1
:
1454 case nir_op_fnoise1_2
:
1455 case nir_op_fnoise1_3
:
1456 case nir_op_fnoise1_4
:
1457 case nir_op_fnoise2_1
:
1458 case nir_op_fnoise2_2
:
1459 case nir_op_fnoise2_3
:
1460 case nir_op_fnoise2_4
:
1461 case nir_op_fnoise3_1
:
1462 case nir_op_fnoise3_2
:
1463 case nir_op_fnoise3_3
:
1464 case nir_op_fnoise3_4
:
1465 case nir_op_fnoise4_1
:
1466 case nir_op_fnoise4_2
:
1467 case nir_op_fnoise4_3
:
1468 case nir_op_fnoise4_4
:
1469 unreachable("not reached: should be handled by lower_noise");
1472 unreachable("not reached: should be handled by ldexp_to_arith()");
1475 inst
= bld
.emit(SHADER_OPCODE_SQRT
, result
, op
[0]);
1476 inst
->saturate
= instr
->dest
.saturate
;
1480 inst
= bld
.emit(SHADER_OPCODE_RSQ
, result
, op
[0]);
1481 inst
->saturate
= instr
->dest
.saturate
;
1485 case nir_op_f2b32
: {
1486 uint32_t bit_size
= nir_src_bit_size(instr
->src
[0].src
);
1487 if (bit_size
== 64) {
1488 /* two-argument instructions can't take 64-bit immediates */
1492 if (instr
->op
== nir_op_f2b32
) {
1493 zero
= vgrf(glsl_type::double_type
);
1494 tmp
= vgrf(glsl_type::double_type
);
1495 bld
.MOV(zero
, setup_imm_df(bld
, 0.0));
1497 zero
= vgrf(glsl_type::int64_t_type
);
1498 tmp
= vgrf(glsl_type::int64_t_type
);
1499 bld
.MOV(zero
, brw_imm_q(0));
1502 /* A SIMD16 execution needs to be split in two instructions, so use
1503 * a vgrf instead of the flag register as dst so instruction splitting
1506 bld
.CMP(tmp
, op
[0], zero
, BRW_CONDITIONAL_NZ
);
1507 bld
.MOV(result
, subscript(tmp
, BRW_REGISTER_TYPE_UD
, 0));
1510 if (bit_size
== 32) {
1511 zero
= instr
->op
== nir_op_f2b32
? brw_imm_f(0.0f
) : brw_imm_d(0);
1513 assert(bit_size
== 16);
1514 zero
= instr
->op
== nir_op_f2b32
?
1515 retype(brw_imm_w(0), BRW_REGISTER_TYPE_HF
) : brw_imm_w(0);
1517 bld
.CMP(result
, op
[0], zero
, BRW_CONDITIONAL_NZ
);
1523 inst
= bld
.RNDZ(result
, op
[0]);
1524 inst
->saturate
= instr
->dest
.saturate
;
1527 case nir_op_fceil
: {
1528 op
[0].negate
= !op
[0].negate
;
1529 fs_reg temp
= vgrf(glsl_type::float_type
);
1530 bld
.RNDD(temp
, op
[0]);
1532 inst
= bld
.MOV(result
, temp
);
1533 inst
->saturate
= instr
->dest
.saturate
;
1537 inst
= bld
.RNDD(result
, op
[0]);
1538 inst
->saturate
= instr
->dest
.saturate
;
1541 inst
= bld
.FRC(result
, op
[0]);
1542 inst
->saturate
= instr
->dest
.saturate
;
1544 case nir_op_fround_even
:
1545 inst
= bld
.RNDE(result
, op
[0]);
1546 inst
->saturate
= instr
->dest
.saturate
;
1549 case nir_op_fquantize2f16
: {
1550 fs_reg tmp16
= bld
.vgrf(BRW_REGISTER_TYPE_D
);
1551 fs_reg tmp32
= bld
.vgrf(BRW_REGISTER_TYPE_F
);
1552 fs_reg zero
= bld
.vgrf(BRW_REGISTER_TYPE_F
);
1554 /* The destination stride must be at least as big as the source stride. */
1555 tmp16
.type
= BRW_REGISTER_TYPE_W
;
1558 /* Check for denormal */
1559 fs_reg abs_src0
= op
[0];
1560 abs_src0
.abs
= true;
1561 bld
.CMP(bld
.null_reg_f(), abs_src0
, brw_imm_f(ldexpf(1.0, -14)),
1563 /* Get the appropriately signed zero */
1564 bld
.AND(retype(zero
, BRW_REGISTER_TYPE_UD
),
1565 retype(op
[0], BRW_REGISTER_TYPE_UD
),
1566 brw_imm_ud(0x80000000));
1567 /* Do the actual F32 -> F16 -> F32 conversion */
1568 bld
.emit(BRW_OPCODE_F32TO16
, tmp16
, op
[0]);
1569 bld
.emit(BRW_OPCODE_F16TO32
, tmp32
, tmp16
);
1570 /* Select that or zero based on normal status */
1571 inst
= bld
.SEL(result
, zero
, tmp32
);
1572 inst
->predicate
= BRW_PREDICATE_NORMAL
;
1573 inst
->saturate
= instr
->dest
.saturate
;
1580 inst
= bld
.emit_minmax(result
, op
[0], op
[1], BRW_CONDITIONAL_L
);
1581 inst
->saturate
= instr
->dest
.saturate
;
1587 inst
= bld
.emit_minmax(result
, op
[0], op
[1], BRW_CONDITIONAL_GE
);
1588 inst
->saturate
= instr
->dest
.saturate
;
1591 case nir_op_pack_snorm_2x16
:
1592 case nir_op_pack_snorm_4x8
:
1593 case nir_op_pack_unorm_2x16
:
1594 case nir_op_pack_unorm_4x8
:
1595 case nir_op_unpack_snorm_2x16
:
1596 case nir_op_unpack_snorm_4x8
:
1597 case nir_op_unpack_unorm_2x16
:
1598 case nir_op_unpack_unorm_4x8
:
1599 case nir_op_unpack_half_2x16
:
1600 case nir_op_pack_half_2x16
:
1601 unreachable("not reached: should be handled by lower_packing_builtins");
1603 case nir_op_unpack_half_2x16_split_x_flush_to_zero
:
1604 assert(FLOAT_CONTROLS_DENORM_FLUSH_TO_ZERO_FP16
& execution_mode
);
1605 case nir_op_unpack_half_2x16_split_x
:
1606 inst
= bld
.emit(BRW_OPCODE_F16TO32
, result
,
1607 subscript(op
[0], BRW_REGISTER_TYPE_UW
, 0));
1608 inst
->saturate
= instr
->dest
.saturate
;
1610 case nir_op_unpack_half_2x16_split_y_flush_to_zero
:
1611 assert(FLOAT_CONTROLS_DENORM_FLUSH_TO_ZERO_FP16
& execution_mode
);
1612 case nir_op_unpack_half_2x16_split_y
:
1613 inst
= bld
.emit(BRW_OPCODE_F16TO32
, result
,
1614 subscript(op
[0], BRW_REGISTER_TYPE_UW
, 1));
1615 inst
->saturate
= instr
->dest
.saturate
;
1618 case nir_op_pack_64_2x32_split
:
1619 case nir_op_pack_32_2x16_split
:
1620 bld
.emit(FS_OPCODE_PACK
, result
, op
[0], op
[1]);
1623 case nir_op_unpack_64_2x32_split_x
:
1624 case nir_op_unpack_64_2x32_split_y
: {
1625 if (instr
->op
== nir_op_unpack_64_2x32_split_x
)
1626 bld
.MOV(result
, subscript(op
[0], BRW_REGISTER_TYPE_UD
, 0));
1628 bld
.MOV(result
, subscript(op
[0], BRW_REGISTER_TYPE_UD
, 1));
1632 case nir_op_unpack_32_2x16_split_x
:
1633 case nir_op_unpack_32_2x16_split_y
: {
1634 if (instr
->op
== nir_op_unpack_32_2x16_split_x
)
1635 bld
.MOV(result
, subscript(op
[0], BRW_REGISTER_TYPE_UW
, 0));
1637 bld
.MOV(result
, subscript(op
[0], BRW_REGISTER_TYPE_UW
, 1));
1642 inst
= bld
.emit(SHADER_OPCODE_POW
, result
, op
[0], op
[1]);
1643 inst
->saturate
= instr
->dest
.saturate
;
1646 case nir_op_bitfield_reverse
:
1647 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1648 bld
.BFREV(result
, op
[0]);
1651 case nir_op_bit_count
:
1652 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1653 bld
.CBIT(result
, op
[0]);
1656 case nir_op_ufind_msb
: {
1657 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1658 emit_find_msb_using_lzd(bld
, result
, op
[0], false);
1662 case nir_op_ifind_msb
: {
1663 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1665 if (devinfo
->gen
< 7) {
1666 emit_find_msb_using_lzd(bld
, result
, op
[0], true);
1668 bld
.FBH(retype(result
, BRW_REGISTER_TYPE_UD
), op
[0]);
1670 /* FBH counts from the MSB side, while GLSL's findMSB() wants the
1671 * count from the LSB side. If FBH didn't return an error
1672 * (0xFFFFFFFF), then subtract the result from 31 to convert the MSB
1673 * count into an LSB count.
1675 bld
.CMP(bld
.null_reg_d(), result
, brw_imm_d(-1), BRW_CONDITIONAL_NZ
);
1677 inst
= bld
.ADD(result
, result
, brw_imm_d(31));
1678 inst
->predicate
= BRW_PREDICATE_NORMAL
;
1679 inst
->src
[0].negate
= true;
1684 case nir_op_find_lsb
:
1685 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1687 if (devinfo
->gen
< 7) {
1688 fs_reg temp
= vgrf(glsl_type::int_type
);
1690 /* (x & -x) generates a value that consists of only the LSB of x.
1691 * For all powers of 2, findMSB(y) == findLSB(y).
1693 fs_reg src
= retype(op
[0], BRW_REGISTER_TYPE_D
);
1694 fs_reg negated_src
= src
;
1696 /* One must be negated, and the other must be non-negated. It
1697 * doesn't matter which is which.
1699 negated_src
.negate
= true;
1702 bld
.AND(temp
, src
, negated_src
);
1703 emit_find_msb_using_lzd(bld
, result
, temp
, false);
1705 bld
.FBL(result
, op
[0]);
1709 case nir_op_ubitfield_extract
:
1710 case nir_op_ibitfield_extract
:
1711 unreachable("should have been lowered");
1714 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1715 bld
.BFE(result
, op
[2], op
[1], op
[0]);
1718 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1719 bld
.BFI1(result
, op
[0], op
[1]);
1722 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1723 bld
.BFI2(result
, op
[0], op
[1], op
[2]);
1726 case nir_op_bitfield_insert
:
1727 unreachable("not reached: should have been lowered");
1730 bld
.SHL(result
, op
[0], op
[1]);
1733 bld
.ASR(result
, op
[0], op
[1]);
1736 bld
.SHR(result
, op
[0], op
[1]);
1740 bld
.ROL(result
, op
[0], op
[1]);
1743 bld
.ROR(result
, op
[0], op
[1]);
1746 case nir_op_pack_half_2x16_split
:
1747 bld
.emit(FS_OPCODE_PACK_HALF_2x16_SPLIT
, result
, op
[0], op
[1]);
1751 inst
= bld
.MAD(result
, op
[2], op
[1], op
[0]);
1752 inst
->saturate
= instr
->dest
.saturate
;
1756 inst
= bld
.LRP(result
, op
[0], op
[1], op
[2]);
1757 inst
->saturate
= instr
->dest
.saturate
;
1760 case nir_op_b32csel
:
1761 if (optimize_frontfacing_ternary(instr
, result
))
1764 bld
.CMP(bld
.null_reg_d(), op
[0], brw_imm_d(0), BRW_CONDITIONAL_NZ
);
1765 inst
= bld
.SEL(result
, op
[1], op
[2]);
1766 inst
->predicate
= BRW_PREDICATE_NORMAL
;
1769 case nir_op_extract_u8
:
1770 case nir_op_extract_i8
: {
1771 unsigned byte
= nir_src_as_uint(instr
->src
[1].src
);
1776 * There is no direct conversion from B/UB to Q/UQ or Q/UQ to B/UB.
1777 * Use two instructions and a word or DWord intermediate integer type.
1779 if (nir_dest_bit_size(instr
->dest
.dest
) == 64) {
1780 const brw_reg_type type
= brw_int_type(1, instr
->op
== nir_op_extract_i8
);
1782 if (instr
->op
== nir_op_extract_i8
) {
1783 /* If we need to sign extend, extract to a word first */
1784 fs_reg w_temp
= bld
.vgrf(BRW_REGISTER_TYPE_W
);
1785 bld
.MOV(w_temp
, subscript(op
[0], type
, byte
));
1786 bld
.MOV(result
, w_temp
);
1787 } else if (byte
& 1) {
1788 /* Extract the high byte from the word containing the desired byte
1792 subscript(op
[0], BRW_REGISTER_TYPE_UW
, byte
/ 2),
1795 /* Otherwise use an AND with 0xff and a word type */
1797 subscript(op
[0], BRW_REGISTER_TYPE_UW
, byte
/ 2),
1801 const brw_reg_type type
= brw_int_type(1, instr
->op
== nir_op_extract_i8
);
1802 bld
.MOV(result
, subscript(op
[0], type
, byte
));
1807 case nir_op_extract_u16
:
1808 case nir_op_extract_i16
: {
1809 const brw_reg_type type
= brw_int_type(2, instr
->op
== nir_op_extract_i16
);
1810 unsigned word
= nir_src_as_uint(instr
->src
[1].src
);
1811 bld
.MOV(result
, subscript(op
[0], type
, word
));
1816 unreachable("unhandled instruction");
1819 /* If we need to do a boolean resolve, replace the result with -(x & 1)
1820 * to sign extend the low bit to 0/~0
1822 if (devinfo
->gen
<= 5 &&
1823 !result
.is_null() &&
1824 (instr
->instr
.pass_flags
& BRW_NIR_BOOLEAN_MASK
) == BRW_NIR_BOOLEAN_NEEDS_RESOLVE
) {
1825 fs_reg masked
= vgrf(glsl_type::int_type
);
1826 bld
.AND(masked
, result
, brw_imm_d(1));
1827 masked
.negate
= true;
1828 bld
.MOV(retype(result
, BRW_REGISTER_TYPE_D
), masked
);
1833 fs_visitor::nir_emit_load_const(const fs_builder
&bld
,
1834 nir_load_const_instr
*instr
)
1836 const brw_reg_type reg_type
=
1837 brw_reg_type_from_bit_size(instr
->def
.bit_size
, BRW_REGISTER_TYPE_D
);
1838 fs_reg reg
= bld
.vgrf(reg_type
, instr
->def
.num_components
);
1840 switch (instr
->def
.bit_size
) {
1842 for (unsigned i
= 0; i
< instr
->def
.num_components
; i
++)
1843 bld
.MOV(offset(reg
, bld
, i
), setup_imm_b(bld
, instr
->value
[i
].i8
));
1847 for (unsigned i
= 0; i
< instr
->def
.num_components
; i
++)
1848 bld
.MOV(offset(reg
, bld
, i
), brw_imm_w(instr
->value
[i
].i16
));
1852 for (unsigned i
= 0; i
< instr
->def
.num_components
; i
++)
1853 bld
.MOV(offset(reg
, bld
, i
), brw_imm_d(instr
->value
[i
].i32
));
1857 assert(devinfo
->gen
>= 7);
1858 if (devinfo
->gen
== 7) {
1859 /* We don't get 64-bit integer types until gen8 */
1860 for (unsigned i
= 0; i
< instr
->def
.num_components
; i
++) {
1861 bld
.MOV(retype(offset(reg
, bld
, i
), BRW_REGISTER_TYPE_DF
),
1862 setup_imm_df(bld
, instr
->value
[i
].f64
));
1865 for (unsigned i
= 0; i
< instr
->def
.num_components
; i
++)
1866 bld
.MOV(offset(reg
, bld
, i
), brw_imm_q(instr
->value
[i
].i64
));
1871 unreachable("Invalid bit size");
1874 nir_ssa_values
[instr
->def
.index
] = reg
;
1878 fs_visitor::get_nir_src(const nir_src
&src
)
1882 if (src
.ssa
->parent_instr
->type
== nir_instr_type_ssa_undef
) {
1883 const brw_reg_type reg_type
=
1884 brw_reg_type_from_bit_size(src
.ssa
->bit_size
, BRW_REGISTER_TYPE_D
);
1885 reg
= bld
.vgrf(reg_type
, src
.ssa
->num_components
);
1887 reg
= nir_ssa_values
[src
.ssa
->index
];
1890 /* We don't handle indirects on locals */
1891 assert(src
.reg
.indirect
== NULL
);
1892 reg
= offset(nir_locals
[src
.reg
.reg
->index
], bld
,
1893 src
.reg
.base_offset
* src
.reg
.reg
->num_components
);
1896 if (nir_src_bit_size(src
) == 64 && devinfo
->gen
== 7) {
1897 /* The only 64-bit type available on gen7 is DF, so use that. */
1898 reg
.type
= BRW_REGISTER_TYPE_DF
;
1900 /* To avoid floating-point denorm flushing problems, set the type by
1901 * default to an integer type - instructions that need floating point
1902 * semantics will set this to F if they need to
1904 reg
.type
= brw_reg_type_from_bit_size(nir_src_bit_size(src
),
1905 BRW_REGISTER_TYPE_D
);
1912 * Return an IMM for constants; otherwise call get_nir_src() as normal.
1914 * This function should not be called on any value which may be 64 bits.
1915 * We could theoretically support 64-bit on gen8+ but we choose not to
1916 * because it wouldn't work in general (no gen7 support) and there are
1917 * enough restrictions in 64-bit immediates that you can't take the return
1918 * value and treat it the same as the result of get_nir_src().
1921 fs_visitor::get_nir_src_imm(const nir_src
&src
)
1923 assert(nir_src_bit_size(src
) == 32);
1924 return nir_src_is_const(src
) ?
1925 fs_reg(brw_imm_d(nir_src_as_int(src
))) : get_nir_src(src
);
1929 fs_visitor::get_nir_dest(const nir_dest
&dest
)
1932 const brw_reg_type reg_type
=
1933 brw_reg_type_from_bit_size(dest
.ssa
.bit_size
,
1934 dest
.ssa
.bit_size
== 8 ?
1935 BRW_REGISTER_TYPE_D
:
1936 BRW_REGISTER_TYPE_F
);
1937 nir_ssa_values
[dest
.ssa
.index
] =
1938 bld
.vgrf(reg_type
, dest
.ssa
.num_components
);
1939 bld
.UNDEF(nir_ssa_values
[dest
.ssa
.index
]);
1940 return nir_ssa_values
[dest
.ssa
.index
];
1942 /* We don't handle indirects on locals */
1943 assert(dest
.reg
.indirect
== NULL
);
1944 return offset(nir_locals
[dest
.reg
.reg
->index
], bld
,
1945 dest
.reg
.base_offset
* dest
.reg
.reg
->num_components
);
1950 fs_visitor::emit_percomp(const fs_builder
&bld
, const fs_inst
&inst
,
1953 for (unsigned i
= 0; i
< 4; i
++) {
1954 if (!((wr_mask
>> i
) & 1))
1957 fs_inst
*new_inst
= new(mem_ctx
) fs_inst(inst
);
1958 new_inst
->dst
= offset(new_inst
->dst
, bld
, i
);
1959 for (unsigned j
= 0; j
< new_inst
->sources
; j
++)
1960 if (new_inst
->src
[j
].file
== VGRF
)
1961 new_inst
->src
[j
] = offset(new_inst
->src
[j
], bld
, i
);
1968 emit_pixel_interpolater_send(const fs_builder
&bld
,
1973 glsl_interp_mode interpolation
)
1975 struct brw_wm_prog_data
*wm_prog_data
=
1976 brw_wm_prog_data(bld
.shader
->stage_prog_data
);
1978 fs_inst
*inst
= bld
.emit(opcode
, dst
, src
, desc
);
1979 /* 2 floats per slot returned */
1980 inst
->size_written
= 2 * dst
.component_size(inst
->exec_size
);
1981 inst
->pi_noperspective
= interpolation
== INTERP_MODE_NOPERSPECTIVE
;
1983 wm_prog_data
->pulls_bary
= true;
1989 * Computes 1 << x, given a D/UD register containing some value x.
1992 intexp2(const fs_builder
&bld
, const fs_reg
&x
)
1994 assert(x
.type
== BRW_REGISTER_TYPE_UD
|| x
.type
== BRW_REGISTER_TYPE_D
);
1996 fs_reg result
= bld
.vgrf(x
.type
, 1);
1997 fs_reg one
= bld
.vgrf(x
.type
, 1);
1999 bld
.MOV(one
, retype(brw_imm_d(1), one
.type
));
2000 bld
.SHL(result
, one
, x
);
2005 fs_visitor::emit_gs_end_primitive(const nir_src
&vertex_count_nir_src
)
2007 assert(stage
== MESA_SHADER_GEOMETRY
);
2009 struct brw_gs_prog_data
*gs_prog_data
= brw_gs_prog_data(prog_data
);
2011 if (gs_compile
->control_data_header_size_bits
== 0)
2014 /* We can only do EndPrimitive() functionality when the control data
2015 * consists of cut bits. Fortunately, the only time it isn't is when the
2016 * output type is points, in which case EndPrimitive() is a no-op.
2018 if (gs_prog_data
->control_data_format
!=
2019 GEN7_GS_CONTROL_DATA_FORMAT_GSCTL_CUT
) {
2023 /* Cut bits use one bit per vertex. */
2024 assert(gs_compile
->control_data_bits_per_vertex
== 1);
2026 fs_reg vertex_count
= get_nir_src(vertex_count_nir_src
);
2027 vertex_count
.type
= BRW_REGISTER_TYPE_UD
;
2029 /* Cut bit n should be set to 1 if EndPrimitive() was called after emitting
2030 * vertex n, 0 otherwise. So all we need to do here is mark bit
2031 * (vertex_count - 1) % 32 in the cut_bits register to indicate that
2032 * EndPrimitive() was called after emitting vertex (vertex_count - 1);
2033 * vec4_gs_visitor::emit_control_data_bits() will take care of the rest.
2035 * Note that if EndPrimitive() is called before emitting any vertices, this
2036 * will cause us to set bit 31 of the control_data_bits register to 1.
2037 * That's fine because:
2039 * - If max_vertices < 32, then vertex number 31 (zero-based) will never be
2040 * output, so the hardware will ignore cut bit 31.
2042 * - If max_vertices == 32, then vertex number 31 is guaranteed to be the
2043 * last vertex, so setting cut bit 31 has no effect (since the primitive
2044 * is automatically ended when the GS terminates).
2046 * - If max_vertices > 32, then the ir_emit_vertex visitor will reset the
2047 * control_data_bits register to 0 when the first vertex is emitted.
2050 const fs_builder abld
= bld
.annotate("end primitive");
2052 /* control_data_bits |= 1 << ((vertex_count - 1) % 32) */
2053 fs_reg prev_count
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2054 abld
.ADD(prev_count
, vertex_count
, brw_imm_ud(0xffffffffu
));
2055 fs_reg mask
= intexp2(abld
, prev_count
);
2056 /* Note: we're relying on the fact that the GEN SHL instruction only pays
2057 * attention to the lower 5 bits of its second source argument, so on this
2058 * architecture, 1 << (vertex_count - 1) is equivalent to 1 <<
2059 * ((vertex_count - 1) % 32).
2061 abld
.OR(this->control_data_bits
, this->control_data_bits
, mask
);
2065 fs_visitor::emit_gs_control_data_bits(const fs_reg
&vertex_count
)
2067 assert(stage
== MESA_SHADER_GEOMETRY
);
2068 assert(gs_compile
->control_data_bits_per_vertex
!= 0);
2070 struct brw_gs_prog_data
*gs_prog_data
= brw_gs_prog_data(prog_data
);
2072 const fs_builder abld
= bld
.annotate("emit control data bits");
2073 const fs_builder fwa_bld
= bld
.exec_all();
2075 /* We use a single UD register to accumulate control data bits (32 bits
2076 * for each of the SIMD8 channels). So we need to write a DWord (32 bits)
2079 * Unfortunately, the URB_WRITE_SIMD8 message uses 128-bit (OWord) offsets.
2080 * We have select a 128-bit group via the Global and Per-Slot Offsets, then
2081 * use the Channel Mask phase to enable/disable which DWord within that
2082 * group to write. (Remember, different SIMD8 channels may have emitted
2083 * different numbers of vertices, so we may need per-slot offsets.)
2085 * Channel masking presents an annoying problem: we may have to replicate
2086 * the data up to 4 times:
2088 * Msg = Handles, Per-Slot Offsets, Channel Masks, Data, Data, Data, Data.
2090 * To avoid penalizing shaders that emit a small number of vertices, we
2091 * can avoid these sometimes: if the size of the control data header is
2092 * <= 128 bits, then there is only 1 OWord. All SIMD8 channels will land
2093 * land in the same 128-bit group, so we can skip per-slot offsets.
2095 * Similarly, if the control data header is <= 32 bits, there is only one
2096 * DWord, so we can skip channel masks.
2098 enum opcode opcode
= SHADER_OPCODE_URB_WRITE_SIMD8
;
2100 fs_reg channel_mask
, per_slot_offset
;
2102 if (gs_compile
->control_data_header_size_bits
> 32) {
2103 opcode
= SHADER_OPCODE_URB_WRITE_SIMD8_MASKED
;
2104 channel_mask
= vgrf(glsl_type::uint_type
);
2107 if (gs_compile
->control_data_header_size_bits
> 128) {
2108 opcode
= SHADER_OPCODE_URB_WRITE_SIMD8_MASKED_PER_SLOT
;
2109 per_slot_offset
= vgrf(glsl_type::uint_type
);
2112 /* Figure out which DWord we're trying to write to using the formula:
2114 * dword_index = (vertex_count - 1) * bits_per_vertex / 32
2116 * Since bits_per_vertex is a power of two, and is known at compile
2117 * time, this can be optimized to:
2119 * dword_index = (vertex_count - 1) >> (6 - log2(bits_per_vertex))
2121 if (opcode
!= SHADER_OPCODE_URB_WRITE_SIMD8
) {
2122 fs_reg dword_index
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2123 fs_reg prev_count
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2124 abld
.ADD(prev_count
, vertex_count
, brw_imm_ud(0xffffffffu
));
2125 unsigned log2_bits_per_vertex
=
2126 util_last_bit(gs_compile
->control_data_bits_per_vertex
);
2127 abld
.SHR(dword_index
, prev_count
, brw_imm_ud(6u - log2_bits_per_vertex
));
2129 if (per_slot_offset
.file
!= BAD_FILE
) {
2130 /* Set the per-slot offset to dword_index / 4, so that we'll write to
2131 * the appropriate OWord within the control data header.
2133 abld
.SHR(per_slot_offset
, dword_index
, brw_imm_ud(2u));
2136 /* Set the channel masks to 1 << (dword_index % 4), so that we'll
2137 * write to the appropriate DWORD within the OWORD.
2139 fs_reg channel
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2140 fwa_bld
.AND(channel
, dword_index
, brw_imm_ud(3u));
2141 channel_mask
= intexp2(fwa_bld
, channel
);
2142 /* Then the channel masks need to be in bits 23:16. */
2143 fwa_bld
.SHL(channel_mask
, channel_mask
, brw_imm_ud(16u));
2146 /* Store the control data bits in the message payload and send it. */
2148 if (channel_mask
.file
!= BAD_FILE
)
2149 mlen
+= 4; /* channel masks, plus 3 extra copies of the data */
2150 if (per_slot_offset
.file
!= BAD_FILE
)
2153 fs_reg payload
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, mlen
);
2154 fs_reg
*sources
= ralloc_array(mem_ctx
, fs_reg
, mlen
);
2156 sources
[i
++] = fs_reg(retype(brw_vec8_grf(1, 0), BRW_REGISTER_TYPE_UD
));
2157 if (per_slot_offset
.file
!= BAD_FILE
)
2158 sources
[i
++] = per_slot_offset
;
2159 if (channel_mask
.file
!= BAD_FILE
)
2160 sources
[i
++] = channel_mask
;
2162 sources
[i
++] = this->control_data_bits
;
2165 abld
.LOAD_PAYLOAD(payload
, sources
, mlen
, mlen
);
2166 fs_inst
*inst
= abld
.emit(opcode
, reg_undef
, payload
);
2168 /* We need to increment Global Offset by 256-bits to make room for
2169 * Broadwell's extra "Vertex Count" payload at the beginning of the
2170 * URB entry. Since this is an OWord message, Global Offset is counted
2171 * in 128-bit units, so we must set it to 2.
2173 if (gs_prog_data
->static_vertex_count
== -1)
2178 fs_visitor::set_gs_stream_control_data_bits(const fs_reg
&vertex_count
,
2181 /* control_data_bits |= stream_id << ((2 * (vertex_count - 1)) % 32) */
2183 /* Note: we are calling this *before* increasing vertex_count, so
2184 * this->vertex_count == vertex_count - 1 in the formula above.
2187 /* Stream mode uses 2 bits per vertex */
2188 assert(gs_compile
->control_data_bits_per_vertex
== 2);
2190 /* Must be a valid stream */
2191 assert(stream_id
< MAX_VERTEX_STREAMS
);
2193 /* Control data bits are initialized to 0 so we don't have to set any
2194 * bits when sending vertices to stream 0.
2199 const fs_builder abld
= bld
.annotate("set stream control data bits", NULL
);
2201 /* reg::sid = stream_id */
2202 fs_reg sid
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2203 abld
.MOV(sid
, brw_imm_ud(stream_id
));
2205 /* reg:shift_count = 2 * (vertex_count - 1) */
2206 fs_reg shift_count
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2207 abld
.SHL(shift_count
, vertex_count
, brw_imm_ud(1u));
2209 /* Note: we're relying on the fact that the GEN SHL instruction only pays
2210 * attention to the lower 5 bits of its second source argument, so on this
2211 * architecture, stream_id << 2 * (vertex_count - 1) is equivalent to
2212 * stream_id << ((2 * (vertex_count - 1)) % 32).
2214 fs_reg mask
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2215 abld
.SHL(mask
, sid
, shift_count
);
2216 abld
.OR(this->control_data_bits
, this->control_data_bits
, mask
);
2220 fs_visitor::emit_gs_vertex(const nir_src
&vertex_count_nir_src
,
2223 assert(stage
== MESA_SHADER_GEOMETRY
);
2225 struct brw_gs_prog_data
*gs_prog_data
= brw_gs_prog_data(prog_data
);
2227 fs_reg vertex_count
= get_nir_src(vertex_count_nir_src
);
2228 vertex_count
.type
= BRW_REGISTER_TYPE_UD
;
2230 /* Haswell and later hardware ignores the "Render Stream Select" bits
2231 * from the 3DSTATE_STREAMOUT packet when the SOL stage is disabled,
2232 * and instead sends all primitives down the pipeline for rasterization.
2233 * If the SOL stage is enabled, "Render Stream Select" is honored and
2234 * primitives bound to non-zero streams are discarded after stream output.
2236 * Since the only purpose of primives sent to non-zero streams is to
2237 * be recorded by transform feedback, we can simply discard all geometry
2238 * bound to these streams when transform feedback is disabled.
2240 if (stream_id
> 0 && !nir
->info
.has_transform_feedback_varyings
)
2243 /* If we're outputting 32 control data bits or less, then we can wait
2244 * until the shader is over to output them all. Otherwise we need to
2245 * output them as we go. Now is the time to do it, since we're about to
2246 * output the vertex_count'th vertex, so it's guaranteed that the
2247 * control data bits associated with the (vertex_count - 1)th vertex are
2250 if (gs_compile
->control_data_header_size_bits
> 32) {
2251 const fs_builder abld
=
2252 bld
.annotate("emit vertex: emit control data bits");
2254 /* Only emit control data bits if we've finished accumulating a batch
2255 * of 32 bits. This is the case when:
2257 * (vertex_count * bits_per_vertex) % 32 == 0
2259 * (in other words, when the last 5 bits of vertex_count *
2260 * bits_per_vertex are 0). Assuming bits_per_vertex == 2^n for some
2261 * integer n (which is always the case, since bits_per_vertex is
2262 * always 1 or 2), this is equivalent to requiring that the last 5-n
2263 * bits of vertex_count are 0:
2265 * vertex_count & (2^(5-n) - 1) == 0
2267 * 2^(5-n) == 2^5 / 2^n == 32 / bits_per_vertex, so this is
2270 * vertex_count & (32 / bits_per_vertex - 1) == 0
2272 * TODO: If vertex_count is an immediate, we could do some of this math
2273 * at compile time...
2276 abld
.AND(bld
.null_reg_d(), vertex_count
,
2277 brw_imm_ud(32u / gs_compile
->control_data_bits_per_vertex
- 1u));
2278 inst
->conditional_mod
= BRW_CONDITIONAL_Z
;
2280 abld
.IF(BRW_PREDICATE_NORMAL
);
2281 /* If vertex_count is 0, then no control data bits have been
2282 * accumulated yet, so we can skip emitting them.
2284 abld
.CMP(bld
.null_reg_d(), vertex_count
, brw_imm_ud(0u),
2285 BRW_CONDITIONAL_NEQ
);
2286 abld
.IF(BRW_PREDICATE_NORMAL
);
2287 emit_gs_control_data_bits(vertex_count
);
2288 abld
.emit(BRW_OPCODE_ENDIF
);
2290 /* Reset control_data_bits to 0 so we can start accumulating a new
2293 * Note: in the case where vertex_count == 0, this neutralizes the
2294 * effect of any call to EndPrimitive() that the shader may have
2295 * made before outputting its first vertex.
2297 inst
= abld
.MOV(this->control_data_bits
, brw_imm_ud(0u));
2298 inst
->force_writemask_all
= true;
2299 abld
.emit(BRW_OPCODE_ENDIF
);
2302 emit_urb_writes(vertex_count
);
2304 /* In stream mode we have to set control data bits for all vertices
2305 * unless we have disabled control data bits completely (which we do
2306 * do for GL_POINTS outputs that don't use streams).
2308 if (gs_compile
->control_data_header_size_bits
> 0 &&
2309 gs_prog_data
->control_data_format
==
2310 GEN7_GS_CONTROL_DATA_FORMAT_GSCTL_SID
) {
2311 set_gs_stream_control_data_bits(vertex_count
, stream_id
);
2316 fs_visitor::emit_gs_input_load(const fs_reg
&dst
,
2317 const nir_src
&vertex_src
,
2318 unsigned base_offset
,
2319 const nir_src
&offset_src
,
2320 unsigned num_components
,
2321 unsigned first_component
)
2323 assert(type_sz(dst
.type
) == 4);
2324 struct brw_gs_prog_data
*gs_prog_data
= brw_gs_prog_data(prog_data
);
2325 const unsigned push_reg_count
= gs_prog_data
->base
.urb_read_length
* 8;
2327 /* TODO: figure out push input layout for invocations == 1 */
2328 if (gs_prog_data
->invocations
== 1 &&
2329 nir_src_is_const(offset_src
) && nir_src_is_const(vertex_src
) &&
2330 4 * (base_offset
+ nir_src_as_uint(offset_src
)) < push_reg_count
) {
2331 int imm_offset
= (base_offset
+ nir_src_as_uint(offset_src
)) * 4 +
2332 nir_src_as_uint(vertex_src
) * push_reg_count
;
2333 for (unsigned i
= 0; i
< num_components
; i
++) {
2334 bld
.MOV(offset(dst
, bld
, i
),
2335 fs_reg(ATTR
, imm_offset
+ i
+ first_component
, dst
.type
));
2340 /* Resort to the pull model. Ensure the VUE handles are provided. */
2341 assert(gs_prog_data
->base
.include_vue_handles
);
2343 unsigned first_icp_handle
= gs_prog_data
->include_primitive_id
? 3 : 2;
2344 fs_reg icp_handle
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2346 if (gs_prog_data
->invocations
== 1) {
2347 if (nir_src_is_const(vertex_src
)) {
2348 /* The vertex index is constant; just select the proper URB handle. */
2350 retype(brw_vec8_grf(first_icp_handle
+ nir_src_as_uint(vertex_src
), 0),
2351 BRW_REGISTER_TYPE_UD
);
2353 /* The vertex index is non-constant. We need to use indirect
2354 * addressing to fetch the proper URB handle.
2356 * First, we start with the sequence <7, 6, 5, 4, 3, 2, 1, 0>
2357 * indicating that channel <n> should read the handle from
2358 * DWord <n>. We convert that to bytes by multiplying by 4.
2360 * Next, we convert the vertex index to bytes by multiplying
2361 * by 32 (shifting by 5), and add the two together. This is
2362 * the final indirect byte offset.
2364 fs_reg sequence
= bld
.vgrf(BRW_REGISTER_TYPE_UW
, 1);
2365 fs_reg channel_offsets
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2366 fs_reg vertex_offset_bytes
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2367 fs_reg icp_offset_bytes
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2369 /* sequence = <7, 6, 5, 4, 3, 2, 1, 0> */
2370 bld
.MOV(sequence
, fs_reg(brw_imm_v(0x76543210)));
2371 /* channel_offsets = 4 * sequence = <28, 24, 20, 16, 12, 8, 4, 0> */
2372 bld
.SHL(channel_offsets
, sequence
, brw_imm_ud(2u));
2373 /* Convert vertex_index to bytes (multiply by 32) */
2374 bld
.SHL(vertex_offset_bytes
,
2375 retype(get_nir_src(vertex_src
), BRW_REGISTER_TYPE_UD
),
2377 bld
.ADD(icp_offset_bytes
, vertex_offset_bytes
, channel_offsets
);
2379 /* Use first_icp_handle as the base offset. There is one register
2380 * of URB handles per vertex, so inform the register allocator that
2381 * we might read up to nir->info.gs.vertices_in registers.
2383 bld
.emit(SHADER_OPCODE_MOV_INDIRECT
, icp_handle
,
2384 retype(brw_vec8_grf(first_icp_handle
, 0), icp_handle
.type
),
2385 fs_reg(icp_offset_bytes
),
2386 brw_imm_ud(nir
->info
.gs
.vertices_in
* REG_SIZE
));
2389 assert(gs_prog_data
->invocations
> 1);
2391 if (nir_src_is_const(vertex_src
)) {
2392 unsigned vertex
= nir_src_as_uint(vertex_src
);
2393 assert(devinfo
->gen
>= 9 || vertex
<= 5);
2395 retype(brw_vec1_grf(first_icp_handle
+ vertex
/ 8, vertex
% 8),
2396 BRW_REGISTER_TYPE_UD
));
2398 /* The vertex index is non-constant. We need to use indirect
2399 * addressing to fetch the proper URB handle.
2402 fs_reg icp_offset_bytes
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2404 /* Convert vertex_index to bytes (multiply by 4) */
2405 bld
.SHL(icp_offset_bytes
,
2406 retype(get_nir_src(vertex_src
), BRW_REGISTER_TYPE_UD
),
2409 /* Use first_icp_handle as the base offset. There is one DWord
2410 * of URB handles per vertex, so inform the register allocator that
2411 * we might read up to ceil(nir->info.gs.vertices_in / 8) registers.
2413 bld
.emit(SHADER_OPCODE_MOV_INDIRECT
, icp_handle
,
2414 retype(brw_vec8_grf(first_icp_handle
, 0), icp_handle
.type
),
2415 fs_reg(icp_offset_bytes
),
2416 brw_imm_ud(DIV_ROUND_UP(nir
->info
.gs
.vertices_in
, 8) *
2422 fs_reg indirect_offset
= get_nir_src(offset_src
);
2424 if (nir_src_is_const(offset_src
)) {
2425 /* Constant indexing - use global offset. */
2426 if (first_component
!= 0) {
2427 unsigned read_components
= num_components
+ first_component
;
2428 fs_reg tmp
= bld
.vgrf(dst
.type
, read_components
);
2429 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8
, tmp
, icp_handle
);
2430 inst
->size_written
= read_components
*
2431 tmp
.component_size(inst
->exec_size
);
2432 for (unsigned i
= 0; i
< num_components
; i
++) {
2433 bld
.MOV(offset(dst
, bld
, i
),
2434 offset(tmp
, bld
, i
+ first_component
));
2437 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8
, dst
, icp_handle
);
2438 inst
->size_written
= num_components
*
2439 dst
.component_size(inst
->exec_size
);
2441 inst
->offset
= base_offset
+ nir_src_as_uint(offset_src
);
2444 /* Indirect indexing - use per-slot offsets as well. */
2445 const fs_reg srcs
[] = { icp_handle
, indirect_offset
};
2446 unsigned read_components
= num_components
+ first_component
;
2447 fs_reg tmp
= bld
.vgrf(dst
.type
, read_components
);
2448 fs_reg payload
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 2);
2449 bld
.LOAD_PAYLOAD(payload
, srcs
, ARRAY_SIZE(srcs
), 0);
2450 if (first_component
!= 0) {
2451 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT
, tmp
,
2453 inst
->size_written
= read_components
*
2454 tmp
.component_size(inst
->exec_size
);
2455 for (unsigned i
= 0; i
< num_components
; i
++) {
2456 bld
.MOV(offset(dst
, bld
, i
),
2457 offset(tmp
, bld
, i
+ first_component
));
2460 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT
, dst
, payload
);
2461 inst
->size_written
= num_components
*
2462 dst
.component_size(inst
->exec_size
);
2464 inst
->offset
= base_offset
;
2470 fs_visitor::get_indirect_offset(nir_intrinsic_instr
*instr
)
2472 nir_src
*offset_src
= nir_get_io_offset_src(instr
);
2474 if (nir_src_is_const(*offset_src
)) {
2475 /* The only constant offset we should find is 0. brw_nir.c's
2476 * add_const_offset_to_base() will fold other constant offsets
2477 * into instr->const_index[0].
2479 assert(nir_src_as_uint(*offset_src
) == 0);
2483 return get_nir_src(*offset_src
);
2487 fs_visitor::nir_emit_vs_intrinsic(const fs_builder
&bld
,
2488 nir_intrinsic_instr
*instr
)
2490 assert(stage
== MESA_SHADER_VERTEX
);
2493 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
2494 dest
= get_nir_dest(instr
->dest
);
2496 switch (instr
->intrinsic
) {
2497 case nir_intrinsic_load_vertex_id
:
2498 case nir_intrinsic_load_base_vertex
:
2499 unreachable("should be lowered by nir_lower_system_values()");
2501 case nir_intrinsic_load_input
: {
2502 assert(nir_dest_bit_size(instr
->dest
) == 32);
2503 fs_reg src
= fs_reg(ATTR
, nir_intrinsic_base(instr
) * 4, dest
.type
);
2504 src
= offset(src
, bld
, nir_intrinsic_component(instr
));
2505 src
= offset(src
, bld
, nir_src_as_uint(instr
->src
[0]));
2507 for (unsigned i
= 0; i
< instr
->num_components
; i
++)
2508 bld
.MOV(offset(dest
, bld
, i
), offset(src
, bld
, i
));
2512 case nir_intrinsic_load_vertex_id_zero_base
:
2513 case nir_intrinsic_load_instance_id
:
2514 case nir_intrinsic_load_base_instance
:
2515 case nir_intrinsic_load_draw_id
:
2516 case nir_intrinsic_load_first_vertex
:
2517 case nir_intrinsic_load_is_indexed_draw
:
2518 unreachable("lowered by brw_nir_lower_vs_inputs");
2521 nir_emit_intrinsic(bld
, instr
);
2527 fs_visitor::get_tcs_single_patch_icp_handle(const fs_builder
&bld
,
2528 nir_intrinsic_instr
*instr
)
2530 struct brw_tcs_prog_data
*tcs_prog_data
= brw_tcs_prog_data(prog_data
);
2531 const nir_src
&vertex_src
= instr
->src
[0];
2532 nir_intrinsic_instr
*vertex_intrin
= nir_src_as_intrinsic(vertex_src
);
2535 if (nir_src_is_const(vertex_src
)) {
2536 /* Emit a MOV to resolve <0,1,0> regioning. */
2537 icp_handle
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2538 unsigned vertex
= nir_src_as_uint(vertex_src
);
2540 retype(brw_vec1_grf(1 + (vertex
>> 3), vertex
& 7),
2541 BRW_REGISTER_TYPE_UD
));
2542 } else if (tcs_prog_data
->instances
== 1 && vertex_intrin
&&
2543 vertex_intrin
->intrinsic
== nir_intrinsic_load_invocation_id
) {
2544 /* For the common case of only 1 instance, an array index of
2545 * gl_InvocationID means reading g1. Skip all the indirect work.
2547 icp_handle
= retype(brw_vec8_grf(1, 0), BRW_REGISTER_TYPE_UD
);
2549 /* The vertex index is non-constant. We need to use indirect
2550 * addressing to fetch the proper URB handle.
2552 icp_handle
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2554 /* Each ICP handle is a single DWord (4 bytes) */
2555 fs_reg vertex_offset_bytes
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2556 bld
.SHL(vertex_offset_bytes
,
2557 retype(get_nir_src(vertex_src
), BRW_REGISTER_TYPE_UD
),
2560 /* Start at g1. We might read up to 4 registers. */
2561 bld
.emit(SHADER_OPCODE_MOV_INDIRECT
, icp_handle
,
2562 retype(brw_vec8_grf(1, 0), icp_handle
.type
), vertex_offset_bytes
,
2563 brw_imm_ud(4 * REG_SIZE
));
2570 fs_visitor::get_tcs_eight_patch_icp_handle(const fs_builder
&bld
,
2571 nir_intrinsic_instr
*instr
)
2573 struct brw_tcs_prog_key
*tcs_key
= (struct brw_tcs_prog_key
*) key
;
2574 struct brw_tcs_prog_data
*tcs_prog_data
= brw_tcs_prog_data(prog_data
);
2575 const nir_src
&vertex_src
= instr
->src
[0];
2577 unsigned first_icp_handle
= tcs_prog_data
->include_primitive_id
? 3 : 2;
2579 if (nir_src_is_const(vertex_src
)) {
2580 return fs_reg(retype(brw_vec8_grf(first_icp_handle
+
2581 nir_src_as_uint(vertex_src
), 0),
2582 BRW_REGISTER_TYPE_UD
));
2585 /* The vertex index is non-constant. We need to use indirect
2586 * addressing to fetch the proper URB handle.
2588 * First, we start with the sequence <7, 6, 5, 4, 3, 2, 1, 0>
2589 * indicating that channel <n> should read the handle from
2590 * DWord <n>. We convert that to bytes by multiplying by 4.
2592 * Next, we convert the vertex index to bytes by multiplying
2593 * by 32 (shifting by 5), and add the two together. This is
2594 * the final indirect byte offset.
2596 fs_reg icp_handle
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2597 fs_reg sequence
= bld
.vgrf(BRW_REGISTER_TYPE_UW
, 1);
2598 fs_reg channel_offsets
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2599 fs_reg vertex_offset_bytes
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2600 fs_reg icp_offset_bytes
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2602 /* sequence = <7, 6, 5, 4, 3, 2, 1, 0> */
2603 bld
.MOV(sequence
, fs_reg(brw_imm_v(0x76543210)));
2604 /* channel_offsets = 4 * sequence = <28, 24, 20, 16, 12, 8, 4, 0> */
2605 bld
.SHL(channel_offsets
, sequence
, brw_imm_ud(2u));
2606 /* Convert vertex_index to bytes (multiply by 32) */
2607 bld
.SHL(vertex_offset_bytes
,
2608 retype(get_nir_src(vertex_src
), BRW_REGISTER_TYPE_UD
),
2610 bld
.ADD(icp_offset_bytes
, vertex_offset_bytes
, channel_offsets
);
2612 /* Use first_icp_handle as the base offset. There is one register
2613 * of URB handles per vertex, so inform the register allocator that
2614 * we might read up to nir->info.gs.vertices_in registers.
2616 bld
.emit(SHADER_OPCODE_MOV_INDIRECT
, icp_handle
,
2617 retype(brw_vec8_grf(first_icp_handle
, 0), icp_handle
.type
),
2618 icp_offset_bytes
, brw_imm_ud(tcs_key
->input_vertices
* REG_SIZE
));
2624 fs_visitor::get_tcs_output_urb_handle()
2626 struct brw_vue_prog_data
*vue_prog_data
= brw_vue_prog_data(prog_data
);
2628 if (vue_prog_data
->dispatch_mode
== DISPATCH_MODE_TCS_SINGLE_PATCH
) {
2629 return retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_UD
);
2631 assert(vue_prog_data
->dispatch_mode
== DISPATCH_MODE_TCS_8_PATCH
);
2632 return retype(brw_vec8_grf(1, 0), BRW_REGISTER_TYPE_UD
);
2637 fs_visitor::nir_emit_tcs_intrinsic(const fs_builder
&bld
,
2638 nir_intrinsic_instr
*instr
)
2640 assert(stage
== MESA_SHADER_TESS_CTRL
);
2641 struct brw_tcs_prog_key
*tcs_key
= (struct brw_tcs_prog_key
*) key
;
2642 struct brw_tcs_prog_data
*tcs_prog_data
= brw_tcs_prog_data(prog_data
);
2643 struct brw_vue_prog_data
*vue_prog_data
= &tcs_prog_data
->base
;
2646 vue_prog_data
->dispatch_mode
== DISPATCH_MODE_TCS_8_PATCH
;
2649 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
2650 dst
= get_nir_dest(instr
->dest
);
2652 switch (instr
->intrinsic
) {
2653 case nir_intrinsic_load_primitive_id
:
2654 bld
.MOV(dst
, fs_reg(eight_patch
? brw_vec8_grf(2, 0)
2655 : brw_vec1_grf(0, 1)));
2657 case nir_intrinsic_load_invocation_id
:
2658 bld
.MOV(retype(dst
, invocation_id
.type
), invocation_id
);
2660 case nir_intrinsic_load_patch_vertices_in
:
2661 bld
.MOV(retype(dst
, BRW_REGISTER_TYPE_D
),
2662 brw_imm_d(tcs_key
->input_vertices
));
2665 case nir_intrinsic_barrier
: {
2666 if (tcs_prog_data
->instances
== 1)
2669 fs_reg m0
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2670 fs_reg m0_2
= component(m0
, 2);
2672 const fs_builder chanbld
= bld
.exec_all().group(1, 0);
2674 /* Zero the message header */
2675 bld
.exec_all().MOV(m0
, brw_imm_ud(0u));
2677 if (devinfo
->gen
< 11) {
2678 /* Copy "Barrier ID" from r0.2, bits 16:13 */
2679 chanbld
.AND(m0_2
, retype(brw_vec1_grf(0, 2), BRW_REGISTER_TYPE_UD
),
2680 brw_imm_ud(INTEL_MASK(16, 13)));
2682 /* Shift it up to bits 27:24. */
2683 chanbld
.SHL(m0_2
, m0_2
, brw_imm_ud(11));
2685 chanbld
.AND(m0_2
, retype(brw_vec1_grf(0, 2), BRW_REGISTER_TYPE_UD
),
2686 brw_imm_ud(INTEL_MASK(30, 24)));
2689 /* Set the Barrier Count and the enable bit */
2690 if (devinfo
->gen
< 11) {
2691 chanbld
.OR(m0_2
, m0_2
,
2692 brw_imm_ud(tcs_prog_data
->instances
<< 9 | (1 << 15)));
2694 chanbld
.OR(m0_2
, m0_2
,
2695 brw_imm_ud(tcs_prog_data
->instances
<< 8 | (1 << 15)));
2698 bld
.emit(SHADER_OPCODE_BARRIER
, bld
.null_reg_ud(), m0
);
2702 case nir_intrinsic_load_input
:
2703 unreachable("nir_lower_io should never give us these.");
2706 case nir_intrinsic_load_per_vertex_input
: {
2707 assert(nir_dest_bit_size(instr
->dest
) == 32);
2708 fs_reg indirect_offset
= get_indirect_offset(instr
);
2709 unsigned imm_offset
= instr
->const_index
[0];
2713 eight_patch
? get_tcs_eight_patch_icp_handle(bld
, instr
)
2714 : get_tcs_single_patch_icp_handle(bld
, instr
);
2716 /* We can only read two double components with each URB read, so
2717 * we send two read messages in that case, each one loading up to
2718 * two double components.
2720 unsigned num_components
= instr
->num_components
;
2721 unsigned first_component
= nir_intrinsic_component(instr
);
2723 if (indirect_offset
.file
== BAD_FILE
) {
2724 /* Constant indexing - use global offset. */
2725 if (first_component
!= 0) {
2726 unsigned read_components
= num_components
+ first_component
;
2727 fs_reg tmp
= bld
.vgrf(dst
.type
, read_components
);
2728 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8
, tmp
, icp_handle
);
2729 for (unsigned i
= 0; i
< num_components
; i
++) {
2730 bld
.MOV(offset(dst
, bld
, i
),
2731 offset(tmp
, bld
, i
+ first_component
));
2734 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8
, dst
, icp_handle
);
2736 inst
->offset
= imm_offset
;
2739 /* Indirect indexing - use per-slot offsets as well. */
2740 const fs_reg srcs
[] = { icp_handle
, indirect_offset
};
2741 fs_reg payload
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 2);
2742 bld
.LOAD_PAYLOAD(payload
, srcs
, ARRAY_SIZE(srcs
), 0);
2743 if (first_component
!= 0) {
2744 unsigned read_components
= num_components
+ first_component
;
2745 fs_reg tmp
= bld
.vgrf(dst
.type
, read_components
);
2746 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT
, tmp
,
2748 for (unsigned i
= 0; i
< num_components
; i
++) {
2749 bld
.MOV(offset(dst
, bld
, i
),
2750 offset(tmp
, bld
, i
+ first_component
));
2753 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT
, dst
,
2756 inst
->offset
= imm_offset
;
2759 inst
->size_written
= (num_components
+ first_component
) *
2760 inst
->dst
.component_size(inst
->exec_size
);
2762 /* Copy the temporary to the destination to deal with writemasking.
2764 * Also attempt to deal with gl_PointSize being in the .w component.
2766 if (inst
->offset
== 0 && indirect_offset
.file
== BAD_FILE
) {
2767 assert(type_sz(dst
.type
) == 4);
2768 inst
->dst
= bld
.vgrf(dst
.type
, 4);
2769 inst
->size_written
= 4 * REG_SIZE
;
2770 bld
.MOV(dst
, offset(inst
->dst
, bld
, 3));
2775 case nir_intrinsic_load_output
:
2776 case nir_intrinsic_load_per_vertex_output
: {
2777 assert(nir_dest_bit_size(instr
->dest
) == 32);
2778 fs_reg indirect_offset
= get_indirect_offset(instr
);
2779 unsigned imm_offset
= instr
->const_index
[0];
2780 unsigned first_component
= nir_intrinsic_component(instr
);
2782 struct brw_reg output_handles
= get_tcs_output_urb_handle();
2785 if (indirect_offset
.file
== BAD_FILE
) {
2786 /* This MOV replicates the output handle to all enabled channels
2787 * is SINGLE_PATCH mode.
2789 fs_reg patch_handle
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2790 bld
.MOV(patch_handle
, output_handles
);
2793 if (first_component
!= 0) {
2794 unsigned read_components
=
2795 instr
->num_components
+ first_component
;
2796 fs_reg tmp
= bld
.vgrf(dst
.type
, read_components
);
2797 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8
, tmp
,
2799 inst
->size_written
= read_components
* REG_SIZE
;
2800 for (unsigned i
= 0; i
< instr
->num_components
; i
++) {
2801 bld
.MOV(offset(dst
, bld
, i
),
2802 offset(tmp
, bld
, i
+ first_component
));
2805 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8
, dst
,
2807 inst
->size_written
= instr
->num_components
* REG_SIZE
;
2809 inst
->offset
= imm_offset
;
2813 /* Indirect indexing - use per-slot offsets as well. */
2814 const fs_reg srcs
[] = { output_handles
, indirect_offset
};
2815 fs_reg payload
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 2);
2816 bld
.LOAD_PAYLOAD(payload
, srcs
, ARRAY_SIZE(srcs
), 0);
2817 if (first_component
!= 0) {
2818 unsigned read_components
=
2819 instr
->num_components
+ first_component
;
2820 fs_reg tmp
= bld
.vgrf(dst
.type
, read_components
);
2821 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT
, tmp
,
2823 inst
->size_written
= read_components
* REG_SIZE
;
2824 for (unsigned i
= 0; i
< instr
->num_components
; i
++) {
2825 bld
.MOV(offset(dst
, bld
, i
),
2826 offset(tmp
, bld
, i
+ first_component
));
2829 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT
, dst
,
2831 inst
->size_written
= instr
->num_components
* REG_SIZE
;
2833 inst
->offset
= imm_offset
;
2839 case nir_intrinsic_store_output
:
2840 case nir_intrinsic_store_per_vertex_output
: {
2841 assert(nir_src_bit_size(instr
->src
[0]) == 32);
2842 fs_reg value
= get_nir_src(instr
->src
[0]);
2843 fs_reg indirect_offset
= get_indirect_offset(instr
);
2844 unsigned imm_offset
= instr
->const_index
[0];
2845 unsigned mask
= instr
->const_index
[1];
2846 unsigned header_regs
= 0;
2847 struct brw_reg output_handles
= get_tcs_output_urb_handle();
2850 srcs
[header_regs
++] = output_handles
;
2852 if (indirect_offset
.file
!= BAD_FILE
) {
2853 srcs
[header_regs
++] = indirect_offset
;
2859 unsigned num_components
= util_last_bit(mask
);
2862 /* We can only pack two 64-bit components in a single message, so send
2863 * 2 messages if we have more components
2865 unsigned first_component
= nir_intrinsic_component(instr
);
2866 mask
= mask
<< first_component
;
2868 if (mask
!= WRITEMASK_XYZW
) {
2869 srcs
[header_regs
++] = brw_imm_ud(mask
<< 16);
2870 opcode
= indirect_offset
.file
!= BAD_FILE
?
2871 SHADER_OPCODE_URB_WRITE_SIMD8_MASKED_PER_SLOT
:
2872 SHADER_OPCODE_URB_WRITE_SIMD8_MASKED
;
2874 opcode
= indirect_offset
.file
!= BAD_FILE
?
2875 SHADER_OPCODE_URB_WRITE_SIMD8_PER_SLOT
:
2876 SHADER_OPCODE_URB_WRITE_SIMD8
;
2879 for (unsigned i
= 0; i
< num_components
; i
++) {
2880 if (!(mask
& (1 << (i
+ first_component
))))
2883 srcs
[header_regs
+ i
+ first_component
] = offset(value
, bld
, i
);
2886 unsigned mlen
= header_regs
+ num_components
+ first_component
;
2888 bld
.vgrf(BRW_REGISTER_TYPE_UD
, mlen
);
2889 bld
.LOAD_PAYLOAD(payload
, srcs
, mlen
, header_regs
);
2891 fs_inst
*inst
= bld
.emit(opcode
, bld
.null_reg_ud(), payload
);
2892 inst
->offset
= imm_offset
;
2898 nir_emit_intrinsic(bld
, instr
);
2904 fs_visitor::nir_emit_tes_intrinsic(const fs_builder
&bld
,
2905 nir_intrinsic_instr
*instr
)
2907 assert(stage
== MESA_SHADER_TESS_EVAL
);
2908 struct brw_tes_prog_data
*tes_prog_data
= brw_tes_prog_data(prog_data
);
2911 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
2912 dest
= get_nir_dest(instr
->dest
);
2914 switch (instr
->intrinsic
) {
2915 case nir_intrinsic_load_primitive_id
:
2916 bld
.MOV(dest
, fs_reg(brw_vec1_grf(0, 1)));
2918 case nir_intrinsic_load_tess_coord
:
2919 /* gl_TessCoord is part of the payload in g1-3 */
2920 for (unsigned i
= 0; i
< 3; i
++) {
2921 bld
.MOV(offset(dest
, bld
, i
), fs_reg(brw_vec8_grf(1 + i
, 0)));
2925 case nir_intrinsic_load_input
:
2926 case nir_intrinsic_load_per_vertex_input
: {
2927 assert(nir_dest_bit_size(instr
->dest
) == 32);
2928 fs_reg indirect_offset
= get_indirect_offset(instr
);
2929 unsigned imm_offset
= instr
->const_index
[0];
2930 unsigned first_component
= nir_intrinsic_component(instr
);
2933 if (indirect_offset
.file
== BAD_FILE
) {
2934 /* Arbitrarily only push up to 32 vec4 slots worth of data,
2935 * which is 16 registers (since each holds 2 vec4 slots).
2937 const unsigned max_push_slots
= 32;
2938 if (imm_offset
< max_push_slots
) {
2939 fs_reg src
= fs_reg(ATTR
, imm_offset
/ 2, dest
.type
);
2940 for (int i
= 0; i
< instr
->num_components
; i
++) {
2941 unsigned comp
= 4 * (imm_offset
% 2) + i
+ first_component
;
2942 bld
.MOV(offset(dest
, bld
, i
), component(src
, comp
));
2945 tes_prog_data
->base
.urb_read_length
=
2946 MAX2(tes_prog_data
->base
.urb_read_length
,
2947 (imm_offset
/ 2) + 1);
2949 /* Replicate the patch handle to all enabled channels */
2950 const fs_reg srcs
[] = {
2951 retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_UD
)
2953 fs_reg patch_handle
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2954 bld
.LOAD_PAYLOAD(patch_handle
, srcs
, ARRAY_SIZE(srcs
), 0);
2956 if (first_component
!= 0) {
2957 unsigned read_components
=
2958 instr
->num_components
+ first_component
;
2959 fs_reg tmp
= bld
.vgrf(dest
.type
, read_components
);
2960 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8
, tmp
,
2962 inst
->size_written
= read_components
* REG_SIZE
;
2963 for (unsigned i
= 0; i
< instr
->num_components
; i
++) {
2964 bld
.MOV(offset(dest
, bld
, i
),
2965 offset(tmp
, bld
, i
+ first_component
));
2968 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8
, dest
,
2970 inst
->size_written
= instr
->num_components
* REG_SIZE
;
2973 inst
->offset
= imm_offset
;
2976 /* Indirect indexing - use per-slot offsets as well. */
2978 /* We can only read two double components with each URB read, so
2979 * we send two read messages in that case, each one loading up to
2980 * two double components.
2982 unsigned num_components
= instr
->num_components
;
2983 const fs_reg srcs
[] = {
2984 retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_UD
),
2987 fs_reg payload
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 2);
2988 bld
.LOAD_PAYLOAD(payload
, srcs
, ARRAY_SIZE(srcs
), 0);
2990 if (first_component
!= 0) {
2991 unsigned read_components
=
2992 num_components
+ first_component
;
2993 fs_reg tmp
= bld
.vgrf(dest
.type
, read_components
);
2994 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT
, tmp
,
2996 for (unsigned i
= 0; i
< num_components
; i
++) {
2997 bld
.MOV(offset(dest
, bld
, i
),
2998 offset(tmp
, bld
, i
+ first_component
));
3001 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT
, dest
,
3005 inst
->offset
= imm_offset
;
3006 inst
->size_written
= (num_components
+ first_component
) *
3007 inst
->dst
.component_size(inst
->exec_size
);
3012 nir_emit_intrinsic(bld
, instr
);
3018 fs_visitor::nir_emit_gs_intrinsic(const fs_builder
&bld
,
3019 nir_intrinsic_instr
*instr
)
3021 assert(stage
== MESA_SHADER_GEOMETRY
);
3022 fs_reg indirect_offset
;
3025 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
3026 dest
= get_nir_dest(instr
->dest
);
3028 switch (instr
->intrinsic
) {
3029 case nir_intrinsic_load_primitive_id
:
3030 assert(stage
== MESA_SHADER_GEOMETRY
);
3031 assert(brw_gs_prog_data(prog_data
)->include_primitive_id
);
3032 bld
.MOV(retype(dest
, BRW_REGISTER_TYPE_UD
),
3033 retype(fs_reg(brw_vec8_grf(2, 0)), BRW_REGISTER_TYPE_UD
));
3036 case nir_intrinsic_load_input
:
3037 unreachable("load_input intrinsics are invalid for the GS stage");
3039 case nir_intrinsic_load_per_vertex_input
:
3040 emit_gs_input_load(dest
, instr
->src
[0], instr
->const_index
[0],
3041 instr
->src
[1], instr
->num_components
,
3042 nir_intrinsic_component(instr
));
3045 case nir_intrinsic_emit_vertex_with_counter
:
3046 emit_gs_vertex(instr
->src
[0], instr
->const_index
[0]);
3049 case nir_intrinsic_end_primitive_with_counter
:
3050 emit_gs_end_primitive(instr
->src
[0]);
3053 case nir_intrinsic_set_vertex_count
:
3054 bld
.MOV(this->final_gs_vertex_count
, get_nir_src(instr
->src
[0]));
3057 case nir_intrinsic_load_invocation_id
: {
3058 fs_reg val
= nir_system_values
[SYSTEM_VALUE_INVOCATION_ID
];
3059 assert(val
.file
!= BAD_FILE
);
3060 dest
.type
= val
.type
;
3066 nir_emit_intrinsic(bld
, instr
);
3072 * Fetch the current render target layer index.
3075 fetch_render_target_array_index(const fs_builder
&bld
)
3077 if (bld
.shader
->devinfo
->gen
>= 6) {
3078 /* The render target array index is provided in the thread payload as
3079 * bits 26:16 of r0.0.
3081 const fs_reg idx
= bld
.vgrf(BRW_REGISTER_TYPE_UD
);
3082 bld
.AND(idx
, brw_uw1_reg(BRW_GENERAL_REGISTER_FILE
, 0, 1),
3086 /* Pre-SNB we only ever render into the first layer of the framebuffer
3087 * since layered rendering is not implemented.
3089 return brw_imm_ud(0);
3094 * Fake non-coherent framebuffer read implemented using TXF to fetch from the
3095 * framebuffer at the current fragment coordinates and sample index.
3098 fs_visitor::emit_non_coherent_fb_read(const fs_builder
&bld
, const fs_reg
&dst
,
3101 const struct gen_device_info
*devinfo
= bld
.shader
->devinfo
;
3103 assert(bld
.shader
->stage
== MESA_SHADER_FRAGMENT
);
3104 const brw_wm_prog_key
*wm_key
=
3105 reinterpret_cast<const brw_wm_prog_key
*>(key
);
3106 assert(!wm_key
->coherent_fb_fetch
);
3107 const struct brw_wm_prog_data
*wm_prog_data
=
3108 brw_wm_prog_data(stage_prog_data
);
3110 /* Calculate the surface index relative to the start of the texture binding
3111 * table block, since that's what the texturing messages expect.
3113 const unsigned surface
= target
+
3114 wm_prog_data
->binding_table
.render_target_read_start
-
3115 wm_prog_data
->base
.binding_table
.texture_start
;
3117 /* Calculate the fragment coordinates. */
3118 const fs_reg coords
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 3);
3119 bld
.MOV(offset(coords
, bld
, 0), pixel_x
);
3120 bld
.MOV(offset(coords
, bld
, 1), pixel_y
);
3121 bld
.MOV(offset(coords
, bld
, 2), fetch_render_target_array_index(bld
));
3123 /* Calculate the sample index and MCS payload when multisampling. Luckily
3124 * the MCS fetch message behaves deterministically for UMS surfaces, so it
3125 * shouldn't be necessary to recompile based on whether the framebuffer is
3128 if (wm_key
->multisample_fbo
&&
3129 nir_system_values
[SYSTEM_VALUE_SAMPLE_ID
].file
== BAD_FILE
)
3130 nir_system_values
[SYSTEM_VALUE_SAMPLE_ID
] = *emit_sampleid_setup();
3132 const fs_reg sample
= nir_system_values
[SYSTEM_VALUE_SAMPLE_ID
];
3133 const fs_reg mcs
= wm_key
->multisample_fbo
?
3134 emit_mcs_fetch(coords
, 3, brw_imm_ud(surface
), fs_reg()) : fs_reg();
3136 /* Use either a normal or a CMS texel fetch message depending on whether
3137 * the framebuffer is single or multisample. On SKL+ use the wide CMS
3138 * message just in case the framebuffer uses 16x multisampling, it should
3139 * be equivalent to the normal CMS fetch for lower multisampling modes.
3141 const opcode op
= !wm_key
->multisample_fbo
? SHADER_OPCODE_TXF_LOGICAL
:
3142 devinfo
->gen
>= 9 ? SHADER_OPCODE_TXF_CMS_W_LOGICAL
:
3143 SHADER_OPCODE_TXF_CMS_LOGICAL
;
3145 /* Emit the instruction. */
3146 fs_reg srcs
[TEX_LOGICAL_NUM_SRCS
];
3147 srcs
[TEX_LOGICAL_SRC_COORDINATE
] = coords
;
3148 srcs
[TEX_LOGICAL_SRC_LOD
] = brw_imm_ud(0);
3149 srcs
[TEX_LOGICAL_SRC_SAMPLE_INDEX
] = sample
;
3150 srcs
[TEX_LOGICAL_SRC_MCS
] = mcs
;
3151 srcs
[TEX_LOGICAL_SRC_SURFACE
] = brw_imm_ud(surface
);
3152 srcs
[TEX_LOGICAL_SRC_SAMPLER
] = brw_imm_ud(0);
3153 srcs
[TEX_LOGICAL_SRC_COORD_COMPONENTS
] = brw_imm_ud(3);
3154 srcs
[TEX_LOGICAL_SRC_GRAD_COMPONENTS
] = brw_imm_ud(0);
3156 fs_inst
*inst
= bld
.emit(op
, dst
, srcs
, ARRAY_SIZE(srcs
));
3157 inst
->size_written
= 4 * inst
->dst
.component_size(inst
->exec_size
);
3163 * Actual coherent framebuffer read implemented using the native render target
3164 * read message. Requires SKL+.
3167 emit_coherent_fb_read(const fs_builder
&bld
, const fs_reg
&dst
, unsigned target
)
3169 assert(bld
.shader
->devinfo
->gen
>= 9);
3170 fs_inst
*inst
= bld
.emit(FS_OPCODE_FB_READ_LOGICAL
, dst
);
3171 inst
->target
= target
;
3172 inst
->size_written
= 4 * inst
->dst
.component_size(inst
->exec_size
);
3178 alloc_temporary(const fs_builder
&bld
, unsigned size
, fs_reg
*regs
, unsigned n
)
3180 if (n
&& regs
[0].file
!= BAD_FILE
) {
3184 const fs_reg tmp
= bld
.vgrf(BRW_REGISTER_TYPE_F
, size
);
3186 for (unsigned i
= 0; i
< n
; i
++)
3194 alloc_frag_output(fs_visitor
*v
, unsigned location
)
3196 assert(v
->stage
== MESA_SHADER_FRAGMENT
);
3197 const brw_wm_prog_key
*const key
=
3198 reinterpret_cast<const brw_wm_prog_key
*>(v
->key
);
3199 const unsigned l
= GET_FIELD(location
, BRW_NIR_FRAG_OUTPUT_LOCATION
);
3200 const unsigned i
= GET_FIELD(location
, BRW_NIR_FRAG_OUTPUT_INDEX
);
3202 if (i
> 0 || (key
->force_dual_color_blend
&& l
== FRAG_RESULT_DATA1
))
3203 return alloc_temporary(v
->bld
, 4, &v
->dual_src_output
, 1);
3205 else if (l
== FRAG_RESULT_COLOR
)
3206 return alloc_temporary(v
->bld
, 4, v
->outputs
,
3207 MAX2(key
->nr_color_regions
, 1));
3209 else if (l
== FRAG_RESULT_DEPTH
)
3210 return alloc_temporary(v
->bld
, 1, &v
->frag_depth
, 1);
3212 else if (l
== FRAG_RESULT_STENCIL
)
3213 return alloc_temporary(v
->bld
, 1, &v
->frag_stencil
, 1);
3215 else if (l
== FRAG_RESULT_SAMPLE_MASK
)
3216 return alloc_temporary(v
->bld
, 1, &v
->sample_mask
, 1);
3218 else if (l
>= FRAG_RESULT_DATA0
&&
3219 l
< FRAG_RESULT_DATA0
+ BRW_MAX_DRAW_BUFFERS
)
3220 return alloc_temporary(v
->bld
, 4,
3221 &v
->outputs
[l
- FRAG_RESULT_DATA0
], 1);
3224 unreachable("Invalid location");
3227 /* Annoyingly, we get the barycentrics into the shader in a layout that's
3228 * optimized for PLN but it doesn't work nearly as well as one would like for
3229 * manual interpolation.
3232 shuffle_from_pln_layout(const fs_builder
&bld
, fs_reg dest
, fs_reg pln_data
)
3234 dest
.type
= BRW_REGISTER_TYPE_F
;
3235 pln_data
.type
= BRW_REGISTER_TYPE_F
;
3236 const fs_reg dest_u
= offset(dest
, bld
, 0);
3237 const fs_reg dest_v
= offset(dest
, bld
, 1);
3239 for (unsigned g
= 0; g
< bld
.dispatch_width() / 8; g
++) {
3240 const fs_builder gbld
= bld
.group(8, g
);
3241 gbld
.MOV(horiz_offset(dest_u
, g
* 8),
3242 byte_offset(pln_data
, (g
* 2 + 0) * REG_SIZE
));
3243 gbld
.MOV(horiz_offset(dest_v
, g
* 8),
3244 byte_offset(pln_data
, (g
* 2 + 1) * REG_SIZE
));
3249 shuffle_to_pln_layout(const fs_builder
&bld
, fs_reg pln_data
, fs_reg src
)
3251 pln_data
.type
= BRW_REGISTER_TYPE_F
;
3252 src
.type
= BRW_REGISTER_TYPE_F
;
3253 const fs_reg src_u
= offset(src
, bld
, 0);
3254 const fs_reg src_v
= offset(src
, bld
, 1);
3256 for (unsigned g
= 0; g
< bld
.dispatch_width() / 8; g
++) {
3257 const fs_builder gbld
= bld
.group(8, g
);
3258 gbld
.MOV(byte_offset(pln_data
, (g
* 2 + 0) * REG_SIZE
),
3259 horiz_offset(src_u
, g
* 8));
3260 gbld
.MOV(byte_offset(pln_data
, (g
* 2 + 1) * REG_SIZE
),
3261 horiz_offset(src_v
, g
* 8));
3266 fs_visitor::nir_emit_fs_intrinsic(const fs_builder
&bld
,
3267 nir_intrinsic_instr
*instr
)
3269 assert(stage
== MESA_SHADER_FRAGMENT
);
3272 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
3273 dest
= get_nir_dest(instr
->dest
);
3275 switch (instr
->intrinsic
) {
3276 case nir_intrinsic_load_front_face
:
3277 bld
.MOV(retype(dest
, BRW_REGISTER_TYPE_D
),
3278 *emit_frontfacing_interpolation());
3281 case nir_intrinsic_load_sample_pos
: {
3282 fs_reg sample_pos
= nir_system_values
[SYSTEM_VALUE_SAMPLE_POS
];
3283 assert(sample_pos
.file
!= BAD_FILE
);
3284 dest
.type
= sample_pos
.type
;
3285 bld
.MOV(dest
, sample_pos
);
3286 bld
.MOV(offset(dest
, bld
, 1), offset(sample_pos
, bld
, 1));
3290 case nir_intrinsic_load_layer_id
:
3291 dest
.type
= BRW_REGISTER_TYPE_UD
;
3292 bld
.MOV(dest
, fetch_render_target_array_index(bld
));
3295 case nir_intrinsic_is_helper_invocation
: {
3296 /* Unlike the regular gl_HelperInvocation, that is defined at dispatch,
3297 * the helperInvocationEXT() (aka SpvOpIsHelperInvocationEXT) takes into
3298 * consideration demoted invocations. That information is stored in
3301 dest
.type
= BRW_REGISTER_TYPE_UD
;
3303 bld
.MOV(dest
, brw_imm_ud(0));
3305 fs_inst
*mov
= bld
.MOV(dest
, brw_imm_ud(~0));
3306 mov
->predicate
= BRW_PREDICATE_NORMAL
;
3307 mov
->predicate_inverse
= true;
3308 mov
->flag_subreg
= 1;
3312 case nir_intrinsic_load_helper_invocation
:
3313 case nir_intrinsic_load_sample_mask_in
:
3314 case nir_intrinsic_load_sample_id
: {
3315 gl_system_value sv
= nir_system_value_from_intrinsic(instr
->intrinsic
);
3316 fs_reg val
= nir_system_values
[sv
];
3317 assert(val
.file
!= BAD_FILE
);
3318 dest
.type
= val
.type
;
3323 case nir_intrinsic_store_output
: {
3324 const fs_reg src
= get_nir_src(instr
->src
[0]);
3325 const unsigned store_offset
= nir_src_as_uint(instr
->src
[1]);
3326 const unsigned location
= nir_intrinsic_base(instr
) +
3327 SET_FIELD(store_offset
, BRW_NIR_FRAG_OUTPUT_LOCATION
);
3328 const fs_reg new_dest
= retype(alloc_frag_output(this, location
),
3331 for (unsigned j
= 0; j
< instr
->num_components
; j
++)
3332 bld
.MOV(offset(new_dest
, bld
, nir_intrinsic_component(instr
) + j
),
3333 offset(src
, bld
, j
));
3338 case nir_intrinsic_load_output
: {
3339 const unsigned l
= GET_FIELD(nir_intrinsic_base(instr
),
3340 BRW_NIR_FRAG_OUTPUT_LOCATION
);
3341 assert(l
>= FRAG_RESULT_DATA0
);
3342 const unsigned load_offset
= nir_src_as_uint(instr
->src
[0]);
3343 const unsigned target
= l
- FRAG_RESULT_DATA0
+ load_offset
;
3344 const fs_reg tmp
= bld
.vgrf(dest
.type
, 4);
3346 if (reinterpret_cast<const brw_wm_prog_key
*>(key
)->coherent_fb_fetch
)
3347 emit_coherent_fb_read(bld
, tmp
, target
);
3349 emit_non_coherent_fb_read(bld
, tmp
, target
);
3351 for (unsigned j
= 0; j
< instr
->num_components
; j
++) {
3352 bld
.MOV(offset(dest
, bld
, j
),
3353 offset(tmp
, bld
, nir_intrinsic_component(instr
) + j
));
3359 case nir_intrinsic_demote
:
3360 case nir_intrinsic_discard
:
3361 case nir_intrinsic_demote_if
:
3362 case nir_intrinsic_discard_if
: {
3363 /* We track our discarded pixels in f0.1. By predicating on it, we can
3364 * update just the flag bits that aren't yet discarded. If there's no
3365 * condition, we emit a CMP of g0 != g0, so all currently executing
3366 * channels will get turned off.
3368 fs_inst
*cmp
= NULL
;
3369 if (instr
->intrinsic
== nir_intrinsic_demote_if
||
3370 instr
->intrinsic
== nir_intrinsic_discard_if
) {
3371 nir_alu_instr
*alu
= nir_src_as_alu_instr(instr
->src
[0]);
3374 alu
->op
!= nir_op_bcsel
&&
3375 alu
->op
!= nir_op_inot
) {
3376 /* Re-emit the instruction that generated the Boolean value, but
3377 * do not store it. Since this instruction will be conditional,
3378 * other instructions that want to use the real Boolean value may
3379 * get garbage. This was a problem for piglit's fs-discard-exit-2
3382 * Ideally we'd detect that the instruction cannot have a
3383 * conditional modifier before emitting the instructions. Alas,
3384 * that is nigh impossible. Instead, we're going to assume the
3385 * instruction (or last instruction) generated can have a
3386 * conditional modifier. If it cannot, fallback to the old-style
3387 * compare, and hope dead code elimination will clean up the
3388 * extra instructions generated.
3390 nir_emit_alu(bld
, alu
, false);
3392 cmp
= (fs_inst
*) instructions
.get_tail();
3393 if (cmp
->conditional_mod
== BRW_CONDITIONAL_NONE
) {
3394 if (cmp
->can_do_cmod())
3395 cmp
->conditional_mod
= BRW_CONDITIONAL_Z
;
3399 /* The old sequence that would have been generated is,
3400 * basically, bool_result == false. This is equivalent to
3401 * !bool_result, so negate the old modifier.
3403 cmp
->conditional_mod
= brw_negate_cmod(cmp
->conditional_mod
);
3408 cmp
= bld
.CMP(bld
.null_reg_f(), get_nir_src(instr
->src
[0]),
3409 brw_imm_d(0), BRW_CONDITIONAL_Z
);
3412 fs_reg some_reg
= fs_reg(retype(brw_vec8_grf(0, 0),
3413 BRW_REGISTER_TYPE_UW
));
3414 cmp
= bld
.CMP(bld
.null_reg_f(), some_reg
, some_reg
, BRW_CONDITIONAL_NZ
);
3417 cmp
->predicate
= BRW_PREDICATE_NORMAL
;
3418 cmp
->flag_subreg
= 1;
3420 if (devinfo
->gen
>= 6) {
3421 /* Due to the way we implement discard, the jump will only happen
3422 * when the whole quad is discarded. So we can do this even for
3423 * demote as it won't break its uniformity promises.
3425 emit_discard_jump();
3428 limit_dispatch_width(16, "Fragment discard/demote not implemented in SIMD32 mode.");
3432 case nir_intrinsic_load_input
: {
3433 /* load_input is only used for flat inputs */
3434 assert(nir_dest_bit_size(instr
->dest
) == 32);
3435 unsigned base
= nir_intrinsic_base(instr
);
3436 unsigned comp
= nir_intrinsic_component(instr
);
3437 unsigned num_components
= instr
->num_components
;
3439 /* Special case fields in the VUE header */
3440 if (base
== VARYING_SLOT_LAYER
)
3442 else if (base
== VARYING_SLOT_VIEWPORT
)
3445 for (unsigned int i
= 0; i
< num_components
; i
++) {
3446 bld
.MOV(offset(dest
, bld
, i
),
3447 retype(component(interp_reg(base
, comp
+ i
), 3), dest
.type
));
3452 case nir_intrinsic_load_fs_input_interp_deltas
: {
3453 assert(stage
== MESA_SHADER_FRAGMENT
);
3454 assert(nir_src_as_uint(instr
->src
[0]) == 0);
3455 fs_reg interp
= interp_reg(nir_intrinsic_base(instr
),
3456 nir_intrinsic_component(instr
));
3457 dest
.type
= BRW_REGISTER_TYPE_F
;
3458 bld
.MOV(offset(dest
, bld
, 0), component(interp
, 3));
3459 bld
.MOV(offset(dest
, bld
, 1), component(interp
, 1));
3460 bld
.MOV(offset(dest
, bld
, 2), component(interp
, 0));
3464 case nir_intrinsic_load_barycentric_pixel
:
3465 case nir_intrinsic_load_barycentric_centroid
:
3466 case nir_intrinsic_load_barycentric_sample
: {
3467 /* Use the delta_xy values computed from the payload */
3468 const glsl_interp_mode interp_mode
=
3469 (enum glsl_interp_mode
) nir_intrinsic_interp_mode(instr
);
3470 enum brw_barycentric_mode bary
=
3471 brw_barycentric_mode(interp_mode
, instr
->intrinsic
);
3473 shuffle_from_pln_layout(bld
, dest
, this->delta_xy
[bary
]);
3477 case nir_intrinsic_load_barycentric_at_sample
: {
3478 const glsl_interp_mode interpolation
=
3479 (enum glsl_interp_mode
) nir_intrinsic_interp_mode(instr
);
3481 fs_reg tmp
= bld
.vgrf(BRW_REGISTER_TYPE_F
, 2);
3482 if (nir_src_is_const(instr
->src
[0])) {
3483 unsigned msg_data
= nir_src_as_uint(instr
->src
[0]) << 4;
3485 emit_pixel_interpolater_send(bld
,
3486 FS_OPCODE_INTERPOLATE_AT_SAMPLE
,
3489 brw_imm_ud(msg_data
),
3492 const fs_reg sample_src
= retype(get_nir_src(instr
->src
[0]),
3493 BRW_REGISTER_TYPE_UD
);
3495 if (nir_src_is_dynamically_uniform(instr
->src
[0])) {
3496 const fs_reg sample_id
= bld
.emit_uniformize(sample_src
);
3497 const fs_reg msg_data
= vgrf(glsl_type::uint_type
);
3498 bld
.exec_all().group(1, 0)
3499 .SHL(msg_data
, sample_id
, brw_imm_ud(4u));
3500 emit_pixel_interpolater_send(bld
,
3501 FS_OPCODE_INTERPOLATE_AT_SAMPLE
,
3507 /* Make a loop that sends a message to the pixel interpolater
3508 * for the sample number in each live channel. If there are
3509 * multiple channels with the same sample number then these
3510 * will be handled simultaneously with a single interation of
3513 bld
.emit(BRW_OPCODE_DO
);
3515 /* Get the next live sample number into sample_id_reg */
3516 const fs_reg sample_id
= bld
.emit_uniformize(sample_src
);
3518 /* Set the flag register so that we can perform the send
3519 * message on all channels that have the same sample number
3521 bld
.CMP(bld
.null_reg_ud(),
3522 sample_src
, sample_id
,
3523 BRW_CONDITIONAL_EQ
);
3524 const fs_reg msg_data
= vgrf(glsl_type::uint_type
);
3525 bld
.exec_all().group(1, 0)
3526 .SHL(msg_data
, sample_id
, brw_imm_ud(4u));
3528 emit_pixel_interpolater_send(bld
,
3529 FS_OPCODE_INTERPOLATE_AT_SAMPLE
,
3532 component(msg_data
, 0),
3534 set_predicate(BRW_PREDICATE_NORMAL
, inst
);
3536 /* Continue the loop if there are any live channels left */
3537 set_predicate_inv(BRW_PREDICATE_NORMAL
,
3539 bld
.emit(BRW_OPCODE_WHILE
));
3542 shuffle_from_pln_layout(bld
, dest
, tmp
);
3546 case nir_intrinsic_load_barycentric_at_offset
: {
3547 const glsl_interp_mode interpolation
=
3548 (enum glsl_interp_mode
) nir_intrinsic_interp_mode(instr
);
3550 nir_const_value
*const_offset
= nir_src_as_const_value(instr
->src
[0]);
3552 fs_reg tmp
= bld
.vgrf(BRW_REGISTER_TYPE_F
, 2);
3554 assert(nir_src_bit_size(instr
->src
[0]) == 32);
3555 unsigned off_x
= MIN2((int)(const_offset
[0].f32
* 16), 7) & 0xf;
3556 unsigned off_y
= MIN2((int)(const_offset
[1].f32
* 16), 7) & 0xf;
3558 emit_pixel_interpolater_send(bld
,
3559 FS_OPCODE_INTERPOLATE_AT_SHARED_OFFSET
,
3562 brw_imm_ud(off_x
| (off_y
<< 4)),
3565 fs_reg src
= vgrf(glsl_type::ivec2_type
);
3566 fs_reg offset_src
= retype(get_nir_src(instr
->src
[0]),
3567 BRW_REGISTER_TYPE_F
);
3568 for (int i
= 0; i
< 2; i
++) {
3569 fs_reg temp
= vgrf(glsl_type::float_type
);
3570 bld
.MUL(temp
, offset(offset_src
, bld
, i
), brw_imm_f(16.0f
));
3571 fs_reg itemp
= vgrf(glsl_type::int_type
);
3573 bld
.MOV(itemp
, temp
);
3575 /* Clamp the upper end of the range to +7/16.
3576 * ARB_gpu_shader5 requires that we support a maximum offset
3577 * of +0.5, which isn't representable in a S0.4 value -- if
3578 * we didn't clamp it, we'd end up with -8/16, which is the
3579 * opposite of what the shader author wanted.
3581 * This is legal due to ARB_gpu_shader5's quantization
3584 * "Not all values of <offset> may be supported; x and y
3585 * offsets may be rounded to fixed-point values with the
3586 * number of fraction bits given by the
3587 * implementation-dependent constant
3588 * FRAGMENT_INTERPOLATION_OFFSET_BITS"
3590 set_condmod(BRW_CONDITIONAL_L
,
3591 bld
.SEL(offset(src
, bld
, i
), itemp
, brw_imm_d(7)));
3594 const enum opcode opcode
= FS_OPCODE_INTERPOLATE_AT_PER_SLOT_OFFSET
;
3595 emit_pixel_interpolater_send(bld
,
3602 shuffle_from_pln_layout(bld
, dest
, tmp
);
3606 case nir_intrinsic_load_frag_coord
:
3607 emit_fragcoord_interpolation(dest
);
3610 case nir_intrinsic_load_interpolated_input
: {
3611 assert(instr
->src
[0].ssa
&&
3612 instr
->src
[0].ssa
->parent_instr
->type
== nir_instr_type_intrinsic
);
3613 nir_intrinsic_instr
*bary_intrinsic
=
3614 nir_instr_as_intrinsic(instr
->src
[0].ssa
->parent_instr
);
3615 nir_intrinsic_op bary_intrin
= bary_intrinsic
->intrinsic
;
3616 enum glsl_interp_mode interp_mode
=
3617 (enum glsl_interp_mode
) nir_intrinsic_interp_mode(bary_intrinsic
);
3620 if (bary_intrin
== nir_intrinsic_load_barycentric_at_offset
||
3621 bary_intrin
== nir_intrinsic_load_barycentric_at_sample
) {
3622 /* Use the result of the PI message. Because the load_barycentric
3623 * intrinsics return a regular vec2 and we need it in PLN layout, we
3624 * have to do a translation. Fortunately, copy-prop cleans this up
3627 dst_xy
= bld
.vgrf(BRW_REGISTER_TYPE_F
, 2);
3628 shuffle_to_pln_layout(bld
, dst_xy
, get_nir_src(instr
->src
[0]));
3630 /* Use the delta_xy values computed from the payload */
3631 enum brw_barycentric_mode bary
=
3632 brw_barycentric_mode(interp_mode
, bary_intrin
);
3634 dst_xy
= this->delta_xy
[bary
];
3637 for (unsigned int i
= 0; i
< instr
->num_components
; i
++) {
3639 component(interp_reg(nir_intrinsic_base(instr
),
3640 nir_intrinsic_component(instr
) + i
), 0);
3641 interp
.type
= BRW_REGISTER_TYPE_F
;
3642 dest
.type
= BRW_REGISTER_TYPE_F
;
3644 if (devinfo
->gen
< 6 && interp_mode
== INTERP_MODE_SMOOTH
) {
3645 fs_reg tmp
= vgrf(glsl_type::float_type
);
3646 bld
.emit(FS_OPCODE_LINTERP
, tmp
, dst_xy
, interp
);
3647 bld
.MUL(offset(dest
, bld
, i
), tmp
, this->pixel_w
);
3649 bld
.emit(FS_OPCODE_LINTERP
, offset(dest
, bld
, i
), dst_xy
, interp
);
3656 nir_emit_intrinsic(bld
, instr
);
3662 fs_visitor::nir_emit_cs_intrinsic(const fs_builder
&bld
,
3663 nir_intrinsic_instr
*instr
)
3665 assert(stage
== MESA_SHADER_COMPUTE
);
3666 struct brw_cs_prog_data
*cs_prog_data
= brw_cs_prog_data(prog_data
);
3669 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
3670 dest
= get_nir_dest(instr
->dest
);
3672 switch (instr
->intrinsic
) {
3673 case nir_intrinsic_barrier
:
3675 cs_prog_data
->uses_barrier
= true;
3678 case nir_intrinsic_load_subgroup_id
:
3679 bld
.MOV(retype(dest
, BRW_REGISTER_TYPE_UD
), subgroup_id
);
3682 case nir_intrinsic_load_local_invocation_id
:
3683 case nir_intrinsic_load_work_group_id
: {
3684 gl_system_value sv
= nir_system_value_from_intrinsic(instr
->intrinsic
);
3685 fs_reg val
= nir_system_values
[sv
];
3686 assert(val
.file
!= BAD_FILE
);
3687 dest
.type
= val
.type
;
3688 for (unsigned i
= 0; i
< 3; i
++)
3689 bld
.MOV(offset(dest
, bld
, i
), offset(val
, bld
, i
));
3693 case nir_intrinsic_load_num_work_groups
: {
3694 const unsigned surface
=
3695 cs_prog_data
->binding_table
.work_groups_start
;
3697 cs_prog_data
->uses_num_work_groups
= true;
3699 fs_reg srcs
[SURFACE_LOGICAL_NUM_SRCS
];
3700 srcs
[SURFACE_LOGICAL_SRC_SURFACE
] = brw_imm_ud(surface
);
3701 srcs
[SURFACE_LOGICAL_SRC_IMM_DIMS
] = brw_imm_ud(1);
3702 srcs
[SURFACE_LOGICAL_SRC_IMM_ARG
] = brw_imm_ud(1); /* num components */
3704 /* Read the 3 GLuint components of gl_NumWorkGroups */
3705 for (unsigned i
= 0; i
< 3; i
++) {
3706 srcs
[SURFACE_LOGICAL_SRC_ADDRESS
] = brw_imm_ud(i
<< 2);
3707 bld
.emit(SHADER_OPCODE_UNTYPED_SURFACE_READ_LOGICAL
,
3708 offset(dest
, bld
, i
), srcs
, SURFACE_LOGICAL_NUM_SRCS
);
3713 case nir_intrinsic_shared_atomic_add
:
3714 case nir_intrinsic_shared_atomic_imin
:
3715 case nir_intrinsic_shared_atomic_umin
:
3716 case nir_intrinsic_shared_atomic_imax
:
3717 case nir_intrinsic_shared_atomic_umax
:
3718 case nir_intrinsic_shared_atomic_and
:
3719 case nir_intrinsic_shared_atomic_or
:
3720 case nir_intrinsic_shared_atomic_xor
:
3721 case nir_intrinsic_shared_atomic_exchange
:
3722 case nir_intrinsic_shared_atomic_comp_swap
:
3723 nir_emit_shared_atomic(bld
, brw_aop_for_nir_intrinsic(instr
), instr
);
3725 case nir_intrinsic_shared_atomic_fmin
:
3726 case nir_intrinsic_shared_atomic_fmax
:
3727 case nir_intrinsic_shared_atomic_fcomp_swap
:
3728 nir_emit_shared_atomic_float(bld
, brw_aop_for_nir_intrinsic(instr
), instr
);
3731 case nir_intrinsic_load_shared
: {
3732 assert(devinfo
->gen
>= 7);
3733 assert(stage
== MESA_SHADER_COMPUTE
);
3735 const unsigned bit_size
= nir_dest_bit_size(instr
->dest
);
3736 fs_reg srcs
[SURFACE_LOGICAL_NUM_SRCS
];
3737 srcs
[SURFACE_LOGICAL_SRC_SURFACE
] = brw_imm_ud(GEN7_BTI_SLM
);
3738 srcs
[SURFACE_LOGICAL_SRC_ADDRESS
] = get_nir_src(instr
->src
[0]);
3739 srcs
[SURFACE_LOGICAL_SRC_IMM_DIMS
] = brw_imm_ud(1);
3741 /* Make dest unsigned because that's what the temporary will be */
3742 dest
.type
= brw_reg_type_from_bit_size(bit_size
, BRW_REGISTER_TYPE_UD
);
3744 /* Read the vector */
3745 if (nir_intrinsic_align(instr
) >= 4) {
3746 assert(nir_dest_bit_size(instr
->dest
) == 32);
3747 srcs
[SURFACE_LOGICAL_SRC_IMM_ARG
] = brw_imm_ud(instr
->num_components
);
3749 bld
.emit(SHADER_OPCODE_UNTYPED_SURFACE_READ_LOGICAL
,
3750 dest
, srcs
, SURFACE_LOGICAL_NUM_SRCS
);
3751 inst
->size_written
= instr
->num_components
* dispatch_width
* 4;
3753 assert(nir_dest_bit_size(instr
->dest
) <= 32);
3754 assert(nir_dest_num_components(instr
->dest
) == 1);
3755 srcs
[SURFACE_LOGICAL_SRC_IMM_ARG
] = brw_imm_ud(bit_size
);
3757 fs_reg read_result
= bld
.vgrf(BRW_REGISTER_TYPE_UD
);
3758 bld
.emit(SHADER_OPCODE_BYTE_SCATTERED_READ_LOGICAL
,
3759 read_result
, srcs
, SURFACE_LOGICAL_NUM_SRCS
);
3760 bld
.MOV(dest
, subscript(read_result
, dest
.type
, 0));
3765 case nir_intrinsic_store_shared
: {
3766 assert(devinfo
->gen
>= 7);
3767 assert(stage
== MESA_SHADER_COMPUTE
);
3769 const unsigned bit_size
= nir_src_bit_size(instr
->src
[0]);
3770 fs_reg srcs
[SURFACE_LOGICAL_NUM_SRCS
];
3771 srcs
[SURFACE_LOGICAL_SRC_SURFACE
] = brw_imm_ud(GEN7_BTI_SLM
);
3772 srcs
[SURFACE_LOGICAL_SRC_ADDRESS
] = get_nir_src(instr
->src
[1]);
3773 srcs
[SURFACE_LOGICAL_SRC_IMM_DIMS
] = brw_imm_ud(1);
3775 fs_reg data
= get_nir_src(instr
->src
[0]);
3776 data
.type
= brw_reg_type_from_bit_size(bit_size
, BRW_REGISTER_TYPE_UD
);
3778 assert(nir_intrinsic_write_mask(instr
) ==
3779 (1u << instr
->num_components
) - 1);
3780 if (nir_intrinsic_align(instr
) >= 4) {
3781 assert(nir_src_bit_size(instr
->src
[0]) == 32);
3782 assert(nir_src_num_components(instr
->src
[0]) <= 4);
3783 srcs
[SURFACE_LOGICAL_SRC_DATA
] = data
;
3784 srcs
[SURFACE_LOGICAL_SRC_IMM_ARG
] = brw_imm_ud(instr
->num_components
);
3785 bld
.emit(SHADER_OPCODE_UNTYPED_SURFACE_WRITE_LOGICAL
,
3786 fs_reg(), srcs
, SURFACE_LOGICAL_NUM_SRCS
);
3788 assert(nir_src_bit_size(instr
->src
[0]) <= 32);
3789 assert(nir_src_num_components(instr
->src
[0]) == 1);
3790 srcs
[SURFACE_LOGICAL_SRC_IMM_ARG
] = brw_imm_ud(bit_size
);
3792 srcs
[SURFACE_LOGICAL_SRC_DATA
] = bld
.vgrf(BRW_REGISTER_TYPE_UD
);
3793 bld
.MOV(srcs
[SURFACE_LOGICAL_SRC_DATA
], data
);
3795 bld
.emit(SHADER_OPCODE_BYTE_SCATTERED_WRITE_LOGICAL
,
3796 fs_reg(), srcs
, SURFACE_LOGICAL_NUM_SRCS
);
3802 nir_emit_intrinsic(bld
, instr
);
3808 brw_nir_reduction_op_identity(const fs_builder
&bld
,
3809 nir_op op
, brw_reg_type type
)
3811 nir_const_value value
= nir_alu_binop_identity(op
, type_sz(type
) * 8);
3812 switch (type_sz(type
)) {
3814 assert(type
!= BRW_REGISTER_TYPE_HF
);
3815 return retype(brw_imm_uw(value
.u16
), type
);
3817 return retype(brw_imm_ud(value
.u32
), type
);
3819 if (type
== BRW_REGISTER_TYPE_DF
)
3820 return setup_imm_df(bld
, value
.f64
);
3822 return retype(brw_imm_u64(value
.u64
), type
);
3824 unreachable("Invalid type size");
3829 brw_op_for_nir_reduction_op(nir_op op
)
3832 case nir_op_iadd
: return BRW_OPCODE_ADD
;
3833 case nir_op_fadd
: return BRW_OPCODE_ADD
;
3834 case nir_op_imul
: return BRW_OPCODE_MUL
;
3835 case nir_op_fmul
: return BRW_OPCODE_MUL
;
3836 case nir_op_imin
: return BRW_OPCODE_SEL
;
3837 case nir_op_umin
: return BRW_OPCODE_SEL
;
3838 case nir_op_fmin
: return BRW_OPCODE_SEL
;
3839 case nir_op_imax
: return BRW_OPCODE_SEL
;
3840 case nir_op_umax
: return BRW_OPCODE_SEL
;
3841 case nir_op_fmax
: return BRW_OPCODE_SEL
;
3842 case nir_op_iand
: return BRW_OPCODE_AND
;
3843 case nir_op_ior
: return BRW_OPCODE_OR
;
3844 case nir_op_ixor
: return BRW_OPCODE_XOR
;
3846 unreachable("Invalid reduction operation");
3850 static brw_conditional_mod
3851 brw_cond_mod_for_nir_reduction_op(nir_op op
)
3854 case nir_op_iadd
: return BRW_CONDITIONAL_NONE
;
3855 case nir_op_fadd
: return BRW_CONDITIONAL_NONE
;
3856 case nir_op_imul
: return BRW_CONDITIONAL_NONE
;
3857 case nir_op_fmul
: return BRW_CONDITIONAL_NONE
;
3858 case nir_op_imin
: return BRW_CONDITIONAL_L
;
3859 case nir_op_umin
: return BRW_CONDITIONAL_L
;
3860 case nir_op_fmin
: return BRW_CONDITIONAL_L
;
3861 case nir_op_imax
: return BRW_CONDITIONAL_GE
;
3862 case nir_op_umax
: return BRW_CONDITIONAL_GE
;
3863 case nir_op_fmax
: return BRW_CONDITIONAL_GE
;
3864 case nir_op_iand
: return BRW_CONDITIONAL_NONE
;
3865 case nir_op_ior
: return BRW_CONDITIONAL_NONE
;
3866 case nir_op_ixor
: return BRW_CONDITIONAL_NONE
;
3868 unreachable("Invalid reduction operation");
3873 fs_visitor::get_nir_image_intrinsic_image(const brw::fs_builder
&bld
,
3874 nir_intrinsic_instr
*instr
)
3876 fs_reg image
= retype(get_nir_src_imm(instr
->src
[0]), BRW_REGISTER_TYPE_UD
);
3878 if (stage_prog_data
->binding_table
.image_start
> 0) {
3879 if (image
.file
== BRW_IMMEDIATE_VALUE
) {
3880 image
.d
+= stage_prog_data
->binding_table
.image_start
;
3882 bld
.ADD(image
, image
,
3883 brw_imm_d(stage_prog_data
->binding_table
.image_start
));
3887 return bld
.emit_uniformize(image
);
3891 fs_visitor::get_nir_ssbo_intrinsic_index(const brw::fs_builder
&bld
,
3892 nir_intrinsic_instr
*instr
)
3894 /* SSBO stores are weird in that their index is in src[1] */
3895 const unsigned src
= instr
->intrinsic
== nir_intrinsic_store_ssbo
? 1 : 0;
3898 if (nir_src_is_const(instr
->src
[src
])) {
3899 unsigned index
= stage_prog_data
->binding_table
.ssbo_start
+
3900 nir_src_as_uint(instr
->src
[src
]);
3901 surf_index
= brw_imm_ud(index
);
3903 surf_index
= vgrf(glsl_type::uint_type
);
3904 bld
.ADD(surf_index
, get_nir_src(instr
->src
[src
]),
3905 brw_imm_ud(stage_prog_data
->binding_table
.ssbo_start
));
3908 return bld
.emit_uniformize(surf_index
);
3912 image_intrinsic_coord_components(nir_intrinsic_instr
*instr
)
3914 switch (nir_intrinsic_image_dim(instr
)) {
3915 case GLSL_SAMPLER_DIM_1D
:
3916 return 1 + nir_intrinsic_image_array(instr
);
3917 case GLSL_SAMPLER_DIM_2D
:
3918 case GLSL_SAMPLER_DIM_RECT
:
3919 return 2 + nir_intrinsic_image_array(instr
);
3920 case GLSL_SAMPLER_DIM_3D
:
3921 case GLSL_SAMPLER_DIM_CUBE
:
3923 case GLSL_SAMPLER_DIM_BUF
:
3925 case GLSL_SAMPLER_DIM_MS
:
3926 return 2 + nir_intrinsic_image_array(instr
);
3928 unreachable("Invalid image dimension");
3933 fs_visitor::nir_emit_intrinsic(const fs_builder
&bld
, nir_intrinsic_instr
*instr
)
3936 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
3937 dest
= get_nir_dest(instr
->dest
);
3939 switch (instr
->intrinsic
) {
3940 case nir_intrinsic_image_load
:
3941 case nir_intrinsic_image_store
:
3942 case nir_intrinsic_image_atomic_add
:
3943 case nir_intrinsic_image_atomic_imin
:
3944 case nir_intrinsic_image_atomic_umin
:
3945 case nir_intrinsic_image_atomic_imax
:
3946 case nir_intrinsic_image_atomic_umax
:
3947 case nir_intrinsic_image_atomic_and
:
3948 case nir_intrinsic_image_atomic_or
:
3949 case nir_intrinsic_image_atomic_xor
:
3950 case nir_intrinsic_image_atomic_exchange
:
3951 case nir_intrinsic_image_atomic_comp_swap
:
3952 case nir_intrinsic_bindless_image_load
:
3953 case nir_intrinsic_bindless_image_store
:
3954 case nir_intrinsic_bindless_image_atomic_add
:
3955 case nir_intrinsic_bindless_image_atomic_imin
:
3956 case nir_intrinsic_bindless_image_atomic_umin
:
3957 case nir_intrinsic_bindless_image_atomic_imax
:
3958 case nir_intrinsic_bindless_image_atomic_umax
:
3959 case nir_intrinsic_bindless_image_atomic_and
:
3960 case nir_intrinsic_bindless_image_atomic_or
:
3961 case nir_intrinsic_bindless_image_atomic_xor
:
3962 case nir_intrinsic_bindless_image_atomic_exchange
:
3963 case nir_intrinsic_bindless_image_atomic_comp_swap
: {
3964 if (stage
== MESA_SHADER_FRAGMENT
&&
3965 instr
->intrinsic
!= nir_intrinsic_image_load
)
3966 brw_wm_prog_data(prog_data
)->has_side_effects
= true;
3968 /* Get some metadata from the image intrinsic. */
3969 const nir_intrinsic_info
*info
= &nir_intrinsic_infos
[instr
->intrinsic
];
3971 fs_reg srcs
[SURFACE_LOGICAL_NUM_SRCS
];
3973 switch (instr
->intrinsic
) {
3974 case nir_intrinsic_image_load
:
3975 case nir_intrinsic_image_store
:
3976 case nir_intrinsic_image_atomic_add
:
3977 case nir_intrinsic_image_atomic_imin
:
3978 case nir_intrinsic_image_atomic_umin
:
3979 case nir_intrinsic_image_atomic_imax
:
3980 case nir_intrinsic_image_atomic_umax
:
3981 case nir_intrinsic_image_atomic_and
:
3982 case nir_intrinsic_image_atomic_or
:
3983 case nir_intrinsic_image_atomic_xor
:
3984 case nir_intrinsic_image_atomic_exchange
:
3985 case nir_intrinsic_image_atomic_comp_swap
:
3986 srcs
[SURFACE_LOGICAL_SRC_SURFACE
] =
3987 get_nir_image_intrinsic_image(bld
, instr
);
3992 srcs
[SURFACE_LOGICAL_SRC_SURFACE_HANDLE
] =
3993 bld
.emit_uniformize(get_nir_src(instr
->src
[0]));
3997 srcs
[SURFACE_LOGICAL_SRC_ADDRESS
] = get_nir_src(instr
->src
[1]);
3998 srcs
[SURFACE_LOGICAL_SRC_IMM_DIMS
] =
3999 brw_imm_ud(image_intrinsic_coord_components(instr
));
4001 /* Emit an image load, store or atomic op. */
4002 if (instr
->intrinsic
== nir_intrinsic_image_load
||
4003 instr
->intrinsic
== nir_intrinsic_bindless_image_load
) {
4004 srcs
[SURFACE_LOGICAL_SRC_IMM_ARG
] = brw_imm_ud(instr
->num_components
);
4006 bld
.emit(SHADER_OPCODE_TYPED_SURFACE_READ_LOGICAL
,
4007 dest
, srcs
, SURFACE_LOGICAL_NUM_SRCS
);
4008 inst
->size_written
= instr
->num_components
* dispatch_width
* 4;
4009 } else if (instr
->intrinsic
== nir_intrinsic_image_store
||
4010 instr
->intrinsic
== nir_intrinsic_bindless_image_store
) {
4011 srcs
[SURFACE_LOGICAL_SRC_IMM_ARG
] = brw_imm_ud(instr
->num_components
);
4012 srcs
[SURFACE_LOGICAL_SRC_DATA
] = get_nir_src(instr
->src
[3]);
4013 bld
.emit(SHADER_OPCODE_TYPED_SURFACE_WRITE_LOGICAL
,
4014 fs_reg(), srcs
, SURFACE_LOGICAL_NUM_SRCS
);
4016 unsigned num_srcs
= info
->num_srcs
;
4017 int op
= brw_aop_for_nir_intrinsic(instr
);
4018 if (op
== BRW_AOP_INC
|| op
== BRW_AOP_DEC
) {
4019 assert(num_srcs
== 4);
4023 srcs
[SURFACE_LOGICAL_SRC_IMM_ARG
] = brw_imm_ud(op
);
4027 data
= get_nir_src(instr
->src
[3]);
4028 if (num_srcs
>= 5) {
4029 fs_reg tmp
= bld
.vgrf(data
.type
, 2);
4030 fs_reg sources
[2] = { data
, get_nir_src(instr
->src
[4]) };
4031 bld
.LOAD_PAYLOAD(tmp
, sources
, 2, 0);
4034 srcs
[SURFACE_LOGICAL_SRC_DATA
] = data
;
4036 bld
.emit(SHADER_OPCODE_TYPED_ATOMIC_LOGICAL
,
4037 dest
, srcs
, SURFACE_LOGICAL_NUM_SRCS
);
4042 case nir_intrinsic_image_size
:
4043 case nir_intrinsic_bindless_image_size
: {
4044 /* Unlike the [un]typed load and store opcodes, the TXS that this turns
4045 * into will handle the binding table index for us in the geneerator.
4046 * Incidentally, this means that we can handle bindless with exactly the
4049 fs_reg image
= retype(get_nir_src_imm(instr
->src
[0]),
4050 BRW_REGISTER_TYPE_UD
);
4051 image
= bld
.emit_uniformize(image
);
4053 fs_reg srcs
[TEX_LOGICAL_NUM_SRCS
];
4054 if (instr
->intrinsic
== nir_intrinsic_image_size
)
4055 srcs
[TEX_LOGICAL_SRC_SURFACE
] = image
;
4057 srcs
[TEX_LOGICAL_SRC_SURFACE_HANDLE
] = image
;
4058 srcs
[TEX_LOGICAL_SRC_SAMPLER
] = brw_imm_d(0);
4059 srcs
[TEX_LOGICAL_SRC_COORD_COMPONENTS
] = brw_imm_d(0);
4060 srcs
[TEX_LOGICAL_SRC_GRAD_COMPONENTS
] = brw_imm_d(0);
4062 /* Since the image size is always uniform, we can just emit a SIMD8
4063 * query instruction and splat the result out.
4065 const fs_builder ubld
= bld
.exec_all().group(8, 0);
4067 fs_reg tmp
= ubld
.vgrf(BRW_REGISTER_TYPE_UD
, 4);
4068 fs_inst
*inst
= ubld
.emit(SHADER_OPCODE_IMAGE_SIZE_LOGICAL
,
4069 tmp
, srcs
, ARRAY_SIZE(srcs
));
4070 inst
->size_written
= 4 * REG_SIZE
;
4072 for (unsigned c
= 0; c
< instr
->dest
.ssa
.num_components
; ++c
) {
4073 if (c
== 2 && nir_intrinsic_image_dim(instr
) == GLSL_SAMPLER_DIM_CUBE
) {
4074 bld
.emit(SHADER_OPCODE_INT_QUOTIENT
,
4075 offset(retype(dest
, tmp
.type
), bld
, c
),
4076 component(offset(tmp
, ubld
, c
), 0), brw_imm_ud(6));
4078 bld
.MOV(offset(retype(dest
, tmp
.type
), bld
, c
),
4079 component(offset(tmp
, ubld
, c
), 0));
4085 case nir_intrinsic_image_load_raw_intel
: {
4086 fs_reg srcs
[SURFACE_LOGICAL_NUM_SRCS
];
4087 srcs
[SURFACE_LOGICAL_SRC_SURFACE
] =
4088 get_nir_image_intrinsic_image(bld
, instr
);
4089 srcs
[SURFACE_LOGICAL_SRC_ADDRESS
] = get_nir_src(instr
->src
[1]);
4090 srcs
[SURFACE_LOGICAL_SRC_IMM_DIMS
] = brw_imm_ud(1);
4091 srcs
[SURFACE_LOGICAL_SRC_IMM_ARG
] = brw_imm_ud(instr
->num_components
);
4094 bld
.emit(SHADER_OPCODE_UNTYPED_SURFACE_READ_LOGICAL
,
4095 dest
, srcs
, SURFACE_LOGICAL_NUM_SRCS
);
4096 inst
->size_written
= instr
->num_components
* dispatch_width
* 4;
4100 case nir_intrinsic_image_store_raw_intel
: {
4101 if (stage
== MESA_SHADER_FRAGMENT
)
4102 brw_wm_prog_data(prog_data
)->has_side_effects
= true;
4104 fs_reg srcs
[SURFACE_LOGICAL_NUM_SRCS
];
4105 srcs
[SURFACE_LOGICAL_SRC_SURFACE
] =
4106 get_nir_image_intrinsic_image(bld
, instr
);
4107 srcs
[SURFACE_LOGICAL_SRC_ADDRESS
] = get_nir_src(instr
->src
[1]);
4108 srcs
[SURFACE_LOGICAL_SRC_DATA
] = get_nir_src(instr
->src
[2]);
4109 srcs
[SURFACE_LOGICAL_SRC_IMM_DIMS
] = brw_imm_ud(1);
4110 srcs
[SURFACE_LOGICAL_SRC_IMM_ARG
] = brw_imm_ud(instr
->num_components
);
4112 bld
.emit(SHADER_OPCODE_UNTYPED_SURFACE_WRITE_LOGICAL
,
4113 fs_reg(), srcs
, SURFACE_LOGICAL_NUM_SRCS
);
4117 case nir_intrinsic_group_memory_barrier
:
4118 case nir_intrinsic_memory_barrier_shared
:
4119 case nir_intrinsic_memory_barrier_atomic_counter
:
4120 case nir_intrinsic_memory_barrier_buffer
:
4121 case nir_intrinsic_memory_barrier_image
:
4122 case nir_intrinsic_memory_barrier
: {
4123 bool l3_fence
, slm_fence
;
4124 if (devinfo
->gen
>= 11) {
4125 l3_fence
= instr
->intrinsic
!= nir_intrinsic_memory_barrier_shared
;
4126 slm_fence
= instr
->intrinsic
== nir_intrinsic_group_memory_barrier
||
4127 instr
->intrinsic
== nir_intrinsic_memory_barrier
||
4128 instr
->intrinsic
== nir_intrinsic_memory_barrier_shared
;
4130 /* Prior to gen11, we only have one kind of fence. */
4135 /* Be conservative in Gen11+ and always stall in a fence. Since there
4136 * are two different fences, and shader might want to synchronize
4139 * TODO: Improve NIR so that scope and visibility information for the
4140 * barriers is available here to make a better decision.
4142 * TODO: When emitting more than one fence, it might help emit all
4143 * the fences first and then generate the stall moves.
4145 const bool stall
= devinfo
->gen
>= 11;
4147 const fs_builder ubld
= bld
.group(8, 0);
4148 const fs_reg tmp
= ubld
.vgrf(BRW_REGISTER_TYPE_UD
, 2);
4151 ubld
.emit(SHADER_OPCODE_MEMORY_FENCE
, tmp
,
4152 brw_vec8_grf(0, 0), brw_imm_ud(stall
),
4153 /* bti */ brw_imm_ud(0))
4154 ->size_written
= 2 * REG_SIZE
;
4158 ubld
.emit(SHADER_OPCODE_MEMORY_FENCE
, tmp
,
4159 brw_vec8_grf(0, 0), brw_imm_ud(stall
),
4160 brw_imm_ud(GEN7_BTI_SLM
))
4161 ->size_written
= 2 * REG_SIZE
;
4167 case nir_intrinsic_shader_clock
: {
4168 /* We cannot do anything if there is an event, so ignore it for now */
4169 const fs_reg shader_clock
= get_timestamp(bld
);
4170 const fs_reg srcs
[] = { component(shader_clock
, 0),
4171 component(shader_clock
, 1) };
4172 bld
.LOAD_PAYLOAD(dest
, srcs
, ARRAY_SIZE(srcs
), 0);
4176 case nir_intrinsic_image_samples
:
4177 /* The driver does not support multi-sampled images. */
4178 bld
.MOV(retype(dest
, BRW_REGISTER_TYPE_D
), brw_imm_d(1));
4181 case nir_intrinsic_load_uniform
: {
4182 /* Offsets are in bytes but they should always aligned to
4185 assert(instr
->const_index
[0] % 4 == 0 ||
4186 instr
->const_index
[0] % type_sz(dest
.type
) == 0);
4188 fs_reg
src(UNIFORM
, instr
->const_index
[0] / 4, dest
.type
);
4190 if (nir_src_is_const(instr
->src
[0])) {
4191 unsigned load_offset
= nir_src_as_uint(instr
->src
[0]);
4192 assert(load_offset
% type_sz(dest
.type
) == 0);
4193 /* For 16-bit types we add the module of the const_index[0]
4194 * offset to access to not 32-bit aligned element
4196 src
.offset
= load_offset
+ instr
->const_index
[0] % 4;
4198 for (unsigned j
= 0; j
< instr
->num_components
; j
++) {
4199 bld
.MOV(offset(dest
, bld
, j
), offset(src
, bld
, j
));
4202 fs_reg indirect
= retype(get_nir_src(instr
->src
[0]),
4203 BRW_REGISTER_TYPE_UD
);
4205 /* We need to pass a size to the MOV_INDIRECT but we don't want it to
4206 * go past the end of the uniform. In order to keep the n'th
4207 * component from running past, we subtract off the size of all but
4208 * one component of the vector.
4210 assert(instr
->const_index
[1] >=
4211 instr
->num_components
* (int) type_sz(dest
.type
));
4212 unsigned read_size
= instr
->const_index
[1] -
4213 (instr
->num_components
- 1) * type_sz(dest
.type
);
4215 bool supports_64bit_indirects
=
4216 !devinfo
->is_cherryview
&& !gen_device_info_is_9lp(devinfo
);
4218 if (type_sz(dest
.type
) != 8 || supports_64bit_indirects
) {
4219 for (unsigned j
= 0; j
< instr
->num_components
; j
++) {
4220 bld
.emit(SHADER_OPCODE_MOV_INDIRECT
,
4221 offset(dest
, bld
, j
), offset(src
, bld
, j
),
4222 indirect
, brw_imm_ud(read_size
));
4225 const unsigned num_mov_indirects
=
4226 type_sz(dest
.type
) / type_sz(BRW_REGISTER_TYPE_UD
);
4227 /* We read a little bit less per MOV INDIRECT, as they are now
4228 * 32-bits ones instead of 64-bit. Fix read_size then.
4230 const unsigned read_size_32bit
= read_size
-
4231 (num_mov_indirects
- 1) * type_sz(BRW_REGISTER_TYPE_UD
);
4232 for (unsigned j
= 0; j
< instr
->num_components
; j
++) {
4233 for (unsigned i
= 0; i
< num_mov_indirects
; i
++) {
4234 bld
.emit(SHADER_OPCODE_MOV_INDIRECT
,
4235 subscript(offset(dest
, bld
, j
), BRW_REGISTER_TYPE_UD
, i
),
4236 subscript(offset(src
, bld
, j
), BRW_REGISTER_TYPE_UD
, i
),
4237 indirect
, brw_imm_ud(read_size_32bit
));
4245 case nir_intrinsic_load_ubo
: {
4247 if (nir_src_is_const(instr
->src
[0])) {
4248 const unsigned index
= stage_prog_data
->binding_table
.ubo_start
+
4249 nir_src_as_uint(instr
->src
[0]);
4250 surf_index
= brw_imm_ud(index
);
4252 /* The block index is not a constant. Evaluate the index expression
4253 * per-channel and add the base UBO index; we have to select a value
4254 * from any live channel.
4256 surf_index
= vgrf(glsl_type::uint_type
);
4257 bld
.ADD(surf_index
, get_nir_src(instr
->src
[0]),
4258 brw_imm_ud(stage_prog_data
->binding_table
.ubo_start
));
4259 surf_index
= bld
.emit_uniformize(surf_index
);
4262 if (!nir_src_is_const(instr
->src
[1])) {
4263 fs_reg base_offset
= retype(get_nir_src(instr
->src
[1]),
4264 BRW_REGISTER_TYPE_UD
);
4266 for (int i
= 0; i
< instr
->num_components
; i
++)
4267 VARYING_PULL_CONSTANT_LOAD(bld
, offset(dest
, bld
, i
), surf_index
,
4268 base_offset
, i
* type_sz(dest
.type
));
4270 /* Even if we are loading doubles, a pull constant load will load
4271 * a 32-bit vec4, so should only reserve vgrf space for that. If we
4272 * need to load a full dvec4 we will have to emit 2 loads. This is
4273 * similar to demote_pull_constants(), except that in that case we
4274 * see individual accesses to each component of the vector and then
4275 * we let CSE deal with duplicate loads. Here we see a vector access
4276 * and we have to split it if necessary.
4278 const unsigned type_size
= type_sz(dest
.type
);
4279 const unsigned load_offset
= nir_src_as_uint(instr
->src
[1]);
4281 /* See if we've selected this as a push constant candidate */
4282 if (nir_src_is_const(instr
->src
[0])) {
4283 const unsigned ubo_block
= nir_src_as_uint(instr
->src
[0]);
4284 const unsigned offset_256b
= load_offset
/ 32;
4287 for (int i
= 0; i
< 4; i
++) {
4288 const struct brw_ubo_range
*range
= &prog_data
->ubo_ranges
[i
];
4289 if (range
->block
== ubo_block
&&
4290 offset_256b
>= range
->start
&&
4291 offset_256b
< range
->start
+ range
->length
) {
4293 push_reg
= fs_reg(UNIFORM
, UBO_START
+ i
, dest
.type
);
4294 push_reg
.offset
= load_offset
- 32 * range
->start
;
4299 if (push_reg
.file
!= BAD_FILE
) {
4300 for (unsigned i
= 0; i
< instr
->num_components
; i
++) {
4301 bld
.MOV(offset(dest
, bld
, i
),
4302 byte_offset(push_reg
, i
* type_size
));
4308 const unsigned block_sz
= 64; /* Fetch one cacheline at a time. */
4309 const fs_builder ubld
= bld
.exec_all().group(block_sz
/ 4, 0);
4310 const fs_reg packed_consts
= ubld
.vgrf(BRW_REGISTER_TYPE_UD
);
4312 for (unsigned c
= 0; c
< instr
->num_components
;) {
4313 const unsigned base
= load_offset
+ c
* type_size
;
4314 /* Number of usable components in the next block-aligned load. */
4315 const unsigned count
= MIN2(instr
->num_components
- c
,
4316 (block_sz
- base
% block_sz
) / type_size
);
4318 ubld
.emit(FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD
,
4319 packed_consts
, surf_index
,
4320 brw_imm_ud(base
& ~(block_sz
- 1)));
4322 const fs_reg consts
=
4323 retype(byte_offset(packed_consts
, base
& (block_sz
- 1)),
4326 for (unsigned d
= 0; d
< count
; d
++)
4327 bld
.MOV(offset(dest
, bld
, c
+ d
), component(consts
, d
));
4335 case nir_intrinsic_load_global
: {
4336 assert(devinfo
->gen
>= 8);
4338 if (nir_intrinsic_align(instr
) >= 4) {
4339 assert(nir_dest_bit_size(instr
->dest
) == 32);
4340 fs_inst
*inst
= bld
.emit(SHADER_OPCODE_A64_UNTYPED_READ_LOGICAL
,
4342 get_nir_src(instr
->src
[0]), /* Address */
4343 fs_reg(), /* No source data */
4344 brw_imm_ud(instr
->num_components
));
4345 inst
->size_written
= instr
->num_components
*
4346 inst
->dst
.component_size(inst
->exec_size
);
4348 const unsigned bit_size
= nir_dest_bit_size(instr
->dest
);
4349 assert(bit_size
<= 32);
4350 assert(nir_dest_num_components(instr
->dest
) == 1);
4351 fs_reg tmp
= bld
.vgrf(BRW_REGISTER_TYPE_UD
);
4352 bld
.emit(SHADER_OPCODE_A64_BYTE_SCATTERED_READ_LOGICAL
,
4354 get_nir_src(instr
->src
[0]), /* Address */
4355 fs_reg(), /* No source data */
4356 brw_imm_ud(bit_size
));
4357 bld
.MOV(dest
, subscript(tmp
, dest
.type
, 0));
4362 case nir_intrinsic_store_global
:
4363 assert(devinfo
->gen
>= 8);
4365 if (stage
== MESA_SHADER_FRAGMENT
)
4366 brw_wm_prog_data(prog_data
)->has_side_effects
= true;
4368 if (nir_intrinsic_align(instr
) >= 4) {
4369 assert(nir_src_bit_size(instr
->src
[0]) == 32);
4370 bld
.emit(SHADER_OPCODE_A64_UNTYPED_WRITE_LOGICAL
,
4372 get_nir_src(instr
->src
[1]), /* Address */
4373 get_nir_src(instr
->src
[0]), /* Data */
4374 brw_imm_ud(instr
->num_components
));
4376 const unsigned bit_size
= nir_src_bit_size(instr
->src
[0]);
4377 assert(bit_size
<= 32);
4378 assert(nir_src_num_components(instr
->src
[0]) == 1);
4379 brw_reg_type data_type
=
4380 brw_reg_type_from_bit_size(bit_size
, BRW_REGISTER_TYPE_UD
);
4381 fs_reg tmp
= bld
.vgrf(BRW_REGISTER_TYPE_UD
);
4382 bld
.MOV(tmp
, retype(get_nir_src(instr
->src
[0]), data_type
));
4383 bld
.emit(SHADER_OPCODE_A64_BYTE_SCATTERED_WRITE_LOGICAL
,
4385 get_nir_src(instr
->src
[1]), /* Address */
4387 brw_imm_ud(nir_src_bit_size(instr
->src
[0])));
4391 case nir_intrinsic_global_atomic_add
:
4392 case nir_intrinsic_global_atomic_imin
:
4393 case nir_intrinsic_global_atomic_umin
:
4394 case nir_intrinsic_global_atomic_imax
:
4395 case nir_intrinsic_global_atomic_umax
:
4396 case nir_intrinsic_global_atomic_and
:
4397 case nir_intrinsic_global_atomic_or
:
4398 case nir_intrinsic_global_atomic_xor
:
4399 case nir_intrinsic_global_atomic_exchange
:
4400 case nir_intrinsic_global_atomic_comp_swap
:
4401 nir_emit_global_atomic(bld
, brw_aop_for_nir_intrinsic(instr
), instr
);
4403 case nir_intrinsic_global_atomic_fmin
:
4404 case nir_intrinsic_global_atomic_fmax
:
4405 case nir_intrinsic_global_atomic_fcomp_swap
:
4406 nir_emit_global_atomic_float(bld
, brw_aop_for_nir_intrinsic(instr
), instr
);
4409 case nir_intrinsic_load_ssbo
: {
4410 assert(devinfo
->gen
>= 7);
4412 const unsigned bit_size
= nir_dest_bit_size(instr
->dest
);
4413 fs_reg srcs
[SURFACE_LOGICAL_NUM_SRCS
];
4414 srcs
[SURFACE_LOGICAL_SRC_SURFACE
] =
4415 get_nir_ssbo_intrinsic_index(bld
, instr
);
4416 srcs
[SURFACE_LOGICAL_SRC_ADDRESS
] = get_nir_src(instr
->src
[1]);
4417 srcs
[SURFACE_LOGICAL_SRC_IMM_DIMS
] = brw_imm_ud(1);
4419 /* Make dest unsigned because that's what the temporary will be */
4420 dest
.type
= brw_reg_type_from_bit_size(bit_size
, BRW_REGISTER_TYPE_UD
);
4422 /* Read the vector */
4423 if (nir_intrinsic_align(instr
) >= 4) {
4424 assert(nir_dest_bit_size(instr
->dest
) == 32);
4425 srcs
[SURFACE_LOGICAL_SRC_IMM_ARG
] = brw_imm_ud(instr
->num_components
);
4427 bld
.emit(SHADER_OPCODE_UNTYPED_SURFACE_READ_LOGICAL
,
4428 dest
, srcs
, SURFACE_LOGICAL_NUM_SRCS
);
4429 inst
->size_written
= instr
->num_components
* dispatch_width
* 4;
4431 assert(nir_dest_bit_size(instr
->dest
) <= 32);
4432 assert(nir_dest_num_components(instr
->dest
) == 1);
4433 srcs
[SURFACE_LOGICAL_SRC_IMM_ARG
] = brw_imm_ud(bit_size
);
4435 fs_reg read_result
= bld
.vgrf(BRW_REGISTER_TYPE_UD
);
4436 bld
.emit(SHADER_OPCODE_BYTE_SCATTERED_READ_LOGICAL
,
4437 read_result
, srcs
, SURFACE_LOGICAL_NUM_SRCS
);
4438 bld
.MOV(dest
, subscript(read_result
, dest
.type
, 0));
4443 case nir_intrinsic_store_ssbo
: {
4444 assert(devinfo
->gen
>= 7);
4446 if (stage
== MESA_SHADER_FRAGMENT
)
4447 brw_wm_prog_data(prog_data
)->has_side_effects
= true;
4449 const unsigned bit_size
= nir_src_bit_size(instr
->src
[0]);
4450 fs_reg srcs
[SURFACE_LOGICAL_NUM_SRCS
];
4451 srcs
[SURFACE_LOGICAL_SRC_SURFACE
] =
4452 get_nir_ssbo_intrinsic_index(bld
, instr
);
4453 srcs
[SURFACE_LOGICAL_SRC_ADDRESS
] = get_nir_src(instr
->src
[2]);
4454 srcs
[SURFACE_LOGICAL_SRC_IMM_DIMS
] = brw_imm_ud(1);
4456 fs_reg data
= get_nir_src(instr
->src
[0]);
4457 data
.type
= brw_reg_type_from_bit_size(bit_size
, BRW_REGISTER_TYPE_UD
);
4459 assert(nir_intrinsic_write_mask(instr
) ==
4460 (1u << instr
->num_components
) - 1);
4461 if (nir_intrinsic_align(instr
) >= 4) {
4462 assert(nir_src_bit_size(instr
->src
[0]) == 32);
4463 assert(nir_src_num_components(instr
->src
[0]) <= 4);
4464 srcs
[SURFACE_LOGICAL_SRC_DATA
] = data
;
4465 srcs
[SURFACE_LOGICAL_SRC_IMM_ARG
] = brw_imm_ud(instr
->num_components
);
4466 bld
.emit(SHADER_OPCODE_UNTYPED_SURFACE_WRITE_LOGICAL
,
4467 fs_reg(), srcs
, SURFACE_LOGICAL_NUM_SRCS
);
4469 assert(nir_src_bit_size(instr
->src
[0]) <= 32);
4470 assert(nir_src_num_components(instr
->src
[0]) == 1);
4471 srcs
[SURFACE_LOGICAL_SRC_IMM_ARG
] = brw_imm_ud(bit_size
);
4473 srcs
[SURFACE_LOGICAL_SRC_DATA
] = bld
.vgrf(BRW_REGISTER_TYPE_UD
);
4474 bld
.MOV(srcs
[SURFACE_LOGICAL_SRC_DATA
], data
);
4476 bld
.emit(SHADER_OPCODE_BYTE_SCATTERED_WRITE_LOGICAL
,
4477 fs_reg(), srcs
, SURFACE_LOGICAL_NUM_SRCS
);
4482 case nir_intrinsic_store_output
: {
4483 assert(nir_src_bit_size(instr
->src
[0]) == 32);
4484 fs_reg src
= get_nir_src(instr
->src
[0]);
4486 unsigned store_offset
= nir_src_as_uint(instr
->src
[1]);
4487 unsigned num_components
= instr
->num_components
;
4488 unsigned first_component
= nir_intrinsic_component(instr
);
4490 fs_reg new_dest
= retype(offset(outputs
[instr
->const_index
[0]], bld
,
4491 4 * store_offset
), src
.type
);
4492 for (unsigned j
= 0; j
< num_components
; j
++) {
4493 bld
.MOV(offset(new_dest
, bld
, j
+ first_component
),
4494 offset(src
, bld
, j
));
4499 case nir_intrinsic_ssbo_atomic_add
:
4500 case nir_intrinsic_ssbo_atomic_imin
:
4501 case nir_intrinsic_ssbo_atomic_umin
:
4502 case nir_intrinsic_ssbo_atomic_imax
:
4503 case nir_intrinsic_ssbo_atomic_umax
:
4504 case nir_intrinsic_ssbo_atomic_and
:
4505 case nir_intrinsic_ssbo_atomic_or
:
4506 case nir_intrinsic_ssbo_atomic_xor
:
4507 case nir_intrinsic_ssbo_atomic_exchange
:
4508 case nir_intrinsic_ssbo_atomic_comp_swap
:
4509 nir_emit_ssbo_atomic(bld
, brw_aop_for_nir_intrinsic(instr
), instr
);
4511 case nir_intrinsic_ssbo_atomic_fmin
:
4512 case nir_intrinsic_ssbo_atomic_fmax
:
4513 case nir_intrinsic_ssbo_atomic_fcomp_swap
:
4514 nir_emit_ssbo_atomic_float(bld
, brw_aop_for_nir_intrinsic(instr
), instr
);
4517 case nir_intrinsic_get_buffer_size
: {
4518 assert(nir_src_num_components(instr
->src
[0]) == 1);
4519 unsigned ssbo_index
= nir_src_is_const(instr
->src
[0]) ?
4520 nir_src_as_uint(instr
->src
[0]) : 0;
4522 /* A resinfo's sampler message is used to get the buffer size. The
4523 * SIMD8's writeback message consists of four registers and SIMD16's
4524 * writeback message consists of 8 destination registers (two per each
4525 * component). Because we are only interested on the first channel of
4526 * the first returned component, where resinfo returns the buffer size
4527 * for SURFTYPE_BUFFER, we can just use the SIMD8 variant regardless of
4528 * the dispatch width.
4530 const fs_builder ubld
= bld
.exec_all().group(8, 0);
4531 fs_reg src_payload
= ubld
.vgrf(BRW_REGISTER_TYPE_UD
);
4532 fs_reg ret_payload
= ubld
.vgrf(BRW_REGISTER_TYPE_UD
, 4);
4535 ubld
.MOV(src_payload
, brw_imm_d(0));
4537 const unsigned index
= prog_data
->binding_table
.ssbo_start
+ ssbo_index
;
4538 fs_inst
*inst
= ubld
.emit(SHADER_OPCODE_GET_BUFFER_SIZE
, ret_payload
,
4539 src_payload
, brw_imm_ud(index
));
4540 inst
->header_size
= 0;
4542 inst
->size_written
= 4 * REG_SIZE
;
4544 /* SKL PRM, vol07, 3D Media GPGPU Engine, Bounds Checking and Faulting:
4546 * "Out-of-bounds checking is always performed at a DWord granularity. If
4547 * any part of the DWord is out-of-bounds then the whole DWord is
4548 * considered out-of-bounds."
4550 * This implies that types with size smaller than 4-bytes need to be
4551 * padded if they don't complete the last dword of the buffer. But as we
4552 * need to maintain the original size we need to reverse the padding
4553 * calculation to return the correct size to know the number of elements
4554 * of an unsized array. As we stored in the last two bits of the surface
4555 * size the needed padding for the buffer, we calculate here the
4556 * original buffer_size reversing the surface_size calculation:
4558 * surface_size = isl_align(buffer_size, 4) +
4559 * (isl_align(buffer_size) - buffer_size)
4561 * buffer_size = surface_size & ~3 - surface_size & 3
4564 fs_reg size_aligned4
= ubld
.vgrf(BRW_REGISTER_TYPE_UD
);
4565 fs_reg size_padding
= ubld
.vgrf(BRW_REGISTER_TYPE_UD
);
4566 fs_reg buffer_size
= ubld
.vgrf(BRW_REGISTER_TYPE_UD
);
4568 ubld
.AND(size_padding
, ret_payload
, brw_imm_ud(3));
4569 ubld
.AND(size_aligned4
, ret_payload
, brw_imm_ud(~3));
4570 ubld
.ADD(buffer_size
, size_aligned4
, negate(size_padding
));
4572 bld
.MOV(retype(dest
, ret_payload
.type
), component(buffer_size
, 0));
4576 case nir_intrinsic_load_subgroup_size
:
4577 /* This should only happen for fragment shaders because every other case
4578 * is lowered in NIR so we can optimize on it.
4580 assert(stage
== MESA_SHADER_FRAGMENT
);
4581 bld
.MOV(retype(dest
, BRW_REGISTER_TYPE_D
), brw_imm_d(dispatch_width
));
4584 case nir_intrinsic_load_subgroup_invocation
:
4585 bld
.MOV(retype(dest
, BRW_REGISTER_TYPE_D
),
4586 nir_system_values
[SYSTEM_VALUE_SUBGROUP_INVOCATION
]);
4589 case nir_intrinsic_load_subgroup_eq_mask
:
4590 case nir_intrinsic_load_subgroup_ge_mask
:
4591 case nir_intrinsic_load_subgroup_gt_mask
:
4592 case nir_intrinsic_load_subgroup_le_mask
:
4593 case nir_intrinsic_load_subgroup_lt_mask
:
4594 unreachable("not reached");
4596 case nir_intrinsic_vote_any
: {
4597 const fs_builder ubld
= bld
.exec_all().group(1, 0);
4599 /* The any/all predicates do not consider channel enables. To prevent
4600 * dead channels from affecting the result, we initialize the flag with
4601 * with the identity value for the logical operation.
4603 if (dispatch_width
== 32) {
4604 /* For SIMD32, we use a UD type so we fill both f0.0 and f0.1. */
4605 ubld
.MOV(retype(brw_flag_reg(0, 0), BRW_REGISTER_TYPE_UD
),
4608 ubld
.MOV(brw_flag_reg(0, 0), brw_imm_uw(0));
4610 bld
.CMP(bld
.null_reg_d(), get_nir_src(instr
->src
[0]), brw_imm_d(0), BRW_CONDITIONAL_NZ
);
4612 /* For some reason, the any/all predicates don't work properly with
4613 * SIMD32. In particular, it appears that a SEL with a QtrCtrl of 2H
4614 * doesn't read the correct subset of the flag register and you end up
4615 * getting garbage in the second half. Work around this by using a pair
4616 * of 1-wide MOVs and scattering the result.
4618 fs_reg res1
= ubld
.vgrf(BRW_REGISTER_TYPE_D
);
4619 ubld
.MOV(res1
, brw_imm_d(0));
4620 set_predicate(dispatch_width
== 8 ? BRW_PREDICATE_ALIGN1_ANY8H
:
4621 dispatch_width
== 16 ? BRW_PREDICATE_ALIGN1_ANY16H
:
4622 BRW_PREDICATE_ALIGN1_ANY32H
,
4623 ubld
.MOV(res1
, brw_imm_d(-1)));
4625 bld
.MOV(retype(dest
, BRW_REGISTER_TYPE_D
), component(res1
, 0));
4628 case nir_intrinsic_vote_all
: {
4629 const fs_builder ubld
= bld
.exec_all().group(1, 0);
4631 /* The any/all predicates do not consider channel enables. To prevent
4632 * dead channels from affecting the result, we initialize the flag with
4633 * with the identity value for the logical operation.
4635 if (dispatch_width
== 32) {
4636 /* For SIMD32, we use a UD type so we fill both f0.0 and f0.1. */
4637 ubld
.MOV(retype(brw_flag_reg(0, 0), BRW_REGISTER_TYPE_UD
),
4638 brw_imm_ud(0xffffffff));
4640 ubld
.MOV(brw_flag_reg(0, 0), brw_imm_uw(0xffff));
4642 bld
.CMP(bld
.null_reg_d(), get_nir_src(instr
->src
[0]), brw_imm_d(0), BRW_CONDITIONAL_NZ
);
4644 /* For some reason, the any/all predicates don't work properly with
4645 * SIMD32. In particular, it appears that a SEL with a QtrCtrl of 2H
4646 * doesn't read the correct subset of the flag register and you end up
4647 * getting garbage in the second half. Work around this by using a pair
4648 * of 1-wide MOVs and scattering the result.
4650 fs_reg res1
= ubld
.vgrf(BRW_REGISTER_TYPE_D
);
4651 ubld
.MOV(res1
, brw_imm_d(0));
4652 set_predicate(dispatch_width
== 8 ? BRW_PREDICATE_ALIGN1_ALL8H
:
4653 dispatch_width
== 16 ? BRW_PREDICATE_ALIGN1_ALL16H
:
4654 BRW_PREDICATE_ALIGN1_ALL32H
,
4655 ubld
.MOV(res1
, brw_imm_d(-1)));
4657 bld
.MOV(retype(dest
, BRW_REGISTER_TYPE_D
), component(res1
, 0));
4660 case nir_intrinsic_vote_feq
:
4661 case nir_intrinsic_vote_ieq
: {
4662 fs_reg value
= get_nir_src(instr
->src
[0]);
4663 if (instr
->intrinsic
== nir_intrinsic_vote_feq
) {
4664 const unsigned bit_size
= nir_src_bit_size(instr
->src
[0]);
4665 value
.type
= bit_size
== 8 ? BRW_REGISTER_TYPE_B
:
4666 brw_reg_type_from_bit_size(bit_size
, BRW_REGISTER_TYPE_F
);
4669 fs_reg uniformized
= bld
.emit_uniformize(value
);
4670 const fs_builder ubld
= bld
.exec_all().group(1, 0);
4672 /* The any/all predicates do not consider channel enables. To prevent
4673 * dead channels from affecting the result, we initialize the flag with
4674 * with the identity value for the logical operation.
4676 if (dispatch_width
== 32) {
4677 /* For SIMD32, we use a UD type so we fill both f0.0 and f0.1. */
4678 ubld
.MOV(retype(brw_flag_reg(0, 0), BRW_REGISTER_TYPE_UD
),
4679 brw_imm_ud(0xffffffff));
4681 ubld
.MOV(brw_flag_reg(0, 0), brw_imm_uw(0xffff));
4683 bld
.CMP(bld
.null_reg_d(), value
, uniformized
, BRW_CONDITIONAL_Z
);
4685 /* For some reason, the any/all predicates don't work properly with
4686 * SIMD32. In particular, it appears that a SEL with a QtrCtrl of 2H
4687 * doesn't read the correct subset of the flag register and you end up
4688 * getting garbage in the second half. Work around this by using a pair
4689 * of 1-wide MOVs and scattering the result.
4691 fs_reg res1
= ubld
.vgrf(BRW_REGISTER_TYPE_D
);
4692 ubld
.MOV(res1
, brw_imm_d(0));
4693 set_predicate(dispatch_width
== 8 ? BRW_PREDICATE_ALIGN1_ALL8H
:
4694 dispatch_width
== 16 ? BRW_PREDICATE_ALIGN1_ALL16H
:
4695 BRW_PREDICATE_ALIGN1_ALL32H
,
4696 ubld
.MOV(res1
, brw_imm_d(-1)));
4698 bld
.MOV(retype(dest
, BRW_REGISTER_TYPE_D
), component(res1
, 0));
4702 case nir_intrinsic_ballot
: {
4703 const fs_reg value
= retype(get_nir_src(instr
->src
[0]),
4704 BRW_REGISTER_TYPE_UD
);
4705 struct brw_reg flag
= brw_flag_reg(0, 0);
4706 /* FIXME: For SIMD32 programs, this causes us to stomp on f0.1 as well
4707 * as f0.0. This is a problem for fragment programs as we currently use
4708 * f0.1 for discards. Fortunately, we don't support SIMD32 fragment
4709 * programs yet so this isn't a problem. When we do, something will
4712 if (dispatch_width
== 32)
4713 flag
.type
= BRW_REGISTER_TYPE_UD
;
4715 bld
.exec_all().group(1, 0).MOV(flag
, brw_imm_ud(0u));
4716 bld
.CMP(bld
.null_reg_ud(), value
, brw_imm_ud(0u), BRW_CONDITIONAL_NZ
);
4718 if (instr
->dest
.ssa
.bit_size
> 32) {
4719 dest
.type
= BRW_REGISTER_TYPE_UQ
;
4721 dest
.type
= BRW_REGISTER_TYPE_UD
;
4723 bld
.MOV(dest
, flag
);
4727 case nir_intrinsic_read_invocation
: {
4728 const fs_reg value
= get_nir_src(instr
->src
[0]);
4729 const fs_reg invocation
= get_nir_src(instr
->src
[1]);
4730 fs_reg tmp
= bld
.vgrf(value
.type
);
4732 bld
.exec_all().emit(SHADER_OPCODE_BROADCAST
, tmp
, value
,
4733 bld
.emit_uniformize(invocation
));
4735 bld
.MOV(retype(dest
, value
.type
), fs_reg(component(tmp
, 0)));
4739 case nir_intrinsic_read_first_invocation
: {
4740 const fs_reg value
= get_nir_src(instr
->src
[0]);
4741 bld
.MOV(retype(dest
, value
.type
), bld
.emit_uniformize(value
));
4745 case nir_intrinsic_shuffle
: {
4746 const fs_reg value
= get_nir_src(instr
->src
[0]);
4747 const fs_reg index
= get_nir_src(instr
->src
[1]);
4749 bld
.emit(SHADER_OPCODE_SHUFFLE
, retype(dest
, value
.type
), value
, index
);
4753 case nir_intrinsic_first_invocation
: {
4754 fs_reg tmp
= bld
.vgrf(BRW_REGISTER_TYPE_UD
);
4755 bld
.exec_all().emit(SHADER_OPCODE_FIND_LIVE_CHANNEL
, tmp
);
4756 bld
.MOV(retype(dest
, BRW_REGISTER_TYPE_UD
),
4757 fs_reg(component(tmp
, 0)));
4761 case nir_intrinsic_quad_broadcast
: {
4762 const fs_reg value
= get_nir_src(instr
->src
[0]);
4763 const unsigned index
= nir_src_as_uint(instr
->src
[1]);
4765 bld
.emit(SHADER_OPCODE_CLUSTER_BROADCAST
, retype(dest
, value
.type
),
4766 value
, brw_imm_ud(index
), brw_imm_ud(4));
4770 case nir_intrinsic_quad_swap_horizontal
: {
4771 const fs_reg value
= get_nir_src(instr
->src
[0]);
4772 const fs_reg tmp
= bld
.vgrf(value
.type
);
4773 if (devinfo
->gen
<= 7) {
4774 /* The hardware doesn't seem to support these crazy regions with
4775 * compressed instructions on gen7 and earlier so we fall back to
4776 * using quad swizzles. Fortunately, we don't support 64-bit
4777 * anything in Vulkan on gen7.
4779 assert(nir_src_bit_size(instr
->src
[0]) == 32);
4780 const fs_builder ubld
= bld
.exec_all();
4781 ubld
.emit(SHADER_OPCODE_QUAD_SWIZZLE
, tmp
, value
,
4782 brw_imm_ud(BRW_SWIZZLE4(1,0,3,2)));
4783 bld
.MOV(retype(dest
, value
.type
), tmp
);
4785 const fs_builder ubld
= bld
.exec_all().group(dispatch_width
/ 2, 0);
4787 const fs_reg src_left
= horiz_stride(value
, 2);
4788 const fs_reg src_right
= horiz_stride(horiz_offset(value
, 1), 2);
4789 const fs_reg tmp_left
= horiz_stride(tmp
, 2);
4790 const fs_reg tmp_right
= horiz_stride(horiz_offset(tmp
, 1), 2);
4792 ubld
.MOV(tmp_left
, src_right
);
4793 ubld
.MOV(tmp_right
, src_left
);
4796 bld
.MOV(retype(dest
, value
.type
), tmp
);
4800 case nir_intrinsic_quad_swap_vertical
: {
4801 const fs_reg value
= get_nir_src(instr
->src
[0]);
4802 if (nir_src_bit_size(instr
->src
[0]) == 32) {
4803 /* For 32-bit, we can use a SIMD4x2 instruction to do this easily */
4804 const fs_reg tmp
= bld
.vgrf(value
.type
);
4805 const fs_builder ubld
= bld
.exec_all();
4806 ubld
.emit(SHADER_OPCODE_QUAD_SWIZZLE
, tmp
, value
,
4807 brw_imm_ud(BRW_SWIZZLE4(2,3,0,1)));
4808 bld
.MOV(retype(dest
, value
.type
), tmp
);
4810 /* For larger data types, we have to either emit dispatch_width many
4811 * MOVs or else fall back to doing indirects.
4813 fs_reg idx
= bld
.vgrf(BRW_REGISTER_TYPE_W
);
4814 bld
.XOR(idx
, nir_system_values
[SYSTEM_VALUE_SUBGROUP_INVOCATION
],
4816 bld
.emit(SHADER_OPCODE_SHUFFLE
, retype(dest
, value
.type
), value
, idx
);
4821 case nir_intrinsic_quad_swap_diagonal
: {
4822 const fs_reg value
= get_nir_src(instr
->src
[0]);
4823 if (nir_src_bit_size(instr
->src
[0]) == 32) {
4824 /* For 32-bit, we can use a SIMD4x2 instruction to do this easily */
4825 const fs_reg tmp
= bld
.vgrf(value
.type
);
4826 const fs_builder ubld
= bld
.exec_all();
4827 ubld
.emit(SHADER_OPCODE_QUAD_SWIZZLE
, tmp
, value
,
4828 brw_imm_ud(BRW_SWIZZLE4(3,2,1,0)));
4829 bld
.MOV(retype(dest
, value
.type
), tmp
);
4831 /* For larger data types, we have to either emit dispatch_width many
4832 * MOVs or else fall back to doing indirects.
4834 fs_reg idx
= bld
.vgrf(BRW_REGISTER_TYPE_W
);
4835 bld
.XOR(idx
, nir_system_values
[SYSTEM_VALUE_SUBGROUP_INVOCATION
],
4837 bld
.emit(SHADER_OPCODE_SHUFFLE
, retype(dest
, value
.type
), value
, idx
);
4842 case nir_intrinsic_reduce
: {
4843 fs_reg src
= get_nir_src(instr
->src
[0]);
4844 nir_op redop
= (nir_op
)nir_intrinsic_reduction_op(instr
);
4845 unsigned cluster_size
= nir_intrinsic_cluster_size(instr
);
4846 if (cluster_size
== 0 || cluster_size
> dispatch_width
)
4847 cluster_size
= dispatch_width
;
4849 /* Figure out the source type */
4850 src
.type
= brw_type_for_nir_type(devinfo
,
4851 (nir_alu_type
)(nir_op_infos
[redop
].input_types
[0] |
4852 nir_src_bit_size(instr
->src
[0])));
4854 fs_reg identity
= brw_nir_reduction_op_identity(bld
, redop
, src
.type
);
4855 opcode brw_op
= brw_op_for_nir_reduction_op(redop
);
4856 brw_conditional_mod cond_mod
= brw_cond_mod_for_nir_reduction_op(redop
);
4858 /* Set up a register for all of our scratching around and initialize it
4859 * to reduction operation's identity value.
4861 fs_reg scan
= bld
.vgrf(src
.type
);
4862 bld
.exec_all().emit(SHADER_OPCODE_SEL_EXEC
, scan
, src
, identity
);
4864 bld
.emit_scan(brw_op
, scan
, cluster_size
, cond_mod
);
4866 dest
.type
= src
.type
;
4867 if (cluster_size
* type_sz(src
.type
) >= REG_SIZE
* 2) {
4868 /* In this case, CLUSTER_BROADCAST instruction isn't needed because
4869 * the distance between clusters is at least 2 GRFs. In this case,
4870 * we don't need the weird striding of the CLUSTER_BROADCAST
4871 * instruction and can just do regular MOVs.
4873 assert((cluster_size
* type_sz(src
.type
)) % (REG_SIZE
* 2) == 0);
4874 const unsigned groups
=
4875 (dispatch_width
* type_sz(src
.type
)) / (REG_SIZE
* 2);
4876 const unsigned group_size
= dispatch_width
/ groups
;
4877 for (unsigned i
= 0; i
< groups
; i
++) {
4878 const unsigned cluster
= (i
* group_size
) / cluster_size
;
4879 const unsigned comp
= cluster
* cluster_size
+ (cluster_size
- 1);
4880 bld
.group(group_size
, i
).MOV(horiz_offset(dest
, i
* group_size
),
4881 component(scan
, comp
));
4884 bld
.emit(SHADER_OPCODE_CLUSTER_BROADCAST
, dest
, scan
,
4885 brw_imm_ud(cluster_size
- 1), brw_imm_ud(cluster_size
));
4890 case nir_intrinsic_inclusive_scan
:
4891 case nir_intrinsic_exclusive_scan
: {
4892 fs_reg src
= get_nir_src(instr
->src
[0]);
4893 nir_op redop
= (nir_op
)nir_intrinsic_reduction_op(instr
);
4895 /* Figure out the source type */
4896 src
.type
= brw_type_for_nir_type(devinfo
,
4897 (nir_alu_type
)(nir_op_infos
[redop
].input_types
[0] |
4898 nir_src_bit_size(instr
->src
[0])));
4900 fs_reg identity
= brw_nir_reduction_op_identity(bld
, redop
, src
.type
);
4901 opcode brw_op
= brw_op_for_nir_reduction_op(redop
);
4902 brw_conditional_mod cond_mod
= brw_cond_mod_for_nir_reduction_op(redop
);
4904 /* Set up a register for all of our scratching around and initialize it
4905 * to reduction operation's identity value.
4907 fs_reg scan
= bld
.vgrf(src
.type
);
4908 const fs_builder allbld
= bld
.exec_all();
4909 allbld
.emit(SHADER_OPCODE_SEL_EXEC
, scan
, src
, identity
);
4911 if (instr
->intrinsic
== nir_intrinsic_exclusive_scan
) {
4912 /* Exclusive scan is a bit harder because we have to do an annoying
4913 * shift of the contents before we can begin. To make things worse,
4914 * we can't do this with a normal stride; we have to use indirects.
4916 fs_reg shifted
= bld
.vgrf(src
.type
);
4917 fs_reg idx
= bld
.vgrf(BRW_REGISTER_TYPE_W
);
4918 allbld
.ADD(idx
, nir_system_values
[SYSTEM_VALUE_SUBGROUP_INVOCATION
],
4920 allbld
.emit(SHADER_OPCODE_SHUFFLE
, shifted
, scan
, idx
);
4921 allbld
.group(1, 0).MOV(component(shifted
, 0), identity
);
4925 bld
.emit_scan(brw_op
, scan
, dispatch_width
, cond_mod
);
4927 bld
.MOV(retype(dest
, src
.type
), scan
);
4931 case nir_intrinsic_begin_invocation_interlock
: {
4932 const fs_builder ubld
= bld
.group(8, 0);
4933 const fs_reg tmp
= ubld
.vgrf(BRW_REGISTER_TYPE_UD
, 2);
4935 ubld
.emit(SHADER_OPCODE_INTERLOCK
, tmp
, brw_vec8_grf(0, 0))
4936 ->size_written
= 2 * REG_SIZE
;
4940 case nir_intrinsic_end_invocation_interlock
: {
4941 /* For endInvocationInterlock(), we need to insert a memory fence which
4942 * stalls in the shader until the memory transactions prior to that
4943 * fence are complete. This ensures that the shader does not end before
4944 * any writes from its critical section have landed. Otherwise, you can
4945 * end up with a case where the next invocation on that pixel properly
4946 * stalls for previous FS invocation on its pixel to complete but
4947 * doesn't actually wait for the dataport memory transactions from that
4948 * thread to land before submitting its own.
4950 const fs_builder ubld
= bld
.group(8, 0);
4951 const fs_reg tmp
= ubld
.vgrf(BRW_REGISTER_TYPE_UD
, 2);
4952 ubld
.emit(SHADER_OPCODE_MEMORY_FENCE
, tmp
,
4953 brw_vec8_grf(0, 0), brw_imm_ud(1), brw_imm_ud(0))
4954 ->size_written
= 2 * REG_SIZE
;
4959 unreachable("unknown intrinsic");
4964 fs_visitor::nir_emit_ssbo_atomic(const fs_builder
&bld
,
4965 int op
, nir_intrinsic_instr
*instr
)
4967 if (stage
== MESA_SHADER_FRAGMENT
)
4968 brw_wm_prog_data(prog_data
)->has_side_effects
= true;
4970 /* The BTI untyped atomic messages only support 32-bit atomics. If you
4971 * just look at the big table of messages in the Vol 7 of the SKL PRM, they
4972 * appear to exist. However, if you look at Vol 2a, there are no message
4973 * descriptors provided for Qword atomic ops except for A64 messages.
4975 assert(nir_dest_bit_size(instr
->dest
) == 32);
4978 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
4979 dest
= get_nir_dest(instr
->dest
);
4981 fs_reg srcs
[SURFACE_LOGICAL_NUM_SRCS
];
4982 srcs
[SURFACE_LOGICAL_SRC_SURFACE
] = get_nir_ssbo_intrinsic_index(bld
, instr
);
4983 srcs
[SURFACE_LOGICAL_SRC_ADDRESS
] = get_nir_src(instr
->src
[1]);
4984 srcs
[SURFACE_LOGICAL_SRC_IMM_DIMS
] = brw_imm_ud(1);
4985 srcs
[SURFACE_LOGICAL_SRC_IMM_ARG
] = brw_imm_ud(op
);
4988 if (op
!= BRW_AOP_INC
&& op
!= BRW_AOP_DEC
&& op
!= BRW_AOP_PREDEC
)
4989 data
= get_nir_src(instr
->src
[2]);
4991 if (op
== BRW_AOP_CMPWR
) {
4992 fs_reg tmp
= bld
.vgrf(data
.type
, 2);
4993 fs_reg sources
[2] = { data
, get_nir_src(instr
->src
[3]) };
4994 bld
.LOAD_PAYLOAD(tmp
, sources
, 2, 0);
4997 srcs
[SURFACE_LOGICAL_SRC_DATA
] = data
;
4999 /* Emit the actual atomic operation */
5001 bld
.emit(SHADER_OPCODE_UNTYPED_ATOMIC_LOGICAL
,
5002 dest
, srcs
, SURFACE_LOGICAL_NUM_SRCS
);
5006 fs_visitor::nir_emit_ssbo_atomic_float(const fs_builder
&bld
,
5007 int op
, nir_intrinsic_instr
*instr
)
5009 if (stage
== MESA_SHADER_FRAGMENT
)
5010 brw_wm_prog_data(prog_data
)->has_side_effects
= true;
5013 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
5014 dest
= get_nir_dest(instr
->dest
);
5016 fs_reg srcs
[SURFACE_LOGICAL_NUM_SRCS
];
5017 srcs
[SURFACE_LOGICAL_SRC_SURFACE
] = get_nir_ssbo_intrinsic_index(bld
, instr
);
5018 srcs
[SURFACE_LOGICAL_SRC_ADDRESS
] = get_nir_src(instr
->src
[1]);
5019 srcs
[SURFACE_LOGICAL_SRC_IMM_DIMS
] = brw_imm_ud(1);
5020 srcs
[SURFACE_LOGICAL_SRC_IMM_ARG
] = brw_imm_ud(op
);
5022 fs_reg data
= get_nir_src(instr
->src
[2]);
5023 if (op
== BRW_AOP_FCMPWR
) {
5024 fs_reg tmp
= bld
.vgrf(data
.type
, 2);
5025 fs_reg sources
[2] = { data
, get_nir_src(instr
->src
[3]) };
5026 bld
.LOAD_PAYLOAD(tmp
, sources
, 2, 0);
5029 srcs
[SURFACE_LOGICAL_SRC_DATA
] = data
;
5031 /* Emit the actual atomic operation */
5033 bld
.emit(SHADER_OPCODE_UNTYPED_ATOMIC_FLOAT_LOGICAL
,
5034 dest
, srcs
, SURFACE_LOGICAL_NUM_SRCS
);
5038 fs_visitor::nir_emit_shared_atomic(const fs_builder
&bld
,
5039 int op
, nir_intrinsic_instr
*instr
)
5042 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
5043 dest
= get_nir_dest(instr
->dest
);
5045 fs_reg srcs
[SURFACE_LOGICAL_NUM_SRCS
];
5046 srcs
[SURFACE_LOGICAL_SRC_SURFACE
] = brw_imm_ud(GEN7_BTI_SLM
);
5047 srcs
[SURFACE_LOGICAL_SRC_IMM_DIMS
] = brw_imm_ud(1);
5048 srcs
[SURFACE_LOGICAL_SRC_IMM_ARG
] = brw_imm_ud(op
);
5051 if (op
!= BRW_AOP_INC
&& op
!= BRW_AOP_DEC
&& op
!= BRW_AOP_PREDEC
)
5052 data
= get_nir_src(instr
->src
[1]);
5053 if (op
== BRW_AOP_CMPWR
) {
5054 fs_reg tmp
= bld
.vgrf(data
.type
, 2);
5055 fs_reg sources
[2] = { data
, get_nir_src(instr
->src
[2]) };
5056 bld
.LOAD_PAYLOAD(tmp
, sources
, 2, 0);
5059 srcs
[SURFACE_LOGICAL_SRC_DATA
] = data
;
5061 /* Get the offset */
5062 if (nir_src_is_const(instr
->src
[0])) {
5063 srcs
[SURFACE_LOGICAL_SRC_ADDRESS
] =
5064 brw_imm_ud(instr
->const_index
[0] + nir_src_as_uint(instr
->src
[0]));
5066 srcs
[SURFACE_LOGICAL_SRC_ADDRESS
] = vgrf(glsl_type::uint_type
);
5067 bld
.ADD(srcs
[SURFACE_LOGICAL_SRC_ADDRESS
],
5068 retype(get_nir_src(instr
->src
[0]), BRW_REGISTER_TYPE_UD
),
5069 brw_imm_ud(instr
->const_index
[0]));
5072 /* Emit the actual atomic operation operation */
5074 bld
.emit(SHADER_OPCODE_UNTYPED_ATOMIC_LOGICAL
,
5075 dest
, srcs
, SURFACE_LOGICAL_NUM_SRCS
);
5079 fs_visitor::nir_emit_shared_atomic_float(const fs_builder
&bld
,
5080 int op
, nir_intrinsic_instr
*instr
)
5083 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
5084 dest
= get_nir_dest(instr
->dest
);
5086 fs_reg srcs
[SURFACE_LOGICAL_NUM_SRCS
];
5087 srcs
[SURFACE_LOGICAL_SRC_SURFACE
] = brw_imm_ud(GEN7_BTI_SLM
);
5088 srcs
[SURFACE_LOGICAL_SRC_IMM_DIMS
] = brw_imm_ud(1);
5089 srcs
[SURFACE_LOGICAL_SRC_IMM_ARG
] = brw_imm_ud(op
);
5091 fs_reg data
= get_nir_src(instr
->src
[1]);
5092 if (op
== BRW_AOP_FCMPWR
) {
5093 fs_reg tmp
= bld
.vgrf(data
.type
, 2);
5094 fs_reg sources
[2] = { data
, get_nir_src(instr
->src
[2]) };
5095 bld
.LOAD_PAYLOAD(tmp
, sources
, 2, 0);
5098 srcs
[SURFACE_LOGICAL_SRC_DATA
] = data
;
5100 /* Get the offset */
5101 if (nir_src_is_const(instr
->src
[0])) {
5102 srcs
[SURFACE_LOGICAL_SRC_ADDRESS
] =
5103 brw_imm_ud(instr
->const_index
[0] + nir_src_as_uint(instr
->src
[0]));
5105 srcs
[SURFACE_LOGICAL_SRC_ADDRESS
] = vgrf(glsl_type::uint_type
);
5106 bld
.ADD(srcs
[SURFACE_LOGICAL_SRC_ADDRESS
],
5107 retype(get_nir_src(instr
->src
[0]), BRW_REGISTER_TYPE_UD
),
5108 brw_imm_ud(instr
->const_index
[0]));
5111 /* Emit the actual atomic operation operation */
5113 bld
.emit(SHADER_OPCODE_UNTYPED_ATOMIC_FLOAT_LOGICAL
,
5114 dest
, srcs
, SURFACE_LOGICAL_NUM_SRCS
);
5118 fs_visitor::nir_emit_global_atomic(const fs_builder
&bld
,
5119 int op
, nir_intrinsic_instr
*instr
)
5121 if (stage
== MESA_SHADER_FRAGMENT
)
5122 brw_wm_prog_data(prog_data
)->has_side_effects
= true;
5125 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
5126 dest
= get_nir_dest(instr
->dest
);
5128 fs_reg addr
= get_nir_src(instr
->src
[0]);
5131 if (op
!= BRW_AOP_INC
&& op
!= BRW_AOP_DEC
&& op
!= BRW_AOP_PREDEC
)
5132 data
= get_nir_src(instr
->src
[1]);
5134 if (op
== BRW_AOP_CMPWR
) {
5135 fs_reg tmp
= bld
.vgrf(data
.type
, 2);
5136 fs_reg sources
[2] = { data
, get_nir_src(instr
->src
[2]) };
5137 bld
.LOAD_PAYLOAD(tmp
, sources
, 2, 0);
5141 if (nir_dest_bit_size(instr
->dest
) == 64) {
5142 bld
.emit(SHADER_OPCODE_A64_UNTYPED_ATOMIC_INT64_LOGICAL
,
5143 dest
, addr
, data
, brw_imm_ud(op
));
5145 assert(nir_dest_bit_size(instr
->dest
) == 32);
5146 bld
.emit(SHADER_OPCODE_A64_UNTYPED_ATOMIC_LOGICAL
,
5147 dest
, addr
, data
, brw_imm_ud(op
));
5152 fs_visitor::nir_emit_global_atomic_float(const fs_builder
&bld
,
5153 int op
, nir_intrinsic_instr
*instr
)
5155 if (stage
== MESA_SHADER_FRAGMENT
)
5156 brw_wm_prog_data(prog_data
)->has_side_effects
= true;
5158 assert(nir_intrinsic_infos
[instr
->intrinsic
].has_dest
);
5159 fs_reg dest
= get_nir_dest(instr
->dest
);
5161 fs_reg addr
= get_nir_src(instr
->src
[0]);
5163 assert(op
!= BRW_AOP_INC
&& op
!= BRW_AOP_DEC
&& op
!= BRW_AOP_PREDEC
);
5164 fs_reg data
= get_nir_src(instr
->src
[1]);
5166 if (op
== BRW_AOP_FCMPWR
) {
5167 fs_reg tmp
= bld
.vgrf(data
.type
, 2);
5168 fs_reg sources
[2] = { data
, get_nir_src(instr
->src
[2]) };
5169 bld
.LOAD_PAYLOAD(tmp
, sources
, 2, 0);
5173 bld
.emit(SHADER_OPCODE_A64_UNTYPED_ATOMIC_LOGICAL
,
5174 dest
, addr
, data
, brw_imm_ud(op
));
5178 fs_visitor::nir_emit_texture(const fs_builder
&bld
, nir_tex_instr
*instr
)
5180 unsigned texture
= instr
->texture_index
;
5181 unsigned sampler
= instr
->sampler_index
;
5183 fs_reg srcs
[TEX_LOGICAL_NUM_SRCS
];
5185 srcs
[TEX_LOGICAL_SRC_SURFACE
] = brw_imm_ud(texture
);
5186 srcs
[TEX_LOGICAL_SRC_SAMPLER
] = brw_imm_ud(sampler
);
5188 int lod_components
= 0;
5190 /* The hardware requires a LOD for buffer textures */
5191 if (instr
->sampler_dim
== GLSL_SAMPLER_DIM_BUF
)
5192 srcs
[TEX_LOGICAL_SRC_LOD
] = brw_imm_d(0);
5194 uint32_t header_bits
= 0;
5195 for (unsigned i
= 0; i
< instr
->num_srcs
; i
++) {
5196 fs_reg src
= get_nir_src(instr
->src
[i
].src
);
5197 switch (instr
->src
[i
].src_type
) {
5198 case nir_tex_src_bias
:
5199 srcs
[TEX_LOGICAL_SRC_LOD
] =
5200 retype(get_nir_src_imm(instr
->src
[i
].src
), BRW_REGISTER_TYPE_F
);
5202 case nir_tex_src_comparator
:
5203 srcs
[TEX_LOGICAL_SRC_SHADOW_C
] = retype(src
, BRW_REGISTER_TYPE_F
);
5205 case nir_tex_src_coord
:
5206 switch (instr
->op
) {
5208 case nir_texop_txf_ms
:
5209 case nir_texop_txf_ms_mcs
:
5210 case nir_texop_samples_identical
:
5211 srcs
[TEX_LOGICAL_SRC_COORDINATE
] = retype(src
, BRW_REGISTER_TYPE_D
);
5214 srcs
[TEX_LOGICAL_SRC_COORDINATE
] = retype(src
, BRW_REGISTER_TYPE_F
);
5218 case nir_tex_src_ddx
:
5219 srcs
[TEX_LOGICAL_SRC_LOD
] = retype(src
, BRW_REGISTER_TYPE_F
);
5220 lod_components
= nir_tex_instr_src_size(instr
, i
);
5222 case nir_tex_src_ddy
:
5223 srcs
[TEX_LOGICAL_SRC_LOD2
] = retype(src
, BRW_REGISTER_TYPE_F
);
5225 case nir_tex_src_lod
:
5226 switch (instr
->op
) {
5228 srcs
[TEX_LOGICAL_SRC_LOD
] =
5229 retype(get_nir_src_imm(instr
->src
[i
].src
), BRW_REGISTER_TYPE_UD
);
5232 srcs
[TEX_LOGICAL_SRC_LOD
] =
5233 retype(get_nir_src_imm(instr
->src
[i
].src
), BRW_REGISTER_TYPE_D
);
5236 srcs
[TEX_LOGICAL_SRC_LOD
] =
5237 retype(get_nir_src_imm(instr
->src
[i
].src
), BRW_REGISTER_TYPE_F
);
5241 case nir_tex_src_min_lod
:
5242 srcs
[TEX_LOGICAL_SRC_MIN_LOD
] =
5243 retype(get_nir_src_imm(instr
->src
[i
].src
), BRW_REGISTER_TYPE_F
);
5245 case nir_tex_src_ms_index
:
5246 srcs
[TEX_LOGICAL_SRC_SAMPLE_INDEX
] = retype(src
, BRW_REGISTER_TYPE_UD
);
5249 case nir_tex_src_offset
: {
5250 uint32_t offset_bits
= 0;
5251 if (brw_texture_offset(instr
, i
, &offset_bits
)) {
5252 header_bits
|= offset_bits
;
5254 srcs
[TEX_LOGICAL_SRC_TG4_OFFSET
] =
5255 retype(src
, BRW_REGISTER_TYPE_D
);
5260 case nir_tex_src_projector
:
5261 unreachable("should be lowered");
5263 case nir_tex_src_texture_offset
: {
5264 /* Emit code to evaluate the actual indexing expression */
5265 fs_reg tmp
= vgrf(glsl_type::uint_type
);
5266 bld
.ADD(tmp
, src
, brw_imm_ud(texture
));
5267 srcs
[TEX_LOGICAL_SRC_SURFACE
] = bld
.emit_uniformize(tmp
);
5271 case nir_tex_src_sampler_offset
: {
5272 /* Emit code to evaluate the actual indexing expression */
5273 fs_reg tmp
= vgrf(glsl_type::uint_type
);
5274 bld
.ADD(tmp
, src
, brw_imm_ud(sampler
));
5275 srcs
[TEX_LOGICAL_SRC_SAMPLER
] = bld
.emit_uniformize(tmp
);
5279 case nir_tex_src_texture_handle
:
5280 assert(nir_tex_instr_src_index(instr
, nir_tex_src_texture_offset
) == -1);
5281 srcs
[TEX_LOGICAL_SRC_SURFACE
] = fs_reg();
5282 srcs
[TEX_LOGICAL_SRC_SURFACE_HANDLE
] = bld
.emit_uniformize(src
);
5285 case nir_tex_src_sampler_handle
:
5286 assert(nir_tex_instr_src_index(instr
, nir_tex_src_sampler_offset
) == -1);
5287 srcs
[TEX_LOGICAL_SRC_SAMPLER
] = fs_reg();
5288 srcs
[TEX_LOGICAL_SRC_SAMPLER_HANDLE
] = bld
.emit_uniformize(src
);
5291 case nir_tex_src_ms_mcs
:
5292 assert(instr
->op
== nir_texop_txf_ms
);
5293 srcs
[TEX_LOGICAL_SRC_MCS
] = retype(src
, BRW_REGISTER_TYPE_D
);
5296 case nir_tex_src_plane
: {
5297 const uint32_t plane
= nir_src_as_uint(instr
->src
[i
].src
);
5298 const uint32_t texture_index
=
5299 instr
->texture_index
+
5300 stage_prog_data
->binding_table
.plane_start
[plane
] -
5301 stage_prog_data
->binding_table
.texture_start
;
5303 srcs
[TEX_LOGICAL_SRC_SURFACE
] = brw_imm_ud(texture_index
);
5308 unreachable("unknown texture source");
5312 if (srcs
[TEX_LOGICAL_SRC_MCS
].file
== BAD_FILE
&&
5313 (instr
->op
== nir_texop_txf_ms
||
5314 instr
->op
== nir_texop_samples_identical
)) {
5315 if (devinfo
->gen
>= 7 &&
5316 key_tex
->compressed_multisample_layout_mask
& (1 << texture
)) {
5317 srcs
[TEX_LOGICAL_SRC_MCS
] =
5318 emit_mcs_fetch(srcs
[TEX_LOGICAL_SRC_COORDINATE
],
5319 instr
->coord_components
,
5320 srcs
[TEX_LOGICAL_SRC_SURFACE
],
5321 srcs
[TEX_LOGICAL_SRC_SURFACE_HANDLE
]);
5323 srcs
[TEX_LOGICAL_SRC_MCS
] = brw_imm_ud(0u);
5327 srcs
[TEX_LOGICAL_SRC_COORD_COMPONENTS
] = brw_imm_d(instr
->coord_components
);
5328 srcs
[TEX_LOGICAL_SRC_GRAD_COMPONENTS
] = brw_imm_d(lod_components
);
5331 switch (instr
->op
) {
5333 opcode
= SHADER_OPCODE_TEX_LOGICAL
;
5336 opcode
= FS_OPCODE_TXB_LOGICAL
;
5339 opcode
= SHADER_OPCODE_TXL_LOGICAL
;
5342 opcode
= SHADER_OPCODE_TXD_LOGICAL
;
5345 opcode
= SHADER_OPCODE_TXF_LOGICAL
;
5347 case nir_texop_txf_ms
:
5348 if ((key_tex
->msaa_16
& (1 << sampler
)))
5349 opcode
= SHADER_OPCODE_TXF_CMS_W_LOGICAL
;
5351 opcode
= SHADER_OPCODE_TXF_CMS_LOGICAL
;
5353 case nir_texop_txf_ms_mcs
:
5354 opcode
= SHADER_OPCODE_TXF_MCS_LOGICAL
;
5356 case nir_texop_query_levels
:
5358 opcode
= SHADER_OPCODE_TXS_LOGICAL
;
5361 opcode
= SHADER_OPCODE_LOD_LOGICAL
;
5364 if (srcs
[TEX_LOGICAL_SRC_TG4_OFFSET
].file
!= BAD_FILE
)
5365 opcode
= SHADER_OPCODE_TG4_OFFSET_LOGICAL
;
5367 opcode
= SHADER_OPCODE_TG4_LOGICAL
;
5369 case nir_texop_texture_samples
:
5370 opcode
= SHADER_OPCODE_SAMPLEINFO_LOGICAL
;
5372 case nir_texop_samples_identical
: {
5373 fs_reg dst
= retype(get_nir_dest(instr
->dest
), BRW_REGISTER_TYPE_D
);
5375 /* If mcs is an immediate value, it means there is no MCS. In that case
5376 * just return false.
5378 if (srcs
[TEX_LOGICAL_SRC_MCS
].file
== BRW_IMMEDIATE_VALUE
) {
5379 bld
.MOV(dst
, brw_imm_ud(0u));
5380 } else if ((key_tex
->msaa_16
& (1 << sampler
))) {
5381 fs_reg tmp
= vgrf(glsl_type::uint_type
);
5382 bld
.OR(tmp
, srcs
[TEX_LOGICAL_SRC_MCS
],
5383 offset(srcs
[TEX_LOGICAL_SRC_MCS
], bld
, 1));
5384 bld
.CMP(dst
, tmp
, brw_imm_ud(0u), BRW_CONDITIONAL_EQ
);
5386 bld
.CMP(dst
, srcs
[TEX_LOGICAL_SRC_MCS
], brw_imm_ud(0u),
5387 BRW_CONDITIONAL_EQ
);
5392 unreachable("unknown texture opcode");
5395 if (instr
->op
== nir_texop_tg4
) {
5396 if (instr
->component
== 1 &&
5397 key_tex
->gather_channel_quirk_mask
& (1 << texture
)) {
5398 /* gather4 sampler is broken for green channel on RG32F --
5399 * we must ask for blue instead.
5401 header_bits
|= 2 << 16;
5403 header_bits
|= instr
->component
<< 16;
5407 fs_reg dst
= bld
.vgrf(brw_type_for_nir_type(devinfo
, instr
->dest_type
), 4);
5408 fs_inst
*inst
= bld
.emit(opcode
, dst
, srcs
, ARRAY_SIZE(srcs
));
5409 inst
->offset
= header_bits
;
5411 const unsigned dest_size
= nir_tex_instr_dest_size(instr
);
5412 if (devinfo
->gen
>= 9 &&
5413 instr
->op
!= nir_texop_tg4
&& instr
->op
!= nir_texop_query_levels
) {
5414 unsigned write_mask
= instr
->dest
.is_ssa
?
5415 nir_ssa_def_components_read(&instr
->dest
.ssa
):
5416 (1 << dest_size
) - 1;
5417 assert(write_mask
!= 0); /* dead code should have been eliminated */
5418 inst
->size_written
= util_last_bit(write_mask
) *
5419 inst
->dst
.component_size(inst
->exec_size
);
5421 inst
->size_written
= 4 * inst
->dst
.component_size(inst
->exec_size
);
5424 if (srcs
[TEX_LOGICAL_SRC_SHADOW_C
].file
!= BAD_FILE
)
5425 inst
->shadow_compare
= true;
5427 if (instr
->op
== nir_texop_tg4
&& devinfo
->gen
== 6)
5428 emit_gen6_gather_wa(key_tex
->gen6_gather_wa
[texture
], dst
);
5431 for (unsigned i
= 0; i
< dest_size
; i
++)
5432 nir_dest
[i
] = offset(dst
, bld
, i
);
5434 if (instr
->op
== nir_texop_query_levels
) {
5435 /* # levels is in .w */
5436 nir_dest
[0] = offset(dst
, bld
, 3);
5437 } else if (instr
->op
== nir_texop_txs
&&
5438 dest_size
>= 3 && devinfo
->gen
< 7) {
5439 /* Gen4-6 return 0 instead of 1 for single layer surfaces. */
5440 fs_reg depth
= offset(dst
, bld
, 2);
5441 nir_dest
[2] = vgrf(glsl_type::int_type
);
5442 bld
.emit_minmax(nir_dest
[2], depth
, brw_imm_d(1), BRW_CONDITIONAL_GE
);
5445 bld
.LOAD_PAYLOAD(get_nir_dest(instr
->dest
), nir_dest
, dest_size
, 0);
5449 fs_visitor::nir_emit_jump(const fs_builder
&bld
, nir_jump_instr
*instr
)
5451 switch (instr
->type
) {
5452 case nir_jump_break
:
5453 bld
.emit(BRW_OPCODE_BREAK
);
5455 case nir_jump_continue
:
5456 bld
.emit(BRW_OPCODE_CONTINUE
);
5458 case nir_jump_return
:
5460 unreachable("unknown jump");
5465 * This helper takes a source register and un/shuffles it into the destination
5468 * If source type size is smaller than destination type size the operation
5469 * needed is a component shuffle. The opposite case would be an unshuffle. If
5470 * source/destination type size is equal a shuffle is done that would be
5471 * equivalent to a simple MOV.
5473 * For example, if source is a 16-bit type and destination is 32-bit. A 3
5474 * components .xyz 16-bit vector on SIMD8 would be.
5476 * |x1|x2|x3|x4|x5|x6|x7|x8|y1|y2|y3|y4|y5|y6|y7|y8|
5477 * |z1|z2|z3|z4|z5|z6|z7|z8| | | | | | | | |
5479 * This helper will return the following 2 32-bit components with the 16-bit
5482 * |x1 y1|x2 y2|x3 y3|x4 y4|x5 y5|x6 y6|x7 y7|x8 y8|
5483 * |z1 |z2 |z3 |z4 |z5 |z6 |z7 |z8 |
5485 * For unshuffle, the example would be the opposite, a 64-bit type source
5486 * and a 32-bit destination. A 2 component .xy 64-bit vector on SIMD8
5489 * | x1l x1h | x2l x2h | x3l x3h | x4l x4h |
5490 * | x5l x5h | x6l x6h | x7l x7h | x8l x8h |
5491 * | y1l y1h | y2l y2h | y3l y3h | y4l y4h |
5492 * | y5l y5h | y6l y6h | y7l y7h | y8l y8h |
5494 * The returned result would be the following 4 32-bit components unshuffled:
5496 * | x1l | x2l | x3l | x4l | x5l | x6l | x7l | x8l |
5497 * | x1h | x2h | x3h | x4h | x5h | x6h | x7h | x8h |
5498 * | y1l | y2l | y3l | y4l | y5l | y6l | y7l | y8l |
5499 * | y1h | y2h | y3h | y4h | y5h | y6h | y7h | y8h |
5501 * - Source and destination register must not be overlapped.
5502 * - components units are measured in terms of the smaller type between
5503 * source and destination because we are un/shuffling the smaller
5504 * components from/into the bigger ones.
5505 * - first_component parameter allows skipping source components.
5508 shuffle_src_to_dst(const fs_builder
&bld
,
5511 uint32_t first_component
,
5512 uint32_t components
)
5514 if (type_sz(src
.type
) == type_sz(dst
.type
)) {
5515 assert(!regions_overlap(dst
,
5516 type_sz(dst
.type
) * bld
.dispatch_width() * components
,
5517 offset(src
, bld
, first_component
),
5518 type_sz(src
.type
) * bld
.dispatch_width() * components
));
5519 for (unsigned i
= 0; i
< components
; i
++) {
5520 bld
.MOV(retype(offset(dst
, bld
, i
), src
.type
),
5521 offset(src
, bld
, i
+ first_component
));
5523 } else if (type_sz(src
.type
) < type_sz(dst
.type
)) {
5524 /* Source is shuffled into destination */
5525 unsigned size_ratio
= type_sz(dst
.type
) / type_sz(src
.type
);
5526 assert(!regions_overlap(dst
,
5527 type_sz(dst
.type
) * bld
.dispatch_width() *
5528 DIV_ROUND_UP(components
, size_ratio
),
5529 offset(src
, bld
, first_component
),
5530 type_sz(src
.type
) * bld
.dispatch_width() * components
));
5532 brw_reg_type shuffle_type
=
5533 brw_reg_type_from_bit_size(8 * type_sz(src
.type
),
5534 BRW_REGISTER_TYPE_D
);
5535 for (unsigned i
= 0; i
< components
; i
++) {
5536 fs_reg shuffle_component_i
=
5537 subscript(offset(dst
, bld
, i
/ size_ratio
),
5538 shuffle_type
, i
% size_ratio
);
5539 bld
.MOV(shuffle_component_i
,
5540 retype(offset(src
, bld
, i
+ first_component
), shuffle_type
));
5543 /* Source is unshuffled into destination */
5544 unsigned size_ratio
= type_sz(src
.type
) / type_sz(dst
.type
);
5545 assert(!regions_overlap(dst
,
5546 type_sz(dst
.type
) * bld
.dispatch_width() * components
,
5547 offset(src
, bld
, first_component
/ size_ratio
),
5548 type_sz(src
.type
) * bld
.dispatch_width() *
5549 DIV_ROUND_UP(components
+ (first_component
% size_ratio
),
5552 brw_reg_type shuffle_type
=
5553 brw_reg_type_from_bit_size(8 * type_sz(dst
.type
),
5554 BRW_REGISTER_TYPE_D
);
5555 for (unsigned i
= 0; i
< components
; i
++) {
5556 fs_reg shuffle_component_i
=
5557 subscript(offset(src
, bld
, (first_component
+ i
) / size_ratio
),
5558 shuffle_type
, (first_component
+ i
) % size_ratio
);
5559 bld
.MOV(retype(offset(dst
, bld
, i
), shuffle_type
),
5560 shuffle_component_i
);
5566 shuffle_from_32bit_read(const fs_builder
&bld
,
5569 uint32_t first_component
,
5570 uint32_t components
)
5572 assert(type_sz(src
.type
) == 4);
5574 /* This function takes components in units of the destination type while
5575 * shuffle_src_to_dst takes components in units of the smallest type
5577 if (type_sz(dst
.type
) > 4) {
5578 assert(type_sz(dst
.type
) == 8);
5579 first_component
*= 2;
5583 shuffle_src_to_dst(bld
, dst
, src
, first_component
, components
);
5587 setup_imm_df(const fs_builder
&bld
, double v
)
5589 const struct gen_device_info
*devinfo
= bld
.shader
->devinfo
;
5590 assert(devinfo
->gen
>= 7);
5592 if (devinfo
->gen
>= 8)
5593 return brw_imm_df(v
);
5595 /* gen7.5 does not support DF immediates straighforward but the DIM
5596 * instruction allows to set the 64-bit immediate value.
5598 if (devinfo
->is_haswell
) {
5599 const fs_builder ubld
= bld
.exec_all().group(1, 0);
5600 fs_reg dst
= ubld
.vgrf(BRW_REGISTER_TYPE_DF
, 1);
5601 ubld
.DIM(dst
, brw_imm_df(v
));
5602 return component(dst
, 0);
5605 /* gen7 does not support DF immediates, so we generate a 64-bit constant by
5606 * writing the low 32-bit of the constant to suboffset 0 of a VGRF and
5607 * the high 32-bit to suboffset 4 and then applying a stride of 0.
5609 * Alternatively, we could also produce a normal VGRF (without stride 0)
5610 * by writing to all the channels in the VGRF, however, that would hit the
5611 * gen7 bug where we have to split writes that span more than 1 register
5612 * into instructions with a width of 4 (otherwise the write to the second
5613 * register written runs into an execmask hardware bug) which isn't very
5626 const fs_builder ubld
= bld
.exec_all().group(1, 0);
5627 const fs_reg tmp
= ubld
.vgrf(BRW_REGISTER_TYPE_UD
, 2);
5628 ubld
.MOV(tmp
, brw_imm_ud(di
.i1
));
5629 ubld
.MOV(horiz_offset(tmp
, 1), brw_imm_ud(di
.i2
));
5631 return component(retype(tmp
, BRW_REGISTER_TYPE_DF
), 0);
5635 setup_imm_b(const fs_builder
&bld
, int8_t v
)
5637 const fs_reg tmp
= bld
.vgrf(BRW_REGISTER_TYPE_B
);
5638 bld
.MOV(tmp
, brw_imm_w(v
));
5643 setup_imm_ub(const fs_builder
&bld
, uint8_t v
)
5645 const fs_reg tmp
= bld
.vgrf(BRW_REGISTER_TYPE_UB
);
5646 bld
.MOV(tmp
, brw_imm_uw(v
));