2 * Copyright © 2010 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 #include "compiler/glsl/ir.h"
26 #include "brw_fs_surface_builder.h"
30 using namespace brw::surface_access
;
33 fs_visitor::emit_nir_code()
35 /* emit the arrays used for inputs and outputs - load/store intrinsics will
36 * be converted to reads/writes of these arrays
40 nir_emit_system_values();
42 /* get the main function and emit it */
43 nir_foreach_function(function
, nir
) {
44 assert(strcmp(function
->name
, "main") == 0);
45 assert(function
->impl
);
46 nir_emit_impl(function
->impl
);
51 fs_visitor::nir_setup_outputs()
53 if (stage
== MESA_SHADER_TESS_CTRL
|| stage
== MESA_SHADER_FRAGMENT
)
56 unsigned vec4s
[VARYING_SLOT_TESS_MAX
] = { 0, };
58 /* Calculate the size of output registers in a separate pass, before
59 * allocating them. With ARB_enhanced_layouts, multiple output variables
60 * may occupy the same slot, but have different type sizes.
62 nir_foreach_variable(var
, &nir
->outputs
) {
63 const int loc
= var
->data
.driver_location
;
64 const unsigned var_vec4s
=
65 var
->data
.compact
? DIV_ROUND_UP(glsl_get_length(var
->type
), 4)
66 : type_size_vec4(var
->type
);
67 vec4s
[loc
] = MAX2(vec4s
[loc
], var_vec4s
);
70 nir_foreach_variable(var
, &nir
->outputs
) {
71 const int loc
= var
->data
.driver_location
;
72 if (outputs
[loc
].file
== BAD_FILE
) {
73 fs_reg reg
= bld
.vgrf(BRW_REGISTER_TYPE_F
, 4 * vec4s
[loc
]);
74 for (unsigned i
= 0; i
< vec4s
[loc
]; i
++) {
75 outputs
[loc
+ i
] = offset(reg
, bld
, 4 * i
);
82 fs_visitor::nir_setup_uniforms()
84 /* Only the first compile gets to set up uniforms. */
85 if (push_constant_loc
) {
86 assert(pull_constant_loc
);
90 uniforms
= nir
->num_uniforms
/ 4;
92 if (stage
== MESA_SHADER_COMPUTE
) {
93 /* Add a uniform for the thread local id. It must be the last uniform
96 assert(uniforms
== prog_data
->nr_params
);
97 uint32_t *param
= brw_stage_prog_data_add_params(prog_data
, 1);
98 *param
= BRW_PARAM_BUILTIN_SUBGROUP_ID
;
99 subgroup_id
= fs_reg(UNIFORM
, uniforms
++, BRW_REGISTER_TYPE_UD
);
104 emit_system_values_block(nir_block
*block
, fs_visitor
*v
)
108 nir_foreach_instr(instr
, block
) {
109 if (instr
->type
!= nir_instr_type_intrinsic
)
112 nir_intrinsic_instr
*intrin
= nir_instr_as_intrinsic(instr
);
113 switch (intrin
->intrinsic
) {
114 case nir_intrinsic_load_vertex_id
:
115 case nir_intrinsic_load_base_vertex
:
116 unreachable("should be lowered by nir_lower_system_values().");
118 case nir_intrinsic_load_vertex_id_zero_base
:
119 case nir_intrinsic_load_is_indexed_draw
:
120 case nir_intrinsic_load_first_vertex
:
121 case nir_intrinsic_load_instance_id
:
122 case nir_intrinsic_load_base_instance
:
123 case nir_intrinsic_load_draw_id
:
124 unreachable("should be lowered by brw_nir_lower_vs_inputs().");
126 case nir_intrinsic_load_invocation_id
:
127 if (v
->stage
== MESA_SHADER_TESS_CTRL
)
129 assert(v
->stage
== MESA_SHADER_GEOMETRY
);
130 reg
= &v
->nir_system_values
[SYSTEM_VALUE_INVOCATION_ID
];
131 if (reg
->file
== BAD_FILE
) {
132 const fs_builder abld
= v
->bld
.annotate("gl_InvocationID", NULL
);
133 fs_reg
g1(retype(brw_vec8_grf(1, 0), BRW_REGISTER_TYPE_UD
));
134 fs_reg iid
= abld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
135 abld
.SHR(iid
, g1
, brw_imm_ud(27u));
140 case nir_intrinsic_load_sample_pos
:
141 assert(v
->stage
== MESA_SHADER_FRAGMENT
);
142 reg
= &v
->nir_system_values
[SYSTEM_VALUE_SAMPLE_POS
];
143 if (reg
->file
== BAD_FILE
)
144 *reg
= *v
->emit_samplepos_setup();
147 case nir_intrinsic_load_sample_id
:
148 assert(v
->stage
== MESA_SHADER_FRAGMENT
);
149 reg
= &v
->nir_system_values
[SYSTEM_VALUE_SAMPLE_ID
];
150 if (reg
->file
== BAD_FILE
)
151 *reg
= *v
->emit_sampleid_setup();
154 case nir_intrinsic_load_sample_mask_in
:
155 assert(v
->stage
== MESA_SHADER_FRAGMENT
);
156 assert(v
->devinfo
->gen
>= 7);
157 reg
= &v
->nir_system_values
[SYSTEM_VALUE_SAMPLE_MASK_IN
];
158 if (reg
->file
== BAD_FILE
)
159 *reg
= *v
->emit_samplemaskin_setup();
162 case nir_intrinsic_load_work_group_id
:
163 assert(v
->stage
== MESA_SHADER_COMPUTE
);
164 reg
= &v
->nir_system_values
[SYSTEM_VALUE_WORK_GROUP_ID
];
165 if (reg
->file
== BAD_FILE
)
166 *reg
= *v
->emit_cs_work_group_id_setup();
169 case nir_intrinsic_load_helper_invocation
:
170 assert(v
->stage
== MESA_SHADER_FRAGMENT
);
171 reg
= &v
->nir_system_values
[SYSTEM_VALUE_HELPER_INVOCATION
];
172 if (reg
->file
== BAD_FILE
) {
173 const fs_builder abld
=
174 v
->bld
.annotate("gl_HelperInvocation", NULL
);
176 /* On Gen6+ (gl_HelperInvocation is only exposed on Gen7+) the
177 * pixel mask is in g1.7 of the thread payload.
179 * We move the per-channel pixel enable bit to the low bit of each
180 * channel by shifting the byte containing the pixel mask by the
181 * vector immediate 0x76543210UV.
183 * The region of <1,8,0> reads only 1 byte (the pixel masks for
184 * subspans 0 and 1) in SIMD8 and an additional byte (the pixel
185 * masks for 2 and 3) in SIMD16.
187 fs_reg shifted
= abld
.vgrf(BRW_REGISTER_TYPE_UW
, 1);
189 stride(byte_offset(retype(brw_vec1_grf(1, 0),
190 BRW_REGISTER_TYPE_UB
), 28),
192 brw_imm_v(0x76543210));
194 /* A set bit in the pixel mask means the channel is enabled, but
195 * that is the opposite of gl_HelperInvocation so we need to invert
198 * The negate source-modifier bit of logical instructions on Gen8+
199 * performs 1's complement negation, so we can use that instead of
202 fs_reg inverted
= negate(shifted
);
203 if (v
->devinfo
->gen
< 8) {
204 inverted
= abld
.vgrf(BRW_REGISTER_TYPE_UW
);
205 abld
.NOT(inverted
, shifted
);
208 /* We then resolve the 0/1 result to 0/~0 boolean values by ANDing
209 * with 1 and negating.
211 fs_reg anded
= abld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
212 abld
.AND(anded
, inverted
, brw_imm_uw(1));
214 fs_reg dst
= abld
.vgrf(BRW_REGISTER_TYPE_D
, 1);
215 abld
.MOV(dst
, negate(retype(anded
, BRW_REGISTER_TYPE_D
)));
229 fs_visitor::nir_emit_system_values()
231 nir_system_values
= ralloc_array(mem_ctx
, fs_reg
, SYSTEM_VALUE_MAX
);
232 for (unsigned i
= 0; i
< SYSTEM_VALUE_MAX
; i
++) {
233 nir_system_values
[i
] = fs_reg();
236 /* Always emit SUBGROUP_INVOCATION. Dead code will clean it up if we
237 * never end up using it.
240 const fs_builder abld
= bld
.annotate("gl_SubgroupInvocation", NULL
);
241 fs_reg
®
= nir_system_values
[SYSTEM_VALUE_SUBGROUP_INVOCATION
];
242 reg
= abld
.vgrf(BRW_REGISTER_TYPE_UW
);
244 const fs_builder allbld8
= abld
.group(8, 0).exec_all();
245 allbld8
.MOV(reg
, brw_imm_v(0x76543210));
246 if (dispatch_width
> 8)
247 allbld8
.ADD(byte_offset(reg
, 16), reg
, brw_imm_uw(8u));
248 if (dispatch_width
> 16) {
249 const fs_builder allbld16
= abld
.group(16, 0).exec_all();
250 allbld16
.ADD(byte_offset(reg
, 32), reg
, brw_imm_uw(16u));
254 nir_foreach_function(function
, nir
) {
255 assert(strcmp(function
->name
, "main") == 0);
256 assert(function
->impl
);
257 nir_foreach_block(block
, function
->impl
) {
258 emit_system_values_block(block
, this);
264 * Returns a type based on a reference_type (word, float, half-float) and a
267 * Reference BRW_REGISTER_TYPE are HF,F,DF,W,D,UW,UD.
269 * @FIXME: 64-bit return types are always DF on integer types to maintain
270 * compability with uses of DF previously to the introduction of int64
274 brw_reg_type_from_bit_size(const unsigned bit_size
,
275 const brw_reg_type reference_type
)
277 switch(reference_type
) {
278 case BRW_REGISTER_TYPE_HF
:
279 case BRW_REGISTER_TYPE_F
:
280 case BRW_REGISTER_TYPE_DF
:
283 return BRW_REGISTER_TYPE_HF
;
285 return BRW_REGISTER_TYPE_F
;
287 return BRW_REGISTER_TYPE_DF
;
289 unreachable("Invalid bit size");
291 case BRW_REGISTER_TYPE_W
:
292 case BRW_REGISTER_TYPE_D
:
293 case BRW_REGISTER_TYPE_Q
:
296 return BRW_REGISTER_TYPE_W
;
298 return BRW_REGISTER_TYPE_D
;
300 return BRW_REGISTER_TYPE_Q
;
302 unreachable("Invalid bit size");
304 case BRW_REGISTER_TYPE_UW
:
305 case BRW_REGISTER_TYPE_UD
:
306 case BRW_REGISTER_TYPE_UQ
:
309 return BRW_REGISTER_TYPE_UW
;
311 return BRW_REGISTER_TYPE_UD
;
313 return BRW_REGISTER_TYPE_UQ
;
315 unreachable("Invalid bit size");
318 unreachable("Unknown type");
323 fs_visitor::nir_emit_impl(nir_function_impl
*impl
)
325 nir_locals
= ralloc_array(mem_ctx
, fs_reg
, impl
->reg_alloc
);
326 for (unsigned i
= 0; i
< impl
->reg_alloc
; i
++) {
327 nir_locals
[i
] = fs_reg();
330 foreach_list_typed(nir_register
, reg
, node
, &impl
->registers
) {
331 unsigned array_elems
=
332 reg
->num_array_elems
== 0 ? 1 : reg
->num_array_elems
;
333 unsigned size
= array_elems
* reg
->num_components
;
334 const brw_reg_type reg_type
=
335 brw_reg_type_from_bit_size(reg
->bit_size
, BRW_REGISTER_TYPE_F
);
336 nir_locals
[reg
->index
] = bld
.vgrf(reg_type
, size
);
339 nir_ssa_values
= reralloc(mem_ctx
, nir_ssa_values
, fs_reg
,
342 nir_emit_cf_list(&impl
->body
);
346 fs_visitor::nir_emit_cf_list(exec_list
*list
)
348 exec_list_validate(list
);
349 foreach_list_typed(nir_cf_node
, node
, node
, list
) {
350 switch (node
->type
) {
352 nir_emit_if(nir_cf_node_as_if(node
));
355 case nir_cf_node_loop
:
356 nir_emit_loop(nir_cf_node_as_loop(node
));
359 case nir_cf_node_block
:
360 nir_emit_block(nir_cf_node_as_block(node
));
364 unreachable("Invalid CFG node block");
370 fs_visitor::nir_emit_if(nir_if
*if_stmt
)
372 /* first, put the condition into f0 */
373 fs_inst
*inst
= bld
.MOV(bld
.null_reg_d(),
374 retype(get_nir_src(if_stmt
->condition
),
375 BRW_REGISTER_TYPE_D
));
376 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
378 bld
.IF(BRW_PREDICATE_NORMAL
);
380 nir_emit_cf_list(&if_stmt
->then_list
);
382 /* note: if the else is empty, dead CF elimination will remove it */
383 bld
.emit(BRW_OPCODE_ELSE
);
385 nir_emit_cf_list(&if_stmt
->else_list
);
387 bld
.emit(BRW_OPCODE_ENDIF
);
391 fs_visitor::nir_emit_loop(nir_loop
*loop
)
393 bld
.emit(BRW_OPCODE_DO
);
395 nir_emit_cf_list(&loop
->body
);
397 bld
.emit(BRW_OPCODE_WHILE
);
401 fs_visitor::nir_emit_block(nir_block
*block
)
403 nir_foreach_instr(instr
, block
) {
404 nir_emit_instr(instr
);
409 fs_visitor::nir_emit_instr(nir_instr
*instr
)
411 const fs_builder abld
= bld
.annotate(NULL
, instr
);
413 switch (instr
->type
) {
414 case nir_instr_type_alu
:
415 nir_emit_alu(abld
, nir_instr_as_alu(instr
));
418 case nir_instr_type_intrinsic
:
420 case MESA_SHADER_VERTEX
:
421 nir_emit_vs_intrinsic(abld
, nir_instr_as_intrinsic(instr
));
423 case MESA_SHADER_TESS_CTRL
:
424 nir_emit_tcs_intrinsic(abld
, nir_instr_as_intrinsic(instr
));
426 case MESA_SHADER_TESS_EVAL
:
427 nir_emit_tes_intrinsic(abld
, nir_instr_as_intrinsic(instr
));
429 case MESA_SHADER_GEOMETRY
:
430 nir_emit_gs_intrinsic(abld
, nir_instr_as_intrinsic(instr
));
432 case MESA_SHADER_FRAGMENT
:
433 nir_emit_fs_intrinsic(abld
, nir_instr_as_intrinsic(instr
));
435 case MESA_SHADER_COMPUTE
:
436 nir_emit_cs_intrinsic(abld
, nir_instr_as_intrinsic(instr
));
439 unreachable("unsupported shader stage");
443 case nir_instr_type_tex
:
444 nir_emit_texture(abld
, nir_instr_as_tex(instr
));
447 case nir_instr_type_load_const
:
448 nir_emit_load_const(abld
, nir_instr_as_load_const(instr
));
451 case nir_instr_type_ssa_undef
:
452 /* We create a new VGRF for undefs on every use (by handling
453 * them in get_nir_src()), rather than for each definition.
454 * This helps register coalescing eliminate MOVs from undef.
458 case nir_instr_type_jump
:
459 nir_emit_jump(abld
, nir_instr_as_jump(instr
));
463 unreachable("unknown instruction type");
468 * Recognizes a parent instruction of nir_op_extract_* and changes the type to
472 fs_visitor::optimize_extract_to_float(nir_alu_instr
*instr
,
473 const fs_reg
&result
)
475 if (!instr
->src
[0].src
.is_ssa
||
476 !instr
->src
[0].src
.ssa
->parent_instr
)
479 if (instr
->src
[0].src
.ssa
->parent_instr
->type
!= nir_instr_type_alu
)
482 nir_alu_instr
*src0
=
483 nir_instr_as_alu(instr
->src
[0].src
.ssa
->parent_instr
);
485 if (src0
->op
!= nir_op_extract_u8
&& src0
->op
!= nir_op_extract_u16
&&
486 src0
->op
!= nir_op_extract_i8
&& src0
->op
!= nir_op_extract_i16
)
489 nir_const_value
*element
= nir_src_as_const_value(src0
->src
[1].src
);
490 assert(element
!= NULL
);
492 /* Element type to extract.*/
493 const brw_reg_type type
= brw_int_type(
494 src0
->op
== nir_op_extract_u16
|| src0
->op
== nir_op_extract_i16
? 2 : 1,
495 src0
->op
== nir_op_extract_i16
|| src0
->op
== nir_op_extract_i8
);
497 fs_reg op0
= get_nir_src(src0
->src
[0].src
);
498 op0
.type
= brw_type_for_nir_type(devinfo
,
499 (nir_alu_type
)(nir_op_infos
[src0
->op
].input_types
[0] |
500 nir_src_bit_size(src0
->src
[0].src
)));
501 op0
= offset(op0
, bld
, src0
->src
[0].swizzle
[0]);
503 set_saturate(instr
->dest
.saturate
,
504 bld
.MOV(result
, subscript(op0
, type
, element
->u32
[0])));
509 fs_visitor::optimize_frontfacing_ternary(nir_alu_instr
*instr
,
510 const fs_reg
&result
)
512 if (!instr
->src
[0].src
.is_ssa
||
513 instr
->src
[0].src
.ssa
->parent_instr
->type
!= nir_instr_type_intrinsic
)
516 nir_intrinsic_instr
*src0
=
517 nir_instr_as_intrinsic(instr
->src
[0].src
.ssa
->parent_instr
);
519 if (src0
->intrinsic
!= nir_intrinsic_load_front_face
)
522 nir_const_value
*value1
= nir_src_as_const_value(instr
->src
[1].src
);
523 if (!value1
|| fabsf(value1
->f32
[0]) != 1.0f
)
526 nir_const_value
*value2
= nir_src_as_const_value(instr
->src
[2].src
);
527 if (!value2
|| fabsf(value2
->f32
[0]) != 1.0f
)
530 fs_reg tmp
= vgrf(glsl_type::int_type
);
532 if (devinfo
->gen
>= 6) {
533 /* Bit 15 of g0.0 is 0 if the polygon is front facing. */
534 fs_reg g0
= fs_reg(retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_W
));
536 /* For (gl_FrontFacing ? 1.0 : -1.0), emit:
538 * or(8) tmp.1<2>W g0.0<0,1,0>W 0x00003f80W
539 * and(8) dst<1>D tmp<8,8,1>D 0xbf800000D
541 * and negate g0.0<0,1,0>W for (gl_FrontFacing ? -1.0 : 1.0).
543 * This negation looks like it's safe in practice, because bits 0:4 will
544 * surely be TRIANGLES
547 if (value1
->f32
[0] == -1.0f
) {
551 bld
.OR(subscript(tmp
, BRW_REGISTER_TYPE_W
, 1),
552 g0
, brw_imm_uw(0x3f80));
554 /* Bit 31 of g1.6 is 0 if the polygon is front facing. */
555 fs_reg g1_6
= fs_reg(retype(brw_vec1_grf(1, 6), BRW_REGISTER_TYPE_D
));
557 /* For (gl_FrontFacing ? 1.0 : -1.0), emit:
559 * or(8) tmp<1>D g1.6<0,1,0>D 0x3f800000D
560 * and(8) dst<1>D tmp<8,8,1>D 0xbf800000D
562 * and negate g1.6<0,1,0>D for (gl_FrontFacing ? -1.0 : 1.0).
564 * This negation looks like it's safe in practice, because bits 0:4 will
565 * surely be TRIANGLES
568 if (value1
->f32
[0] == -1.0f
) {
572 bld
.OR(tmp
, g1_6
, brw_imm_d(0x3f800000));
574 bld
.AND(retype(result
, BRW_REGISTER_TYPE_D
), tmp
, brw_imm_d(0xbf800000));
580 emit_find_msb_using_lzd(const fs_builder
&bld
,
581 const fs_reg
&result
,
589 /* LZD of an absolute value source almost always does the right
590 * thing. There are two problem values:
592 * * 0x80000000. Since abs(0x80000000) == 0x80000000, LZD returns
593 * 0. However, findMSB(int(0x80000000)) == 30.
595 * * 0xffffffff. Since abs(0xffffffff) == 1, LZD returns
596 * 31. Section 8.8 (Integer Functions) of the GLSL 4.50 spec says:
598 * For a value of zero or negative one, -1 will be returned.
600 * * Negative powers of two. LZD(abs(-(1<<x))) returns x, but
601 * findMSB(-(1<<x)) should return x-1.
603 * For all negative number cases, including 0x80000000 and
604 * 0xffffffff, the correct value is obtained from LZD if instead of
605 * negating the (already negative) value the logical-not is used. A
606 * conditonal logical-not can be achieved in two instructions.
608 temp
= bld
.vgrf(BRW_REGISTER_TYPE_D
);
610 bld
.ASR(temp
, src
, brw_imm_d(31));
611 bld
.XOR(temp
, temp
, src
);
614 bld
.LZD(retype(result
, BRW_REGISTER_TYPE_UD
),
615 retype(temp
, BRW_REGISTER_TYPE_UD
));
617 /* LZD counts from the MSB side, while GLSL's findMSB() wants the count
618 * from the LSB side. Subtract the result from 31 to convert the MSB
619 * count into an LSB count. If no bits are set, LZD will return 32.
620 * 31-32 = -1, which is exactly what findMSB() is supposed to return.
622 inst
= bld
.ADD(result
, retype(result
, BRW_REGISTER_TYPE_D
), brw_imm_d(31));
623 inst
->src
[0].negate
= true;
627 brw_rnd_mode_from_nir_op (const nir_op op
) {
629 case nir_op_f2f16_rtz
:
630 return BRW_RND_MODE_RTZ
;
631 case nir_op_f2f16_rtne
:
632 return BRW_RND_MODE_RTNE
;
634 unreachable("Operation doesn't support rounding mode");
639 fs_visitor::nir_emit_alu(const fs_builder
&bld
, nir_alu_instr
*instr
)
641 struct brw_wm_prog_key
*fs_key
= (struct brw_wm_prog_key
*) this->key
;
644 fs_reg result
= get_nir_dest(instr
->dest
.dest
);
645 result
.type
= brw_type_for_nir_type(devinfo
,
646 (nir_alu_type
)(nir_op_infos
[instr
->op
].output_type
|
647 nir_dest_bit_size(instr
->dest
.dest
)));
650 for (unsigned i
= 0; i
< nir_op_infos
[instr
->op
].num_inputs
; i
++) {
651 op
[i
] = get_nir_src(instr
->src
[i
].src
);
652 op
[i
].type
= brw_type_for_nir_type(devinfo
,
653 (nir_alu_type
)(nir_op_infos
[instr
->op
].input_types
[i
] |
654 nir_src_bit_size(instr
->src
[i
].src
)));
655 op
[i
].abs
= instr
->src
[i
].abs
;
656 op
[i
].negate
= instr
->src
[i
].negate
;
659 /* We get a bunch of mov's out of the from_ssa pass and they may still
660 * be vectorized. We'll handle them as a special-case. We'll also
661 * handle vecN here because it's basically the same thing.
669 fs_reg temp
= result
;
670 bool need_extra_copy
= false;
671 for (unsigned i
= 0; i
< nir_op_infos
[instr
->op
].num_inputs
; i
++) {
672 if (!instr
->src
[i
].src
.is_ssa
&&
673 instr
->dest
.dest
.reg
.reg
== instr
->src
[i
].src
.reg
.reg
) {
674 need_extra_copy
= true;
675 temp
= bld
.vgrf(result
.type
, 4);
680 for (unsigned i
= 0; i
< 4; i
++) {
681 if (!(instr
->dest
.write_mask
& (1 << i
)))
684 if (instr
->op
== nir_op_imov
|| instr
->op
== nir_op_fmov
) {
685 inst
= bld
.MOV(offset(temp
, bld
, i
),
686 offset(op
[0], bld
, instr
->src
[0].swizzle
[i
]));
688 inst
= bld
.MOV(offset(temp
, bld
, i
),
689 offset(op
[i
], bld
, instr
->src
[i
].swizzle
[0]));
691 inst
->saturate
= instr
->dest
.saturate
;
694 /* In this case the source and destination registers were the same,
695 * so we need to insert an extra set of moves in order to deal with
698 if (need_extra_copy
) {
699 for (unsigned i
= 0; i
< 4; i
++) {
700 if (!(instr
->dest
.write_mask
& (1 << i
)))
703 bld
.MOV(offset(result
, bld
, i
), offset(temp
, bld
, i
));
712 /* At this point, we have dealt with any instruction that operates on
713 * more than a single channel. Therefore, we can just adjust the source
714 * and destination registers for that channel and emit the instruction.
716 unsigned channel
= 0;
717 if (nir_op_infos
[instr
->op
].output_size
== 0) {
718 /* Since NIR is doing the scalarizing for us, we should only ever see
719 * vectorized operations with a single channel.
721 assert(_mesa_bitcount(instr
->dest
.write_mask
) == 1);
722 channel
= ffs(instr
->dest
.write_mask
) - 1;
724 result
= offset(result
, bld
, channel
);
727 for (unsigned i
= 0; i
< nir_op_infos
[instr
->op
].num_inputs
; i
++) {
728 assert(nir_op_infos
[instr
->op
].input_sizes
[i
] < 2);
729 op
[i
] = offset(op
[i
], bld
, instr
->src
[i
].swizzle
[channel
]);
735 if (optimize_extract_to_float(instr
, result
))
737 inst
= bld
.MOV(result
, op
[0]);
738 inst
->saturate
= instr
->dest
.saturate
;
741 case nir_op_f2f16_rtne
:
742 case nir_op_f2f16_rtz
:
743 bld
.emit(SHADER_OPCODE_RND_MODE
, bld
.null_reg_ud(),
744 brw_imm_d(brw_rnd_mode_from_nir_op(instr
->op
)));
747 /* In theory, it would be better to use BRW_OPCODE_F32TO16. Depending
748 * on the HW gen, it is a special hw opcode or just a MOV, and
749 * brw_F32TO16 (at brw_eu_emit) would do the work to chose.
751 * But if we want to use that opcode, we need to provide support on
752 * different optimizations and lowerings. As right now HF support is
753 * only for gen8+, it will be better to use directly the MOV, and use
754 * BRW_OPCODE_F32TO16 when/if we work for HF support on gen7.
757 case nir_op_f2f16_undef
:
758 inst
= bld
.MOV(result
, op
[0]);
759 inst
->saturate
= instr
->dest
.saturate
;
769 /* CHV PRM, vol07, 3D Media GPGPU Engine, Register Region Restrictions:
771 * "When source or destination is 64b (...), regioning in Align1
772 * must follow these rules:
774 * 1. Source and destination horizontal stride must be aligned to
778 * This means that 32-bit to 64-bit conversions need to have the 32-bit
779 * data elements aligned to 64-bit. This restriction does not apply to
782 if (nir_dest_bit_size(instr
->dest
.dest
) == 64 &&
783 nir_src_bit_size(instr
->src
[0].src
) == 32 &&
784 (devinfo
->is_cherryview
|| gen_device_info_is_9lp(devinfo
))) {
785 fs_reg tmp
= bld
.vgrf(result
.type
, 1);
786 tmp
= subscript(tmp
, op
[0].type
, 0);
787 inst
= bld
.MOV(tmp
, op
[0]);
788 inst
= bld
.MOV(result
, tmp
);
789 inst
->saturate
= instr
->dest
.saturate
;
804 inst
= bld
.MOV(result
, op
[0]);
805 inst
->saturate
= instr
->dest
.saturate
;
810 /* Straightforward since the source can be assumed to be
813 set_condmod(BRW_CONDITIONAL_NZ
, bld
.MOV(result
, op
[0]));
814 set_predicate(BRW_PREDICATE_NORMAL
, bld
.MOV(result
, brw_imm_f(1.0f
)));
816 } else if (type_sz(op
[0].type
) < 8) {
817 /* AND(val, 0x80000000) gives the sign bit.
819 * Predicated OR ORs 1.0 (0x3f800000) with the sign bit if val is not
822 bld
.CMP(bld
.null_reg_f(), op
[0], brw_imm_f(0.0f
), BRW_CONDITIONAL_NZ
);
824 fs_reg result_int
= retype(result
, BRW_REGISTER_TYPE_UD
);
825 op
[0].type
= BRW_REGISTER_TYPE_UD
;
826 result
.type
= BRW_REGISTER_TYPE_UD
;
827 bld
.AND(result_int
, op
[0], brw_imm_ud(0x80000000u
));
829 inst
= bld
.OR(result_int
, result_int
, brw_imm_ud(0x3f800000u
));
830 inst
->predicate
= BRW_PREDICATE_NORMAL
;
831 if (instr
->dest
.saturate
) {
832 inst
= bld
.MOV(result
, result
);
833 inst
->saturate
= true;
836 /* For doubles we do the same but we need to consider:
838 * - 2-src instructions can't operate with 64-bit immediates
839 * - The sign is encoded in the high 32-bit of each DF
840 * - We need to produce a DF result.
843 fs_reg zero
= vgrf(glsl_type::double_type
);
844 bld
.MOV(zero
, setup_imm_df(bld
, 0.0));
845 bld
.CMP(bld
.null_reg_df(), op
[0], zero
, BRW_CONDITIONAL_NZ
);
847 bld
.MOV(result
, zero
);
849 fs_reg r
= subscript(result
, BRW_REGISTER_TYPE_UD
, 1);
850 bld
.AND(r
, subscript(op
[0], BRW_REGISTER_TYPE_UD
, 1),
851 brw_imm_ud(0x80000000u
));
853 set_predicate(BRW_PREDICATE_NORMAL
,
854 bld
.OR(r
, r
, brw_imm_ud(0x3ff00000u
)));
856 if (instr
->dest
.saturate
) {
857 inst
= bld
.MOV(result
, result
);
858 inst
->saturate
= true;
865 /* ASR(val, 31) -> negative val generates 0xffffffff (signed -1).
866 * -> non-negative val generates 0x00000000.
867 * Predicated OR sets 1 if val is positive.
869 uint32_t bit_size
= nir_dest_bit_size(instr
->dest
.dest
);
870 assert(bit_size
== 32 || bit_size
== 16);
872 fs_reg zero
= bit_size
== 32 ? brw_imm_d(0) : brw_imm_w(0);
873 fs_reg one
= bit_size
== 32 ? brw_imm_d(1) : brw_imm_w(1);
874 fs_reg shift
= bit_size
== 32 ? brw_imm_d(31) : brw_imm_w(15);
876 bld
.CMP(bld
.null_reg_d(), op
[0], zero
, BRW_CONDITIONAL_G
);
877 bld
.ASR(result
, op
[0], shift
);
878 inst
= bld
.OR(result
, result
, one
);
879 inst
->predicate
= BRW_PREDICATE_NORMAL
;
884 inst
= bld
.emit(SHADER_OPCODE_RCP
, result
, op
[0]);
885 inst
->saturate
= instr
->dest
.saturate
;
889 inst
= bld
.emit(SHADER_OPCODE_EXP2
, result
, op
[0]);
890 inst
->saturate
= instr
->dest
.saturate
;
894 inst
= bld
.emit(SHADER_OPCODE_LOG2
, result
, op
[0]);
895 inst
->saturate
= instr
->dest
.saturate
;
899 inst
= bld
.emit(SHADER_OPCODE_SIN
, result
, op
[0]);
900 inst
->saturate
= instr
->dest
.saturate
;
904 inst
= bld
.emit(SHADER_OPCODE_COS
, result
, op
[0]);
905 inst
->saturate
= instr
->dest
.saturate
;
909 if (fs_key
->high_quality_derivatives
) {
910 inst
= bld
.emit(FS_OPCODE_DDX_FINE
, result
, op
[0]);
912 inst
= bld
.emit(FS_OPCODE_DDX_COARSE
, result
, op
[0]);
914 inst
->saturate
= instr
->dest
.saturate
;
916 case nir_op_fddx_fine
:
917 inst
= bld
.emit(FS_OPCODE_DDX_FINE
, result
, op
[0]);
918 inst
->saturate
= instr
->dest
.saturate
;
920 case nir_op_fddx_coarse
:
921 inst
= bld
.emit(FS_OPCODE_DDX_COARSE
, result
, op
[0]);
922 inst
->saturate
= instr
->dest
.saturate
;
925 if (fs_key
->high_quality_derivatives
) {
926 inst
= bld
.emit(FS_OPCODE_DDY_FINE
, result
, op
[0]);
928 inst
= bld
.emit(FS_OPCODE_DDY_COARSE
, result
, op
[0]);
930 inst
->saturate
= instr
->dest
.saturate
;
932 case nir_op_fddy_fine
:
933 inst
= bld
.emit(FS_OPCODE_DDY_FINE
, result
, op
[0]);
934 inst
->saturate
= instr
->dest
.saturate
;
936 case nir_op_fddy_coarse
:
937 inst
= bld
.emit(FS_OPCODE_DDY_COARSE
, result
, op
[0]);
938 inst
->saturate
= instr
->dest
.saturate
;
943 inst
= bld
.ADD(result
, op
[0], op
[1]);
944 inst
->saturate
= instr
->dest
.saturate
;
948 inst
= bld
.MUL(result
, op
[0], op
[1]);
949 inst
->saturate
= instr
->dest
.saturate
;
953 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
954 bld
.MUL(result
, op
[0], op
[1]);
957 case nir_op_imul_high
:
958 case nir_op_umul_high
:
959 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
960 bld
.emit(SHADER_OPCODE_MULH
, result
, op
[0], op
[1]);
965 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
966 bld
.emit(SHADER_OPCODE_INT_QUOTIENT
, result
, op
[0], op
[1]);
969 case nir_op_uadd_carry
:
970 unreachable("Should have been lowered by carry_to_arith().");
972 case nir_op_usub_borrow
:
973 unreachable("Should have been lowered by borrow_to_arith().");
977 /* According to the sign table for INT DIV in the Ivy Bridge PRM, it
978 * appears that our hardware just does the right thing for signed
981 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
982 bld
.emit(SHADER_OPCODE_INT_REMAINDER
, result
, op
[0], op
[1]);
986 /* Get a regular C-style remainder. If a % b == 0, set the predicate. */
987 bld
.emit(SHADER_OPCODE_INT_REMAINDER
, result
, op
[0], op
[1]);
989 /* Math instructions don't support conditional mod */
990 inst
= bld
.MOV(bld
.null_reg_d(), result
);
991 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
993 /* Now, we need to determine if signs of the sources are different.
994 * When we XOR the sources, the top bit is 0 if they are the same and 1
995 * if they are different. We can then use a conditional modifier to
996 * turn that into a predicate. This leads us to an XOR.l instruction.
998 * Technically, according to the PRM, you're not allowed to use .l on a
999 * XOR instruction. However, emperical experiments and Curro's reading
1000 * of the simulator source both indicate that it's safe.
1002 fs_reg tmp
= bld
.vgrf(BRW_REGISTER_TYPE_D
);
1003 inst
= bld
.XOR(tmp
, op
[0], op
[1]);
1004 inst
->predicate
= BRW_PREDICATE_NORMAL
;
1005 inst
->conditional_mod
= BRW_CONDITIONAL_L
;
1007 /* If the result of the initial remainder operation is non-zero and the
1008 * two sources have different signs, add in a copy of op[1] to get the
1009 * final integer modulus value.
1011 inst
= bld
.ADD(result
, result
, op
[1]);
1012 inst
->predicate
= BRW_PREDICATE_NORMAL
;
1020 fs_reg dest
= result
;
1021 if (nir_src_bit_size(instr
->src
[0].src
) > 32) {
1022 dest
= bld
.vgrf(BRW_REGISTER_TYPE_DF
, 1);
1024 brw_conditional_mod cond
;
1025 switch (instr
->op
) {
1027 cond
= BRW_CONDITIONAL_L
;
1030 cond
= BRW_CONDITIONAL_GE
;
1033 cond
= BRW_CONDITIONAL_Z
;
1036 cond
= BRW_CONDITIONAL_NZ
;
1039 unreachable("bad opcode");
1041 bld
.CMP(dest
, op
[0], op
[1], cond
);
1042 if (nir_src_bit_size(instr
->src
[0].src
) > 32) {
1043 bld
.MOV(result
, subscript(dest
, BRW_REGISTER_TYPE_UD
, 0));
1054 fs_reg dest
= result
;
1055 if (nir_src_bit_size(instr
->src
[0].src
) > 32) {
1056 dest
= bld
.vgrf(BRW_REGISTER_TYPE_UQ
, 1);
1059 brw_conditional_mod cond
;
1060 switch (instr
->op
) {
1063 cond
= BRW_CONDITIONAL_L
;
1067 cond
= BRW_CONDITIONAL_GE
;
1070 cond
= BRW_CONDITIONAL_Z
;
1073 cond
= BRW_CONDITIONAL_NZ
;
1076 unreachable("bad opcode");
1078 bld
.CMP(dest
, op
[0], op
[1], cond
);
1079 if (nir_src_bit_size(instr
->src
[0].src
) > 32) {
1080 bld
.MOV(result
, subscript(dest
, BRW_REGISTER_TYPE_UD
, 0));
1086 if (devinfo
->gen
>= 8) {
1087 op
[0] = resolve_source_modifiers(op
[0]);
1089 bld
.NOT(result
, op
[0]);
1092 if (devinfo
->gen
>= 8) {
1093 op
[0] = resolve_source_modifiers(op
[0]);
1094 op
[1] = resolve_source_modifiers(op
[1]);
1096 bld
.XOR(result
, op
[0], op
[1]);
1099 if (devinfo
->gen
>= 8) {
1100 op
[0] = resolve_source_modifiers(op
[0]);
1101 op
[1] = resolve_source_modifiers(op
[1]);
1103 bld
.OR(result
, op
[0], op
[1]);
1106 if (devinfo
->gen
>= 8) {
1107 op
[0] = resolve_source_modifiers(op
[0]);
1108 op
[1] = resolve_source_modifiers(op
[1]);
1110 bld
.AND(result
, op
[0], op
[1]);
1116 case nir_op_ball_fequal2
:
1117 case nir_op_ball_iequal2
:
1118 case nir_op_ball_fequal3
:
1119 case nir_op_ball_iequal3
:
1120 case nir_op_ball_fequal4
:
1121 case nir_op_ball_iequal4
:
1122 case nir_op_bany_fnequal2
:
1123 case nir_op_bany_inequal2
:
1124 case nir_op_bany_fnequal3
:
1125 case nir_op_bany_inequal3
:
1126 case nir_op_bany_fnequal4
:
1127 case nir_op_bany_inequal4
:
1128 unreachable("Lowered by nir_lower_alu_reductions");
1130 case nir_op_fnoise1_1
:
1131 case nir_op_fnoise1_2
:
1132 case nir_op_fnoise1_3
:
1133 case nir_op_fnoise1_4
:
1134 case nir_op_fnoise2_1
:
1135 case nir_op_fnoise2_2
:
1136 case nir_op_fnoise2_3
:
1137 case nir_op_fnoise2_4
:
1138 case nir_op_fnoise3_1
:
1139 case nir_op_fnoise3_2
:
1140 case nir_op_fnoise3_3
:
1141 case nir_op_fnoise3_4
:
1142 case nir_op_fnoise4_1
:
1143 case nir_op_fnoise4_2
:
1144 case nir_op_fnoise4_3
:
1145 case nir_op_fnoise4_4
:
1146 unreachable("not reached: should be handled by lower_noise");
1149 unreachable("not reached: should be handled by ldexp_to_arith()");
1152 inst
= bld
.emit(SHADER_OPCODE_SQRT
, result
, op
[0]);
1153 inst
->saturate
= instr
->dest
.saturate
;
1157 inst
= bld
.emit(SHADER_OPCODE_RSQ
, result
, op
[0]);
1158 inst
->saturate
= instr
->dest
.saturate
;
1163 bld
.MOV(result
, negate(op
[0]));
1168 if (nir_src_bit_size(instr
->src
[0].src
) == 64) {
1169 /* two-argument instructions can't take 64-bit immediates */
1173 if (instr
->op
== nir_op_f2b
) {
1174 zero
= vgrf(glsl_type::double_type
);
1175 tmp
= vgrf(glsl_type::double_type
);
1176 bld
.MOV(zero
, setup_imm_df(bld
, 0.0));
1178 zero
= vgrf(glsl_type::int64_t_type
);
1179 tmp
= vgrf(glsl_type::int64_t_type
);
1180 bld
.MOV(zero
, brw_imm_q(0));
1183 /* A SIMD16 execution needs to be split in two instructions, so use
1184 * a vgrf instead of the flag register as dst so instruction splitting
1187 bld
.CMP(tmp
, op
[0], zero
, BRW_CONDITIONAL_NZ
);
1188 bld
.MOV(result
, subscript(tmp
, BRW_REGISTER_TYPE_UD
, 0));
1190 if (instr
->op
== nir_op_f2b
) {
1191 bld
.CMP(result
, op
[0], brw_imm_f(0.0f
), BRW_CONDITIONAL_NZ
);
1193 bld
.CMP(result
, op
[0], brw_imm_d(0), BRW_CONDITIONAL_NZ
);
1199 inst
= bld
.RNDZ(result
, op
[0]);
1200 inst
->saturate
= instr
->dest
.saturate
;
1203 case nir_op_fceil
: {
1204 op
[0].negate
= !op
[0].negate
;
1205 fs_reg temp
= vgrf(glsl_type::float_type
);
1206 bld
.RNDD(temp
, op
[0]);
1208 inst
= bld
.MOV(result
, temp
);
1209 inst
->saturate
= instr
->dest
.saturate
;
1213 inst
= bld
.RNDD(result
, op
[0]);
1214 inst
->saturate
= instr
->dest
.saturate
;
1217 inst
= bld
.FRC(result
, op
[0]);
1218 inst
->saturate
= instr
->dest
.saturate
;
1220 case nir_op_fround_even
:
1221 inst
= bld
.RNDE(result
, op
[0]);
1222 inst
->saturate
= instr
->dest
.saturate
;
1225 case nir_op_fquantize2f16
: {
1226 fs_reg tmp16
= bld
.vgrf(BRW_REGISTER_TYPE_D
);
1227 fs_reg tmp32
= bld
.vgrf(BRW_REGISTER_TYPE_F
);
1228 fs_reg zero
= bld
.vgrf(BRW_REGISTER_TYPE_F
);
1230 /* The destination stride must be at least as big as the source stride. */
1231 tmp16
.type
= BRW_REGISTER_TYPE_W
;
1234 /* Check for denormal */
1235 fs_reg abs_src0
= op
[0];
1236 abs_src0
.abs
= true;
1237 bld
.CMP(bld
.null_reg_f(), abs_src0
, brw_imm_f(ldexpf(1.0, -14)),
1239 /* Get the appropriately signed zero */
1240 bld
.AND(retype(zero
, BRW_REGISTER_TYPE_UD
),
1241 retype(op
[0], BRW_REGISTER_TYPE_UD
),
1242 brw_imm_ud(0x80000000));
1243 /* Do the actual F32 -> F16 -> F32 conversion */
1244 bld
.emit(BRW_OPCODE_F32TO16
, tmp16
, op
[0]);
1245 bld
.emit(BRW_OPCODE_F16TO32
, tmp32
, tmp16
);
1246 /* Select that or zero based on normal status */
1247 inst
= bld
.SEL(result
, zero
, tmp32
);
1248 inst
->predicate
= BRW_PREDICATE_NORMAL
;
1249 inst
->saturate
= instr
->dest
.saturate
;
1256 inst
= bld
.emit_minmax(result
, op
[0], op
[1], BRW_CONDITIONAL_L
);
1257 inst
->saturate
= instr
->dest
.saturate
;
1263 inst
= bld
.emit_minmax(result
, op
[0], op
[1], BRW_CONDITIONAL_GE
);
1264 inst
->saturate
= instr
->dest
.saturate
;
1267 case nir_op_pack_snorm_2x16
:
1268 case nir_op_pack_snorm_4x8
:
1269 case nir_op_pack_unorm_2x16
:
1270 case nir_op_pack_unorm_4x8
:
1271 case nir_op_unpack_snorm_2x16
:
1272 case nir_op_unpack_snorm_4x8
:
1273 case nir_op_unpack_unorm_2x16
:
1274 case nir_op_unpack_unorm_4x8
:
1275 case nir_op_unpack_half_2x16
:
1276 case nir_op_pack_half_2x16
:
1277 unreachable("not reached: should be handled by lower_packing_builtins");
1279 case nir_op_unpack_half_2x16_split_x
:
1280 inst
= bld
.emit(FS_OPCODE_UNPACK_HALF_2x16_SPLIT_X
, result
, op
[0]);
1281 inst
->saturate
= instr
->dest
.saturate
;
1283 case nir_op_unpack_half_2x16_split_y
:
1284 inst
= bld
.emit(FS_OPCODE_UNPACK_HALF_2x16_SPLIT_Y
, result
, op
[0]);
1285 inst
->saturate
= instr
->dest
.saturate
;
1288 case nir_op_pack_64_2x32_split
:
1289 bld
.emit(FS_OPCODE_PACK
, result
, op
[0], op
[1]);
1292 case nir_op_unpack_64_2x32_split_x
:
1293 case nir_op_unpack_64_2x32_split_y
: {
1294 if (instr
->op
== nir_op_unpack_64_2x32_split_x
)
1295 bld
.MOV(result
, subscript(op
[0], BRW_REGISTER_TYPE_UD
, 0));
1297 bld
.MOV(result
, subscript(op
[0], BRW_REGISTER_TYPE_UD
, 1));
1302 inst
= bld
.emit(SHADER_OPCODE_POW
, result
, op
[0], op
[1]);
1303 inst
->saturate
= instr
->dest
.saturate
;
1306 case nir_op_bitfield_reverse
:
1307 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1308 bld
.BFREV(result
, op
[0]);
1311 case nir_op_bit_count
:
1312 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1313 bld
.CBIT(result
, op
[0]);
1316 case nir_op_ufind_msb
: {
1317 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1318 emit_find_msb_using_lzd(bld
, result
, op
[0], false);
1322 case nir_op_ifind_msb
: {
1323 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1325 if (devinfo
->gen
< 7) {
1326 emit_find_msb_using_lzd(bld
, result
, op
[0], true);
1328 bld
.FBH(retype(result
, BRW_REGISTER_TYPE_UD
), op
[0]);
1330 /* FBH counts from the MSB side, while GLSL's findMSB() wants the
1331 * count from the LSB side. If FBH didn't return an error
1332 * (0xFFFFFFFF), then subtract the result from 31 to convert the MSB
1333 * count into an LSB count.
1335 bld
.CMP(bld
.null_reg_d(), result
, brw_imm_d(-1), BRW_CONDITIONAL_NZ
);
1337 inst
= bld
.ADD(result
, result
, brw_imm_d(31));
1338 inst
->predicate
= BRW_PREDICATE_NORMAL
;
1339 inst
->src
[0].negate
= true;
1344 case nir_op_find_lsb
:
1345 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1347 if (devinfo
->gen
< 7) {
1348 fs_reg temp
= vgrf(glsl_type::int_type
);
1350 /* (x & -x) generates a value that consists of only the LSB of x.
1351 * For all powers of 2, findMSB(y) == findLSB(y).
1353 fs_reg src
= retype(op
[0], BRW_REGISTER_TYPE_D
);
1354 fs_reg negated_src
= src
;
1356 /* One must be negated, and the other must be non-negated. It
1357 * doesn't matter which is which.
1359 negated_src
.negate
= true;
1362 bld
.AND(temp
, src
, negated_src
);
1363 emit_find_msb_using_lzd(bld
, result
, temp
, false);
1365 bld
.FBL(result
, op
[0]);
1369 case nir_op_ubitfield_extract
:
1370 case nir_op_ibitfield_extract
:
1371 unreachable("should have been lowered");
1374 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1375 bld
.BFE(result
, op
[2], op
[1], op
[0]);
1378 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1379 bld
.BFI1(result
, op
[0], op
[1]);
1382 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1383 bld
.BFI2(result
, op
[0], op
[1], op
[2]);
1386 case nir_op_bitfield_insert
:
1387 unreachable("not reached: should have been lowered");
1392 fs_reg shift_count
= op
[1];
1394 if (devinfo
->is_cherryview
|| gen_device_info_is_9lp(devinfo
)) {
1395 if (op
[1].file
== VGRF
&&
1396 (result
.type
== BRW_REGISTER_TYPE_Q
||
1397 result
.type
== BRW_REGISTER_TYPE_UQ
)) {
1398 shift_count
= fs_reg(VGRF
, alloc
.allocate(dispatch_width
/ 4),
1399 BRW_REGISTER_TYPE_UD
);
1400 shift_count
.stride
= 2;
1401 bld
.MOV(shift_count
, op
[1]);
1405 switch (instr
->op
) {
1407 bld
.SHL(result
, op
[0], shift_count
);
1410 bld
.ASR(result
, op
[0], shift_count
);
1413 bld
.SHR(result
, op
[0], shift_count
);
1416 unreachable("not reached");
1421 case nir_op_pack_half_2x16_split
:
1422 bld
.emit(FS_OPCODE_PACK_HALF_2x16_SPLIT
, result
, op
[0], op
[1]);
1426 inst
= bld
.MAD(result
, op
[2], op
[1], op
[0]);
1427 inst
->saturate
= instr
->dest
.saturate
;
1431 inst
= bld
.LRP(result
, op
[0], op
[1], op
[2]);
1432 inst
->saturate
= instr
->dest
.saturate
;
1436 if (optimize_frontfacing_ternary(instr
, result
))
1439 bld
.CMP(bld
.null_reg_d(), op
[0], brw_imm_d(0), BRW_CONDITIONAL_NZ
);
1440 inst
= bld
.SEL(result
, op
[1], op
[2]);
1441 inst
->predicate
= BRW_PREDICATE_NORMAL
;
1444 case nir_op_extract_u8
:
1445 case nir_op_extract_i8
: {
1446 nir_const_value
*byte
= nir_src_as_const_value(instr
->src
[1].src
);
1447 assert(byte
!= NULL
);
1452 * There is no direct conversion from B/UB to Q/UQ or Q/UQ to B/UB.
1453 * Use two instructions and a word or DWord intermediate integer type.
1455 if (nir_dest_bit_size(instr
->dest
.dest
) == 64) {
1456 const brw_reg_type type
= brw_int_type(2, instr
->op
== nir_op_extract_i8
);
1458 if (instr
->op
== nir_op_extract_i8
) {
1459 /* If we need to sign extend, extract to a word first */
1460 fs_reg w_temp
= bld
.vgrf(BRW_REGISTER_TYPE_W
);
1461 bld
.MOV(w_temp
, subscript(op
[0], type
, byte
->u32
[0]));
1462 bld
.MOV(result
, w_temp
);
1464 /* Otherwise use an AND with 0xff and a word type */
1465 bld
.AND(result
, subscript(op
[0], type
, byte
->u32
[0] / 2), brw_imm_uw(0xff));
1468 const brw_reg_type type
= brw_int_type(1, instr
->op
== nir_op_extract_i8
);
1469 bld
.MOV(result
, subscript(op
[0], type
, byte
->u32
[0]));
1474 case nir_op_extract_u16
:
1475 case nir_op_extract_i16
: {
1476 const brw_reg_type type
= brw_int_type(2, instr
->op
== nir_op_extract_i16
);
1477 nir_const_value
*word
= nir_src_as_const_value(instr
->src
[1].src
);
1478 assert(word
!= NULL
);
1479 bld
.MOV(result
, subscript(op
[0], type
, word
->u32
[0]));
1484 unreachable("unhandled instruction");
1487 /* If we need to do a boolean resolve, replace the result with -(x & 1)
1488 * to sign extend the low bit to 0/~0
1490 if (devinfo
->gen
<= 5 &&
1491 (instr
->instr
.pass_flags
& BRW_NIR_BOOLEAN_MASK
) == BRW_NIR_BOOLEAN_NEEDS_RESOLVE
) {
1492 fs_reg masked
= vgrf(glsl_type::int_type
);
1493 bld
.AND(masked
, result
, brw_imm_d(1));
1494 masked
.negate
= true;
1495 bld
.MOV(retype(result
, BRW_REGISTER_TYPE_D
), masked
);
1500 fs_visitor::nir_emit_load_const(const fs_builder
&bld
,
1501 nir_load_const_instr
*instr
)
1503 const brw_reg_type reg_type
=
1504 brw_reg_type_from_bit_size(instr
->def
.bit_size
, BRW_REGISTER_TYPE_D
);
1505 fs_reg reg
= bld
.vgrf(reg_type
, instr
->def
.num_components
);
1507 switch (instr
->def
.bit_size
) {
1509 for (unsigned i
= 0; i
< instr
->def
.num_components
; i
++)
1510 bld
.MOV(offset(reg
, bld
, i
), brw_imm_d(instr
->value
.i32
[i
]));
1514 assert(devinfo
->gen
>= 7);
1515 if (devinfo
->gen
== 7) {
1516 /* We don't get 64-bit integer types until gen8 */
1517 for (unsigned i
= 0; i
< instr
->def
.num_components
; i
++) {
1518 bld
.MOV(retype(offset(reg
, bld
, i
), BRW_REGISTER_TYPE_DF
),
1519 setup_imm_df(bld
, instr
->value
.f64
[i
]));
1522 for (unsigned i
= 0; i
< instr
->def
.num_components
; i
++)
1523 bld
.MOV(offset(reg
, bld
, i
), brw_imm_q(instr
->value
.i64
[i
]));
1528 unreachable("Invalid bit size");
1531 nir_ssa_values
[instr
->def
.index
] = reg
;
1535 fs_visitor::get_nir_src(const nir_src
&src
)
1539 if (src
.ssa
->parent_instr
->type
== nir_instr_type_ssa_undef
) {
1540 const brw_reg_type reg_type
=
1541 brw_reg_type_from_bit_size(src
.ssa
->bit_size
, BRW_REGISTER_TYPE_D
);
1542 reg
= bld
.vgrf(reg_type
, src
.ssa
->num_components
);
1544 reg
= nir_ssa_values
[src
.ssa
->index
];
1547 /* We don't handle indirects on locals */
1548 assert(src
.reg
.indirect
== NULL
);
1549 reg
= offset(nir_locals
[src
.reg
.reg
->index
], bld
,
1550 src
.reg
.base_offset
* src
.reg
.reg
->num_components
);
1553 if (nir_src_bit_size(src
) == 64 && devinfo
->gen
== 7) {
1554 /* The only 64-bit type available on gen7 is DF, so use that. */
1555 reg
.type
= BRW_REGISTER_TYPE_DF
;
1557 /* To avoid floating-point denorm flushing problems, set the type by
1558 * default to an integer type - instructions that need floating point
1559 * semantics will set this to F if they need to
1561 reg
.type
= brw_reg_type_from_bit_size(nir_src_bit_size(src
),
1562 BRW_REGISTER_TYPE_D
);
1569 * Return an IMM for constants; otherwise call get_nir_src() as normal.
1571 * This function should not be called on any value which may be 64 bits.
1572 * We could theoretically support 64-bit on gen8+ but we choose not to
1573 * because it wouldn't work in general (no gen7 support) and there are
1574 * enough restrictions in 64-bit immediates that you can't take the return
1575 * value and treat it the same as the result of get_nir_src().
1578 fs_visitor::get_nir_src_imm(const nir_src
&src
)
1580 nir_const_value
*val
= nir_src_as_const_value(src
);
1581 assert(nir_src_bit_size(src
) == 32);
1582 return val
? fs_reg(brw_imm_d(val
->i32
[0])) : get_nir_src(src
);
1586 fs_visitor::get_nir_dest(const nir_dest
&dest
)
1589 const brw_reg_type reg_type
=
1590 brw_reg_type_from_bit_size(dest
.ssa
.bit_size
, BRW_REGISTER_TYPE_F
);
1591 nir_ssa_values
[dest
.ssa
.index
] =
1592 bld
.vgrf(reg_type
, dest
.ssa
.num_components
);
1593 return nir_ssa_values
[dest
.ssa
.index
];
1595 /* We don't handle indirects on locals */
1596 assert(dest
.reg
.indirect
== NULL
);
1597 return offset(nir_locals
[dest
.reg
.reg
->index
], bld
,
1598 dest
.reg
.base_offset
* dest
.reg
.reg
->num_components
);
1603 fs_visitor::get_nir_image_deref(const nir_deref_var
*deref
)
1605 fs_reg
image(UNIFORM
, deref
->var
->data
.driver_location
/ 4,
1606 BRW_REGISTER_TYPE_UD
);
1608 unsigned indirect_max
= 0;
1610 for (const nir_deref
*tail
= &deref
->deref
; tail
->child
;
1611 tail
= tail
->child
) {
1612 const nir_deref_array
*deref_array
= nir_deref_as_array(tail
->child
);
1613 assert(tail
->child
->deref_type
== nir_deref_type_array
);
1614 const unsigned size
= glsl_get_length(tail
->type
);
1615 const unsigned element_size
= type_size_scalar(deref_array
->deref
.type
);
1616 const unsigned base
= MIN2(deref_array
->base_offset
, size
- 1);
1617 image
= offset(image
, bld
, base
* element_size
);
1619 if (deref_array
->deref_array_type
== nir_deref_array_type_indirect
) {
1620 fs_reg tmp
= vgrf(glsl_type::uint_type
);
1622 /* Accessing an invalid surface index with the dataport can result
1623 * in a hang. According to the spec "if the index used to
1624 * select an individual element is negative or greater than or
1625 * equal to the size of the array, the results of the operation
1626 * are undefined but may not lead to termination" -- which is one
1627 * of the possible outcomes of the hang. Clamp the index to
1628 * prevent access outside of the array bounds.
1630 bld
.emit_minmax(tmp
, retype(get_nir_src(deref_array
->indirect
),
1631 BRW_REGISTER_TYPE_UD
),
1632 brw_imm_ud(size
- base
- 1), BRW_CONDITIONAL_L
);
1634 indirect_max
+= element_size
* (tail
->type
->length
- 1);
1636 bld
.MUL(tmp
, tmp
, brw_imm_ud(element_size
* 4));
1637 if (indirect
.file
== BAD_FILE
) {
1640 bld
.ADD(indirect
, indirect
, tmp
);
1645 if (indirect
.file
== BAD_FILE
) {
1648 /* Emit a pile of MOVs to load the uniform into a temporary. The
1649 * dead-code elimination pass will get rid of what we don't use.
1651 fs_reg tmp
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, BRW_IMAGE_PARAM_SIZE
);
1652 for (unsigned j
= 0; j
< BRW_IMAGE_PARAM_SIZE
; j
++) {
1653 bld
.emit(SHADER_OPCODE_MOV_INDIRECT
,
1654 offset(tmp
, bld
, j
), offset(image
, bld
, j
),
1655 indirect
, brw_imm_ud((indirect_max
+ 1) * 4));
1662 fs_visitor::emit_percomp(const fs_builder
&bld
, const fs_inst
&inst
,
1665 for (unsigned i
= 0; i
< 4; i
++) {
1666 if (!((wr_mask
>> i
) & 1))
1669 fs_inst
*new_inst
= new(mem_ctx
) fs_inst(inst
);
1670 new_inst
->dst
= offset(new_inst
->dst
, bld
, i
);
1671 for (unsigned j
= 0; j
< new_inst
->sources
; j
++)
1672 if (new_inst
->src
[j
].file
== VGRF
)
1673 new_inst
->src
[j
] = offset(new_inst
->src
[j
], bld
, i
);
1680 * Get the matching channel register datatype for an image intrinsic of the
1681 * specified GLSL image type.
1684 get_image_base_type(const glsl_type
*type
)
1686 switch ((glsl_base_type
)type
->sampled_type
) {
1687 case GLSL_TYPE_UINT
:
1688 return BRW_REGISTER_TYPE_UD
;
1690 return BRW_REGISTER_TYPE_D
;
1691 case GLSL_TYPE_FLOAT
:
1692 return BRW_REGISTER_TYPE_F
;
1694 unreachable("Not reached.");
1699 * Get the appropriate atomic op for an image atomic intrinsic.
1702 get_image_atomic_op(nir_intrinsic_op op
, const glsl_type
*type
)
1705 case nir_intrinsic_image_var_atomic_add
:
1707 case nir_intrinsic_image_var_atomic_min
:
1708 return (get_image_base_type(type
) == BRW_REGISTER_TYPE_D
?
1709 BRW_AOP_IMIN
: BRW_AOP_UMIN
);
1710 case nir_intrinsic_image_var_atomic_max
:
1711 return (get_image_base_type(type
) == BRW_REGISTER_TYPE_D
?
1712 BRW_AOP_IMAX
: BRW_AOP_UMAX
);
1713 case nir_intrinsic_image_var_atomic_and
:
1715 case nir_intrinsic_image_var_atomic_or
:
1717 case nir_intrinsic_image_var_atomic_xor
:
1719 case nir_intrinsic_image_var_atomic_exchange
:
1721 case nir_intrinsic_image_var_atomic_comp_swap
:
1722 return BRW_AOP_CMPWR
;
1724 unreachable("Not reachable.");
1729 emit_pixel_interpolater_send(const fs_builder
&bld
,
1734 glsl_interp_mode interpolation
)
1736 struct brw_wm_prog_data
*wm_prog_data
=
1737 brw_wm_prog_data(bld
.shader
->stage_prog_data
);
1742 if (src
.file
== BAD_FILE
) {
1744 payload
= bld
.vgrf(BRW_REGISTER_TYPE_F
, 1);
1748 mlen
= 2 * bld
.dispatch_width() / 8;
1751 inst
= bld
.emit(opcode
, dst
, payload
, desc
);
1753 /* 2 floats per slot returned */
1754 inst
->size_written
= 2 * dst
.component_size(inst
->exec_size
);
1755 inst
->pi_noperspective
= interpolation
== INTERP_MODE_NOPERSPECTIVE
;
1757 wm_prog_data
->pulls_bary
= true;
1763 * Computes 1 << x, given a D/UD register containing some value x.
1766 intexp2(const fs_builder
&bld
, const fs_reg
&x
)
1768 assert(x
.type
== BRW_REGISTER_TYPE_UD
|| x
.type
== BRW_REGISTER_TYPE_D
);
1770 fs_reg result
= bld
.vgrf(x
.type
, 1);
1771 fs_reg one
= bld
.vgrf(x
.type
, 1);
1773 bld
.MOV(one
, retype(brw_imm_d(1), one
.type
));
1774 bld
.SHL(result
, one
, x
);
1779 fs_visitor::emit_gs_end_primitive(const nir_src
&vertex_count_nir_src
)
1781 assert(stage
== MESA_SHADER_GEOMETRY
);
1783 struct brw_gs_prog_data
*gs_prog_data
= brw_gs_prog_data(prog_data
);
1785 if (gs_compile
->control_data_header_size_bits
== 0)
1788 /* We can only do EndPrimitive() functionality when the control data
1789 * consists of cut bits. Fortunately, the only time it isn't is when the
1790 * output type is points, in which case EndPrimitive() is a no-op.
1792 if (gs_prog_data
->control_data_format
!=
1793 GEN7_GS_CONTROL_DATA_FORMAT_GSCTL_CUT
) {
1797 /* Cut bits use one bit per vertex. */
1798 assert(gs_compile
->control_data_bits_per_vertex
== 1);
1800 fs_reg vertex_count
= get_nir_src(vertex_count_nir_src
);
1801 vertex_count
.type
= BRW_REGISTER_TYPE_UD
;
1803 /* Cut bit n should be set to 1 if EndPrimitive() was called after emitting
1804 * vertex n, 0 otherwise. So all we need to do here is mark bit
1805 * (vertex_count - 1) % 32 in the cut_bits register to indicate that
1806 * EndPrimitive() was called after emitting vertex (vertex_count - 1);
1807 * vec4_gs_visitor::emit_control_data_bits() will take care of the rest.
1809 * Note that if EndPrimitive() is called before emitting any vertices, this
1810 * will cause us to set bit 31 of the control_data_bits register to 1.
1811 * That's fine because:
1813 * - If max_vertices < 32, then vertex number 31 (zero-based) will never be
1814 * output, so the hardware will ignore cut bit 31.
1816 * - If max_vertices == 32, then vertex number 31 is guaranteed to be the
1817 * last vertex, so setting cut bit 31 has no effect (since the primitive
1818 * is automatically ended when the GS terminates).
1820 * - If max_vertices > 32, then the ir_emit_vertex visitor will reset the
1821 * control_data_bits register to 0 when the first vertex is emitted.
1824 const fs_builder abld
= bld
.annotate("end primitive");
1826 /* control_data_bits |= 1 << ((vertex_count - 1) % 32) */
1827 fs_reg prev_count
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
1828 abld
.ADD(prev_count
, vertex_count
, brw_imm_ud(0xffffffffu
));
1829 fs_reg mask
= intexp2(abld
, prev_count
);
1830 /* Note: we're relying on the fact that the GEN SHL instruction only pays
1831 * attention to the lower 5 bits of its second source argument, so on this
1832 * architecture, 1 << (vertex_count - 1) is equivalent to 1 <<
1833 * ((vertex_count - 1) % 32).
1835 abld
.OR(this->control_data_bits
, this->control_data_bits
, mask
);
1839 fs_visitor::emit_gs_control_data_bits(const fs_reg
&vertex_count
)
1841 assert(stage
== MESA_SHADER_GEOMETRY
);
1842 assert(gs_compile
->control_data_bits_per_vertex
!= 0);
1844 struct brw_gs_prog_data
*gs_prog_data
= brw_gs_prog_data(prog_data
);
1846 const fs_builder abld
= bld
.annotate("emit control data bits");
1847 const fs_builder fwa_bld
= bld
.exec_all();
1849 /* We use a single UD register to accumulate control data bits (32 bits
1850 * for each of the SIMD8 channels). So we need to write a DWord (32 bits)
1853 * Unfortunately, the URB_WRITE_SIMD8 message uses 128-bit (OWord) offsets.
1854 * We have select a 128-bit group via the Global and Per-Slot Offsets, then
1855 * use the Channel Mask phase to enable/disable which DWord within that
1856 * group to write. (Remember, different SIMD8 channels may have emitted
1857 * different numbers of vertices, so we may need per-slot offsets.)
1859 * Channel masking presents an annoying problem: we may have to replicate
1860 * the data up to 4 times:
1862 * Msg = Handles, Per-Slot Offsets, Channel Masks, Data, Data, Data, Data.
1864 * To avoid penalizing shaders that emit a small number of vertices, we
1865 * can avoid these sometimes: if the size of the control data header is
1866 * <= 128 bits, then there is only 1 OWord. All SIMD8 channels will land
1867 * land in the same 128-bit group, so we can skip per-slot offsets.
1869 * Similarly, if the control data header is <= 32 bits, there is only one
1870 * DWord, so we can skip channel masks.
1872 enum opcode opcode
= SHADER_OPCODE_URB_WRITE_SIMD8
;
1874 fs_reg channel_mask
, per_slot_offset
;
1876 if (gs_compile
->control_data_header_size_bits
> 32) {
1877 opcode
= SHADER_OPCODE_URB_WRITE_SIMD8_MASKED
;
1878 channel_mask
= vgrf(glsl_type::uint_type
);
1881 if (gs_compile
->control_data_header_size_bits
> 128) {
1882 opcode
= SHADER_OPCODE_URB_WRITE_SIMD8_MASKED_PER_SLOT
;
1883 per_slot_offset
= vgrf(glsl_type::uint_type
);
1886 /* Figure out which DWord we're trying to write to using the formula:
1888 * dword_index = (vertex_count - 1) * bits_per_vertex / 32
1890 * Since bits_per_vertex is a power of two, and is known at compile
1891 * time, this can be optimized to:
1893 * dword_index = (vertex_count - 1) >> (6 - log2(bits_per_vertex))
1895 if (opcode
!= SHADER_OPCODE_URB_WRITE_SIMD8
) {
1896 fs_reg dword_index
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
1897 fs_reg prev_count
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
1898 abld
.ADD(prev_count
, vertex_count
, brw_imm_ud(0xffffffffu
));
1899 unsigned log2_bits_per_vertex
=
1900 util_last_bit(gs_compile
->control_data_bits_per_vertex
);
1901 abld
.SHR(dword_index
, prev_count
, brw_imm_ud(6u - log2_bits_per_vertex
));
1903 if (per_slot_offset
.file
!= BAD_FILE
) {
1904 /* Set the per-slot offset to dword_index / 4, so that we'll write to
1905 * the appropriate OWord within the control data header.
1907 abld
.SHR(per_slot_offset
, dword_index
, brw_imm_ud(2u));
1910 /* Set the channel masks to 1 << (dword_index % 4), so that we'll
1911 * write to the appropriate DWORD within the OWORD.
1913 fs_reg channel
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
1914 fwa_bld
.AND(channel
, dword_index
, brw_imm_ud(3u));
1915 channel_mask
= intexp2(fwa_bld
, channel
);
1916 /* Then the channel masks need to be in bits 23:16. */
1917 fwa_bld
.SHL(channel_mask
, channel_mask
, brw_imm_ud(16u));
1920 /* Store the control data bits in the message payload and send it. */
1922 if (channel_mask
.file
!= BAD_FILE
)
1923 mlen
+= 4; /* channel masks, plus 3 extra copies of the data */
1924 if (per_slot_offset
.file
!= BAD_FILE
)
1927 fs_reg payload
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, mlen
);
1928 fs_reg
*sources
= ralloc_array(mem_ctx
, fs_reg
, mlen
);
1930 sources
[i
++] = fs_reg(retype(brw_vec8_grf(1, 0), BRW_REGISTER_TYPE_UD
));
1931 if (per_slot_offset
.file
!= BAD_FILE
)
1932 sources
[i
++] = per_slot_offset
;
1933 if (channel_mask
.file
!= BAD_FILE
)
1934 sources
[i
++] = channel_mask
;
1936 sources
[i
++] = this->control_data_bits
;
1939 abld
.LOAD_PAYLOAD(payload
, sources
, mlen
, mlen
);
1940 fs_inst
*inst
= abld
.emit(opcode
, reg_undef
, payload
);
1942 /* We need to increment Global Offset by 256-bits to make room for
1943 * Broadwell's extra "Vertex Count" payload at the beginning of the
1944 * URB entry. Since this is an OWord message, Global Offset is counted
1945 * in 128-bit units, so we must set it to 2.
1947 if (gs_prog_data
->static_vertex_count
== -1)
1952 fs_visitor::set_gs_stream_control_data_bits(const fs_reg
&vertex_count
,
1955 /* control_data_bits |= stream_id << ((2 * (vertex_count - 1)) % 32) */
1957 /* Note: we are calling this *before* increasing vertex_count, so
1958 * this->vertex_count == vertex_count - 1 in the formula above.
1961 /* Stream mode uses 2 bits per vertex */
1962 assert(gs_compile
->control_data_bits_per_vertex
== 2);
1964 /* Must be a valid stream */
1965 assert(stream_id
< MAX_VERTEX_STREAMS
);
1967 /* Control data bits are initialized to 0 so we don't have to set any
1968 * bits when sending vertices to stream 0.
1973 const fs_builder abld
= bld
.annotate("set stream control data bits", NULL
);
1975 /* reg::sid = stream_id */
1976 fs_reg sid
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
1977 abld
.MOV(sid
, brw_imm_ud(stream_id
));
1979 /* reg:shift_count = 2 * (vertex_count - 1) */
1980 fs_reg shift_count
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
1981 abld
.SHL(shift_count
, vertex_count
, brw_imm_ud(1u));
1983 /* Note: we're relying on the fact that the GEN SHL instruction only pays
1984 * attention to the lower 5 bits of its second source argument, so on this
1985 * architecture, stream_id << 2 * (vertex_count - 1) is equivalent to
1986 * stream_id << ((2 * (vertex_count - 1)) % 32).
1988 fs_reg mask
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
1989 abld
.SHL(mask
, sid
, shift_count
);
1990 abld
.OR(this->control_data_bits
, this->control_data_bits
, mask
);
1994 fs_visitor::emit_gs_vertex(const nir_src
&vertex_count_nir_src
,
1997 assert(stage
== MESA_SHADER_GEOMETRY
);
1999 struct brw_gs_prog_data
*gs_prog_data
= brw_gs_prog_data(prog_data
);
2001 fs_reg vertex_count
= get_nir_src(vertex_count_nir_src
);
2002 vertex_count
.type
= BRW_REGISTER_TYPE_UD
;
2004 /* Haswell and later hardware ignores the "Render Stream Select" bits
2005 * from the 3DSTATE_STREAMOUT packet when the SOL stage is disabled,
2006 * and instead sends all primitives down the pipeline for rasterization.
2007 * If the SOL stage is enabled, "Render Stream Select" is honored and
2008 * primitives bound to non-zero streams are discarded after stream output.
2010 * Since the only purpose of primives sent to non-zero streams is to
2011 * be recorded by transform feedback, we can simply discard all geometry
2012 * bound to these streams when transform feedback is disabled.
2014 if (stream_id
> 0 && !nir
->info
.has_transform_feedback_varyings
)
2017 /* If we're outputting 32 control data bits or less, then we can wait
2018 * until the shader is over to output them all. Otherwise we need to
2019 * output them as we go. Now is the time to do it, since we're about to
2020 * output the vertex_count'th vertex, so it's guaranteed that the
2021 * control data bits associated with the (vertex_count - 1)th vertex are
2024 if (gs_compile
->control_data_header_size_bits
> 32) {
2025 const fs_builder abld
=
2026 bld
.annotate("emit vertex: emit control data bits");
2028 /* Only emit control data bits if we've finished accumulating a batch
2029 * of 32 bits. This is the case when:
2031 * (vertex_count * bits_per_vertex) % 32 == 0
2033 * (in other words, when the last 5 bits of vertex_count *
2034 * bits_per_vertex are 0). Assuming bits_per_vertex == 2^n for some
2035 * integer n (which is always the case, since bits_per_vertex is
2036 * always 1 or 2), this is equivalent to requiring that the last 5-n
2037 * bits of vertex_count are 0:
2039 * vertex_count & (2^(5-n) - 1) == 0
2041 * 2^(5-n) == 2^5 / 2^n == 32 / bits_per_vertex, so this is
2044 * vertex_count & (32 / bits_per_vertex - 1) == 0
2046 * TODO: If vertex_count is an immediate, we could do some of this math
2047 * at compile time...
2050 abld
.AND(bld
.null_reg_d(), vertex_count
,
2051 brw_imm_ud(32u / gs_compile
->control_data_bits_per_vertex
- 1u));
2052 inst
->conditional_mod
= BRW_CONDITIONAL_Z
;
2054 abld
.IF(BRW_PREDICATE_NORMAL
);
2055 /* If vertex_count is 0, then no control data bits have been
2056 * accumulated yet, so we can skip emitting them.
2058 abld
.CMP(bld
.null_reg_d(), vertex_count
, brw_imm_ud(0u),
2059 BRW_CONDITIONAL_NEQ
);
2060 abld
.IF(BRW_PREDICATE_NORMAL
);
2061 emit_gs_control_data_bits(vertex_count
);
2062 abld
.emit(BRW_OPCODE_ENDIF
);
2064 /* Reset control_data_bits to 0 so we can start accumulating a new
2067 * Note: in the case where vertex_count == 0, this neutralizes the
2068 * effect of any call to EndPrimitive() that the shader may have
2069 * made before outputting its first vertex.
2071 inst
= abld
.MOV(this->control_data_bits
, brw_imm_ud(0u));
2072 inst
->force_writemask_all
= true;
2073 abld
.emit(BRW_OPCODE_ENDIF
);
2076 emit_urb_writes(vertex_count
);
2078 /* In stream mode we have to set control data bits for all vertices
2079 * unless we have disabled control data bits completely (which we do
2080 * do for GL_POINTS outputs that don't use streams).
2082 if (gs_compile
->control_data_header_size_bits
> 0 &&
2083 gs_prog_data
->control_data_format
==
2084 GEN7_GS_CONTROL_DATA_FORMAT_GSCTL_SID
) {
2085 set_gs_stream_control_data_bits(vertex_count
, stream_id
);
2090 fs_visitor::emit_gs_input_load(const fs_reg
&dst
,
2091 const nir_src
&vertex_src
,
2092 unsigned base_offset
,
2093 const nir_src
&offset_src
,
2094 unsigned num_components
,
2095 unsigned first_component
)
2097 struct brw_gs_prog_data
*gs_prog_data
= brw_gs_prog_data(prog_data
);
2099 nir_const_value
*vertex_const
= nir_src_as_const_value(vertex_src
);
2100 nir_const_value
*offset_const
= nir_src_as_const_value(offset_src
);
2101 const unsigned push_reg_count
= gs_prog_data
->base
.urb_read_length
* 8;
2103 /* TODO: figure out push input layout for invocations == 1 */
2104 /* TODO: make this work with 64-bit inputs */
2105 if (gs_prog_data
->invocations
== 1 &&
2106 type_sz(dst
.type
) <= 4 &&
2107 offset_const
!= NULL
&& vertex_const
!= NULL
&&
2108 4 * (base_offset
+ offset_const
->u32
[0]) < push_reg_count
) {
2109 int imm_offset
= (base_offset
+ offset_const
->u32
[0]) * 4 +
2110 vertex_const
->u32
[0] * push_reg_count
;
2111 for (unsigned i
= 0; i
< num_components
; i
++) {
2112 bld
.MOV(offset(dst
, bld
, i
),
2113 fs_reg(ATTR
, imm_offset
+ i
+ first_component
, dst
.type
));
2118 /* Resort to the pull model. Ensure the VUE handles are provided. */
2119 assert(gs_prog_data
->base
.include_vue_handles
);
2121 unsigned first_icp_handle
= gs_prog_data
->include_primitive_id
? 3 : 2;
2122 fs_reg icp_handle
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2124 if (gs_prog_data
->invocations
== 1) {
2126 /* The vertex index is constant; just select the proper URB handle. */
2128 retype(brw_vec8_grf(first_icp_handle
+ vertex_const
->i32
[0], 0),
2129 BRW_REGISTER_TYPE_UD
);
2131 /* The vertex index is non-constant. We need to use indirect
2132 * addressing to fetch the proper URB handle.
2134 * First, we start with the sequence <7, 6, 5, 4, 3, 2, 1, 0>
2135 * indicating that channel <n> should read the handle from
2136 * DWord <n>. We convert that to bytes by multiplying by 4.
2138 * Next, we convert the vertex index to bytes by multiplying
2139 * by 32 (shifting by 5), and add the two together. This is
2140 * the final indirect byte offset.
2142 fs_reg sequence
= bld
.vgrf(BRW_REGISTER_TYPE_UW
, 1);
2143 fs_reg channel_offsets
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2144 fs_reg vertex_offset_bytes
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2145 fs_reg icp_offset_bytes
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2147 /* sequence = <7, 6, 5, 4, 3, 2, 1, 0> */
2148 bld
.MOV(sequence
, fs_reg(brw_imm_v(0x76543210)));
2149 /* channel_offsets = 4 * sequence = <28, 24, 20, 16, 12, 8, 4, 0> */
2150 bld
.SHL(channel_offsets
, sequence
, brw_imm_ud(2u));
2151 /* Convert vertex_index to bytes (multiply by 32) */
2152 bld
.SHL(vertex_offset_bytes
,
2153 retype(get_nir_src(vertex_src
), BRW_REGISTER_TYPE_UD
),
2155 bld
.ADD(icp_offset_bytes
, vertex_offset_bytes
, channel_offsets
);
2157 /* Use first_icp_handle as the base offset. There is one register
2158 * of URB handles per vertex, so inform the register allocator that
2159 * we might read up to nir->info.gs.vertices_in registers.
2161 bld
.emit(SHADER_OPCODE_MOV_INDIRECT
, icp_handle
,
2162 retype(brw_vec8_grf(first_icp_handle
, 0), icp_handle
.type
),
2163 fs_reg(icp_offset_bytes
),
2164 brw_imm_ud(nir
->info
.gs
.vertices_in
* REG_SIZE
));
2167 assert(gs_prog_data
->invocations
> 1);
2170 assert(devinfo
->gen
>= 9 || vertex_const
->i32
[0] <= 5);
2172 retype(brw_vec1_grf(first_icp_handle
+
2173 vertex_const
->i32
[0] / 8,
2174 vertex_const
->i32
[0] % 8),
2175 BRW_REGISTER_TYPE_UD
));
2177 /* The vertex index is non-constant. We need to use indirect
2178 * addressing to fetch the proper URB handle.
2181 fs_reg icp_offset_bytes
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2183 /* Convert vertex_index to bytes (multiply by 4) */
2184 bld
.SHL(icp_offset_bytes
,
2185 retype(get_nir_src(vertex_src
), BRW_REGISTER_TYPE_UD
),
2188 /* Use first_icp_handle as the base offset. There is one DWord
2189 * of URB handles per vertex, so inform the register allocator that
2190 * we might read up to ceil(nir->info.gs.vertices_in / 8) registers.
2192 bld
.emit(SHADER_OPCODE_MOV_INDIRECT
, icp_handle
,
2193 retype(brw_vec8_grf(first_icp_handle
, 0), icp_handle
.type
),
2194 fs_reg(icp_offset_bytes
),
2195 brw_imm_ud(DIV_ROUND_UP(nir
->info
.gs
.vertices_in
, 8) *
2202 fs_reg tmp_dst
= dst
;
2203 fs_reg indirect_offset
= get_nir_src(offset_src
);
2204 unsigned num_iterations
= 1;
2205 unsigned orig_num_components
= num_components
;
2207 if (type_sz(dst
.type
) == 8) {
2208 if (num_components
> 2) {
2212 fs_reg tmp
= fs_reg(VGRF
, alloc
.allocate(4), dst
.type
);
2214 first_component
= first_component
/ 2;
2217 for (unsigned iter
= 0; iter
< num_iterations
; iter
++) {
2219 /* Constant indexing - use global offset. */
2220 if (first_component
!= 0) {
2221 unsigned read_components
= num_components
+ first_component
;
2222 fs_reg tmp
= bld
.vgrf(dst
.type
, read_components
);
2223 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8
, tmp
, icp_handle
);
2224 inst
->size_written
= read_components
*
2225 tmp
.component_size(inst
->exec_size
);
2226 for (unsigned i
= 0; i
< num_components
; i
++) {
2227 bld
.MOV(offset(tmp_dst
, bld
, i
),
2228 offset(tmp
, bld
, i
+ first_component
));
2231 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8
, tmp_dst
,
2233 inst
->size_written
= num_components
*
2234 tmp_dst
.component_size(inst
->exec_size
);
2236 inst
->offset
= base_offset
+ offset_const
->u32
[0];
2239 /* Indirect indexing - use per-slot offsets as well. */
2240 const fs_reg srcs
[] = { icp_handle
, indirect_offset
};
2241 unsigned read_components
= num_components
+ first_component
;
2242 fs_reg tmp
= bld
.vgrf(dst
.type
, read_components
);
2243 fs_reg payload
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 2);
2244 bld
.LOAD_PAYLOAD(payload
, srcs
, ARRAY_SIZE(srcs
), 0);
2245 if (first_component
!= 0) {
2246 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT
, tmp
,
2248 inst
->size_written
= read_components
*
2249 tmp
.component_size(inst
->exec_size
);
2250 for (unsigned i
= 0; i
< num_components
; i
++) {
2251 bld
.MOV(offset(tmp_dst
, bld
, i
),
2252 offset(tmp
, bld
, i
+ first_component
));
2255 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT
, tmp_dst
,
2257 inst
->size_written
= num_components
*
2258 tmp_dst
.component_size(inst
->exec_size
);
2260 inst
->offset
= base_offset
;
2264 if (type_sz(dst
.type
) == 8) {
2265 shuffle_32bit_load_result_to_64bit_data(
2266 bld
, tmp_dst
, retype(tmp_dst
, BRW_REGISTER_TYPE_F
), num_components
);
2268 for (unsigned c
= 0; c
< num_components
; c
++)
2269 bld
.MOV(offset(dst
, bld
, iter
* 2 + c
), offset(tmp_dst
, bld
, c
));
2272 if (num_iterations
> 1) {
2273 num_components
= orig_num_components
- 2;
2277 fs_reg new_indirect
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2278 bld
.ADD(new_indirect
, indirect_offset
, brw_imm_ud(1u));
2279 indirect_offset
= new_indirect
;
2286 fs_visitor::get_indirect_offset(nir_intrinsic_instr
*instr
)
2288 nir_src
*offset_src
= nir_get_io_offset_src(instr
);
2289 nir_const_value
*const_value
= nir_src_as_const_value(*offset_src
);
2292 /* The only constant offset we should find is 0. brw_nir.c's
2293 * add_const_offset_to_base() will fold other constant offsets
2294 * into instr->const_index[0].
2296 assert(const_value
->u32
[0] == 0);
2300 return get_nir_src(*offset_src
);
2304 do_untyped_vector_read(const fs_builder
&bld
,
2306 const fs_reg surf_index
,
2307 const fs_reg offset_reg
,
2308 unsigned num_components
)
2310 if (type_sz(dest
.type
) <= 2) {
2311 assert(dest
.stride
== 1);
2312 boolean is_const_offset
= offset_reg
.file
== BRW_IMMEDIATE_VALUE
;
2314 if (is_const_offset
) {
2315 uint32_t start
= offset_reg
.ud
& ~3;
2316 uint32_t end
= offset_reg
.ud
+ num_components
* type_sz(dest
.type
);
2317 end
= ALIGN(end
, 4);
2318 assert (end
- start
<= 16);
2320 /* At this point we have 16-bit component/s that have constant
2321 * offset aligned to 4-bytes that can be read with untyped_reads.
2322 * untyped_read message requires 32-bit aligned offsets.
2324 unsigned first_component
= (offset_reg
.ud
& 3) / type_sz(dest
.type
);
2325 unsigned num_components_32bit
= (end
- start
) / 4;
2327 fs_reg read_result
=
2328 emit_untyped_read(bld
, surf_index
, brw_imm_ud(start
),
2330 num_components_32bit
,
2331 BRW_PREDICATE_NONE
);
2332 shuffle_32bit_load_result_to_16bit_data(bld
,
2333 retype(dest
, BRW_REGISTER_TYPE_W
),
2334 retype(read_result
, BRW_REGISTER_TYPE_D
),
2335 first_component
, num_components
);
2337 fs_reg read_offset
= bld
.vgrf(BRW_REGISTER_TYPE_UD
);
2338 for (unsigned i
= 0; i
< num_components
; i
++) {
2340 bld
.MOV(read_offset
, offset_reg
);
2342 bld
.ADD(read_offset
, offset_reg
,
2343 brw_imm_ud(i
* type_sz(dest
.type
)));
2345 /* Non constant offsets are not guaranteed to be aligned 32-bits
2346 * so they are read using one byte_scattered_read message
2347 * for each component.
2349 fs_reg read_result
=
2350 emit_byte_scattered_read(bld
, surf_index
, read_offset
,
2352 type_sz(dest
.type
) * 8 /* bit_size */,
2353 BRW_PREDICATE_NONE
);
2354 bld
.MOV(offset(dest
, bld
, i
),
2355 subscript (read_result
, dest
.type
, 0));
2358 } else if (type_sz(dest
.type
) == 4) {
2359 fs_reg read_result
= emit_untyped_read(bld
, surf_index
, offset_reg
,
2362 BRW_PREDICATE_NONE
);
2363 read_result
.type
= dest
.type
;
2364 for (unsigned i
= 0; i
< num_components
; i
++)
2365 bld
.MOV(offset(dest
, bld
, i
), offset(read_result
, bld
, i
));
2366 } else if (type_sz(dest
.type
) == 8) {
2367 /* Reading a dvec, so we need to:
2369 * 1. Multiply num_components by 2, to account for the fact that we
2370 * need to read 64-bit components.
2371 * 2. Shuffle the result of the load to form valid 64-bit elements
2372 * 3. Emit a second load (for components z/w) if needed.
2374 fs_reg read_offset
= bld
.vgrf(BRW_REGISTER_TYPE_UD
);
2375 bld
.MOV(read_offset
, offset_reg
);
2377 int iters
= num_components
<= 2 ? 1 : 2;
2379 /* Load the dvec, the first iteration loads components x/y, the second
2380 * iteration, if needed, loads components z/w
2382 for (int it
= 0; it
< iters
; it
++) {
2383 /* Compute number of components to read in this iteration */
2384 int iter_components
= MIN2(2, num_components
);
2385 num_components
-= iter_components
;
2387 /* Read. Since this message reads 32-bit components, we need to
2388 * read twice as many components.
2390 fs_reg read_result
= emit_untyped_read(bld
, surf_index
, read_offset
,
2392 iter_components
* 2,
2393 BRW_PREDICATE_NONE
);
2395 /* Shuffle the 32-bit load result into valid 64-bit data */
2396 const fs_reg packed_result
= bld
.vgrf(dest
.type
, iter_components
);
2397 shuffle_32bit_load_result_to_64bit_data(
2398 bld
, packed_result
, read_result
, iter_components
);
2400 /* Move each component to its destination */
2401 read_result
= retype(read_result
, BRW_REGISTER_TYPE_DF
);
2402 for (int c
= 0; c
< iter_components
; c
++) {
2403 bld
.MOV(offset(dest
, bld
, it
* 2 + c
),
2404 offset(packed_result
, bld
, c
));
2407 bld
.ADD(read_offset
, read_offset
, brw_imm_ud(16));
2410 unreachable("Unsupported type");
2415 fs_visitor::nir_emit_vs_intrinsic(const fs_builder
&bld
,
2416 nir_intrinsic_instr
*instr
)
2418 assert(stage
== MESA_SHADER_VERTEX
);
2421 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
2422 dest
= get_nir_dest(instr
->dest
);
2424 switch (instr
->intrinsic
) {
2425 case nir_intrinsic_load_vertex_id
:
2426 case nir_intrinsic_load_base_vertex
:
2427 unreachable("should be lowered by nir_lower_system_values()");
2429 case nir_intrinsic_load_vertex_id_zero_base
:
2430 case nir_intrinsic_load_instance_id
:
2431 case nir_intrinsic_load_base_instance
:
2432 case nir_intrinsic_load_draw_id
: {
2433 gl_system_value sv
= nir_system_value_from_intrinsic(instr
->intrinsic
);
2434 fs_reg val
= nir_system_values
[sv
];
2435 assert(val
.file
!= BAD_FILE
);
2436 dest
.type
= val
.type
;
2441 case nir_intrinsic_load_input
: {
2442 fs_reg src
= fs_reg(ATTR
, nir_intrinsic_base(instr
) * 4, dest
.type
);
2443 unsigned first_component
= nir_intrinsic_component(instr
);
2444 unsigned num_components
= instr
->num_components
;
2446 nir_const_value
*const_offset
= nir_src_as_const_value(instr
->src
[0]);
2447 assert(const_offset
&& "Indirect input loads not allowed");
2448 src
= offset(src
, bld
, const_offset
->u32
[0]);
2450 if (type_sz(dest
.type
) == 8)
2451 first_component
/= 2;
2453 for (unsigned j
= 0; j
< num_components
; j
++) {
2454 bld
.MOV(offset(dest
, bld
, j
), offset(src
, bld
, j
+ first_component
));
2457 if (type_sz(dest
.type
) == 8) {
2458 shuffle_32bit_load_result_to_64bit_data(bld
,
2460 retype(dest
, BRW_REGISTER_TYPE_F
),
2461 instr
->num_components
);
2466 case nir_intrinsic_load_first_vertex
:
2467 case nir_intrinsic_load_is_indexed_draw
:
2468 unreachable("lowered by brw_nir_lower_vs_inputs");
2471 nir_emit_intrinsic(bld
, instr
);
2477 fs_visitor::nir_emit_tcs_intrinsic(const fs_builder
&bld
,
2478 nir_intrinsic_instr
*instr
)
2480 assert(stage
== MESA_SHADER_TESS_CTRL
);
2481 struct brw_tcs_prog_key
*tcs_key
= (struct brw_tcs_prog_key
*) key
;
2482 struct brw_tcs_prog_data
*tcs_prog_data
= brw_tcs_prog_data(prog_data
);
2485 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
2486 dst
= get_nir_dest(instr
->dest
);
2488 switch (instr
->intrinsic
) {
2489 case nir_intrinsic_load_primitive_id
:
2490 bld
.MOV(dst
, fs_reg(brw_vec1_grf(0, 1)));
2492 case nir_intrinsic_load_invocation_id
:
2493 bld
.MOV(retype(dst
, invocation_id
.type
), invocation_id
);
2495 case nir_intrinsic_load_patch_vertices_in
:
2496 bld
.MOV(retype(dst
, BRW_REGISTER_TYPE_D
),
2497 brw_imm_d(tcs_key
->input_vertices
));
2500 case nir_intrinsic_barrier
: {
2501 if (tcs_prog_data
->instances
== 1)
2504 fs_reg m0
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2505 fs_reg m0_2
= component(m0
, 2);
2507 const fs_builder chanbld
= bld
.exec_all().group(1, 0);
2509 /* Zero the message header */
2510 bld
.exec_all().MOV(m0
, brw_imm_ud(0u));
2512 /* Copy "Barrier ID" from r0.2, bits 16:13 */
2513 chanbld
.AND(m0_2
, retype(brw_vec1_grf(0, 2), BRW_REGISTER_TYPE_UD
),
2514 brw_imm_ud(INTEL_MASK(16, 13)));
2516 /* Shift it up to bits 27:24. */
2517 chanbld
.SHL(m0_2
, m0_2
, brw_imm_ud(11));
2519 /* Set the Barrier Count and the enable bit */
2520 chanbld
.OR(m0_2
, m0_2
,
2521 brw_imm_ud(tcs_prog_data
->instances
<< 9 | (1 << 15)));
2523 bld
.emit(SHADER_OPCODE_BARRIER
, bld
.null_reg_ud(), m0
);
2527 case nir_intrinsic_load_input
:
2528 unreachable("nir_lower_io should never give us these.");
2531 case nir_intrinsic_load_per_vertex_input
: {
2532 fs_reg indirect_offset
= get_indirect_offset(instr
);
2533 unsigned imm_offset
= instr
->const_index
[0];
2535 const nir_src
&vertex_src
= instr
->src
[0];
2536 nir_const_value
*vertex_const
= nir_src_as_const_value(vertex_src
);
2543 /* Emit a MOV to resolve <0,1,0> regioning. */
2544 icp_handle
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2546 retype(brw_vec1_grf(1 + (vertex_const
->i32
[0] >> 3),
2547 vertex_const
->i32
[0] & 7),
2548 BRW_REGISTER_TYPE_UD
));
2549 } else if (tcs_prog_data
->instances
== 1 &&
2550 vertex_src
.is_ssa
&&
2551 vertex_src
.ssa
->parent_instr
->type
== nir_instr_type_intrinsic
&&
2552 nir_instr_as_intrinsic(vertex_src
.ssa
->parent_instr
)->intrinsic
== nir_intrinsic_load_invocation_id
) {
2553 /* For the common case of only 1 instance, an array index of
2554 * gl_InvocationID means reading g1. Skip all the indirect work.
2556 icp_handle
= retype(brw_vec8_grf(1, 0), BRW_REGISTER_TYPE_UD
);
2558 /* The vertex index is non-constant. We need to use indirect
2559 * addressing to fetch the proper URB handle.
2561 icp_handle
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2563 /* Each ICP handle is a single DWord (4 bytes) */
2564 fs_reg vertex_offset_bytes
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2565 bld
.SHL(vertex_offset_bytes
,
2566 retype(get_nir_src(vertex_src
), BRW_REGISTER_TYPE_UD
),
2569 /* Start at g1. We might read up to 4 registers. */
2570 bld
.emit(SHADER_OPCODE_MOV_INDIRECT
, icp_handle
,
2571 retype(brw_vec8_grf(1, 0), icp_handle
.type
), vertex_offset_bytes
,
2572 brw_imm_ud(4 * REG_SIZE
));
2575 /* We can only read two double components with each URB read, so
2576 * we send two read messages in that case, each one loading up to
2577 * two double components.
2579 unsigned num_iterations
= 1;
2580 unsigned num_components
= instr
->num_components
;
2581 unsigned first_component
= nir_intrinsic_component(instr
);
2582 fs_reg orig_dst
= dst
;
2583 if (type_sz(dst
.type
) == 8) {
2584 first_component
= first_component
/ 2;
2585 if (instr
->num_components
> 2) {
2590 fs_reg tmp
= fs_reg(VGRF
, alloc
.allocate(4), dst
.type
);
2594 for (unsigned iter
= 0; iter
< num_iterations
; iter
++) {
2595 if (indirect_offset
.file
== BAD_FILE
) {
2596 /* Constant indexing - use global offset. */
2597 if (first_component
!= 0) {
2598 unsigned read_components
= num_components
+ first_component
;
2599 fs_reg tmp
= bld
.vgrf(dst
.type
, read_components
);
2600 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8
, tmp
, icp_handle
);
2601 for (unsigned i
= 0; i
< num_components
; i
++) {
2602 bld
.MOV(offset(dst
, bld
, i
),
2603 offset(tmp
, bld
, i
+ first_component
));
2606 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8
, dst
, icp_handle
);
2608 inst
->offset
= imm_offset
;
2611 /* Indirect indexing - use per-slot offsets as well. */
2612 const fs_reg srcs
[] = { icp_handle
, indirect_offset
};
2613 fs_reg payload
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 2);
2614 bld
.LOAD_PAYLOAD(payload
, srcs
, ARRAY_SIZE(srcs
), 0);
2615 if (first_component
!= 0) {
2616 unsigned read_components
= num_components
+ first_component
;
2617 fs_reg tmp
= bld
.vgrf(dst
.type
, read_components
);
2618 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT
, tmp
,
2620 for (unsigned i
= 0; i
< num_components
; i
++) {
2621 bld
.MOV(offset(dst
, bld
, i
),
2622 offset(tmp
, bld
, i
+ first_component
));
2625 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT
, dst
,
2628 inst
->offset
= imm_offset
;
2631 inst
->size_written
= (num_components
+ first_component
) *
2632 inst
->dst
.component_size(inst
->exec_size
);
2634 /* If we are reading 64-bit data using 32-bit read messages we need
2635 * build proper 64-bit data elements by shuffling the low and high
2636 * 32-bit components around like we do for other things like UBOs
2639 if (type_sz(dst
.type
) == 8) {
2640 shuffle_32bit_load_result_to_64bit_data(
2641 bld
, dst
, retype(dst
, BRW_REGISTER_TYPE_F
), num_components
);
2643 for (unsigned c
= 0; c
< num_components
; c
++) {
2644 bld
.MOV(offset(orig_dst
, bld
, iter
* 2 + c
),
2645 offset(dst
, bld
, c
));
2649 /* Copy the temporary to the destination to deal with writemasking.
2651 * Also attempt to deal with gl_PointSize being in the .w component.
2653 if (inst
->offset
== 0 && indirect_offset
.file
== BAD_FILE
) {
2654 assert(type_sz(dst
.type
) < 8);
2655 inst
->dst
= bld
.vgrf(dst
.type
, 4);
2656 inst
->size_written
= 4 * REG_SIZE
;
2657 bld
.MOV(dst
, offset(inst
->dst
, bld
, 3));
2660 /* If we are loading double data and we need a second read message
2661 * adjust the write offset
2663 if (num_iterations
> 1) {
2664 num_components
= instr
->num_components
- 2;
2671 case nir_intrinsic_load_output
:
2672 case nir_intrinsic_load_per_vertex_output
: {
2673 fs_reg indirect_offset
= get_indirect_offset(instr
);
2674 unsigned imm_offset
= instr
->const_index
[0];
2675 unsigned first_component
= nir_intrinsic_component(instr
);
2678 if (indirect_offset
.file
== BAD_FILE
) {
2679 /* Replicate the patch handle to all enabled channels */
2680 fs_reg patch_handle
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2681 bld
.MOV(patch_handle
,
2682 retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_UD
));
2685 if (first_component
!= 0) {
2686 unsigned read_components
=
2687 instr
->num_components
+ first_component
;
2688 fs_reg tmp
= bld
.vgrf(dst
.type
, read_components
);
2689 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8
, tmp
,
2691 inst
->size_written
= read_components
* REG_SIZE
;
2692 for (unsigned i
= 0; i
< instr
->num_components
; i
++) {
2693 bld
.MOV(offset(dst
, bld
, i
),
2694 offset(tmp
, bld
, i
+ first_component
));
2697 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8
, dst
,
2699 inst
->size_written
= instr
->num_components
* REG_SIZE
;
2701 inst
->offset
= imm_offset
;
2705 /* Indirect indexing - use per-slot offsets as well. */
2706 const fs_reg srcs
[] = {
2707 retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_UD
),
2710 fs_reg payload
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 2);
2711 bld
.LOAD_PAYLOAD(payload
, srcs
, ARRAY_SIZE(srcs
), 0);
2712 if (first_component
!= 0) {
2713 unsigned read_components
=
2714 instr
->num_components
+ first_component
;
2715 fs_reg tmp
= bld
.vgrf(dst
.type
, read_components
);
2716 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT
, tmp
,
2718 inst
->size_written
= read_components
* REG_SIZE
;
2719 for (unsigned i
= 0; i
< instr
->num_components
; i
++) {
2720 bld
.MOV(offset(dst
, bld
, i
),
2721 offset(tmp
, bld
, i
+ first_component
));
2724 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT
, dst
,
2726 inst
->size_written
= instr
->num_components
* REG_SIZE
;
2728 inst
->offset
= imm_offset
;
2734 case nir_intrinsic_store_output
:
2735 case nir_intrinsic_store_per_vertex_output
: {
2736 fs_reg value
= get_nir_src(instr
->src
[0]);
2737 bool is_64bit
= (instr
->src
[0].is_ssa
?
2738 instr
->src
[0].ssa
->bit_size
: instr
->src
[0].reg
.reg
->bit_size
) == 64;
2739 fs_reg indirect_offset
= get_indirect_offset(instr
);
2740 unsigned imm_offset
= instr
->const_index
[0];
2741 unsigned mask
= instr
->const_index
[1];
2742 unsigned header_regs
= 0;
2744 srcs
[header_regs
++] = retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_UD
);
2746 if (indirect_offset
.file
!= BAD_FILE
) {
2747 srcs
[header_regs
++] = indirect_offset
;
2753 unsigned num_components
= util_last_bit(mask
);
2756 /* We can only pack two 64-bit components in a single message, so send
2757 * 2 messages if we have more components
2759 unsigned num_iterations
= 1;
2760 unsigned iter_components
= num_components
;
2761 unsigned first_component
= nir_intrinsic_component(instr
);
2763 first_component
= first_component
/ 2;
2764 if (instr
->num_components
> 2) {
2766 iter_components
= 2;
2770 mask
= mask
<< first_component
;
2772 for (unsigned iter
= 0; iter
< num_iterations
; iter
++) {
2773 if (!is_64bit
&& mask
!= WRITEMASK_XYZW
) {
2774 srcs
[header_regs
++] = brw_imm_ud(mask
<< 16);
2775 opcode
= indirect_offset
.file
!= BAD_FILE
?
2776 SHADER_OPCODE_URB_WRITE_SIMD8_MASKED_PER_SLOT
:
2777 SHADER_OPCODE_URB_WRITE_SIMD8_MASKED
;
2778 } else if (is_64bit
&& ((mask
& WRITEMASK_XY
) != WRITEMASK_XY
)) {
2779 /* Expand the 64-bit mask to 32-bit channels. We only handle
2780 * two channels in each iteration, so we only care about X/Y.
2782 unsigned mask32
= 0;
2783 if (mask
& WRITEMASK_X
)
2784 mask32
|= WRITEMASK_XY
;
2785 if (mask
& WRITEMASK_Y
)
2786 mask32
|= WRITEMASK_ZW
;
2788 /* If the mask does not include any of the channels X or Y there
2789 * is nothing to do in this iteration. Move on to the next couple
2790 * of 64-bit channels.
2798 srcs
[header_regs
++] = brw_imm_ud(mask32
<< 16);
2799 opcode
= indirect_offset
.file
!= BAD_FILE
?
2800 SHADER_OPCODE_URB_WRITE_SIMD8_MASKED_PER_SLOT
:
2801 SHADER_OPCODE_URB_WRITE_SIMD8_MASKED
;
2803 opcode
= indirect_offset
.file
!= BAD_FILE
?
2804 SHADER_OPCODE_URB_WRITE_SIMD8_PER_SLOT
:
2805 SHADER_OPCODE_URB_WRITE_SIMD8
;
2808 for (unsigned i
= 0; i
< iter_components
; i
++) {
2809 if (!(mask
& (1 << (i
+ first_component
))))
2813 srcs
[header_regs
+ i
+ first_component
] = offset(value
, bld
, i
);
2815 /* We need to shuffle the 64-bit data to match the layout
2816 * expected by our 32-bit URB write messages. We use a temporary
2819 unsigned channel
= iter
* 2 + i
;
2820 fs_reg dest
= shuffle_64bit_data_for_32bit_write(bld
,
2821 offset(value
, bld
, channel
), 1);
2823 srcs
[header_regs
+ (i
+ first_component
) * 2] = dest
;
2824 srcs
[header_regs
+ (i
+ first_component
) * 2 + 1] =
2825 offset(dest
, bld
, 1);
2830 header_regs
+ (is_64bit
? 2 * iter_components
: iter_components
) +
2831 (is_64bit
? 2 * first_component
: first_component
);
2833 bld
.vgrf(BRW_REGISTER_TYPE_UD
, mlen
);
2834 bld
.LOAD_PAYLOAD(payload
, srcs
, mlen
, header_regs
);
2836 fs_inst
*inst
= bld
.emit(opcode
, bld
.null_reg_ud(), payload
);
2837 inst
->offset
= imm_offset
;
2840 /* If this is a 64-bit attribute, select the next two 64-bit channels
2841 * to be handled in the next iteration.
2852 nir_emit_intrinsic(bld
, instr
);
2858 fs_visitor::nir_emit_tes_intrinsic(const fs_builder
&bld
,
2859 nir_intrinsic_instr
*instr
)
2861 assert(stage
== MESA_SHADER_TESS_EVAL
);
2862 struct brw_tes_prog_data
*tes_prog_data
= brw_tes_prog_data(prog_data
);
2865 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
2866 dest
= get_nir_dest(instr
->dest
);
2868 switch (instr
->intrinsic
) {
2869 case nir_intrinsic_load_primitive_id
:
2870 bld
.MOV(dest
, fs_reg(brw_vec1_grf(0, 1)));
2872 case nir_intrinsic_load_tess_coord
:
2873 /* gl_TessCoord is part of the payload in g1-3 */
2874 for (unsigned i
= 0; i
< 3; i
++) {
2875 bld
.MOV(offset(dest
, bld
, i
), fs_reg(brw_vec8_grf(1 + i
, 0)));
2879 case nir_intrinsic_load_input
:
2880 case nir_intrinsic_load_per_vertex_input
: {
2881 fs_reg indirect_offset
= get_indirect_offset(instr
);
2882 unsigned imm_offset
= instr
->const_index
[0];
2883 unsigned first_component
= nir_intrinsic_component(instr
);
2885 if (type_sz(dest
.type
) == 8) {
2886 first_component
= first_component
/ 2;
2890 if (indirect_offset
.file
== BAD_FILE
) {
2891 /* Arbitrarily only push up to 32 vec4 slots worth of data,
2892 * which is 16 registers (since each holds 2 vec4 slots).
2894 unsigned slot_count
= 1;
2895 if (type_sz(dest
.type
) == 8 && instr
->num_components
> 2)
2898 const unsigned max_push_slots
= 32;
2899 if (imm_offset
+ slot_count
<= max_push_slots
) {
2900 fs_reg src
= fs_reg(ATTR
, imm_offset
/ 2, dest
.type
);
2901 for (int i
= 0; i
< instr
->num_components
; i
++) {
2902 unsigned comp
= 16 / type_sz(dest
.type
) * (imm_offset
% 2) +
2903 i
+ first_component
;
2904 bld
.MOV(offset(dest
, bld
, i
), component(src
, comp
));
2907 tes_prog_data
->base
.urb_read_length
=
2908 MAX2(tes_prog_data
->base
.urb_read_length
,
2909 DIV_ROUND_UP(imm_offset
+ slot_count
, 2));
2911 /* Replicate the patch handle to all enabled channels */
2912 const fs_reg srcs
[] = {
2913 retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_UD
)
2915 fs_reg patch_handle
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2916 bld
.LOAD_PAYLOAD(patch_handle
, srcs
, ARRAY_SIZE(srcs
), 0);
2918 if (first_component
!= 0) {
2919 unsigned read_components
=
2920 instr
->num_components
+ first_component
;
2921 fs_reg tmp
= bld
.vgrf(dest
.type
, read_components
);
2922 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8
, tmp
,
2924 inst
->size_written
= read_components
* REG_SIZE
;
2925 for (unsigned i
= 0; i
< instr
->num_components
; i
++) {
2926 bld
.MOV(offset(dest
, bld
, i
),
2927 offset(tmp
, bld
, i
+ first_component
));
2930 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8
, dest
,
2932 inst
->size_written
= instr
->num_components
* REG_SIZE
;
2935 inst
->offset
= imm_offset
;
2938 /* Indirect indexing - use per-slot offsets as well. */
2940 /* We can only read two double components with each URB read, so
2941 * we send two read messages in that case, each one loading up to
2942 * two double components.
2944 unsigned num_iterations
= 1;
2945 unsigned num_components
= instr
->num_components
;
2946 fs_reg orig_dest
= dest
;
2947 if (type_sz(dest
.type
) == 8) {
2948 if (instr
->num_components
> 2) {
2952 fs_reg tmp
= fs_reg(VGRF
, alloc
.allocate(4), dest
.type
);
2956 for (unsigned iter
= 0; iter
< num_iterations
; iter
++) {
2957 const fs_reg srcs
[] = {
2958 retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_UD
),
2961 fs_reg payload
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 2);
2962 bld
.LOAD_PAYLOAD(payload
, srcs
, ARRAY_SIZE(srcs
), 0);
2964 if (first_component
!= 0) {
2965 unsigned read_components
=
2966 num_components
+ first_component
;
2967 fs_reg tmp
= bld
.vgrf(dest
.type
, read_components
);
2968 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT
, tmp
,
2970 for (unsigned i
= 0; i
< num_components
; i
++) {
2971 bld
.MOV(offset(dest
, bld
, i
),
2972 offset(tmp
, bld
, i
+ first_component
));
2975 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT
, dest
,
2979 inst
->offset
= imm_offset
;
2980 inst
->size_written
= (num_components
+ first_component
) *
2981 inst
->dst
.component_size(inst
->exec_size
);
2983 /* If we are reading 64-bit data using 32-bit read messages we need
2984 * build proper 64-bit data elements by shuffling the low and high
2985 * 32-bit components around like we do for other things like UBOs
2988 if (type_sz(dest
.type
) == 8) {
2989 shuffle_32bit_load_result_to_64bit_data(
2990 bld
, dest
, retype(dest
, BRW_REGISTER_TYPE_F
), num_components
);
2992 for (unsigned c
= 0; c
< num_components
; c
++) {
2993 bld
.MOV(offset(orig_dest
, bld
, iter
* 2 + c
),
2994 offset(dest
, bld
, c
));
2998 /* If we are loading double data and we need a second read message
3001 if (num_iterations
> 1) {
3002 num_components
= instr
->num_components
- 2;
3010 nir_emit_intrinsic(bld
, instr
);
3016 fs_visitor::nir_emit_gs_intrinsic(const fs_builder
&bld
,
3017 nir_intrinsic_instr
*instr
)
3019 assert(stage
== MESA_SHADER_GEOMETRY
);
3020 fs_reg indirect_offset
;
3023 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
3024 dest
= get_nir_dest(instr
->dest
);
3026 switch (instr
->intrinsic
) {
3027 case nir_intrinsic_load_primitive_id
:
3028 assert(stage
== MESA_SHADER_GEOMETRY
);
3029 assert(brw_gs_prog_data(prog_data
)->include_primitive_id
);
3030 bld
.MOV(retype(dest
, BRW_REGISTER_TYPE_UD
),
3031 retype(fs_reg(brw_vec8_grf(2, 0)), BRW_REGISTER_TYPE_UD
));
3034 case nir_intrinsic_load_input
:
3035 unreachable("load_input intrinsics are invalid for the GS stage");
3037 case nir_intrinsic_load_per_vertex_input
:
3038 emit_gs_input_load(dest
, instr
->src
[0], instr
->const_index
[0],
3039 instr
->src
[1], instr
->num_components
,
3040 nir_intrinsic_component(instr
));
3043 case nir_intrinsic_emit_vertex_with_counter
:
3044 emit_gs_vertex(instr
->src
[0], instr
->const_index
[0]);
3047 case nir_intrinsic_end_primitive_with_counter
:
3048 emit_gs_end_primitive(instr
->src
[0]);
3051 case nir_intrinsic_set_vertex_count
:
3052 bld
.MOV(this->final_gs_vertex_count
, get_nir_src(instr
->src
[0]));
3055 case nir_intrinsic_load_invocation_id
: {
3056 fs_reg val
= nir_system_values
[SYSTEM_VALUE_INVOCATION_ID
];
3057 assert(val
.file
!= BAD_FILE
);
3058 dest
.type
= val
.type
;
3064 nir_emit_intrinsic(bld
, instr
);
3070 * Fetch the current render target layer index.
3073 fetch_render_target_array_index(const fs_builder
&bld
)
3075 if (bld
.shader
->devinfo
->gen
>= 6) {
3076 /* The render target array index is provided in the thread payload as
3077 * bits 26:16 of r0.0.
3079 const fs_reg idx
= bld
.vgrf(BRW_REGISTER_TYPE_UD
);
3080 bld
.AND(idx
, brw_uw1_reg(BRW_GENERAL_REGISTER_FILE
, 0, 1),
3084 /* Pre-SNB we only ever render into the first layer of the framebuffer
3085 * since layered rendering is not implemented.
3087 return brw_imm_ud(0);
3092 * Fake non-coherent framebuffer read implemented using TXF to fetch from the
3093 * framebuffer at the current fragment coordinates and sample index.
3096 fs_visitor::emit_non_coherent_fb_read(const fs_builder
&bld
, const fs_reg
&dst
,
3099 const struct gen_device_info
*devinfo
= bld
.shader
->devinfo
;
3101 assert(bld
.shader
->stage
== MESA_SHADER_FRAGMENT
);
3102 const brw_wm_prog_key
*wm_key
=
3103 reinterpret_cast<const brw_wm_prog_key
*>(key
);
3104 assert(!wm_key
->coherent_fb_fetch
);
3105 const struct brw_wm_prog_data
*wm_prog_data
=
3106 brw_wm_prog_data(stage_prog_data
);
3108 /* Calculate the surface index relative to the start of the texture binding
3109 * table block, since that's what the texturing messages expect.
3111 const unsigned surface
= target
+
3112 wm_prog_data
->binding_table
.render_target_read_start
-
3113 wm_prog_data
->base
.binding_table
.texture_start
;
3115 brw_mark_surface_used(
3116 bld
.shader
->stage_prog_data
,
3117 wm_prog_data
->binding_table
.render_target_read_start
+ target
);
3119 /* Calculate the fragment coordinates. */
3120 const fs_reg coords
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 3);
3121 bld
.MOV(offset(coords
, bld
, 0), pixel_x
);
3122 bld
.MOV(offset(coords
, bld
, 1), pixel_y
);
3123 bld
.MOV(offset(coords
, bld
, 2), fetch_render_target_array_index(bld
));
3125 /* Calculate the sample index and MCS payload when multisampling. Luckily
3126 * the MCS fetch message behaves deterministically for UMS surfaces, so it
3127 * shouldn't be necessary to recompile based on whether the framebuffer is
3130 if (wm_key
->multisample_fbo
&&
3131 nir_system_values
[SYSTEM_VALUE_SAMPLE_ID
].file
== BAD_FILE
)
3132 nir_system_values
[SYSTEM_VALUE_SAMPLE_ID
] = *emit_sampleid_setup();
3134 const fs_reg sample
= nir_system_values
[SYSTEM_VALUE_SAMPLE_ID
];
3135 const fs_reg mcs
= wm_key
->multisample_fbo
?
3136 emit_mcs_fetch(coords
, 3, brw_imm_ud(surface
)) : fs_reg();
3138 /* Use either a normal or a CMS texel fetch message depending on whether
3139 * the framebuffer is single or multisample. On SKL+ use the wide CMS
3140 * message just in case the framebuffer uses 16x multisampling, it should
3141 * be equivalent to the normal CMS fetch for lower multisampling modes.
3143 const opcode op
= !wm_key
->multisample_fbo
? SHADER_OPCODE_TXF_LOGICAL
:
3144 devinfo
->gen
>= 9 ? SHADER_OPCODE_TXF_CMS_W_LOGICAL
:
3145 SHADER_OPCODE_TXF_CMS_LOGICAL
;
3147 /* Emit the instruction. */
3148 const fs_reg srcs
[] = { coords
, fs_reg(), brw_imm_ud(0), fs_reg(),
3150 brw_imm_ud(surface
), brw_imm_ud(0),
3151 fs_reg(), brw_imm_ud(3), brw_imm_ud(0) };
3152 STATIC_ASSERT(ARRAY_SIZE(srcs
) == TEX_LOGICAL_NUM_SRCS
);
3154 fs_inst
*inst
= bld
.emit(op
, dst
, srcs
, ARRAY_SIZE(srcs
));
3155 inst
->size_written
= 4 * inst
->dst
.component_size(inst
->exec_size
);
3161 * Actual coherent framebuffer read implemented using the native render target
3162 * read message. Requires SKL+.
3165 emit_coherent_fb_read(const fs_builder
&bld
, const fs_reg
&dst
, unsigned target
)
3167 assert(bld
.shader
->devinfo
->gen
>= 9);
3168 fs_inst
*inst
= bld
.emit(FS_OPCODE_FB_READ_LOGICAL
, dst
);
3169 inst
->target
= target
;
3170 inst
->size_written
= 4 * inst
->dst
.component_size(inst
->exec_size
);
3176 alloc_temporary(const fs_builder
&bld
, unsigned size
, fs_reg
*regs
, unsigned n
)
3178 if (n
&& regs
[0].file
!= BAD_FILE
) {
3182 const fs_reg tmp
= bld
.vgrf(BRW_REGISTER_TYPE_F
, size
);
3184 for (unsigned i
= 0; i
< n
; i
++)
3192 alloc_frag_output(fs_visitor
*v
, unsigned location
)
3194 assert(v
->stage
== MESA_SHADER_FRAGMENT
);
3195 const brw_wm_prog_key
*const key
=
3196 reinterpret_cast<const brw_wm_prog_key
*>(v
->key
);
3197 const unsigned l
= GET_FIELD(location
, BRW_NIR_FRAG_OUTPUT_LOCATION
);
3198 const unsigned i
= GET_FIELD(location
, BRW_NIR_FRAG_OUTPUT_INDEX
);
3200 if (i
> 0 || (key
->force_dual_color_blend
&& l
== FRAG_RESULT_DATA1
))
3201 return alloc_temporary(v
->bld
, 4, &v
->dual_src_output
, 1);
3203 else if (l
== FRAG_RESULT_COLOR
)
3204 return alloc_temporary(v
->bld
, 4, v
->outputs
,
3205 MAX2(key
->nr_color_regions
, 1));
3207 else if (l
== FRAG_RESULT_DEPTH
)
3208 return alloc_temporary(v
->bld
, 1, &v
->frag_depth
, 1);
3210 else if (l
== FRAG_RESULT_STENCIL
)
3211 return alloc_temporary(v
->bld
, 1, &v
->frag_stencil
, 1);
3213 else if (l
== FRAG_RESULT_SAMPLE_MASK
)
3214 return alloc_temporary(v
->bld
, 1, &v
->sample_mask
, 1);
3216 else if (l
>= FRAG_RESULT_DATA0
&&
3217 l
< FRAG_RESULT_DATA0
+ BRW_MAX_DRAW_BUFFERS
)
3218 return alloc_temporary(v
->bld
, 4,
3219 &v
->outputs
[l
- FRAG_RESULT_DATA0
], 1);
3222 unreachable("Invalid location");
3226 fs_visitor::nir_emit_fs_intrinsic(const fs_builder
&bld
,
3227 nir_intrinsic_instr
*instr
)
3229 assert(stage
== MESA_SHADER_FRAGMENT
);
3232 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
3233 dest
= get_nir_dest(instr
->dest
);
3235 switch (instr
->intrinsic
) {
3236 case nir_intrinsic_load_front_face
:
3237 bld
.MOV(retype(dest
, BRW_REGISTER_TYPE_D
),
3238 *emit_frontfacing_interpolation());
3241 case nir_intrinsic_load_sample_pos
: {
3242 fs_reg sample_pos
= nir_system_values
[SYSTEM_VALUE_SAMPLE_POS
];
3243 assert(sample_pos
.file
!= BAD_FILE
);
3244 dest
.type
= sample_pos
.type
;
3245 bld
.MOV(dest
, sample_pos
);
3246 bld
.MOV(offset(dest
, bld
, 1), offset(sample_pos
, bld
, 1));
3250 case nir_intrinsic_load_layer_id
:
3251 dest
.type
= BRW_REGISTER_TYPE_UD
;
3252 bld
.MOV(dest
, fetch_render_target_array_index(bld
));
3255 case nir_intrinsic_load_helper_invocation
:
3256 case nir_intrinsic_load_sample_mask_in
:
3257 case nir_intrinsic_load_sample_id
: {
3258 gl_system_value sv
= nir_system_value_from_intrinsic(instr
->intrinsic
);
3259 fs_reg val
= nir_system_values
[sv
];
3260 assert(val
.file
!= BAD_FILE
);
3261 dest
.type
= val
.type
;
3266 case nir_intrinsic_store_output
: {
3267 const fs_reg src
= get_nir_src(instr
->src
[0]);
3268 const nir_const_value
*const_offset
= nir_src_as_const_value(instr
->src
[1]);
3269 assert(const_offset
&& "Indirect output stores not allowed");
3270 const unsigned location
= nir_intrinsic_base(instr
) +
3271 SET_FIELD(const_offset
->u32
[0], BRW_NIR_FRAG_OUTPUT_LOCATION
);
3272 const fs_reg new_dest
= retype(alloc_frag_output(this, location
),
3275 for (unsigned j
= 0; j
< instr
->num_components
; j
++)
3276 bld
.MOV(offset(new_dest
, bld
, nir_intrinsic_component(instr
) + j
),
3277 offset(src
, bld
, j
));
3282 case nir_intrinsic_load_output
: {
3283 const unsigned l
= GET_FIELD(nir_intrinsic_base(instr
),
3284 BRW_NIR_FRAG_OUTPUT_LOCATION
);
3285 assert(l
>= FRAG_RESULT_DATA0
);
3286 nir_const_value
*const_offset
= nir_src_as_const_value(instr
->src
[0]);
3287 assert(const_offset
&& "Indirect output loads not allowed");
3288 const unsigned target
= l
- FRAG_RESULT_DATA0
+ const_offset
->u32
[0];
3289 const fs_reg tmp
= bld
.vgrf(dest
.type
, 4);
3291 if (reinterpret_cast<const brw_wm_prog_key
*>(key
)->coherent_fb_fetch
)
3292 emit_coherent_fb_read(bld
, tmp
, target
);
3294 emit_non_coherent_fb_read(bld
, tmp
, target
);
3296 for (unsigned j
= 0; j
< instr
->num_components
; j
++) {
3297 bld
.MOV(offset(dest
, bld
, j
),
3298 offset(tmp
, bld
, nir_intrinsic_component(instr
) + j
));
3304 case nir_intrinsic_discard
:
3305 case nir_intrinsic_discard_if
: {
3306 /* We track our discarded pixels in f0.1. By predicating on it, we can
3307 * update just the flag bits that aren't yet discarded. If there's no
3308 * condition, we emit a CMP of g0 != g0, so all currently executing
3309 * channels will get turned off.
3312 if (instr
->intrinsic
== nir_intrinsic_discard_if
) {
3313 cmp
= bld
.CMP(bld
.null_reg_f(), get_nir_src(instr
->src
[0]),
3314 brw_imm_d(0), BRW_CONDITIONAL_Z
);
3316 fs_reg some_reg
= fs_reg(retype(brw_vec8_grf(0, 0),
3317 BRW_REGISTER_TYPE_UW
));
3318 cmp
= bld
.CMP(bld
.null_reg_f(), some_reg
, some_reg
, BRW_CONDITIONAL_NZ
);
3320 cmp
->predicate
= BRW_PREDICATE_NORMAL
;
3321 cmp
->flag_subreg
= 1;
3323 if (devinfo
->gen
>= 6) {
3324 emit_discard_jump();
3329 case nir_intrinsic_load_input
: {
3330 /* load_input is only used for flat inputs */
3331 unsigned base
= nir_intrinsic_base(instr
);
3332 unsigned component
= nir_intrinsic_component(instr
);
3333 unsigned num_components
= instr
->num_components
;
3334 enum brw_reg_type type
= dest
.type
;
3336 /* Special case fields in the VUE header */
3337 if (base
== VARYING_SLOT_LAYER
)
3339 else if (base
== VARYING_SLOT_VIEWPORT
)
3342 if (nir_dest_bit_size(instr
->dest
) == 64) {
3343 /* const_index is in 32-bit type size units that could not be aligned
3344 * with DF. We need to read the double vector as if it was a float
3345 * vector of twice the number of components to fetch the right data.
3347 type
= BRW_REGISTER_TYPE_F
;
3348 num_components
*= 2;
3351 for (unsigned int i
= 0; i
< num_components
; i
++) {
3352 struct brw_reg interp
= interp_reg(base
, component
+ i
);
3353 interp
= suboffset(interp
, 3);
3354 bld
.emit(FS_OPCODE_CINTERP
, offset(retype(dest
, type
), bld
, i
),
3355 retype(fs_reg(interp
), type
));
3358 if (nir_dest_bit_size(instr
->dest
) == 64) {
3359 shuffle_32bit_load_result_to_64bit_data(bld
,
3362 instr
->num_components
);
3367 case nir_intrinsic_load_barycentric_pixel
:
3368 case nir_intrinsic_load_barycentric_centroid
:
3369 case nir_intrinsic_load_barycentric_sample
:
3370 /* Do nothing - load_interpolated_input handling will handle it later. */
3373 case nir_intrinsic_load_barycentric_at_sample
: {
3374 const glsl_interp_mode interpolation
=
3375 (enum glsl_interp_mode
) nir_intrinsic_interp_mode(instr
);
3377 nir_const_value
*const_sample
= nir_src_as_const_value(instr
->src
[0]);
3380 unsigned msg_data
= const_sample
->i32
[0] << 4;
3382 emit_pixel_interpolater_send(bld
,
3383 FS_OPCODE_INTERPOLATE_AT_SAMPLE
,
3386 brw_imm_ud(msg_data
),
3389 const fs_reg sample_src
= retype(get_nir_src(instr
->src
[0]),
3390 BRW_REGISTER_TYPE_UD
);
3392 if (nir_src_is_dynamically_uniform(instr
->src
[0])) {
3393 const fs_reg sample_id
= bld
.emit_uniformize(sample_src
);
3394 const fs_reg msg_data
= vgrf(glsl_type::uint_type
);
3395 bld
.exec_all().group(1, 0)
3396 .SHL(msg_data
, sample_id
, brw_imm_ud(4u));
3397 emit_pixel_interpolater_send(bld
,
3398 FS_OPCODE_INTERPOLATE_AT_SAMPLE
,
3404 /* Make a loop that sends a message to the pixel interpolater
3405 * for the sample number in each live channel. If there are
3406 * multiple channels with the same sample number then these
3407 * will be handled simultaneously with a single interation of
3410 bld
.emit(BRW_OPCODE_DO
);
3412 /* Get the next live sample number into sample_id_reg */
3413 const fs_reg sample_id
= bld
.emit_uniformize(sample_src
);
3415 /* Set the flag register so that we can perform the send
3416 * message on all channels that have the same sample number
3418 bld
.CMP(bld
.null_reg_ud(),
3419 sample_src
, sample_id
,
3420 BRW_CONDITIONAL_EQ
);
3421 const fs_reg msg_data
= vgrf(glsl_type::uint_type
);
3422 bld
.exec_all().group(1, 0)
3423 .SHL(msg_data
, sample_id
, brw_imm_ud(4u));
3425 emit_pixel_interpolater_send(bld
,
3426 FS_OPCODE_INTERPOLATE_AT_SAMPLE
,
3431 set_predicate(BRW_PREDICATE_NORMAL
, inst
);
3433 /* Continue the loop if there are any live channels left */
3434 set_predicate_inv(BRW_PREDICATE_NORMAL
,
3436 bld
.emit(BRW_OPCODE_WHILE
));
3442 case nir_intrinsic_load_barycentric_at_offset
: {
3443 const glsl_interp_mode interpolation
=
3444 (enum glsl_interp_mode
) nir_intrinsic_interp_mode(instr
);
3446 nir_const_value
*const_offset
= nir_src_as_const_value(instr
->src
[0]);
3449 unsigned off_x
= MIN2((int)(const_offset
->f32
[0] * 16), 7) & 0xf;
3450 unsigned off_y
= MIN2((int)(const_offset
->f32
[1] * 16), 7) & 0xf;
3452 emit_pixel_interpolater_send(bld
,
3453 FS_OPCODE_INTERPOLATE_AT_SHARED_OFFSET
,
3456 brw_imm_ud(off_x
| (off_y
<< 4)),
3459 fs_reg src
= vgrf(glsl_type::ivec2_type
);
3460 fs_reg offset_src
= retype(get_nir_src(instr
->src
[0]),
3461 BRW_REGISTER_TYPE_F
);
3462 for (int i
= 0; i
< 2; i
++) {
3463 fs_reg temp
= vgrf(glsl_type::float_type
);
3464 bld
.MUL(temp
, offset(offset_src
, bld
, i
), brw_imm_f(16.0f
));
3465 fs_reg itemp
= vgrf(glsl_type::int_type
);
3467 bld
.MOV(itemp
, temp
);
3469 /* Clamp the upper end of the range to +7/16.
3470 * ARB_gpu_shader5 requires that we support a maximum offset
3471 * of +0.5, which isn't representable in a S0.4 value -- if
3472 * we didn't clamp it, we'd end up with -8/16, which is the
3473 * opposite of what the shader author wanted.
3475 * This is legal due to ARB_gpu_shader5's quantization
3478 * "Not all values of <offset> may be supported; x and y
3479 * offsets may be rounded to fixed-point values with the
3480 * number of fraction bits given by the
3481 * implementation-dependent constant
3482 * FRAGMENT_INTERPOLATION_OFFSET_BITS"
3484 set_condmod(BRW_CONDITIONAL_L
,
3485 bld
.SEL(offset(src
, bld
, i
), itemp
, brw_imm_d(7)));
3488 const enum opcode opcode
= FS_OPCODE_INTERPOLATE_AT_PER_SLOT_OFFSET
;
3489 emit_pixel_interpolater_send(bld
,
3499 case nir_intrinsic_load_interpolated_input
: {
3500 if (nir_intrinsic_base(instr
) == VARYING_SLOT_POS
) {
3501 emit_fragcoord_interpolation(dest
);
3505 assert(instr
->src
[0].ssa
&&
3506 instr
->src
[0].ssa
->parent_instr
->type
== nir_instr_type_intrinsic
);
3507 nir_intrinsic_instr
*bary_intrinsic
=
3508 nir_instr_as_intrinsic(instr
->src
[0].ssa
->parent_instr
);
3509 nir_intrinsic_op bary_intrin
= bary_intrinsic
->intrinsic
;
3510 enum glsl_interp_mode interp_mode
=
3511 (enum glsl_interp_mode
) nir_intrinsic_interp_mode(bary_intrinsic
);
3514 if (bary_intrin
== nir_intrinsic_load_barycentric_at_offset
||
3515 bary_intrin
== nir_intrinsic_load_barycentric_at_sample
) {
3516 /* Use the result of the PI message */
3517 dst_xy
= retype(get_nir_src(instr
->src
[0]), BRW_REGISTER_TYPE_F
);
3519 /* Use the delta_xy values computed from the payload */
3520 enum brw_barycentric_mode bary
=
3521 brw_barycentric_mode(interp_mode
, bary_intrin
);
3523 dst_xy
= this->delta_xy
[bary
];
3526 for (unsigned int i
= 0; i
< instr
->num_components
; i
++) {
3528 fs_reg(interp_reg(nir_intrinsic_base(instr
),
3529 nir_intrinsic_component(instr
) + i
));
3530 interp
.type
= BRW_REGISTER_TYPE_F
;
3531 dest
.type
= BRW_REGISTER_TYPE_F
;
3533 if (devinfo
->gen
< 6 && interp_mode
== INTERP_MODE_SMOOTH
) {
3534 fs_reg tmp
= vgrf(glsl_type::float_type
);
3535 bld
.emit(FS_OPCODE_LINTERP
, tmp
, dst_xy
, interp
);
3536 bld
.MUL(offset(dest
, bld
, i
), tmp
, this->pixel_w
);
3538 bld
.emit(FS_OPCODE_LINTERP
, offset(dest
, bld
, i
), dst_xy
, interp
);
3545 nir_emit_intrinsic(bld
, instr
);
3551 fs_visitor::nir_emit_cs_intrinsic(const fs_builder
&bld
,
3552 nir_intrinsic_instr
*instr
)
3554 assert(stage
== MESA_SHADER_COMPUTE
);
3555 struct brw_cs_prog_data
*cs_prog_data
= brw_cs_prog_data(prog_data
);
3558 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
3559 dest
= get_nir_dest(instr
->dest
);
3561 switch (instr
->intrinsic
) {
3562 case nir_intrinsic_barrier
:
3564 cs_prog_data
->uses_barrier
= true;
3567 case nir_intrinsic_load_subgroup_id
:
3568 bld
.MOV(retype(dest
, BRW_REGISTER_TYPE_UD
), subgroup_id
);
3571 case nir_intrinsic_load_local_invocation_id
:
3572 case nir_intrinsic_load_work_group_id
: {
3573 gl_system_value sv
= nir_system_value_from_intrinsic(instr
->intrinsic
);
3574 fs_reg val
= nir_system_values
[sv
];
3575 assert(val
.file
!= BAD_FILE
);
3576 dest
.type
= val
.type
;
3577 for (unsigned i
= 0; i
< 3; i
++)
3578 bld
.MOV(offset(dest
, bld
, i
), offset(val
, bld
, i
));
3582 case nir_intrinsic_load_num_work_groups
: {
3583 const unsigned surface
=
3584 cs_prog_data
->binding_table
.work_groups_start
;
3586 cs_prog_data
->uses_num_work_groups
= true;
3588 fs_reg surf_index
= brw_imm_ud(surface
);
3589 brw_mark_surface_used(prog_data
, surface
);
3591 /* Read the 3 GLuint components of gl_NumWorkGroups */
3592 for (unsigned i
= 0; i
< 3; i
++) {
3593 fs_reg read_result
=
3594 emit_untyped_read(bld
, surf_index
,
3596 1 /* dims */, 1 /* size */,
3597 BRW_PREDICATE_NONE
);
3598 read_result
.type
= dest
.type
;
3599 bld
.MOV(dest
, read_result
);
3600 dest
= offset(dest
, bld
, 1);
3605 case nir_intrinsic_shared_atomic_add
:
3606 nir_emit_shared_atomic(bld
, BRW_AOP_ADD
, instr
);
3608 case nir_intrinsic_shared_atomic_imin
:
3609 nir_emit_shared_atomic(bld
, BRW_AOP_IMIN
, instr
);
3611 case nir_intrinsic_shared_atomic_umin
:
3612 nir_emit_shared_atomic(bld
, BRW_AOP_UMIN
, instr
);
3614 case nir_intrinsic_shared_atomic_imax
:
3615 nir_emit_shared_atomic(bld
, BRW_AOP_IMAX
, instr
);
3617 case nir_intrinsic_shared_atomic_umax
:
3618 nir_emit_shared_atomic(bld
, BRW_AOP_UMAX
, instr
);
3620 case nir_intrinsic_shared_atomic_and
:
3621 nir_emit_shared_atomic(bld
, BRW_AOP_AND
, instr
);
3623 case nir_intrinsic_shared_atomic_or
:
3624 nir_emit_shared_atomic(bld
, BRW_AOP_OR
, instr
);
3626 case nir_intrinsic_shared_atomic_xor
:
3627 nir_emit_shared_atomic(bld
, BRW_AOP_XOR
, instr
);
3629 case nir_intrinsic_shared_atomic_exchange
:
3630 nir_emit_shared_atomic(bld
, BRW_AOP_MOV
, instr
);
3632 case nir_intrinsic_shared_atomic_comp_swap
:
3633 nir_emit_shared_atomic(bld
, BRW_AOP_CMPWR
, instr
);
3636 case nir_intrinsic_load_shared
: {
3637 assert(devinfo
->gen
>= 7);
3639 fs_reg surf_index
= brw_imm_ud(GEN7_BTI_SLM
);
3641 /* Get the offset to read from */
3643 nir_const_value
*const_offset
= nir_src_as_const_value(instr
->src
[0]);
3645 offset_reg
= brw_imm_ud(instr
->const_index
[0] + const_offset
->u32
[0]);
3647 offset_reg
= vgrf(glsl_type::uint_type
);
3649 retype(get_nir_src(instr
->src
[0]), BRW_REGISTER_TYPE_UD
),
3650 brw_imm_ud(instr
->const_index
[0]));
3653 /* Read the vector */
3654 do_untyped_vector_read(bld
, dest
, surf_index
, offset_reg
,
3655 instr
->num_components
);
3659 case nir_intrinsic_store_shared
: {
3660 assert(devinfo
->gen
>= 7);
3663 fs_reg surf_index
= brw_imm_ud(GEN7_BTI_SLM
);
3666 fs_reg val_reg
= get_nir_src(instr
->src
[0]);
3669 unsigned writemask
= instr
->const_index
[1];
3671 /* get_nir_src() retypes to integer. Be wary of 64-bit types though
3672 * since the untyped writes below operate in units of 32-bits, which
3673 * means that we need to write twice as many components each time.
3674 * Also, we have to suffle 64-bit data to be in the appropriate layout
3675 * expected by our 32-bit write messages.
3677 unsigned type_size
= 4;
3678 if (nir_src_bit_size(instr
->src
[0]) == 64) {
3680 val_reg
= shuffle_64bit_data_for_32bit_write(bld
,
3681 val_reg
, instr
->num_components
);
3684 unsigned type_slots
= type_size
/ 4;
3686 /* Combine groups of consecutive enabled channels in one write
3687 * message. We use ffs to find the first enabled channel and then ffs on
3688 * the bit-inverse, down-shifted writemask to determine the length of
3689 * the block of enabled bits.
3692 unsigned first_component
= ffs(writemask
) - 1;
3693 unsigned length
= ffs(~(writemask
>> first_component
)) - 1;
3695 /* We can't write more than 2 64-bit components at once. Limit the
3696 * length of the write to what we can do and let the next iteration
3700 length
= MIN2(2, length
);
3703 nir_const_value
*const_offset
= nir_src_as_const_value(instr
->src
[1]);
3705 offset_reg
= brw_imm_ud(instr
->const_index
[0] + const_offset
->u32
[0] +
3706 type_size
* first_component
);
3708 offset_reg
= vgrf(glsl_type::uint_type
);
3710 retype(get_nir_src(instr
->src
[1]), BRW_REGISTER_TYPE_UD
),
3711 brw_imm_ud(instr
->const_index
[0] + type_size
* first_component
));
3714 emit_untyped_write(bld
, surf_index
, offset_reg
,
3715 offset(val_reg
, bld
, first_component
* type_slots
),
3716 1 /* dims */, length
* type_slots
,
3717 BRW_PREDICATE_NONE
);
3719 /* Clear the bits in the writemask that we just wrote, then try
3720 * again to see if more channels are left.
3722 writemask
&= (15 << (first_component
+ length
));
3729 nir_emit_intrinsic(bld
, instr
);
3735 brw_nir_reduction_op_identity(const fs_builder
&bld
,
3736 nir_op op
, brw_reg_type type
)
3738 nir_const_value value
= nir_alu_binop_identity(op
, type_sz(type
) * 8);
3739 switch (type_sz(type
)) {
3741 assert(type
!= BRW_REGISTER_TYPE_HF
);
3742 return retype(brw_imm_uw(value
.u16
[0]), type
);
3744 return retype(brw_imm_ud(value
.u32
[0]), type
);
3746 if (type
== BRW_REGISTER_TYPE_DF
)
3747 return setup_imm_df(bld
, value
.f64
[0]);
3749 return retype(brw_imm_u64(value
.u64
[0]), type
);
3751 unreachable("Invalid type size");
3756 brw_op_for_nir_reduction_op(nir_op op
)
3759 case nir_op_iadd
: return BRW_OPCODE_ADD
;
3760 case nir_op_fadd
: return BRW_OPCODE_ADD
;
3761 case nir_op_imul
: return BRW_OPCODE_MUL
;
3762 case nir_op_fmul
: return BRW_OPCODE_MUL
;
3763 case nir_op_imin
: return BRW_OPCODE_SEL
;
3764 case nir_op_umin
: return BRW_OPCODE_SEL
;
3765 case nir_op_fmin
: return BRW_OPCODE_SEL
;
3766 case nir_op_imax
: return BRW_OPCODE_SEL
;
3767 case nir_op_umax
: return BRW_OPCODE_SEL
;
3768 case nir_op_fmax
: return BRW_OPCODE_SEL
;
3769 case nir_op_iand
: return BRW_OPCODE_AND
;
3770 case nir_op_ior
: return BRW_OPCODE_OR
;
3771 case nir_op_ixor
: return BRW_OPCODE_XOR
;
3773 unreachable("Invalid reduction operation");
3777 static brw_conditional_mod
3778 brw_cond_mod_for_nir_reduction_op(nir_op op
)
3781 case nir_op_iadd
: return BRW_CONDITIONAL_NONE
;
3782 case nir_op_fadd
: return BRW_CONDITIONAL_NONE
;
3783 case nir_op_imul
: return BRW_CONDITIONAL_NONE
;
3784 case nir_op_fmul
: return BRW_CONDITIONAL_NONE
;
3785 case nir_op_imin
: return BRW_CONDITIONAL_L
;
3786 case nir_op_umin
: return BRW_CONDITIONAL_L
;
3787 case nir_op_fmin
: return BRW_CONDITIONAL_L
;
3788 case nir_op_imax
: return BRW_CONDITIONAL_GE
;
3789 case nir_op_umax
: return BRW_CONDITIONAL_GE
;
3790 case nir_op_fmax
: return BRW_CONDITIONAL_GE
;
3791 case nir_op_iand
: return BRW_CONDITIONAL_NONE
;
3792 case nir_op_ior
: return BRW_CONDITIONAL_NONE
;
3793 case nir_op_ixor
: return BRW_CONDITIONAL_NONE
;
3795 unreachable("Invalid reduction operation");
3800 fs_visitor::nir_emit_intrinsic(const fs_builder
&bld
, nir_intrinsic_instr
*instr
)
3803 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
3804 dest
= get_nir_dest(instr
->dest
);
3806 switch (instr
->intrinsic
) {
3807 case nir_intrinsic_image_var_load
:
3808 case nir_intrinsic_image_var_store
:
3809 case nir_intrinsic_image_var_atomic_add
:
3810 case nir_intrinsic_image_var_atomic_min
:
3811 case nir_intrinsic_image_var_atomic_max
:
3812 case nir_intrinsic_image_var_atomic_and
:
3813 case nir_intrinsic_image_var_atomic_or
:
3814 case nir_intrinsic_image_var_atomic_xor
:
3815 case nir_intrinsic_image_var_atomic_exchange
:
3816 case nir_intrinsic_image_var_atomic_comp_swap
: {
3817 using namespace image_access
;
3819 if (stage
== MESA_SHADER_FRAGMENT
&&
3820 instr
->intrinsic
!= nir_intrinsic_image_var_load
)
3821 brw_wm_prog_data(prog_data
)->has_side_effects
= true;
3823 /* Get the referenced image variable and type. */
3824 const nir_variable
*var
= instr
->variables
[0]->var
;
3825 const glsl_type
*type
= var
->type
->without_array();
3826 const brw_reg_type base_type
= get_image_base_type(type
);
3828 /* Get some metadata from the image intrinsic. */
3829 const nir_intrinsic_info
*info
= &nir_intrinsic_infos
[instr
->intrinsic
];
3830 const unsigned arr_dims
= type
->sampler_array
? 1 : 0;
3831 const unsigned surf_dims
= type
->coordinate_components() - arr_dims
;
3832 const unsigned format
= var
->data
.image
.format
;
3833 const unsigned dest_components
= nir_intrinsic_dest_components(instr
);
3835 /* Get the arguments of the image intrinsic. */
3836 const fs_reg image
= get_nir_image_deref(instr
->variables
[0]);
3837 const fs_reg addr
= retype(get_nir_src(instr
->src
[0]),
3838 BRW_REGISTER_TYPE_UD
);
3839 const fs_reg src0
= (info
->num_srcs
>= 3 ?
3840 retype(get_nir_src(instr
->src
[2]), base_type
) :
3842 const fs_reg src1
= (info
->num_srcs
>= 4 ?
3843 retype(get_nir_src(instr
->src
[3]), base_type
) :
3847 /* Emit an image load, store or atomic op. */
3848 if (instr
->intrinsic
== nir_intrinsic_image_var_load
)
3849 tmp
= emit_image_load(bld
, image
, addr
, surf_dims
, arr_dims
, format
);
3851 else if (instr
->intrinsic
== nir_intrinsic_image_var_store
)
3852 emit_image_store(bld
, image
, addr
, src0
, surf_dims
, arr_dims
,
3853 var
->data
.image
.write_only
? GL_NONE
: format
);
3856 tmp
= emit_image_atomic(bld
, image
, addr
, src0
, src1
,
3857 surf_dims
, arr_dims
, dest_components
,
3858 get_image_atomic_op(instr
->intrinsic
, type
));
3860 /* Assign the result. */
3861 for (unsigned c
= 0; c
< dest_components
; ++c
) {
3862 bld
.MOV(offset(retype(dest
, base_type
), bld
, c
),
3863 offset(tmp
, bld
, c
));
3868 case nir_intrinsic_memory_barrier_atomic_counter
:
3869 case nir_intrinsic_memory_barrier_buffer
:
3870 case nir_intrinsic_memory_barrier_image
:
3871 case nir_intrinsic_memory_barrier
: {
3872 const fs_builder ubld
= bld
.group(8, 0);
3873 const fs_reg tmp
= ubld
.vgrf(BRW_REGISTER_TYPE_UD
, 2);
3874 ubld
.emit(SHADER_OPCODE_MEMORY_FENCE
, tmp
)
3875 ->size_written
= 2 * REG_SIZE
;
3879 case nir_intrinsic_group_memory_barrier
:
3880 case nir_intrinsic_memory_barrier_shared
:
3881 /* We treat these workgroup-level barriers as no-ops. This should be
3882 * safe at present and as long as:
3884 * - Memory access instructions are not subsequently reordered by the
3885 * compiler back-end.
3887 * - All threads from a given compute shader workgroup fit within a
3888 * single subslice and therefore talk to the same HDC shared unit
3889 * what supposedly guarantees ordering and coherency between threads
3890 * from the same workgroup. This may change in the future when we
3891 * start splitting workgroups across multiple subslices.
3893 * - The context is not in fault-and-stream mode, which could cause
3894 * memory transactions (including to SLM) prior to the barrier to be
3895 * replayed after the barrier if a pagefault occurs. This shouldn't
3896 * be a problem up to and including SKL because fault-and-stream is
3897 * not usable due to hardware issues, but that's likely to change in
3902 case nir_intrinsic_shader_clock
: {
3903 /* We cannot do anything if there is an event, so ignore it for now */
3904 const fs_reg shader_clock
= get_timestamp(bld
);
3905 const fs_reg srcs
[] = { component(shader_clock
, 0),
3906 component(shader_clock
, 1) };
3907 bld
.LOAD_PAYLOAD(dest
, srcs
, ARRAY_SIZE(srcs
), 0);
3911 case nir_intrinsic_image_var_size
: {
3912 /* Get the referenced image variable and type. */
3913 const nir_variable
*var
= instr
->variables
[0]->var
;
3914 const glsl_type
*type
= var
->type
->without_array();
3916 /* Get the size of the image. */
3917 const fs_reg image
= get_nir_image_deref(instr
->variables
[0]);
3918 const fs_reg size
= offset(image
, bld
, BRW_IMAGE_PARAM_SIZE_OFFSET
);
3920 /* For 1DArray image types, the array index is stored in the Z component.
3921 * Fix this by swizzling the Z component to the Y component.
3923 const bool is_1d_array_image
=
3924 type
->sampler_dimensionality
== GLSL_SAMPLER_DIM_1D
&&
3925 type
->sampler_array
;
3927 /* For CubeArray images, we should count the number of cubes instead
3928 * of the number of faces. Fix it by dividing the (Z component) by 6.
3930 const bool is_cube_array_image
=
3931 type
->sampler_dimensionality
== GLSL_SAMPLER_DIM_CUBE
&&
3932 type
->sampler_array
;
3934 /* Copy all the components. */
3935 for (unsigned c
= 0; c
< instr
->dest
.ssa
.num_components
; ++c
) {
3936 if ((int)c
>= type
->coordinate_components()) {
3937 bld
.MOV(offset(retype(dest
, BRW_REGISTER_TYPE_D
), bld
, c
),
3939 } else if (c
== 1 && is_1d_array_image
) {
3940 bld
.MOV(offset(retype(dest
, BRW_REGISTER_TYPE_D
), bld
, c
),
3941 offset(size
, bld
, 2));
3942 } else if (c
== 2 && is_cube_array_image
) {
3943 bld
.emit(SHADER_OPCODE_INT_QUOTIENT
,
3944 offset(retype(dest
, BRW_REGISTER_TYPE_D
), bld
, c
),
3945 offset(size
, bld
, c
), brw_imm_d(6));
3947 bld
.MOV(offset(retype(dest
, BRW_REGISTER_TYPE_D
), bld
, c
),
3948 offset(size
, bld
, c
));
3955 case nir_intrinsic_image_var_samples
:
3956 /* The driver does not support multi-sampled images. */
3957 bld
.MOV(retype(dest
, BRW_REGISTER_TYPE_D
), brw_imm_d(1));
3960 case nir_intrinsic_load_uniform
: {
3961 /* Offsets are in bytes but they should always aligned to
3964 assert(instr
->const_index
[0] % 4 == 0 ||
3965 instr
->const_index
[0] % type_sz(dest
.type
) == 0);
3967 fs_reg
src(UNIFORM
, instr
->const_index
[0] / 4, dest
.type
);
3969 nir_const_value
*const_offset
= nir_src_as_const_value(instr
->src
[0]);
3971 assert(const_offset
->u32
[0] % type_sz(dest
.type
) == 0);
3972 /* For 16-bit types we add the module of the const_index[0]
3973 * offset to access to not 32-bit aligned element
3975 src
.offset
= const_offset
->u32
[0] + instr
->const_index
[0] % 4;
3977 for (unsigned j
= 0; j
< instr
->num_components
; j
++) {
3978 bld
.MOV(offset(dest
, bld
, j
), offset(src
, bld
, j
));
3981 fs_reg indirect
= retype(get_nir_src(instr
->src
[0]),
3982 BRW_REGISTER_TYPE_UD
);
3984 /* We need to pass a size to the MOV_INDIRECT but we don't want it to
3985 * go past the end of the uniform. In order to keep the n'th
3986 * component from running past, we subtract off the size of all but
3987 * one component of the vector.
3989 assert(instr
->const_index
[1] >=
3990 instr
->num_components
* (int) type_sz(dest
.type
));
3991 unsigned read_size
= instr
->const_index
[1] -
3992 (instr
->num_components
- 1) * type_sz(dest
.type
);
3994 bool supports_64bit_indirects
=
3995 !devinfo
->is_cherryview
&& !gen_device_info_is_9lp(devinfo
);
3997 if (type_sz(dest
.type
) != 8 || supports_64bit_indirects
) {
3998 for (unsigned j
= 0; j
< instr
->num_components
; j
++) {
3999 bld
.emit(SHADER_OPCODE_MOV_INDIRECT
,
4000 offset(dest
, bld
, j
), offset(src
, bld
, j
),
4001 indirect
, brw_imm_ud(read_size
));
4004 const unsigned num_mov_indirects
=
4005 type_sz(dest
.type
) / type_sz(BRW_REGISTER_TYPE_UD
);
4006 /* We read a little bit less per MOV INDIRECT, as they are now
4007 * 32-bits ones instead of 64-bit. Fix read_size then.
4009 const unsigned read_size_32bit
= read_size
-
4010 (num_mov_indirects
- 1) * type_sz(BRW_REGISTER_TYPE_UD
);
4011 for (unsigned j
= 0; j
< instr
->num_components
; j
++) {
4012 for (unsigned i
= 0; i
< num_mov_indirects
; i
++) {
4013 bld
.emit(SHADER_OPCODE_MOV_INDIRECT
,
4014 subscript(offset(dest
, bld
, j
), BRW_REGISTER_TYPE_UD
, i
),
4015 subscript(offset(src
, bld
, j
), BRW_REGISTER_TYPE_UD
, i
),
4016 indirect
, brw_imm_ud(read_size_32bit
));
4024 case nir_intrinsic_load_ubo
: {
4025 nir_const_value
*const_index
= nir_src_as_const_value(instr
->src
[0]);
4029 const unsigned index
= stage_prog_data
->binding_table
.ubo_start
+
4030 const_index
->u32
[0];
4031 surf_index
= brw_imm_ud(index
);
4032 brw_mark_surface_used(prog_data
, index
);
4034 /* The block index is not a constant. Evaluate the index expression
4035 * per-channel and add the base UBO index; we have to select a value
4036 * from any live channel.
4038 surf_index
= vgrf(glsl_type::uint_type
);
4039 bld
.ADD(surf_index
, get_nir_src(instr
->src
[0]),
4040 brw_imm_ud(stage_prog_data
->binding_table
.ubo_start
));
4041 surf_index
= bld
.emit_uniformize(surf_index
);
4043 /* Assume this may touch any UBO. It would be nice to provide
4044 * a tighter bound, but the array information is already lowered away.
4046 brw_mark_surface_used(prog_data
,
4047 stage_prog_data
->binding_table
.ubo_start
+
4048 nir
->info
.num_ubos
- 1);
4051 nir_const_value
*const_offset
= nir_src_as_const_value(instr
->src
[1]);
4052 if (const_offset
== NULL
) {
4053 fs_reg base_offset
= retype(get_nir_src(instr
->src
[1]),
4054 BRW_REGISTER_TYPE_UD
);
4056 for (int i
= 0; i
< instr
->num_components
; i
++)
4057 VARYING_PULL_CONSTANT_LOAD(bld
, offset(dest
, bld
, i
), surf_index
,
4058 base_offset
, i
* type_sz(dest
.type
));
4060 /* Even if we are loading doubles, a pull constant load will load
4061 * a 32-bit vec4, so should only reserve vgrf space for that. If we
4062 * need to load a full dvec4 we will have to emit 2 loads. This is
4063 * similar to demote_pull_constants(), except that in that case we
4064 * see individual accesses to each component of the vector and then
4065 * we let CSE deal with duplicate loads. Here we see a vector access
4066 * and we have to split it if necessary.
4068 const unsigned type_size
= type_sz(dest
.type
);
4070 /* See if we've selected this as a push constant candidate */
4072 const unsigned ubo_block
= const_index
->u32
[0];
4073 const unsigned offset_256b
= const_offset
->u32
[0] / 32;
4076 for (int i
= 0; i
< 4; i
++) {
4077 const struct brw_ubo_range
*range
= &prog_data
->ubo_ranges
[i
];
4078 if (range
->block
== ubo_block
&&
4079 offset_256b
>= range
->start
&&
4080 offset_256b
< range
->start
+ range
->length
) {
4082 push_reg
= fs_reg(UNIFORM
, UBO_START
+ i
, dest
.type
);
4083 push_reg
.offset
= const_offset
->u32
[0] - 32 * range
->start
;
4088 if (push_reg
.file
!= BAD_FILE
) {
4089 for (unsigned i
= 0; i
< instr
->num_components
; i
++) {
4090 bld
.MOV(offset(dest
, bld
, i
),
4091 byte_offset(push_reg
, i
* type_size
));
4097 const unsigned block_sz
= 64; /* Fetch one cacheline at a time. */
4098 const fs_builder ubld
= bld
.exec_all().group(block_sz
/ 4, 0);
4099 const fs_reg packed_consts
= ubld
.vgrf(BRW_REGISTER_TYPE_UD
);
4101 for (unsigned c
= 0; c
< instr
->num_components
;) {
4102 const unsigned base
= const_offset
->u32
[0] + c
* type_size
;
4103 /* Number of usable components in the next block-aligned load. */
4104 const unsigned count
= MIN2(instr
->num_components
- c
,
4105 (block_sz
- base
% block_sz
) / type_size
);
4107 ubld
.emit(FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD
,
4108 packed_consts
, surf_index
,
4109 brw_imm_ud(base
& ~(block_sz
- 1)));
4111 const fs_reg consts
=
4112 retype(byte_offset(packed_consts
, base
& (block_sz
- 1)),
4115 for (unsigned d
= 0; d
< count
; d
++)
4116 bld
.MOV(offset(dest
, bld
, c
+ d
), component(consts
, d
));
4124 case nir_intrinsic_load_ssbo
: {
4125 assert(devinfo
->gen
>= 7);
4127 nir_const_value
*const_uniform_block
=
4128 nir_src_as_const_value(instr
->src
[0]);
4131 if (const_uniform_block
) {
4132 unsigned index
= stage_prog_data
->binding_table
.ssbo_start
+
4133 const_uniform_block
->u32
[0];
4134 surf_index
= brw_imm_ud(index
);
4135 brw_mark_surface_used(prog_data
, index
);
4137 surf_index
= vgrf(glsl_type::uint_type
);
4138 bld
.ADD(surf_index
, get_nir_src(instr
->src
[0]),
4139 brw_imm_ud(stage_prog_data
->binding_table
.ssbo_start
));
4141 /* Assume this may touch any UBO. It would be nice to provide
4142 * a tighter bound, but the array information is already lowered away.
4144 brw_mark_surface_used(prog_data
,
4145 stage_prog_data
->binding_table
.ssbo_start
+
4146 nir
->info
.num_ssbos
- 1);
4150 nir_const_value
*const_offset
= nir_src_as_const_value(instr
->src
[1]);
4152 offset_reg
= brw_imm_ud(const_offset
->u32
[0]);
4154 offset_reg
= retype(get_nir_src(instr
->src
[1]), BRW_REGISTER_TYPE_UD
);
4157 /* Read the vector */
4158 do_untyped_vector_read(bld
, dest
, surf_index
, offset_reg
,
4159 instr
->num_components
);
4164 case nir_intrinsic_store_ssbo
: {
4165 assert(devinfo
->gen
>= 7);
4167 if (stage
== MESA_SHADER_FRAGMENT
)
4168 brw_wm_prog_data(prog_data
)->has_side_effects
= true;
4172 nir_const_value
*const_uniform_block
=
4173 nir_src_as_const_value(instr
->src
[1]);
4174 if (const_uniform_block
) {
4175 unsigned index
= stage_prog_data
->binding_table
.ssbo_start
+
4176 const_uniform_block
->u32
[0];
4177 surf_index
= brw_imm_ud(index
);
4178 brw_mark_surface_used(prog_data
, index
);
4180 surf_index
= vgrf(glsl_type::uint_type
);
4181 bld
.ADD(surf_index
, get_nir_src(instr
->src
[1]),
4182 brw_imm_ud(stage_prog_data
->binding_table
.ssbo_start
));
4184 brw_mark_surface_used(prog_data
,
4185 stage_prog_data
->binding_table
.ssbo_start
+
4186 nir
->info
.num_ssbos
- 1);
4190 fs_reg val_reg
= get_nir_src(instr
->src
[0]);
4193 unsigned writemask
= instr
->const_index
[0];
4195 /* get_nir_src() retypes to integer. Be wary of 64-bit types though
4196 * since the untyped writes below operate in units of 32-bits, which
4197 * means that we need to write twice as many components each time.
4198 * Also, we have to suffle 64-bit data to be in the appropriate layout
4199 * expected by our 32-bit write messages.
4201 unsigned bit_size
= nir_src_bit_size(instr
->src
[0]);
4202 unsigned type_size
= bit_size
/ 8;
4204 /* Combine groups of consecutive enabled channels in one write
4205 * message. We use ffs to find the first enabled channel and then ffs on
4206 * the bit-inverse, down-shifted writemask to determine the num_components
4207 * of the block of enabled bits.
4210 unsigned first_component
= ffs(writemask
) - 1;
4211 unsigned num_components
= ffs(~(writemask
>> first_component
)) - 1;
4212 fs_reg write_src
= offset(val_reg
, bld
, first_component
);
4214 nir_const_value
*const_offset
= nir_src_as_const_value(instr
->src
[2]);
4216 if (type_size
> 4) {
4217 /* We can't write more than 2 64-bit components at once. Limit
4218 * the num_components of the write to what we can do and let the next
4219 * iteration handle the rest.
4221 num_components
= MIN2(2, num_components
);
4222 write_src
= shuffle_64bit_data_for_32bit_write(bld
, write_src
,
4224 } else if (type_size
< 4) {
4225 assert(type_size
== 2);
4226 /* For 16-bit types we pack two consecutive values into a 32-bit
4227 * word and use an untyped write message. For single values or not
4228 * 32-bit-aligned we need to use byte-scattered writes because
4229 * untyped writes works with 32-bit components with 32-bit
4230 * alignment. byte_scattered_write messages only support one
4231 * 16-bit component at a time. As VK_KHR_relaxed_block_layout
4232 * could be enabled we can not guarantee that not constant offsets
4233 * to be 32-bit aligned for 16-bit types. For example an array, of
4234 * 16-bit vec3 with array element stride of 6.
4236 * In the case of 32-bit aligned constant offsets if there is
4237 * a 3-components vector we submit one untyped-write message
4238 * of 32-bit (first two components), and one byte-scattered
4239 * write message (the last component).
4242 if ( !const_offset
|| ((const_offset
->u32
[0] +
4243 type_size
* first_component
) % 4)) {
4244 /* If we use a .yz writemask we also need to emit 2
4245 * byte-scattered write messages because of y-component not
4246 * being aligned to 32-bit.
4249 } else if (num_components
> 2 && (num_components
% 2)) {
4250 /* If there is an odd number of consecutive components we left
4251 * the not paired component for a following emit of length == 1
4252 * with byte_scattered_write.
4256 /* For num_components == 1 we are also shuffling the component
4257 * because byte scattered writes of 16-bit need values to be dword
4258 * aligned. Shuffling only one component would be the same as
4261 fs_reg tmp
= bld
.vgrf(BRW_REGISTER_TYPE_D
,
4262 DIV_ROUND_UP(num_components
, 2));
4263 shuffle_16bit_data_for_32bit_write(bld
, tmp
, write_src
,
4271 offset_reg
= brw_imm_ud(const_offset
->u32
[0] +
4272 type_size
* first_component
);
4274 offset_reg
= vgrf(glsl_type::uint_type
);
4276 retype(get_nir_src(instr
->src
[2]), BRW_REGISTER_TYPE_UD
),
4277 brw_imm_ud(type_size
* first_component
));
4280 if (type_size
< 4 && num_components
== 1) {
4281 assert(type_size
== 2);
4282 /* Untyped Surface messages have a fixed 32-bit size, so we need
4283 * to rely on byte scattered in order to write 16-bit elements.
4284 * The byte_scattered_write message needs that every written 16-bit
4285 * type to be aligned 32-bits (stride=2).
4287 emit_byte_scattered_write(bld
, surf_index
, offset_reg
,
4291 BRW_PREDICATE_NONE
);
4293 assert(num_components
* type_size
<= 16);
4294 assert((num_components
* type_size
) % 4 == 0);
4295 assert(offset_reg
.file
!= BRW_IMMEDIATE_VALUE
||
4296 offset_reg
.ud
% 4 == 0);
4297 unsigned num_slots
= (num_components
* type_size
) / 4;
4299 emit_untyped_write(bld
, surf_index
, offset_reg
,
4301 1 /* dims */, num_slots
,
4302 BRW_PREDICATE_NONE
);
4305 /* Clear the bits in the writemask that we just wrote, then try
4306 * again to see if more channels are left.
4308 writemask
&= (15 << (first_component
+ num_components
));
4313 case nir_intrinsic_store_output
: {
4314 fs_reg src
= get_nir_src(instr
->src
[0]);
4316 nir_const_value
*const_offset
= nir_src_as_const_value(instr
->src
[1]);
4317 assert(const_offset
&& "Indirect output stores not allowed");
4319 unsigned num_components
= instr
->num_components
;
4320 unsigned first_component
= nir_intrinsic_component(instr
);
4321 if (nir_src_bit_size(instr
->src
[0]) == 64) {
4322 src
= shuffle_64bit_data_for_32bit_write(bld
, src
, num_components
);
4323 num_components
*= 2;
4326 fs_reg new_dest
= retype(offset(outputs
[instr
->const_index
[0]], bld
,
4327 4 * const_offset
->u32
[0]), src
.type
);
4328 for (unsigned j
= 0; j
< num_components
; j
++) {
4329 bld
.MOV(offset(new_dest
, bld
, j
+ first_component
),
4330 offset(src
, bld
, j
));
4335 case nir_intrinsic_ssbo_atomic_add
:
4336 nir_emit_ssbo_atomic(bld
, BRW_AOP_ADD
, instr
);
4338 case nir_intrinsic_ssbo_atomic_imin
:
4339 nir_emit_ssbo_atomic(bld
, BRW_AOP_IMIN
, instr
);
4341 case nir_intrinsic_ssbo_atomic_umin
:
4342 nir_emit_ssbo_atomic(bld
, BRW_AOP_UMIN
, instr
);
4344 case nir_intrinsic_ssbo_atomic_imax
:
4345 nir_emit_ssbo_atomic(bld
, BRW_AOP_IMAX
, instr
);
4347 case nir_intrinsic_ssbo_atomic_umax
:
4348 nir_emit_ssbo_atomic(bld
, BRW_AOP_UMAX
, instr
);
4350 case nir_intrinsic_ssbo_atomic_and
:
4351 nir_emit_ssbo_atomic(bld
, BRW_AOP_AND
, instr
);
4353 case nir_intrinsic_ssbo_atomic_or
:
4354 nir_emit_ssbo_atomic(bld
, BRW_AOP_OR
, instr
);
4356 case nir_intrinsic_ssbo_atomic_xor
:
4357 nir_emit_ssbo_atomic(bld
, BRW_AOP_XOR
, instr
);
4359 case nir_intrinsic_ssbo_atomic_exchange
:
4360 nir_emit_ssbo_atomic(bld
, BRW_AOP_MOV
, instr
);
4362 case nir_intrinsic_ssbo_atomic_comp_swap
:
4363 nir_emit_ssbo_atomic(bld
, BRW_AOP_CMPWR
, instr
);
4366 case nir_intrinsic_get_buffer_size
: {
4367 nir_const_value
*const_uniform_block
= nir_src_as_const_value(instr
->src
[0]);
4368 unsigned ssbo_index
= const_uniform_block
? const_uniform_block
->u32
[0] : 0;
4370 /* A resinfo's sampler message is used to get the buffer size. The
4371 * SIMD8's writeback message consists of four registers and SIMD16's
4372 * writeback message consists of 8 destination registers (two per each
4373 * component). Because we are only interested on the first channel of
4374 * the first returned component, where resinfo returns the buffer size
4375 * for SURFTYPE_BUFFER, we can just use the SIMD8 variant regardless of
4376 * the dispatch width.
4378 const fs_builder ubld
= bld
.exec_all().group(8, 0);
4379 fs_reg src_payload
= ubld
.vgrf(BRW_REGISTER_TYPE_UD
);
4380 fs_reg ret_payload
= ubld
.vgrf(BRW_REGISTER_TYPE_UD
, 4);
4383 ubld
.MOV(src_payload
, brw_imm_d(0));
4385 const unsigned index
= prog_data
->binding_table
.ssbo_start
+ ssbo_index
;
4386 fs_inst
*inst
= ubld
.emit(SHADER_OPCODE_GET_BUFFER_SIZE
, ret_payload
,
4387 src_payload
, brw_imm_ud(index
));
4388 inst
->header_size
= 0;
4390 inst
->size_written
= 4 * REG_SIZE
;
4392 /* SKL PRM, vol07, 3D Media GPGPU Engine, Bounds Checking and Faulting:
4394 * "Out-of-bounds checking is always performed at a DWord granularity. If
4395 * any part of the DWord is out-of-bounds then the whole DWord is
4396 * considered out-of-bounds."
4398 * This implies that types with size smaller than 4-bytes need to be
4399 * padded if they don't complete the last dword of the buffer. But as we
4400 * need to maintain the original size we need to reverse the padding
4401 * calculation to return the correct size to know the number of elements
4402 * of an unsized array. As we stored in the last two bits of the surface
4403 * size the needed padding for the buffer, we calculate here the
4404 * original buffer_size reversing the surface_size calculation:
4406 * surface_size = isl_align(buffer_size, 4) +
4407 * (isl_align(buffer_size) - buffer_size)
4409 * buffer_size = surface_size & ~3 - surface_size & 3
4412 fs_reg size_aligned4
= ubld
.vgrf(BRW_REGISTER_TYPE_UD
);
4413 fs_reg size_padding
= ubld
.vgrf(BRW_REGISTER_TYPE_UD
);
4414 fs_reg buffer_size
= ubld
.vgrf(BRW_REGISTER_TYPE_UD
);
4416 ubld
.AND(size_padding
, ret_payload
, brw_imm_ud(3));
4417 ubld
.AND(size_aligned4
, ret_payload
, brw_imm_ud(~3));
4418 ubld
.ADD(buffer_size
, size_aligned4
, negate(size_padding
));
4420 bld
.MOV(retype(dest
, ret_payload
.type
), component(buffer_size
, 0));
4422 brw_mark_surface_used(prog_data
, index
);
4426 case nir_intrinsic_load_subgroup_invocation
:
4427 bld
.MOV(retype(dest
, BRW_REGISTER_TYPE_D
),
4428 nir_system_values
[SYSTEM_VALUE_SUBGROUP_INVOCATION
]);
4431 case nir_intrinsic_load_subgroup_eq_mask
:
4432 case nir_intrinsic_load_subgroup_ge_mask
:
4433 case nir_intrinsic_load_subgroup_gt_mask
:
4434 case nir_intrinsic_load_subgroup_le_mask
:
4435 case nir_intrinsic_load_subgroup_lt_mask
:
4436 unreachable("not reached");
4438 case nir_intrinsic_vote_any
: {
4439 const fs_builder ubld
= bld
.exec_all().group(1, 0);
4441 /* The any/all predicates do not consider channel enables. To prevent
4442 * dead channels from affecting the result, we initialize the flag with
4443 * with the identity value for the logical operation.
4445 if (dispatch_width
== 32) {
4446 /* For SIMD32, we use a UD type so we fill both f0.0 and f0.1. */
4447 ubld
.MOV(retype(brw_flag_reg(0, 0), BRW_REGISTER_TYPE_UD
),
4450 ubld
.MOV(brw_flag_reg(0, 0), brw_imm_uw(0));
4452 bld
.CMP(bld
.null_reg_d(), get_nir_src(instr
->src
[0]), brw_imm_d(0), BRW_CONDITIONAL_NZ
);
4454 /* For some reason, the any/all predicates don't work properly with
4455 * SIMD32. In particular, it appears that a SEL with a QtrCtrl of 2H
4456 * doesn't read the correct subset of the flag register and you end up
4457 * getting garbage in the second half. Work around this by using a pair
4458 * of 1-wide MOVs and scattering the result.
4460 fs_reg res1
= ubld
.vgrf(BRW_REGISTER_TYPE_D
);
4461 ubld
.MOV(res1
, brw_imm_d(0));
4462 set_predicate(dispatch_width
== 8 ? BRW_PREDICATE_ALIGN1_ANY8H
:
4463 dispatch_width
== 16 ? BRW_PREDICATE_ALIGN1_ANY16H
:
4464 BRW_PREDICATE_ALIGN1_ANY32H
,
4465 ubld
.MOV(res1
, brw_imm_d(-1)));
4467 bld
.MOV(retype(dest
, BRW_REGISTER_TYPE_D
), component(res1
, 0));
4470 case nir_intrinsic_vote_all
: {
4471 const fs_builder ubld
= bld
.exec_all().group(1, 0);
4473 /* The any/all predicates do not consider channel enables. To prevent
4474 * dead channels from affecting the result, we initialize the flag with
4475 * with the identity value for the logical operation.
4477 if (dispatch_width
== 32) {
4478 /* For SIMD32, we use a UD type so we fill both f0.0 and f0.1. */
4479 ubld
.MOV(retype(brw_flag_reg(0, 0), BRW_REGISTER_TYPE_UD
),
4480 brw_imm_ud(0xffffffff));
4482 ubld
.MOV(brw_flag_reg(0, 0), brw_imm_uw(0xffff));
4484 bld
.CMP(bld
.null_reg_d(), get_nir_src(instr
->src
[0]), brw_imm_d(0), BRW_CONDITIONAL_NZ
);
4486 /* For some reason, the any/all predicates don't work properly with
4487 * SIMD32. In particular, it appears that a SEL with a QtrCtrl of 2H
4488 * doesn't read the correct subset of the flag register and you end up
4489 * getting garbage in the second half. Work around this by using a pair
4490 * of 1-wide MOVs and scattering the result.
4492 fs_reg res1
= ubld
.vgrf(BRW_REGISTER_TYPE_D
);
4493 ubld
.MOV(res1
, brw_imm_d(0));
4494 set_predicate(dispatch_width
== 8 ? BRW_PREDICATE_ALIGN1_ALL8H
:
4495 dispatch_width
== 16 ? BRW_PREDICATE_ALIGN1_ALL16H
:
4496 BRW_PREDICATE_ALIGN1_ALL32H
,
4497 ubld
.MOV(res1
, brw_imm_d(-1)));
4499 bld
.MOV(retype(dest
, BRW_REGISTER_TYPE_D
), component(res1
, 0));
4502 case nir_intrinsic_vote_feq
:
4503 case nir_intrinsic_vote_ieq
: {
4504 fs_reg value
= get_nir_src(instr
->src
[0]);
4505 if (instr
->intrinsic
== nir_intrinsic_vote_feq
) {
4506 const unsigned bit_size
= nir_src_bit_size(instr
->src
[0]);
4507 value
.type
= brw_reg_type_from_bit_size(bit_size
, BRW_REGISTER_TYPE_F
);
4510 fs_reg uniformized
= bld
.emit_uniformize(value
);
4511 const fs_builder ubld
= bld
.exec_all().group(1, 0);
4513 /* The any/all predicates do not consider channel enables. To prevent
4514 * dead channels from affecting the result, we initialize the flag with
4515 * with the identity value for the logical operation.
4517 if (dispatch_width
== 32) {
4518 /* For SIMD32, we use a UD type so we fill both f0.0 and f0.1. */
4519 ubld
.MOV(retype(brw_flag_reg(0, 0), BRW_REGISTER_TYPE_UD
),
4520 brw_imm_ud(0xffffffff));
4522 ubld
.MOV(brw_flag_reg(0, 0), brw_imm_uw(0xffff));
4524 bld
.CMP(bld
.null_reg_d(), value
, uniformized
, BRW_CONDITIONAL_Z
);
4526 /* For some reason, the any/all predicates don't work properly with
4527 * SIMD32. In particular, it appears that a SEL with a QtrCtrl of 2H
4528 * doesn't read the correct subset of the flag register and you end up
4529 * getting garbage in the second half. Work around this by using a pair
4530 * of 1-wide MOVs and scattering the result.
4532 fs_reg res1
= ubld
.vgrf(BRW_REGISTER_TYPE_D
);
4533 ubld
.MOV(res1
, brw_imm_d(0));
4534 set_predicate(dispatch_width
== 8 ? BRW_PREDICATE_ALIGN1_ALL8H
:
4535 dispatch_width
== 16 ? BRW_PREDICATE_ALIGN1_ALL16H
:
4536 BRW_PREDICATE_ALIGN1_ALL32H
,
4537 ubld
.MOV(res1
, brw_imm_d(-1)));
4539 bld
.MOV(retype(dest
, BRW_REGISTER_TYPE_D
), component(res1
, 0));
4543 case nir_intrinsic_ballot
: {
4544 const fs_reg value
= retype(get_nir_src(instr
->src
[0]),
4545 BRW_REGISTER_TYPE_UD
);
4546 struct brw_reg flag
= brw_flag_reg(0, 0);
4547 /* FIXME: For SIMD32 programs, this causes us to stomp on f0.1 as well
4548 * as f0.0. This is a problem for fragment programs as we currently use
4549 * f0.1 for discards. Fortunately, we don't support SIMD32 fragment
4550 * programs yet so this isn't a problem. When we do, something will
4553 if (dispatch_width
== 32)
4554 flag
.type
= BRW_REGISTER_TYPE_UD
;
4556 bld
.exec_all().group(1, 0).MOV(flag
, brw_imm_ud(0u));
4557 bld
.CMP(bld
.null_reg_ud(), value
, brw_imm_ud(0u), BRW_CONDITIONAL_NZ
);
4559 if (instr
->dest
.ssa
.bit_size
> 32) {
4560 dest
.type
= BRW_REGISTER_TYPE_UQ
;
4562 dest
.type
= BRW_REGISTER_TYPE_UD
;
4564 bld
.MOV(dest
, flag
);
4568 case nir_intrinsic_read_invocation
: {
4569 const fs_reg value
= get_nir_src(instr
->src
[0]);
4570 const fs_reg invocation
= get_nir_src(instr
->src
[1]);
4571 fs_reg tmp
= bld
.vgrf(value
.type
);
4573 bld
.exec_all().emit(SHADER_OPCODE_BROADCAST
, tmp
, value
,
4574 bld
.emit_uniformize(invocation
));
4576 bld
.MOV(retype(dest
, value
.type
), fs_reg(component(tmp
, 0)));
4580 case nir_intrinsic_read_first_invocation
: {
4581 const fs_reg value
= get_nir_src(instr
->src
[0]);
4582 bld
.MOV(retype(dest
, value
.type
), bld
.emit_uniformize(value
));
4586 case nir_intrinsic_shuffle
: {
4587 const fs_reg value
= get_nir_src(instr
->src
[0]);
4588 const fs_reg index
= get_nir_src(instr
->src
[1]);
4590 bld
.emit(SHADER_OPCODE_SHUFFLE
, retype(dest
, value
.type
), value
, index
);
4594 case nir_intrinsic_first_invocation
: {
4595 fs_reg tmp
= bld
.vgrf(BRW_REGISTER_TYPE_UD
);
4596 bld
.exec_all().emit(SHADER_OPCODE_FIND_LIVE_CHANNEL
, tmp
);
4597 bld
.MOV(retype(dest
, BRW_REGISTER_TYPE_UD
),
4598 fs_reg(component(tmp
, 0)));
4602 case nir_intrinsic_quad_broadcast
: {
4603 const fs_reg value
= get_nir_src(instr
->src
[0]);
4604 nir_const_value
*index
= nir_src_as_const_value(instr
->src
[1]);
4605 assert(nir_src_bit_size(instr
->src
[1]) == 32);
4607 bld
.emit(SHADER_OPCODE_CLUSTER_BROADCAST
, retype(dest
, value
.type
),
4608 value
, brw_imm_ud(index
->u32
[0]), brw_imm_ud(4));
4612 case nir_intrinsic_quad_swap_horizontal
: {
4613 const fs_reg value
= get_nir_src(instr
->src
[0]);
4614 const fs_reg tmp
= bld
.vgrf(value
.type
);
4615 const fs_builder ubld
= bld
.exec_all().group(dispatch_width
/ 2, 0);
4617 const fs_reg src_left
= horiz_stride(value
, 2);
4618 const fs_reg src_right
= horiz_stride(horiz_offset(value
, 1), 2);
4619 const fs_reg tmp_left
= horiz_stride(tmp
, 2);
4620 const fs_reg tmp_right
= horiz_stride(horiz_offset(tmp
, 1), 2);
4622 /* From the Cherryview PRM Vol. 7, "Register Region Restrictiosn":
4624 * "When source or destination datatype is 64b or operation is
4625 * integer DWord multiply, regioning in Align1 must follow
4630 * 3. Source and Destination offset must be the same, except
4631 * the case of scalar source."
4633 * In order to work around this, we have to emit two 32-bit MOVs instead
4634 * of a single 64-bit MOV to do the shuffle.
4636 if (type_sz(value
.type
) > 4 &&
4637 (devinfo
->is_cherryview
|| gen_device_info_is_9lp(devinfo
))) {
4638 ubld
.MOV(subscript(tmp_left
, BRW_REGISTER_TYPE_D
, 0),
4639 subscript(src_right
, BRW_REGISTER_TYPE_D
, 0));
4640 ubld
.MOV(subscript(tmp_left
, BRW_REGISTER_TYPE_D
, 1),
4641 subscript(src_right
, BRW_REGISTER_TYPE_D
, 1));
4642 ubld
.MOV(subscript(tmp_right
, BRW_REGISTER_TYPE_D
, 0),
4643 subscript(src_left
, BRW_REGISTER_TYPE_D
, 0));
4644 ubld
.MOV(subscript(tmp_right
, BRW_REGISTER_TYPE_D
, 1),
4645 subscript(src_left
, BRW_REGISTER_TYPE_D
, 1));
4647 ubld
.MOV(tmp_left
, src_right
);
4648 ubld
.MOV(tmp_right
, src_left
);
4650 bld
.MOV(retype(dest
, value
.type
), tmp
);
4654 case nir_intrinsic_quad_swap_vertical
: {
4655 const fs_reg value
= get_nir_src(instr
->src
[0]);
4656 if (nir_src_bit_size(instr
->src
[0]) == 32) {
4657 /* For 32-bit, we can use a SIMD4x2 instruction to do this easily */
4658 const fs_reg tmp
= bld
.vgrf(value
.type
);
4659 const fs_builder ubld
= bld
.exec_all();
4660 ubld
.emit(SHADER_OPCODE_QUAD_SWIZZLE
, tmp
, value
,
4661 brw_imm_ud(BRW_SWIZZLE4(2,3,0,1)));
4662 bld
.MOV(retype(dest
, value
.type
), tmp
);
4664 /* For larger data types, we have to either emit dispatch_width many
4665 * MOVs or else fall back to doing indirects.
4667 fs_reg idx
= bld
.vgrf(BRW_REGISTER_TYPE_W
);
4668 bld
.XOR(idx
, nir_system_values
[SYSTEM_VALUE_SUBGROUP_INVOCATION
],
4670 bld
.emit(SHADER_OPCODE_SHUFFLE
, retype(dest
, value
.type
), value
, idx
);
4675 case nir_intrinsic_quad_swap_diagonal
: {
4676 const fs_reg value
= get_nir_src(instr
->src
[0]);
4677 if (nir_src_bit_size(instr
->src
[0]) == 32) {
4678 /* For 32-bit, we can use a SIMD4x2 instruction to do this easily */
4679 const fs_reg tmp
= bld
.vgrf(value
.type
);
4680 const fs_builder ubld
= bld
.exec_all();
4681 ubld
.emit(SHADER_OPCODE_QUAD_SWIZZLE
, tmp
, value
,
4682 brw_imm_ud(BRW_SWIZZLE4(3,2,1,0)));
4683 bld
.MOV(retype(dest
, value
.type
), tmp
);
4685 /* For larger data types, we have to either emit dispatch_width many
4686 * MOVs or else fall back to doing indirects.
4688 fs_reg idx
= bld
.vgrf(BRW_REGISTER_TYPE_W
);
4689 bld
.XOR(idx
, nir_system_values
[SYSTEM_VALUE_SUBGROUP_INVOCATION
],
4691 bld
.emit(SHADER_OPCODE_SHUFFLE
, retype(dest
, value
.type
), value
, idx
);
4696 case nir_intrinsic_reduce
: {
4697 fs_reg src
= get_nir_src(instr
->src
[0]);
4698 nir_op redop
= (nir_op
)nir_intrinsic_reduction_op(instr
);
4699 unsigned cluster_size
= nir_intrinsic_cluster_size(instr
);
4700 if (cluster_size
== 0 || cluster_size
> dispatch_width
)
4701 cluster_size
= dispatch_width
;
4703 /* Figure out the source type */
4704 src
.type
= brw_type_for_nir_type(devinfo
,
4705 (nir_alu_type
)(nir_op_infos
[redop
].input_types
[0] |
4706 nir_src_bit_size(instr
->src
[0])));
4708 fs_reg identity
= brw_nir_reduction_op_identity(bld
, redop
, src
.type
);
4709 opcode brw_op
= brw_op_for_nir_reduction_op(redop
);
4710 brw_conditional_mod cond_mod
= brw_cond_mod_for_nir_reduction_op(redop
);
4712 /* Set up a register for all of our scratching around and initialize it
4713 * to reduction operation's identity value.
4715 fs_reg scan
= bld
.vgrf(src
.type
);
4716 bld
.exec_all().emit(SHADER_OPCODE_SEL_EXEC
, scan
, src
, identity
);
4718 bld
.emit_scan(brw_op
, scan
, cluster_size
, cond_mod
);
4720 dest
.type
= src
.type
;
4721 if (cluster_size
* type_sz(src
.type
) >= REG_SIZE
* 2) {
4722 /* In this case, CLUSTER_BROADCAST instruction isn't needed because
4723 * the distance between clusters is at least 2 GRFs. In this case,
4724 * we don't need the weird striding of the CLUSTER_BROADCAST
4725 * instruction and can just do regular MOVs.
4727 assert((cluster_size
* type_sz(src
.type
)) % (REG_SIZE
* 2) == 0);
4728 const unsigned groups
=
4729 (dispatch_width
* type_sz(src
.type
)) / (REG_SIZE
* 2);
4730 const unsigned group_size
= dispatch_width
/ groups
;
4731 for (unsigned i
= 0; i
< groups
; i
++) {
4732 const unsigned cluster
= (i
* group_size
) / cluster_size
;
4733 const unsigned comp
= cluster
* cluster_size
+ (cluster_size
- 1);
4734 bld
.group(group_size
, i
).MOV(horiz_offset(dest
, i
* group_size
),
4735 component(scan
, comp
));
4738 bld
.emit(SHADER_OPCODE_CLUSTER_BROADCAST
, dest
, scan
,
4739 brw_imm_ud(cluster_size
- 1), brw_imm_ud(cluster_size
));
4744 case nir_intrinsic_inclusive_scan
:
4745 case nir_intrinsic_exclusive_scan
: {
4746 fs_reg src
= get_nir_src(instr
->src
[0]);
4747 nir_op redop
= (nir_op
)nir_intrinsic_reduction_op(instr
);
4749 /* Figure out the source type */
4750 src
.type
= brw_type_for_nir_type(devinfo
,
4751 (nir_alu_type
)(nir_op_infos
[redop
].input_types
[0] |
4752 nir_src_bit_size(instr
->src
[0])));
4754 fs_reg identity
= brw_nir_reduction_op_identity(bld
, redop
, src
.type
);
4755 opcode brw_op
= brw_op_for_nir_reduction_op(redop
);
4756 brw_conditional_mod cond_mod
= brw_cond_mod_for_nir_reduction_op(redop
);
4758 /* Set up a register for all of our scratching around and initialize it
4759 * to reduction operation's identity value.
4761 fs_reg scan
= bld
.vgrf(src
.type
);
4762 const fs_builder allbld
= bld
.exec_all();
4763 allbld
.emit(SHADER_OPCODE_SEL_EXEC
, scan
, src
, identity
);
4765 if (instr
->intrinsic
== nir_intrinsic_exclusive_scan
) {
4766 /* Exclusive scan is a bit harder because we have to do an annoying
4767 * shift of the contents before we can begin. To make things worse,
4768 * we can't do this with a normal stride; we have to use indirects.
4770 fs_reg shifted
= bld
.vgrf(src
.type
);
4771 fs_reg idx
= bld
.vgrf(BRW_REGISTER_TYPE_W
);
4772 allbld
.ADD(idx
, nir_system_values
[SYSTEM_VALUE_SUBGROUP_INVOCATION
],
4774 allbld
.emit(SHADER_OPCODE_SHUFFLE
, shifted
, scan
, idx
);
4775 allbld
.group(1, 0).MOV(component(shifted
, 0), identity
);
4779 bld
.emit_scan(brw_op
, scan
, dispatch_width
, cond_mod
);
4781 bld
.MOV(retype(dest
, src
.type
), scan
);
4786 unreachable("unknown intrinsic");
4791 fs_visitor::nir_emit_ssbo_atomic(const fs_builder
&bld
,
4792 int op
, nir_intrinsic_instr
*instr
)
4794 if (stage
== MESA_SHADER_FRAGMENT
)
4795 brw_wm_prog_data(prog_data
)->has_side_effects
= true;
4798 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
4799 dest
= get_nir_dest(instr
->dest
);
4802 nir_const_value
*const_surface
= nir_src_as_const_value(instr
->src
[0]);
4803 if (const_surface
) {
4804 unsigned surf_index
= stage_prog_data
->binding_table
.ssbo_start
+
4805 const_surface
->u32
[0];
4806 surface
= brw_imm_ud(surf_index
);
4807 brw_mark_surface_used(prog_data
, surf_index
);
4809 surface
= vgrf(glsl_type::uint_type
);
4810 bld
.ADD(surface
, get_nir_src(instr
->src
[0]),
4811 brw_imm_ud(stage_prog_data
->binding_table
.ssbo_start
));
4813 /* Assume this may touch any SSBO. This is the same we do for other
4814 * UBO/SSBO accesses with non-constant surface.
4816 brw_mark_surface_used(prog_data
,
4817 stage_prog_data
->binding_table
.ssbo_start
+
4818 nir
->info
.num_ssbos
- 1);
4821 fs_reg offset
= get_nir_src(instr
->src
[1]);
4822 fs_reg data1
= get_nir_src(instr
->src
[2]);
4824 if (op
== BRW_AOP_CMPWR
)
4825 data2
= get_nir_src(instr
->src
[3]);
4827 /* Emit the actual atomic operation */
4829 fs_reg atomic_result
= emit_untyped_atomic(bld
, surface
, offset
,
4831 1 /* dims */, 1 /* rsize */,
4833 BRW_PREDICATE_NONE
);
4834 dest
.type
= atomic_result
.type
;
4835 bld
.MOV(dest
, atomic_result
);
4839 fs_visitor::nir_emit_shared_atomic(const fs_builder
&bld
,
4840 int op
, nir_intrinsic_instr
*instr
)
4843 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
4844 dest
= get_nir_dest(instr
->dest
);
4846 fs_reg surface
= brw_imm_ud(GEN7_BTI_SLM
);
4848 fs_reg data1
= get_nir_src(instr
->src
[1]);
4850 if (op
== BRW_AOP_CMPWR
)
4851 data2
= get_nir_src(instr
->src
[2]);
4853 /* Get the offset */
4854 nir_const_value
*const_offset
= nir_src_as_const_value(instr
->src
[0]);
4856 offset
= brw_imm_ud(instr
->const_index
[0] + const_offset
->u32
[0]);
4858 offset
= vgrf(glsl_type::uint_type
);
4860 retype(get_nir_src(instr
->src
[0]), BRW_REGISTER_TYPE_UD
),
4861 brw_imm_ud(instr
->const_index
[0]));
4864 /* Emit the actual atomic operation operation */
4866 fs_reg atomic_result
= emit_untyped_atomic(bld
, surface
, offset
,
4868 1 /* dims */, 1 /* rsize */,
4870 BRW_PREDICATE_NONE
);
4871 dest
.type
= atomic_result
.type
;
4872 bld
.MOV(dest
, atomic_result
);
4876 fs_visitor::nir_emit_texture(const fs_builder
&bld
, nir_tex_instr
*instr
)
4878 unsigned texture
= instr
->texture_index
;
4879 unsigned sampler
= instr
->sampler_index
;
4881 fs_reg srcs
[TEX_LOGICAL_NUM_SRCS
];
4883 srcs
[TEX_LOGICAL_SRC_SURFACE
] = brw_imm_ud(texture
);
4884 srcs
[TEX_LOGICAL_SRC_SAMPLER
] = brw_imm_ud(sampler
);
4886 int lod_components
= 0;
4888 /* The hardware requires a LOD for buffer textures */
4889 if (instr
->sampler_dim
== GLSL_SAMPLER_DIM_BUF
)
4890 srcs
[TEX_LOGICAL_SRC_LOD
] = brw_imm_d(0);
4892 uint32_t header_bits
= 0;
4893 for (unsigned i
= 0; i
< instr
->num_srcs
; i
++) {
4894 fs_reg src
= get_nir_src(instr
->src
[i
].src
);
4895 switch (instr
->src
[i
].src_type
) {
4896 case nir_tex_src_bias
:
4897 srcs
[TEX_LOGICAL_SRC_LOD
] =
4898 retype(get_nir_src_imm(instr
->src
[i
].src
), BRW_REGISTER_TYPE_F
);
4900 case nir_tex_src_comparator
:
4901 srcs
[TEX_LOGICAL_SRC_SHADOW_C
] = retype(src
, BRW_REGISTER_TYPE_F
);
4903 case nir_tex_src_coord
:
4904 switch (instr
->op
) {
4906 case nir_texop_txf_ms
:
4907 case nir_texop_txf_ms_mcs
:
4908 case nir_texop_samples_identical
:
4909 srcs
[TEX_LOGICAL_SRC_COORDINATE
] = retype(src
, BRW_REGISTER_TYPE_D
);
4912 srcs
[TEX_LOGICAL_SRC_COORDINATE
] = retype(src
, BRW_REGISTER_TYPE_F
);
4916 case nir_tex_src_ddx
:
4917 srcs
[TEX_LOGICAL_SRC_LOD
] = retype(src
, BRW_REGISTER_TYPE_F
);
4918 lod_components
= nir_tex_instr_src_size(instr
, i
);
4920 case nir_tex_src_ddy
:
4921 srcs
[TEX_LOGICAL_SRC_LOD2
] = retype(src
, BRW_REGISTER_TYPE_F
);
4923 case nir_tex_src_lod
:
4924 switch (instr
->op
) {
4926 srcs
[TEX_LOGICAL_SRC_LOD
] =
4927 retype(get_nir_src_imm(instr
->src
[i
].src
), BRW_REGISTER_TYPE_UD
);
4930 srcs
[TEX_LOGICAL_SRC_LOD
] =
4931 retype(get_nir_src_imm(instr
->src
[i
].src
), BRW_REGISTER_TYPE_D
);
4934 srcs
[TEX_LOGICAL_SRC_LOD
] =
4935 retype(get_nir_src_imm(instr
->src
[i
].src
), BRW_REGISTER_TYPE_F
);
4939 case nir_tex_src_ms_index
:
4940 srcs
[TEX_LOGICAL_SRC_SAMPLE_INDEX
] = retype(src
, BRW_REGISTER_TYPE_UD
);
4943 case nir_tex_src_offset
: {
4944 nir_const_value
*const_offset
=
4945 nir_src_as_const_value(instr
->src
[i
].src
);
4946 unsigned offset_bits
= 0;
4948 brw_texture_offset(const_offset
->i32
,
4949 nir_tex_instr_src_size(instr
, i
),
4951 header_bits
|= offset_bits
;
4953 srcs
[TEX_LOGICAL_SRC_TG4_OFFSET
] =
4954 retype(src
, BRW_REGISTER_TYPE_D
);
4959 case nir_tex_src_projector
:
4960 unreachable("should be lowered");
4962 case nir_tex_src_texture_offset
: {
4963 /* Figure out the highest possible texture index and mark it as used */
4964 uint32_t max_used
= texture
+ instr
->texture_array_size
- 1;
4965 if (instr
->op
== nir_texop_tg4
&& devinfo
->gen
< 8) {
4966 max_used
+= stage_prog_data
->binding_table
.gather_texture_start
;
4968 max_used
+= stage_prog_data
->binding_table
.texture_start
;
4970 brw_mark_surface_used(prog_data
, max_used
);
4972 /* Emit code to evaluate the actual indexing expression */
4973 fs_reg tmp
= vgrf(glsl_type::uint_type
);
4974 bld
.ADD(tmp
, src
, brw_imm_ud(texture
));
4975 srcs
[TEX_LOGICAL_SRC_SURFACE
] = bld
.emit_uniformize(tmp
);
4979 case nir_tex_src_sampler_offset
: {
4980 /* Emit code to evaluate the actual indexing expression */
4981 fs_reg tmp
= vgrf(glsl_type::uint_type
);
4982 bld
.ADD(tmp
, src
, brw_imm_ud(sampler
));
4983 srcs
[TEX_LOGICAL_SRC_SAMPLER
] = bld
.emit_uniformize(tmp
);
4987 case nir_tex_src_ms_mcs
:
4988 assert(instr
->op
== nir_texop_txf_ms
);
4989 srcs
[TEX_LOGICAL_SRC_MCS
] = retype(src
, BRW_REGISTER_TYPE_D
);
4992 case nir_tex_src_plane
: {
4993 nir_const_value
*const_plane
=
4994 nir_src_as_const_value(instr
->src
[i
].src
);
4995 const uint32_t plane
= const_plane
->u32
[0];
4996 const uint32_t texture_index
=
4997 instr
->texture_index
+
4998 stage_prog_data
->binding_table
.plane_start
[plane
] -
4999 stage_prog_data
->binding_table
.texture_start
;
5001 srcs
[TEX_LOGICAL_SRC_SURFACE
] = brw_imm_ud(texture_index
);
5006 unreachable("unknown texture source");
5010 if (srcs
[TEX_LOGICAL_SRC_MCS
].file
== BAD_FILE
&&
5011 (instr
->op
== nir_texop_txf_ms
||
5012 instr
->op
== nir_texop_samples_identical
)) {
5013 if (devinfo
->gen
>= 7 &&
5014 key_tex
->compressed_multisample_layout_mask
& (1 << texture
)) {
5015 srcs
[TEX_LOGICAL_SRC_MCS
] =
5016 emit_mcs_fetch(srcs
[TEX_LOGICAL_SRC_COORDINATE
],
5017 instr
->coord_components
,
5018 srcs
[TEX_LOGICAL_SRC_SURFACE
]);
5020 srcs
[TEX_LOGICAL_SRC_MCS
] = brw_imm_ud(0u);
5024 srcs
[TEX_LOGICAL_SRC_COORD_COMPONENTS
] = brw_imm_d(instr
->coord_components
);
5025 srcs
[TEX_LOGICAL_SRC_GRAD_COMPONENTS
] = brw_imm_d(lod_components
);
5028 switch (instr
->op
) {
5030 opcode
= (stage
== MESA_SHADER_FRAGMENT
? SHADER_OPCODE_TEX_LOGICAL
:
5031 SHADER_OPCODE_TXL_LOGICAL
);
5034 opcode
= FS_OPCODE_TXB_LOGICAL
;
5037 opcode
= SHADER_OPCODE_TXL_LOGICAL
;
5040 opcode
= SHADER_OPCODE_TXD_LOGICAL
;
5043 opcode
= SHADER_OPCODE_TXF_LOGICAL
;
5045 case nir_texop_txf_ms
:
5046 if ((key_tex
->msaa_16
& (1 << sampler
)))
5047 opcode
= SHADER_OPCODE_TXF_CMS_W_LOGICAL
;
5049 opcode
= SHADER_OPCODE_TXF_CMS_LOGICAL
;
5051 case nir_texop_txf_ms_mcs
:
5052 opcode
= SHADER_OPCODE_TXF_MCS_LOGICAL
;
5054 case nir_texop_query_levels
:
5056 opcode
= SHADER_OPCODE_TXS_LOGICAL
;
5059 opcode
= SHADER_OPCODE_LOD_LOGICAL
;
5062 if (srcs
[TEX_LOGICAL_SRC_TG4_OFFSET
].file
!= BAD_FILE
)
5063 opcode
= SHADER_OPCODE_TG4_OFFSET_LOGICAL
;
5065 opcode
= SHADER_OPCODE_TG4_LOGICAL
;
5067 case nir_texop_texture_samples
:
5068 opcode
= SHADER_OPCODE_SAMPLEINFO_LOGICAL
;
5070 case nir_texop_samples_identical
: {
5071 fs_reg dst
= retype(get_nir_dest(instr
->dest
), BRW_REGISTER_TYPE_D
);
5073 /* If mcs is an immediate value, it means there is no MCS. In that case
5074 * just return false.
5076 if (srcs
[TEX_LOGICAL_SRC_MCS
].file
== BRW_IMMEDIATE_VALUE
) {
5077 bld
.MOV(dst
, brw_imm_ud(0u));
5078 } else if ((key_tex
->msaa_16
& (1 << sampler
))) {
5079 fs_reg tmp
= vgrf(glsl_type::uint_type
);
5080 bld
.OR(tmp
, srcs
[TEX_LOGICAL_SRC_MCS
],
5081 offset(srcs
[TEX_LOGICAL_SRC_MCS
], bld
, 1));
5082 bld
.CMP(dst
, tmp
, brw_imm_ud(0u), BRW_CONDITIONAL_EQ
);
5084 bld
.CMP(dst
, srcs
[TEX_LOGICAL_SRC_MCS
], brw_imm_ud(0u),
5085 BRW_CONDITIONAL_EQ
);
5090 unreachable("unknown texture opcode");
5093 if (instr
->op
== nir_texop_tg4
) {
5094 if (instr
->component
== 1 &&
5095 key_tex
->gather_channel_quirk_mask
& (1 << texture
)) {
5096 /* gather4 sampler is broken for green channel on RG32F --
5097 * we must ask for blue instead.
5099 header_bits
|= 2 << 16;
5101 header_bits
|= instr
->component
<< 16;
5105 fs_reg dst
= bld
.vgrf(brw_type_for_nir_type(devinfo
, instr
->dest_type
), 4);
5106 fs_inst
*inst
= bld
.emit(opcode
, dst
, srcs
, ARRAY_SIZE(srcs
));
5107 inst
->offset
= header_bits
;
5109 const unsigned dest_size
= nir_tex_instr_dest_size(instr
);
5110 if (devinfo
->gen
>= 9 &&
5111 instr
->op
!= nir_texop_tg4
&& instr
->op
!= nir_texop_query_levels
) {
5112 unsigned write_mask
= instr
->dest
.is_ssa
?
5113 nir_ssa_def_components_read(&instr
->dest
.ssa
):
5114 (1 << dest_size
) - 1;
5115 assert(write_mask
!= 0); /* dead code should have been eliminated */
5116 inst
->size_written
= util_last_bit(write_mask
) *
5117 inst
->dst
.component_size(inst
->exec_size
);
5119 inst
->size_written
= 4 * inst
->dst
.component_size(inst
->exec_size
);
5122 if (srcs
[TEX_LOGICAL_SRC_SHADOW_C
].file
!= BAD_FILE
)
5123 inst
->shadow_compare
= true;
5125 if (instr
->op
== nir_texop_tg4
&& devinfo
->gen
== 6)
5126 emit_gen6_gather_wa(key_tex
->gen6_gather_wa
[texture
], dst
);
5129 for (unsigned i
= 0; i
< dest_size
; i
++)
5130 nir_dest
[i
] = offset(dst
, bld
, i
);
5132 if (instr
->op
== nir_texop_query_levels
) {
5133 /* # levels is in .w */
5134 nir_dest
[0] = offset(dst
, bld
, 3);
5135 } else if (instr
->op
== nir_texop_txs
&&
5136 dest_size
>= 3 && devinfo
->gen
< 7) {
5137 /* Gen4-6 return 0 instead of 1 for single layer surfaces. */
5138 fs_reg depth
= offset(dst
, bld
, 2);
5139 nir_dest
[2] = vgrf(glsl_type::int_type
);
5140 bld
.emit_minmax(nir_dest
[2], depth
, brw_imm_d(1), BRW_CONDITIONAL_GE
);
5143 bld
.LOAD_PAYLOAD(get_nir_dest(instr
->dest
), nir_dest
, dest_size
, 0);
5147 fs_visitor::nir_emit_jump(const fs_builder
&bld
, nir_jump_instr
*instr
)
5149 switch (instr
->type
) {
5150 case nir_jump_break
:
5151 bld
.emit(BRW_OPCODE_BREAK
);
5153 case nir_jump_continue
:
5154 bld
.emit(BRW_OPCODE_CONTINUE
);
5156 case nir_jump_return
:
5158 unreachable("unknown jump");
5163 * This helper takes the result of a load operation that reads 32-bit elements
5171 * and shuffles the data to get this:
5178 * Which is exactly what we want if the load is reading 64-bit components
5179 * like doubles, where x represents the low 32-bit of the x double component
5180 * and y represents the high 32-bit of the x double component (likewise with
5181 * z and w for double component y). The parameter @components represents
5182 * the number of 64-bit components present in @src. This would typically be
5183 * 2 at most, since we can only fit 2 double elements in the result of a
5186 * Notice that @dst and @src can be the same register.
5189 shuffle_32bit_load_result_to_64bit_data(const fs_builder
&bld
,
5192 uint32_t components
)
5194 assert(type_sz(src
.type
) == 4);
5195 assert(type_sz(dst
.type
) == 8);
5197 /* A temporary that we will use to shuffle the 32-bit data of each
5198 * component in the vector into valid 64-bit data. We can't write directly
5199 * to dst because dst can be (and would usually be) the same as src
5200 * and in that case the first MOV in the loop below would overwrite the
5201 * data read in the second MOV.
5203 fs_reg tmp
= bld
.vgrf(dst
.type
);
5205 for (unsigned i
= 0; i
< components
; i
++) {
5206 const fs_reg component_i
= offset(src
, bld
, 2 * i
);
5208 bld
.MOV(subscript(tmp
, src
.type
, 0), component_i
);
5209 bld
.MOV(subscript(tmp
, src
.type
, 1), offset(component_i
, bld
, 1));
5211 bld
.MOV(offset(dst
, bld
, i
), tmp
);
5216 shuffle_32bit_load_result_to_16bit_data(const fs_builder
&bld
,
5219 uint32_t first_component
,
5220 uint32_t components
)
5222 assert(type_sz(src
.type
) == 4);
5223 assert(type_sz(dst
.type
) == 2);
5225 /* A temporary is used to un-shuffle the 32-bit data of each component in
5226 * into a valid 16-bit vector. We can't write directly to dst because it
5227 * can be the same register as src and in that case the first MOV in the
5228 * loop below would overwrite the data read in the second MOV.
5230 fs_reg tmp
= retype(bld
.vgrf(src
.type
), dst
.type
);
5232 for (unsigned i
= 0; i
< components
; i
++) {
5233 const fs_reg component_i
=
5234 subscript(offset(src
, bld
, (first_component
+ i
) / 2), dst
.type
,
5235 (first_component
+ i
) % 2);
5237 bld
.MOV(offset(tmp
, bld
, i
% 2), component_i
);
5240 bld
.MOV(offset(dst
, bld
, i
-1), offset(tmp
, bld
, 0));
5241 bld
.MOV(offset(dst
, bld
, i
), offset(tmp
, bld
, 1));
5244 if (components
% 2) {
5245 bld
.MOV(offset(dst
, bld
, components
- 1), tmp
);
5250 * This helper does the inverse operation of
5251 * SHUFFLE_32BIT_LOAD_RESULT_TO_64BIT_DATA.
5253 * We need to do this when we are going to use untyped write messsages that
5254 * operate with 32-bit components in order to arrange our 64-bit data to be
5255 * in the expected layout.
5257 * Notice that callers of this function, unlike in the case of the inverse
5258 * operation, would typically need to call this with dst and src being
5259 * different registers, since they would otherwise corrupt the original
5260 * 64-bit data they are about to write. Because of this the function checks
5261 * that the src and dst regions involved in the operation do not overlap.
5264 shuffle_64bit_data_for_32bit_write(const fs_builder
&bld
,
5266 uint32_t components
)
5268 assert(type_sz(src
.type
) == 8);
5270 fs_reg dst
= bld
.vgrf(BRW_REGISTER_TYPE_D
, 2 * components
);
5272 for (unsigned i
= 0; i
< components
; i
++) {
5273 const fs_reg component_i
= offset(src
, bld
, i
);
5274 bld
.MOV(offset(dst
, bld
, 2 * i
), subscript(component_i
, dst
.type
, 0));
5275 bld
.MOV(offset(dst
, bld
, 2 * i
+ 1), subscript(component_i
, dst
.type
, 1));
5282 shuffle_16bit_data_for_32bit_write(const fs_builder
&bld
,
5285 uint32_t components
)
5287 assert(type_sz(src
.type
) == 2);
5288 assert(type_sz(dst
.type
) == 4);
5290 /* A temporary is used to shuffle the 16-bit data of each component in the
5291 * 32-bit data vector. We can't write directly to dst because it can be the
5292 * same register as src and in that case the first MOV in the loop below
5293 * would overwrite the data read in the second MOV.
5295 fs_reg tmp
= bld
.vgrf(dst
.type
);
5297 for (unsigned i
= 0; i
< components
; i
++) {
5298 const fs_reg component_i
= offset(src
, bld
, i
);
5299 bld
.MOV(subscript(tmp
, src
.type
, i
% 2), component_i
);
5301 bld
.MOV(offset(dst
, bld
, i
/ 2), tmp
);
5304 if (components
% 2) {
5305 bld
.MOV(offset(dst
, bld
, components
/ 2), tmp
);
5310 setup_imm_df(const fs_builder
&bld
, double v
)
5312 const struct gen_device_info
*devinfo
= bld
.shader
->devinfo
;
5313 assert(devinfo
->gen
>= 7);
5315 if (devinfo
->gen
>= 8)
5316 return brw_imm_df(v
);
5318 /* gen7.5 does not support DF immediates straighforward but the DIM
5319 * instruction allows to set the 64-bit immediate value.
5321 if (devinfo
->is_haswell
) {
5322 const fs_builder ubld
= bld
.exec_all().group(1, 0);
5323 fs_reg dst
= ubld
.vgrf(BRW_REGISTER_TYPE_DF
, 1);
5324 ubld
.DIM(dst
, brw_imm_df(v
));
5325 return component(dst
, 0);
5328 /* gen7 does not support DF immediates, so we generate a 64-bit constant by
5329 * writing the low 32-bit of the constant to suboffset 0 of a VGRF and
5330 * the high 32-bit to suboffset 4 and then applying a stride of 0.
5332 * Alternatively, we could also produce a normal VGRF (without stride 0)
5333 * by writing to all the channels in the VGRF, however, that would hit the
5334 * gen7 bug where we have to split writes that span more than 1 register
5335 * into instructions with a width of 4 (otherwise the write to the second
5336 * register written runs into an execmask hardware bug) which isn't very
5349 const fs_builder ubld
= bld
.exec_all().group(1, 0);
5350 const fs_reg tmp
= ubld
.vgrf(BRW_REGISTER_TYPE_UD
, 2);
5351 ubld
.MOV(tmp
, brw_imm_ud(di
.i1
));
5352 ubld
.MOV(horiz_offset(tmp
, 1), brw_imm_ud(di
.i2
));
5354 return component(retype(tmp
, BRW_REGISTER_TYPE_DF
), 0);