2 * Copyright © 2010 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 #include "compiler/glsl/ir.h"
26 #include "brw_fs_surface_builder.h"
30 using namespace brw::surface_access
;
33 fs_visitor::emit_nir_code()
35 /* emit the arrays used for inputs and outputs - load/store intrinsics will
36 * be converted to reads/writes of these arrays
40 nir_emit_system_values();
42 /* get the main function and emit it */
43 nir_foreach_function(function
, nir
) {
44 assert(strcmp(function
->name
, "main") == 0);
45 assert(function
->impl
);
46 nir_emit_impl(function
->impl
);
51 fs_visitor::nir_setup_outputs()
53 if (stage
== MESA_SHADER_TESS_CTRL
|| stage
== MESA_SHADER_FRAGMENT
)
56 unsigned vec4s
[VARYING_SLOT_TESS_MAX
] = { 0, };
58 /* Calculate the size of output registers in a separate pass, before
59 * allocating them. With ARB_enhanced_layouts, multiple output variables
60 * may occupy the same slot, but have different type sizes.
62 nir_foreach_variable(var
, &nir
->outputs
) {
63 const int loc
= var
->data
.driver_location
;
64 const unsigned var_vec4s
=
65 var
->data
.compact
? DIV_ROUND_UP(glsl_get_length(var
->type
), 4)
66 : type_size_vec4(var
->type
);
67 vec4s
[loc
] = MAX2(vec4s
[loc
], var_vec4s
);
70 nir_foreach_variable(var
, &nir
->outputs
) {
71 const int loc
= var
->data
.driver_location
;
72 if (outputs
[loc
].file
== BAD_FILE
) {
73 fs_reg reg
= bld
.vgrf(BRW_REGISTER_TYPE_F
, 4 * vec4s
[loc
]);
74 for (unsigned i
= 0; i
< vec4s
[loc
]; i
++) {
75 outputs
[loc
+ i
] = offset(reg
, bld
, 4 * i
);
82 fs_visitor::nir_setup_uniforms()
84 /* Only the first compile gets to set up uniforms. */
85 if (push_constant_loc
) {
86 assert(pull_constant_loc
);
90 uniforms
= nir
->num_uniforms
/ 4;
92 if (stage
== MESA_SHADER_COMPUTE
) {
93 /* Add a uniform for the thread local id. It must be the last uniform
96 assert(uniforms
== prog_data
->nr_params
);
97 uint32_t *param
= brw_stage_prog_data_add_params(prog_data
, 1);
98 *param
= BRW_PARAM_BUILTIN_SUBGROUP_ID
;
99 subgroup_id
= fs_reg(UNIFORM
, uniforms
++, BRW_REGISTER_TYPE_UD
);
104 emit_system_values_block(nir_block
*block
, fs_visitor
*v
)
108 nir_foreach_instr(instr
, block
) {
109 if (instr
->type
!= nir_instr_type_intrinsic
)
112 nir_intrinsic_instr
*intrin
= nir_instr_as_intrinsic(instr
);
113 switch (intrin
->intrinsic
) {
114 case nir_intrinsic_load_vertex_id
:
115 unreachable("should be lowered by lower_vertex_id().");
117 case nir_intrinsic_load_vertex_id_zero_base
:
118 case nir_intrinsic_load_base_vertex
:
119 case nir_intrinsic_load_instance_id
:
120 case nir_intrinsic_load_base_instance
:
121 case nir_intrinsic_load_draw_id
:
122 unreachable("should be lowered by brw_nir_lower_vs_inputs().");
124 case nir_intrinsic_load_invocation_id
:
125 if (v
->stage
== MESA_SHADER_TESS_CTRL
)
127 assert(v
->stage
== MESA_SHADER_GEOMETRY
);
128 reg
= &v
->nir_system_values
[SYSTEM_VALUE_INVOCATION_ID
];
129 if (reg
->file
== BAD_FILE
) {
130 const fs_builder abld
= v
->bld
.annotate("gl_InvocationID", NULL
);
131 fs_reg
g1(retype(brw_vec8_grf(1, 0), BRW_REGISTER_TYPE_UD
));
132 fs_reg iid
= abld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
133 abld
.SHR(iid
, g1
, brw_imm_ud(27u));
138 case nir_intrinsic_load_sample_pos
:
139 assert(v
->stage
== MESA_SHADER_FRAGMENT
);
140 reg
= &v
->nir_system_values
[SYSTEM_VALUE_SAMPLE_POS
];
141 if (reg
->file
== BAD_FILE
)
142 *reg
= *v
->emit_samplepos_setup();
145 case nir_intrinsic_load_sample_id
:
146 assert(v
->stage
== MESA_SHADER_FRAGMENT
);
147 reg
= &v
->nir_system_values
[SYSTEM_VALUE_SAMPLE_ID
];
148 if (reg
->file
== BAD_FILE
)
149 *reg
= *v
->emit_sampleid_setup();
152 case nir_intrinsic_load_sample_mask_in
:
153 assert(v
->stage
== MESA_SHADER_FRAGMENT
);
154 assert(v
->devinfo
->gen
>= 7);
155 reg
= &v
->nir_system_values
[SYSTEM_VALUE_SAMPLE_MASK_IN
];
156 if (reg
->file
== BAD_FILE
)
157 *reg
= *v
->emit_samplemaskin_setup();
160 case nir_intrinsic_load_work_group_id
:
161 assert(v
->stage
== MESA_SHADER_COMPUTE
);
162 reg
= &v
->nir_system_values
[SYSTEM_VALUE_WORK_GROUP_ID
];
163 if (reg
->file
== BAD_FILE
)
164 *reg
= *v
->emit_cs_work_group_id_setup();
167 case nir_intrinsic_load_helper_invocation
:
168 assert(v
->stage
== MESA_SHADER_FRAGMENT
);
169 reg
= &v
->nir_system_values
[SYSTEM_VALUE_HELPER_INVOCATION
];
170 if (reg
->file
== BAD_FILE
) {
171 const fs_builder abld
=
172 v
->bld
.annotate("gl_HelperInvocation", NULL
);
174 /* On Gen6+ (gl_HelperInvocation is only exposed on Gen7+) the
175 * pixel mask is in g1.7 of the thread payload.
177 * We move the per-channel pixel enable bit to the low bit of each
178 * channel by shifting the byte containing the pixel mask by the
179 * vector immediate 0x76543210UV.
181 * The region of <1,8,0> reads only 1 byte (the pixel masks for
182 * subspans 0 and 1) in SIMD8 and an additional byte (the pixel
183 * masks for 2 and 3) in SIMD16.
185 fs_reg shifted
= abld
.vgrf(BRW_REGISTER_TYPE_UW
, 1);
187 stride(byte_offset(retype(brw_vec1_grf(1, 0),
188 BRW_REGISTER_TYPE_UB
), 28),
190 brw_imm_v(0x76543210));
192 /* A set bit in the pixel mask means the channel is enabled, but
193 * that is the opposite of gl_HelperInvocation so we need to invert
196 * The negate source-modifier bit of logical instructions on Gen8+
197 * performs 1's complement negation, so we can use that instead of
200 fs_reg inverted
= negate(shifted
);
201 if (v
->devinfo
->gen
< 8) {
202 inverted
= abld
.vgrf(BRW_REGISTER_TYPE_UW
);
203 abld
.NOT(inverted
, shifted
);
206 /* We then resolve the 0/1 result to 0/~0 boolean values by ANDing
207 * with 1 and negating.
209 fs_reg anded
= abld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
210 abld
.AND(anded
, inverted
, brw_imm_uw(1));
212 fs_reg dst
= abld
.vgrf(BRW_REGISTER_TYPE_D
, 1);
213 abld
.MOV(dst
, negate(retype(anded
, BRW_REGISTER_TYPE_D
)));
227 fs_visitor::nir_emit_system_values()
229 nir_system_values
= ralloc_array(mem_ctx
, fs_reg
, SYSTEM_VALUE_MAX
);
230 for (unsigned i
= 0; i
< SYSTEM_VALUE_MAX
; i
++) {
231 nir_system_values
[i
] = fs_reg();
234 /* Always emit SUBGROUP_INVOCATION. Dead code will clean it up if we
235 * never end up using it.
238 const fs_builder abld
= bld
.annotate("gl_SubgroupInvocation", NULL
);
239 fs_reg
®
= nir_system_values
[SYSTEM_VALUE_SUBGROUP_INVOCATION
];
240 reg
= abld
.vgrf(BRW_REGISTER_TYPE_W
);
242 const fs_builder allbld8
= abld
.group(8, 0).exec_all();
243 allbld8
.MOV(reg
, brw_imm_v(0x76543210));
244 if (dispatch_width
> 8)
245 allbld8
.ADD(byte_offset(reg
, 16), reg
, brw_imm_uw(8u));
246 if (dispatch_width
> 16) {
247 const fs_builder allbld16
= abld
.group(16, 0).exec_all();
248 allbld16
.ADD(byte_offset(reg
, 32), reg
, brw_imm_uw(16u));
252 nir_foreach_function(function
, nir
) {
253 assert(strcmp(function
->name
, "main") == 0);
254 assert(function
->impl
);
255 nir_foreach_block(block
, function
->impl
) {
256 emit_system_values_block(block
, this);
262 * Returns a type based on a reference_type (word, float, half-float) and a
265 * Reference BRW_REGISTER_TYPE are HF,F,DF,W,D,UW,UD.
267 * @FIXME: 64-bit return types are always DF on integer types to maintain
268 * compability with uses of DF previously to the introduction of int64
272 brw_reg_type_from_bit_size(const unsigned bit_size
,
273 const brw_reg_type reference_type
)
275 switch(reference_type
) {
276 case BRW_REGISTER_TYPE_HF
:
277 case BRW_REGISTER_TYPE_F
:
278 case BRW_REGISTER_TYPE_DF
:
281 return BRW_REGISTER_TYPE_HF
;
283 return BRW_REGISTER_TYPE_F
;
285 return BRW_REGISTER_TYPE_DF
;
287 unreachable("Invalid bit size");
289 case BRW_REGISTER_TYPE_W
:
290 case BRW_REGISTER_TYPE_D
:
291 case BRW_REGISTER_TYPE_Q
:
294 return BRW_REGISTER_TYPE_W
;
296 return BRW_REGISTER_TYPE_D
;
298 return BRW_REGISTER_TYPE_Q
;
300 unreachable("Invalid bit size");
302 case BRW_REGISTER_TYPE_UW
:
303 case BRW_REGISTER_TYPE_UD
:
304 case BRW_REGISTER_TYPE_UQ
:
307 return BRW_REGISTER_TYPE_UW
;
309 return BRW_REGISTER_TYPE_UD
;
311 return BRW_REGISTER_TYPE_UQ
;
313 unreachable("Invalid bit size");
316 unreachable("Unknown type");
321 fs_visitor::nir_emit_impl(nir_function_impl
*impl
)
323 nir_locals
= ralloc_array(mem_ctx
, fs_reg
, impl
->reg_alloc
);
324 for (unsigned i
= 0; i
< impl
->reg_alloc
; i
++) {
325 nir_locals
[i
] = fs_reg();
328 foreach_list_typed(nir_register
, reg
, node
, &impl
->registers
) {
329 unsigned array_elems
=
330 reg
->num_array_elems
== 0 ? 1 : reg
->num_array_elems
;
331 unsigned size
= array_elems
* reg
->num_components
;
332 const brw_reg_type reg_type
=
333 brw_reg_type_from_bit_size(reg
->bit_size
, BRW_REGISTER_TYPE_F
);
334 nir_locals
[reg
->index
] = bld
.vgrf(reg_type
, size
);
337 nir_ssa_values
= reralloc(mem_ctx
, nir_ssa_values
, fs_reg
,
340 nir_emit_cf_list(&impl
->body
);
344 fs_visitor::nir_emit_cf_list(exec_list
*list
)
346 exec_list_validate(list
);
347 foreach_list_typed(nir_cf_node
, node
, node
, list
) {
348 switch (node
->type
) {
350 nir_emit_if(nir_cf_node_as_if(node
));
353 case nir_cf_node_loop
:
354 nir_emit_loop(nir_cf_node_as_loop(node
));
357 case nir_cf_node_block
:
358 nir_emit_block(nir_cf_node_as_block(node
));
362 unreachable("Invalid CFG node block");
368 fs_visitor::nir_emit_if(nir_if
*if_stmt
)
370 /* first, put the condition into f0 */
371 fs_inst
*inst
= bld
.MOV(bld
.null_reg_d(),
372 retype(get_nir_src(if_stmt
->condition
),
373 BRW_REGISTER_TYPE_D
));
374 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
376 bld
.IF(BRW_PREDICATE_NORMAL
);
378 nir_emit_cf_list(&if_stmt
->then_list
);
380 /* note: if the else is empty, dead CF elimination will remove it */
381 bld
.emit(BRW_OPCODE_ELSE
);
383 nir_emit_cf_list(&if_stmt
->else_list
);
385 bld
.emit(BRW_OPCODE_ENDIF
);
389 fs_visitor::nir_emit_loop(nir_loop
*loop
)
391 bld
.emit(BRW_OPCODE_DO
);
393 nir_emit_cf_list(&loop
->body
);
395 bld
.emit(BRW_OPCODE_WHILE
);
399 fs_visitor::nir_emit_block(nir_block
*block
)
401 nir_foreach_instr(instr
, block
) {
402 nir_emit_instr(instr
);
407 fs_visitor::nir_emit_instr(nir_instr
*instr
)
409 const fs_builder abld
= bld
.annotate(NULL
, instr
);
411 switch (instr
->type
) {
412 case nir_instr_type_alu
:
413 nir_emit_alu(abld
, nir_instr_as_alu(instr
));
416 case nir_instr_type_intrinsic
:
418 case MESA_SHADER_VERTEX
:
419 nir_emit_vs_intrinsic(abld
, nir_instr_as_intrinsic(instr
));
421 case MESA_SHADER_TESS_CTRL
:
422 nir_emit_tcs_intrinsic(abld
, nir_instr_as_intrinsic(instr
));
424 case MESA_SHADER_TESS_EVAL
:
425 nir_emit_tes_intrinsic(abld
, nir_instr_as_intrinsic(instr
));
427 case MESA_SHADER_GEOMETRY
:
428 nir_emit_gs_intrinsic(abld
, nir_instr_as_intrinsic(instr
));
430 case MESA_SHADER_FRAGMENT
:
431 nir_emit_fs_intrinsic(abld
, nir_instr_as_intrinsic(instr
));
433 case MESA_SHADER_COMPUTE
:
434 nir_emit_cs_intrinsic(abld
, nir_instr_as_intrinsic(instr
));
437 unreachable("unsupported shader stage");
441 case nir_instr_type_tex
:
442 nir_emit_texture(abld
, nir_instr_as_tex(instr
));
445 case nir_instr_type_load_const
:
446 nir_emit_load_const(abld
, nir_instr_as_load_const(instr
));
449 case nir_instr_type_ssa_undef
:
450 /* We create a new VGRF for undefs on every use (by handling
451 * them in get_nir_src()), rather than for each definition.
452 * This helps register coalescing eliminate MOVs from undef.
456 case nir_instr_type_jump
:
457 nir_emit_jump(abld
, nir_instr_as_jump(instr
));
461 unreachable("unknown instruction type");
466 * Recognizes a parent instruction of nir_op_extract_* and changes the type to
470 fs_visitor::optimize_extract_to_float(nir_alu_instr
*instr
,
471 const fs_reg
&result
)
473 if (!instr
->src
[0].src
.is_ssa
||
474 !instr
->src
[0].src
.ssa
->parent_instr
)
477 if (instr
->src
[0].src
.ssa
->parent_instr
->type
!= nir_instr_type_alu
)
480 nir_alu_instr
*src0
=
481 nir_instr_as_alu(instr
->src
[0].src
.ssa
->parent_instr
);
483 if (src0
->op
!= nir_op_extract_u8
&& src0
->op
!= nir_op_extract_u16
&&
484 src0
->op
!= nir_op_extract_i8
&& src0
->op
!= nir_op_extract_i16
)
487 nir_const_value
*element
= nir_src_as_const_value(src0
->src
[1].src
);
488 assert(element
!= NULL
);
490 /* Element type to extract.*/
491 const brw_reg_type type
= brw_int_type(
492 src0
->op
== nir_op_extract_u16
|| src0
->op
== nir_op_extract_i16
? 2 : 1,
493 src0
->op
== nir_op_extract_i16
|| src0
->op
== nir_op_extract_i8
);
495 fs_reg op0
= get_nir_src(src0
->src
[0].src
);
496 op0
.type
= brw_type_for_nir_type(devinfo
,
497 (nir_alu_type
)(nir_op_infos
[src0
->op
].input_types
[0] |
498 nir_src_bit_size(src0
->src
[0].src
)));
499 op0
= offset(op0
, bld
, src0
->src
[0].swizzle
[0]);
501 set_saturate(instr
->dest
.saturate
,
502 bld
.MOV(result
, subscript(op0
, type
, element
->u32
[0])));
507 fs_visitor::optimize_frontfacing_ternary(nir_alu_instr
*instr
,
508 const fs_reg
&result
)
510 if (!instr
->src
[0].src
.is_ssa
||
511 instr
->src
[0].src
.ssa
->parent_instr
->type
!= nir_instr_type_intrinsic
)
514 nir_intrinsic_instr
*src0
=
515 nir_instr_as_intrinsic(instr
->src
[0].src
.ssa
->parent_instr
);
517 if (src0
->intrinsic
!= nir_intrinsic_load_front_face
)
520 nir_const_value
*value1
= nir_src_as_const_value(instr
->src
[1].src
);
521 if (!value1
|| fabsf(value1
->f32
[0]) != 1.0f
)
524 nir_const_value
*value2
= nir_src_as_const_value(instr
->src
[2].src
);
525 if (!value2
|| fabsf(value2
->f32
[0]) != 1.0f
)
528 fs_reg tmp
= vgrf(glsl_type::int_type
);
530 if (devinfo
->gen
>= 6) {
531 /* Bit 15 of g0.0 is 0 if the polygon is front facing. */
532 fs_reg g0
= fs_reg(retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_W
));
534 /* For (gl_FrontFacing ? 1.0 : -1.0), emit:
536 * or(8) tmp.1<2>W g0.0<0,1,0>W 0x00003f80W
537 * and(8) dst<1>D tmp<8,8,1>D 0xbf800000D
539 * and negate g0.0<0,1,0>W for (gl_FrontFacing ? -1.0 : 1.0).
541 * This negation looks like it's safe in practice, because bits 0:4 will
542 * surely be TRIANGLES
545 if (value1
->f32
[0] == -1.0f
) {
549 bld
.OR(subscript(tmp
, BRW_REGISTER_TYPE_W
, 1),
550 g0
, brw_imm_uw(0x3f80));
552 /* Bit 31 of g1.6 is 0 if the polygon is front facing. */
553 fs_reg g1_6
= fs_reg(retype(brw_vec1_grf(1, 6), BRW_REGISTER_TYPE_D
));
555 /* For (gl_FrontFacing ? 1.0 : -1.0), emit:
557 * or(8) tmp<1>D g1.6<0,1,0>D 0x3f800000D
558 * and(8) dst<1>D tmp<8,8,1>D 0xbf800000D
560 * and negate g1.6<0,1,0>D for (gl_FrontFacing ? -1.0 : 1.0).
562 * This negation looks like it's safe in practice, because bits 0:4 will
563 * surely be TRIANGLES
566 if (value1
->f32
[0] == -1.0f
) {
570 bld
.OR(tmp
, g1_6
, brw_imm_d(0x3f800000));
572 bld
.AND(retype(result
, BRW_REGISTER_TYPE_D
), tmp
, brw_imm_d(0xbf800000));
578 emit_find_msb_using_lzd(const fs_builder
&bld
,
579 const fs_reg
&result
,
587 /* LZD of an absolute value source almost always does the right
588 * thing. There are two problem values:
590 * * 0x80000000. Since abs(0x80000000) == 0x80000000, LZD returns
591 * 0. However, findMSB(int(0x80000000)) == 30.
593 * * 0xffffffff. Since abs(0xffffffff) == 1, LZD returns
594 * 31. Section 8.8 (Integer Functions) of the GLSL 4.50 spec says:
596 * For a value of zero or negative one, -1 will be returned.
598 * * Negative powers of two. LZD(abs(-(1<<x))) returns x, but
599 * findMSB(-(1<<x)) should return x-1.
601 * For all negative number cases, including 0x80000000 and
602 * 0xffffffff, the correct value is obtained from LZD if instead of
603 * negating the (already negative) value the logical-not is used. A
604 * conditonal logical-not can be achieved in two instructions.
606 temp
= bld
.vgrf(BRW_REGISTER_TYPE_D
);
608 bld
.ASR(temp
, src
, brw_imm_d(31));
609 bld
.XOR(temp
, temp
, src
);
612 bld
.LZD(retype(result
, BRW_REGISTER_TYPE_UD
),
613 retype(temp
, BRW_REGISTER_TYPE_UD
));
615 /* LZD counts from the MSB side, while GLSL's findMSB() wants the count
616 * from the LSB side. Subtract the result from 31 to convert the MSB
617 * count into an LSB count. If no bits are set, LZD will return 32.
618 * 31-32 = -1, which is exactly what findMSB() is supposed to return.
620 inst
= bld
.ADD(result
, retype(result
, BRW_REGISTER_TYPE_D
), brw_imm_d(31));
621 inst
->src
[0].negate
= true;
625 fs_visitor::nir_emit_alu(const fs_builder
&bld
, nir_alu_instr
*instr
)
627 struct brw_wm_prog_key
*fs_key
= (struct brw_wm_prog_key
*) this->key
;
630 fs_reg result
= get_nir_dest(instr
->dest
.dest
);
631 result
.type
= brw_type_for_nir_type(devinfo
,
632 (nir_alu_type
)(nir_op_infos
[instr
->op
].output_type
|
633 nir_dest_bit_size(instr
->dest
.dest
)));
636 for (unsigned i
= 0; i
< nir_op_infos
[instr
->op
].num_inputs
; i
++) {
637 op
[i
] = get_nir_src(instr
->src
[i
].src
);
638 op
[i
].type
= brw_type_for_nir_type(devinfo
,
639 (nir_alu_type
)(nir_op_infos
[instr
->op
].input_types
[i
] |
640 nir_src_bit_size(instr
->src
[i
].src
)));
641 op
[i
].abs
= instr
->src
[i
].abs
;
642 op
[i
].negate
= instr
->src
[i
].negate
;
645 /* We get a bunch of mov's out of the from_ssa pass and they may still
646 * be vectorized. We'll handle them as a special-case. We'll also
647 * handle vecN here because it's basically the same thing.
655 fs_reg temp
= result
;
656 bool need_extra_copy
= false;
657 for (unsigned i
= 0; i
< nir_op_infos
[instr
->op
].num_inputs
; i
++) {
658 if (!instr
->src
[i
].src
.is_ssa
&&
659 instr
->dest
.dest
.reg
.reg
== instr
->src
[i
].src
.reg
.reg
) {
660 need_extra_copy
= true;
661 temp
= bld
.vgrf(result
.type
, 4);
666 for (unsigned i
= 0; i
< 4; i
++) {
667 if (!(instr
->dest
.write_mask
& (1 << i
)))
670 if (instr
->op
== nir_op_imov
|| instr
->op
== nir_op_fmov
) {
671 inst
= bld
.MOV(offset(temp
, bld
, i
),
672 offset(op
[0], bld
, instr
->src
[0].swizzle
[i
]));
674 inst
= bld
.MOV(offset(temp
, bld
, i
),
675 offset(op
[i
], bld
, instr
->src
[i
].swizzle
[0]));
677 inst
->saturate
= instr
->dest
.saturate
;
680 /* In this case the source and destination registers were the same,
681 * so we need to insert an extra set of moves in order to deal with
684 if (need_extra_copy
) {
685 for (unsigned i
= 0; i
< 4; i
++) {
686 if (!(instr
->dest
.write_mask
& (1 << i
)))
689 bld
.MOV(offset(result
, bld
, i
), offset(temp
, bld
, i
));
698 /* At this point, we have dealt with any instruction that operates on
699 * more than a single channel. Therefore, we can just adjust the source
700 * and destination registers for that channel and emit the instruction.
702 unsigned channel
= 0;
703 if (nir_op_infos
[instr
->op
].output_size
== 0) {
704 /* Since NIR is doing the scalarizing for us, we should only ever see
705 * vectorized operations with a single channel.
707 assert(_mesa_bitcount(instr
->dest
.write_mask
) == 1);
708 channel
= ffs(instr
->dest
.write_mask
) - 1;
710 result
= offset(result
, bld
, channel
);
713 for (unsigned i
= 0; i
< nir_op_infos
[instr
->op
].num_inputs
; i
++) {
714 assert(nir_op_infos
[instr
->op
].input_sizes
[i
] < 2);
715 op
[i
] = offset(op
[i
], bld
, instr
->src
[i
].swizzle
[channel
]);
721 if (optimize_extract_to_float(instr
, result
))
723 inst
= bld
.MOV(result
, op
[0]);
724 inst
->saturate
= instr
->dest
.saturate
;
734 /* CHV PRM, vol07, 3D Media GPGPU Engine, Register Region Restrictions:
736 * "When source or destination is 64b (...), regioning in Align1
737 * must follow these rules:
739 * 1. Source and destination horizontal stride must be aligned to
743 * This means that 32-bit to 64-bit conversions need to have the 32-bit
744 * data elements aligned to 64-bit. This restriction does not apply to
747 if (nir_dest_bit_size(instr
->dest
.dest
) == 64 &&
748 nir_src_bit_size(instr
->src
[0].src
) == 32 &&
749 (devinfo
->is_cherryview
|| gen_device_info_is_9lp(devinfo
))) {
750 fs_reg tmp
= bld
.vgrf(result
.type
, 1);
751 tmp
= subscript(tmp
, op
[0].type
, 0);
752 inst
= bld
.MOV(tmp
, op
[0]);
753 inst
= bld
.MOV(result
, tmp
);
754 inst
->saturate
= instr
->dest
.saturate
;
763 inst
= bld
.MOV(result
, op
[0]);
764 inst
->saturate
= instr
->dest
.saturate
;
769 /* Straightforward since the source can be assumed to be
772 set_condmod(BRW_CONDITIONAL_NZ
, bld
.MOV(result
, op
[0]));
773 set_predicate(BRW_PREDICATE_NORMAL
, bld
.MOV(result
, brw_imm_f(1.0f
)));
775 } else if (type_sz(op
[0].type
) < 8) {
776 /* AND(val, 0x80000000) gives the sign bit.
778 * Predicated OR ORs 1.0 (0x3f800000) with the sign bit if val is not
781 bld
.CMP(bld
.null_reg_f(), op
[0], brw_imm_f(0.0f
), BRW_CONDITIONAL_NZ
);
783 fs_reg result_int
= retype(result
, BRW_REGISTER_TYPE_UD
);
784 op
[0].type
= BRW_REGISTER_TYPE_UD
;
785 result
.type
= BRW_REGISTER_TYPE_UD
;
786 bld
.AND(result_int
, op
[0], brw_imm_ud(0x80000000u
));
788 inst
= bld
.OR(result_int
, result_int
, brw_imm_ud(0x3f800000u
));
789 inst
->predicate
= BRW_PREDICATE_NORMAL
;
790 if (instr
->dest
.saturate
) {
791 inst
= bld
.MOV(result
, result
);
792 inst
->saturate
= true;
795 /* For doubles we do the same but we need to consider:
797 * - 2-src instructions can't operate with 64-bit immediates
798 * - The sign is encoded in the high 32-bit of each DF
799 * - We need to produce a DF result.
802 fs_reg zero
= vgrf(glsl_type::double_type
);
803 bld
.MOV(zero
, setup_imm_df(bld
, 0.0));
804 bld
.CMP(bld
.null_reg_df(), op
[0], zero
, BRW_CONDITIONAL_NZ
);
806 bld
.MOV(result
, zero
);
808 fs_reg r
= subscript(result
, BRW_REGISTER_TYPE_UD
, 1);
809 bld
.AND(r
, subscript(op
[0], BRW_REGISTER_TYPE_UD
, 1),
810 brw_imm_ud(0x80000000u
));
812 set_predicate(BRW_PREDICATE_NORMAL
,
813 bld
.OR(r
, r
, brw_imm_ud(0x3ff00000u
)));
815 if (instr
->dest
.saturate
) {
816 inst
= bld
.MOV(result
, result
);
817 inst
->saturate
= true;
824 /* ASR(val, 31) -> negative val generates 0xffffffff (signed -1).
825 * -> non-negative val generates 0x00000000.
826 * Predicated OR sets 1 if val is positive.
828 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
829 bld
.CMP(bld
.null_reg_d(), op
[0], brw_imm_d(0), BRW_CONDITIONAL_G
);
830 bld
.ASR(result
, op
[0], brw_imm_d(31));
831 inst
= bld
.OR(result
, result
, brw_imm_d(1));
832 inst
->predicate
= BRW_PREDICATE_NORMAL
;
836 inst
= bld
.emit(SHADER_OPCODE_RCP
, result
, op
[0]);
837 inst
->saturate
= instr
->dest
.saturate
;
841 inst
= bld
.emit(SHADER_OPCODE_EXP2
, result
, op
[0]);
842 inst
->saturate
= instr
->dest
.saturate
;
846 inst
= bld
.emit(SHADER_OPCODE_LOG2
, result
, op
[0]);
847 inst
->saturate
= instr
->dest
.saturate
;
851 inst
= bld
.emit(SHADER_OPCODE_SIN
, result
, op
[0]);
852 inst
->saturate
= instr
->dest
.saturate
;
856 inst
= bld
.emit(SHADER_OPCODE_COS
, result
, op
[0]);
857 inst
->saturate
= instr
->dest
.saturate
;
861 if (fs_key
->high_quality_derivatives
) {
862 inst
= bld
.emit(FS_OPCODE_DDX_FINE
, result
, op
[0]);
864 inst
= bld
.emit(FS_OPCODE_DDX_COARSE
, result
, op
[0]);
866 inst
->saturate
= instr
->dest
.saturate
;
868 case nir_op_fddx_fine
:
869 inst
= bld
.emit(FS_OPCODE_DDX_FINE
, result
, op
[0]);
870 inst
->saturate
= instr
->dest
.saturate
;
872 case nir_op_fddx_coarse
:
873 inst
= bld
.emit(FS_OPCODE_DDX_COARSE
, result
, op
[0]);
874 inst
->saturate
= instr
->dest
.saturate
;
877 if (fs_key
->high_quality_derivatives
) {
878 inst
= bld
.emit(FS_OPCODE_DDY_FINE
, result
, op
[0]);
880 inst
= bld
.emit(FS_OPCODE_DDY_COARSE
, result
, op
[0]);
882 inst
->saturate
= instr
->dest
.saturate
;
884 case nir_op_fddy_fine
:
885 inst
= bld
.emit(FS_OPCODE_DDY_FINE
, result
, op
[0]);
886 inst
->saturate
= instr
->dest
.saturate
;
888 case nir_op_fddy_coarse
:
889 inst
= bld
.emit(FS_OPCODE_DDY_COARSE
, result
, op
[0]);
890 inst
->saturate
= instr
->dest
.saturate
;
895 inst
= bld
.ADD(result
, op
[0], op
[1]);
896 inst
->saturate
= instr
->dest
.saturate
;
900 inst
= bld
.MUL(result
, op
[0], op
[1]);
901 inst
->saturate
= instr
->dest
.saturate
;
905 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
906 bld
.MUL(result
, op
[0], op
[1]);
909 case nir_op_imul_high
:
910 case nir_op_umul_high
:
911 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
912 bld
.emit(SHADER_OPCODE_MULH
, result
, op
[0], op
[1]);
917 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
918 bld
.emit(SHADER_OPCODE_INT_QUOTIENT
, result
, op
[0], op
[1]);
921 case nir_op_uadd_carry
:
922 unreachable("Should have been lowered by carry_to_arith().");
924 case nir_op_usub_borrow
:
925 unreachable("Should have been lowered by borrow_to_arith().");
929 /* According to the sign table for INT DIV in the Ivy Bridge PRM, it
930 * appears that our hardware just does the right thing for signed
933 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
934 bld
.emit(SHADER_OPCODE_INT_REMAINDER
, result
, op
[0], op
[1]);
938 /* Get a regular C-style remainder. If a % b == 0, set the predicate. */
939 bld
.emit(SHADER_OPCODE_INT_REMAINDER
, result
, op
[0], op
[1]);
941 /* Math instructions don't support conditional mod */
942 inst
= bld
.MOV(bld
.null_reg_d(), result
);
943 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
945 /* Now, we need to determine if signs of the sources are different.
946 * When we XOR the sources, the top bit is 0 if they are the same and 1
947 * if they are different. We can then use a conditional modifier to
948 * turn that into a predicate. This leads us to an XOR.l instruction.
950 * Technically, according to the PRM, you're not allowed to use .l on a
951 * XOR instruction. However, emperical experiments and Curro's reading
952 * of the simulator source both indicate that it's safe.
954 fs_reg tmp
= bld
.vgrf(BRW_REGISTER_TYPE_D
);
955 inst
= bld
.XOR(tmp
, op
[0], op
[1]);
956 inst
->predicate
= BRW_PREDICATE_NORMAL
;
957 inst
->conditional_mod
= BRW_CONDITIONAL_L
;
959 /* If the result of the initial remainder operation is non-zero and the
960 * two sources have different signs, add in a copy of op[1] to get the
961 * final integer modulus value.
963 inst
= bld
.ADD(result
, result
, op
[1]);
964 inst
->predicate
= BRW_PREDICATE_NORMAL
;
972 fs_reg dest
= result
;
973 if (nir_src_bit_size(instr
->src
[0].src
) > 32) {
974 dest
= bld
.vgrf(BRW_REGISTER_TYPE_DF
, 1);
976 brw_conditional_mod cond
;
979 cond
= BRW_CONDITIONAL_L
;
982 cond
= BRW_CONDITIONAL_GE
;
985 cond
= BRW_CONDITIONAL_Z
;
988 cond
= BRW_CONDITIONAL_NZ
;
991 unreachable("bad opcode");
993 bld
.CMP(dest
, op
[0], op
[1], cond
);
994 if (nir_src_bit_size(instr
->src
[0].src
) > 32) {
995 bld
.MOV(result
, subscript(dest
, BRW_REGISTER_TYPE_UD
, 0));
1006 fs_reg dest
= result
;
1007 if (nir_src_bit_size(instr
->src
[0].src
) > 32) {
1008 dest
= bld
.vgrf(BRW_REGISTER_TYPE_UQ
, 1);
1011 brw_conditional_mod cond
;
1012 switch (instr
->op
) {
1015 cond
= BRW_CONDITIONAL_L
;
1019 cond
= BRW_CONDITIONAL_GE
;
1022 cond
= BRW_CONDITIONAL_Z
;
1025 cond
= BRW_CONDITIONAL_NZ
;
1028 unreachable("bad opcode");
1030 bld
.CMP(dest
, op
[0], op
[1], cond
);
1031 if (nir_src_bit_size(instr
->src
[0].src
) > 32) {
1032 bld
.MOV(result
, subscript(dest
, BRW_REGISTER_TYPE_UD
, 0));
1038 if (devinfo
->gen
>= 8) {
1039 op
[0] = resolve_source_modifiers(op
[0]);
1041 bld
.NOT(result
, op
[0]);
1044 if (devinfo
->gen
>= 8) {
1045 op
[0] = resolve_source_modifiers(op
[0]);
1046 op
[1] = resolve_source_modifiers(op
[1]);
1048 bld
.XOR(result
, op
[0], op
[1]);
1051 if (devinfo
->gen
>= 8) {
1052 op
[0] = resolve_source_modifiers(op
[0]);
1053 op
[1] = resolve_source_modifiers(op
[1]);
1055 bld
.OR(result
, op
[0], op
[1]);
1058 if (devinfo
->gen
>= 8) {
1059 op
[0] = resolve_source_modifiers(op
[0]);
1060 op
[1] = resolve_source_modifiers(op
[1]);
1062 bld
.AND(result
, op
[0], op
[1]);
1068 case nir_op_ball_fequal2
:
1069 case nir_op_ball_iequal2
:
1070 case nir_op_ball_fequal3
:
1071 case nir_op_ball_iequal3
:
1072 case nir_op_ball_fequal4
:
1073 case nir_op_ball_iequal4
:
1074 case nir_op_bany_fnequal2
:
1075 case nir_op_bany_inequal2
:
1076 case nir_op_bany_fnequal3
:
1077 case nir_op_bany_inequal3
:
1078 case nir_op_bany_fnequal4
:
1079 case nir_op_bany_inequal4
:
1080 unreachable("Lowered by nir_lower_alu_reductions");
1082 case nir_op_fnoise1_1
:
1083 case nir_op_fnoise1_2
:
1084 case nir_op_fnoise1_3
:
1085 case nir_op_fnoise1_4
:
1086 case nir_op_fnoise2_1
:
1087 case nir_op_fnoise2_2
:
1088 case nir_op_fnoise2_3
:
1089 case nir_op_fnoise2_4
:
1090 case nir_op_fnoise3_1
:
1091 case nir_op_fnoise3_2
:
1092 case nir_op_fnoise3_3
:
1093 case nir_op_fnoise3_4
:
1094 case nir_op_fnoise4_1
:
1095 case nir_op_fnoise4_2
:
1096 case nir_op_fnoise4_3
:
1097 case nir_op_fnoise4_4
:
1098 unreachable("not reached: should be handled by lower_noise");
1101 unreachable("not reached: should be handled by ldexp_to_arith()");
1104 inst
= bld
.emit(SHADER_OPCODE_SQRT
, result
, op
[0]);
1105 inst
->saturate
= instr
->dest
.saturate
;
1109 inst
= bld
.emit(SHADER_OPCODE_RSQ
, result
, op
[0]);
1110 inst
->saturate
= instr
->dest
.saturate
;
1115 bld
.MOV(result
, negate(op
[0]));
1120 if (nir_src_bit_size(instr
->src
[0].src
) == 64) {
1121 /* two-argument instructions can't take 64-bit immediates */
1125 if (instr
->op
== nir_op_f2b
) {
1126 zero
= vgrf(glsl_type::double_type
);
1127 tmp
= vgrf(glsl_type::double_type
);
1128 bld
.MOV(zero
, setup_imm_df(bld
, 0.0));
1130 zero
= vgrf(glsl_type::int64_t_type
);
1131 tmp
= vgrf(glsl_type::int64_t_type
);
1132 bld
.MOV(zero
, brw_imm_q(0));
1135 /* A SIMD16 execution needs to be split in two instructions, so use
1136 * a vgrf instead of the flag register as dst so instruction splitting
1139 bld
.CMP(tmp
, op
[0], zero
, BRW_CONDITIONAL_NZ
);
1140 bld
.MOV(result
, subscript(tmp
, BRW_REGISTER_TYPE_UD
, 0));
1142 if (instr
->op
== nir_op_f2b
) {
1143 bld
.CMP(result
, op
[0], brw_imm_f(0.0f
), BRW_CONDITIONAL_NZ
);
1145 bld
.CMP(result
, op
[0], brw_imm_d(0), BRW_CONDITIONAL_NZ
);
1151 inst
= bld
.RNDZ(result
, op
[0]);
1152 inst
->saturate
= instr
->dest
.saturate
;
1155 case nir_op_fceil
: {
1156 op
[0].negate
= !op
[0].negate
;
1157 fs_reg temp
= vgrf(glsl_type::float_type
);
1158 bld
.RNDD(temp
, op
[0]);
1160 inst
= bld
.MOV(result
, temp
);
1161 inst
->saturate
= instr
->dest
.saturate
;
1165 inst
= bld
.RNDD(result
, op
[0]);
1166 inst
->saturate
= instr
->dest
.saturate
;
1169 inst
= bld
.FRC(result
, op
[0]);
1170 inst
->saturate
= instr
->dest
.saturate
;
1172 case nir_op_fround_even
:
1173 inst
= bld
.RNDE(result
, op
[0]);
1174 inst
->saturate
= instr
->dest
.saturate
;
1177 case nir_op_fquantize2f16
: {
1178 fs_reg tmp16
= bld
.vgrf(BRW_REGISTER_TYPE_D
);
1179 fs_reg tmp32
= bld
.vgrf(BRW_REGISTER_TYPE_F
);
1180 fs_reg zero
= bld
.vgrf(BRW_REGISTER_TYPE_F
);
1182 /* The destination stride must be at least as big as the source stride. */
1183 tmp16
.type
= BRW_REGISTER_TYPE_W
;
1186 /* Check for denormal */
1187 fs_reg abs_src0
= op
[0];
1188 abs_src0
.abs
= true;
1189 bld
.CMP(bld
.null_reg_f(), abs_src0
, brw_imm_f(ldexpf(1.0, -14)),
1191 /* Get the appropriately signed zero */
1192 bld
.AND(retype(zero
, BRW_REGISTER_TYPE_UD
),
1193 retype(op
[0], BRW_REGISTER_TYPE_UD
),
1194 brw_imm_ud(0x80000000));
1195 /* Do the actual F32 -> F16 -> F32 conversion */
1196 bld
.emit(BRW_OPCODE_F32TO16
, tmp16
, op
[0]);
1197 bld
.emit(BRW_OPCODE_F16TO32
, tmp32
, tmp16
);
1198 /* Select that or zero based on normal status */
1199 inst
= bld
.SEL(result
, zero
, tmp32
);
1200 inst
->predicate
= BRW_PREDICATE_NORMAL
;
1201 inst
->saturate
= instr
->dest
.saturate
;
1208 inst
= bld
.emit_minmax(result
, op
[0], op
[1], BRW_CONDITIONAL_L
);
1209 inst
->saturate
= instr
->dest
.saturate
;
1215 inst
= bld
.emit_minmax(result
, op
[0], op
[1], BRW_CONDITIONAL_GE
);
1216 inst
->saturate
= instr
->dest
.saturate
;
1219 case nir_op_pack_snorm_2x16
:
1220 case nir_op_pack_snorm_4x8
:
1221 case nir_op_pack_unorm_2x16
:
1222 case nir_op_pack_unorm_4x8
:
1223 case nir_op_unpack_snorm_2x16
:
1224 case nir_op_unpack_snorm_4x8
:
1225 case nir_op_unpack_unorm_2x16
:
1226 case nir_op_unpack_unorm_4x8
:
1227 case nir_op_unpack_half_2x16
:
1228 case nir_op_pack_half_2x16
:
1229 unreachable("not reached: should be handled by lower_packing_builtins");
1231 case nir_op_unpack_half_2x16_split_x
:
1232 inst
= bld
.emit(FS_OPCODE_UNPACK_HALF_2x16_SPLIT_X
, result
, op
[0]);
1233 inst
->saturate
= instr
->dest
.saturate
;
1235 case nir_op_unpack_half_2x16_split_y
:
1236 inst
= bld
.emit(FS_OPCODE_UNPACK_HALF_2x16_SPLIT_Y
, result
, op
[0]);
1237 inst
->saturate
= instr
->dest
.saturate
;
1240 case nir_op_pack_64_2x32_split
:
1241 bld
.emit(FS_OPCODE_PACK
, result
, op
[0], op
[1]);
1244 case nir_op_unpack_64_2x32_split_x
:
1245 case nir_op_unpack_64_2x32_split_y
: {
1246 if (instr
->op
== nir_op_unpack_64_2x32_split_x
)
1247 bld
.MOV(result
, subscript(op
[0], BRW_REGISTER_TYPE_UD
, 0));
1249 bld
.MOV(result
, subscript(op
[0], BRW_REGISTER_TYPE_UD
, 1));
1254 inst
= bld
.emit(SHADER_OPCODE_POW
, result
, op
[0], op
[1]);
1255 inst
->saturate
= instr
->dest
.saturate
;
1258 case nir_op_bitfield_reverse
:
1259 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1260 bld
.BFREV(result
, op
[0]);
1263 case nir_op_bit_count
:
1264 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1265 bld
.CBIT(result
, op
[0]);
1268 case nir_op_ufind_msb
: {
1269 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1270 emit_find_msb_using_lzd(bld
, result
, op
[0], false);
1274 case nir_op_ifind_msb
: {
1275 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1277 if (devinfo
->gen
< 7) {
1278 emit_find_msb_using_lzd(bld
, result
, op
[0], true);
1280 bld
.FBH(retype(result
, BRW_REGISTER_TYPE_UD
), op
[0]);
1282 /* FBH counts from the MSB side, while GLSL's findMSB() wants the
1283 * count from the LSB side. If FBH didn't return an error
1284 * (0xFFFFFFFF), then subtract the result from 31 to convert the MSB
1285 * count into an LSB count.
1287 bld
.CMP(bld
.null_reg_d(), result
, brw_imm_d(-1), BRW_CONDITIONAL_NZ
);
1289 inst
= bld
.ADD(result
, result
, brw_imm_d(31));
1290 inst
->predicate
= BRW_PREDICATE_NORMAL
;
1291 inst
->src
[0].negate
= true;
1296 case nir_op_find_lsb
:
1297 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1299 if (devinfo
->gen
< 7) {
1300 fs_reg temp
= vgrf(glsl_type::int_type
);
1302 /* (x & -x) generates a value that consists of only the LSB of x.
1303 * For all powers of 2, findMSB(y) == findLSB(y).
1305 fs_reg src
= retype(op
[0], BRW_REGISTER_TYPE_D
);
1306 fs_reg negated_src
= src
;
1308 /* One must be negated, and the other must be non-negated. It
1309 * doesn't matter which is which.
1311 negated_src
.negate
= true;
1314 bld
.AND(temp
, src
, negated_src
);
1315 emit_find_msb_using_lzd(bld
, result
, temp
, false);
1317 bld
.FBL(result
, op
[0]);
1321 case nir_op_ubitfield_extract
:
1322 case nir_op_ibitfield_extract
:
1323 unreachable("should have been lowered");
1326 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1327 bld
.BFE(result
, op
[2], op
[1], op
[0]);
1330 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1331 bld
.BFI1(result
, op
[0], op
[1]);
1334 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1335 bld
.BFI2(result
, op
[0], op
[1], op
[2]);
1338 case nir_op_bitfield_insert
:
1339 unreachable("not reached: should have been lowered");
1344 fs_reg shift_count
= op
[1];
1346 if (devinfo
->is_cherryview
|| gen_device_info_is_9lp(devinfo
)) {
1347 if (op
[1].file
== VGRF
&&
1348 (result
.type
== BRW_REGISTER_TYPE_Q
||
1349 result
.type
== BRW_REGISTER_TYPE_UQ
)) {
1350 shift_count
= fs_reg(VGRF
, alloc
.allocate(dispatch_width
/ 4),
1351 BRW_REGISTER_TYPE_UD
);
1352 shift_count
.stride
= 2;
1353 bld
.MOV(shift_count
, op
[1]);
1357 switch (instr
->op
) {
1359 bld
.SHL(result
, op
[0], shift_count
);
1362 bld
.ASR(result
, op
[0], shift_count
);
1365 bld
.SHR(result
, op
[0], shift_count
);
1368 unreachable("not reached");
1373 case nir_op_pack_half_2x16_split
:
1374 bld
.emit(FS_OPCODE_PACK_HALF_2x16_SPLIT
, result
, op
[0], op
[1]);
1378 inst
= bld
.MAD(result
, op
[2], op
[1], op
[0]);
1379 inst
->saturate
= instr
->dest
.saturate
;
1383 inst
= bld
.LRP(result
, op
[0], op
[1], op
[2]);
1384 inst
->saturate
= instr
->dest
.saturate
;
1388 if (optimize_frontfacing_ternary(instr
, result
))
1391 bld
.CMP(bld
.null_reg_d(), op
[0], brw_imm_d(0), BRW_CONDITIONAL_NZ
);
1392 inst
= bld
.SEL(result
, op
[1], op
[2]);
1393 inst
->predicate
= BRW_PREDICATE_NORMAL
;
1396 case nir_op_extract_u8
:
1397 case nir_op_extract_i8
: {
1398 nir_const_value
*byte
= nir_src_as_const_value(instr
->src
[1].src
);
1399 assert(byte
!= NULL
);
1404 * There is no direct conversion from B/UB to Q/UQ or Q/UQ to B/UB.
1405 * Use two instructions and a word or DWord intermediate integer type.
1407 if (nir_dest_bit_size(instr
->dest
.dest
) == 64) {
1408 const brw_reg_type type
= brw_int_type(2, instr
->op
== nir_op_extract_i8
);
1410 if (instr
->op
== nir_op_extract_i8
) {
1411 /* If we need to sign extend, extract to a word first */
1412 fs_reg w_temp
= bld
.vgrf(BRW_REGISTER_TYPE_W
);
1413 bld
.MOV(w_temp
, subscript(op
[0], type
, byte
->u32
[0]));
1414 bld
.MOV(result
, w_temp
);
1416 /* Otherwise use an AND with 0xff and a word type */
1417 bld
.AND(result
, subscript(op
[0], type
, byte
->u32
[0] / 2), brw_imm_uw(0xff));
1420 const brw_reg_type type
= brw_int_type(1, instr
->op
== nir_op_extract_i8
);
1421 bld
.MOV(result
, subscript(op
[0], type
, byte
->u32
[0]));
1426 case nir_op_extract_u16
:
1427 case nir_op_extract_i16
: {
1428 const brw_reg_type type
= brw_int_type(2, instr
->op
== nir_op_extract_i16
);
1429 nir_const_value
*word
= nir_src_as_const_value(instr
->src
[1].src
);
1430 assert(word
!= NULL
);
1431 bld
.MOV(result
, subscript(op
[0], type
, word
->u32
[0]));
1436 unreachable("unhandled instruction");
1439 /* If we need to do a boolean resolve, replace the result with -(x & 1)
1440 * to sign extend the low bit to 0/~0
1442 if (devinfo
->gen
<= 5 &&
1443 (instr
->instr
.pass_flags
& BRW_NIR_BOOLEAN_MASK
) == BRW_NIR_BOOLEAN_NEEDS_RESOLVE
) {
1444 fs_reg masked
= vgrf(glsl_type::int_type
);
1445 bld
.AND(masked
, result
, brw_imm_d(1));
1446 masked
.negate
= true;
1447 bld
.MOV(retype(result
, BRW_REGISTER_TYPE_D
), masked
);
1452 fs_visitor::nir_emit_load_const(const fs_builder
&bld
,
1453 nir_load_const_instr
*instr
)
1455 const brw_reg_type reg_type
=
1456 brw_reg_type_from_bit_size(instr
->def
.bit_size
, BRW_REGISTER_TYPE_D
);
1457 fs_reg reg
= bld
.vgrf(reg_type
, instr
->def
.num_components
);
1459 switch (instr
->def
.bit_size
) {
1461 for (unsigned i
= 0; i
< instr
->def
.num_components
; i
++)
1462 bld
.MOV(offset(reg
, bld
, i
), brw_imm_d(instr
->value
.i32
[i
]));
1466 assert(devinfo
->gen
>= 7);
1467 if (devinfo
->gen
== 7) {
1468 /* We don't get 64-bit integer types until gen8 */
1469 for (unsigned i
= 0; i
< instr
->def
.num_components
; i
++) {
1470 bld
.MOV(retype(offset(reg
, bld
, i
), BRW_REGISTER_TYPE_DF
),
1471 setup_imm_df(bld
, instr
->value
.f64
[i
]));
1474 for (unsigned i
= 0; i
< instr
->def
.num_components
; i
++)
1475 bld
.MOV(offset(reg
, bld
, i
), brw_imm_q(instr
->value
.i64
[i
]));
1480 unreachable("Invalid bit size");
1483 nir_ssa_values
[instr
->def
.index
] = reg
;
1487 fs_visitor::get_nir_src(const nir_src
&src
)
1491 if (src
.ssa
->parent_instr
->type
== nir_instr_type_ssa_undef
) {
1492 const brw_reg_type reg_type
=
1493 brw_reg_type_from_bit_size(src
.ssa
->bit_size
, BRW_REGISTER_TYPE_D
);
1494 reg
= bld
.vgrf(reg_type
, src
.ssa
->num_components
);
1496 reg
= nir_ssa_values
[src
.ssa
->index
];
1499 /* We don't handle indirects on locals */
1500 assert(src
.reg
.indirect
== NULL
);
1501 reg
= offset(nir_locals
[src
.reg
.reg
->index
], bld
,
1502 src
.reg
.base_offset
* src
.reg
.reg
->num_components
);
1505 if (nir_src_bit_size(src
) == 64 && devinfo
->gen
== 7) {
1506 /* The only 64-bit type available on gen7 is DF, so use that. */
1507 reg
.type
= BRW_REGISTER_TYPE_DF
;
1509 /* To avoid floating-point denorm flushing problems, set the type by
1510 * default to an integer type - instructions that need floating point
1511 * semantics will set this to F if they need to
1513 reg
.type
= brw_reg_type_from_bit_size(nir_src_bit_size(src
),
1514 BRW_REGISTER_TYPE_D
);
1521 * Return an IMM for constants; otherwise call get_nir_src() as normal.
1523 * This function should not be called on any value which may be 64 bits.
1524 * We could theoretically support 64-bit on gen8+ but we choose not to
1525 * because it wouldn't work in general (no gen7 support) and there are
1526 * enough restrictions in 64-bit immediates that you can't take the return
1527 * value and treat it the same as the result of get_nir_src().
1530 fs_visitor::get_nir_src_imm(const nir_src
&src
)
1532 nir_const_value
*val
= nir_src_as_const_value(src
);
1533 assert(nir_src_bit_size(src
) == 32);
1534 return val
? fs_reg(brw_imm_d(val
->i32
[0])) : get_nir_src(src
);
1538 fs_visitor::get_nir_dest(const nir_dest
&dest
)
1541 const brw_reg_type reg_type
=
1542 brw_reg_type_from_bit_size(dest
.ssa
.bit_size
, BRW_REGISTER_TYPE_F
);
1543 nir_ssa_values
[dest
.ssa
.index
] =
1544 bld
.vgrf(reg_type
, dest
.ssa
.num_components
);
1545 return nir_ssa_values
[dest
.ssa
.index
];
1547 /* We don't handle indirects on locals */
1548 assert(dest
.reg
.indirect
== NULL
);
1549 return offset(nir_locals
[dest
.reg
.reg
->index
], bld
,
1550 dest
.reg
.base_offset
* dest
.reg
.reg
->num_components
);
1555 fs_visitor::get_nir_image_deref(const nir_deref_var
*deref
)
1557 fs_reg
image(UNIFORM
, deref
->var
->data
.driver_location
/ 4,
1558 BRW_REGISTER_TYPE_UD
);
1560 unsigned indirect_max
= 0;
1562 for (const nir_deref
*tail
= &deref
->deref
; tail
->child
;
1563 tail
= tail
->child
) {
1564 const nir_deref_array
*deref_array
= nir_deref_as_array(tail
->child
);
1565 assert(tail
->child
->deref_type
== nir_deref_type_array
);
1566 const unsigned size
= glsl_get_length(tail
->type
);
1567 const unsigned element_size
= type_size_scalar(deref_array
->deref
.type
);
1568 const unsigned base
= MIN2(deref_array
->base_offset
, size
- 1);
1569 image
= offset(image
, bld
, base
* element_size
);
1571 if (deref_array
->deref_array_type
== nir_deref_array_type_indirect
) {
1572 fs_reg tmp
= vgrf(glsl_type::uint_type
);
1574 /* Accessing an invalid surface index with the dataport can result
1575 * in a hang. According to the spec "if the index used to
1576 * select an individual element is negative or greater than or
1577 * equal to the size of the array, the results of the operation
1578 * are undefined but may not lead to termination" -- which is one
1579 * of the possible outcomes of the hang. Clamp the index to
1580 * prevent access outside of the array bounds.
1582 bld
.emit_minmax(tmp
, retype(get_nir_src(deref_array
->indirect
),
1583 BRW_REGISTER_TYPE_UD
),
1584 brw_imm_ud(size
- base
- 1), BRW_CONDITIONAL_L
);
1586 indirect_max
+= element_size
* (tail
->type
->length
- 1);
1588 bld
.MUL(tmp
, tmp
, brw_imm_ud(element_size
* 4));
1589 if (indirect
.file
== BAD_FILE
) {
1592 bld
.ADD(indirect
, indirect
, tmp
);
1597 if (indirect
.file
== BAD_FILE
) {
1600 /* Emit a pile of MOVs to load the uniform into a temporary. The
1601 * dead-code elimination pass will get rid of what we don't use.
1603 fs_reg tmp
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, BRW_IMAGE_PARAM_SIZE
);
1604 for (unsigned j
= 0; j
< BRW_IMAGE_PARAM_SIZE
; j
++) {
1605 bld
.emit(SHADER_OPCODE_MOV_INDIRECT
,
1606 offset(tmp
, bld
, j
), offset(image
, bld
, j
),
1607 indirect
, brw_imm_ud((indirect_max
+ 1) * 4));
1614 fs_visitor::emit_percomp(const fs_builder
&bld
, const fs_inst
&inst
,
1617 for (unsigned i
= 0; i
< 4; i
++) {
1618 if (!((wr_mask
>> i
) & 1))
1621 fs_inst
*new_inst
= new(mem_ctx
) fs_inst(inst
);
1622 new_inst
->dst
= offset(new_inst
->dst
, bld
, i
);
1623 for (unsigned j
= 0; j
< new_inst
->sources
; j
++)
1624 if (new_inst
->src
[j
].file
== VGRF
)
1625 new_inst
->src
[j
] = offset(new_inst
->src
[j
], bld
, i
);
1632 * Get the matching channel register datatype for an image intrinsic of the
1633 * specified GLSL image type.
1636 get_image_base_type(const glsl_type
*type
)
1638 switch ((glsl_base_type
)type
->sampled_type
) {
1639 case GLSL_TYPE_UINT
:
1640 return BRW_REGISTER_TYPE_UD
;
1642 return BRW_REGISTER_TYPE_D
;
1643 case GLSL_TYPE_FLOAT
:
1644 return BRW_REGISTER_TYPE_F
;
1646 unreachable("Not reached.");
1651 * Get the appropriate atomic op for an image atomic intrinsic.
1654 get_image_atomic_op(nir_intrinsic_op op
, const glsl_type
*type
)
1657 case nir_intrinsic_image_atomic_add
:
1659 case nir_intrinsic_image_atomic_min
:
1660 return (get_image_base_type(type
) == BRW_REGISTER_TYPE_D
?
1661 BRW_AOP_IMIN
: BRW_AOP_UMIN
);
1662 case nir_intrinsic_image_atomic_max
:
1663 return (get_image_base_type(type
) == BRW_REGISTER_TYPE_D
?
1664 BRW_AOP_IMAX
: BRW_AOP_UMAX
);
1665 case nir_intrinsic_image_atomic_and
:
1667 case nir_intrinsic_image_atomic_or
:
1669 case nir_intrinsic_image_atomic_xor
:
1671 case nir_intrinsic_image_atomic_exchange
:
1673 case nir_intrinsic_image_atomic_comp_swap
:
1674 return BRW_AOP_CMPWR
;
1676 unreachable("Not reachable.");
1681 emit_pixel_interpolater_send(const fs_builder
&bld
,
1686 glsl_interp_mode interpolation
)
1688 struct brw_wm_prog_data
*wm_prog_data
=
1689 brw_wm_prog_data(bld
.shader
->stage_prog_data
);
1694 if (src
.file
== BAD_FILE
) {
1696 payload
= bld
.vgrf(BRW_REGISTER_TYPE_F
, 1);
1700 mlen
= 2 * bld
.dispatch_width() / 8;
1703 inst
= bld
.emit(opcode
, dst
, payload
, desc
);
1705 /* 2 floats per slot returned */
1706 inst
->size_written
= 2 * dst
.component_size(inst
->exec_size
);
1707 inst
->pi_noperspective
= interpolation
== INTERP_MODE_NOPERSPECTIVE
;
1709 wm_prog_data
->pulls_bary
= true;
1715 * Computes 1 << x, given a D/UD register containing some value x.
1718 intexp2(const fs_builder
&bld
, const fs_reg
&x
)
1720 assert(x
.type
== BRW_REGISTER_TYPE_UD
|| x
.type
== BRW_REGISTER_TYPE_D
);
1722 fs_reg result
= bld
.vgrf(x
.type
, 1);
1723 fs_reg one
= bld
.vgrf(x
.type
, 1);
1725 bld
.MOV(one
, retype(brw_imm_d(1), one
.type
));
1726 bld
.SHL(result
, one
, x
);
1731 fs_visitor::emit_gs_end_primitive(const nir_src
&vertex_count_nir_src
)
1733 assert(stage
== MESA_SHADER_GEOMETRY
);
1735 struct brw_gs_prog_data
*gs_prog_data
= brw_gs_prog_data(prog_data
);
1737 if (gs_compile
->control_data_header_size_bits
== 0)
1740 /* We can only do EndPrimitive() functionality when the control data
1741 * consists of cut bits. Fortunately, the only time it isn't is when the
1742 * output type is points, in which case EndPrimitive() is a no-op.
1744 if (gs_prog_data
->control_data_format
!=
1745 GEN7_GS_CONTROL_DATA_FORMAT_GSCTL_CUT
) {
1749 /* Cut bits use one bit per vertex. */
1750 assert(gs_compile
->control_data_bits_per_vertex
== 1);
1752 fs_reg vertex_count
= get_nir_src(vertex_count_nir_src
);
1753 vertex_count
.type
= BRW_REGISTER_TYPE_UD
;
1755 /* Cut bit n should be set to 1 if EndPrimitive() was called after emitting
1756 * vertex n, 0 otherwise. So all we need to do here is mark bit
1757 * (vertex_count - 1) % 32 in the cut_bits register to indicate that
1758 * EndPrimitive() was called after emitting vertex (vertex_count - 1);
1759 * vec4_gs_visitor::emit_control_data_bits() will take care of the rest.
1761 * Note that if EndPrimitive() is called before emitting any vertices, this
1762 * will cause us to set bit 31 of the control_data_bits register to 1.
1763 * That's fine because:
1765 * - If max_vertices < 32, then vertex number 31 (zero-based) will never be
1766 * output, so the hardware will ignore cut bit 31.
1768 * - If max_vertices == 32, then vertex number 31 is guaranteed to be the
1769 * last vertex, so setting cut bit 31 has no effect (since the primitive
1770 * is automatically ended when the GS terminates).
1772 * - If max_vertices > 32, then the ir_emit_vertex visitor will reset the
1773 * control_data_bits register to 0 when the first vertex is emitted.
1776 const fs_builder abld
= bld
.annotate("end primitive");
1778 /* control_data_bits |= 1 << ((vertex_count - 1) % 32) */
1779 fs_reg prev_count
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
1780 abld
.ADD(prev_count
, vertex_count
, brw_imm_ud(0xffffffffu
));
1781 fs_reg mask
= intexp2(abld
, prev_count
);
1782 /* Note: we're relying on the fact that the GEN SHL instruction only pays
1783 * attention to the lower 5 bits of its second source argument, so on this
1784 * architecture, 1 << (vertex_count - 1) is equivalent to 1 <<
1785 * ((vertex_count - 1) % 32).
1787 abld
.OR(this->control_data_bits
, this->control_data_bits
, mask
);
1791 fs_visitor::emit_gs_control_data_bits(const fs_reg
&vertex_count
)
1793 assert(stage
== MESA_SHADER_GEOMETRY
);
1794 assert(gs_compile
->control_data_bits_per_vertex
!= 0);
1796 struct brw_gs_prog_data
*gs_prog_data
= brw_gs_prog_data(prog_data
);
1798 const fs_builder abld
= bld
.annotate("emit control data bits");
1799 const fs_builder fwa_bld
= bld
.exec_all();
1801 /* We use a single UD register to accumulate control data bits (32 bits
1802 * for each of the SIMD8 channels). So we need to write a DWord (32 bits)
1805 * Unfortunately, the URB_WRITE_SIMD8 message uses 128-bit (OWord) offsets.
1806 * We have select a 128-bit group via the Global and Per-Slot Offsets, then
1807 * use the Channel Mask phase to enable/disable which DWord within that
1808 * group to write. (Remember, different SIMD8 channels may have emitted
1809 * different numbers of vertices, so we may need per-slot offsets.)
1811 * Channel masking presents an annoying problem: we may have to replicate
1812 * the data up to 4 times:
1814 * Msg = Handles, Per-Slot Offsets, Channel Masks, Data, Data, Data, Data.
1816 * To avoid penalizing shaders that emit a small number of vertices, we
1817 * can avoid these sometimes: if the size of the control data header is
1818 * <= 128 bits, then there is only 1 OWord. All SIMD8 channels will land
1819 * land in the same 128-bit group, so we can skip per-slot offsets.
1821 * Similarly, if the control data header is <= 32 bits, there is only one
1822 * DWord, so we can skip channel masks.
1824 enum opcode opcode
= SHADER_OPCODE_URB_WRITE_SIMD8
;
1826 fs_reg channel_mask
, per_slot_offset
;
1828 if (gs_compile
->control_data_header_size_bits
> 32) {
1829 opcode
= SHADER_OPCODE_URB_WRITE_SIMD8_MASKED
;
1830 channel_mask
= vgrf(glsl_type::uint_type
);
1833 if (gs_compile
->control_data_header_size_bits
> 128) {
1834 opcode
= SHADER_OPCODE_URB_WRITE_SIMD8_MASKED_PER_SLOT
;
1835 per_slot_offset
= vgrf(glsl_type::uint_type
);
1838 /* Figure out which DWord we're trying to write to using the formula:
1840 * dword_index = (vertex_count - 1) * bits_per_vertex / 32
1842 * Since bits_per_vertex is a power of two, and is known at compile
1843 * time, this can be optimized to:
1845 * dword_index = (vertex_count - 1) >> (6 - log2(bits_per_vertex))
1847 if (opcode
!= SHADER_OPCODE_URB_WRITE_SIMD8
) {
1848 fs_reg dword_index
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
1849 fs_reg prev_count
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
1850 abld
.ADD(prev_count
, vertex_count
, brw_imm_ud(0xffffffffu
));
1851 unsigned log2_bits_per_vertex
=
1852 util_last_bit(gs_compile
->control_data_bits_per_vertex
);
1853 abld
.SHR(dword_index
, prev_count
, brw_imm_ud(6u - log2_bits_per_vertex
));
1855 if (per_slot_offset
.file
!= BAD_FILE
) {
1856 /* Set the per-slot offset to dword_index / 4, so that we'll write to
1857 * the appropriate OWord within the control data header.
1859 abld
.SHR(per_slot_offset
, dword_index
, brw_imm_ud(2u));
1862 /* Set the channel masks to 1 << (dword_index % 4), so that we'll
1863 * write to the appropriate DWORD within the OWORD.
1865 fs_reg channel
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
1866 fwa_bld
.AND(channel
, dword_index
, brw_imm_ud(3u));
1867 channel_mask
= intexp2(fwa_bld
, channel
);
1868 /* Then the channel masks need to be in bits 23:16. */
1869 fwa_bld
.SHL(channel_mask
, channel_mask
, brw_imm_ud(16u));
1872 /* Store the control data bits in the message payload and send it. */
1874 if (channel_mask
.file
!= BAD_FILE
)
1875 mlen
+= 4; /* channel masks, plus 3 extra copies of the data */
1876 if (per_slot_offset
.file
!= BAD_FILE
)
1879 fs_reg payload
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, mlen
);
1880 fs_reg
*sources
= ralloc_array(mem_ctx
, fs_reg
, mlen
);
1882 sources
[i
++] = fs_reg(retype(brw_vec8_grf(1, 0), BRW_REGISTER_TYPE_UD
));
1883 if (per_slot_offset
.file
!= BAD_FILE
)
1884 sources
[i
++] = per_slot_offset
;
1885 if (channel_mask
.file
!= BAD_FILE
)
1886 sources
[i
++] = channel_mask
;
1888 sources
[i
++] = this->control_data_bits
;
1891 abld
.LOAD_PAYLOAD(payload
, sources
, mlen
, mlen
);
1892 fs_inst
*inst
= abld
.emit(opcode
, reg_undef
, payload
);
1894 /* We need to increment Global Offset by 256-bits to make room for
1895 * Broadwell's extra "Vertex Count" payload at the beginning of the
1896 * URB entry. Since this is an OWord message, Global Offset is counted
1897 * in 128-bit units, so we must set it to 2.
1899 if (gs_prog_data
->static_vertex_count
== -1)
1904 fs_visitor::set_gs_stream_control_data_bits(const fs_reg
&vertex_count
,
1907 /* control_data_bits |= stream_id << ((2 * (vertex_count - 1)) % 32) */
1909 /* Note: we are calling this *before* increasing vertex_count, so
1910 * this->vertex_count == vertex_count - 1 in the formula above.
1913 /* Stream mode uses 2 bits per vertex */
1914 assert(gs_compile
->control_data_bits_per_vertex
== 2);
1916 /* Must be a valid stream */
1917 assert(stream_id
< MAX_VERTEX_STREAMS
);
1919 /* Control data bits are initialized to 0 so we don't have to set any
1920 * bits when sending vertices to stream 0.
1925 const fs_builder abld
= bld
.annotate("set stream control data bits", NULL
);
1927 /* reg::sid = stream_id */
1928 fs_reg sid
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
1929 abld
.MOV(sid
, brw_imm_ud(stream_id
));
1931 /* reg:shift_count = 2 * (vertex_count - 1) */
1932 fs_reg shift_count
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
1933 abld
.SHL(shift_count
, vertex_count
, brw_imm_ud(1u));
1935 /* Note: we're relying on the fact that the GEN SHL instruction only pays
1936 * attention to the lower 5 bits of its second source argument, so on this
1937 * architecture, stream_id << 2 * (vertex_count - 1) is equivalent to
1938 * stream_id << ((2 * (vertex_count - 1)) % 32).
1940 fs_reg mask
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
1941 abld
.SHL(mask
, sid
, shift_count
);
1942 abld
.OR(this->control_data_bits
, this->control_data_bits
, mask
);
1946 fs_visitor::emit_gs_vertex(const nir_src
&vertex_count_nir_src
,
1949 assert(stage
== MESA_SHADER_GEOMETRY
);
1951 struct brw_gs_prog_data
*gs_prog_data
= brw_gs_prog_data(prog_data
);
1953 fs_reg vertex_count
= get_nir_src(vertex_count_nir_src
);
1954 vertex_count
.type
= BRW_REGISTER_TYPE_UD
;
1956 /* Haswell and later hardware ignores the "Render Stream Select" bits
1957 * from the 3DSTATE_STREAMOUT packet when the SOL stage is disabled,
1958 * and instead sends all primitives down the pipeline for rasterization.
1959 * If the SOL stage is enabled, "Render Stream Select" is honored and
1960 * primitives bound to non-zero streams are discarded after stream output.
1962 * Since the only purpose of primives sent to non-zero streams is to
1963 * be recorded by transform feedback, we can simply discard all geometry
1964 * bound to these streams when transform feedback is disabled.
1966 if (stream_id
> 0 && !nir
->info
.has_transform_feedback_varyings
)
1969 /* If we're outputting 32 control data bits or less, then we can wait
1970 * until the shader is over to output them all. Otherwise we need to
1971 * output them as we go. Now is the time to do it, since we're about to
1972 * output the vertex_count'th vertex, so it's guaranteed that the
1973 * control data bits associated with the (vertex_count - 1)th vertex are
1976 if (gs_compile
->control_data_header_size_bits
> 32) {
1977 const fs_builder abld
=
1978 bld
.annotate("emit vertex: emit control data bits");
1980 /* Only emit control data bits if we've finished accumulating a batch
1981 * of 32 bits. This is the case when:
1983 * (vertex_count * bits_per_vertex) % 32 == 0
1985 * (in other words, when the last 5 bits of vertex_count *
1986 * bits_per_vertex are 0). Assuming bits_per_vertex == 2^n for some
1987 * integer n (which is always the case, since bits_per_vertex is
1988 * always 1 or 2), this is equivalent to requiring that the last 5-n
1989 * bits of vertex_count are 0:
1991 * vertex_count & (2^(5-n) - 1) == 0
1993 * 2^(5-n) == 2^5 / 2^n == 32 / bits_per_vertex, so this is
1996 * vertex_count & (32 / bits_per_vertex - 1) == 0
1998 * TODO: If vertex_count is an immediate, we could do some of this math
1999 * at compile time...
2002 abld
.AND(bld
.null_reg_d(), vertex_count
,
2003 brw_imm_ud(32u / gs_compile
->control_data_bits_per_vertex
- 1u));
2004 inst
->conditional_mod
= BRW_CONDITIONAL_Z
;
2006 abld
.IF(BRW_PREDICATE_NORMAL
);
2007 /* If vertex_count is 0, then no control data bits have been
2008 * accumulated yet, so we can skip emitting them.
2010 abld
.CMP(bld
.null_reg_d(), vertex_count
, brw_imm_ud(0u),
2011 BRW_CONDITIONAL_NEQ
);
2012 abld
.IF(BRW_PREDICATE_NORMAL
);
2013 emit_gs_control_data_bits(vertex_count
);
2014 abld
.emit(BRW_OPCODE_ENDIF
);
2016 /* Reset control_data_bits to 0 so we can start accumulating a new
2019 * Note: in the case where vertex_count == 0, this neutralizes the
2020 * effect of any call to EndPrimitive() that the shader may have
2021 * made before outputting its first vertex.
2023 inst
= abld
.MOV(this->control_data_bits
, brw_imm_ud(0u));
2024 inst
->force_writemask_all
= true;
2025 abld
.emit(BRW_OPCODE_ENDIF
);
2028 emit_urb_writes(vertex_count
);
2030 /* In stream mode we have to set control data bits for all vertices
2031 * unless we have disabled control data bits completely (which we do
2032 * do for GL_POINTS outputs that don't use streams).
2034 if (gs_compile
->control_data_header_size_bits
> 0 &&
2035 gs_prog_data
->control_data_format
==
2036 GEN7_GS_CONTROL_DATA_FORMAT_GSCTL_SID
) {
2037 set_gs_stream_control_data_bits(vertex_count
, stream_id
);
2042 fs_visitor::emit_gs_input_load(const fs_reg
&dst
,
2043 const nir_src
&vertex_src
,
2044 unsigned base_offset
,
2045 const nir_src
&offset_src
,
2046 unsigned num_components
,
2047 unsigned first_component
)
2049 struct brw_gs_prog_data
*gs_prog_data
= brw_gs_prog_data(prog_data
);
2051 nir_const_value
*vertex_const
= nir_src_as_const_value(vertex_src
);
2052 nir_const_value
*offset_const
= nir_src_as_const_value(offset_src
);
2053 const unsigned push_reg_count
= gs_prog_data
->base
.urb_read_length
* 8;
2055 /* TODO: figure out push input layout for invocations == 1 */
2056 /* TODO: make this work with 64-bit inputs */
2057 if (gs_prog_data
->invocations
== 1 &&
2058 type_sz(dst
.type
) <= 4 &&
2059 offset_const
!= NULL
&& vertex_const
!= NULL
&&
2060 4 * (base_offset
+ offset_const
->u32
[0]) < push_reg_count
) {
2061 int imm_offset
= (base_offset
+ offset_const
->u32
[0]) * 4 +
2062 vertex_const
->u32
[0] * push_reg_count
;
2063 for (unsigned i
= 0; i
< num_components
; i
++) {
2064 bld
.MOV(offset(dst
, bld
, i
),
2065 fs_reg(ATTR
, imm_offset
+ i
+ first_component
, dst
.type
));
2070 /* Resort to the pull model. Ensure the VUE handles are provided. */
2071 assert(gs_prog_data
->base
.include_vue_handles
);
2073 unsigned first_icp_handle
= gs_prog_data
->include_primitive_id
? 3 : 2;
2074 fs_reg icp_handle
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2076 if (gs_prog_data
->invocations
== 1) {
2078 /* The vertex index is constant; just select the proper URB handle. */
2080 retype(brw_vec8_grf(first_icp_handle
+ vertex_const
->i32
[0], 0),
2081 BRW_REGISTER_TYPE_UD
);
2083 /* The vertex index is non-constant. We need to use indirect
2084 * addressing to fetch the proper URB handle.
2086 * First, we start with the sequence <7, 6, 5, 4, 3, 2, 1, 0>
2087 * indicating that channel <n> should read the handle from
2088 * DWord <n>. We convert that to bytes by multiplying by 4.
2090 * Next, we convert the vertex index to bytes by multiplying
2091 * by 32 (shifting by 5), and add the two together. This is
2092 * the final indirect byte offset.
2094 fs_reg sequence
= bld
.vgrf(BRW_REGISTER_TYPE_W
, 1);
2095 fs_reg channel_offsets
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2096 fs_reg vertex_offset_bytes
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2097 fs_reg icp_offset_bytes
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2099 /* sequence = <7, 6, 5, 4, 3, 2, 1, 0> */
2100 bld
.MOV(sequence
, fs_reg(brw_imm_v(0x76543210)));
2101 /* channel_offsets = 4 * sequence = <28, 24, 20, 16, 12, 8, 4, 0> */
2102 bld
.SHL(channel_offsets
, sequence
, brw_imm_ud(2u));
2103 /* Convert vertex_index to bytes (multiply by 32) */
2104 bld
.SHL(vertex_offset_bytes
,
2105 retype(get_nir_src(vertex_src
), BRW_REGISTER_TYPE_UD
),
2107 bld
.ADD(icp_offset_bytes
, vertex_offset_bytes
, channel_offsets
);
2109 /* Use first_icp_handle as the base offset. There is one register
2110 * of URB handles per vertex, so inform the register allocator that
2111 * we might read up to nir->info.gs.vertices_in registers.
2113 bld
.emit(SHADER_OPCODE_MOV_INDIRECT
, icp_handle
,
2114 retype(brw_vec8_grf(first_icp_handle
, 0), icp_handle
.type
),
2115 fs_reg(icp_offset_bytes
),
2116 brw_imm_ud(nir
->info
.gs
.vertices_in
* REG_SIZE
));
2119 assert(gs_prog_data
->invocations
> 1);
2122 assert(devinfo
->gen
>= 9 || vertex_const
->i32
[0] <= 5);
2124 retype(brw_vec1_grf(first_icp_handle
+
2125 vertex_const
->i32
[0] / 8,
2126 vertex_const
->i32
[0] % 8),
2127 BRW_REGISTER_TYPE_UD
));
2129 /* The vertex index is non-constant. We need to use indirect
2130 * addressing to fetch the proper URB handle.
2133 fs_reg icp_offset_bytes
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2135 /* Convert vertex_index to bytes (multiply by 4) */
2136 bld
.SHL(icp_offset_bytes
,
2137 retype(get_nir_src(vertex_src
), BRW_REGISTER_TYPE_UD
),
2140 /* Use first_icp_handle as the base offset. There is one DWord
2141 * of URB handles per vertex, so inform the register allocator that
2142 * we might read up to ceil(nir->info.gs.vertices_in / 8) registers.
2144 bld
.emit(SHADER_OPCODE_MOV_INDIRECT
, icp_handle
,
2145 retype(brw_vec8_grf(first_icp_handle
, 0), icp_handle
.type
),
2146 fs_reg(icp_offset_bytes
),
2147 brw_imm_ud(DIV_ROUND_UP(nir
->info
.gs
.vertices_in
, 8) *
2154 fs_reg tmp_dst
= dst
;
2155 fs_reg indirect_offset
= get_nir_src(offset_src
);
2156 unsigned num_iterations
= 1;
2157 unsigned orig_num_components
= num_components
;
2159 if (type_sz(dst
.type
) == 8) {
2160 if (num_components
> 2) {
2164 fs_reg tmp
= fs_reg(VGRF
, alloc
.allocate(4), dst
.type
);
2166 first_component
= first_component
/ 2;
2169 for (unsigned iter
= 0; iter
< num_iterations
; iter
++) {
2171 /* Constant indexing - use global offset. */
2172 if (first_component
!= 0) {
2173 unsigned read_components
= num_components
+ first_component
;
2174 fs_reg tmp
= bld
.vgrf(dst
.type
, read_components
);
2175 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8
, tmp
, icp_handle
);
2176 inst
->size_written
= read_components
*
2177 tmp
.component_size(inst
->exec_size
);
2178 for (unsigned i
= 0; i
< num_components
; i
++) {
2179 bld
.MOV(offset(tmp_dst
, bld
, i
),
2180 offset(tmp
, bld
, i
+ first_component
));
2183 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8
, tmp_dst
,
2185 inst
->size_written
= num_components
*
2186 tmp_dst
.component_size(inst
->exec_size
);
2188 inst
->offset
= base_offset
+ offset_const
->u32
[0];
2191 /* Indirect indexing - use per-slot offsets as well. */
2192 const fs_reg srcs
[] = { icp_handle
, indirect_offset
};
2193 unsigned read_components
= num_components
+ first_component
;
2194 fs_reg tmp
= bld
.vgrf(dst
.type
, read_components
);
2195 fs_reg payload
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 2);
2196 bld
.LOAD_PAYLOAD(payload
, srcs
, ARRAY_SIZE(srcs
), 0);
2197 if (first_component
!= 0) {
2198 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT
, tmp
,
2200 inst
->size_written
= read_components
*
2201 tmp
.component_size(inst
->exec_size
);
2202 for (unsigned i
= 0; i
< num_components
; i
++) {
2203 bld
.MOV(offset(tmp_dst
, bld
, i
),
2204 offset(tmp
, bld
, i
+ first_component
));
2207 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT
, tmp_dst
,
2209 inst
->size_written
= num_components
*
2210 tmp_dst
.component_size(inst
->exec_size
);
2212 inst
->offset
= base_offset
;
2216 if (type_sz(dst
.type
) == 8) {
2217 shuffle_32bit_load_result_to_64bit_data(
2218 bld
, tmp_dst
, retype(tmp_dst
, BRW_REGISTER_TYPE_F
), num_components
);
2220 for (unsigned c
= 0; c
< num_components
; c
++)
2221 bld
.MOV(offset(dst
, bld
, iter
* 2 + c
), offset(tmp_dst
, bld
, c
));
2224 if (num_iterations
> 1) {
2225 num_components
= orig_num_components
- 2;
2229 fs_reg new_indirect
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2230 bld
.ADD(new_indirect
, indirect_offset
, brw_imm_ud(1u));
2231 indirect_offset
= new_indirect
;
2238 fs_visitor::get_indirect_offset(nir_intrinsic_instr
*instr
)
2240 nir_src
*offset_src
= nir_get_io_offset_src(instr
);
2241 nir_const_value
*const_value
= nir_src_as_const_value(*offset_src
);
2244 /* The only constant offset we should find is 0. brw_nir.c's
2245 * add_const_offset_to_base() will fold other constant offsets
2246 * into instr->const_index[0].
2248 assert(const_value
->u32
[0] == 0);
2252 return get_nir_src(*offset_src
);
2256 do_untyped_vector_read(const fs_builder
&bld
,
2258 const fs_reg surf_index
,
2259 const fs_reg offset_reg
,
2260 unsigned num_components
)
2262 if (type_sz(dest
.type
) == 4) {
2263 fs_reg read_result
= emit_untyped_read(bld
, surf_index
, offset_reg
,
2266 BRW_PREDICATE_NONE
);
2267 read_result
.type
= dest
.type
;
2268 for (unsigned i
= 0; i
< num_components
; i
++)
2269 bld
.MOV(offset(dest
, bld
, i
), offset(read_result
, bld
, i
));
2270 } else if (type_sz(dest
.type
) == 8) {
2271 /* Reading a dvec, so we need to:
2273 * 1. Multiply num_components by 2, to account for the fact that we
2274 * need to read 64-bit components.
2275 * 2. Shuffle the result of the load to form valid 64-bit elements
2276 * 3. Emit a second load (for components z/w) if needed.
2278 fs_reg read_offset
= bld
.vgrf(BRW_REGISTER_TYPE_UD
);
2279 bld
.MOV(read_offset
, offset_reg
);
2281 int iters
= num_components
<= 2 ? 1 : 2;
2283 /* Load the dvec, the first iteration loads components x/y, the second
2284 * iteration, if needed, loads components z/w
2286 for (int it
= 0; it
< iters
; it
++) {
2287 /* Compute number of components to read in this iteration */
2288 int iter_components
= MIN2(2, num_components
);
2289 num_components
-= iter_components
;
2291 /* Read. Since this message reads 32-bit components, we need to
2292 * read twice as many components.
2294 fs_reg read_result
= emit_untyped_read(bld
, surf_index
, read_offset
,
2296 iter_components
* 2,
2297 BRW_PREDICATE_NONE
);
2299 /* Shuffle the 32-bit load result into valid 64-bit data */
2300 const fs_reg packed_result
= bld
.vgrf(dest
.type
, iter_components
);
2301 shuffle_32bit_load_result_to_64bit_data(
2302 bld
, packed_result
, read_result
, iter_components
);
2304 /* Move each component to its destination */
2305 read_result
= retype(read_result
, BRW_REGISTER_TYPE_DF
);
2306 for (int c
= 0; c
< iter_components
; c
++) {
2307 bld
.MOV(offset(dest
, bld
, it
* 2 + c
),
2308 offset(packed_result
, bld
, c
));
2311 bld
.ADD(read_offset
, read_offset
, brw_imm_ud(16));
2314 unreachable("Unsupported type");
2319 fs_visitor::nir_emit_vs_intrinsic(const fs_builder
&bld
,
2320 nir_intrinsic_instr
*instr
)
2322 assert(stage
== MESA_SHADER_VERTEX
);
2325 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
2326 dest
= get_nir_dest(instr
->dest
);
2328 switch (instr
->intrinsic
) {
2329 case nir_intrinsic_load_vertex_id
:
2330 unreachable("should be lowered by lower_vertex_id()");
2332 case nir_intrinsic_load_vertex_id_zero_base
:
2333 case nir_intrinsic_load_base_vertex
:
2334 case nir_intrinsic_load_instance_id
:
2335 case nir_intrinsic_load_base_instance
:
2336 case nir_intrinsic_load_draw_id
: {
2337 gl_system_value sv
= nir_system_value_from_intrinsic(instr
->intrinsic
);
2338 fs_reg val
= nir_system_values
[sv
];
2339 assert(val
.file
!= BAD_FILE
);
2340 dest
.type
= val
.type
;
2345 case nir_intrinsic_load_input
: {
2346 fs_reg src
= fs_reg(ATTR
, nir_intrinsic_base(instr
) * 4, dest
.type
);
2347 unsigned first_component
= nir_intrinsic_component(instr
);
2348 unsigned num_components
= instr
->num_components
;
2349 enum brw_reg_type type
= dest
.type
;
2351 nir_const_value
*const_offset
= nir_src_as_const_value(instr
->src
[0]);
2352 assert(const_offset
&& "Indirect input loads not allowed");
2353 src
= offset(src
, bld
, const_offset
->u32
[0]);
2355 for (unsigned j
= 0; j
< num_components
; j
++) {
2356 bld
.MOV(offset(dest
, bld
, j
), offset(src
, bld
, j
+ first_component
));
2359 if (type
== BRW_REGISTER_TYPE_DF
) {
2360 /* Once the double vector is read, set again its original register
2361 * type to continue with normal execution.
2363 src
= retype(src
, type
);
2364 dest
= retype(dest
, type
);
2367 if (type_sz(src
.type
) == 8) {
2368 shuffle_32bit_load_result_to_64bit_data(bld
,
2370 retype(dest
, BRW_REGISTER_TYPE_F
),
2371 instr
->num_components
);
2377 nir_emit_intrinsic(bld
, instr
);
2383 fs_visitor::nir_emit_tcs_intrinsic(const fs_builder
&bld
,
2384 nir_intrinsic_instr
*instr
)
2386 assert(stage
== MESA_SHADER_TESS_CTRL
);
2387 struct brw_tcs_prog_key
*tcs_key
= (struct brw_tcs_prog_key
*) key
;
2388 struct brw_tcs_prog_data
*tcs_prog_data
= brw_tcs_prog_data(prog_data
);
2391 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
2392 dst
= get_nir_dest(instr
->dest
);
2394 switch (instr
->intrinsic
) {
2395 case nir_intrinsic_load_primitive_id
:
2396 bld
.MOV(dst
, fs_reg(brw_vec1_grf(0, 1)));
2398 case nir_intrinsic_load_invocation_id
:
2399 bld
.MOV(retype(dst
, invocation_id
.type
), invocation_id
);
2401 case nir_intrinsic_load_patch_vertices_in
:
2402 bld
.MOV(retype(dst
, BRW_REGISTER_TYPE_D
),
2403 brw_imm_d(tcs_key
->input_vertices
));
2406 case nir_intrinsic_barrier
: {
2407 if (tcs_prog_data
->instances
== 1)
2410 fs_reg m0
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2411 fs_reg m0_2
= component(m0
, 2);
2413 const fs_builder chanbld
= bld
.exec_all().group(1, 0);
2415 /* Zero the message header */
2416 bld
.exec_all().MOV(m0
, brw_imm_ud(0u));
2418 /* Copy "Barrier ID" from r0.2, bits 16:13 */
2419 chanbld
.AND(m0_2
, retype(brw_vec1_grf(0, 2), BRW_REGISTER_TYPE_UD
),
2420 brw_imm_ud(INTEL_MASK(16, 13)));
2422 /* Shift it up to bits 27:24. */
2423 chanbld
.SHL(m0_2
, m0_2
, brw_imm_ud(11));
2425 /* Set the Barrier Count and the enable bit */
2426 chanbld
.OR(m0_2
, m0_2
,
2427 brw_imm_ud(tcs_prog_data
->instances
<< 9 | (1 << 15)));
2429 bld
.emit(SHADER_OPCODE_BARRIER
, bld
.null_reg_ud(), m0
);
2433 case nir_intrinsic_load_input
:
2434 unreachable("nir_lower_io should never give us these.");
2437 case nir_intrinsic_load_per_vertex_input
: {
2438 fs_reg indirect_offset
= get_indirect_offset(instr
);
2439 unsigned imm_offset
= instr
->const_index
[0];
2441 const nir_src
&vertex_src
= instr
->src
[0];
2442 nir_const_value
*vertex_const
= nir_src_as_const_value(vertex_src
);
2449 /* Emit a MOV to resolve <0,1,0> regioning. */
2450 icp_handle
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2452 retype(brw_vec1_grf(1 + (vertex_const
->i32
[0] >> 3),
2453 vertex_const
->i32
[0] & 7),
2454 BRW_REGISTER_TYPE_UD
));
2455 } else if (tcs_prog_data
->instances
== 1 &&
2456 vertex_src
.is_ssa
&&
2457 vertex_src
.ssa
->parent_instr
->type
== nir_instr_type_intrinsic
&&
2458 nir_instr_as_intrinsic(vertex_src
.ssa
->parent_instr
)->intrinsic
== nir_intrinsic_load_invocation_id
) {
2459 /* For the common case of only 1 instance, an array index of
2460 * gl_InvocationID means reading g1. Skip all the indirect work.
2462 icp_handle
= retype(brw_vec8_grf(1, 0), BRW_REGISTER_TYPE_UD
);
2464 /* The vertex index is non-constant. We need to use indirect
2465 * addressing to fetch the proper URB handle.
2467 icp_handle
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2469 /* Each ICP handle is a single DWord (4 bytes) */
2470 fs_reg vertex_offset_bytes
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2471 bld
.SHL(vertex_offset_bytes
,
2472 retype(get_nir_src(vertex_src
), BRW_REGISTER_TYPE_UD
),
2475 /* Start at g1. We might read up to 4 registers. */
2476 bld
.emit(SHADER_OPCODE_MOV_INDIRECT
, icp_handle
,
2477 retype(brw_vec8_grf(1, 0), icp_handle
.type
), vertex_offset_bytes
,
2478 brw_imm_ud(4 * REG_SIZE
));
2481 /* We can only read two double components with each URB read, so
2482 * we send two read messages in that case, each one loading up to
2483 * two double components.
2485 unsigned num_iterations
= 1;
2486 unsigned num_components
= instr
->num_components
;
2487 unsigned first_component
= nir_intrinsic_component(instr
);
2488 fs_reg orig_dst
= dst
;
2489 if (type_sz(dst
.type
) == 8) {
2490 first_component
= first_component
/ 2;
2491 if (instr
->num_components
> 2) {
2496 fs_reg tmp
= fs_reg(VGRF
, alloc
.allocate(4), dst
.type
);
2500 for (unsigned iter
= 0; iter
< num_iterations
; iter
++) {
2501 if (indirect_offset
.file
== BAD_FILE
) {
2502 /* Constant indexing - use global offset. */
2503 if (first_component
!= 0) {
2504 unsigned read_components
= num_components
+ first_component
;
2505 fs_reg tmp
= bld
.vgrf(dst
.type
, read_components
);
2506 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8
, tmp
, icp_handle
);
2507 for (unsigned i
= 0; i
< num_components
; i
++) {
2508 bld
.MOV(offset(dst
, bld
, i
),
2509 offset(tmp
, bld
, i
+ first_component
));
2512 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8
, dst
, icp_handle
);
2514 inst
->offset
= imm_offset
;
2517 /* Indirect indexing - use per-slot offsets as well. */
2518 const fs_reg srcs
[] = { icp_handle
, indirect_offset
};
2519 fs_reg payload
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 2);
2520 bld
.LOAD_PAYLOAD(payload
, srcs
, ARRAY_SIZE(srcs
), 0);
2521 if (first_component
!= 0) {
2522 unsigned read_components
= num_components
+ first_component
;
2523 fs_reg tmp
= bld
.vgrf(dst
.type
, read_components
);
2524 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT
, tmp
,
2526 for (unsigned i
= 0; i
< num_components
; i
++) {
2527 bld
.MOV(offset(dst
, bld
, i
),
2528 offset(tmp
, bld
, i
+ first_component
));
2531 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT
, dst
,
2534 inst
->offset
= imm_offset
;
2537 inst
->size_written
= (num_components
+ first_component
) *
2538 inst
->dst
.component_size(inst
->exec_size
);
2540 /* If we are reading 64-bit data using 32-bit read messages we need
2541 * build proper 64-bit data elements by shuffling the low and high
2542 * 32-bit components around like we do for other things like UBOs
2545 if (type_sz(dst
.type
) == 8) {
2546 shuffle_32bit_load_result_to_64bit_data(
2547 bld
, dst
, retype(dst
, BRW_REGISTER_TYPE_F
), num_components
);
2549 for (unsigned c
= 0; c
< num_components
; c
++) {
2550 bld
.MOV(offset(orig_dst
, bld
, iter
* 2 + c
),
2551 offset(dst
, bld
, c
));
2555 /* Copy the temporary to the destination to deal with writemasking.
2557 * Also attempt to deal with gl_PointSize being in the .w component.
2559 if (inst
->offset
== 0 && indirect_offset
.file
== BAD_FILE
) {
2560 assert(type_sz(dst
.type
) < 8);
2561 inst
->dst
= bld
.vgrf(dst
.type
, 4);
2562 inst
->size_written
= 4 * REG_SIZE
;
2563 bld
.MOV(dst
, offset(inst
->dst
, bld
, 3));
2566 /* If we are loading double data and we need a second read message
2567 * adjust the write offset
2569 if (num_iterations
> 1) {
2570 num_components
= instr
->num_components
- 2;
2577 case nir_intrinsic_load_output
:
2578 case nir_intrinsic_load_per_vertex_output
: {
2579 fs_reg indirect_offset
= get_indirect_offset(instr
);
2580 unsigned imm_offset
= instr
->const_index
[0];
2581 unsigned first_component
= nir_intrinsic_component(instr
);
2584 if (indirect_offset
.file
== BAD_FILE
) {
2585 /* Replicate the patch handle to all enabled channels */
2586 fs_reg patch_handle
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2587 bld
.MOV(patch_handle
,
2588 retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_UD
));
2591 if (first_component
!= 0) {
2592 unsigned read_components
=
2593 instr
->num_components
+ first_component
;
2594 fs_reg tmp
= bld
.vgrf(dst
.type
, read_components
);
2595 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8
, tmp
,
2597 inst
->size_written
= read_components
* REG_SIZE
;
2598 for (unsigned i
= 0; i
< instr
->num_components
; i
++) {
2599 bld
.MOV(offset(dst
, bld
, i
),
2600 offset(tmp
, bld
, i
+ first_component
));
2603 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8
, dst
,
2605 inst
->size_written
= instr
->num_components
* REG_SIZE
;
2607 inst
->offset
= imm_offset
;
2611 /* Indirect indexing - use per-slot offsets as well. */
2612 const fs_reg srcs
[] = {
2613 retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_UD
),
2616 fs_reg payload
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 2);
2617 bld
.LOAD_PAYLOAD(payload
, srcs
, ARRAY_SIZE(srcs
), 0);
2618 if (first_component
!= 0) {
2619 unsigned read_components
=
2620 instr
->num_components
+ first_component
;
2621 fs_reg tmp
= bld
.vgrf(dst
.type
, read_components
);
2622 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT
, tmp
,
2624 inst
->size_written
= read_components
* REG_SIZE
;
2625 for (unsigned i
= 0; i
< instr
->num_components
; i
++) {
2626 bld
.MOV(offset(dst
, bld
, i
),
2627 offset(tmp
, bld
, i
+ first_component
));
2630 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT
, dst
,
2632 inst
->size_written
= instr
->num_components
* REG_SIZE
;
2634 inst
->offset
= imm_offset
;
2640 case nir_intrinsic_store_output
:
2641 case nir_intrinsic_store_per_vertex_output
: {
2642 fs_reg value
= get_nir_src(instr
->src
[0]);
2643 bool is_64bit
= (instr
->src
[0].is_ssa
?
2644 instr
->src
[0].ssa
->bit_size
: instr
->src
[0].reg
.reg
->bit_size
) == 64;
2645 fs_reg indirect_offset
= get_indirect_offset(instr
);
2646 unsigned imm_offset
= instr
->const_index
[0];
2647 unsigned mask
= instr
->const_index
[1];
2648 unsigned header_regs
= 0;
2650 srcs
[header_regs
++] = retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_UD
);
2652 if (indirect_offset
.file
!= BAD_FILE
) {
2653 srcs
[header_regs
++] = indirect_offset
;
2659 unsigned num_components
= util_last_bit(mask
);
2662 /* We can only pack two 64-bit components in a single message, so send
2663 * 2 messages if we have more components
2665 unsigned num_iterations
= 1;
2666 unsigned iter_components
= num_components
;
2667 unsigned first_component
= nir_intrinsic_component(instr
);
2669 first_component
= first_component
/ 2;
2670 if (instr
->num_components
> 2) {
2672 iter_components
= 2;
2676 mask
= mask
<< first_component
;
2678 for (unsigned iter
= 0; iter
< num_iterations
; iter
++) {
2679 if (!is_64bit
&& mask
!= WRITEMASK_XYZW
) {
2680 srcs
[header_regs
++] = brw_imm_ud(mask
<< 16);
2681 opcode
= indirect_offset
.file
!= BAD_FILE
?
2682 SHADER_OPCODE_URB_WRITE_SIMD8_MASKED_PER_SLOT
:
2683 SHADER_OPCODE_URB_WRITE_SIMD8_MASKED
;
2684 } else if (is_64bit
&& ((mask
& WRITEMASK_XY
) != WRITEMASK_XY
)) {
2685 /* Expand the 64-bit mask to 32-bit channels. We only handle
2686 * two channels in each iteration, so we only care about X/Y.
2688 unsigned mask32
= 0;
2689 if (mask
& WRITEMASK_X
)
2690 mask32
|= WRITEMASK_XY
;
2691 if (mask
& WRITEMASK_Y
)
2692 mask32
|= WRITEMASK_ZW
;
2694 /* If the mask does not include any of the channels X or Y there
2695 * is nothing to do in this iteration. Move on to the next couple
2696 * of 64-bit channels.
2704 srcs
[header_regs
++] = brw_imm_ud(mask32
<< 16);
2705 opcode
= indirect_offset
.file
!= BAD_FILE
?
2706 SHADER_OPCODE_URB_WRITE_SIMD8_MASKED_PER_SLOT
:
2707 SHADER_OPCODE_URB_WRITE_SIMD8_MASKED
;
2709 opcode
= indirect_offset
.file
!= BAD_FILE
?
2710 SHADER_OPCODE_URB_WRITE_SIMD8_PER_SLOT
:
2711 SHADER_OPCODE_URB_WRITE_SIMD8
;
2714 for (unsigned i
= 0; i
< iter_components
; i
++) {
2715 if (!(mask
& (1 << (i
+ first_component
))))
2719 srcs
[header_regs
+ i
+ first_component
] = offset(value
, bld
, i
);
2721 /* We need to shuffle the 64-bit data to match the layout
2722 * expected by our 32-bit URB write messages. We use a temporary
2725 unsigned channel
= iter
* 2 + i
;
2726 fs_reg dest
= shuffle_64bit_data_for_32bit_write(bld
,
2727 offset(value
, bld
, channel
), 1);
2729 srcs
[header_regs
+ (i
+ first_component
) * 2] = dest
;
2730 srcs
[header_regs
+ (i
+ first_component
) * 2 + 1] =
2731 offset(dest
, bld
, 1);
2736 header_regs
+ (is_64bit
? 2 * iter_components
: iter_components
) +
2737 (is_64bit
? 2 * first_component
: first_component
);
2739 bld
.vgrf(BRW_REGISTER_TYPE_UD
, mlen
);
2740 bld
.LOAD_PAYLOAD(payload
, srcs
, mlen
, header_regs
);
2742 fs_inst
*inst
= bld
.emit(opcode
, bld
.null_reg_ud(), payload
);
2743 inst
->offset
= imm_offset
;
2746 /* If this is a 64-bit attribute, select the next two 64-bit channels
2747 * to be handled in the next iteration.
2758 nir_emit_intrinsic(bld
, instr
);
2764 fs_visitor::nir_emit_tes_intrinsic(const fs_builder
&bld
,
2765 nir_intrinsic_instr
*instr
)
2767 assert(stage
== MESA_SHADER_TESS_EVAL
);
2768 struct brw_tes_prog_data
*tes_prog_data
= brw_tes_prog_data(prog_data
);
2771 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
2772 dest
= get_nir_dest(instr
->dest
);
2774 switch (instr
->intrinsic
) {
2775 case nir_intrinsic_load_primitive_id
:
2776 bld
.MOV(dest
, fs_reg(brw_vec1_grf(0, 1)));
2778 case nir_intrinsic_load_tess_coord
:
2779 /* gl_TessCoord is part of the payload in g1-3 */
2780 for (unsigned i
= 0; i
< 3; i
++) {
2781 bld
.MOV(offset(dest
, bld
, i
), fs_reg(brw_vec8_grf(1 + i
, 0)));
2785 case nir_intrinsic_load_input
:
2786 case nir_intrinsic_load_per_vertex_input
: {
2787 fs_reg indirect_offset
= get_indirect_offset(instr
);
2788 unsigned imm_offset
= instr
->const_index
[0];
2789 unsigned first_component
= nir_intrinsic_component(instr
);
2791 if (type_sz(dest
.type
) == 8) {
2792 first_component
= first_component
/ 2;
2796 if (indirect_offset
.file
== BAD_FILE
) {
2797 /* Arbitrarily only push up to 32 vec4 slots worth of data,
2798 * which is 16 registers (since each holds 2 vec4 slots).
2800 unsigned slot_count
= 1;
2801 if (type_sz(dest
.type
) == 8 && instr
->num_components
> 2)
2804 const unsigned max_push_slots
= 32;
2805 if (imm_offset
+ slot_count
<= max_push_slots
) {
2806 fs_reg src
= fs_reg(ATTR
, imm_offset
/ 2, dest
.type
);
2807 for (int i
= 0; i
< instr
->num_components
; i
++) {
2808 unsigned comp
= 16 / type_sz(dest
.type
) * (imm_offset
% 2) +
2809 i
+ first_component
;
2810 bld
.MOV(offset(dest
, bld
, i
), component(src
, comp
));
2813 tes_prog_data
->base
.urb_read_length
=
2814 MAX2(tes_prog_data
->base
.urb_read_length
,
2815 DIV_ROUND_UP(imm_offset
+ slot_count
, 2));
2817 /* Replicate the patch handle to all enabled channels */
2818 const fs_reg srcs
[] = {
2819 retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_UD
)
2821 fs_reg patch_handle
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2822 bld
.LOAD_PAYLOAD(patch_handle
, srcs
, ARRAY_SIZE(srcs
), 0);
2824 if (first_component
!= 0) {
2825 unsigned read_components
=
2826 instr
->num_components
+ first_component
;
2827 fs_reg tmp
= bld
.vgrf(dest
.type
, read_components
);
2828 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8
, tmp
,
2830 inst
->size_written
= read_components
* REG_SIZE
;
2831 for (unsigned i
= 0; i
< instr
->num_components
; i
++) {
2832 bld
.MOV(offset(dest
, bld
, i
),
2833 offset(tmp
, bld
, i
+ first_component
));
2836 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8
, dest
,
2838 inst
->size_written
= instr
->num_components
* REG_SIZE
;
2841 inst
->offset
= imm_offset
;
2844 /* Indirect indexing - use per-slot offsets as well. */
2846 /* We can only read two double components with each URB read, so
2847 * we send two read messages in that case, each one loading up to
2848 * two double components.
2850 unsigned num_iterations
= 1;
2851 unsigned num_components
= instr
->num_components
;
2852 fs_reg orig_dest
= dest
;
2853 if (type_sz(dest
.type
) == 8) {
2854 if (instr
->num_components
> 2) {
2858 fs_reg tmp
= fs_reg(VGRF
, alloc
.allocate(4), dest
.type
);
2862 for (unsigned iter
= 0; iter
< num_iterations
; iter
++) {
2863 const fs_reg srcs
[] = {
2864 retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_UD
),
2867 fs_reg payload
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 2);
2868 bld
.LOAD_PAYLOAD(payload
, srcs
, ARRAY_SIZE(srcs
), 0);
2870 if (first_component
!= 0) {
2871 unsigned read_components
=
2872 num_components
+ first_component
;
2873 fs_reg tmp
= bld
.vgrf(dest
.type
, read_components
);
2874 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT
, tmp
,
2876 for (unsigned i
= 0; i
< num_components
; i
++) {
2877 bld
.MOV(offset(dest
, bld
, i
),
2878 offset(tmp
, bld
, i
+ first_component
));
2881 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT
, dest
,
2885 inst
->offset
= imm_offset
;
2886 inst
->size_written
= (num_components
+ first_component
) *
2887 inst
->dst
.component_size(inst
->exec_size
);
2889 /* If we are reading 64-bit data using 32-bit read messages we need
2890 * build proper 64-bit data elements by shuffling the low and high
2891 * 32-bit components around like we do for other things like UBOs
2894 if (type_sz(dest
.type
) == 8) {
2895 shuffle_32bit_load_result_to_64bit_data(
2896 bld
, dest
, retype(dest
, BRW_REGISTER_TYPE_F
), num_components
);
2898 for (unsigned c
= 0; c
< num_components
; c
++) {
2899 bld
.MOV(offset(orig_dest
, bld
, iter
* 2 + c
),
2900 offset(dest
, bld
, c
));
2904 /* If we are loading double data and we need a second read message
2907 if (num_iterations
> 1) {
2908 num_components
= instr
->num_components
- 2;
2916 nir_emit_intrinsic(bld
, instr
);
2922 fs_visitor::nir_emit_gs_intrinsic(const fs_builder
&bld
,
2923 nir_intrinsic_instr
*instr
)
2925 assert(stage
== MESA_SHADER_GEOMETRY
);
2926 fs_reg indirect_offset
;
2929 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
2930 dest
= get_nir_dest(instr
->dest
);
2932 switch (instr
->intrinsic
) {
2933 case nir_intrinsic_load_primitive_id
:
2934 assert(stage
== MESA_SHADER_GEOMETRY
);
2935 assert(brw_gs_prog_data(prog_data
)->include_primitive_id
);
2936 bld
.MOV(retype(dest
, BRW_REGISTER_TYPE_UD
),
2937 retype(fs_reg(brw_vec8_grf(2, 0)), BRW_REGISTER_TYPE_UD
));
2940 case nir_intrinsic_load_input
:
2941 unreachable("load_input intrinsics are invalid for the GS stage");
2943 case nir_intrinsic_load_per_vertex_input
:
2944 emit_gs_input_load(dest
, instr
->src
[0], instr
->const_index
[0],
2945 instr
->src
[1], instr
->num_components
,
2946 nir_intrinsic_component(instr
));
2949 case nir_intrinsic_emit_vertex_with_counter
:
2950 emit_gs_vertex(instr
->src
[0], instr
->const_index
[0]);
2953 case nir_intrinsic_end_primitive_with_counter
:
2954 emit_gs_end_primitive(instr
->src
[0]);
2957 case nir_intrinsic_set_vertex_count
:
2958 bld
.MOV(this->final_gs_vertex_count
, get_nir_src(instr
->src
[0]));
2961 case nir_intrinsic_load_invocation_id
: {
2962 fs_reg val
= nir_system_values
[SYSTEM_VALUE_INVOCATION_ID
];
2963 assert(val
.file
!= BAD_FILE
);
2964 dest
.type
= val
.type
;
2970 nir_emit_intrinsic(bld
, instr
);
2976 * Fetch the current render target layer index.
2979 fetch_render_target_array_index(const fs_builder
&bld
)
2981 if (bld
.shader
->devinfo
->gen
>= 6) {
2982 /* The render target array index is provided in the thread payload as
2983 * bits 26:16 of r0.0.
2985 const fs_reg idx
= bld
.vgrf(BRW_REGISTER_TYPE_UD
);
2986 bld
.AND(idx
, brw_uw1_reg(BRW_GENERAL_REGISTER_FILE
, 0, 1),
2990 /* Pre-SNB we only ever render into the first layer of the framebuffer
2991 * since layered rendering is not implemented.
2993 return brw_imm_ud(0);
2998 * Fake non-coherent framebuffer read implemented using TXF to fetch from the
2999 * framebuffer at the current fragment coordinates and sample index.
3002 fs_visitor::emit_non_coherent_fb_read(const fs_builder
&bld
, const fs_reg
&dst
,
3005 const struct gen_device_info
*devinfo
= bld
.shader
->devinfo
;
3007 assert(bld
.shader
->stage
== MESA_SHADER_FRAGMENT
);
3008 const brw_wm_prog_key
*wm_key
=
3009 reinterpret_cast<const brw_wm_prog_key
*>(key
);
3010 assert(!wm_key
->coherent_fb_fetch
);
3011 const struct brw_wm_prog_data
*wm_prog_data
=
3012 brw_wm_prog_data(stage_prog_data
);
3014 /* Calculate the surface index relative to the start of the texture binding
3015 * table block, since that's what the texturing messages expect.
3017 const unsigned surface
= target
+
3018 wm_prog_data
->binding_table
.render_target_read_start
-
3019 wm_prog_data
->base
.binding_table
.texture_start
;
3021 brw_mark_surface_used(
3022 bld
.shader
->stage_prog_data
,
3023 wm_prog_data
->binding_table
.render_target_read_start
+ target
);
3025 /* Calculate the fragment coordinates. */
3026 const fs_reg coords
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 3);
3027 bld
.MOV(offset(coords
, bld
, 0), pixel_x
);
3028 bld
.MOV(offset(coords
, bld
, 1), pixel_y
);
3029 bld
.MOV(offset(coords
, bld
, 2), fetch_render_target_array_index(bld
));
3031 /* Calculate the sample index and MCS payload when multisampling. Luckily
3032 * the MCS fetch message behaves deterministically for UMS surfaces, so it
3033 * shouldn't be necessary to recompile based on whether the framebuffer is
3036 if (wm_key
->multisample_fbo
&&
3037 nir_system_values
[SYSTEM_VALUE_SAMPLE_ID
].file
== BAD_FILE
)
3038 nir_system_values
[SYSTEM_VALUE_SAMPLE_ID
] = *emit_sampleid_setup();
3040 const fs_reg sample
= nir_system_values
[SYSTEM_VALUE_SAMPLE_ID
];
3041 const fs_reg mcs
= wm_key
->multisample_fbo
?
3042 emit_mcs_fetch(coords
, 3, brw_imm_ud(surface
)) : fs_reg();
3044 /* Use either a normal or a CMS texel fetch message depending on whether
3045 * the framebuffer is single or multisample. On SKL+ use the wide CMS
3046 * message just in case the framebuffer uses 16x multisampling, it should
3047 * be equivalent to the normal CMS fetch for lower multisampling modes.
3049 const opcode op
= !wm_key
->multisample_fbo
? SHADER_OPCODE_TXF_LOGICAL
:
3050 devinfo
->gen
>= 9 ? SHADER_OPCODE_TXF_CMS_W_LOGICAL
:
3051 SHADER_OPCODE_TXF_CMS_LOGICAL
;
3053 /* Emit the instruction. */
3054 const fs_reg srcs
[] = { coords
, fs_reg(), brw_imm_ud(0), fs_reg(),
3056 brw_imm_ud(surface
), brw_imm_ud(0),
3057 fs_reg(), brw_imm_ud(3), brw_imm_ud(0) };
3058 STATIC_ASSERT(ARRAY_SIZE(srcs
) == TEX_LOGICAL_NUM_SRCS
);
3060 fs_inst
*inst
= bld
.emit(op
, dst
, srcs
, ARRAY_SIZE(srcs
));
3061 inst
->size_written
= 4 * inst
->dst
.component_size(inst
->exec_size
);
3067 * Actual coherent framebuffer read implemented using the native render target
3068 * read message. Requires SKL+.
3071 emit_coherent_fb_read(const fs_builder
&bld
, const fs_reg
&dst
, unsigned target
)
3073 assert(bld
.shader
->devinfo
->gen
>= 9);
3074 fs_inst
*inst
= bld
.emit(FS_OPCODE_FB_READ_LOGICAL
, dst
);
3075 inst
->target
= target
;
3076 inst
->size_written
= 4 * inst
->dst
.component_size(inst
->exec_size
);
3082 alloc_temporary(const fs_builder
&bld
, unsigned size
, fs_reg
*regs
, unsigned n
)
3084 if (n
&& regs
[0].file
!= BAD_FILE
) {
3088 const fs_reg tmp
= bld
.vgrf(BRW_REGISTER_TYPE_F
, size
);
3090 for (unsigned i
= 0; i
< n
; i
++)
3098 alloc_frag_output(fs_visitor
*v
, unsigned location
)
3100 assert(v
->stage
== MESA_SHADER_FRAGMENT
);
3101 const brw_wm_prog_key
*const key
=
3102 reinterpret_cast<const brw_wm_prog_key
*>(v
->key
);
3103 const unsigned l
= GET_FIELD(location
, BRW_NIR_FRAG_OUTPUT_LOCATION
);
3104 const unsigned i
= GET_FIELD(location
, BRW_NIR_FRAG_OUTPUT_INDEX
);
3106 if (i
> 0 || (key
->force_dual_color_blend
&& l
== FRAG_RESULT_DATA1
))
3107 return alloc_temporary(v
->bld
, 4, &v
->dual_src_output
, 1);
3109 else if (l
== FRAG_RESULT_COLOR
)
3110 return alloc_temporary(v
->bld
, 4, v
->outputs
,
3111 MAX2(key
->nr_color_regions
, 1));
3113 else if (l
== FRAG_RESULT_DEPTH
)
3114 return alloc_temporary(v
->bld
, 1, &v
->frag_depth
, 1);
3116 else if (l
== FRAG_RESULT_STENCIL
)
3117 return alloc_temporary(v
->bld
, 1, &v
->frag_stencil
, 1);
3119 else if (l
== FRAG_RESULT_SAMPLE_MASK
)
3120 return alloc_temporary(v
->bld
, 1, &v
->sample_mask
, 1);
3122 else if (l
>= FRAG_RESULT_DATA0
&&
3123 l
< FRAG_RESULT_DATA0
+ BRW_MAX_DRAW_BUFFERS
)
3124 return alloc_temporary(v
->bld
, 4,
3125 &v
->outputs
[l
- FRAG_RESULT_DATA0
], 1);
3128 unreachable("Invalid location");
3132 fs_visitor::nir_emit_fs_intrinsic(const fs_builder
&bld
,
3133 nir_intrinsic_instr
*instr
)
3135 assert(stage
== MESA_SHADER_FRAGMENT
);
3138 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
3139 dest
= get_nir_dest(instr
->dest
);
3141 switch (instr
->intrinsic
) {
3142 case nir_intrinsic_load_front_face
:
3143 bld
.MOV(retype(dest
, BRW_REGISTER_TYPE_D
),
3144 *emit_frontfacing_interpolation());
3147 case nir_intrinsic_load_sample_pos
: {
3148 fs_reg sample_pos
= nir_system_values
[SYSTEM_VALUE_SAMPLE_POS
];
3149 assert(sample_pos
.file
!= BAD_FILE
);
3150 dest
.type
= sample_pos
.type
;
3151 bld
.MOV(dest
, sample_pos
);
3152 bld
.MOV(offset(dest
, bld
, 1), offset(sample_pos
, bld
, 1));
3156 case nir_intrinsic_load_layer_id
:
3157 dest
.type
= BRW_REGISTER_TYPE_UD
;
3158 bld
.MOV(dest
, fetch_render_target_array_index(bld
));
3161 case nir_intrinsic_load_helper_invocation
:
3162 case nir_intrinsic_load_sample_mask_in
:
3163 case nir_intrinsic_load_sample_id
: {
3164 gl_system_value sv
= nir_system_value_from_intrinsic(instr
->intrinsic
);
3165 fs_reg val
= nir_system_values
[sv
];
3166 assert(val
.file
!= BAD_FILE
);
3167 dest
.type
= val
.type
;
3172 case nir_intrinsic_store_output
: {
3173 const fs_reg src
= get_nir_src(instr
->src
[0]);
3174 const nir_const_value
*const_offset
= nir_src_as_const_value(instr
->src
[1]);
3175 assert(const_offset
&& "Indirect output stores not allowed");
3176 const unsigned location
= nir_intrinsic_base(instr
) +
3177 SET_FIELD(const_offset
->u32
[0], BRW_NIR_FRAG_OUTPUT_LOCATION
);
3178 const fs_reg new_dest
= retype(alloc_frag_output(this, location
),
3181 for (unsigned j
= 0; j
< instr
->num_components
; j
++)
3182 bld
.MOV(offset(new_dest
, bld
, nir_intrinsic_component(instr
) + j
),
3183 offset(src
, bld
, j
));
3188 case nir_intrinsic_load_output
: {
3189 const unsigned l
= GET_FIELD(nir_intrinsic_base(instr
),
3190 BRW_NIR_FRAG_OUTPUT_LOCATION
);
3191 assert(l
>= FRAG_RESULT_DATA0
);
3192 nir_const_value
*const_offset
= nir_src_as_const_value(instr
->src
[0]);
3193 assert(const_offset
&& "Indirect output loads not allowed");
3194 const unsigned target
= l
- FRAG_RESULT_DATA0
+ const_offset
->u32
[0];
3195 const fs_reg tmp
= bld
.vgrf(dest
.type
, 4);
3197 if (reinterpret_cast<const brw_wm_prog_key
*>(key
)->coherent_fb_fetch
)
3198 emit_coherent_fb_read(bld
, tmp
, target
);
3200 emit_non_coherent_fb_read(bld
, tmp
, target
);
3202 for (unsigned j
= 0; j
< instr
->num_components
; j
++) {
3203 bld
.MOV(offset(dest
, bld
, j
),
3204 offset(tmp
, bld
, nir_intrinsic_component(instr
) + j
));
3210 case nir_intrinsic_discard
:
3211 case nir_intrinsic_discard_if
: {
3212 /* We track our discarded pixels in f0.1. By predicating on it, we can
3213 * update just the flag bits that aren't yet discarded. If there's no
3214 * condition, we emit a CMP of g0 != g0, so all currently executing
3215 * channels will get turned off.
3218 if (instr
->intrinsic
== nir_intrinsic_discard_if
) {
3219 cmp
= bld
.CMP(bld
.null_reg_f(), get_nir_src(instr
->src
[0]),
3220 brw_imm_d(0), BRW_CONDITIONAL_Z
);
3222 fs_reg some_reg
= fs_reg(retype(brw_vec8_grf(0, 0),
3223 BRW_REGISTER_TYPE_UW
));
3224 cmp
= bld
.CMP(bld
.null_reg_f(), some_reg
, some_reg
, BRW_CONDITIONAL_NZ
);
3226 cmp
->predicate
= BRW_PREDICATE_NORMAL
;
3227 cmp
->flag_subreg
= 1;
3229 if (devinfo
->gen
>= 6) {
3230 emit_discard_jump();
3235 case nir_intrinsic_load_input
: {
3236 /* load_input is only used for flat inputs */
3237 unsigned base
= nir_intrinsic_base(instr
);
3238 unsigned component
= nir_intrinsic_component(instr
);
3239 unsigned num_components
= instr
->num_components
;
3240 enum brw_reg_type type
= dest
.type
;
3242 /* Special case fields in the VUE header */
3243 if (base
== VARYING_SLOT_LAYER
)
3245 else if (base
== VARYING_SLOT_VIEWPORT
)
3248 if (nir_dest_bit_size(instr
->dest
) == 64) {
3249 /* const_index is in 32-bit type size units that could not be aligned
3250 * with DF. We need to read the double vector as if it was a float
3251 * vector of twice the number of components to fetch the right data.
3253 type
= BRW_REGISTER_TYPE_F
;
3254 num_components
*= 2;
3257 for (unsigned int i
= 0; i
< num_components
; i
++) {
3258 struct brw_reg interp
= interp_reg(base
, component
+ i
);
3259 interp
= suboffset(interp
, 3);
3260 bld
.emit(FS_OPCODE_CINTERP
, offset(retype(dest
, type
), bld
, i
),
3261 retype(fs_reg(interp
), type
));
3264 if (nir_dest_bit_size(instr
->dest
) == 64) {
3265 shuffle_32bit_load_result_to_64bit_data(bld
,
3268 instr
->num_components
);
3273 case nir_intrinsic_load_barycentric_pixel
:
3274 case nir_intrinsic_load_barycentric_centroid
:
3275 case nir_intrinsic_load_barycentric_sample
:
3276 /* Do nothing - load_interpolated_input handling will handle it later. */
3279 case nir_intrinsic_load_barycentric_at_sample
: {
3280 const glsl_interp_mode interpolation
=
3281 (enum glsl_interp_mode
) nir_intrinsic_interp_mode(instr
);
3283 nir_const_value
*const_sample
= nir_src_as_const_value(instr
->src
[0]);
3286 unsigned msg_data
= const_sample
->i32
[0] << 4;
3288 emit_pixel_interpolater_send(bld
,
3289 FS_OPCODE_INTERPOLATE_AT_SAMPLE
,
3292 brw_imm_ud(msg_data
),
3295 const fs_reg sample_src
= retype(get_nir_src(instr
->src
[0]),
3296 BRW_REGISTER_TYPE_UD
);
3298 if (nir_src_is_dynamically_uniform(instr
->src
[0])) {
3299 const fs_reg sample_id
= bld
.emit_uniformize(sample_src
);
3300 const fs_reg msg_data
= vgrf(glsl_type::uint_type
);
3301 bld
.exec_all().group(1, 0)
3302 .SHL(msg_data
, sample_id
, brw_imm_ud(4u));
3303 emit_pixel_interpolater_send(bld
,
3304 FS_OPCODE_INTERPOLATE_AT_SAMPLE
,
3310 /* Make a loop that sends a message to the pixel interpolater
3311 * for the sample number in each live channel. If there are
3312 * multiple channels with the same sample number then these
3313 * will be handled simultaneously with a single interation of
3316 bld
.emit(BRW_OPCODE_DO
);
3318 /* Get the next live sample number into sample_id_reg */
3319 const fs_reg sample_id
= bld
.emit_uniformize(sample_src
);
3321 /* Set the flag register so that we can perform the send
3322 * message on all channels that have the same sample number
3324 bld
.CMP(bld
.null_reg_ud(),
3325 sample_src
, sample_id
,
3326 BRW_CONDITIONAL_EQ
);
3327 const fs_reg msg_data
= vgrf(glsl_type::uint_type
);
3328 bld
.exec_all().group(1, 0)
3329 .SHL(msg_data
, sample_id
, brw_imm_ud(4u));
3331 emit_pixel_interpolater_send(bld
,
3332 FS_OPCODE_INTERPOLATE_AT_SAMPLE
,
3337 set_predicate(BRW_PREDICATE_NORMAL
, inst
);
3339 /* Continue the loop if there are any live channels left */
3340 set_predicate_inv(BRW_PREDICATE_NORMAL
,
3342 bld
.emit(BRW_OPCODE_WHILE
));
3348 case nir_intrinsic_load_barycentric_at_offset
: {
3349 const glsl_interp_mode interpolation
=
3350 (enum glsl_interp_mode
) nir_intrinsic_interp_mode(instr
);
3352 nir_const_value
*const_offset
= nir_src_as_const_value(instr
->src
[0]);
3355 unsigned off_x
= MIN2((int)(const_offset
->f32
[0] * 16), 7) & 0xf;
3356 unsigned off_y
= MIN2((int)(const_offset
->f32
[1] * 16), 7) & 0xf;
3358 emit_pixel_interpolater_send(bld
,
3359 FS_OPCODE_INTERPOLATE_AT_SHARED_OFFSET
,
3362 brw_imm_ud(off_x
| (off_y
<< 4)),
3365 fs_reg src
= vgrf(glsl_type::ivec2_type
);
3366 fs_reg offset_src
= retype(get_nir_src(instr
->src
[0]),
3367 BRW_REGISTER_TYPE_F
);
3368 for (int i
= 0; i
< 2; i
++) {
3369 fs_reg temp
= vgrf(glsl_type::float_type
);
3370 bld
.MUL(temp
, offset(offset_src
, bld
, i
), brw_imm_f(16.0f
));
3371 fs_reg itemp
= vgrf(glsl_type::int_type
);
3373 bld
.MOV(itemp
, temp
);
3375 /* Clamp the upper end of the range to +7/16.
3376 * ARB_gpu_shader5 requires that we support a maximum offset
3377 * of +0.5, which isn't representable in a S0.4 value -- if
3378 * we didn't clamp it, we'd end up with -8/16, which is the
3379 * opposite of what the shader author wanted.
3381 * This is legal due to ARB_gpu_shader5's quantization
3384 * "Not all values of <offset> may be supported; x and y
3385 * offsets may be rounded to fixed-point values with the
3386 * number of fraction bits given by the
3387 * implementation-dependent constant
3388 * FRAGMENT_INTERPOLATION_OFFSET_BITS"
3390 set_condmod(BRW_CONDITIONAL_L
,
3391 bld
.SEL(offset(src
, bld
, i
), itemp
, brw_imm_d(7)));
3394 const enum opcode opcode
= FS_OPCODE_INTERPOLATE_AT_PER_SLOT_OFFSET
;
3395 emit_pixel_interpolater_send(bld
,
3405 case nir_intrinsic_load_interpolated_input
: {
3406 if (nir_intrinsic_base(instr
) == VARYING_SLOT_POS
) {
3407 emit_fragcoord_interpolation(dest
);
3411 assert(instr
->src
[0].ssa
&&
3412 instr
->src
[0].ssa
->parent_instr
->type
== nir_instr_type_intrinsic
);
3413 nir_intrinsic_instr
*bary_intrinsic
=
3414 nir_instr_as_intrinsic(instr
->src
[0].ssa
->parent_instr
);
3415 nir_intrinsic_op bary_intrin
= bary_intrinsic
->intrinsic
;
3416 enum glsl_interp_mode interp_mode
=
3417 (enum glsl_interp_mode
) nir_intrinsic_interp_mode(bary_intrinsic
);
3420 if (bary_intrin
== nir_intrinsic_load_barycentric_at_offset
||
3421 bary_intrin
== nir_intrinsic_load_barycentric_at_sample
) {
3422 /* Use the result of the PI message */
3423 dst_xy
= retype(get_nir_src(instr
->src
[0]), BRW_REGISTER_TYPE_F
);
3425 /* Use the delta_xy values computed from the payload */
3426 enum brw_barycentric_mode bary
=
3427 brw_barycentric_mode(interp_mode
, bary_intrin
);
3429 dst_xy
= this->delta_xy
[bary
];
3432 for (unsigned int i
= 0; i
< instr
->num_components
; i
++) {
3434 fs_reg(interp_reg(nir_intrinsic_base(instr
),
3435 nir_intrinsic_component(instr
) + i
));
3436 interp
.type
= BRW_REGISTER_TYPE_F
;
3437 dest
.type
= BRW_REGISTER_TYPE_F
;
3439 if (devinfo
->gen
< 6 && interp_mode
== INTERP_MODE_SMOOTH
) {
3440 fs_reg tmp
= vgrf(glsl_type::float_type
);
3441 bld
.emit(FS_OPCODE_LINTERP
, tmp
, dst_xy
, interp
);
3442 bld
.MUL(offset(dest
, bld
, i
), tmp
, this->pixel_w
);
3444 bld
.emit(FS_OPCODE_LINTERP
, offset(dest
, bld
, i
), dst_xy
, interp
);
3451 nir_emit_intrinsic(bld
, instr
);
3457 fs_visitor::nir_emit_cs_intrinsic(const fs_builder
&bld
,
3458 nir_intrinsic_instr
*instr
)
3460 assert(stage
== MESA_SHADER_COMPUTE
);
3461 struct brw_cs_prog_data
*cs_prog_data
= brw_cs_prog_data(prog_data
);
3464 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
3465 dest
= get_nir_dest(instr
->dest
);
3467 switch (instr
->intrinsic
) {
3468 case nir_intrinsic_barrier
:
3470 cs_prog_data
->uses_barrier
= true;
3473 case nir_intrinsic_load_subgroup_id
:
3474 bld
.MOV(retype(dest
, BRW_REGISTER_TYPE_UD
), subgroup_id
);
3477 case nir_intrinsic_load_local_invocation_id
:
3478 case nir_intrinsic_load_work_group_id
: {
3479 gl_system_value sv
= nir_system_value_from_intrinsic(instr
->intrinsic
);
3480 fs_reg val
= nir_system_values
[sv
];
3481 assert(val
.file
!= BAD_FILE
);
3482 dest
.type
= val
.type
;
3483 for (unsigned i
= 0; i
< 3; i
++)
3484 bld
.MOV(offset(dest
, bld
, i
), offset(val
, bld
, i
));
3488 case nir_intrinsic_load_num_work_groups
: {
3489 const unsigned surface
=
3490 cs_prog_data
->binding_table
.work_groups_start
;
3492 cs_prog_data
->uses_num_work_groups
= true;
3494 fs_reg surf_index
= brw_imm_ud(surface
);
3495 brw_mark_surface_used(prog_data
, surface
);
3497 /* Read the 3 GLuint components of gl_NumWorkGroups */
3498 for (unsigned i
= 0; i
< 3; i
++) {
3499 fs_reg read_result
=
3500 emit_untyped_read(bld
, surf_index
,
3502 1 /* dims */, 1 /* size */,
3503 BRW_PREDICATE_NONE
);
3504 read_result
.type
= dest
.type
;
3505 bld
.MOV(dest
, read_result
);
3506 dest
= offset(dest
, bld
, 1);
3511 case nir_intrinsic_shared_atomic_add
:
3512 nir_emit_shared_atomic(bld
, BRW_AOP_ADD
, instr
);
3514 case nir_intrinsic_shared_atomic_imin
:
3515 nir_emit_shared_atomic(bld
, BRW_AOP_IMIN
, instr
);
3517 case nir_intrinsic_shared_atomic_umin
:
3518 nir_emit_shared_atomic(bld
, BRW_AOP_UMIN
, instr
);
3520 case nir_intrinsic_shared_atomic_imax
:
3521 nir_emit_shared_atomic(bld
, BRW_AOP_IMAX
, instr
);
3523 case nir_intrinsic_shared_atomic_umax
:
3524 nir_emit_shared_atomic(bld
, BRW_AOP_UMAX
, instr
);
3526 case nir_intrinsic_shared_atomic_and
:
3527 nir_emit_shared_atomic(bld
, BRW_AOP_AND
, instr
);
3529 case nir_intrinsic_shared_atomic_or
:
3530 nir_emit_shared_atomic(bld
, BRW_AOP_OR
, instr
);
3532 case nir_intrinsic_shared_atomic_xor
:
3533 nir_emit_shared_atomic(bld
, BRW_AOP_XOR
, instr
);
3535 case nir_intrinsic_shared_atomic_exchange
:
3536 nir_emit_shared_atomic(bld
, BRW_AOP_MOV
, instr
);
3538 case nir_intrinsic_shared_atomic_comp_swap
:
3539 nir_emit_shared_atomic(bld
, BRW_AOP_CMPWR
, instr
);
3542 case nir_intrinsic_load_shared
: {
3543 assert(devinfo
->gen
>= 7);
3545 fs_reg surf_index
= brw_imm_ud(GEN7_BTI_SLM
);
3547 /* Get the offset to read from */
3549 nir_const_value
*const_offset
= nir_src_as_const_value(instr
->src
[0]);
3551 offset_reg
= brw_imm_ud(instr
->const_index
[0] + const_offset
->u32
[0]);
3553 offset_reg
= vgrf(glsl_type::uint_type
);
3555 retype(get_nir_src(instr
->src
[0]), BRW_REGISTER_TYPE_UD
),
3556 brw_imm_ud(instr
->const_index
[0]));
3559 /* Read the vector */
3560 do_untyped_vector_read(bld
, dest
, surf_index
, offset_reg
,
3561 instr
->num_components
);
3565 case nir_intrinsic_store_shared
: {
3566 assert(devinfo
->gen
>= 7);
3569 fs_reg surf_index
= brw_imm_ud(GEN7_BTI_SLM
);
3572 fs_reg val_reg
= get_nir_src(instr
->src
[0]);
3575 unsigned writemask
= instr
->const_index
[1];
3577 /* get_nir_src() retypes to integer. Be wary of 64-bit types though
3578 * since the untyped writes below operate in units of 32-bits, which
3579 * means that we need to write twice as many components each time.
3580 * Also, we have to suffle 64-bit data to be in the appropriate layout
3581 * expected by our 32-bit write messages.
3583 unsigned type_size
= 4;
3584 if (nir_src_bit_size(instr
->src
[0]) == 64) {
3586 val_reg
= shuffle_64bit_data_for_32bit_write(bld
,
3587 val_reg
, instr
->num_components
);
3590 unsigned type_slots
= type_size
/ 4;
3592 /* Combine groups of consecutive enabled channels in one write
3593 * message. We use ffs to find the first enabled channel and then ffs on
3594 * the bit-inverse, down-shifted writemask to determine the length of
3595 * the block of enabled bits.
3598 unsigned first_component
= ffs(writemask
) - 1;
3599 unsigned length
= ffs(~(writemask
>> first_component
)) - 1;
3601 /* We can't write more than 2 64-bit components at once. Limit the
3602 * length of the write to what we can do and let the next iteration
3606 length
= MIN2(2, length
);
3609 nir_const_value
*const_offset
= nir_src_as_const_value(instr
->src
[1]);
3611 offset_reg
= brw_imm_ud(instr
->const_index
[0] + const_offset
->u32
[0] +
3612 type_size
* first_component
);
3614 offset_reg
= vgrf(glsl_type::uint_type
);
3616 retype(get_nir_src(instr
->src
[1]), BRW_REGISTER_TYPE_UD
),
3617 brw_imm_ud(instr
->const_index
[0] + type_size
* first_component
));
3620 emit_untyped_write(bld
, surf_index
, offset_reg
,
3621 offset(val_reg
, bld
, first_component
* type_slots
),
3622 1 /* dims */, length
* type_slots
,
3623 BRW_PREDICATE_NONE
);
3625 /* Clear the bits in the writemask that we just wrote, then try
3626 * again to see if more channels are left.
3628 writemask
&= (15 << (first_component
+ length
));
3635 nir_emit_intrinsic(bld
, instr
);
3641 fs_visitor::nir_emit_intrinsic(const fs_builder
&bld
, nir_intrinsic_instr
*instr
)
3644 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
3645 dest
= get_nir_dest(instr
->dest
);
3647 switch (instr
->intrinsic
) {
3648 case nir_intrinsic_image_load
:
3649 case nir_intrinsic_image_store
:
3650 case nir_intrinsic_image_atomic_add
:
3651 case nir_intrinsic_image_atomic_min
:
3652 case nir_intrinsic_image_atomic_max
:
3653 case nir_intrinsic_image_atomic_and
:
3654 case nir_intrinsic_image_atomic_or
:
3655 case nir_intrinsic_image_atomic_xor
:
3656 case nir_intrinsic_image_atomic_exchange
:
3657 case nir_intrinsic_image_atomic_comp_swap
: {
3658 using namespace image_access
;
3660 if (stage
== MESA_SHADER_FRAGMENT
&&
3661 instr
->intrinsic
!= nir_intrinsic_image_load
)
3662 brw_wm_prog_data(prog_data
)->has_side_effects
= true;
3664 /* Get the referenced image variable and type. */
3665 const nir_variable
*var
= instr
->variables
[0]->var
;
3666 const glsl_type
*type
= var
->type
->without_array();
3667 const brw_reg_type base_type
= get_image_base_type(type
);
3669 /* Get some metadata from the image intrinsic. */
3670 const nir_intrinsic_info
*info
= &nir_intrinsic_infos
[instr
->intrinsic
];
3671 const unsigned arr_dims
= type
->sampler_array
? 1 : 0;
3672 const unsigned surf_dims
= type
->coordinate_components() - arr_dims
;
3673 const unsigned format
= var
->data
.image
.format
;
3675 /* Get the arguments of the image intrinsic. */
3676 const fs_reg image
= get_nir_image_deref(instr
->variables
[0]);
3677 const fs_reg addr
= retype(get_nir_src(instr
->src
[0]),
3678 BRW_REGISTER_TYPE_UD
);
3679 const fs_reg src0
= (info
->num_srcs
>= 3 ?
3680 retype(get_nir_src(instr
->src
[2]), base_type
) :
3682 const fs_reg src1
= (info
->num_srcs
>= 4 ?
3683 retype(get_nir_src(instr
->src
[3]), base_type
) :
3687 /* Emit an image load, store or atomic op. */
3688 if (instr
->intrinsic
== nir_intrinsic_image_load
)
3689 tmp
= emit_image_load(bld
, image
, addr
, surf_dims
, arr_dims
, format
);
3691 else if (instr
->intrinsic
== nir_intrinsic_image_store
)
3692 emit_image_store(bld
, image
, addr
, src0
, surf_dims
, arr_dims
,
3693 var
->data
.image
.write_only
? GL_NONE
: format
);
3696 tmp
= emit_image_atomic(bld
, image
, addr
, src0
, src1
,
3697 surf_dims
, arr_dims
, info
->dest_components
,
3698 get_image_atomic_op(instr
->intrinsic
, type
));
3700 /* Assign the result. */
3701 for (unsigned c
= 0; c
< info
->dest_components
; ++c
)
3702 bld
.MOV(offset(retype(dest
, base_type
), bld
, c
),
3703 offset(tmp
, bld
, c
));
3707 case nir_intrinsic_memory_barrier_atomic_counter
:
3708 case nir_intrinsic_memory_barrier_buffer
:
3709 case nir_intrinsic_memory_barrier_image
:
3710 case nir_intrinsic_memory_barrier
: {
3711 const fs_builder ubld
= bld
.group(8, 0);
3712 const fs_reg tmp
= ubld
.vgrf(BRW_REGISTER_TYPE_UD
, 2);
3713 ubld
.emit(SHADER_OPCODE_MEMORY_FENCE
, tmp
)
3714 ->size_written
= 2 * REG_SIZE
;
3718 case nir_intrinsic_group_memory_barrier
:
3719 case nir_intrinsic_memory_barrier_shared
:
3720 /* We treat these workgroup-level barriers as no-ops. This should be
3721 * safe at present and as long as:
3723 * - Memory access instructions are not subsequently reordered by the
3724 * compiler back-end.
3726 * - All threads from a given compute shader workgroup fit within a
3727 * single subslice and therefore talk to the same HDC shared unit
3728 * what supposedly guarantees ordering and coherency between threads
3729 * from the same workgroup. This may change in the future when we
3730 * start splitting workgroups across multiple subslices.
3732 * - The context is not in fault-and-stream mode, which could cause
3733 * memory transactions (including to SLM) prior to the barrier to be
3734 * replayed after the barrier if a pagefault occurs. This shouldn't
3735 * be a problem up to and including SKL because fault-and-stream is
3736 * not usable due to hardware issues, but that's likely to change in
3741 case nir_intrinsic_shader_clock
: {
3742 /* We cannot do anything if there is an event, so ignore it for now */
3743 const fs_reg shader_clock
= get_timestamp(bld
);
3744 const fs_reg srcs
[] = { component(shader_clock
, 0),
3745 component(shader_clock
, 1) };
3746 bld
.LOAD_PAYLOAD(dest
, srcs
, ARRAY_SIZE(srcs
), 0);
3750 case nir_intrinsic_image_size
: {
3751 /* Get the referenced image variable and type. */
3752 const nir_variable
*var
= instr
->variables
[0]->var
;
3753 const glsl_type
*type
= var
->type
->without_array();
3755 /* Get the size of the image. */
3756 const fs_reg image
= get_nir_image_deref(instr
->variables
[0]);
3757 const fs_reg size
= offset(image
, bld
, BRW_IMAGE_PARAM_SIZE_OFFSET
);
3759 /* For 1DArray image types, the array index is stored in the Z component.
3760 * Fix this by swizzling the Z component to the Y component.
3762 const bool is_1d_array_image
=
3763 type
->sampler_dimensionality
== GLSL_SAMPLER_DIM_1D
&&
3764 type
->sampler_array
;
3766 /* For CubeArray images, we should count the number of cubes instead
3767 * of the number of faces. Fix it by dividing the (Z component) by 6.
3769 const bool is_cube_array_image
=
3770 type
->sampler_dimensionality
== GLSL_SAMPLER_DIM_CUBE
&&
3771 type
->sampler_array
;
3773 /* Copy all the components. */
3774 for (unsigned c
= 0; c
< instr
->dest
.ssa
.num_components
; ++c
) {
3775 if ((int)c
>= type
->coordinate_components()) {
3776 bld
.MOV(offset(retype(dest
, BRW_REGISTER_TYPE_D
), bld
, c
),
3778 } else if (c
== 1 && is_1d_array_image
) {
3779 bld
.MOV(offset(retype(dest
, BRW_REGISTER_TYPE_D
), bld
, c
),
3780 offset(size
, bld
, 2));
3781 } else if (c
== 2 && is_cube_array_image
) {
3782 bld
.emit(SHADER_OPCODE_INT_QUOTIENT
,
3783 offset(retype(dest
, BRW_REGISTER_TYPE_D
), bld
, c
),
3784 offset(size
, bld
, c
), brw_imm_d(6));
3786 bld
.MOV(offset(retype(dest
, BRW_REGISTER_TYPE_D
), bld
, c
),
3787 offset(size
, bld
, c
));
3794 case nir_intrinsic_image_samples
:
3795 /* The driver does not support multi-sampled images. */
3796 bld
.MOV(retype(dest
, BRW_REGISTER_TYPE_D
), brw_imm_d(1));
3799 case nir_intrinsic_load_uniform
: {
3800 /* Offsets are in bytes but they should always be multiples of 4 */
3801 assert(instr
->const_index
[0] % 4 == 0);
3803 fs_reg
src(UNIFORM
, instr
->const_index
[0] / 4, dest
.type
);
3805 nir_const_value
*const_offset
= nir_src_as_const_value(instr
->src
[0]);
3807 /* Offsets are in bytes but they should always be multiples of 4 */
3808 assert(const_offset
->u32
[0] % 4 == 0);
3809 src
.offset
= const_offset
->u32
[0];
3811 for (unsigned j
= 0; j
< instr
->num_components
; j
++) {
3812 bld
.MOV(offset(dest
, bld
, j
), offset(src
, bld
, j
));
3815 fs_reg indirect
= retype(get_nir_src(instr
->src
[0]),
3816 BRW_REGISTER_TYPE_UD
);
3818 /* We need to pass a size to the MOV_INDIRECT but we don't want it to
3819 * go past the end of the uniform. In order to keep the n'th
3820 * component from running past, we subtract off the size of all but
3821 * one component of the vector.
3823 assert(instr
->const_index
[1] >=
3824 instr
->num_components
* (int) type_sz(dest
.type
));
3825 unsigned read_size
= instr
->const_index
[1] -
3826 (instr
->num_components
- 1) * type_sz(dest
.type
);
3828 bool supports_64bit_indirects
=
3829 !devinfo
->is_cherryview
&& !gen_device_info_is_9lp(devinfo
);
3831 if (type_sz(dest
.type
) != 8 || supports_64bit_indirects
) {
3832 for (unsigned j
= 0; j
< instr
->num_components
; j
++) {
3833 bld
.emit(SHADER_OPCODE_MOV_INDIRECT
,
3834 offset(dest
, bld
, j
), offset(src
, bld
, j
),
3835 indirect
, brw_imm_ud(read_size
));
3838 const unsigned num_mov_indirects
=
3839 type_sz(dest
.type
) / type_sz(BRW_REGISTER_TYPE_UD
);
3840 /* We read a little bit less per MOV INDIRECT, as they are now
3841 * 32-bits ones instead of 64-bit. Fix read_size then.
3843 const unsigned read_size_32bit
= read_size
-
3844 (num_mov_indirects
- 1) * type_sz(BRW_REGISTER_TYPE_UD
);
3845 for (unsigned j
= 0; j
< instr
->num_components
; j
++) {
3846 for (unsigned i
= 0; i
< num_mov_indirects
; i
++) {
3847 bld
.emit(SHADER_OPCODE_MOV_INDIRECT
,
3848 subscript(offset(dest
, bld
, j
), BRW_REGISTER_TYPE_UD
, i
),
3849 subscript(offset(src
, bld
, j
), BRW_REGISTER_TYPE_UD
, i
),
3850 indirect
, brw_imm_ud(read_size_32bit
));
3858 case nir_intrinsic_load_ubo
: {
3859 nir_const_value
*const_index
= nir_src_as_const_value(instr
->src
[0]);
3863 const unsigned index
= stage_prog_data
->binding_table
.ubo_start
+
3864 const_index
->u32
[0];
3865 surf_index
= brw_imm_ud(index
);
3866 brw_mark_surface_used(prog_data
, index
);
3868 /* The block index is not a constant. Evaluate the index expression
3869 * per-channel and add the base UBO index; we have to select a value
3870 * from any live channel.
3872 surf_index
= vgrf(glsl_type::uint_type
);
3873 bld
.ADD(surf_index
, get_nir_src(instr
->src
[0]),
3874 brw_imm_ud(stage_prog_data
->binding_table
.ubo_start
));
3875 surf_index
= bld
.emit_uniformize(surf_index
);
3877 /* Assume this may touch any UBO. It would be nice to provide
3878 * a tighter bound, but the array information is already lowered away.
3880 brw_mark_surface_used(prog_data
,
3881 stage_prog_data
->binding_table
.ubo_start
+
3882 nir
->info
.num_ubos
- 1);
3885 nir_const_value
*const_offset
= nir_src_as_const_value(instr
->src
[1]);
3886 if (const_offset
== NULL
) {
3887 fs_reg base_offset
= retype(get_nir_src(instr
->src
[1]),
3888 BRW_REGISTER_TYPE_UD
);
3890 for (int i
= 0; i
< instr
->num_components
; i
++)
3891 VARYING_PULL_CONSTANT_LOAD(bld
, offset(dest
, bld
, i
), surf_index
,
3892 base_offset
, i
* type_sz(dest
.type
));
3894 /* Even if we are loading doubles, a pull constant load will load
3895 * a 32-bit vec4, so should only reserve vgrf space for that. If we
3896 * need to load a full dvec4 we will have to emit 2 loads. This is
3897 * similar to demote_pull_constants(), except that in that case we
3898 * see individual accesses to each component of the vector and then
3899 * we let CSE deal with duplicate loads. Here we see a vector access
3900 * and we have to split it if necessary.
3902 const unsigned type_size
= type_sz(dest
.type
);
3904 /* See if we've selected this as a push constant candidate */
3906 const unsigned ubo_block
= const_index
->u32
[0];
3907 const unsigned offset_256b
= const_offset
->u32
[0] / 32;
3910 for (int i
= 0; i
< 4; i
++) {
3911 const struct brw_ubo_range
*range
= &prog_data
->ubo_ranges
[i
];
3912 if (range
->block
== ubo_block
&&
3913 offset_256b
>= range
->start
&&
3914 offset_256b
< range
->start
+ range
->length
) {
3916 push_reg
= fs_reg(UNIFORM
, UBO_START
+ i
, dest
.type
);
3917 push_reg
.offset
= const_offset
->u32
[0] - 32 * range
->start
;
3922 if (push_reg
.file
!= BAD_FILE
) {
3923 for (unsigned i
= 0; i
< instr
->num_components
; i
++) {
3924 bld
.MOV(offset(dest
, bld
, i
),
3925 byte_offset(push_reg
, i
* type_size
));
3931 const unsigned block_sz
= 64; /* Fetch one cacheline at a time. */
3932 const fs_builder ubld
= bld
.exec_all().group(block_sz
/ 4, 0);
3933 const fs_reg packed_consts
= ubld
.vgrf(BRW_REGISTER_TYPE_UD
);
3935 for (unsigned c
= 0; c
< instr
->num_components
;) {
3936 const unsigned base
= const_offset
->u32
[0] + c
* type_size
;
3937 /* Number of usable components in the next block-aligned load. */
3938 const unsigned count
= MIN2(instr
->num_components
- c
,
3939 (block_sz
- base
% block_sz
) / type_size
);
3941 ubld
.emit(FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD
,
3942 packed_consts
, surf_index
,
3943 brw_imm_ud(base
& ~(block_sz
- 1)));
3945 const fs_reg consts
=
3946 retype(byte_offset(packed_consts
, base
& (block_sz
- 1)),
3949 for (unsigned d
= 0; d
< count
; d
++)
3950 bld
.MOV(offset(dest
, bld
, c
+ d
), component(consts
, d
));
3958 case nir_intrinsic_load_ssbo
: {
3959 assert(devinfo
->gen
>= 7);
3961 nir_const_value
*const_uniform_block
=
3962 nir_src_as_const_value(instr
->src
[0]);
3965 if (const_uniform_block
) {
3966 unsigned index
= stage_prog_data
->binding_table
.ssbo_start
+
3967 const_uniform_block
->u32
[0];
3968 surf_index
= brw_imm_ud(index
);
3969 brw_mark_surface_used(prog_data
, index
);
3971 surf_index
= vgrf(glsl_type::uint_type
);
3972 bld
.ADD(surf_index
, get_nir_src(instr
->src
[0]),
3973 brw_imm_ud(stage_prog_data
->binding_table
.ssbo_start
));
3975 /* Assume this may touch any UBO. It would be nice to provide
3976 * a tighter bound, but the array information is already lowered away.
3978 brw_mark_surface_used(prog_data
,
3979 stage_prog_data
->binding_table
.ssbo_start
+
3980 nir
->info
.num_ssbos
- 1);
3984 nir_const_value
*const_offset
= nir_src_as_const_value(instr
->src
[1]);
3986 offset_reg
= brw_imm_ud(const_offset
->u32
[0]);
3988 offset_reg
= get_nir_src(instr
->src
[1]);
3991 /* Read the vector */
3992 do_untyped_vector_read(bld
, dest
, surf_index
, offset_reg
,
3993 instr
->num_components
);
3998 case nir_intrinsic_store_ssbo
: {
3999 assert(devinfo
->gen
>= 7);
4001 if (stage
== MESA_SHADER_FRAGMENT
)
4002 brw_wm_prog_data(prog_data
)->has_side_effects
= true;
4006 nir_const_value
*const_uniform_block
=
4007 nir_src_as_const_value(instr
->src
[1]);
4008 if (const_uniform_block
) {
4009 unsigned index
= stage_prog_data
->binding_table
.ssbo_start
+
4010 const_uniform_block
->u32
[0];
4011 surf_index
= brw_imm_ud(index
);
4012 brw_mark_surface_used(prog_data
, index
);
4014 surf_index
= vgrf(glsl_type::uint_type
);
4015 bld
.ADD(surf_index
, get_nir_src(instr
->src
[1]),
4016 brw_imm_ud(stage_prog_data
->binding_table
.ssbo_start
));
4018 brw_mark_surface_used(prog_data
,
4019 stage_prog_data
->binding_table
.ssbo_start
+
4020 nir
->info
.num_ssbos
- 1);
4024 fs_reg val_reg
= get_nir_src(instr
->src
[0]);
4027 unsigned writemask
= instr
->const_index
[0];
4029 /* get_nir_src() retypes to integer. Be wary of 64-bit types though
4030 * since the untyped writes below operate in units of 32-bits, which
4031 * means that we need to write twice as many components each time.
4032 * Also, we have to suffle 64-bit data to be in the appropriate layout
4033 * expected by our 32-bit write messages.
4035 unsigned type_size
= 4;
4036 if (nir_src_bit_size(instr
->src
[0]) == 64) {
4038 val_reg
= shuffle_64bit_data_for_32bit_write(bld
,
4039 val_reg
, instr
->num_components
);
4042 unsigned type_slots
= type_size
/ 4;
4044 /* Combine groups of consecutive enabled channels in one write
4045 * message. We use ffs to find the first enabled channel and then ffs on
4046 * the bit-inverse, down-shifted writemask to determine the length of
4047 * the block of enabled bits.
4050 unsigned first_component
= ffs(writemask
) - 1;
4051 unsigned length
= ffs(~(writemask
>> first_component
)) - 1;
4053 /* We can't write more than 2 64-bit components at once. Limit the
4054 * length of the write to what we can do and let the next iteration
4058 length
= MIN2(2, length
);
4061 nir_const_value
*const_offset
= nir_src_as_const_value(instr
->src
[2]);
4063 offset_reg
= brw_imm_ud(const_offset
->u32
[0] +
4064 type_size
* first_component
);
4066 offset_reg
= vgrf(glsl_type::uint_type
);
4068 retype(get_nir_src(instr
->src
[2]), BRW_REGISTER_TYPE_UD
),
4069 brw_imm_ud(type_size
* first_component
));
4073 emit_untyped_write(bld
, surf_index
, offset_reg
,
4074 offset(val_reg
, bld
, first_component
* type_slots
),
4075 1 /* dims */, length
* type_slots
,
4076 BRW_PREDICATE_NONE
);
4078 /* Clear the bits in the writemask that we just wrote, then try
4079 * again to see if more channels are left.
4081 writemask
&= (15 << (first_component
+ length
));
4086 case nir_intrinsic_store_output
: {
4087 fs_reg src
= get_nir_src(instr
->src
[0]);
4089 nir_const_value
*const_offset
= nir_src_as_const_value(instr
->src
[1]);
4090 assert(const_offset
&& "Indirect output stores not allowed");
4092 unsigned num_components
= instr
->num_components
;
4093 unsigned first_component
= nir_intrinsic_component(instr
);
4094 if (nir_src_bit_size(instr
->src
[0]) == 64) {
4095 src
= shuffle_64bit_data_for_32bit_write(bld
, src
, num_components
);
4096 num_components
*= 2;
4099 fs_reg new_dest
= retype(offset(outputs
[instr
->const_index
[0]], bld
,
4100 4 * const_offset
->u32
[0]), src
.type
);
4101 for (unsigned j
= 0; j
< num_components
; j
++) {
4102 bld
.MOV(offset(new_dest
, bld
, j
+ first_component
),
4103 offset(src
, bld
, j
));
4108 case nir_intrinsic_ssbo_atomic_add
:
4109 nir_emit_ssbo_atomic(bld
, BRW_AOP_ADD
, instr
);
4111 case nir_intrinsic_ssbo_atomic_imin
:
4112 nir_emit_ssbo_atomic(bld
, BRW_AOP_IMIN
, instr
);
4114 case nir_intrinsic_ssbo_atomic_umin
:
4115 nir_emit_ssbo_atomic(bld
, BRW_AOP_UMIN
, instr
);
4117 case nir_intrinsic_ssbo_atomic_imax
:
4118 nir_emit_ssbo_atomic(bld
, BRW_AOP_IMAX
, instr
);
4120 case nir_intrinsic_ssbo_atomic_umax
:
4121 nir_emit_ssbo_atomic(bld
, BRW_AOP_UMAX
, instr
);
4123 case nir_intrinsic_ssbo_atomic_and
:
4124 nir_emit_ssbo_atomic(bld
, BRW_AOP_AND
, instr
);
4126 case nir_intrinsic_ssbo_atomic_or
:
4127 nir_emit_ssbo_atomic(bld
, BRW_AOP_OR
, instr
);
4129 case nir_intrinsic_ssbo_atomic_xor
:
4130 nir_emit_ssbo_atomic(bld
, BRW_AOP_XOR
, instr
);
4132 case nir_intrinsic_ssbo_atomic_exchange
:
4133 nir_emit_ssbo_atomic(bld
, BRW_AOP_MOV
, instr
);
4135 case nir_intrinsic_ssbo_atomic_comp_swap
:
4136 nir_emit_ssbo_atomic(bld
, BRW_AOP_CMPWR
, instr
);
4139 case nir_intrinsic_get_buffer_size
: {
4140 nir_const_value
*const_uniform_block
= nir_src_as_const_value(instr
->src
[0]);
4141 unsigned ssbo_index
= const_uniform_block
? const_uniform_block
->u32
[0] : 0;
4143 /* A resinfo's sampler message is used to get the buffer size. The
4144 * SIMD8's writeback message consists of four registers and SIMD16's
4145 * writeback message consists of 8 destination registers (two per each
4146 * component). Because we are only interested on the first channel of
4147 * the first returned component, where resinfo returns the buffer size
4148 * for SURFTYPE_BUFFER, we can just use the SIMD8 variant regardless of
4149 * the dispatch width.
4151 const fs_builder ubld
= bld
.exec_all().group(8, 0);
4152 fs_reg src_payload
= ubld
.vgrf(BRW_REGISTER_TYPE_UD
);
4153 fs_reg ret_payload
= ubld
.vgrf(BRW_REGISTER_TYPE_UD
, 4);
4156 ubld
.MOV(src_payload
, brw_imm_d(0));
4158 const unsigned index
= prog_data
->binding_table
.ssbo_start
+ ssbo_index
;
4159 fs_inst
*inst
= ubld
.emit(FS_OPCODE_GET_BUFFER_SIZE
, ret_payload
,
4160 src_payload
, brw_imm_ud(index
));
4161 inst
->header_size
= 0;
4163 inst
->size_written
= 4 * REG_SIZE
;
4165 bld
.MOV(retype(dest
, ret_payload
.type
), component(ret_payload
, 0));
4166 brw_mark_surface_used(prog_data
, index
);
4170 case nir_intrinsic_load_subgroup_invocation
:
4171 bld
.MOV(retype(dest
, BRW_REGISTER_TYPE_D
),
4172 nir_system_values
[SYSTEM_VALUE_SUBGROUP_INVOCATION
]);
4175 case nir_intrinsic_load_subgroup_eq_mask
:
4176 case nir_intrinsic_load_subgroup_ge_mask
:
4177 case nir_intrinsic_load_subgroup_gt_mask
:
4178 case nir_intrinsic_load_subgroup_le_mask
:
4179 case nir_intrinsic_load_subgroup_lt_mask
:
4180 unreachable("not reached");
4182 case nir_intrinsic_vote_any
: {
4183 const fs_builder ubld
= bld
.exec_all().group(1, 0);
4185 /* The any/all predicates do not consider channel enables. To prevent
4186 * dead channels from affecting the result, we initialize the flag with
4187 * with the identity value for the logical operation.
4189 if (dispatch_width
== 32) {
4190 /* For SIMD32, we use a UD type so we fill both f0.0 and f0.1. */
4191 ubld
.MOV(retype(brw_flag_reg(0, 0), BRW_REGISTER_TYPE_UD
),
4194 ubld
.MOV(brw_flag_reg(0, 0), brw_imm_uw(0));
4196 bld
.CMP(bld
.null_reg_d(), get_nir_src(instr
->src
[0]), brw_imm_d(0), BRW_CONDITIONAL_NZ
);
4198 /* For some reason, the any/all predicates don't work properly with
4199 * SIMD32. In particular, it appears that a SEL with a QtrCtrl of 2H
4200 * doesn't read the correct subset of the flag register and you end up
4201 * getting garbage in the second half. Work around this by using a pair
4202 * of 1-wide MOVs and scattering the result.
4204 fs_reg res1
= ubld
.vgrf(BRW_REGISTER_TYPE_D
);
4205 ubld
.MOV(res1
, brw_imm_d(0));
4206 set_predicate(dispatch_width
== 8 ? BRW_PREDICATE_ALIGN1_ANY8H
:
4207 dispatch_width
== 16 ? BRW_PREDICATE_ALIGN1_ANY16H
:
4208 BRW_PREDICATE_ALIGN1_ANY32H
,
4209 ubld
.MOV(res1
, brw_imm_d(-1)));
4211 bld
.MOV(retype(dest
, BRW_REGISTER_TYPE_D
), component(res1
, 0));
4214 case nir_intrinsic_vote_all
: {
4215 const fs_builder ubld
= bld
.exec_all().group(1, 0);
4217 /* The any/all predicates do not consider channel enables. To prevent
4218 * dead channels from affecting the result, we initialize the flag with
4219 * with the identity value for the logical operation.
4221 if (dispatch_width
== 32) {
4222 /* For SIMD32, we use a UD type so we fill both f0.0 and f0.1. */
4223 ubld
.MOV(retype(brw_flag_reg(0, 0), BRW_REGISTER_TYPE_UD
),
4224 brw_imm_ud(0xffffffff));
4226 ubld
.MOV(brw_flag_reg(0, 0), brw_imm_uw(0xffff));
4228 bld
.CMP(bld
.null_reg_d(), get_nir_src(instr
->src
[0]), brw_imm_d(0), BRW_CONDITIONAL_NZ
);
4230 /* For some reason, the any/all predicates don't work properly with
4231 * SIMD32. In particular, it appears that a SEL with a QtrCtrl of 2H
4232 * doesn't read the correct subset of the flag register and you end up
4233 * getting garbage in the second half. Work around this by using a pair
4234 * of 1-wide MOVs and scattering the result.
4236 fs_reg res1
= ubld
.vgrf(BRW_REGISTER_TYPE_D
);
4237 ubld
.MOV(res1
, brw_imm_d(0));
4238 set_predicate(dispatch_width
== 8 ? BRW_PREDICATE_ALIGN1_ALL8H
:
4239 dispatch_width
== 16 ? BRW_PREDICATE_ALIGN1_ALL16H
:
4240 BRW_PREDICATE_ALIGN1_ALL32H
,
4241 ubld
.MOV(res1
, brw_imm_d(-1)));
4243 bld
.MOV(retype(dest
, BRW_REGISTER_TYPE_D
), component(res1
, 0));
4246 case nir_intrinsic_vote_eq
: {
4247 fs_reg value
= get_nir_src(instr
->src
[0]);
4248 fs_reg uniformized
= bld
.emit_uniformize(value
);
4249 const fs_builder ubld
= bld
.exec_all().group(1, 0);
4251 /* The any/all predicates do not consider channel enables. To prevent
4252 * dead channels from affecting the result, we initialize the flag with
4253 * with the identity value for the logical operation.
4255 if (dispatch_width
== 32) {
4256 /* For SIMD32, we use a UD type so we fill both f0.0 and f0.1. */
4257 ubld
.MOV(retype(brw_flag_reg(0, 0), BRW_REGISTER_TYPE_UD
),
4258 brw_imm_ud(0xffffffff));
4260 ubld
.MOV(brw_flag_reg(0, 0), brw_imm_uw(0xffff));
4262 bld
.CMP(bld
.null_reg_d(), value
, uniformized
, BRW_CONDITIONAL_Z
);
4264 /* For some reason, the any/all predicates don't work properly with
4265 * SIMD32. In particular, it appears that a SEL with a QtrCtrl of 2H
4266 * doesn't read the correct subset of the flag register and you end up
4267 * getting garbage in the second half. Work around this by using a pair
4268 * of 1-wide MOVs and scattering the result.
4270 fs_reg res1
= ubld
.vgrf(BRW_REGISTER_TYPE_D
);
4271 ubld
.MOV(res1
, brw_imm_d(0));
4272 set_predicate(dispatch_width
== 8 ? BRW_PREDICATE_ALIGN1_ALL8H
:
4273 dispatch_width
== 16 ? BRW_PREDICATE_ALIGN1_ALL16H
:
4274 BRW_PREDICATE_ALIGN1_ALL32H
,
4275 ubld
.MOV(res1
, brw_imm_d(-1)));
4277 bld
.MOV(retype(dest
, BRW_REGISTER_TYPE_D
), component(res1
, 0));
4281 case nir_intrinsic_ballot
: {
4282 const fs_reg value
= retype(get_nir_src(instr
->src
[0]),
4283 BRW_REGISTER_TYPE_UD
);
4284 struct brw_reg flag
= brw_flag_reg(0, 0);
4285 /* FIXME: For SIMD32 programs, this causes us to stomp on f0.1 as well
4286 * as f0.0. This is a problem for fragment programs as we currently use
4287 * f0.1 for discards. Fortunately, we don't support SIMD32 fragment
4288 * programs yet so this isn't a problem. When we do, something will
4291 if (dispatch_width
== 32)
4292 flag
.type
= BRW_REGISTER_TYPE_UD
;
4294 bld
.exec_all().group(1, 0).MOV(flag
, brw_imm_ud(0u));
4295 bld
.CMP(bld
.null_reg_ud(), value
, brw_imm_ud(0u), BRW_CONDITIONAL_NZ
);
4297 if (instr
->dest
.ssa
.bit_size
> 32) {
4298 dest
.type
= BRW_REGISTER_TYPE_UQ
;
4300 dest
.type
= BRW_REGISTER_TYPE_UD
;
4302 bld
.MOV(dest
, flag
);
4306 case nir_intrinsic_read_invocation
: {
4307 const fs_reg value
= get_nir_src(instr
->src
[0]);
4308 const fs_reg invocation
= get_nir_src(instr
->src
[1]);
4309 fs_reg tmp
= bld
.vgrf(value
.type
);
4311 bld
.exec_all().emit(SHADER_OPCODE_BROADCAST
, tmp
, value
,
4312 bld
.emit_uniformize(invocation
));
4314 bld
.MOV(retype(dest
, value
.type
), fs_reg(component(tmp
, 0)));
4318 case nir_intrinsic_read_first_invocation
: {
4319 const fs_reg value
= get_nir_src(instr
->src
[0]);
4320 bld
.MOV(retype(dest
, value
.type
), bld
.emit_uniformize(value
));
4325 unreachable("unknown intrinsic");
4330 fs_visitor::nir_emit_ssbo_atomic(const fs_builder
&bld
,
4331 int op
, nir_intrinsic_instr
*instr
)
4333 if (stage
== MESA_SHADER_FRAGMENT
)
4334 brw_wm_prog_data(prog_data
)->has_side_effects
= true;
4337 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
4338 dest
= get_nir_dest(instr
->dest
);
4341 nir_const_value
*const_surface
= nir_src_as_const_value(instr
->src
[0]);
4342 if (const_surface
) {
4343 unsigned surf_index
= stage_prog_data
->binding_table
.ssbo_start
+
4344 const_surface
->u32
[0];
4345 surface
= brw_imm_ud(surf_index
);
4346 brw_mark_surface_used(prog_data
, surf_index
);
4348 surface
= vgrf(glsl_type::uint_type
);
4349 bld
.ADD(surface
, get_nir_src(instr
->src
[0]),
4350 brw_imm_ud(stage_prog_data
->binding_table
.ssbo_start
));
4352 /* Assume this may touch any SSBO. This is the same we do for other
4353 * UBO/SSBO accesses with non-constant surface.
4355 brw_mark_surface_used(prog_data
,
4356 stage_prog_data
->binding_table
.ssbo_start
+
4357 nir
->info
.num_ssbos
- 1);
4360 fs_reg offset
= get_nir_src(instr
->src
[1]);
4361 fs_reg data1
= get_nir_src(instr
->src
[2]);
4363 if (op
== BRW_AOP_CMPWR
)
4364 data2
= get_nir_src(instr
->src
[3]);
4366 /* Emit the actual atomic operation */
4368 fs_reg atomic_result
= emit_untyped_atomic(bld
, surface
, offset
,
4370 1 /* dims */, 1 /* rsize */,
4372 BRW_PREDICATE_NONE
);
4373 dest
.type
= atomic_result
.type
;
4374 bld
.MOV(dest
, atomic_result
);
4378 fs_visitor::nir_emit_shared_atomic(const fs_builder
&bld
,
4379 int op
, nir_intrinsic_instr
*instr
)
4382 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
4383 dest
= get_nir_dest(instr
->dest
);
4385 fs_reg surface
= brw_imm_ud(GEN7_BTI_SLM
);
4387 fs_reg data1
= get_nir_src(instr
->src
[1]);
4389 if (op
== BRW_AOP_CMPWR
)
4390 data2
= get_nir_src(instr
->src
[2]);
4392 /* Get the offset */
4393 nir_const_value
*const_offset
= nir_src_as_const_value(instr
->src
[0]);
4395 offset
= brw_imm_ud(instr
->const_index
[0] + const_offset
->u32
[0]);
4397 offset
= vgrf(glsl_type::uint_type
);
4399 retype(get_nir_src(instr
->src
[0]), BRW_REGISTER_TYPE_UD
),
4400 brw_imm_ud(instr
->const_index
[0]));
4403 /* Emit the actual atomic operation operation */
4405 fs_reg atomic_result
= emit_untyped_atomic(bld
, surface
, offset
,
4407 1 /* dims */, 1 /* rsize */,
4409 BRW_PREDICATE_NONE
);
4410 dest
.type
= atomic_result
.type
;
4411 bld
.MOV(dest
, atomic_result
);
4415 fs_visitor::nir_emit_texture(const fs_builder
&bld
, nir_tex_instr
*instr
)
4417 unsigned texture
= instr
->texture_index
;
4418 unsigned sampler
= instr
->sampler_index
;
4420 fs_reg srcs
[TEX_LOGICAL_NUM_SRCS
];
4422 srcs
[TEX_LOGICAL_SRC_SURFACE
] = brw_imm_ud(texture
);
4423 srcs
[TEX_LOGICAL_SRC_SAMPLER
] = brw_imm_ud(sampler
);
4425 int lod_components
= 0;
4427 /* The hardware requires a LOD for buffer textures */
4428 if (instr
->sampler_dim
== GLSL_SAMPLER_DIM_BUF
)
4429 srcs
[TEX_LOGICAL_SRC_LOD
] = brw_imm_d(0);
4431 uint32_t header_bits
= 0;
4432 for (unsigned i
= 0; i
< instr
->num_srcs
; i
++) {
4433 fs_reg src
= get_nir_src(instr
->src
[i
].src
);
4434 switch (instr
->src
[i
].src_type
) {
4435 case nir_tex_src_bias
:
4436 srcs
[TEX_LOGICAL_SRC_LOD
] =
4437 retype(get_nir_src_imm(instr
->src
[i
].src
), BRW_REGISTER_TYPE_F
);
4439 case nir_tex_src_comparator
:
4440 srcs
[TEX_LOGICAL_SRC_SHADOW_C
] = retype(src
, BRW_REGISTER_TYPE_F
);
4442 case nir_tex_src_coord
:
4443 switch (instr
->op
) {
4445 case nir_texop_txf_ms
:
4446 case nir_texop_txf_ms_mcs
:
4447 case nir_texop_samples_identical
:
4448 srcs
[TEX_LOGICAL_SRC_COORDINATE
] = retype(src
, BRW_REGISTER_TYPE_D
);
4451 srcs
[TEX_LOGICAL_SRC_COORDINATE
] = retype(src
, BRW_REGISTER_TYPE_F
);
4455 case nir_tex_src_ddx
:
4456 srcs
[TEX_LOGICAL_SRC_LOD
] = retype(src
, BRW_REGISTER_TYPE_F
);
4457 lod_components
= nir_tex_instr_src_size(instr
, i
);
4459 case nir_tex_src_ddy
:
4460 srcs
[TEX_LOGICAL_SRC_LOD2
] = retype(src
, BRW_REGISTER_TYPE_F
);
4462 case nir_tex_src_lod
:
4463 switch (instr
->op
) {
4465 srcs
[TEX_LOGICAL_SRC_LOD
] =
4466 retype(get_nir_src_imm(instr
->src
[i
].src
), BRW_REGISTER_TYPE_UD
);
4469 srcs
[TEX_LOGICAL_SRC_LOD
] =
4470 retype(get_nir_src_imm(instr
->src
[i
].src
), BRW_REGISTER_TYPE_D
);
4473 srcs
[TEX_LOGICAL_SRC_LOD
] =
4474 retype(get_nir_src_imm(instr
->src
[i
].src
), BRW_REGISTER_TYPE_F
);
4478 case nir_tex_src_ms_index
:
4479 srcs
[TEX_LOGICAL_SRC_SAMPLE_INDEX
] = retype(src
, BRW_REGISTER_TYPE_UD
);
4482 case nir_tex_src_offset
: {
4483 nir_const_value
*const_offset
=
4484 nir_src_as_const_value(instr
->src
[i
].src
);
4485 unsigned offset_bits
= 0;
4487 brw_texture_offset(const_offset
->i32
,
4488 nir_tex_instr_src_size(instr
, i
),
4490 header_bits
|= offset_bits
;
4492 srcs
[TEX_LOGICAL_SRC_TG4_OFFSET
] =
4493 retype(src
, BRW_REGISTER_TYPE_D
);
4498 case nir_tex_src_projector
:
4499 unreachable("should be lowered");
4501 case nir_tex_src_texture_offset
: {
4502 /* Figure out the highest possible texture index and mark it as used */
4503 uint32_t max_used
= texture
+ instr
->texture_array_size
- 1;
4504 if (instr
->op
== nir_texop_tg4
&& devinfo
->gen
< 8) {
4505 max_used
+= stage_prog_data
->binding_table
.gather_texture_start
;
4507 max_used
+= stage_prog_data
->binding_table
.texture_start
;
4509 brw_mark_surface_used(prog_data
, max_used
);
4511 /* Emit code to evaluate the actual indexing expression */
4512 fs_reg tmp
= vgrf(glsl_type::uint_type
);
4513 bld
.ADD(tmp
, src
, brw_imm_ud(texture
));
4514 srcs
[TEX_LOGICAL_SRC_SURFACE
] = bld
.emit_uniformize(tmp
);
4518 case nir_tex_src_sampler_offset
: {
4519 /* Emit code to evaluate the actual indexing expression */
4520 fs_reg tmp
= vgrf(glsl_type::uint_type
);
4521 bld
.ADD(tmp
, src
, brw_imm_ud(sampler
));
4522 srcs
[TEX_LOGICAL_SRC_SAMPLER
] = bld
.emit_uniformize(tmp
);
4526 case nir_tex_src_ms_mcs
:
4527 assert(instr
->op
== nir_texop_txf_ms
);
4528 srcs
[TEX_LOGICAL_SRC_MCS
] = retype(src
, BRW_REGISTER_TYPE_D
);
4531 case nir_tex_src_plane
: {
4532 nir_const_value
*const_plane
=
4533 nir_src_as_const_value(instr
->src
[i
].src
);
4534 const uint32_t plane
= const_plane
->u32
[0];
4535 const uint32_t texture_index
=
4536 instr
->texture_index
+
4537 stage_prog_data
->binding_table
.plane_start
[plane
] -
4538 stage_prog_data
->binding_table
.texture_start
;
4540 srcs
[TEX_LOGICAL_SRC_SURFACE
] = brw_imm_ud(texture_index
);
4545 unreachable("unknown texture source");
4549 if (srcs
[TEX_LOGICAL_SRC_MCS
].file
== BAD_FILE
&&
4550 (instr
->op
== nir_texop_txf_ms
||
4551 instr
->op
== nir_texop_samples_identical
)) {
4552 if (devinfo
->gen
>= 7 &&
4553 key_tex
->compressed_multisample_layout_mask
& (1 << texture
)) {
4554 srcs
[TEX_LOGICAL_SRC_MCS
] =
4555 emit_mcs_fetch(srcs
[TEX_LOGICAL_SRC_COORDINATE
],
4556 instr
->coord_components
,
4557 srcs
[TEX_LOGICAL_SRC_SURFACE
]);
4559 srcs
[TEX_LOGICAL_SRC_MCS
] = brw_imm_ud(0u);
4563 srcs
[TEX_LOGICAL_SRC_COORD_COMPONENTS
] = brw_imm_d(instr
->coord_components
);
4564 srcs
[TEX_LOGICAL_SRC_GRAD_COMPONENTS
] = brw_imm_d(lod_components
);
4567 switch (instr
->op
) {
4569 opcode
= (stage
== MESA_SHADER_FRAGMENT
? SHADER_OPCODE_TEX_LOGICAL
:
4570 SHADER_OPCODE_TXL_LOGICAL
);
4573 opcode
= FS_OPCODE_TXB_LOGICAL
;
4576 opcode
= SHADER_OPCODE_TXL_LOGICAL
;
4579 opcode
= SHADER_OPCODE_TXD_LOGICAL
;
4582 opcode
= SHADER_OPCODE_TXF_LOGICAL
;
4584 case nir_texop_txf_ms
:
4585 if ((key_tex
->msaa_16
& (1 << sampler
)))
4586 opcode
= SHADER_OPCODE_TXF_CMS_W_LOGICAL
;
4588 opcode
= SHADER_OPCODE_TXF_CMS_LOGICAL
;
4590 case nir_texop_txf_ms_mcs
:
4591 opcode
= SHADER_OPCODE_TXF_MCS_LOGICAL
;
4593 case nir_texop_query_levels
:
4595 opcode
= SHADER_OPCODE_TXS_LOGICAL
;
4598 opcode
= SHADER_OPCODE_LOD_LOGICAL
;
4601 if (srcs
[TEX_LOGICAL_SRC_TG4_OFFSET
].file
!= BAD_FILE
)
4602 opcode
= SHADER_OPCODE_TG4_OFFSET_LOGICAL
;
4604 opcode
= SHADER_OPCODE_TG4_LOGICAL
;
4606 case nir_texop_texture_samples
:
4607 opcode
= SHADER_OPCODE_SAMPLEINFO_LOGICAL
;
4609 case nir_texop_samples_identical
: {
4610 fs_reg dst
= retype(get_nir_dest(instr
->dest
), BRW_REGISTER_TYPE_D
);
4612 /* If mcs is an immediate value, it means there is no MCS. In that case
4613 * just return false.
4615 if (srcs
[TEX_LOGICAL_SRC_MCS
].file
== BRW_IMMEDIATE_VALUE
) {
4616 bld
.MOV(dst
, brw_imm_ud(0u));
4617 } else if ((key_tex
->msaa_16
& (1 << sampler
))) {
4618 fs_reg tmp
= vgrf(glsl_type::uint_type
);
4619 bld
.OR(tmp
, srcs
[TEX_LOGICAL_SRC_MCS
],
4620 offset(srcs
[TEX_LOGICAL_SRC_MCS
], bld
, 1));
4621 bld
.CMP(dst
, tmp
, brw_imm_ud(0u), BRW_CONDITIONAL_EQ
);
4623 bld
.CMP(dst
, srcs
[TEX_LOGICAL_SRC_MCS
], brw_imm_ud(0u),
4624 BRW_CONDITIONAL_EQ
);
4629 unreachable("unknown texture opcode");
4632 if (instr
->op
== nir_texop_tg4
) {
4633 if (instr
->component
== 1 &&
4634 key_tex
->gather_channel_quirk_mask
& (1 << texture
)) {
4635 /* gather4 sampler is broken for green channel on RG32F --
4636 * we must ask for blue instead.
4638 header_bits
|= 2 << 16;
4640 header_bits
|= instr
->component
<< 16;
4644 fs_reg dst
= bld
.vgrf(brw_type_for_nir_type(devinfo
, instr
->dest_type
), 4);
4645 fs_inst
*inst
= bld
.emit(opcode
, dst
, srcs
, ARRAY_SIZE(srcs
));
4646 inst
->offset
= header_bits
;
4648 const unsigned dest_size
= nir_tex_instr_dest_size(instr
);
4649 if (devinfo
->gen
>= 9 &&
4650 instr
->op
!= nir_texop_tg4
&& instr
->op
!= nir_texop_query_levels
) {
4651 unsigned write_mask
= instr
->dest
.is_ssa
?
4652 nir_ssa_def_components_read(&instr
->dest
.ssa
):
4653 (1 << dest_size
) - 1;
4654 assert(write_mask
!= 0); /* dead code should have been eliminated */
4655 inst
->size_written
= util_last_bit(write_mask
) *
4656 inst
->dst
.component_size(inst
->exec_size
);
4658 inst
->size_written
= 4 * inst
->dst
.component_size(inst
->exec_size
);
4661 if (srcs
[TEX_LOGICAL_SRC_SHADOW_C
].file
!= BAD_FILE
)
4662 inst
->shadow_compare
= true;
4664 if (instr
->op
== nir_texop_tg4
&& devinfo
->gen
== 6)
4665 emit_gen6_gather_wa(key_tex
->gen6_gather_wa
[texture
], dst
);
4668 for (unsigned i
= 0; i
< dest_size
; i
++)
4669 nir_dest
[i
] = offset(dst
, bld
, i
);
4671 if (instr
->op
== nir_texop_query_levels
) {
4672 /* # levels is in .w */
4673 nir_dest
[0] = offset(dst
, bld
, 3);
4674 } else if (instr
->op
== nir_texop_txs
&&
4675 dest_size
>= 3 && devinfo
->gen
< 7) {
4676 /* Gen4-6 return 0 instead of 1 for single layer surfaces. */
4677 fs_reg depth
= offset(dst
, bld
, 2);
4678 nir_dest
[2] = vgrf(glsl_type::int_type
);
4679 bld
.emit_minmax(nir_dest
[2], depth
, brw_imm_d(1), BRW_CONDITIONAL_GE
);
4682 bld
.LOAD_PAYLOAD(get_nir_dest(instr
->dest
), nir_dest
, dest_size
, 0);
4686 fs_visitor::nir_emit_jump(const fs_builder
&bld
, nir_jump_instr
*instr
)
4688 switch (instr
->type
) {
4689 case nir_jump_break
:
4690 bld
.emit(BRW_OPCODE_BREAK
);
4692 case nir_jump_continue
:
4693 bld
.emit(BRW_OPCODE_CONTINUE
);
4695 case nir_jump_return
:
4697 unreachable("unknown jump");
4702 * This helper takes the result of a load operation that reads 32-bit elements
4710 * and shuffles the data to get this:
4717 * Which is exactly what we want if the load is reading 64-bit components
4718 * like doubles, where x represents the low 32-bit of the x double component
4719 * and y represents the high 32-bit of the x double component (likewise with
4720 * z and w for double component y). The parameter @components represents
4721 * the number of 64-bit components present in @src. This would typically be
4722 * 2 at most, since we can only fit 2 double elements in the result of a
4725 * Notice that @dst and @src can be the same register.
4728 shuffle_32bit_load_result_to_64bit_data(const fs_builder
&bld
,
4731 uint32_t components
)
4733 assert(type_sz(src
.type
) == 4);
4734 assert(type_sz(dst
.type
) == 8);
4736 /* A temporary that we will use to shuffle the 32-bit data of each
4737 * component in the vector into valid 64-bit data. We can't write directly
4738 * to dst because dst can be (and would usually be) the same as src
4739 * and in that case the first MOV in the loop below would overwrite the
4740 * data read in the second MOV.
4742 fs_reg tmp
= bld
.vgrf(dst
.type
);
4744 for (unsigned i
= 0; i
< components
; i
++) {
4745 const fs_reg component_i
= offset(src
, bld
, 2 * i
);
4747 bld
.MOV(subscript(tmp
, src
.type
, 0), component_i
);
4748 bld
.MOV(subscript(tmp
, src
.type
, 1), offset(component_i
, bld
, 1));
4750 bld
.MOV(offset(dst
, bld
, i
), tmp
);
4755 * This helper does the inverse operation of
4756 * SHUFFLE_32BIT_LOAD_RESULT_TO_64BIT_DATA.
4758 * We need to do this when we are going to use untyped write messsages that
4759 * operate with 32-bit components in order to arrange our 64-bit data to be
4760 * in the expected layout.
4762 * Notice that callers of this function, unlike in the case of the inverse
4763 * operation, would typically need to call this with dst and src being
4764 * different registers, since they would otherwise corrupt the original
4765 * 64-bit data they are about to write. Because of this the function checks
4766 * that the src and dst regions involved in the operation do not overlap.
4769 shuffle_64bit_data_for_32bit_write(const fs_builder
&bld
,
4771 uint32_t components
)
4773 assert(type_sz(src
.type
) == 8);
4775 fs_reg dst
= bld
.vgrf(BRW_REGISTER_TYPE_D
, 2 * components
);
4777 for (unsigned i
= 0; i
< components
; i
++) {
4778 const fs_reg component_i
= offset(src
, bld
, i
);
4779 bld
.MOV(offset(dst
, bld
, 2 * i
), subscript(component_i
, dst
.type
, 0));
4780 bld
.MOV(offset(dst
, bld
, 2 * i
+ 1), subscript(component_i
, dst
.type
, 1));
4787 setup_imm_df(const fs_builder
&bld
, double v
)
4789 const struct gen_device_info
*devinfo
= bld
.shader
->devinfo
;
4790 assert(devinfo
->gen
>= 7);
4792 if (devinfo
->gen
>= 8)
4793 return brw_imm_df(v
);
4795 /* gen7.5 does not support DF immediates straighforward but the DIM
4796 * instruction allows to set the 64-bit immediate value.
4798 if (devinfo
->is_haswell
) {
4799 const fs_builder ubld
= bld
.exec_all().group(1, 0);
4800 fs_reg dst
= ubld
.vgrf(BRW_REGISTER_TYPE_DF
, 1);
4801 ubld
.DIM(dst
, brw_imm_df(v
));
4802 return component(dst
, 0);
4805 /* gen7 does not support DF immediates, so we generate a 64-bit constant by
4806 * writing the low 32-bit of the constant to suboffset 0 of a VGRF and
4807 * the high 32-bit to suboffset 4 and then applying a stride of 0.
4809 * Alternatively, we could also produce a normal VGRF (without stride 0)
4810 * by writing to all the channels in the VGRF, however, that would hit the
4811 * gen7 bug where we have to split writes that span more than 1 register
4812 * into instructions with a width of 4 (otherwise the write to the second
4813 * register written runs into an execmask hardware bug) which isn't very
4826 const fs_builder ubld
= bld
.exec_all().group(1, 0);
4827 const fs_reg tmp
= ubld
.vgrf(BRW_REGISTER_TYPE_UD
, 2);
4828 ubld
.MOV(tmp
, brw_imm_ud(di
.i1
));
4829 ubld
.MOV(horiz_offset(tmp
, 1), brw_imm_ud(di
.i2
));
4831 return component(retype(tmp
, BRW_REGISTER_TYPE_DF
), 0);