2 * Copyright © 2010 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Eric Anholt <eric@anholt.net>
31 #include "util/register_allocate.h"
36 assign_reg(unsigned *reg_hw_locations
, fs_reg
*reg
)
38 if (reg
->file
== VGRF
) {
39 reg
->nr
= reg_hw_locations
[reg
->nr
] + reg
->offset
/ REG_SIZE
;
40 reg
->offset
%= REG_SIZE
;
45 fs_visitor::assign_regs_trivial()
47 unsigned hw_reg_mapping
[this->alloc
.count
+ 1];
49 int reg_width
= dispatch_width
/ 8;
51 /* Note that compressed instructions require alignment to 2 registers. */
52 hw_reg_mapping
[0] = ALIGN(this->first_non_payload_grf
, reg_width
);
53 for (i
= 1; i
<= this->alloc
.count
; i
++) {
54 hw_reg_mapping
[i
] = (hw_reg_mapping
[i
- 1] +
55 this->alloc
.sizes
[i
- 1]);
57 this->grf_used
= hw_reg_mapping
[this->alloc
.count
];
59 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
60 assign_reg(hw_reg_mapping
, &inst
->dst
);
61 for (i
= 0; i
< inst
->sources
; i
++) {
62 assign_reg(hw_reg_mapping
, &inst
->src
[i
]);
66 if (this->grf_used
>= max_grf
) {
67 fail("Ran out of regs on trivial allocator (%d/%d)\n",
68 this->grf_used
, max_grf
);
70 this->alloc
.count
= this->grf_used
;
76 brw_alloc_reg_set(struct brw_compiler
*compiler
, int dispatch_width
)
78 const struct gen_device_info
*devinfo
= compiler
->devinfo
;
79 int base_reg_count
= BRW_MAX_GRF
;
80 const int index
= _mesa_logbase2(dispatch_width
/ 8);
82 if (dispatch_width
> 8 && devinfo
->gen
>= 7) {
83 /* For IVB+, we don't need the PLN hacks or the even-reg alignment in
84 * SIMD16. Therefore, we can use the exact same register sets for
85 * SIMD16 as we do for SIMD8 and we don't need to recalculate them.
87 compiler
->fs_reg_sets
[index
] = compiler
->fs_reg_sets
[0];
91 /* The registers used to make up almost all values handled in the compiler
92 * are a scalar value occupying a single register (or 2 registers in the
93 * case of SIMD16, which is handled by dividing base_reg_count by 2 and
94 * multiplying allocated register numbers by 2). Things that were
95 * aggregates of scalar values at the GLSL level were split to scalar
96 * values by split_virtual_grfs().
98 * However, texture SEND messages return a series of contiguous registers
99 * to write into. We currently always ask for 4 registers, but we may
100 * convert that to use less some day.
102 * Additionally, on gen5 we need aligned pairs of registers for the PLN
103 * instruction, and on gen4 we need 8 contiguous regs for workaround simd16
106 const int class_count
= MAX_VGRF_SIZE
;
107 int class_sizes
[MAX_VGRF_SIZE
];
108 for (unsigned i
= 0; i
< MAX_VGRF_SIZE
; i
++)
109 class_sizes
[i
] = i
+ 1;
111 memset(compiler
->fs_reg_sets
[index
].class_to_ra_reg_range
, 0,
112 sizeof(compiler
->fs_reg_sets
[index
].class_to_ra_reg_range
));
113 int *class_to_ra_reg_range
= compiler
->fs_reg_sets
[index
].class_to_ra_reg_range
;
115 /* Compute the total number of registers across all classes. */
116 int ra_reg_count
= 0;
117 for (int i
= 0; i
< class_count
; i
++) {
118 if (devinfo
->gen
<= 5 && dispatch_width
>= 16) {
121 * In order to reduce the hardware complexity, the following
122 * rules and restrictions apply to the compressed instruction:
124 * * Operand Alignment Rule: With the exceptions listed below, a
125 * source/destination operand in general should be aligned to
126 * even 256-bit physical register with a region size equal to
127 * two 256-bit physical register
129 ra_reg_count
+= (base_reg_count
- (class_sizes
[i
] - 1)) / 2;
131 ra_reg_count
+= base_reg_count
- (class_sizes
[i
] - 1);
133 /* Mark the last register. We'll fill in the beginnings later. */
134 class_to_ra_reg_range
[class_sizes
[i
]] = ra_reg_count
;
137 /* Fill out the rest of the range markers */
138 for (int i
= 1; i
< 17; ++i
) {
139 if (class_to_ra_reg_range
[i
] == 0)
140 class_to_ra_reg_range
[i
] = class_to_ra_reg_range
[i
-1];
143 uint8_t *ra_reg_to_grf
= ralloc_array(compiler
, uint8_t, ra_reg_count
);
144 struct ra_regs
*regs
= ra_alloc_reg_set(compiler
, ra_reg_count
, false);
145 if (devinfo
->gen
>= 6)
146 ra_set_allocate_round_robin(regs
);
147 int *classes
= ralloc_array(compiler
, int, class_count
);
148 int aligned_pairs_class
= -1;
150 /* Allocate space for q values. We allocate class_count + 1 because we
151 * want to leave room for the aligned pairs class if we have it. */
152 unsigned int **q_values
= ralloc_array(compiler
, unsigned int *,
154 for (int i
= 0; i
< class_count
+ 1; ++i
)
155 q_values
[i
] = ralloc_array(q_values
, unsigned int, class_count
+ 1);
157 /* Now, add the registers to their classes, and add the conflicts
158 * between them and the base GRF registers (and also each other).
161 int pairs_base_reg
= 0;
162 int pairs_reg_count
= 0;
163 for (int i
= 0; i
< class_count
; i
++) {
165 if (devinfo
->gen
<= 5 && dispatch_width
>= 16) {
166 class_reg_count
= (base_reg_count
- (class_sizes
[i
] - 1)) / 2;
168 /* See comment below. The only difference here is that we are
169 * dealing with pairs of registers instead of single registers.
170 * Registers of odd sizes simply get rounded up. */
171 for (int j
= 0; j
< class_count
; j
++)
172 q_values
[i
][j
] = (class_sizes
[i
] + 1) / 2 +
173 (class_sizes
[j
] + 1) / 2 - 1;
175 class_reg_count
= base_reg_count
- (class_sizes
[i
] - 1);
177 /* From register_allocate.c:
179 * q(B,C) (indexed by C, B is this register class) in
180 * Runeson/Nyström paper. This is "how many registers of B could
181 * the worst choice register from C conflict with".
183 * If we just let the register allocation algorithm compute these
184 * values, is extremely expensive. However, since all of our
185 * registers are laid out, we can very easily compute them
186 * ourselves. View the register from C as fixed starting at GRF n
187 * somwhere in the middle, and the register from B as sliding back
188 * and forth. Then the first register to conflict from B is the
189 * one starting at n - class_size[B] + 1 and the last register to
190 * conflict will start at n + class_size[B] - 1. Therefore, the
191 * number of conflicts from B is class_size[B] + class_size[C] - 1.
193 * +-+-+-+-+-+-+ +-+-+-+-+-+-+
194 * B | | | | | |n| --> | | | | | | |
195 * +-+-+-+-+-+-+ +-+-+-+-+-+-+
200 for (int j
= 0; j
< class_count
; j
++)
201 q_values
[i
][j
] = class_sizes
[i
] + class_sizes
[j
] - 1;
203 classes
[i
] = ra_alloc_reg_class(regs
);
205 /* Save this off for the aligned pair class at the end. */
206 if (class_sizes
[i
] == 2) {
207 pairs_base_reg
= reg
;
208 pairs_reg_count
= class_reg_count
;
211 if (devinfo
->gen
<= 5 && dispatch_width
>= 16) {
212 for (int j
= 0; j
< class_reg_count
; j
++) {
213 ra_class_add_reg(regs
, classes
[i
], reg
);
215 ra_reg_to_grf
[reg
] = j
* 2;
217 for (int base_reg
= j
;
218 base_reg
< j
+ (class_sizes
[i
] + 1) / 2;
220 ra_add_reg_conflict(regs
, base_reg
, reg
);
226 for (int j
= 0; j
< class_reg_count
; j
++) {
227 ra_class_add_reg(regs
, classes
[i
], reg
);
229 ra_reg_to_grf
[reg
] = j
;
231 for (int base_reg
= j
;
232 base_reg
< j
+ class_sizes
[i
];
234 ra_add_reg_conflict(regs
, base_reg
, reg
);
241 assert(reg
== ra_reg_count
);
243 /* Applying transitivity to all of the base registers gives us the
244 * appropreate register conflict relationships everywhere.
246 for (int reg
= 0; reg
< base_reg_count
; reg
++)
247 ra_make_reg_conflicts_transitive(regs
, reg
);
249 /* Add a special class for aligned pairs, which we'll put delta_xy
250 * in on Gen <= 6 so that we can do PLN.
252 if (devinfo
->has_pln
&& dispatch_width
== 8 && devinfo
->gen
<= 6) {
253 aligned_pairs_class
= ra_alloc_reg_class(regs
);
255 for (int i
= 0; i
< pairs_reg_count
; i
++) {
256 if ((ra_reg_to_grf
[pairs_base_reg
+ i
] & 1) == 0) {
257 ra_class_add_reg(regs
, aligned_pairs_class
, pairs_base_reg
+ i
);
261 for (int i
= 0; i
< class_count
; i
++) {
262 /* These are a little counter-intuitive because the pair registers
263 * are required to be aligned while the register they are
264 * potentially interferring with are not. In the case where the
265 * size is even, the worst-case is that the register is
266 * odd-aligned. In the odd-size case, it doesn't matter.
268 q_values
[class_count
][i
] = class_sizes
[i
] / 2 + 1;
269 q_values
[i
][class_count
] = class_sizes
[i
] + 1;
271 q_values
[class_count
][class_count
] = 1;
274 ra_set_finalize(regs
, q_values
);
276 ralloc_free(q_values
);
278 compiler
->fs_reg_sets
[index
].regs
= regs
;
279 for (unsigned i
= 0; i
< ARRAY_SIZE(compiler
->fs_reg_sets
[index
].classes
); i
++)
280 compiler
->fs_reg_sets
[index
].classes
[i
] = -1;
281 for (int i
= 0; i
< class_count
; i
++)
282 compiler
->fs_reg_sets
[index
].classes
[class_sizes
[i
] - 1] = classes
[i
];
283 compiler
->fs_reg_sets
[index
].ra_reg_to_grf
= ra_reg_to_grf
;
284 compiler
->fs_reg_sets
[index
].aligned_pairs_class
= aligned_pairs_class
;
288 brw_fs_alloc_reg_sets(struct brw_compiler
*compiler
)
290 brw_alloc_reg_set(compiler
, 8);
291 brw_alloc_reg_set(compiler
, 16);
292 brw_alloc_reg_set(compiler
, 32);
296 count_to_loop_end(const bblock_t
*block
)
298 if (block
->end()->opcode
== BRW_OPCODE_WHILE
)
299 return block
->end_ip
;
302 /* Skip the first block, since we don't want to count the do the calling
305 for (block
= block
->next();
307 block
= block
->next()) {
308 if (block
->start()->opcode
== BRW_OPCODE_DO
)
310 if (block
->end()->opcode
== BRW_OPCODE_WHILE
) {
313 return block
->end_ip
;
316 unreachable("not reached");
319 void fs_visitor::calculate_payload_ranges(int payload_node_count
,
320 int *payload_last_use_ip
)
325 for (int i
= 0; i
< payload_node_count
; i
++)
326 payload_last_use_ip
[i
] = -1;
329 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
330 switch (inst
->opcode
) {
334 /* Since payload regs are deffed only at the start of the shader
335 * execution, any uses of the payload within a loop mean the live
336 * interval extends to the end of the outermost loop. Find the ip of
340 loop_end_ip
= count_to_loop_end(block
);
342 case BRW_OPCODE_WHILE
:
351 use_ip
= loop_end_ip
;
355 /* Note that UNIFORM args have been turned into FIXED_GRF by
356 * assign_curbe_setup(), and interpolation uses fixed hardware regs from
357 * the start (see interp_reg()).
359 for (int i
= 0; i
< inst
->sources
; i
++) {
360 if (inst
->src
[i
].file
== FIXED_GRF
) {
361 int node_nr
= inst
->src
[i
].nr
;
362 if (node_nr
>= payload_node_count
)
365 for (unsigned j
= 0; j
< regs_read(inst
, i
); j
++) {
366 payload_last_use_ip
[node_nr
+ j
] = use_ip
;
367 assert(node_nr
+ j
< unsigned(payload_node_count
));
372 /* Special case instructions which have extra implied registers used. */
373 switch (inst
->opcode
) {
374 case CS_OPCODE_CS_TERMINATE
:
375 payload_last_use_ip
[0] = use_ip
;
380 /* We could omit this for the !inst->header_present case, except
381 * that the simulator apparently incorrectly reads from g0/g1
382 * instead of sideband. It also really freaks out driver
383 * developers to see g0 used in unusual places, so just always
386 payload_last_use_ip
[0] = use_ip
;
387 payload_last_use_ip
[1] = use_ip
;
398 * Sets up interference between thread payload registers and the virtual GRFs
399 * to be allocated for program temporaries.
401 * We want to be able to reallocate the payload for our virtual GRFs, notably
402 * because the setup coefficients for a full set of 16 FS inputs takes up 8 of
405 * The layout of the payload registers is:
407 * 0..payload.num_regs-1: fixed function setup (including bary coordinates).
408 * payload.num_regs..payload.num_regs+curb_read_lengh-1: uniform data
409 * payload.num_regs+curb_read_lengh..first_non_payload_grf-1: setup coefficients.
411 * And we have payload_node_count nodes covering these registers in order
412 * (note that in SIMD16, a node is two registers).
415 fs_visitor::setup_payload_interference(struct ra_graph
*g
,
416 int payload_node_count
,
417 int first_payload_node
)
419 int payload_last_use_ip
[payload_node_count
];
420 calculate_payload_ranges(payload_node_count
, payload_last_use_ip
);
422 for (int i
= 0; i
< payload_node_count
; i
++) {
423 if (payload_last_use_ip
[i
] == -1)
426 /* Mark the payload node as interfering with any virtual grf that is
427 * live between the start of the program and our last use of the payload
430 for (unsigned j
= 0; j
< this->alloc
.count
; j
++) {
431 /* Note that we use a <= comparison, unlike virtual_grf_interferes(),
432 * in order to not have to worry about the uniform issue described in
433 * calculate_live_intervals().
435 if (this->virtual_grf_start
[j
] <= payload_last_use_ip
[i
]) {
436 ra_add_node_interference(g
, first_payload_node
+ i
, j
);
441 for (int i
= 0; i
< payload_node_count
; i
++) {
442 /* Mark each payload node as being allocated to its physical register.
444 * The alternative would be to have per-physical-register classes, which
445 * would just be silly.
447 if (devinfo
->gen
<= 5 && dispatch_width
>= 16) {
448 /* We have to divide by 2 here because we only have even numbered
449 * registers. Some of the payload registers will be odd, but
450 * that's ok because their physical register numbers have already
451 * been assigned. The only thing this is used for is interference.
453 ra_set_node_reg(g
, first_payload_node
+ i
, i
/ 2);
455 ra_set_node_reg(g
, first_payload_node
+ i
, i
);
461 * Sets the mrf_used array to indicate which MRFs are used by the shader IR
463 * This is used in assign_regs() to decide which of the GRFs that we use as
464 * MRFs on gen7 get normally register allocated, and in register spilling to
465 * see if we can actually use MRFs to do spills without overwriting normal MRF
469 get_used_mrfs(fs_visitor
*v
, bool *mrf_used
)
471 int reg_width
= v
->dispatch_width
/ 8;
473 memset(mrf_used
, 0, BRW_MAX_MRF(v
->devinfo
->gen
) * sizeof(bool));
475 foreach_block_and_inst(block
, fs_inst
, inst
, v
->cfg
) {
476 if (inst
->dst
.file
== MRF
) {
477 int reg
= inst
->dst
.nr
& ~BRW_MRF_COMPR4
;
478 mrf_used
[reg
] = true;
479 if (reg_width
== 2) {
480 if (inst
->dst
.nr
& BRW_MRF_COMPR4
) {
481 mrf_used
[reg
+ 4] = true;
483 mrf_used
[reg
+ 1] = true;
488 if (inst
->mlen
> 0) {
489 for (int i
= 0; i
< v
->implied_mrf_writes(inst
); i
++) {
490 mrf_used
[inst
->base_mrf
+ i
] = true;
497 * Sets interference between virtual GRFs and usage of the high GRFs for SEND
498 * messages (treated as MRFs in code generation).
501 setup_mrf_hack_interference(fs_visitor
*v
, struct ra_graph
*g
,
502 int first_mrf_node
, int *first_used_mrf
)
504 bool mrf_used
[BRW_MAX_MRF(v
->devinfo
->gen
)];
505 get_used_mrfs(v
, mrf_used
);
507 *first_used_mrf
= BRW_MAX_MRF(v
->devinfo
->gen
);
508 for (int i
= 0; i
< BRW_MAX_MRF(v
->devinfo
->gen
); i
++) {
509 /* Mark each MRF reg node as being allocated to its physical register.
511 * The alternative would be to have per-physical-register classes, which
512 * would just be silly.
514 ra_set_node_reg(g
, first_mrf_node
+ i
, GEN7_MRF_HACK_START
+ i
);
516 /* Since we don't have any live/dead analysis on the MRFs, just mark all
517 * that are used as conflicting with all virtual GRFs.
520 if (i
< *first_used_mrf
)
523 for (unsigned j
= 0; j
< v
->alloc
.count
; j
++) {
524 ra_add_node_interference(g
, first_mrf_node
+ i
, j
);
531 fs_visitor::assign_regs(bool allow_spilling
, bool spill_all
)
533 /* Most of this allocation was written for a reg_width of 1
534 * (dispatch_width == 8). In extending to SIMD16, the code was
535 * left in place and it was converted to have the hardware
536 * registers it's allocating be contiguous physical pairs of regs
537 * for reg_width == 2.
539 int reg_width
= dispatch_width
/ 8;
540 unsigned hw_reg_mapping
[this->alloc
.count
];
541 int payload_node_count
= ALIGN(this->first_non_payload_grf
, reg_width
);
542 int rsi
= _mesa_logbase2(reg_width
); /* Which compiler->fs_reg_sets[] to use */
543 calculate_live_intervals();
545 int node_count
= this->alloc
.count
;
546 int first_payload_node
= node_count
;
547 node_count
+= payload_node_count
;
548 int first_mrf_hack_node
= node_count
;
549 if (devinfo
->gen
>= 7)
550 node_count
+= BRW_MAX_GRF
- GEN7_MRF_HACK_START
;
551 int grf127_send_hack_node
= node_count
;
552 if (devinfo
->gen
>= 8)
555 ra_alloc_interference_graph(compiler
->fs_reg_sets
[rsi
].regs
, node_count
);
557 for (unsigned i
= 0; i
< this->alloc
.count
; i
++) {
558 unsigned size
= this->alloc
.sizes
[i
];
561 assert(size
<= ARRAY_SIZE(compiler
->fs_reg_sets
[rsi
].classes
) &&
562 "Register allocation relies on split_virtual_grfs()");
563 c
= compiler
->fs_reg_sets
[rsi
].classes
[size
- 1];
565 /* Special case: on pre-GEN6 hardware that supports PLN, the
566 * second operand of a PLN instruction needs to be an
567 * even-numbered register, so we have a special register class
568 * wm_aligned_pairs_class to handle this case. pre-GEN6 always
569 * uses this->delta_xy[BRW_BARYCENTRIC_PERSPECTIVE_PIXEL] as the
570 * second operand of a PLN instruction (since it doesn't support
571 * any other interpolation modes). So all we need to do is find
572 * that register and set it to the appropriate class.
574 if (compiler
->fs_reg_sets
[rsi
].aligned_pairs_class
>= 0 &&
575 this->delta_xy
[BRW_BARYCENTRIC_PERSPECTIVE_PIXEL
].file
== VGRF
&&
576 this->delta_xy
[BRW_BARYCENTRIC_PERSPECTIVE_PIXEL
].nr
== i
) {
577 c
= compiler
->fs_reg_sets
[rsi
].aligned_pairs_class
;
580 ra_set_node_class(g
, i
, c
);
582 for (unsigned j
= 0; j
< i
; j
++) {
583 if (virtual_grf_interferes(i
, j
)) {
584 ra_add_node_interference(g
, i
, j
);
589 /* Certain instructions can't safely use the same register for their
590 * sources and destination. Add interference.
592 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
593 if (inst
->dst
.file
== VGRF
&& inst
->has_source_and_destination_hazard()) {
594 for (unsigned i
= 0; i
< 3; i
++) {
595 if (inst
->src
[i
].file
== VGRF
) {
596 ra_add_node_interference(g
, inst
->dst
.nr
, inst
->src
[i
].nr
);
602 setup_payload_interference(g
, payload_node_count
, first_payload_node
);
603 if (devinfo
->gen
>= 7) {
604 int first_used_mrf
= BRW_MAX_MRF(devinfo
->gen
);
605 setup_mrf_hack_interference(this, g
, first_mrf_hack_node
,
608 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
609 /* When we do send-from-GRF for FB writes, we need to ensure that
610 * the last write instruction sends from a high register. This is
611 * because the vertex fetcher wants to start filling the low
612 * payload registers while the pixel data port is still working on
613 * writing out the memory. If we don't do this, we get rendering
616 * We could just do "something high". Instead, we just pick the
617 * highest register that works.
620 const int vgrf
= inst
->opcode
== SHADER_OPCODE_SEND
?
621 inst
->src
[2].nr
: inst
->src
[0].nr
;
622 int size
= alloc
.sizes
[vgrf
];
623 int reg
= compiler
->fs_reg_sets
[rsi
].class_to_ra_reg_range
[size
] - 1;
625 /* If something happened to spill, we want to push the EOT send
626 * register early enough in the register file that we don't
627 * conflict with any used MRF hack registers.
629 reg
-= BRW_MAX_MRF(devinfo
->gen
) - first_used_mrf
;
631 ra_set_node_reg(g
, vgrf
, reg
);
637 /* In 16-wide instructions we have an issue where a compressed
638 * instruction is actually two instructions executed simultaneously.
639 * It's actually ok to have the source and destination registers be
640 * the same. In this case, each instruction over-writes its own
641 * source and there's no problem. The real problem here is if the
642 * source and destination registers are off by one. Then you can end
643 * up in a scenario where the first instruction over-writes the
644 * source of the second instruction. Since the compiler doesn't know
645 * about this level of granularity, we simply make the source and
646 * destination interfere.
648 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
649 if (inst
->exec_size
< 16 || inst
->dst
.file
!= VGRF
)
652 for (int i
= 0; i
< inst
->sources
; ++i
) {
653 if (inst
->src
[i
].file
== VGRF
) {
654 ra_add_node_interference(g
, inst
->dst
.nr
, inst
->src
[i
].nr
);
659 if (devinfo
->gen
>= 8) {
660 /* At Intel Broadwell PRM, vol 07, section "Instruction Set Reference",
661 * subsection "EUISA Instructions", Send Message (page 990):
663 * "r127 must not be used for return address when there is a src and
664 * dest overlap in send instruction."
666 * We are avoiding using grf127 as part of the destination of send
667 * messages adding a node interference to the grf127_send_hack_node.
668 * This node has a fixed asignment to grf127.
670 * We don't apply it to SIMD16 because previous code avoids any register
671 * overlap between sources and destination.
673 ra_set_node_reg(g
, grf127_send_hack_node
, 127);
674 if (dispatch_width
== 8) {
675 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
676 if (inst
->is_send_from_grf() && inst
->dst
.file
== VGRF
)
677 ra_add_node_interference(g
, inst
->dst
.nr
, grf127_send_hack_node
);
681 if (spilled_any_registers
) {
682 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
683 /* Spilling instruction are genereated as SEND messages from MRF
684 * but as Gen7+ supports sending from GRF the driver will maps
685 * assingn these MRF registers to a GRF. Implementations reuses
686 * the dest of the send message as source. So as we will have an
687 * overlap for sure, we create an interference between destination
690 if ((inst
->opcode
== SHADER_OPCODE_GEN7_SCRATCH_READ
||
691 inst
->opcode
== SHADER_OPCODE_GEN4_SCRATCH_READ
) &&
692 inst
->dst
.file
== VGRF
)
693 ra_add_node_interference(g
, inst
->dst
.nr
, grf127_send_hack_node
);
698 /* From the Skylake PRM Vol. 2a docs for sends:
700 * "It is required that the second block of GRFs does not overlap with
703 * Normally, this is taken care of by fixup_sends_duplicate_payload() but
704 * in the case where one of the registers is an undefined value, the
705 * register allocator may decide that they don't interfere even though
706 * they're used as sources in the same instruction. We also need to add
709 if (devinfo
->gen
>= 9) {
710 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
711 if (inst
->opcode
== SHADER_OPCODE_SEND
&& inst
->ex_mlen
> 0 &&
712 inst
->src
[2].file
== VGRF
&&
713 inst
->src
[3].file
== VGRF
&&
714 inst
->src
[2].nr
!= inst
->src
[3].nr
) {
715 for (unsigned i
= 0; i
< inst
->mlen
; i
++) {
716 for (unsigned j
= 0; j
< inst
->ex_mlen
; j
++) {
717 ra_add_node_interference(g
, inst
->src
[2].nr
+ i
,
718 inst
->src
[3].nr
+ j
);
725 /* Debug of register spilling: Go spill everything. */
726 if (unlikely(spill_all
)) {
727 int reg
= choose_spill_reg(g
);
736 if (!ra_allocate(g
)) {
737 /* Failed to allocate registers. Spill a reg, and the caller will
738 * loop back into here to try again.
740 int reg
= choose_spill_reg(g
);
743 fail("no register to spill:\n");
744 dump_instructions(NULL
);
745 } else if (allow_spilling
) {
754 /* Get the chosen virtual registers for each node, and map virtual
755 * regs in the register classes back down to real hardware reg
758 this->grf_used
= payload_node_count
;
759 for (unsigned i
= 0; i
< this->alloc
.count
; i
++) {
760 int reg
= ra_get_node_reg(g
, i
);
762 hw_reg_mapping
[i
] = compiler
->fs_reg_sets
[rsi
].ra_reg_to_grf
[reg
];
763 this->grf_used
= MAX2(this->grf_used
,
764 hw_reg_mapping
[i
] + this->alloc
.sizes
[i
]);
767 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
768 assign_reg(hw_reg_mapping
, &inst
->dst
);
769 for (int i
= 0; i
< inst
->sources
; i
++) {
770 assign_reg(hw_reg_mapping
, &inst
->src
[i
]);
774 this->alloc
.count
= this->grf_used
;
783 * Maximum spill block size we expect to encounter in 32B units.
785 * This is somewhat arbitrary and doesn't necessarily limit the maximum
786 * variable size that can be spilled -- A higher value will allow a
787 * variable of a given size to be spilled more efficiently with a smaller
788 * number of scratch messages, but will increase the likelihood of a
789 * collision between the MRFs reserved for spilling and other MRFs used by
790 * the program (and possibly increase GRF register pressure on platforms
791 * without hardware MRFs), what could cause register allocation to fail.
793 * For the moment reserve just enough space so a register of 32 bit
794 * component type and natural region width can be spilled without splitting
795 * into multiple (force_writemask_all) scratch messages.
798 spill_max_size(const backend_shader
*s
)
800 /* FINISHME - On Gen7+ it should be possible to avoid this limit
801 * altogether by spilling directly from the temporary GRF
802 * allocated to hold the result of the instruction (and the
803 * scratch write header).
805 /* FINISHME - The shader's dispatch width probably belongs in
806 * backend_shader (or some nonexistent fs_shader class?)
807 * rather than in the visitor class.
809 return static_cast<const fs_visitor
*>(s
)->dispatch_width
/ 8;
813 * First MRF register available for spilling.
816 spill_base_mrf(const backend_shader
*s
)
818 return BRW_MAX_MRF(s
->devinfo
->gen
) - spill_max_size(s
) - 1;
823 emit_unspill(const fs_builder
&bld
, fs_reg dst
,
824 uint32_t spill_offset
, unsigned count
)
826 const gen_device_info
*devinfo
= bld
.shader
->devinfo
;
827 const unsigned reg_size
= dst
.component_size(bld
.dispatch_width()) /
829 assert(count
% reg_size
== 0);
831 for (unsigned i
= 0; i
< count
/ reg_size
; i
++) {
832 /* The Gen7 descriptor-based offset is 12 bits of HWORD units. Because
833 * the Gen7-style scratch block read is hardwired to BTI 255, on Gen9+
834 * it would cause the DC to do an IA-coherent read, what largely
835 * outweighs the slight advantage from not having to provide the address
836 * as part of the message header, so we're better off using plain old
839 bool gen7_read
= (devinfo
->gen
>= 7 && devinfo
->gen
< 9 &&
840 spill_offset
< (1 << 12) * REG_SIZE
);
841 fs_inst
*unspill_inst
= bld
.emit(gen7_read
?
842 SHADER_OPCODE_GEN7_SCRATCH_READ
:
843 SHADER_OPCODE_GEN4_SCRATCH_READ
,
845 unspill_inst
->offset
= spill_offset
;
848 unspill_inst
->base_mrf
= spill_base_mrf(bld
.shader
);
849 unspill_inst
->mlen
= 1; /* header contains offset */
852 dst
.offset
+= reg_size
* REG_SIZE
;
853 spill_offset
+= reg_size
* REG_SIZE
;
858 emit_spill(const fs_builder
&bld
, fs_reg src
,
859 uint32_t spill_offset
, unsigned count
)
861 const unsigned reg_size
= src
.component_size(bld
.dispatch_width()) /
863 assert(count
% reg_size
== 0);
865 for (unsigned i
= 0; i
< count
/ reg_size
; i
++) {
866 fs_inst
*spill_inst
=
867 bld
.emit(SHADER_OPCODE_GEN4_SCRATCH_WRITE
, bld
.null_reg_f(), src
);
868 src
.offset
+= reg_size
* REG_SIZE
;
869 spill_inst
->offset
= spill_offset
+ i
* reg_size
* REG_SIZE
;
870 spill_inst
->mlen
= 1 + reg_size
; /* header, value */
871 spill_inst
->base_mrf
= spill_base_mrf(bld
.shader
);
876 fs_visitor::choose_spill_reg(struct ra_graph
*g
)
878 float block_scale
= 1.0;
879 float spill_costs
[this->alloc
.count
];
880 bool no_spill
[this->alloc
.count
];
882 for (unsigned i
= 0; i
< this->alloc
.count
; i
++) {
883 spill_costs
[i
] = 0.0;
887 /* Calculate costs for spilling nodes. Call it a cost of 1 per
888 * spill/unspill we'll have to do, and guess that the insides of
889 * loops run 10 times.
891 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
892 for (unsigned int i
= 0; i
< inst
->sources
; i
++) {
893 if (inst
->src
[i
].file
== VGRF
)
894 spill_costs
[inst
->src
[i
].nr
] += regs_read(inst
, i
) * block_scale
;
897 if (inst
->dst
.file
== VGRF
)
898 spill_costs
[inst
->dst
.nr
] += regs_written(inst
) * block_scale
;
900 switch (inst
->opcode
) {
906 case BRW_OPCODE_WHILE
:
915 case BRW_OPCODE_ENDIF
:
919 case SHADER_OPCODE_GEN4_SCRATCH_WRITE
:
920 if (inst
->src
[0].file
== VGRF
)
921 no_spill
[inst
->src
[0].nr
] = true;
924 case SHADER_OPCODE_GEN4_SCRATCH_READ
:
925 case SHADER_OPCODE_GEN7_SCRATCH_READ
:
926 if (inst
->dst
.file
== VGRF
)
927 no_spill
[inst
->dst
.nr
] = true;
935 for (unsigned i
= 0; i
< this->alloc
.count
; i
++) {
937 ra_set_node_spill_cost(g
, i
, spill_costs
[i
]);
940 return ra_get_best_spill_node(g
);
944 fs_visitor::spill_reg(unsigned spill_reg
)
946 int size
= alloc
.sizes
[spill_reg
];
947 unsigned int spill_offset
= last_scratch
;
948 assert(ALIGN(spill_offset
, 16) == spill_offset
); /* oword read/write req. */
950 /* Spills may use MRFs 13-15 in the SIMD16 case. Our texturing is done
951 * using up to 11 MRFs starting from either m1 or m2, and fb writes can use
952 * up to m13 (gen6+ simd16: 2 header + 8 color + 2 src0alpha + 2 omask) or
953 * m15 (gen4-5 simd16: 2 header + 8 color + 1 aads + 2 src depth + 2 dst
954 * depth), starting from m1. In summary: We may not be able to spill in
955 * SIMD16 mode, because we'd stomp the FB writes.
957 if (!spilled_any_registers
) {
958 bool mrf_used
[BRW_MAX_MRF(devinfo
->gen
)];
959 get_used_mrfs(this, mrf_used
);
961 for (int i
= spill_base_mrf(this); i
< BRW_MAX_MRF(devinfo
->gen
); i
++) {
963 fail("Register spilling not supported with m%d used", i
);
968 spilled_any_registers
= true;
971 last_scratch
+= size
* REG_SIZE
;
973 /* Generate spill/unspill instructions for the objects being
974 * spilled. Right now, we spill or unspill the whole thing to a
975 * virtual grf of the same size. For most instructions, though, we
976 * could just spill/unspill the GRF being accessed.
978 foreach_block_and_inst (block
, fs_inst
, inst
, cfg
) {
979 const fs_builder ibld
= fs_builder(this, block
, inst
);
981 for (unsigned int i
= 0; i
< inst
->sources
; i
++) {
982 if (inst
->src
[i
].file
== VGRF
&&
983 inst
->src
[i
].nr
== spill_reg
) {
984 int count
= regs_read(inst
, i
);
985 int subset_spill_offset
= spill_offset
+
986 ROUND_DOWN_TO(inst
->src
[i
].offset
, REG_SIZE
);
987 fs_reg
unspill_dst(VGRF
, alloc
.allocate(count
));
989 inst
->src
[i
].nr
= unspill_dst
.nr
;
990 inst
->src
[i
].offset
%= REG_SIZE
;
992 /* We read the largest power-of-two divisor of the register count
993 * (because only POT scratch read blocks are allowed by the
994 * hardware) up to the maximum supported block size.
996 const unsigned width
=
997 MIN2(32, 1u << (ffs(MAX2(1, count
) * 8) - 1));
999 /* Set exec_all() on unspill messages under the (rather
1000 * pessimistic) assumption that there is no one-to-one
1001 * correspondence between channels of the spilled variable in
1002 * scratch space and the scratch read message, which operates on
1003 * 32 bit channels. It shouldn't hurt in any case because the
1004 * unspill destination is a block-local temporary.
1006 emit_unspill(ibld
.exec_all().group(width
, 0),
1007 unspill_dst
, subset_spill_offset
, count
);
1011 if (inst
->dst
.file
== VGRF
&&
1012 inst
->dst
.nr
== spill_reg
) {
1013 int subset_spill_offset
= spill_offset
+
1014 ROUND_DOWN_TO(inst
->dst
.offset
, REG_SIZE
);
1015 fs_reg
spill_src(VGRF
, alloc
.allocate(regs_written(inst
)));
1017 inst
->dst
.nr
= spill_src
.nr
;
1018 inst
->dst
.offset
%= REG_SIZE
;
1020 /* If we're immediately spilling the register, we should not use
1021 * destination dependency hints. Doing so will cause the GPU do
1022 * try to read and write the register at the same time and may
1025 inst
->no_dd_clear
= false;
1026 inst
->no_dd_check
= false;
1028 /* Calculate the execution width of the scratch messages (which work
1029 * in terms of 32 bit components so we have a fixed number of eight
1030 * channels per spilled register). We attempt to write one
1031 * exec_size-wide component of the variable at a time without
1032 * exceeding the maximum number of (fake) MRF registers reserved for
1035 const unsigned width
= 8 * MIN2(
1036 DIV_ROUND_UP(inst
->dst
.component_size(inst
->exec_size
), REG_SIZE
),
1037 spill_max_size(this));
1039 /* Spills should only write data initialized by the instruction for
1040 * whichever channels are enabled in the excution mask. If that's
1041 * not possible we'll have to emit a matching unspill before the
1042 * instruction and set force_writemask_all on the spill.
1044 const bool per_channel
=
1045 inst
->dst
.is_contiguous() && type_sz(inst
->dst
.type
) == 4 &&
1046 inst
->exec_size
== width
;
1048 /* Builder used to emit the scratch messages. */
1049 const fs_builder ubld
= ibld
.exec_all(!per_channel
).group(width
, 0);
1051 /* If our write is going to affect just part of the
1052 * regs_written(inst), then we need to unspill the destination since
1053 * we write back out all of the regs_written(). If the original
1054 * instruction had force_writemask_all set and is not a partial
1055 * write, there should be no need for the unspill since the
1056 * instruction will be overwriting the whole destination in any case.
1058 if (inst
->is_partial_write() ||
1059 (!inst
->force_writemask_all
&& !per_channel
))
1060 emit_unspill(ubld
, spill_src
, subset_spill_offset
,
1061 regs_written(inst
));
1063 emit_spill(ubld
.at(block
, inst
->next
), spill_src
,
1064 subset_spill_offset
, regs_written(inst
));
1068 invalidate_live_intervals();