src/intel/compiler/brw_fs_register_coalesce.cpp

   1 /*
   2  * Copyright © 2012 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  */
  23
  24 /** @file brw_fs_register_coalesce.cpp
  25  *
  26  * Implements register coalescing: Checks if the two registers involved in a
  27  * raw move don't interfere, in which case they can both be stored in the same
  28  * place and the MOV removed.
  29  *
  30  * To do this, all uses of the source of the MOV in the shader are replaced
  31  * with the destination of the MOV. For example:
  32  *
  33  * add vgrf3:F, vgrf1:F, vgrf2:F
  34  * mov vgrf4:F, vgrf3:F
  35  * mul vgrf5:F, vgrf5:F, vgrf4:F
  36  *
  37  * becomes
  38  *
  39  * add vgrf4:F, vgrf1:F, vgrf2:F
  40  * mul vgrf5:F, vgrf5:F, vgrf4:F
  41  */
  42
  43 #include "brw_fs.h"
  44 #include "brw_cfg.h"
  45 #include "brw_fs_live_variables.h"
  46
  47 using namespace brw;
  48
  49 static bool
  50 is_nop_mov(const fs_inst *inst)
  51 {
  52    if (inst->opcode == SHADER_OPCODE_LOAD_PAYLOAD) {
  53       fs_reg dst = inst->dst;
  54       for (int i = 0; i < inst->sources; i++) {
  55          if (!dst.equals(inst->src[i])) {
  56             return false;
  57          }
  58          dst.offset += (i < inst->header_size ? REG_SIZE :
  59                         inst->exec_size * dst.stride *
  60                         type_sz(inst->src[i].type));
  61       }
  62       return true;
  63    } else if (inst->opcode == BRW_OPCODE_MOV) {
  64       return inst->dst.equals(inst->src[0]);
  65    }
  66
  67    return false;
  68 }
  69
  70 static bool
  71 is_coalesce_candidate(const fs_visitor *v, const fs_inst *inst)
  72 {
  73    if ((inst->opcode != BRW_OPCODE_MOV &&
  74         inst->opcode != SHADER_OPCODE_LOAD_PAYLOAD) ||
  75        inst->is_partial_write() ||
  76        inst->saturate ||
  77        inst->src[0].file != VGRF ||
  78        inst->src[0].negate ||
  79        inst->src[0].abs ||
  80        !inst->src[0].is_contiguous() ||
  81        inst->dst.file != VGRF ||
  82        inst->dst.type != inst->src[0].type) {
  83       return false;
  84    }
  85
  86    if (v->alloc.sizes[inst->src[0].nr] >
  87        v->alloc.sizes[inst->dst.nr])
  88       return false;
  89
  90    if (inst->opcode == SHADER_OPCODE_LOAD_PAYLOAD) {
  91       if (!is_coalescing_payload(v->alloc, inst)) {
  92          return false;
  93       }
  94    }
  95
  96    return true;
  97 }
  98
  99 static bool
 100 can_coalesce_vars(brw::fs_live_variables *live_intervals,
 101                   const cfg_t *cfg, const fs_inst *inst,
 102                   int dst_var, int src_var)
 103 {
 104    if (!live_intervals->vars_interfere(src_var, dst_var))
 105       return true;
 106
 107    int dst_start = live_intervals->start[dst_var];
 108    int dst_end = live_intervals->end[dst_var];
 109    int src_start = live_intervals->start[src_var];
 110    int src_end = live_intervals->end[src_var];
 111
 112    /* Variables interfere and one line range isn't a subset of the other. */
 113    if ((dst_end > src_end && src_start < dst_start) ||
 114        (src_end > dst_end && dst_start < src_start))
 115       return false;
 116
 117    /* Check for a write to either register in the intersection of their live
 118     * ranges.
 119     */
 120    int start_ip = MAX2(dst_start, src_start);
 121    int end_ip = MIN2(dst_end, src_end);
 122
 123    foreach_block(block, cfg) {
 124       if (block->end_ip < start_ip)
 125          continue;
 126
 127       int scan_ip = block->start_ip - 1;
 128
 129       foreach_inst_in_block(fs_inst, scan_inst, block) {
 130          scan_ip++;
 131
 132          /* Ignore anything before the intersection of the live ranges */
 133          if (scan_ip < start_ip)
 134             continue;
 135
 136          /* Ignore the copying instruction itself */
 137          if (scan_inst == inst)
 138             continue;
 139
 140          if (scan_ip > end_ip)
 141             return true; /* registers do not interfere */
 142
 143          if (regions_overlap(scan_inst->dst, scan_inst->size_written,
 144                              inst->dst, inst->size_written) ||
 145              regions_overlap(scan_inst->dst, scan_inst->size_written,
 146                              inst->src[0], inst->size_read(0)))
 147             return false; /* registers interfere */
 148       }
 149    }
 150
 151    return true;
 152 }
 153
 154 bool
 155 fs_visitor::register_coalesce()
 156 {
 157    bool progress = false;
 158
 159    calculate_live_intervals();
 160
 161    int src_size = 0;
 162    int channels_remaining = 0;
 163    unsigned src_reg = ~0u, dst_reg = ~0u;
 164    int dst_reg_offset[MAX_VGRF_SIZE];
 165    fs_inst *mov[MAX_VGRF_SIZE];
 166    int dst_var[MAX_VGRF_SIZE];
 167    int src_var[MAX_VGRF_SIZE];
 168
 169    foreach_block_and_inst(block, fs_inst, inst, cfg) {
 170       if (!is_coalesce_candidate(this, inst))
 171          continue;
 172
 173       if (is_nop_mov(inst)) {
 174          inst->opcode = BRW_OPCODE_NOP;
 175          progress = true;
 176          continue;
 177       }
 178
 179       if (src_reg != inst->src[0].nr) {
 180          src_reg = inst->src[0].nr;
 181
 182          src_size = alloc.sizes[inst->src[0].nr];
 183          assert(src_size <= MAX_VGRF_SIZE);
 184
 185          channels_remaining = src_size;
 186          memset(mov, 0, sizeof(mov));
 187
 188          dst_reg = inst->dst.nr;
 189       }
 190
 191       if (dst_reg != inst->dst.nr)
 192          continue;
 193
 194       if (inst->opcode == SHADER_OPCODE_LOAD_PAYLOAD) {
 195          for (int i = 0; i < src_size; i++) {
 196             dst_reg_offset[i] = i;
 197          }
 198          mov[0] = inst;
 199          channels_remaining -= regs_written(inst);
 200       } else {
 201          const int offset = inst->src[0].offset / REG_SIZE;
 202          if (mov[offset]) {
 203             /* This is the second time that this offset in the register has
 204              * been set.  This means, in particular, that inst->dst was
 205              * live before this instruction and that the live ranges of
 206              * inst->dst and inst->src[0] overlap and we can't coalesce the
 207              * two variables.  Let's ensure that doesn't happen.
 208              */
 209             channels_remaining = -1;
 210             continue;
 211          }
 212          for (unsigned i = 0; i < MAX2(inst->size_written / REG_SIZE, 1); i++)
 213             dst_reg_offset[offset + i] = inst->dst.offset / REG_SIZE + i;
 214          mov[offset] = inst;
 215          channels_remaining -= regs_written(inst);
 216       }
 217
 218       if (channels_remaining)
 219          continue;
 220
 221       bool can_coalesce = true;
 222       for (int i = 0; i < src_size; i++) {
 223          if (dst_reg_offset[i] != dst_reg_offset[0] + i) {
 224             /* Registers are out-of-order. */
 225             can_coalesce = false;
 226             src_reg = ~0u;
 227             break;
 228          }
 229
 230          dst_var[i] = live_intervals->var_from_vgrf[dst_reg] + dst_reg_offset[i];
 231          src_var[i] = live_intervals->var_from_vgrf[src_reg] + i;
 232
 233          if (!can_coalesce_vars(live_intervals, cfg, inst,
 234                                 dst_var[i], src_var[i])) {
 235             can_coalesce = false;
 236             src_reg = ~0u;
 237             break;
 238          }
 239       }
 240
 241       if (!can_coalesce)
 242          continue;
 243
 244       progress = true;
 245
 246       for (int i = 0; i < src_size; i++) {
 247          if (mov[i]) {
 248             mov[i]->opcode = BRW_OPCODE_NOP;
 249             mov[i]->conditional_mod = BRW_CONDITIONAL_NONE;
 250             mov[i]->dst = reg_undef;
 251             for (int j = 0; j < mov[i]->sources; j++) {
 252                mov[i]->src[j] = reg_undef;
 253             }
 254          }
 255       }
 256
 257       foreach_block_and_inst(block, fs_inst, scan_inst, cfg) {
 258          if (scan_inst->dst.file == VGRF &&
 259              scan_inst->dst.nr == src_reg) {
 260             scan_inst->dst.nr = dst_reg;
 261             scan_inst->dst.offset = scan_inst->dst.offset % REG_SIZE +
 262                dst_reg_offset[scan_inst->dst.offset / REG_SIZE] * REG_SIZE;
 263          }
 264
 265          for (int j = 0; j < scan_inst->sources; j++) {
 266             if (scan_inst->src[j].file == VGRF &&
 267                 scan_inst->src[j].nr == src_reg) {
 268                scan_inst->src[j].nr = dst_reg;
 269                scan_inst->src[j].offset = scan_inst->src[j].offset % REG_SIZE +
 270                   dst_reg_offset[scan_inst->src[j].offset / REG_SIZE] * REG_SIZE;
 271             }
 272          }
 273       }
 274
 275       for (int i = 0; i < src_size; i++) {
 276          live_intervals->start[dst_var[i]] =
 277             MIN2(live_intervals->start[dst_var[i]],
 278                  live_intervals->start[src_var[i]]);
 279          live_intervals->end[dst_var[i]] =
 280             MAX2(live_intervals->end[dst_var[i]],
 281                  live_intervals->end[src_var[i]]);
 282       }
 283       src_reg = ~0u;
 284    }
 285
 286    if (progress) {
 287       foreach_block_and_inst_safe (block, backend_instruction, inst, cfg) {
 288          if (inst->opcode == BRW_OPCODE_NOP) {
 289             inst->remove(block);
 290          }
 291       }
 292
 293       invalidate_analysis(DEPENDENCY_EVERYTHING);
 294    }
 295
 296    return progress;
 297 }