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24 /** @file brw_fs_register_coalesce.cpp
26 * Implements register coalescing: Checks if the two registers involved in a
27 * raw move don't interfere, in which case they can both be stored in the same
28 * place and the MOV removed.
30 * To do this, all uses of the source of the MOV in the shader are replaced
31 * with the destination of the MOV. For example:
33 * add vgrf3:F, vgrf1:F, vgrf2:F
34 * mov vgrf4:F, vgrf3:F
35 * mul vgrf5:F, vgrf5:F, vgrf4:F
39 * add vgrf4:F, vgrf1:F, vgrf2:F
40 * mul vgrf5:F, vgrf5:F, vgrf4:F
45 #include "brw_fs_live_variables.h"
50 is_nop_mov(const fs_inst
*inst
)
52 if (inst
->opcode
== SHADER_OPCODE_LOAD_PAYLOAD
) {
53 fs_reg dst
= inst
->dst
;
54 for (int i
= 0; i
< inst
->sources
; i
++) {
55 if (!dst
.equals(inst
->src
[i
])) {
58 dst
.offset
+= (i
< inst
->header_size
? REG_SIZE
:
59 inst
->exec_size
* dst
.stride
*
60 type_sz(inst
->src
[i
].type
));
63 } else if (inst
->opcode
== BRW_OPCODE_MOV
) {
64 return inst
->dst
.equals(inst
->src
[0]);
71 is_coalesce_candidate(const fs_visitor
*v
, const fs_inst
*inst
)
73 if ((inst
->opcode
!= BRW_OPCODE_MOV
&&
74 inst
->opcode
!= SHADER_OPCODE_LOAD_PAYLOAD
) ||
75 inst
->is_partial_write() ||
77 inst
->src
[0].file
!= VGRF
||
78 inst
->src
[0].negate
||
80 !inst
->src
[0].is_contiguous() ||
81 inst
->dst
.file
!= VGRF
||
82 inst
->dst
.type
!= inst
->src
[0].type
) {
86 if (v
->alloc
.sizes
[inst
->src
[0].nr
] >
87 v
->alloc
.sizes
[inst
->dst
.nr
])
90 if (inst
->opcode
== SHADER_OPCODE_LOAD_PAYLOAD
) {
91 if (!is_coalescing_payload(v
->alloc
, inst
)) {
100 can_coalesce_vars(const fs_live_variables
&live
,
101 const cfg_t
*cfg
, const fs_inst
*inst
,
102 int dst_var
, int src_var
)
104 if (!live
.vars_interfere(src_var
, dst_var
))
107 int dst_start
= live
.start
[dst_var
];
108 int dst_end
= live
.end
[dst_var
];
109 int src_start
= live
.start
[src_var
];
110 int src_end
= live
.end
[src_var
];
112 /* Variables interfere and one line range isn't a subset of the other. */
113 if ((dst_end
> src_end
&& src_start
< dst_start
) ||
114 (src_end
> dst_end
&& dst_start
< src_start
))
117 /* Check for a write to either register in the intersection of their live
120 int start_ip
= MAX2(dst_start
, src_start
);
121 int end_ip
= MIN2(dst_end
, src_end
);
123 foreach_block(scan_block
, cfg
) {
124 if (scan_block
->end_ip
< start_ip
)
127 int scan_ip
= scan_block
->start_ip
- 1;
129 foreach_inst_in_block(fs_inst
, scan_inst
, scan_block
) {
132 /* Ignore anything before the intersection of the live ranges */
133 if (scan_ip
< start_ip
)
136 /* Ignore the copying instruction itself */
137 if (scan_inst
== inst
)
140 if (scan_ip
> end_ip
)
141 return true; /* registers do not interfere */
143 if (regions_overlap(scan_inst
->dst
, scan_inst
->size_written
,
144 inst
->dst
, inst
->size_written
) ||
145 regions_overlap(scan_inst
->dst
, scan_inst
->size_written
,
146 inst
->src
[0], inst
->size_read(0)))
147 return false; /* registers interfere */
155 fs_visitor::register_coalesce()
157 bool progress
= false;
158 fs_live_variables
&live
= live_analysis
.require();
160 int channels_remaining
= 0;
161 unsigned src_reg
= ~0u, dst_reg
= ~0u;
162 int dst_reg_offset
[MAX_VGRF_SIZE
];
163 fs_inst
*mov
[MAX_VGRF_SIZE
];
164 int dst_var
[MAX_VGRF_SIZE
];
165 int src_var
[MAX_VGRF_SIZE
];
167 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
168 if (!is_coalesce_candidate(this, inst
))
171 if (is_nop_mov(inst
)) {
172 inst
->opcode
= BRW_OPCODE_NOP
;
177 if (src_reg
!= inst
->src
[0].nr
) {
178 src_reg
= inst
->src
[0].nr
;
180 src_size
= alloc
.sizes
[inst
->src
[0].nr
];
181 assert(src_size
<= MAX_VGRF_SIZE
);
183 channels_remaining
= src_size
;
184 memset(mov
, 0, sizeof(mov
));
186 dst_reg
= inst
->dst
.nr
;
189 if (dst_reg
!= inst
->dst
.nr
)
192 if (inst
->opcode
== SHADER_OPCODE_LOAD_PAYLOAD
) {
193 for (int i
= 0; i
< src_size
; i
++) {
194 dst_reg_offset
[i
] = i
;
197 channels_remaining
-= regs_written(inst
);
199 const int offset
= inst
->src
[0].offset
/ REG_SIZE
;
201 /* This is the second time that this offset in the register has
202 * been set. This means, in particular, that inst->dst was
203 * live before this instruction and that the live ranges of
204 * inst->dst and inst->src[0] overlap and we can't coalesce the
205 * two variables. Let's ensure that doesn't happen.
207 channels_remaining
= -1;
210 for (unsigned i
= 0; i
< MAX2(inst
->size_written
/ REG_SIZE
, 1); i
++)
211 dst_reg_offset
[offset
+ i
] = inst
->dst
.offset
/ REG_SIZE
+ i
;
213 channels_remaining
-= regs_written(inst
);
216 if (channels_remaining
)
219 bool can_coalesce
= true;
220 for (int i
= 0; i
< src_size
; i
++) {
221 if (dst_reg_offset
[i
] != dst_reg_offset
[0] + i
) {
222 /* Registers are out-of-order. */
223 can_coalesce
= false;
228 dst_var
[i
] = live
.var_from_vgrf
[dst_reg
] + dst_reg_offset
[i
];
229 src_var
[i
] = live
.var_from_vgrf
[src_reg
] + i
;
231 if (!can_coalesce_vars(live
, cfg
, inst
, dst_var
[i
], src_var
[i
])) {
232 can_coalesce
= false;
243 for (int i
= 0; i
< src_size
; i
++) {
245 mov
[i
]->opcode
= BRW_OPCODE_NOP
;
246 mov
[i
]->conditional_mod
= BRW_CONDITIONAL_NONE
;
247 mov
[i
]->dst
= reg_undef
;
248 for (int j
= 0; j
< mov
[i
]->sources
; j
++) {
249 mov
[i
]->src
[j
] = reg_undef
;
254 foreach_block_and_inst(block
, fs_inst
, scan_inst
, cfg
) {
255 if (scan_inst
->dst
.file
== VGRF
&&
256 scan_inst
->dst
.nr
== src_reg
) {
257 scan_inst
->dst
.nr
= dst_reg
;
258 scan_inst
->dst
.offset
= scan_inst
->dst
.offset
% REG_SIZE
+
259 dst_reg_offset
[scan_inst
->dst
.offset
/ REG_SIZE
] * REG_SIZE
;
262 for (int j
= 0; j
< scan_inst
->sources
; j
++) {
263 if (scan_inst
->src
[j
].file
== VGRF
&&
264 scan_inst
->src
[j
].nr
== src_reg
) {
265 scan_inst
->src
[j
].nr
= dst_reg
;
266 scan_inst
->src
[j
].offset
= scan_inst
->src
[j
].offset
% REG_SIZE
+
267 dst_reg_offset
[scan_inst
->src
[j
].offset
/ REG_SIZE
] * REG_SIZE
;
272 for (int i
= 0; i
< src_size
; i
++) {
273 live
.start
[dst_var
[i
]] = MIN2(live
.start
[dst_var
[i
]],
274 live
.start
[src_var
[i
]]);
275 live
.end
[dst_var
[i
]] = MAX2(live
.end
[dst_var
[i
]],
276 live
.end
[src_var
[i
]]);
282 foreach_block_and_inst_safe (block
, backend_instruction
, inst
, cfg
) {
283 if (inst
->opcode
== BRW_OPCODE_NOP
) {
288 invalidate_analysis(DEPENDENCY_INSTRUCTIONS
);