2 * Copyright © 2010 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 /** @file brw_fs_visitor.cpp
26 * This file supports generating the FS LIR from the GLSL IR. The LIR
27 * makes it easier to do backend-specific optimizations than doing so
28 * in the GLSL IR or in the native code.
31 #include "compiler/glsl_types.h"
35 /* Sample from the MCS surface attached to this multisample texture. */
37 fs_visitor::emit_mcs_fetch(const fs_reg
&coordinate
, unsigned components
,
38 const fs_reg
&texture
)
40 const fs_reg dest
= vgrf(glsl_type::uvec4_type
);
42 fs_reg srcs
[TEX_LOGICAL_NUM_SRCS
];
43 srcs
[TEX_LOGICAL_SRC_COORDINATE
] = coordinate
;
44 srcs
[TEX_LOGICAL_SRC_SURFACE
] = texture
;
45 srcs
[TEX_LOGICAL_SRC_SAMPLER
] = brw_imm_ud(0);
46 srcs
[TEX_LOGICAL_SRC_COORD_COMPONENTS
] = brw_imm_d(components
);
47 srcs
[TEX_LOGICAL_SRC_GRAD_COMPONENTS
] = brw_imm_d(0);
49 fs_inst
*inst
= bld
.emit(SHADER_OPCODE_TXF_MCS_LOGICAL
, dest
, srcs
,
52 /* We only care about one or two regs of response, but the sampler always
55 inst
->size_written
= 4 * dest
.component_size(inst
->exec_size
);
61 * Apply workarounds for Gen6 gather with UINT/SINT
64 fs_visitor::emit_gen6_gather_wa(uint8_t wa
, fs_reg dst
)
69 int width
= (wa
& WA_8BIT
) ? 8 : 16;
71 for (int i
= 0; i
< 4; i
++) {
72 fs_reg dst_f
= retype(dst
, BRW_REGISTER_TYPE_F
);
73 /* Convert from UNORM to UINT */
74 bld
.MUL(dst_f
, dst_f
, brw_imm_f((1 << width
) - 1));
78 /* Reinterpret the UINT value as a signed INT value by
79 * shifting the sign bit into place, then shifting back
82 bld
.SHL(dst
, dst
, brw_imm_d(32 - width
));
83 bld
.ASR(dst
, dst
, brw_imm_d(32 - width
));
86 dst
= offset(dst
, bld
, 1);
90 /** Emits a dummy fragment shader consisting of magenta for bringup purposes. */
92 fs_visitor::emit_dummy_fs()
94 int reg_width
= dispatch_width
/ 8;
96 /* Everyone's favorite color. */
97 const float color
[4] = { 1.0, 0.0, 1.0, 0.0 };
98 for (int i
= 0; i
< 4; i
++) {
99 bld
.MOV(fs_reg(MRF
, 2 + i
* reg_width
, BRW_REGISTER_TYPE_F
),
100 brw_imm_f(color
[i
]));
104 write
= bld
.emit(FS_OPCODE_FB_WRITE
);
106 write
->last_rt
= true;
107 if (devinfo
->gen
>= 6) {
109 write
->mlen
= 4 * reg_width
;
111 write
->header_size
= 2;
113 write
->mlen
= 2 + 4 * reg_width
;
116 /* Tell the SF we don't have any inputs. Gen4-5 require at least one
117 * varying to avoid GPU hangs, so set that.
119 struct brw_wm_prog_data
*wm_prog_data
= brw_wm_prog_data(this->prog_data
);
120 wm_prog_data
->num_varying_inputs
= devinfo
->gen
< 6 ? 1 : 0;
121 memset(wm_prog_data
->urb_setup
, -1,
122 sizeof(wm_prog_data
->urb_setup
[0]) * VARYING_SLOT_MAX
);
124 /* We don't have any uniforms. */
125 stage_prog_data
->nr_params
= 0;
126 stage_prog_data
->nr_pull_params
= 0;
127 stage_prog_data
->curb_read_length
= 0;
128 stage_prog_data
->dispatch_grf_start_reg
= 2;
129 wm_prog_data
->dispatch_grf_start_reg_16
= 2;
130 wm_prog_data
->dispatch_grf_start_reg_32
= 2;
131 grf_used
= 1; /* Gen4-5 don't allow zero GRF blocks */
136 /* The register location here is relative to the start of the URB
137 * data. It will get adjusted to be a real location before
138 * generate_code() time.
141 fs_visitor::interp_reg(int location
, int channel
)
143 assert(stage
== MESA_SHADER_FRAGMENT
);
144 struct brw_wm_prog_data
*prog_data
= brw_wm_prog_data(this->prog_data
);
145 int regnr
= prog_data
->urb_setup
[location
] * 4 + channel
;
146 assert(prog_data
->urb_setup
[location
] != -1);
148 return fs_reg(ATTR
, regnr
, BRW_REGISTER_TYPE_F
);
151 /** Emits the interpolation for the varying inputs. */
153 fs_visitor::emit_interpolation_setup_gen4()
155 struct brw_reg g1_uw
= retype(brw_vec1_grf(1, 0), BRW_REGISTER_TYPE_UW
);
157 fs_builder abld
= bld
.annotate("compute pixel centers");
158 this->pixel_x
= vgrf(glsl_type::uint_type
);
159 this->pixel_y
= vgrf(glsl_type::uint_type
);
160 this->pixel_x
.type
= BRW_REGISTER_TYPE_UW
;
161 this->pixel_y
.type
= BRW_REGISTER_TYPE_UW
;
162 abld
.ADD(this->pixel_x
,
163 fs_reg(stride(suboffset(g1_uw
, 4), 2, 4, 0)),
164 fs_reg(brw_imm_v(0x10101010)));
165 abld
.ADD(this->pixel_y
,
166 fs_reg(stride(suboffset(g1_uw
, 5), 2, 4, 0)),
167 fs_reg(brw_imm_v(0x11001100)));
169 abld
= bld
.annotate("compute pixel deltas from v0");
171 this->delta_xy
[BRW_BARYCENTRIC_PERSPECTIVE_PIXEL
] =
172 vgrf(glsl_type::vec2_type
);
173 const fs_reg
&delta_xy
= this->delta_xy
[BRW_BARYCENTRIC_PERSPECTIVE_PIXEL
];
174 const fs_reg
xstart(negate(brw_vec1_grf(1, 0)));
175 const fs_reg
ystart(negate(brw_vec1_grf(1, 1)));
177 if (devinfo
->has_pln
&& dispatch_width
== 16) {
178 for (unsigned i
= 0; i
< 2; i
++) {
179 abld
.half(i
).ADD(half(offset(delta_xy
, abld
, i
), 0),
180 half(this->pixel_x
, i
), xstart
);
181 abld
.half(i
).ADD(half(offset(delta_xy
, abld
, i
), 1),
182 half(this->pixel_y
, i
), ystart
);
185 abld
.ADD(offset(delta_xy
, abld
, 0), this->pixel_x
, xstart
);
186 abld
.ADD(offset(delta_xy
, abld
, 1), this->pixel_y
, ystart
);
189 abld
= bld
.annotate("compute pos.w and 1/pos.w");
190 /* Compute wpos.w. It's always in our setup, since it's needed to
191 * interpolate the other attributes.
193 this->wpos_w
= vgrf(glsl_type::float_type
);
194 abld
.emit(FS_OPCODE_LINTERP
, wpos_w
, delta_xy
,
195 component(interp_reg(VARYING_SLOT_POS
, 3), 0));
196 /* Compute the pixel 1/W value from wpos.w. */
197 this->pixel_w
= vgrf(glsl_type::float_type
);
198 abld
.emit(SHADER_OPCODE_RCP
, this->pixel_w
, wpos_w
);
201 /** Emits the interpolation for the varying inputs. */
203 fs_visitor::emit_interpolation_setup_gen6()
205 fs_builder abld
= bld
.annotate("compute pixel centers");
207 this->pixel_x
= vgrf(glsl_type::float_type
);
208 this->pixel_y
= vgrf(glsl_type::float_type
);
210 for (unsigned i
= 0; i
< DIV_ROUND_UP(dispatch_width
, 16); i
++) {
211 const fs_builder hbld
= abld
.group(MIN2(16, dispatch_width
), i
);
212 struct brw_reg gi_uw
= retype(brw_vec1_grf(1 + i
, 0), BRW_REGISTER_TYPE_UW
);
214 if (devinfo
->gen
>= 8 || dispatch_width
== 8) {
215 /* The "Register Region Restrictions" page says for BDW (and newer,
218 * "When destination spans two registers, the source may be one or
219 * two registers. The destination elements must be evenly split
220 * between the two registers."
222 * Thus we can do a single add(16) in SIMD8 or an add(32) in SIMD16
223 * to compute our pixel centers.
225 const fs_builder dbld
=
226 abld
.exec_all().group(hbld
.dispatch_width() * 2, 0);
227 fs_reg int_pixel_xy
= dbld
.vgrf(BRW_REGISTER_TYPE_UW
);
229 dbld
.ADD(int_pixel_xy
,
230 fs_reg(stride(suboffset(gi_uw
, 4), 1, 4, 0)),
231 fs_reg(brw_imm_v(0x11001010)));
233 hbld
.emit(FS_OPCODE_PIXEL_X
, offset(pixel_x
, hbld
, i
), int_pixel_xy
);
234 hbld
.emit(FS_OPCODE_PIXEL_Y
, offset(pixel_y
, hbld
, i
), int_pixel_xy
);
236 /* The "Register Region Restrictions" page says for SNB, IVB, HSW:
238 * "When destination spans two registers, the source MUST span
241 * Since the GRF source of the ADD will only read a single register,
242 * we must do two separate ADDs in SIMD16.
244 const fs_reg int_pixel_x
= hbld
.vgrf(BRW_REGISTER_TYPE_UW
);
245 const fs_reg int_pixel_y
= hbld
.vgrf(BRW_REGISTER_TYPE_UW
);
247 hbld
.ADD(int_pixel_x
,
248 fs_reg(stride(suboffset(gi_uw
, 4), 2, 4, 0)),
249 fs_reg(brw_imm_v(0x10101010)));
250 hbld
.ADD(int_pixel_y
,
251 fs_reg(stride(suboffset(gi_uw
, 5), 2, 4, 0)),
252 fs_reg(brw_imm_v(0x11001100)));
254 /* As of gen6, we can no longer mix float and int sources. We have
255 * to turn the integer pixel centers into floats for their actual
258 hbld
.MOV(offset(pixel_x
, hbld
, i
), int_pixel_x
);
259 hbld
.MOV(offset(pixel_y
, hbld
, i
), int_pixel_y
);
263 abld
= bld
.annotate("compute pos.w");
264 this->pixel_w
= fetch_payload_reg(abld
, payload
.source_w_reg
);
265 this->wpos_w
= vgrf(glsl_type::float_type
);
266 abld
.emit(SHADER_OPCODE_RCP
, this->wpos_w
, this->pixel_w
);
268 struct brw_wm_prog_data
*wm_prog_data
= brw_wm_prog_data(prog_data
);
270 for (int i
= 0; i
< BRW_BARYCENTRIC_MODE_COUNT
; ++i
) {
271 this->delta_xy
[i
] = fetch_payload_reg(
272 bld
, payload
.barycentric_coord_reg
[i
], BRW_REGISTER_TYPE_F
, 2);
275 uint32_t centroid_modes
= wm_prog_data
->barycentric_interp_modes
&
276 (1 << BRW_BARYCENTRIC_PERSPECTIVE_CENTROID
|
277 1 << BRW_BARYCENTRIC_NONPERSPECTIVE_CENTROID
);
279 if (devinfo
->needs_unlit_centroid_workaround
&& centroid_modes
) {
280 /* Get the pixel/sample mask into f0 so that we know which
281 * pixels are lit. Then, for each channel that is unlit,
282 * replace the centroid data with non-centroid data.
284 for (unsigned i
= 0; i
< DIV_ROUND_UP(dispatch_width
, 16); i
++) {
285 bld
.exec_all().group(1, 0)
286 .MOV(retype(brw_flag_reg(0, i
), BRW_REGISTER_TYPE_UW
),
287 retype(brw_vec1_grf(1 + i
, 7), BRW_REGISTER_TYPE_UW
));
290 for (int i
= 0; i
< BRW_BARYCENTRIC_MODE_COUNT
; ++i
) {
291 if (!(centroid_modes
& (1 << i
)))
294 const fs_reg
&pixel_delta_xy
= delta_xy
[i
- 1];
296 for (unsigned q
= 0; q
< dispatch_width
/ 8; q
++) {
297 for (unsigned c
= 0; c
< 2; c
++) {
298 const unsigned idx
= c
+ (q
& 2) + (q
& 1) * dispatch_width
/ 8;
300 BRW_PREDICATE_NORMAL
, true,
301 bld
.half(q
).MOV(horiz_offset(delta_xy
[i
], idx
* 8),
302 horiz_offset(pixel_delta_xy
, idx
* 8)));
309 static enum brw_conditional_mod
310 cond_for_alpha_func(GLenum func
)
314 return BRW_CONDITIONAL_G
;
316 return BRW_CONDITIONAL_GE
;
318 return BRW_CONDITIONAL_L
;
320 return BRW_CONDITIONAL_LE
;
322 return BRW_CONDITIONAL_EQ
;
324 return BRW_CONDITIONAL_NEQ
;
326 unreachable("Not reached");
331 * Alpha test support for when we compile it into the shader instead
332 * of using the normal fixed-function alpha test.
335 fs_visitor::emit_alpha_test()
337 assert(stage
== MESA_SHADER_FRAGMENT
);
338 brw_wm_prog_key
*key
= (brw_wm_prog_key
*) this->key
;
339 const fs_builder abld
= bld
.annotate("Alpha test");
342 if (key
->alpha_test_func
== GL_ALWAYS
)
345 if (key
->alpha_test_func
== GL_NEVER
) {
347 fs_reg some_reg
= fs_reg(retype(brw_vec8_grf(0, 0),
348 BRW_REGISTER_TYPE_UW
));
349 cmp
= abld
.CMP(bld
.null_reg_f(), some_reg
, some_reg
,
350 BRW_CONDITIONAL_NEQ
);
353 fs_reg color
= offset(outputs
[0], bld
, 3);
355 /* f0.1 &= func(color, ref) */
356 cmp
= abld
.CMP(bld
.null_reg_f(), color
, brw_imm_f(key
->alpha_test_ref
),
357 cond_for_alpha_func(key
->alpha_test_func
));
359 cmp
->predicate
= BRW_PREDICATE_NORMAL
;
360 cmp
->flag_subreg
= 1;
364 fs_visitor::emit_single_fb_write(const fs_builder
&bld
,
365 fs_reg color0
, fs_reg color1
,
366 fs_reg src0_alpha
, unsigned components
)
368 assert(stage
== MESA_SHADER_FRAGMENT
);
369 struct brw_wm_prog_data
*prog_data
= brw_wm_prog_data(this->prog_data
);
371 /* Hand over gl_FragDepth or the payload depth. */
372 const fs_reg dst_depth
= fetch_payload_reg(bld
, payload
.dest_depth_reg
);
373 fs_reg src_depth
, src_stencil
;
375 if (source_depth_to_render_target
) {
376 if (nir
->info
.outputs_written
& BITFIELD64_BIT(FRAG_RESULT_DEPTH
))
377 src_depth
= frag_depth
;
379 src_depth
= fetch_payload_reg(bld
, payload
.source_depth_reg
);
382 if (nir
->info
.outputs_written
& BITFIELD64_BIT(FRAG_RESULT_STENCIL
))
383 src_stencil
= frag_stencil
;
385 const fs_reg sources
[] = {
386 color0
, color1
, src0_alpha
, src_depth
, dst_depth
, src_stencil
,
387 (prog_data
->uses_omask
? sample_mask
: fs_reg()),
388 brw_imm_ud(components
)
390 assert(ARRAY_SIZE(sources
) - 1 == FB_WRITE_LOGICAL_SRC_COMPONENTS
);
391 fs_inst
*write
= bld
.emit(FS_OPCODE_FB_WRITE_LOGICAL
, fs_reg(),
392 sources
, ARRAY_SIZE(sources
));
394 if (prog_data
->uses_kill
) {
395 write
->predicate
= BRW_PREDICATE_NORMAL
;
396 write
->flag_subreg
= 1;
403 fs_visitor::emit_alpha_to_coverage_workaround(const fs_reg
&src0_alpha
)
405 /* We need to compute alpha to coverage dithering manually in shader
406 * and replace sample mask store with the bitwise-AND of sample mask and
407 * alpha to coverage dithering.
409 * The following formula is used to compute final sample mask:
410 * m = int(16.0 * clamp(src0_alpha, 0.0, 1.0))
411 * dither_mask = 0x1111 * ((0xfea80 >> (m & ~3)) & 0xf) |
412 * 0x0808 * (m & 2) | 0x0100 * (m & 1)
413 * sample_mask = sample_mask & dither_mask
415 * It gives a number of ones proportional to the alpha for 2, 4, 8 or 16
416 * least significant bits of the result:
417 * 0.0000 0000000000000000
418 * 0.0625 0000000100000000
419 * 0.1250 0001000000010000
420 * 0.1875 0001000100010000
421 * 0.2500 1000100010001000
422 * 0.3125 1000100110001000
423 * 0.3750 1001100010011000
424 * 0.4375 1001100110011000
425 * 0.5000 1010101010101010
426 * 0.5625 1010101110101010
427 * 0.6250 1011101010111010
428 * 0.6875 1011101110111010
429 * 0.7500 1110111011101110
430 * 0.8125 1110111111101110
431 * 0.8750 1111111011111110
432 * 0.9375 1111111111111110
433 * 1.0000 1111111111111111
435 const fs_builder abld
= bld
.annotate("compute alpha_to_coverage & "
438 /* clamp(src0_alpha, 0.f, 1.f) */
439 const fs_reg float_tmp
= abld
.vgrf(BRW_REGISTER_TYPE_F
);
440 set_saturate(true, abld
.MOV(float_tmp
, src0_alpha
));
442 /* 16.0 * clamp(src0_alpha, 0.0, 1.0) */
443 abld
.MUL(float_tmp
, float_tmp
, brw_imm_f(16.0));
445 /* m = int(16.0 * clamp(src0_alpha, 0.0, 1.0)) */
446 const fs_reg m
= abld
.vgrf(BRW_REGISTER_TYPE_UW
);
447 abld
.MOV(m
, float_tmp
);
449 /* 0x1111 * ((0xfea80 >> (m & ~3)) & 0xf) */
450 const fs_reg int_tmp_1
= abld
.vgrf(BRW_REGISTER_TYPE_UW
);
451 const fs_reg shift_const
= abld
.vgrf(BRW_REGISTER_TYPE_UD
);
452 abld
.MOV(shift_const
, brw_imm_d(0xfea80));
453 abld
.AND(int_tmp_1
, m
, brw_imm_uw(~3));
454 abld
.SHR(int_tmp_1
, shift_const
, int_tmp_1
);
455 abld
.AND(int_tmp_1
, int_tmp_1
, brw_imm_uw(0xf));
456 abld
.MUL(int_tmp_1
, int_tmp_1
, brw_imm_uw(0x1111));
458 /* 0x0808 * (m & 2) */
459 const fs_reg int_tmp_2
= abld
.vgrf(BRW_REGISTER_TYPE_UW
);
460 abld
.AND(int_tmp_2
, m
, brw_imm_uw(2));
461 abld
.MUL(int_tmp_2
, int_tmp_2
, brw_imm_uw(0x0808));
463 abld
.OR(int_tmp_1
, int_tmp_1
, int_tmp_2
);
465 /* 0x0100 * (m & 1) */
466 const fs_reg int_tmp_3
= abld
.vgrf(BRW_REGISTER_TYPE_UW
);
467 abld
.AND(int_tmp_3
, m
, brw_imm_uw(1));
468 abld
.MUL(int_tmp_3
, int_tmp_3
, brw_imm_uw(0x0100));
470 abld
.OR(int_tmp_1
, int_tmp_1
, int_tmp_3
);
472 /* sample_mask = sample_mask & dither_mask */
473 const fs_reg mask
= abld
.vgrf(BRW_REGISTER_TYPE_UD
);
474 abld
.AND(mask
, sample_mask
, int_tmp_1
);
479 fs_visitor::emit_fb_writes()
481 assert(stage
== MESA_SHADER_FRAGMENT
);
482 struct brw_wm_prog_data
*prog_data
= brw_wm_prog_data(this->prog_data
);
483 brw_wm_prog_key
*key
= (brw_wm_prog_key
*) this->key
;
485 fs_inst
*inst
= NULL
;
487 if (source_depth_to_render_target
&& devinfo
->gen
== 6) {
488 /* For outputting oDepth on gen6, SIMD8 writes have to be used. This
489 * would require SIMD8 moves of each half to message regs, e.g. by using
490 * the SIMD lowering pass. Unfortunately this is more difficult than it
491 * sounds because the SIMD8 single-source message lacks channel selects
492 * for the second and third subspans.
494 limit_dispatch_width(8, "Depth writes unsupported in SIMD16+ mode.\n");
497 if (nir
->info
.outputs_written
& BITFIELD64_BIT(FRAG_RESULT_STENCIL
)) {
498 /* From the 'Render Target Write message' section of the docs:
499 * "Output Stencil is not supported with SIMD16 Render Target Write
502 limit_dispatch_width(8, "gl_FragStencilRefARB unsupported "
503 "in SIMD16+ mode.\n");
506 /* ANV doesn't know about sample mask output during the wm key creation
507 * so we compute if we need replicate alpha and emit alpha to coverage
510 prog_data
->replicate_alpha
= key
->alpha_test_replicate_alpha
||
511 (key
->nr_color_regions
> 1 && key
->alpha_to_coverage
&&
512 (sample_mask
.file
== BAD_FILE
|| devinfo
->gen
== 6));
514 /* From the SKL PRM, Volume 7, "Alpha Coverage":
515 * "If Pixel Shader outputs oMask, AlphaToCoverage is disabled in
516 * hardware, regardless of the state setting for this feature."
518 if (devinfo
->gen
> 6 && key
->alpha_to_coverage
&&
519 sample_mask
.file
!= BAD_FILE
&& this->outputs
[0].file
!= BAD_FILE
)
520 emit_alpha_to_coverage_workaround(offset(this->outputs
[0], bld
, 3));
522 for (int target
= 0; target
< key
->nr_color_regions
; target
++) {
523 /* Skip over outputs that weren't written. */
524 if (this->outputs
[target
].file
== BAD_FILE
)
527 const fs_builder abld
= bld
.annotate(
528 ralloc_asprintf(this->mem_ctx
, "FB write target %d", target
));
531 if (devinfo
->gen
>= 6 && prog_data
->replicate_alpha
&& target
!= 0)
532 src0_alpha
= offset(outputs
[0], bld
, 3);
534 inst
= emit_single_fb_write(abld
, this->outputs
[target
],
535 this->dual_src_output
, src0_alpha
, 4);
536 inst
->target
= target
;
539 prog_data
->dual_src_blend
= (this->dual_src_output
.file
!= BAD_FILE
&&
540 this->outputs
[0].file
!= BAD_FILE
);
541 assert(!prog_data
->dual_src_blend
|| key
->nr_color_regions
== 1);
544 /* Even if there's no color buffers enabled, we still need to send
545 * alpha out the pipeline to our null renderbuffer to support
546 * alpha-testing, alpha-to-coverage, and so on.
548 /* FINISHME: Factor out this frequently recurring pattern into a
551 const fs_reg srcs
[] = { reg_undef
, reg_undef
,
552 reg_undef
, offset(this->outputs
[0], bld
, 3) };
553 const fs_reg tmp
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 4);
554 bld
.LOAD_PAYLOAD(tmp
, srcs
, 4, 0);
556 inst
= emit_single_fb_write(bld
, tmp
, reg_undef
, reg_undef
, 4);
560 inst
->last_rt
= true;
565 fs_visitor::setup_uniform_clipplane_values()
567 const struct brw_vs_prog_key
*key
=
568 (const struct brw_vs_prog_key
*) this->key
;
570 if (key
->nr_userclip_plane_consts
== 0)
573 assert(stage_prog_data
->nr_params
== uniforms
);
574 brw_stage_prog_data_add_params(stage_prog_data
,
575 key
->nr_userclip_plane_consts
* 4);
577 for (int i
= 0; i
< key
->nr_userclip_plane_consts
; i
++) {
578 this->userplane
[i
] = fs_reg(UNIFORM
, uniforms
);
579 for (int j
= 0; j
< 4; ++j
) {
580 stage_prog_data
->param
[uniforms
+ j
] =
581 BRW_PARAM_BUILTIN_CLIP_PLANE(i
, j
);
588 * Lower legacy fixed-function and gl_ClipVertex clipping to clip distances.
590 * This does nothing if the shader uses gl_ClipDistance or user clipping is
591 * disabled altogether.
593 void fs_visitor::compute_clip_distance()
595 struct brw_vue_prog_data
*vue_prog_data
= brw_vue_prog_data(prog_data
);
596 const struct brw_vs_prog_key
*key
=
597 (const struct brw_vs_prog_key
*) this->key
;
599 /* Bail unless some sort of legacy clipping is enabled */
600 if (key
->nr_userclip_plane_consts
== 0)
603 /* From the GLSL 1.30 spec, section 7.1 (Vertex Shader Special Variables):
605 * "If a linked set of shaders forming the vertex stage contains no
606 * static write to gl_ClipVertex or gl_ClipDistance, but the
607 * application has requested clipping against user clip planes through
608 * the API, then the coordinate written to gl_Position is used for
609 * comparison against the user clip planes."
611 * This function is only called if the shader didn't write to
612 * gl_ClipDistance. Accordingly, we use gl_ClipVertex to perform clipping
613 * if the user wrote to it; otherwise we use gl_Position.
616 gl_varying_slot clip_vertex
= VARYING_SLOT_CLIP_VERTEX
;
617 if (!(vue_prog_data
->vue_map
.slots_valid
& VARYING_BIT_CLIP_VERTEX
))
618 clip_vertex
= VARYING_SLOT_POS
;
620 /* If the clip vertex isn't written, skip this. Typically this means
621 * the GS will set up clipping. */
622 if (outputs
[clip_vertex
].file
== BAD_FILE
)
625 setup_uniform_clipplane_values();
627 const fs_builder abld
= bld
.annotate("user clip distances");
629 this->outputs
[VARYING_SLOT_CLIP_DIST0
] = vgrf(glsl_type::vec4_type
);
630 this->outputs
[VARYING_SLOT_CLIP_DIST1
] = vgrf(glsl_type::vec4_type
);
632 for (int i
= 0; i
< key
->nr_userclip_plane_consts
; i
++) {
633 fs_reg u
= userplane
[i
];
634 const fs_reg output
= offset(outputs
[VARYING_SLOT_CLIP_DIST0
+ i
/ 4],
637 abld
.MUL(output
, outputs
[clip_vertex
], u
);
638 for (int j
= 1; j
< 4; j
++) {
639 u
.nr
= userplane
[i
].nr
+ j
;
640 abld
.MAD(output
, output
, offset(outputs
[clip_vertex
], bld
, j
), u
);
646 fs_visitor::emit_urb_writes(const fs_reg
&gs_vertex_count
)
648 int slot
, urb_offset
, length
;
649 int starting_urb_offset
= 0;
650 const struct brw_vue_prog_data
*vue_prog_data
=
651 brw_vue_prog_data(this->prog_data
);
652 const struct brw_vs_prog_key
*vs_key
=
653 (const struct brw_vs_prog_key
*) this->key
;
654 const GLbitfield64 psiz_mask
=
655 VARYING_BIT_LAYER
| VARYING_BIT_VIEWPORT
| VARYING_BIT_PSIZ
;
656 const struct brw_vue_map
*vue_map
= &vue_prog_data
->vue_map
;
661 if (stage
== MESA_SHADER_TESS_EVAL
)
662 urb_handle
= fs_reg(retype(brw_vec8_grf(4, 0), BRW_REGISTER_TYPE_UD
));
664 urb_handle
= fs_reg(retype(brw_vec8_grf(1, 0), BRW_REGISTER_TYPE_UD
));
666 opcode opcode
= SHADER_OPCODE_URB_WRITE_SIMD8
;
668 fs_reg per_slot_offsets
;
670 if (stage
== MESA_SHADER_GEOMETRY
) {
671 const struct brw_gs_prog_data
*gs_prog_data
=
672 brw_gs_prog_data(this->prog_data
);
674 /* We need to increment the Global Offset to skip over the control data
675 * header and the extra "Vertex Count" field (1 HWord) at the beginning
676 * of the VUE. We're counting in OWords, so the units are doubled.
678 starting_urb_offset
= 2 * gs_prog_data
->control_data_header_size_hwords
;
679 if (gs_prog_data
->static_vertex_count
== -1)
680 starting_urb_offset
+= 2;
682 /* We also need to use per-slot offsets. The per-slot offset is the
683 * Vertex Count. SIMD8 mode processes 8 different primitives at a
684 * time; each may output a different number of vertices.
686 opcode
= SHADER_OPCODE_URB_WRITE_SIMD8_PER_SLOT
;
689 /* The URB offset is in 128-bit units, so we need to multiply by 2 */
690 const int output_vertex_size_owords
=
691 gs_prog_data
->output_vertex_size_hwords
* 2;
693 if (gs_vertex_count
.file
== IMM
) {
694 per_slot_offsets
= brw_imm_ud(output_vertex_size_owords
*
697 per_slot_offsets
= vgrf(glsl_type::uint_type
);
698 bld
.MUL(per_slot_offsets
, gs_vertex_count
,
699 brw_imm_ud(output_vertex_size_owords
));
704 urb_offset
= starting_urb_offset
;
707 /* SSO shaders can have VUE slots allocated which are never actually
708 * written to, so ignore them when looking for the last (written) slot.
710 int last_slot
= vue_map
->num_slots
- 1;
711 while (last_slot
> 0 &&
712 (vue_map
->slot_to_varying
[last_slot
] == BRW_VARYING_SLOT_PAD
||
713 outputs
[vue_map
->slot_to_varying
[last_slot
]].file
== BAD_FILE
)) {
717 bool urb_written
= false;
718 for (slot
= 0; slot
< vue_map
->num_slots
; slot
++) {
719 int varying
= vue_map
->slot_to_varying
[slot
];
721 case VARYING_SLOT_PSIZ
: {
722 /* The point size varying slot is the vue header and is always in the
723 * vue map. But often none of the special varyings that live there
724 * are written and in that case we can skip writing to the vue
725 * header, provided the corresponding state properly clamps the
726 * values further down the pipeline. */
727 if ((vue_map
->slots_valid
& psiz_mask
) == 0) {
733 fs_reg
zero(VGRF
, alloc
.allocate(1), BRW_REGISTER_TYPE_UD
);
734 bld
.MOV(zero
, brw_imm_ud(0u));
736 sources
[length
++] = zero
;
737 if (vue_map
->slots_valid
& VARYING_BIT_LAYER
)
738 sources
[length
++] = this->outputs
[VARYING_SLOT_LAYER
];
740 sources
[length
++] = zero
;
742 if (vue_map
->slots_valid
& VARYING_BIT_VIEWPORT
)
743 sources
[length
++] = this->outputs
[VARYING_SLOT_VIEWPORT
];
745 sources
[length
++] = zero
;
747 if (vue_map
->slots_valid
& VARYING_BIT_PSIZ
)
748 sources
[length
++] = this->outputs
[VARYING_SLOT_PSIZ
];
750 sources
[length
++] = zero
;
753 case BRW_VARYING_SLOT_NDC
:
754 case VARYING_SLOT_EDGE
:
755 unreachable("unexpected scalar vs output");
759 /* gl_Position is always in the vue map, but isn't always written by
760 * the shader. Other varyings (clip distances) get added to the vue
761 * map but don't always get written. In those cases, the
762 * corresponding this->output[] slot will be invalid we and can skip
763 * the urb write for the varying. If we've already queued up a vue
764 * slot for writing we flush a mlen 5 urb write, otherwise we just
765 * advance the urb_offset.
767 if (varying
== BRW_VARYING_SLOT_PAD
||
768 this->outputs
[varying
].file
== BAD_FILE
) {
776 if (stage
== MESA_SHADER_VERTEX
&& vs_key
->clamp_vertex_color
&&
777 (varying
== VARYING_SLOT_COL0
||
778 varying
== VARYING_SLOT_COL1
||
779 varying
== VARYING_SLOT_BFC0
||
780 varying
== VARYING_SLOT_BFC1
)) {
781 /* We need to clamp these guys, so do a saturating MOV into a
782 * temp register and use that for the payload.
784 for (int i
= 0; i
< 4; i
++) {
785 fs_reg reg
= fs_reg(VGRF
, alloc
.allocate(1), outputs
[varying
].type
);
786 fs_reg src
= offset(this->outputs
[varying
], bld
, i
);
787 set_saturate(true, bld
.MOV(reg
, src
));
788 sources
[length
++] = reg
;
791 for (unsigned i
= 0; i
< 4; i
++)
792 sources
[length
++] = offset(this->outputs
[varying
], bld
, i
);
797 const fs_builder abld
= bld
.annotate("URB write");
799 /* If we've queued up 8 registers of payload (2 VUE slots), if this is
800 * the last slot or if we need to flush (see BAD_FILE varying case
801 * above), emit a URB write send now to flush out the data.
803 if (length
== 8 || (length
> 0 && slot
== last_slot
))
806 fs_reg
*payload_sources
=
807 ralloc_array(mem_ctx
, fs_reg
, length
+ header_size
);
808 fs_reg payload
= fs_reg(VGRF
, alloc
.allocate(length
+ header_size
),
809 BRW_REGISTER_TYPE_F
);
810 payload_sources
[0] = urb_handle
;
812 if (opcode
== SHADER_OPCODE_URB_WRITE_SIMD8_PER_SLOT
)
813 payload_sources
[1] = per_slot_offsets
;
815 memcpy(&payload_sources
[header_size
], sources
,
816 length
* sizeof sources
[0]);
818 abld
.LOAD_PAYLOAD(payload
, payload_sources
, length
+ header_size
,
821 fs_inst
*inst
= abld
.emit(opcode
, reg_undef
, payload
);
822 inst
->eot
= slot
== last_slot
&& stage
!= MESA_SHADER_GEOMETRY
;
823 inst
->mlen
= length
+ header_size
;
824 inst
->offset
= urb_offset
;
825 urb_offset
= starting_urb_offset
+ slot
+ 1;
832 /* If we don't have any valid slots to write, just do a minimal urb write
833 * send to terminate the shader. This includes 1 slot of undefined data,
834 * because it's invalid to write 0 data:
836 * From the Broadwell PRM, Volume 7: 3D Media GPGPU, Shared Functions -
837 * Unified Return Buffer (URB) > URB_SIMD8_Write and URB_SIMD8_Read >
838 * Write Data Payload:
840 * "The write data payload can be between 1 and 8 message phases long."
843 /* For GS, just turn EmitVertex() into a no-op. We don't want it to
844 * end the thread, and emit_gs_thread_end() already emits a SEND with
845 * EOT at the end of the program for us.
847 if (stage
== MESA_SHADER_GEOMETRY
)
850 fs_reg payload
= fs_reg(VGRF
, alloc
.allocate(2), BRW_REGISTER_TYPE_UD
);
851 bld
.exec_all().MOV(payload
, urb_handle
);
853 fs_inst
*inst
= bld
.emit(SHADER_OPCODE_URB_WRITE_SIMD8
, reg_undef
, payload
);
862 fs_visitor::emit_cs_terminate()
864 assert(devinfo
->gen
>= 7);
866 /* We are getting the thread ID from the compute shader header */
867 assert(stage
== MESA_SHADER_COMPUTE
);
869 /* We can't directly send from g0, since sends with EOT have to use
870 * g112-127. So, copy it to a virtual register, The register allocator will
871 * make sure it uses the appropriate register range.
873 struct brw_reg g0
= retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UD
);
874 fs_reg payload
= fs_reg(VGRF
, alloc
.allocate(1), BRW_REGISTER_TYPE_UD
);
875 bld
.group(8, 0).exec_all().MOV(payload
, g0
);
877 /* Send a message to the thread spawner to terminate the thread. */
878 fs_inst
*inst
= bld
.exec_all()
879 .emit(CS_OPCODE_CS_TERMINATE
, reg_undef
, payload
);
884 fs_visitor::emit_barrier()
886 uint32_t barrier_id_mask
;
887 switch (devinfo
->gen
) {
890 barrier_id_mask
= 0x0f000000u
; break;
893 barrier_id_mask
= 0x8f000000u
; break;
895 barrier_id_mask
= 0x7f000000u
; break;
897 unreachable("barrier is only available on gen >= 7");
900 /* We are getting the barrier ID from the compute shader header */
901 assert(stage
== MESA_SHADER_COMPUTE
);
903 fs_reg payload
= fs_reg(VGRF
, alloc
.allocate(1), BRW_REGISTER_TYPE_UD
);
905 /* Clear the message payload */
906 bld
.exec_all().group(8, 0).MOV(payload
, brw_imm_ud(0u));
908 /* Copy the barrier id from r0.2 to the message payload reg.2 */
909 fs_reg r0_2
= fs_reg(retype(brw_vec1_grf(0, 2), BRW_REGISTER_TYPE_UD
));
910 bld
.exec_all().group(1, 0).AND(component(payload
, 2), r0_2
,
911 brw_imm_ud(barrier_id_mask
));
913 /* Emit a gateway "barrier" message using the payload we set up, followed
914 * by a wait instruction.
916 bld
.exec_all().emit(SHADER_OPCODE_BARRIER
, reg_undef
, payload
);
919 fs_visitor::fs_visitor(const struct brw_compiler
*compiler
, void *log_data
,
922 struct brw_stage_prog_data
*prog_data
,
923 struct gl_program
*prog
,
924 const nir_shader
*shader
,
925 unsigned dispatch_width
,
926 int shader_time_index
,
927 const struct brw_vue_map
*input_vue_map
)
928 : backend_shader(compiler
, log_data
, mem_ctx
, shader
, prog_data
),
929 key(key
), gs_compile(NULL
), prog_data(prog_data
), prog(prog
),
930 input_vue_map(input_vue_map
),
931 dispatch_width(dispatch_width
),
932 shader_time_index(shader_time_index
),
933 bld(fs_builder(this, dispatch_width
).at_end())
938 fs_visitor::fs_visitor(const struct brw_compiler
*compiler
, void *log_data
,
940 struct brw_gs_compile
*c
,
941 struct brw_gs_prog_data
*prog_data
,
942 const nir_shader
*shader
,
943 int shader_time_index
)
944 : backend_shader(compiler
, log_data
, mem_ctx
, shader
,
945 &prog_data
->base
.base
),
946 key(&c
->key
), gs_compile(c
),
947 prog_data(&prog_data
->base
.base
), prog(NULL
),
949 shader_time_index(shader_time_index
),
950 bld(fs_builder(this, dispatch_width
).at_end())
960 case MESA_SHADER_FRAGMENT
:
961 key_tex
= &((const brw_wm_prog_key
*) key
)->tex
;
963 case MESA_SHADER_VERTEX
:
964 key_tex
= &((const brw_vs_prog_key
*) key
)->tex
;
966 case MESA_SHADER_TESS_CTRL
:
967 key_tex
= &((const brw_tcs_prog_key
*) key
)->tex
;
969 case MESA_SHADER_TESS_EVAL
:
970 key_tex
= &((const brw_tes_prog_key
*) key
)->tex
;
972 case MESA_SHADER_GEOMETRY
:
973 key_tex
= &((const brw_gs_prog_key
*) key
)->tex
;
975 case MESA_SHADER_COMPUTE
:
976 key_tex
= &((const brw_cs_prog_key
*) key
)->tex
;
979 unreachable("unhandled shader stage");
982 this->max_dispatch_width
= 32;
983 this->prog_data
= this->stage_prog_data
;
985 this->failed
= false;
987 this->nir_locals
= NULL
;
988 this->nir_ssa_values
= NULL
;
990 memset(&this->payload
, 0, sizeof(this->payload
));
991 this->source_depth_to_render_target
= false;
992 this->runtime_check_aads_emit
= false;
993 this->first_non_payload_grf
= 0;
994 this->max_grf
= devinfo
->gen
>= 7 ? GEN7_MRF_HACK_START
: BRW_MAX_GRF
;
996 this->virtual_grf_start
= NULL
;
997 this->virtual_grf_end
= NULL
;
998 this->live_intervals
= NULL
;
999 this->regs_live_at_ip
= NULL
;
1002 this->last_scratch
= 0;
1003 this->pull_constant_loc
= NULL
;
1004 this->push_constant_loc
= NULL
;
1006 this->promoted_constants
= 0,
1009 this->spilled_any_registers
= false;
1012 fs_visitor::~fs_visitor()