2 * Copyright © 2010 Intel Corporation
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5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 /** @file brw_fs_visitor.cpp
26 * This file supports generating the FS LIR from the GLSL IR. The LIR
27 * makes it easier to do backend-specific optimizations than doing so
28 * in the GLSL IR or in the native code.
31 #include "compiler/glsl_types.h"
35 /* Sample from the MCS surface attached to this multisample texture. */
37 fs_visitor::emit_mcs_fetch(const fs_reg
&coordinate
, unsigned components
,
38 const fs_reg
&texture
,
39 const fs_reg
&texture_handle
)
41 const fs_reg dest
= vgrf(glsl_type::uvec4_type
);
43 fs_reg srcs
[TEX_LOGICAL_NUM_SRCS
];
44 srcs
[TEX_LOGICAL_SRC_COORDINATE
] = coordinate
;
45 srcs
[TEX_LOGICAL_SRC_SURFACE
] = texture
;
46 srcs
[TEX_LOGICAL_SRC_SAMPLER
] = brw_imm_ud(0);
47 srcs
[TEX_LOGICAL_SRC_SURFACE_HANDLE
] = texture_handle
;
48 srcs
[TEX_LOGICAL_SRC_COORD_COMPONENTS
] = brw_imm_d(components
);
49 srcs
[TEX_LOGICAL_SRC_GRAD_COMPONENTS
] = brw_imm_d(0);
51 fs_inst
*inst
= bld
.emit(SHADER_OPCODE_TXF_MCS_LOGICAL
, dest
, srcs
,
54 /* We only care about one or two regs of response, but the sampler always
57 inst
->size_written
= 4 * dest
.component_size(inst
->exec_size
);
63 * Apply workarounds for Gen6 gather with UINT/SINT
66 fs_visitor::emit_gen6_gather_wa(uint8_t wa
, fs_reg dst
)
71 int width
= (wa
& WA_8BIT
) ? 8 : 16;
73 for (int i
= 0; i
< 4; i
++) {
74 fs_reg dst_f
= retype(dst
, BRW_REGISTER_TYPE_F
);
75 /* Convert from UNORM to UINT */
76 bld
.MUL(dst_f
, dst_f
, brw_imm_f((1 << width
) - 1));
80 /* Reinterpret the UINT value as a signed INT value by
81 * shifting the sign bit into place, then shifting back
84 bld
.SHL(dst
, dst
, brw_imm_d(32 - width
));
85 bld
.ASR(dst
, dst
, brw_imm_d(32 - width
));
88 dst
= offset(dst
, bld
, 1);
92 /** Emits a dummy fragment shader consisting of magenta for bringup purposes. */
94 fs_visitor::emit_dummy_fs()
96 int reg_width
= dispatch_width
/ 8;
98 /* Everyone's favorite color. */
99 const float color
[4] = { 1.0, 0.0, 1.0, 0.0 };
100 for (int i
= 0; i
< 4; i
++) {
101 bld
.MOV(fs_reg(MRF
, 2 + i
* reg_width
, BRW_REGISTER_TYPE_F
),
102 brw_imm_f(color
[i
]));
106 write
= bld
.emit(FS_OPCODE_FB_WRITE
);
108 write
->last_rt
= true;
109 if (devinfo
->gen
>= 6) {
111 write
->mlen
= 4 * reg_width
;
113 write
->header_size
= 2;
115 write
->mlen
= 2 + 4 * reg_width
;
118 /* Tell the SF we don't have any inputs. Gen4-5 require at least one
119 * varying to avoid GPU hangs, so set that.
121 struct brw_wm_prog_data
*wm_prog_data
= brw_wm_prog_data(this->prog_data
);
122 wm_prog_data
->num_varying_inputs
= devinfo
->gen
< 6 ? 1 : 0;
123 memset(wm_prog_data
->urb_setup
, -1,
124 sizeof(wm_prog_data
->urb_setup
[0]) * VARYING_SLOT_MAX
);
126 /* We don't have any uniforms. */
127 stage_prog_data
->nr_params
= 0;
128 stage_prog_data
->nr_pull_params
= 0;
129 stage_prog_data
->curb_read_length
= 0;
130 stage_prog_data
->dispatch_grf_start_reg
= 2;
131 wm_prog_data
->dispatch_grf_start_reg_16
= 2;
132 wm_prog_data
->dispatch_grf_start_reg_32
= 2;
133 grf_used
= 1; /* Gen4-5 don't allow zero GRF blocks */
138 /* The register location here is relative to the start of the URB
139 * data. It will get adjusted to be a real location before
140 * generate_code() time.
143 fs_visitor::interp_reg(int location
, int channel
)
145 assert(stage
== MESA_SHADER_FRAGMENT
);
146 struct brw_wm_prog_data
*prog_data
= brw_wm_prog_data(this->prog_data
);
147 int regnr
= prog_data
->urb_setup
[location
] * 4 + channel
;
148 assert(prog_data
->urb_setup
[location
] != -1);
150 return fs_reg(ATTR
, regnr
, BRW_REGISTER_TYPE_F
);
153 /** Emits the interpolation for the varying inputs. */
155 fs_visitor::emit_interpolation_setup_gen4()
157 struct brw_reg g1_uw
= retype(brw_vec1_grf(1, 0), BRW_REGISTER_TYPE_UW
);
159 fs_builder abld
= bld
.annotate("compute pixel centers");
160 this->pixel_x
= vgrf(glsl_type::uint_type
);
161 this->pixel_y
= vgrf(glsl_type::uint_type
);
162 this->pixel_x
.type
= BRW_REGISTER_TYPE_UW
;
163 this->pixel_y
.type
= BRW_REGISTER_TYPE_UW
;
164 abld
.ADD(this->pixel_x
,
165 fs_reg(stride(suboffset(g1_uw
, 4), 2, 4, 0)),
166 fs_reg(brw_imm_v(0x10101010)));
167 abld
.ADD(this->pixel_y
,
168 fs_reg(stride(suboffset(g1_uw
, 5), 2, 4, 0)),
169 fs_reg(brw_imm_v(0x11001100)));
171 abld
= bld
.annotate("compute pixel deltas from v0");
173 this->delta_xy
[BRW_BARYCENTRIC_PERSPECTIVE_PIXEL
] =
174 vgrf(glsl_type::vec2_type
);
175 const fs_reg
&delta_xy
= this->delta_xy
[BRW_BARYCENTRIC_PERSPECTIVE_PIXEL
];
176 const fs_reg
xstart(negate(brw_vec1_grf(1, 0)));
177 const fs_reg
ystart(negate(brw_vec1_grf(1, 1)));
179 if (devinfo
->has_pln
&& dispatch_width
== 16) {
180 for (unsigned i
= 0; i
< 2; i
++) {
181 abld
.half(i
).ADD(half(offset(delta_xy
, abld
, i
), 0),
182 half(this->pixel_x
, i
), xstart
);
183 abld
.half(i
).ADD(half(offset(delta_xy
, abld
, i
), 1),
184 half(this->pixel_y
, i
), ystart
);
187 abld
.ADD(offset(delta_xy
, abld
, 0), this->pixel_x
, xstart
);
188 abld
.ADD(offset(delta_xy
, abld
, 1), this->pixel_y
, ystart
);
191 abld
= bld
.annotate("compute pos.w and 1/pos.w");
192 /* Compute wpos.w. It's always in our setup, since it's needed to
193 * interpolate the other attributes.
195 this->wpos_w
= vgrf(glsl_type::float_type
);
196 abld
.emit(FS_OPCODE_LINTERP
, wpos_w
, delta_xy
,
197 component(interp_reg(VARYING_SLOT_POS
, 3), 0));
198 /* Compute the pixel 1/W value from wpos.w. */
199 this->pixel_w
= vgrf(glsl_type::float_type
);
200 abld
.emit(SHADER_OPCODE_RCP
, this->pixel_w
, wpos_w
);
204 brw_rnd_mode_from_nir(unsigned mode
, unsigned *mask
)
206 unsigned brw_mode
= 0;
209 if ((FLOAT_CONTROLS_ROUNDING_MODE_RTZ_FP16
|
210 FLOAT_CONTROLS_ROUNDING_MODE_RTZ_FP32
|
211 FLOAT_CONTROLS_ROUNDING_MODE_RTZ_FP64
) &
213 brw_mode
|= BRW_RND_MODE_RTZ
<< BRW_CR0_RND_MODE_SHIFT
;
214 *mask
|= BRW_CR0_RND_MODE_MASK
;
216 if ((FLOAT_CONTROLS_ROUNDING_MODE_RTE_FP16
|
217 FLOAT_CONTROLS_ROUNDING_MODE_RTE_FP32
|
218 FLOAT_CONTROLS_ROUNDING_MODE_RTE_FP64
) &
220 brw_mode
|= BRW_RND_MODE_RTNE
<< BRW_CR0_RND_MODE_SHIFT
;
221 *mask
|= BRW_CR0_RND_MODE_MASK
;
223 if (mode
& FLOAT_CONTROLS_DENORM_PRESERVE_FP16
) {
224 brw_mode
|= BRW_CR0_FP16_DENORM_PRESERVE
;
225 *mask
|= BRW_CR0_FP16_DENORM_PRESERVE
;
227 if (mode
& FLOAT_CONTROLS_DENORM_PRESERVE_FP32
) {
228 brw_mode
|= BRW_CR0_FP32_DENORM_PRESERVE
;
229 *mask
|= BRW_CR0_FP32_DENORM_PRESERVE
;
231 if (mode
& FLOAT_CONTROLS_DENORM_PRESERVE_FP64
) {
232 brw_mode
|= BRW_CR0_FP64_DENORM_PRESERVE
;
233 *mask
|= BRW_CR0_FP64_DENORM_PRESERVE
;
235 if (mode
& FLOAT_CONTROLS_DENORM_FLUSH_TO_ZERO_FP16
)
236 *mask
|= BRW_CR0_FP16_DENORM_PRESERVE
;
237 if (mode
& FLOAT_CONTROLS_DENORM_FLUSH_TO_ZERO_FP32
)
238 *mask
|= BRW_CR0_FP32_DENORM_PRESERVE
;
239 if (mode
& FLOAT_CONTROLS_DENORM_FLUSH_TO_ZERO_FP64
)
240 *mask
|= BRW_CR0_FP64_DENORM_PRESERVE
;
241 if (mode
== FLOAT_CONTROLS_DEFAULT_FLOAT_CONTROL_MODE
)
242 *mask
|= BRW_CR0_FP_MODE_MASK
;
248 fs_visitor::emit_shader_float_controls_execution_mode()
250 unsigned execution_mode
= this->nir
->info
.float_controls_execution_mode
;
251 if (execution_mode
== FLOAT_CONTROLS_DEFAULT_FLOAT_CONTROL_MODE
)
254 fs_builder abld
= bld
.annotate("shader floats control execution mode");
256 unsigned mode
= brw_rnd_mode_from_nir(execution_mode
, &mask
);
257 abld
.emit(SHADER_OPCODE_FLOAT_CONTROL_MODE
, bld
.null_reg_ud(),
258 brw_imm_d(mode
), brw_imm_d(mask
));
261 /** Emits the interpolation for the varying inputs. */
263 fs_visitor::emit_interpolation_setup_gen6()
265 fs_builder abld
= bld
.annotate("compute pixel centers");
267 this->pixel_x
= vgrf(glsl_type::float_type
);
268 this->pixel_y
= vgrf(glsl_type::float_type
);
270 for (unsigned i
= 0; i
< DIV_ROUND_UP(dispatch_width
, 16); i
++) {
271 const fs_builder hbld
= abld
.group(MIN2(16, dispatch_width
), i
);
272 struct brw_reg gi_uw
= retype(brw_vec1_grf(1 + i
, 0), BRW_REGISTER_TYPE_UW
);
274 if (devinfo
->gen
>= 8 || dispatch_width
== 8) {
275 /* The "Register Region Restrictions" page says for BDW (and newer,
278 * "When destination spans two registers, the source may be one or
279 * two registers. The destination elements must be evenly split
280 * between the two registers."
282 * Thus we can do a single add(16) in SIMD8 or an add(32) in SIMD16
283 * to compute our pixel centers.
285 const fs_builder dbld
=
286 abld
.exec_all().group(hbld
.dispatch_width() * 2, 0);
287 fs_reg int_pixel_xy
= dbld
.vgrf(BRW_REGISTER_TYPE_UW
);
289 dbld
.ADD(int_pixel_xy
,
290 fs_reg(stride(suboffset(gi_uw
, 4), 1, 4, 0)),
291 fs_reg(brw_imm_v(0x11001010)));
293 hbld
.emit(FS_OPCODE_PIXEL_X
, offset(pixel_x
, hbld
, i
), int_pixel_xy
);
294 hbld
.emit(FS_OPCODE_PIXEL_Y
, offset(pixel_y
, hbld
, i
), int_pixel_xy
);
296 /* The "Register Region Restrictions" page says for SNB, IVB, HSW:
298 * "When destination spans two registers, the source MUST span
301 * Since the GRF source of the ADD will only read a single register,
302 * we must do two separate ADDs in SIMD16.
304 const fs_reg int_pixel_x
= hbld
.vgrf(BRW_REGISTER_TYPE_UW
);
305 const fs_reg int_pixel_y
= hbld
.vgrf(BRW_REGISTER_TYPE_UW
);
307 hbld
.ADD(int_pixel_x
,
308 fs_reg(stride(suboffset(gi_uw
, 4), 2, 4, 0)),
309 fs_reg(brw_imm_v(0x10101010)));
310 hbld
.ADD(int_pixel_y
,
311 fs_reg(stride(suboffset(gi_uw
, 5), 2, 4, 0)),
312 fs_reg(brw_imm_v(0x11001100)));
314 /* As of gen6, we can no longer mix float and int sources. We have
315 * to turn the integer pixel centers into floats for their actual
318 hbld
.MOV(offset(pixel_x
, hbld
, i
), int_pixel_x
);
319 hbld
.MOV(offset(pixel_y
, hbld
, i
), int_pixel_y
);
323 abld
= bld
.annotate("compute pos.w");
324 this->pixel_w
= fetch_payload_reg(abld
, payload
.source_w_reg
);
325 this->wpos_w
= vgrf(glsl_type::float_type
);
326 abld
.emit(SHADER_OPCODE_RCP
, this->wpos_w
, this->pixel_w
);
328 struct brw_wm_prog_data
*wm_prog_data
= brw_wm_prog_data(prog_data
);
330 for (int i
= 0; i
< BRW_BARYCENTRIC_MODE_COUNT
; ++i
) {
331 this->delta_xy
[i
] = fetch_payload_reg(
332 bld
, payload
.barycentric_coord_reg
[i
], BRW_REGISTER_TYPE_F
, 2);
335 uint32_t centroid_modes
= wm_prog_data
->barycentric_interp_modes
&
336 (1 << BRW_BARYCENTRIC_PERSPECTIVE_CENTROID
|
337 1 << BRW_BARYCENTRIC_NONPERSPECTIVE_CENTROID
);
339 if (devinfo
->needs_unlit_centroid_workaround
&& centroid_modes
) {
340 /* Get the pixel/sample mask into f0 so that we know which
341 * pixels are lit. Then, for each channel that is unlit,
342 * replace the centroid data with non-centroid data.
344 for (unsigned i
= 0; i
< DIV_ROUND_UP(dispatch_width
, 16); i
++) {
345 bld
.exec_all().group(1, 0)
346 .MOV(retype(brw_flag_reg(0, i
), BRW_REGISTER_TYPE_UW
),
347 retype(brw_vec1_grf(1 + i
, 7), BRW_REGISTER_TYPE_UW
));
350 for (int i
= 0; i
< BRW_BARYCENTRIC_MODE_COUNT
; ++i
) {
351 if (!(centroid_modes
& (1 << i
)))
354 const fs_reg
&pixel_delta_xy
= delta_xy
[i
- 1];
356 for (unsigned q
= 0; q
< dispatch_width
/ 8; q
++) {
357 for (unsigned c
= 0; c
< 2; c
++) {
358 const unsigned idx
= c
+ (q
& 2) + (q
& 1) * dispatch_width
/ 8;
360 BRW_PREDICATE_NORMAL
, true,
361 bld
.half(q
).MOV(horiz_offset(delta_xy
[i
], idx
* 8),
362 horiz_offset(pixel_delta_xy
, idx
* 8)));
369 static enum brw_conditional_mod
370 cond_for_alpha_func(GLenum func
)
374 return BRW_CONDITIONAL_G
;
376 return BRW_CONDITIONAL_GE
;
378 return BRW_CONDITIONAL_L
;
380 return BRW_CONDITIONAL_LE
;
382 return BRW_CONDITIONAL_EQ
;
384 return BRW_CONDITIONAL_NEQ
;
386 unreachable("Not reached");
391 * Alpha test support for when we compile it into the shader instead
392 * of using the normal fixed-function alpha test.
395 fs_visitor::emit_alpha_test()
397 assert(stage
== MESA_SHADER_FRAGMENT
);
398 brw_wm_prog_key
*key
= (brw_wm_prog_key
*) this->key
;
399 const fs_builder abld
= bld
.annotate("Alpha test");
402 if (key
->alpha_test_func
== GL_ALWAYS
)
405 if (key
->alpha_test_func
== GL_NEVER
) {
407 fs_reg some_reg
= fs_reg(retype(brw_vec8_grf(0, 0),
408 BRW_REGISTER_TYPE_UW
));
409 cmp
= abld
.CMP(bld
.null_reg_f(), some_reg
, some_reg
,
410 BRW_CONDITIONAL_NEQ
);
413 fs_reg color
= offset(outputs
[0], bld
, 3);
415 /* f0.1 &= func(color, ref) */
416 cmp
= abld
.CMP(bld
.null_reg_f(), color
, brw_imm_f(key
->alpha_test_ref
),
417 cond_for_alpha_func(key
->alpha_test_func
));
419 cmp
->predicate
= BRW_PREDICATE_NORMAL
;
420 cmp
->flag_subreg
= 1;
424 fs_visitor::emit_single_fb_write(const fs_builder
&bld
,
425 fs_reg color0
, fs_reg color1
,
426 fs_reg src0_alpha
, unsigned components
)
428 assert(stage
== MESA_SHADER_FRAGMENT
);
429 struct brw_wm_prog_data
*prog_data
= brw_wm_prog_data(this->prog_data
);
431 /* Hand over gl_FragDepth or the payload depth. */
432 const fs_reg dst_depth
= fetch_payload_reg(bld
, payload
.dest_depth_reg
);
433 fs_reg src_depth
, src_stencil
;
435 if (source_depth_to_render_target
) {
436 if (nir
->info
.outputs_written
& BITFIELD64_BIT(FRAG_RESULT_DEPTH
))
437 src_depth
= frag_depth
;
439 src_depth
= fetch_payload_reg(bld
, payload
.source_depth_reg
);
442 if (nir
->info
.outputs_written
& BITFIELD64_BIT(FRAG_RESULT_STENCIL
))
443 src_stencil
= frag_stencil
;
445 const fs_reg sources
[] = {
446 color0
, color1
, src0_alpha
, src_depth
, dst_depth
, src_stencil
,
447 (prog_data
->uses_omask
? sample_mask
: fs_reg()),
448 brw_imm_ud(components
)
450 assert(ARRAY_SIZE(sources
) - 1 == FB_WRITE_LOGICAL_SRC_COMPONENTS
);
451 fs_inst
*write
= bld
.emit(FS_OPCODE_FB_WRITE_LOGICAL
, fs_reg(),
452 sources
, ARRAY_SIZE(sources
));
454 if (prog_data
->uses_kill
) {
455 write
->predicate
= BRW_PREDICATE_NORMAL
;
456 write
->flag_subreg
= 1;
463 fs_visitor::emit_alpha_to_coverage_workaround(const fs_reg
&src0_alpha
)
465 /* We need to compute alpha to coverage dithering manually in shader
466 * and replace sample mask store with the bitwise-AND of sample mask and
467 * alpha to coverage dithering.
469 * The following formula is used to compute final sample mask:
470 * m = int(16.0 * clamp(src0_alpha, 0.0, 1.0))
471 * dither_mask = 0x1111 * ((0xfea80 >> (m & ~3)) & 0xf) |
472 * 0x0808 * (m & 2) | 0x0100 * (m & 1)
473 * sample_mask = sample_mask & dither_mask
475 * It gives a number of ones proportional to the alpha for 2, 4, 8 or 16
476 * least significant bits of the result:
477 * 0.0000 0000000000000000
478 * 0.0625 0000000100000000
479 * 0.1250 0001000000010000
480 * 0.1875 0001000100010000
481 * 0.2500 1000100010001000
482 * 0.3125 1000100110001000
483 * 0.3750 1001100010011000
484 * 0.4375 1001100110011000
485 * 0.5000 1010101010101010
486 * 0.5625 1010101110101010
487 * 0.6250 1011101010111010
488 * 0.6875 1011101110111010
489 * 0.7500 1110111011101110
490 * 0.8125 1110111111101110
491 * 0.8750 1111111011111110
492 * 0.9375 1111111111111110
493 * 1.0000 1111111111111111
495 const fs_builder abld
= bld
.annotate("compute alpha_to_coverage & "
498 /* clamp(src0_alpha, 0.f, 1.f) */
499 const fs_reg float_tmp
= abld
.vgrf(BRW_REGISTER_TYPE_F
);
500 set_saturate(true, abld
.MOV(float_tmp
, src0_alpha
));
502 /* 16.0 * clamp(src0_alpha, 0.0, 1.0) */
503 abld
.MUL(float_tmp
, float_tmp
, brw_imm_f(16.0));
505 /* m = int(16.0 * clamp(src0_alpha, 0.0, 1.0)) */
506 const fs_reg m
= abld
.vgrf(BRW_REGISTER_TYPE_UW
);
507 abld
.MOV(m
, float_tmp
);
509 /* 0x1111 * ((0xfea80 >> (m & ~3)) & 0xf) */
510 const fs_reg int_tmp_1
= abld
.vgrf(BRW_REGISTER_TYPE_UW
);
511 const fs_reg shift_const
= abld
.vgrf(BRW_REGISTER_TYPE_UD
);
512 abld
.MOV(shift_const
, brw_imm_d(0xfea80));
513 abld
.AND(int_tmp_1
, m
, brw_imm_uw(~3));
514 abld
.SHR(int_tmp_1
, shift_const
, int_tmp_1
);
515 abld
.AND(int_tmp_1
, int_tmp_1
, brw_imm_uw(0xf));
516 abld
.MUL(int_tmp_1
, int_tmp_1
, brw_imm_uw(0x1111));
518 /* 0x0808 * (m & 2) */
519 const fs_reg int_tmp_2
= abld
.vgrf(BRW_REGISTER_TYPE_UW
);
520 abld
.AND(int_tmp_2
, m
, brw_imm_uw(2));
521 abld
.MUL(int_tmp_2
, int_tmp_2
, brw_imm_uw(0x0808));
523 abld
.OR(int_tmp_1
, int_tmp_1
, int_tmp_2
);
525 /* 0x0100 * (m & 1) */
526 const fs_reg int_tmp_3
= abld
.vgrf(BRW_REGISTER_TYPE_UW
);
527 abld
.AND(int_tmp_3
, m
, brw_imm_uw(1));
528 abld
.MUL(int_tmp_3
, int_tmp_3
, brw_imm_uw(0x0100));
530 abld
.OR(int_tmp_1
, int_tmp_1
, int_tmp_3
);
532 /* sample_mask = sample_mask & dither_mask */
533 const fs_reg mask
= abld
.vgrf(BRW_REGISTER_TYPE_UD
);
534 abld
.AND(mask
, sample_mask
, int_tmp_1
);
539 fs_visitor::emit_fb_writes()
541 assert(stage
== MESA_SHADER_FRAGMENT
);
542 struct brw_wm_prog_data
*prog_data
= brw_wm_prog_data(this->prog_data
);
543 brw_wm_prog_key
*key
= (brw_wm_prog_key
*) this->key
;
545 fs_inst
*inst
= NULL
;
547 if (source_depth_to_render_target
&& devinfo
->gen
== 6) {
548 /* For outputting oDepth on gen6, SIMD8 writes have to be used. This
549 * would require SIMD8 moves of each half to message regs, e.g. by using
550 * the SIMD lowering pass. Unfortunately this is more difficult than it
551 * sounds because the SIMD8 single-source message lacks channel selects
552 * for the second and third subspans.
554 limit_dispatch_width(8, "Depth writes unsupported in SIMD16+ mode.\n");
557 if (nir
->info
.outputs_written
& BITFIELD64_BIT(FRAG_RESULT_STENCIL
)) {
558 /* From the 'Render Target Write message' section of the docs:
559 * "Output Stencil is not supported with SIMD16 Render Target Write
562 limit_dispatch_width(8, "gl_FragStencilRefARB unsupported "
563 "in SIMD16+ mode.\n");
566 /* ANV doesn't know about sample mask output during the wm key creation
567 * so we compute if we need replicate alpha and emit alpha to coverage
570 prog_data
->replicate_alpha
= key
->alpha_test_replicate_alpha
||
571 (key
->nr_color_regions
> 1 && key
->alpha_to_coverage
&&
572 (sample_mask
.file
== BAD_FILE
|| devinfo
->gen
== 6));
574 /* From the SKL PRM, Volume 7, "Alpha Coverage":
575 * "If Pixel Shader outputs oMask, AlphaToCoverage is disabled in
576 * hardware, regardless of the state setting for this feature."
578 if (devinfo
->gen
> 6 && key
->alpha_to_coverage
&&
579 sample_mask
.file
!= BAD_FILE
&& this->outputs
[0].file
!= BAD_FILE
)
580 emit_alpha_to_coverage_workaround(offset(this->outputs
[0], bld
, 3));
582 for (int target
= 0; target
< key
->nr_color_regions
; target
++) {
583 /* Skip over outputs that weren't written. */
584 if (this->outputs
[target
].file
== BAD_FILE
)
587 const fs_builder abld
= bld
.annotate(
588 ralloc_asprintf(this->mem_ctx
, "FB write target %d", target
));
591 if (devinfo
->gen
>= 6 && prog_data
->replicate_alpha
&& target
!= 0)
592 src0_alpha
= offset(outputs
[0], bld
, 3);
594 inst
= emit_single_fb_write(abld
, this->outputs
[target
],
595 this->dual_src_output
, src0_alpha
, 4);
596 inst
->target
= target
;
599 prog_data
->dual_src_blend
= (this->dual_src_output
.file
!= BAD_FILE
&&
600 this->outputs
[0].file
!= BAD_FILE
);
601 assert(!prog_data
->dual_src_blend
|| key
->nr_color_regions
== 1);
604 /* Even if there's no color buffers enabled, we still need to send
605 * alpha out the pipeline to our null renderbuffer to support
606 * alpha-testing, alpha-to-coverage, and so on.
608 /* FINISHME: Factor out this frequently recurring pattern into a
611 const fs_reg srcs
[] = { reg_undef
, reg_undef
,
612 reg_undef
, offset(this->outputs
[0], bld
, 3) };
613 const fs_reg tmp
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 4);
614 bld
.LOAD_PAYLOAD(tmp
, srcs
, 4, 0);
616 inst
= emit_single_fb_write(bld
, tmp
, reg_undef
, reg_undef
, 4);
620 inst
->last_rt
= true;
625 fs_visitor::emit_urb_writes(const fs_reg
&gs_vertex_count
)
627 int slot
, urb_offset
, length
;
628 int starting_urb_offset
= 0;
629 const struct brw_vue_prog_data
*vue_prog_data
=
630 brw_vue_prog_data(this->prog_data
);
631 const struct brw_vs_prog_key
*vs_key
=
632 (const struct brw_vs_prog_key
*) this->key
;
633 const GLbitfield64 psiz_mask
=
634 VARYING_BIT_LAYER
| VARYING_BIT_VIEWPORT
| VARYING_BIT_PSIZ
;
635 const struct brw_vue_map
*vue_map
= &vue_prog_data
->vue_map
;
640 if (stage
== MESA_SHADER_TESS_EVAL
)
641 urb_handle
= fs_reg(retype(brw_vec8_grf(4, 0), BRW_REGISTER_TYPE_UD
));
643 urb_handle
= fs_reg(retype(brw_vec8_grf(1, 0), BRW_REGISTER_TYPE_UD
));
645 opcode opcode
= SHADER_OPCODE_URB_WRITE_SIMD8
;
647 fs_reg per_slot_offsets
;
649 if (stage
== MESA_SHADER_GEOMETRY
) {
650 const struct brw_gs_prog_data
*gs_prog_data
=
651 brw_gs_prog_data(this->prog_data
);
653 /* We need to increment the Global Offset to skip over the control data
654 * header and the extra "Vertex Count" field (1 HWord) at the beginning
655 * of the VUE. We're counting in OWords, so the units are doubled.
657 starting_urb_offset
= 2 * gs_prog_data
->control_data_header_size_hwords
;
658 if (gs_prog_data
->static_vertex_count
== -1)
659 starting_urb_offset
+= 2;
661 /* We also need to use per-slot offsets. The per-slot offset is the
662 * Vertex Count. SIMD8 mode processes 8 different primitives at a
663 * time; each may output a different number of vertices.
665 opcode
= SHADER_OPCODE_URB_WRITE_SIMD8_PER_SLOT
;
668 /* The URB offset is in 128-bit units, so we need to multiply by 2 */
669 const int output_vertex_size_owords
=
670 gs_prog_data
->output_vertex_size_hwords
* 2;
672 if (gs_vertex_count
.file
== IMM
) {
673 per_slot_offsets
= brw_imm_ud(output_vertex_size_owords
*
676 per_slot_offsets
= vgrf(glsl_type::uint_type
);
677 bld
.MUL(per_slot_offsets
, gs_vertex_count
,
678 brw_imm_ud(output_vertex_size_owords
));
683 urb_offset
= starting_urb_offset
;
686 /* SSO shaders can have VUE slots allocated which are never actually
687 * written to, so ignore them when looking for the last (written) slot.
689 int last_slot
= vue_map
->num_slots
- 1;
690 while (last_slot
> 0 &&
691 (vue_map
->slot_to_varying
[last_slot
] == BRW_VARYING_SLOT_PAD
||
692 outputs
[vue_map
->slot_to_varying
[last_slot
]].file
== BAD_FILE
)) {
696 bool urb_written
= false;
697 for (slot
= 0; slot
< vue_map
->num_slots
; slot
++) {
698 int varying
= vue_map
->slot_to_varying
[slot
];
700 case VARYING_SLOT_PSIZ
: {
701 /* The point size varying slot is the vue header and is always in the
702 * vue map. But often none of the special varyings that live there
703 * are written and in that case we can skip writing to the vue
704 * header, provided the corresponding state properly clamps the
705 * values further down the pipeline. */
706 if ((vue_map
->slots_valid
& psiz_mask
) == 0) {
712 fs_reg
zero(VGRF
, alloc
.allocate(1), BRW_REGISTER_TYPE_UD
);
713 bld
.MOV(zero
, brw_imm_ud(0u));
715 sources
[length
++] = zero
;
716 if (vue_map
->slots_valid
& VARYING_BIT_LAYER
)
717 sources
[length
++] = this->outputs
[VARYING_SLOT_LAYER
];
719 sources
[length
++] = zero
;
721 if (vue_map
->slots_valid
& VARYING_BIT_VIEWPORT
)
722 sources
[length
++] = this->outputs
[VARYING_SLOT_VIEWPORT
];
724 sources
[length
++] = zero
;
726 if (vue_map
->slots_valid
& VARYING_BIT_PSIZ
)
727 sources
[length
++] = this->outputs
[VARYING_SLOT_PSIZ
];
729 sources
[length
++] = zero
;
732 case BRW_VARYING_SLOT_NDC
:
733 case VARYING_SLOT_EDGE
:
734 unreachable("unexpected scalar vs output");
738 /* gl_Position is always in the vue map, but isn't always written by
739 * the shader. Other varyings (clip distances) get added to the vue
740 * map but don't always get written. In those cases, the
741 * corresponding this->output[] slot will be invalid we and can skip
742 * the urb write for the varying. If we've already queued up a vue
743 * slot for writing we flush a mlen 5 urb write, otherwise we just
744 * advance the urb_offset.
746 if (varying
== BRW_VARYING_SLOT_PAD
||
747 this->outputs
[varying
].file
== BAD_FILE
) {
755 if (stage
== MESA_SHADER_VERTEX
&& vs_key
->clamp_vertex_color
&&
756 (varying
== VARYING_SLOT_COL0
||
757 varying
== VARYING_SLOT_COL1
||
758 varying
== VARYING_SLOT_BFC0
||
759 varying
== VARYING_SLOT_BFC1
)) {
760 /* We need to clamp these guys, so do a saturating MOV into a
761 * temp register and use that for the payload.
763 for (int i
= 0; i
< 4; i
++) {
764 fs_reg reg
= fs_reg(VGRF
, alloc
.allocate(1), outputs
[varying
].type
);
765 fs_reg src
= offset(this->outputs
[varying
], bld
, i
);
766 set_saturate(true, bld
.MOV(reg
, src
));
767 sources
[length
++] = reg
;
770 for (unsigned i
= 0; i
< 4; i
++)
771 sources
[length
++] = offset(this->outputs
[varying
], bld
, i
);
776 const fs_builder abld
= bld
.annotate("URB write");
778 /* If we've queued up 8 registers of payload (2 VUE slots), if this is
779 * the last slot or if we need to flush (see BAD_FILE varying case
780 * above), emit a URB write send now to flush out the data.
782 if (length
== 8 || (length
> 0 && slot
== last_slot
))
785 fs_reg
*payload_sources
=
786 ralloc_array(mem_ctx
, fs_reg
, length
+ header_size
);
787 fs_reg payload
= fs_reg(VGRF
, alloc
.allocate(length
+ header_size
),
788 BRW_REGISTER_TYPE_F
);
789 payload_sources
[0] = urb_handle
;
791 if (opcode
== SHADER_OPCODE_URB_WRITE_SIMD8_PER_SLOT
)
792 payload_sources
[1] = per_slot_offsets
;
794 memcpy(&payload_sources
[header_size
], sources
,
795 length
* sizeof sources
[0]);
797 abld
.LOAD_PAYLOAD(payload
, payload_sources
, length
+ header_size
,
800 fs_inst
*inst
= abld
.emit(opcode
, reg_undef
, payload
);
802 /* For ICL WA 1805992985 one needs additional write in the end. */
803 if (devinfo
->gen
== 11 && stage
== MESA_SHADER_TESS_EVAL
)
806 inst
->eot
= slot
== last_slot
&& stage
!= MESA_SHADER_GEOMETRY
;
808 inst
->mlen
= length
+ header_size
;
809 inst
->offset
= urb_offset
;
810 urb_offset
= starting_urb_offset
+ slot
+ 1;
817 /* If we don't have any valid slots to write, just do a minimal urb write
818 * send to terminate the shader. This includes 1 slot of undefined data,
819 * because it's invalid to write 0 data:
821 * From the Broadwell PRM, Volume 7: 3D Media GPGPU, Shared Functions -
822 * Unified Return Buffer (URB) > URB_SIMD8_Write and URB_SIMD8_Read >
823 * Write Data Payload:
825 * "The write data payload can be between 1 and 8 message phases long."
828 /* For GS, just turn EmitVertex() into a no-op. We don't want it to
829 * end the thread, and emit_gs_thread_end() already emits a SEND with
830 * EOT at the end of the program for us.
832 if (stage
== MESA_SHADER_GEOMETRY
)
835 fs_reg payload
= fs_reg(VGRF
, alloc
.allocate(2), BRW_REGISTER_TYPE_UD
);
836 bld
.exec_all().MOV(payload
, urb_handle
);
838 fs_inst
*inst
= bld
.emit(SHADER_OPCODE_URB_WRITE_SIMD8
, reg_undef
, payload
);
845 /* ICL WA 1805992985:
847 * ICLLP GPU hangs on one of tessellation vkcts tests with DS not done. The
848 * send cycle, which is a urb write with an eot must be 4 phases long and
849 * all 8 lanes must valid.
851 if (devinfo
->gen
== 11 && stage
== MESA_SHADER_TESS_EVAL
) {
852 fs_reg payload
= fs_reg(VGRF
, alloc
.allocate(6), BRW_REGISTER_TYPE_UD
);
854 /* Workaround requires all 8 channels (lanes) to be valid. This is
855 * understood to mean they all need to be alive. First trick is to find
856 * a live channel and copy its urb handle for all the other channels to
857 * make sure all handles are valid.
859 bld
.exec_all().MOV(payload
, bld
.emit_uniformize(urb_handle
));
861 /* Second trick is to use masked URB write where one can tell the HW to
862 * actually write data only for selected channels even though all are
864 * Third trick is to take advantage of the must-be-zero (MBZ) area in
865 * the very beginning of the URB.
867 * One masks data to be written only for the first channel and uses
868 * offset zero explicitly to land data to the MBZ area avoiding trashing
869 * any other part of the URB.
871 * Since the WA says that the write needs to be 4 phases long one uses
872 * 4 slots data. All are explicitly zeros in order to to keep the MBZ
873 * area written as zeros.
875 bld
.exec_all().MOV(offset(payload
, bld
, 1), brw_imm_ud(0x10000u
));
876 bld
.exec_all().MOV(offset(payload
, bld
, 2), brw_imm_ud(0u));
877 bld
.exec_all().MOV(offset(payload
, bld
, 3), brw_imm_ud(0u));
878 bld
.exec_all().MOV(offset(payload
, bld
, 4), brw_imm_ud(0u));
879 bld
.exec_all().MOV(offset(payload
, bld
, 5), brw_imm_ud(0u));
881 fs_inst
*inst
= bld
.exec_all().emit(SHADER_OPCODE_URB_WRITE_SIMD8_MASKED
,
890 fs_visitor::emit_cs_terminate()
892 assert(devinfo
->gen
>= 7);
894 /* We are getting the thread ID from the compute shader header */
895 assert(stage
== MESA_SHADER_COMPUTE
);
897 /* We can't directly send from g0, since sends with EOT have to use
898 * g112-127. So, copy it to a virtual register, The register allocator will
899 * make sure it uses the appropriate register range.
901 struct brw_reg g0
= retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UD
);
902 fs_reg payload
= fs_reg(VGRF
, alloc
.allocate(1), BRW_REGISTER_TYPE_UD
);
903 bld
.group(8, 0).exec_all().MOV(payload
, g0
);
905 /* Send a message to the thread spawner to terminate the thread. */
906 fs_inst
*inst
= bld
.exec_all()
907 .emit(CS_OPCODE_CS_TERMINATE
, reg_undef
, payload
);
912 fs_visitor::emit_barrier()
914 uint32_t barrier_id_mask
;
915 switch (devinfo
->gen
) {
918 barrier_id_mask
= 0x0f000000u
; break;
921 barrier_id_mask
= 0x8f000000u
; break;
923 barrier_id_mask
= 0x7f000000u
; break;
925 unreachable("barrier is only available on gen >= 7");
928 /* We are getting the barrier ID from the compute shader header */
929 assert(stage
== MESA_SHADER_COMPUTE
);
931 fs_reg payload
= fs_reg(VGRF
, alloc
.allocate(1), BRW_REGISTER_TYPE_UD
);
933 /* Clear the message payload */
934 bld
.exec_all().group(8, 0).MOV(payload
, brw_imm_ud(0u));
936 /* Copy the barrier id from r0.2 to the message payload reg.2 */
937 fs_reg r0_2
= fs_reg(retype(brw_vec1_grf(0, 2), BRW_REGISTER_TYPE_UD
));
938 bld
.exec_all().group(1, 0).AND(component(payload
, 2), r0_2
,
939 brw_imm_ud(barrier_id_mask
));
941 /* Emit a gateway "barrier" message using the payload we set up, followed
942 * by a wait instruction.
944 bld
.exec_all().emit(SHADER_OPCODE_BARRIER
, reg_undef
, payload
);
947 fs_visitor::fs_visitor(const struct brw_compiler
*compiler
, void *log_data
,
949 const brw_base_prog_key
*key
,
950 struct brw_stage_prog_data
*prog_data
,
951 const nir_shader
*shader
,
952 unsigned dispatch_width
,
953 int shader_time_index
,
954 const struct brw_vue_map
*input_vue_map
)
955 : backend_shader(compiler
, log_data
, mem_ctx
, shader
, prog_data
),
956 key(key
), gs_compile(NULL
), prog_data(prog_data
),
957 input_vue_map(input_vue_map
),
958 dispatch_width(dispatch_width
),
959 shader_time_index(shader_time_index
),
960 bld(fs_builder(this, dispatch_width
).at_end())
965 fs_visitor::fs_visitor(const struct brw_compiler
*compiler
, void *log_data
,
967 struct brw_gs_compile
*c
,
968 struct brw_gs_prog_data
*prog_data
,
969 const nir_shader
*shader
,
970 int shader_time_index
)
971 : backend_shader(compiler
, log_data
, mem_ctx
, shader
,
972 &prog_data
->base
.base
),
973 key(&c
->key
.base
), gs_compile(c
),
974 prog_data(&prog_data
->base
.base
),
976 shader_time_index(shader_time_index
),
977 bld(fs_builder(this, dispatch_width
).at_end())
986 this->key_tex
= &key
->tex
;
988 this->max_dispatch_width
= 32;
989 this->prog_data
= this->stage_prog_data
;
991 this->failed
= false;
993 this->nir_locals
= NULL
;
994 this->nir_ssa_values
= NULL
;
996 memset(&this->payload
, 0, sizeof(this->payload
));
997 this->source_depth_to_render_target
= false;
998 this->runtime_check_aads_emit
= false;
999 this->first_non_payload_grf
= 0;
1000 this->max_grf
= devinfo
->gen
>= 7 ? GEN7_MRF_HACK_START
: BRW_MAX_GRF
;
1002 this->virtual_grf_start
= NULL
;
1003 this->virtual_grf_end
= NULL
;
1004 this->live_intervals
= NULL
;
1005 this->regs_live_at_ip
= NULL
;
1008 this->last_scratch
= 0;
1009 this->pull_constant_loc
= NULL
;
1010 this->push_constant_loc
= NULL
;
1012 this->shader_stats
.scheduler_mode
= NULL
;
1013 this->shader_stats
.promoted_constants
= 0,
1016 this->spilled_any_registers
= false;
1019 fs_visitor::~fs_visitor()