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[mesa.git] / src / intel / compiler / brw_inst.h
1 /*
2 * Copyright © 2014 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 */
23
24 /**
25 * @file brw_inst.h
26 *
27 * A representation of i965 EU assembly instructions, with helper methods to
28 * get and set various fields. This is the actual hardware format.
29 */
30
31 #ifndef BRW_INST_H
32 #define BRW_INST_H
33
34 #include <assert.h>
35 #include <stdint.h>
36
37 #include "brw_eu_defines.h"
38 #include "brw_reg_type.h"
39 #include "common/gen_device_info.h"
40
41 #ifdef __cplusplus
42 extern "C" {
43 #endif
44
45 /* brw_context.h has a forward declaration of brw_inst, so name the struct. */
46 typedef struct brw_inst {
47 uint64_t data[2];
48 } brw_inst;
49
50 static inline uint64_t brw_inst_bits(const brw_inst *inst,
51 unsigned high, unsigned low);
52 static inline void brw_inst_set_bits(brw_inst *inst,
53 unsigned high, unsigned low,
54 uint64_t value);
55
56 #define FC(name, high, low, assertions) \
57 static inline void \
58 brw_inst_set_##name(const struct gen_device_info *devinfo, \
59 brw_inst *inst, uint64_t v) \
60 { \
61 assert(assertions); \
62 (void) devinfo; \
63 brw_inst_set_bits(inst, high, low, v); \
64 } \
65 static inline uint64_t \
66 brw_inst_##name(const struct gen_device_info *devinfo, \
67 const brw_inst *inst) \
68 { \
69 assert(assertions); \
70 (void) devinfo; \
71 return brw_inst_bits(inst, high, low); \
72 }
73
74 /* A simple macro for fields which stay in the same place on all generations. */
75 #define F(name, high, low) FC(name, high, low, true)
76
77 #define BOUNDS(hi4, lo4, hi45, lo45, hi5, lo5, hi6, lo6, hi7, lo7, hi8, lo8) \
78 unsigned high, low; \
79 if (devinfo->gen >= 8) { \
80 high = hi8; low = lo8; \
81 } else if (devinfo->gen >= 7) { \
82 high = hi7; low = lo7; \
83 } else if (devinfo->gen >= 6) { \
84 high = hi6; low = lo6; \
85 } else if (devinfo->gen >= 5) { \
86 high = hi5; low = lo5; \
87 } else if (devinfo->is_g4x) { \
88 high = hi45; low = lo45; \
89 } else { \
90 high = hi4; low = lo4; \
91 } \
92 assert(((int) high) != -1 && ((int) low) != -1);
93
94 /* A general macro for cases where the field has moved to several different
95 * bit locations across generations. GCC appears to combine cases where the
96 * bits are identical, removing some of the inefficiency.
97 */
98 #define FF(name, hi4, lo4, hi45, lo45, hi5, lo5, hi6, lo6, hi7, lo7, hi8, lo8)\
99 static inline void \
100 brw_inst_set_##name(const struct gen_device_info *devinfo, \
101 brw_inst *inst, uint64_t value) \
102 { \
103 BOUNDS(hi4, lo4, hi45, lo45, hi5, lo5, hi6, lo6, hi7, lo7, hi8, lo8) \
104 brw_inst_set_bits(inst, high, low, value); \
105 } \
106 static inline uint64_t \
107 brw_inst_##name(const struct gen_device_info *devinfo, const brw_inst *inst) \
108 { \
109 BOUNDS(hi4, lo4, hi45, lo45, hi5, lo5, hi6, lo6, hi7, lo7, hi8, lo8) \
110 return brw_inst_bits(inst, high, low); \
111 }
112
113 /* A macro for fields which moved as of Gen8+. */
114 #define F8(name, gen4_high, gen4_low, gen8_high, gen8_low) \
115 FF(name, \
116 /* 4: */ gen4_high, gen4_low, \
117 /* 4.5: */ gen4_high, gen4_low, \
118 /* 5: */ gen4_high, gen4_low, \
119 /* 6: */ gen4_high, gen4_low, \
120 /* 7: */ gen4_high, gen4_low, \
121 /* 8: */ gen8_high, gen8_low);
122
123 F(src1_vstride, 120, 117)
124 F(src1_width, 116, 114)
125 F(src1_da16_swiz_w, 115, 114)
126 F(src1_da16_swiz_z, 113, 112)
127 F(src1_hstride, 113, 112)
128 F(src1_address_mode, 111, 111)
129 /** Src1.SrcMod @{ */
130 F(src1_negate, 110, 110)
131 F(src1_abs, 109, 109)
132 /** @} */
133 F8(src1_ia_subreg_nr, /* 4+ */ 108, 106, /* 8+ */ 108, 105)
134 F(src1_da_reg_nr, 108, 101)
135 F(src1_da16_subreg_nr, 100, 100)
136 F(src1_da1_subreg_nr, 100, 96)
137 F(src1_da16_swiz_y, 99, 98)
138 F(src1_da16_swiz_x, 97, 96)
139 F8(src1_reg_hw_type, /* 4+ */ 46, 44, /* 8+ */ 94, 91)
140 F8(src1_reg_file, /* 4+ */ 43, 42, /* 8+ */ 90, 89)
141 F(src0_vstride, 88, 85)
142 F(src0_width, 84, 82)
143 F(src0_da16_swiz_w, 83, 82)
144 F(src0_da16_swiz_z, 81, 80)
145 F(src0_hstride, 81, 80)
146 F(src0_address_mode, 79, 79)
147 /** Src0.SrcMod @{ */
148 F(src0_negate, 78, 78)
149 F(src0_abs, 77, 77)
150 /** @} */
151 F8(src0_ia_subreg_nr, /* 4+ */ 76, 74, /* 8+ */ 76, 73)
152 F(src0_da_reg_nr, 76, 69)
153 F(src0_da16_subreg_nr, 68, 68)
154 F(src0_da1_subreg_nr, 68, 64)
155 F(src0_da16_swiz_y, 67, 66)
156 F(src0_da16_swiz_x, 65, 64)
157 F(dst_address_mode, 63, 63)
158 F(dst_hstride, 62, 61)
159 F8(dst_ia_subreg_nr, /* 4+ */ 60, 58, /* 8+ */ 60, 57)
160 F(dst_da_reg_nr, 60, 53)
161 F(dst_da16_subreg_nr, 52, 52)
162 F(dst_da1_subreg_nr, 52, 48)
163 F(da16_writemask, 51, 48) /* Dst.ChanEn */
164 F8(src0_reg_hw_type, /* 4+ */ 41, 39, /* 8+ */ 46, 43)
165 F8(src0_reg_file, /* 4+ */ 38, 37, /* 8+ */ 42, 41)
166 F8(dst_reg_hw_type, /* 4+ */ 36, 34, /* 8+ */ 40, 37)
167 F8(dst_reg_file, /* 4+ */ 33, 32, /* 8+ */ 36, 35)
168 F8(mask_control, /* 4+ */ 9, 9, /* 8+ */ 34, 34)
169 FF(flag_reg_nr,
170 /* 4-6: doesn't exist */ -1, -1, -1, -1, -1, -1, -1, -1,
171 /* 7: */ 90, 90,
172 /* 8: */ 33, 33)
173 F8(flag_subreg_nr, /* 4+ */ 89, 89, /* 8+ */ 32, 32)
174 F(saturate, 31, 31)
175 F(debug_control, 30, 30)
176 F(cmpt_control, 29, 29)
177 FC(branch_control, 28, 28, devinfo->gen >= 8)
178 FC(acc_wr_control, 28, 28, devinfo->gen >= 6)
179 FC(mask_control_ex, 28, 28, devinfo->is_g4x || devinfo->gen == 5)
180 F(cond_modifier, 27, 24)
181 FC(math_function, 27, 24, devinfo->gen >= 6)
182 F(exec_size, 23, 21)
183 F(pred_inv, 20, 20)
184 F(pred_control, 19, 16)
185 F(thread_control, 15, 14)
186 F(qtr_control, 13, 12)
187 FF(nib_control,
188 /* 4-6: doesn't exist */ -1, -1, -1, -1, -1, -1, -1, -1,
189 /* 7: */ 47, 47,
190 /* 8: */ 11, 11)
191 F8(no_dd_check, /* 4+ */ 11, 11, /* 8+ */ 10, 10)
192 F8(no_dd_clear, /* 4+ */ 10, 10, /* 8+ */ 9, 9)
193 F(access_mode, 8, 8)
194 /* Bit 7 is Reserved (for future Opcode expansion) */
195 F(opcode, 6, 0)
196
197 /**
198 * Three-source instructions:
199 * @{
200 */
201 F(3src_src2_reg_nr, 125, 118) /* same in align1 */
202 F(3src_a16_src2_subreg_nr, 117, 115) /* Extra discontiguous bit on CHV? */
203 F(3src_a16_src2_swizzle, 114, 107)
204 F(3src_a16_src2_rep_ctrl, 106, 106)
205 F(3src_src1_reg_nr, 104, 97) /* same in align1 */
206 F(3src_a16_src1_subreg_nr, 96, 94) /* Extra discontiguous bit on CHV? */
207 F(3src_a16_src1_swizzle, 93, 86)
208 F(3src_a16_src1_rep_ctrl, 85, 85)
209 F(3src_src0_reg_nr, 83, 76) /* same in align1 */
210 F(3src_a16_src0_subreg_nr, 75, 73) /* Extra discontiguous bit on CHV? */
211 F(3src_a16_src0_swizzle, 72, 65)
212 F(3src_a16_src0_rep_ctrl, 64, 64)
213 F(3src_dst_reg_nr, 63, 56) /* same in align1 */
214 F(3src_a16_dst_subreg_nr, 55, 53)
215 F(3src_a16_dst_writemask, 52, 49)
216 F8(3src_a16_nib_ctrl, 47, 47, 11, 11) /* only exists on IVB+ */
217 F8(3src_a16_dst_hw_type, 45, 44, 48, 46) /* only exists on IVB+ */
218 F8(3src_a16_src_hw_type, 43, 42, 45, 43)
219 F8(3src_src2_negate, 41, 41, 42, 42)
220 F8(3src_src2_abs, 40, 40, 41, 41)
221 F8(3src_src1_negate, 39, 39, 40, 40)
222 F8(3src_src1_abs, 38, 38, 39, 39)
223 F8(3src_src0_negate, 37, 37, 38, 38)
224 F8(3src_src0_abs, 36, 36, 37, 37)
225 F8(3src_a16_flag_reg_nr, 34, 34, 33, 33)
226 F8(3src_a16_flag_subreg_nr, 33, 33, 32, 32)
227 FF(3src_a16_dst_reg_file,
228 /* 4-5: doesn't exist - no 3-source instructions */ -1, -1, -1, -1, -1, -1,
229 /* 6: */ 32, 32,
230 /* 7-8: doesn't exist - no MRFs */ -1, -1, -1, -1)
231 F(3src_saturate, 31, 31)
232 F(3src_debug_control, 30, 30)
233 F(3src_cmpt_control, 29, 29)
234 F(3src_acc_wr_control, 28, 28)
235 F(3src_cond_modifier, 27, 24)
236 F(3src_exec_size, 23, 21)
237 F(3src_pred_inv, 20, 20)
238 F(3src_pred_control, 19, 16)
239 F(3src_thread_control, 15, 14)
240 F(3src_qtr_control, 13, 12)
241 F8(3src_no_dd_check, 11, 11, 10, 10)
242 F8(3src_no_dd_clear, 10, 10, 9, 9)
243 F8(3src_mask_control, 9, 9, 34, 34)
244 F(3src_access_mode, 8, 8)
245 /* Bit 7 is Reserved (for future Opcode expansion) */
246 F(3src_opcode, 6, 0)
247 /** @} */
248
249 #define REG_TYPE(reg) \
250 static inline void \
251 brw_inst_set_3src_a16_##reg##_type(const struct gen_device_info *devinfo, \
252 brw_inst *inst, enum brw_reg_type type) \
253 { \
254 unsigned hw_type = brw_reg_type_to_a16_hw_3src_type(devinfo, type); \
255 brw_inst_set_3src_a16_##reg##_hw_type(devinfo, inst, hw_type); \
256 } \
257 \
258 static inline enum brw_reg_type \
259 brw_inst_3src_a16_##reg##_type(const struct gen_device_info *devinfo, \
260 const brw_inst *inst) \
261 { \
262 unsigned hw_type = brw_inst_3src_a16_##reg##_hw_type(devinfo, inst); \
263 return brw_a16_hw_3src_type_to_reg_type(devinfo, hw_type); \
264 }
265
266 REG_TYPE(dst)
267 REG_TYPE(src)
268 #undef REG_TYPE
269
270 /**
271 * Flow control instruction bits:
272 * @{
273 */
274 static inline void
275 brw_inst_set_uip(const struct gen_device_info *devinfo,
276 brw_inst *inst, int32_t value)
277 {
278 assert(devinfo->gen >= 6);
279
280 if (devinfo->gen >= 8) {
281 brw_inst_set_bits(inst, 95, 64, (uint32_t)value);
282 } else {
283 assert(value <= (1 << 16) - 1);
284 assert(value > -(1 << 16));
285 brw_inst_set_bits(inst, 127, 112, (uint16_t)value);
286 }
287 }
288
289 static inline int32_t
290 brw_inst_uip(const struct gen_device_info *devinfo, const brw_inst *inst)
291 {
292 assert(devinfo->gen >= 6);
293
294 if (devinfo->gen >= 8) {
295 return brw_inst_bits(inst, 95, 64);
296 } else {
297 return (int16_t)brw_inst_bits(inst, 127, 112);
298 }
299 }
300
301 static inline void
302 brw_inst_set_jip(const struct gen_device_info *devinfo,
303 brw_inst *inst, int32_t value)
304 {
305 assert(devinfo->gen >= 6);
306
307 if (devinfo->gen >= 8) {
308 brw_inst_set_bits(inst, 127, 96, (uint32_t)value);
309 } else {
310 assert(value <= (1 << 15) - 1);
311 assert(value >= -(1 << 15));
312 brw_inst_set_bits(inst, 111, 96, (uint16_t)value);
313 }
314 }
315
316 static inline int32_t
317 brw_inst_jip(const struct gen_device_info *devinfo, const brw_inst *inst)
318 {
319 assert(devinfo->gen >= 6);
320
321 if (devinfo->gen >= 8) {
322 return brw_inst_bits(inst, 127, 96);
323 } else {
324 return (int16_t)brw_inst_bits(inst, 111, 96);
325 }
326 }
327
328 /** Like FC, but using int16_t to handle negative jump targets. */
329 #define FJ(name, high, low, assertions) \
330 static inline void \
331 brw_inst_set_##name(const struct gen_device_info *devinfo, brw_inst *inst, int16_t v) \
332 { \
333 assert(assertions); \
334 (void) devinfo; \
335 brw_inst_set_bits(inst, high, low, (uint16_t) v); \
336 } \
337 static inline int16_t \
338 brw_inst_##name(const struct gen_device_info *devinfo, const brw_inst *inst) \
339 { \
340 assert(assertions); \
341 (void) devinfo; \
342 return brw_inst_bits(inst, high, low); \
343 }
344
345 FJ(gen6_jump_count, 63, 48, devinfo->gen == 6)
346 FJ(gen4_jump_count, 111, 96, devinfo->gen < 6)
347 FC(gen4_pop_count, 115, 112, devinfo->gen < 6)
348 /** @} */
349
350 /* Message descriptor bits */
351 #define MD(x) ((x) + 96)
352
353 /**
354 * Fields for SEND messages:
355 * @{
356 */
357 F(eot, 127, 127)
358 FF(mlen,
359 /* 4: */ 119, 116,
360 /* 4.5: */ 119, 116,
361 /* 5: */ 124, 121,
362 /* 6: */ 124, 121,
363 /* 7: */ 124, 121,
364 /* 8: */ 124, 121);
365 FF(rlen,
366 /* 4: */ 115, 112,
367 /* 4.5: */ 115, 112,
368 /* 5: */ 120, 116,
369 /* 6: */ 120, 116,
370 /* 7: */ 120, 116,
371 /* 8: */ 120, 116);
372 FF(header_present,
373 /* 4: doesn't exist */ -1, -1, -1, -1,
374 /* 5: */ 115, 115,
375 /* 6: */ 115, 115,
376 /* 7: */ 115, 115,
377 /* 8: */ 115, 115)
378 F(gateway_notify, MD(16), MD(15))
379 FF(function_control,
380 /* 4: */ 111, 96,
381 /* 4.5: */ 111, 96,
382 /* 5: */ 114, 96,
383 /* 6: */ 114, 96,
384 /* 7: */ 114, 96,
385 /* 8: */ 114, 96)
386 FF(gateway_subfuncid,
387 /* 4: */ MD(1), MD(0),
388 /* 4.5: */ MD(1), MD(0),
389 /* 5: */ MD(1), MD(0), /* 2:0, but bit 2 is reserved MBZ */
390 /* 6: */ MD(2), MD(0),
391 /* 7: */ MD(2), MD(0),
392 /* 8: */ MD(2), MD(0))
393 FF(sfid,
394 /* 4: */ 123, 120, /* called msg_target */
395 /* 4.5 */ 123, 120,
396 /* 5: */ 95, 92,
397 /* 6: */ 27, 24,
398 /* 7: */ 27, 24,
399 /* 8: */ 27, 24)
400 FC(base_mrf, 27, 24, devinfo->gen < 6);
401 /** @} */
402
403 /**
404 * URB message function control bits:
405 * @{
406 */
407 FF(urb_per_slot_offset,
408 /* 4-6: */ -1, -1, -1, -1, -1, -1, -1, -1,
409 /* 7: */ MD(16), MD(16),
410 /* 8: */ MD(17), MD(17))
411 FC(urb_channel_mask_present, MD(15), MD(15), devinfo->gen >= 8)
412 FC(urb_complete, MD(15), MD(15), devinfo->gen < 8)
413 FC(urb_used, MD(14), MD(14), devinfo->gen < 7)
414 FC(urb_allocate, MD(13), MD(13), devinfo->gen < 7)
415 FF(urb_swizzle_control,
416 /* 4: */ MD(11), MD(10),
417 /* 4.5: */ MD(11), MD(10),
418 /* 5: */ MD(11), MD(10),
419 /* 6: */ MD(11), MD(10),
420 /* 7: */ MD(14), MD(14),
421 /* 8: */ MD(15), MD(15))
422 FF(urb_global_offset,
423 /* 4: */ MD( 9), MD(4),
424 /* 4.5: */ MD( 9), MD(4),
425 /* 5: */ MD( 9), MD(4),
426 /* 6: */ MD( 9), MD(4),
427 /* 7: */ MD(13), MD(3),
428 /* 8: */ MD(14), MD(4))
429 FF(urb_opcode,
430 /* 4: */ MD( 3), MD(0),
431 /* 4.5: */ MD( 3), MD(0),
432 /* 5: */ MD( 3), MD(0),
433 /* 6: */ MD( 3), MD(0),
434 /* 7: */ MD( 2), MD(0),
435 /* 8: */ MD( 3), MD(0))
436 /** @} */
437
438 /**
439 * Gen4-5 math messages:
440 * @{
441 */
442 FC(math_msg_data_type, MD(7), MD(7), devinfo->gen < 6)
443 FC(math_msg_saturate, MD(6), MD(6), devinfo->gen < 6)
444 FC(math_msg_precision, MD(5), MD(5), devinfo->gen < 6)
445 FC(math_msg_signed_int, MD(4), MD(4), devinfo->gen < 6)
446 FC(math_msg_function, MD(3), MD(0), devinfo->gen < 6)
447 /** @} */
448
449 /**
450 * Sampler message function control bits:
451 * @{
452 */
453 FF(sampler_simd_mode,
454 /* 4: doesn't exist */ -1, -1, -1, -1,
455 /* 5: */ MD(17), MD(16),
456 /* 6: */ MD(17), MD(16),
457 /* 7: */ MD(18), MD(17),
458 /* 8: */ MD(18), MD(17))
459 FF(sampler_msg_type,
460 /* 4: */ MD(15), MD(14),
461 /* 4.5: */ MD(15), MD(12),
462 /* 5: */ MD(15), MD(12),
463 /* 6: */ MD(15), MD(12),
464 /* 7: */ MD(16), MD(12),
465 /* 8: */ MD(16), MD(12))
466 FC(sampler_return_format, MD(13), MD(12), devinfo->gen == 4 && !devinfo->is_g4x)
467 F(sampler, MD(11), MD(8))
468 F(binding_table_index, MD( 7), MD(0)) /* also used by other messages */
469 /** @} */
470
471 /**
472 * Data port message function control bits:
473 * @{
474 */
475 FC(dp_category, MD(18), MD(18), devinfo->gen >= 7)
476
477 /* Gen4-5 store fields in different bits for read/write messages. */
478 FF(dp_read_msg_type,
479 /* 4: */ MD(13), MD(12),
480 /* 4.5: */ MD(13), MD(11),
481 /* 5: */ MD(13), MD(11),
482 /* 6: */ MD(16), MD(13),
483 /* 7: */ MD(17), MD(14),
484 /* 8: */ MD(17), MD(14))
485 FF(dp_write_msg_type,
486 /* 4: */ MD(14), MD(12),
487 /* 4.5: */ MD(14), MD(12),
488 /* 5: */ MD(14), MD(12),
489 /* 6: */ MD(16), MD(13),
490 /* 7: */ MD(17), MD(14),
491 /* 8: */ MD(17), MD(14))
492 FF(dp_read_msg_control,
493 /* 4: */ MD(11), MD( 8),
494 /* 4.5: */ MD(10), MD( 8),
495 /* 5: */ MD(10), MD( 8),
496 /* 6: */ MD(12), MD( 8),
497 /* 7: */ MD(13), MD( 8),
498 /* 8: */ MD(13), MD( 8))
499 FF(dp_write_msg_control,
500 /* 4: */ MD(11), MD( 8),
501 /* 4.5: */ MD(11), MD( 8),
502 /* 5: */ MD(11), MD( 8),
503 /* 6: */ MD(12), MD( 8),
504 /* 7: */ MD(13), MD( 8),
505 /* 8: */ MD(13), MD( 8))
506 FC(dp_read_target_cache, MD(15), MD(14), devinfo->gen < 6);
507
508 FF(dp_write_commit,
509 /* 4: */ MD(15), MD(15),
510 /* 4.5: */ MD(15), MD(15),
511 /* 5: */ MD(15), MD(15),
512 /* 6: */ MD(17), MD(17),
513 /* 7+: does not exist */ -1, -1, -1, -1)
514
515 /* Gen6+ use the same bit locations for everything. */
516 FF(dp_msg_type,
517 /* 4-5: use dp_read_msg_type or dp_write_msg_type instead */
518 -1, -1, -1, -1, -1, -1,
519 /* 6: */ MD(16), MD(13),
520 /* 7: */ MD(17), MD(14),
521 /* 8: */ MD(17), MD(14))
522 FF(dp_msg_control,
523 /* 4: */ MD(11), MD( 8),
524 /* 4.5-5: use dp_read_msg_control or dp_write_msg_control */ -1, -1, -1, -1,
525 /* 6: */ MD(12), MD( 8),
526 /* 7: */ MD(13), MD( 8),
527 /* 8: */ MD(13), MD( 8))
528 /** @} */
529
530 /**
531 * Scratch message bits (Gen7+):
532 * @{
533 */
534 FC(scratch_read_write, MD(17), MD(17), devinfo->gen >= 7) /* 0 = read, 1 = write */
535 FC(scratch_type, MD(16), MD(16), devinfo->gen >= 7) /* 0 = OWord, 1 = DWord */
536 FC(scratch_invalidate_after_read, MD(15), MD(15), devinfo->gen >= 7)
537 FC(scratch_block_size, MD(13), MD(12), devinfo->gen >= 7)
538 FC(scratch_addr_offset, MD(11), MD( 0), devinfo->gen >= 7)
539 /** @} */
540
541 /**
542 * Render Target message function control bits:
543 * @{
544 */
545 FF(rt_last,
546 /* 4: */ MD(11), MD(11),
547 /* 4.5: */ MD(11), MD(11),
548 /* 5: */ MD(11), MD(11),
549 /* 6: */ MD(12), MD(12),
550 /* 7: */ MD(12), MD(12),
551 /* 8: */ MD(12), MD(12))
552 FC(rt_slot_group, MD(11), MD(11), devinfo->gen >= 6)
553 F(rt_message_type, MD(10), MD( 8))
554 /** @} */
555
556 /**
557 * Thread Spawn message function control bits:
558 * @{
559 */
560 F(ts_resource_select, MD( 4), MD( 4))
561 F(ts_request_type, MD( 1), MD( 1))
562 F(ts_opcode, MD( 0), MD( 0))
563 /** @} */
564
565 /**
566 * Pixel Interpolator message function control bits:
567 * @{
568 */
569 F(pi_simd_mode, MD(16), MD(16))
570 F(pi_nopersp, MD(14), MD(14))
571 F(pi_message_type, MD(13), MD(12))
572 F(pi_slot_group, MD(11), MD(11))
573 F(pi_message_data, MD(7), MD(0))
574 /** @} */
575
576 /**
577 * Immediates:
578 * @{
579 */
580 static inline int
581 brw_inst_imm_d(const struct gen_device_info *devinfo, const brw_inst *insn)
582 {
583 (void) devinfo;
584 return brw_inst_bits(insn, 127, 96);
585 }
586
587 static inline unsigned
588 brw_inst_imm_ud(const struct gen_device_info *devinfo, const brw_inst *insn)
589 {
590 (void) devinfo;
591 return brw_inst_bits(insn, 127, 96);
592 }
593
594 static inline uint64_t
595 brw_inst_imm_uq(const struct gen_device_info *devinfo, const brw_inst *insn)
596 {
597 assert(devinfo->gen >= 8);
598 return brw_inst_bits(insn, 127, 64);
599 }
600
601 static inline float
602 brw_inst_imm_f(const struct gen_device_info *devinfo, const brw_inst *insn)
603 {
604 union {
605 float f;
606 uint32_t u;
607 } ft;
608 (void) devinfo;
609 ft.u = brw_inst_bits(insn, 127, 96);
610 return ft.f;
611 }
612
613 static inline double
614 brw_inst_imm_df(const struct gen_device_info *devinfo, const brw_inst *insn)
615 {
616 union {
617 double d;
618 uint64_t u;
619 } dt;
620 (void) devinfo;
621 dt.u = brw_inst_bits(insn, 127, 64);
622 return dt.d;
623 }
624
625 static inline void
626 brw_inst_set_imm_d(const struct gen_device_info *devinfo,
627 brw_inst *insn, int value)
628 {
629 (void) devinfo;
630 return brw_inst_set_bits(insn, 127, 96, value);
631 }
632
633 static inline void
634 brw_inst_set_imm_ud(const struct gen_device_info *devinfo,
635 brw_inst *insn, unsigned value)
636 {
637 (void) devinfo;
638 return brw_inst_set_bits(insn, 127, 96, value);
639 }
640
641 static inline void
642 brw_inst_set_imm_f(const struct gen_device_info *devinfo,
643 brw_inst *insn, float value)
644 {
645 union {
646 float f;
647 uint32_t u;
648 } ft;
649 (void) devinfo;
650 ft.f = value;
651 brw_inst_set_bits(insn, 127, 96, ft.u);
652 }
653
654 static inline void
655 brw_inst_set_imm_df(const struct gen_device_info *devinfo,
656 brw_inst *insn, double value)
657 {
658 union {
659 double d;
660 uint64_t u;
661 } dt;
662 (void) devinfo;
663 dt.d = value;
664 brw_inst_set_bits(insn, 127, 64, dt.u);
665 }
666
667 static inline void
668 brw_inst_set_imm_uq(const struct gen_device_info *devinfo,
669 brw_inst *insn, uint64_t value)
670 {
671 (void) devinfo;
672 brw_inst_set_bits(insn, 127, 64, value);
673 }
674
675 /** @} */
676
677 #define REG_TYPE(reg) \
678 static inline void \
679 brw_inst_set_##reg##_file_type(const struct gen_device_info *devinfo, \
680 brw_inst *inst, enum brw_reg_file file, \
681 enum brw_reg_type type) \
682 { \
683 assert(file <= BRW_IMMEDIATE_VALUE); \
684 unsigned hw_type = brw_reg_type_to_hw_type(devinfo, file, type); \
685 brw_inst_set_##reg##_reg_file(devinfo, inst, file); \
686 brw_inst_set_##reg##_reg_hw_type(devinfo, inst, hw_type); \
687 } \
688 \
689 static inline enum brw_reg_type \
690 brw_inst_##reg##_type(const struct gen_device_info *devinfo, \
691 const brw_inst *inst) \
692 { \
693 unsigned file = __builtin_strcmp("dst", #reg) == 0 ? \
694 BRW_GENERAL_REGISTER_FILE : \
695 brw_inst_##reg##_reg_file(devinfo, inst); \
696 unsigned hw_type = brw_inst_##reg##_reg_hw_type(devinfo, inst); \
697 return brw_hw_type_to_reg_type(devinfo, (enum brw_reg_file)file, hw_type); \
698 }
699
700 REG_TYPE(dst)
701 REG_TYPE(src0)
702 REG_TYPE(src1)
703 #undef REG_TYPE
704
705
706 /* The AddrImm fields are split into two discontiguous sections on Gen8+ */
707 #define BRW_IA1_ADDR_IMM(reg, g4_high, g4_low, g8_nine, g8_high, g8_low) \
708 static inline void \
709 brw_inst_set_##reg##_ia1_addr_imm(const struct gen_device_info *devinfo, \
710 brw_inst *inst, \
711 unsigned value) \
712 { \
713 assert((value & ~0x3ff) == 0); \
714 if (devinfo->gen >= 8) { \
715 brw_inst_set_bits(inst, g8_high, g8_low, value & 0x1ff); \
716 brw_inst_set_bits(inst, g8_nine, g8_nine, value >> 9); \
717 } else { \
718 brw_inst_set_bits(inst, g4_high, g4_low, value); \
719 } \
720 } \
721 static inline unsigned \
722 brw_inst_##reg##_ia1_addr_imm(const struct gen_device_info *devinfo, \
723 const brw_inst *inst) \
724 { \
725 if (devinfo->gen >= 8) { \
726 return brw_inst_bits(inst, g8_high, g8_low) | \
727 (brw_inst_bits(inst, g8_nine, g8_nine) << 9); \
728 } else { \
729 return brw_inst_bits(inst, g4_high, g4_low); \
730 } \
731 }
732
733 /* AddrImm[9:0] for Align1 Indirect Addressing */
734 /* -Gen 4- ----Gen8---- */
735 BRW_IA1_ADDR_IMM(src1, 105, 96, 121, 104, 96)
736 BRW_IA1_ADDR_IMM(src0, 73, 64, 95, 72, 64)
737 BRW_IA1_ADDR_IMM(dst, 57, 48, 47, 56, 48)
738
739 #define BRW_IA16_ADDR_IMM(reg, g4_high, g4_low, g8_nine, g8_high, g8_low) \
740 static inline void \
741 brw_inst_set_##reg##_ia16_addr_imm(const struct gen_device_info *devinfo, \
742 brw_inst *inst, unsigned value) \
743 { \
744 assert((value & ~0x3ff) == 0); \
745 if (devinfo->gen >= 8) { \
746 brw_inst_set_bits(inst, g8_high, g8_low, value & 0x1ff); \
747 brw_inst_set_bits(inst, g8_nine, g8_nine, value >> 9); \
748 } else { \
749 brw_inst_set_bits(inst, g4_high, g4_low, value >> 9); \
750 } \
751 } \
752 static inline unsigned \
753 brw_inst_##reg##_ia16_addr_imm(const struct gen_device_info *devinfo, \
754 const brw_inst *inst) \
755 { \
756 if (devinfo->gen >= 8) { \
757 return brw_inst_bits(inst, g8_high, g8_low) | \
758 (brw_inst_bits(inst, g8_nine, g8_nine) << 9); \
759 } else { \
760 return brw_inst_bits(inst, g4_high, g4_low); \
761 } \
762 }
763
764 /* AddrImm[9:0] for Align16 Indirect Addressing:
765 * Compared to Align1, these are missing the low 4 bits.
766 * -Gen 4- ----Gen8----
767 */
768 BRW_IA16_ADDR_IMM(src1, 105, 96, 121, 104, 100)
769 BRW_IA16_ADDR_IMM(src0, 73, 64, 95, 72, 68)
770 BRW_IA16_ADDR_IMM(dst, 57, 52, 47, 56, 52)
771
772 /**
773 * Fetch a set of contiguous bits from the instruction.
774 *
775 * Bits indices range from 0..127; fields may not cross 64-bit boundaries.
776 */
777 static inline uint64_t
778 brw_inst_bits(const brw_inst *inst, unsigned high, unsigned low)
779 {
780 /* We assume the field doesn't cross 64-bit boundaries. */
781 const unsigned word = high / 64;
782 assert(word == low / 64);
783
784 high %= 64;
785 low %= 64;
786
787 const uint64_t mask = (~0ull >> (64 - (high - low + 1)));
788
789 return (inst->data[word] >> low) & mask;
790 }
791
792 /**
793 * Set bits in the instruction, with proper shifting and masking.
794 *
795 * Bits indices range from 0..127; fields may not cross 64-bit boundaries.
796 */
797 static inline void
798 brw_inst_set_bits(brw_inst *inst, unsigned high, unsigned low, uint64_t value)
799 {
800 const unsigned word = high / 64;
801 assert(word == low / 64);
802
803 high %= 64;
804 low %= 64;
805
806 const uint64_t mask = (~0ull >> (64 - (high - low + 1))) << low;
807
808 /* Make sure the supplied value actually fits in the given bitfield. */
809 assert((value & (mask >> low)) == value);
810
811 inst->data[word] = (inst->data[word] & ~mask) | (value << low);
812 }
813
814 #undef BRW_IA16_ADDR_IMM
815 #undef BRW_IA1_ADDR_IMM
816 #undef MD
817 #undef F8
818 #undef FF
819 #undef BOUNDS
820 #undef F
821 #undef FC
822
823 typedef struct {
824 uint64_t data;
825 } brw_compact_inst;
826
827 /**
828 * Fetch a set of contiguous bits from the compacted instruction.
829 *
830 * Bits indices range from 0..63.
831 */
832 static inline unsigned
833 brw_compact_inst_bits(const brw_compact_inst *inst, unsigned high, unsigned low)
834 {
835 const uint64_t mask = (1ull << (high - low + 1)) - 1;
836
837 return (inst->data >> low) & mask;
838 }
839
840 /**
841 * Set bits in the compacted instruction.
842 *
843 * Bits indices range from 0..63.
844 */
845 static inline void
846 brw_compact_inst_set_bits(brw_compact_inst *inst, unsigned high, unsigned low,
847 uint64_t value)
848 {
849 const uint64_t mask = ((1ull << (high - low + 1)) - 1) << low;
850
851 /* Make sure the supplied value actually fits in the given bitfield. */
852 assert((value & (mask >> low)) == value);
853
854 inst->data = (inst->data & ~mask) | (value << low);
855 }
856
857 #define FC(name, high, low, assertions) \
858 static inline void \
859 brw_compact_inst_set_##name(const struct gen_device_info *devinfo, \
860 brw_compact_inst *inst, unsigned v) \
861 { \
862 assert(assertions); \
863 (void) devinfo; \
864 brw_compact_inst_set_bits(inst, high, low, v); \
865 } \
866 static inline unsigned \
867 brw_compact_inst_##name(const struct gen_device_info *devinfo, \
868 const brw_compact_inst *inst) \
869 { \
870 assert(assertions); \
871 (void) devinfo; \
872 return brw_compact_inst_bits(inst, high, low); \
873 }
874
875 /* A simple macro for fields which stay in the same place on all generations. */
876 #define F(name, high, low) FC(name, high, low, true)
877
878 F(src1_reg_nr, 63, 56)
879 F(src0_reg_nr, 55, 48)
880 F(dst_reg_nr, 47, 40)
881 F(src1_index, 39, 35)
882 F(src0_index, 34, 30)
883 F(cmpt_control, 29, 29) /* Same location as brw_inst */
884 FC(flag_subreg_nr, 28, 28, devinfo->gen <= 6)
885 F(cond_modifier, 27, 24) /* Same location as brw_inst */
886 FC(acc_wr_control, 23, 23, devinfo->gen >= 6)
887 FC(mask_control_ex, 23, 23, devinfo->is_g4x || devinfo->gen == 5)
888 F(subreg_index, 22, 18)
889 F(datatype_index, 17, 13)
890 F(control_index, 12, 8)
891 F(debug_control, 7, 7)
892 F(opcode, 6, 0) /* Same location as brw_inst */
893
894 /**
895 * (Gen8+) Compacted three-source instructions:
896 * @{
897 */
898 FC(3src_src2_reg_nr, 63, 57, devinfo->gen >= 8)
899 FC(3src_src1_reg_nr, 56, 50, devinfo->gen >= 8)
900 FC(3src_src0_reg_nr, 49, 43, devinfo->gen >= 8)
901 FC(3src_src2_subreg_nr, 42, 40, devinfo->gen >= 8)
902 FC(3src_src1_subreg_nr, 39, 37, devinfo->gen >= 8)
903 FC(3src_src0_subreg_nr, 36, 34, devinfo->gen >= 8)
904 FC(3src_src2_rep_ctrl, 33, 33, devinfo->gen >= 8)
905 FC(3src_src1_rep_ctrl, 32, 32, devinfo->gen >= 8)
906 FC(3src_saturate, 31, 31, devinfo->gen >= 8)
907 FC(3src_debug_control, 30, 30, devinfo->gen >= 8)
908 FC(3src_cmpt_control, 29, 29, devinfo->gen >= 8)
909 FC(3src_src0_rep_ctrl, 28, 28, devinfo->gen >= 8)
910 /* Reserved */
911 FC(3src_dst_reg_nr, 18, 12, devinfo->gen >= 8)
912 FC(3src_source_index, 11, 10, devinfo->gen >= 8)
913 FC(3src_control_index, 9, 8, devinfo->gen >= 8)
914 /* Bit 7 is Reserved (for future Opcode expansion) */
915 FC(3src_opcode, 6, 0, devinfo->gen >= 8)
916 /** @} */
917
918 #undef F
919
920 #ifdef __cplusplus
921 }
922 #endif
923
924 #endif