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[mesa.git] / src / intel / compiler / brw_inst.h
1 /*
2 * Copyright © 2014 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 */
23
24 /**
25 * @file brw_inst.h
26 *
27 * A representation of i965 EU assembly instructions, with helper methods to
28 * get and set various fields. This is the actual hardware format.
29 */
30
31 #ifndef BRW_INST_H
32 #define BRW_INST_H
33
34 #include <assert.h>
35 #include <stdint.h>
36
37 #include "brw_eu_defines.h"
38 #include "brw_reg_type.h"
39 #include "dev/gen_device_info.h"
40
41 #ifdef __cplusplus
42 extern "C" {
43 #endif
44
45 /* brw_context.h has a forward declaration of brw_inst, so name the struct. */
46 typedef struct brw_inst {
47 uint64_t data[2];
48 } brw_inst;
49
50 static inline uint64_t brw_inst_bits(const brw_inst *inst,
51 unsigned high, unsigned low);
52 static inline void brw_inst_set_bits(brw_inst *inst,
53 unsigned high, unsigned low,
54 uint64_t value);
55
56 #define FC(name, hi4, lo4, hi12, lo12, assertions) \
57 static inline void \
58 brw_inst_set_##name(const struct gen_device_info *devinfo, \
59 brw_inst *inst, uint64_t v) \
60 { \
61 assert(assertions); \
62 if (devinfo->gen >= 12) \
63 brw_inst_set_bits(inst, hi12, lo12, v); \
64 else \
65 brw_inst_set_bits(inst, hi4, lo4, v); \
66 } \
67 static inline uint64_t \
68 brw_inst_##name(const struct gen_device_info *devinfo, \
69 const brw_inst *inst) \
70 { \
71 assert(assertions); \
72 if (devinfo->gen >= 12) \
73 return brw_inst_bits(inst, hi12, lo12); \
74 else \
75 return brw_inst_bits(inst, hi4, lo4); \
76 }
77
78 /* A simple macro for fields which stay in the same place on all generations,
79 * except for Gen12!
80 */
81 #define F(name, hi4, lo4, hi12, lo12) FC(name, hi4, lo4, hi12, lo12, true)
82
83 #define BOUNDS(hi4, lo4, hi45, lo45, hi5, lo5, hi6, lo6, \
84 hi7, lo7, hi8, lo8, hi12, lo12) \
85 unsigned high, low; \
86 if (devinfo->gen >= 12) { \
87 high = hi12; low = lo12; \
88 } else if (devinfo->gen >= 8) { \
89 high = hi8; low = lo8; \
90 } else if (devinfo->gen >= 7) { \
91 high = hi7; low = lo7; \
92 } else if (devinfo->gen >= 6) { \
93 high = hi6; low = lo6; \
94 } else if (devinfo->gen >= 5) { \
95 high = hi5; low = lo5; \
96 } else if (devinfo->is_g4x) { \
97 high = hi45; low = lo45; \
98 } else { \
99 high = hi4; low = lo4; \
100 } \
101 assert(((int) high) != -1 && ((int) low) != -1);
102
103 /* A general macro for cases where the field has moved to several different
104 * bit locations across generations. GCC appears to combine cases where the
105 * bits are identical, removing some of the inefficiency.
106 */
107 #define FF(name, hi4, lo4, hi45, lo45, hi5, lo5, hi6, lo6, \
108 hi7, lo7, hi8, lo8, hi12, lo12) \
109 static inline void \
110 brw_inst_set_##name(const struct gen_device_info *devinfo, \
111 brw_inst *inst, uint64_t value) \
112 { \
113 BOUNDS(hi4, lo4, hi45, lo45, hi5, lo5, hi6, lo6, \
114 hi7, lo7, hi8, lo8, hi12, lo12) \
115 brw_inst_set_bits(inst, high, low, value); \
116 } \
117 static inline uint64_t \
118 brw_inst_##name(const struct gen_device_info *devinfo, const brw_inst *inst) \
119 { \
120 BOUNDS(hi4, lo4, hi45, lo45, hi5, lo5, hi6, lo6, \
121 hi7, lo7, hi8, lo8, hi12, lo12) \
122 return brw_inst_bits(inst, high, low); \
123 }
124
125 /* A macro for fields which moved as of Gen8+. */
126 #define F8(name, gen4_high, gen4_low, gen8_high, gen8_low, \
127 gen12_high, gen12_low) \
128 FF(name, \
129 /* 4: */ gen4_high, gen4_low, \
130 /* 4.5: */ gen4_high, gen4_low, \
131 /* 5: */ gen4_high, gen4_low, \
132 /* 6: */ gen4_high, gen4_low, \
133 /* 7: */ gen4_high, gen4_low, \
134 /* 8: */ gen8_high, gen8_low, \
135 /* 12: */ gen12_high, gen12_low);
136
137 /* Macro for fields that gained extra discontiguous MSBs in Gen12 (specified
138 * by hi12ex-lo12ex).
139 */
140 #define FFDC(name, hi4, lo4, hi45, lo45, hi5, lo5, hi6, lo6, \
141 hi7, lo7, hi8, lo8, hi12ex, lo12ex, hi12, lo12, assertions) \
142 static inline void \
143 brw_inst_set_##name(const struct gen_device_info *devinfo, \
144 brw_inst *inst, uint64_t value) \
145 { \
146 assert(assertions); \
147 if (devinfo->gen >= 12) { \
148 const unsigned k = hi12 - lo12 + 1; \
149 if (hi12ex != -1 && lo12ex != -1) \
150 brw_inst_set_bits(inst, hi12ex, lo12ex, value >> k); \
151 brw_inst_set_bits(inst, hi12, lo12, value & ((1ull << k) - 1)); \
152 } else { \
153 BOUNDS(hi4, lo4, hi45, lo45, hi5, lo5, hi6, lo6, \
154 hi7, lo7, hi8, lo8, -1, -1); \
155 brw_inst_set_bits(inst, high, low, value); \
156 } \
157 } \
158 static inline uint64_t \
159 brw_inst_##name(const struct gen_device_info *devinfo, const brw_inst *inst) \
160 { \
161 assert(assertions); \
162 if (devinfo->gen >= 12) { \
163 const unsigned k = hi12 - lo12 + 1; \
164 return (hi12ex == -1 || lo12ex == -1 ? 0 : \
165 brw_inst_bits(inst, hi12ex, lo12ex) << k) | \
166 brw_inst_bits(inst, hi12, lo12); \
167 } else { \
168 BOUNDS(hi4, lo4, hi45, lo45, hi5, lo5, hi6, lo6, \
169 hi7, lo7, hi8, lo8, -1, -1); \
170 return brw_inst_bits(inst, high, low); \
171 } \
172 }
173
174 #define FD(name, hi4, lo4, hi45, lo45, hi5, lo5, hi6, lo6, \
175 hi7, lo7, hi8, lo8, hi12ex, lo12ex, hi12, lo12) \
176 FFDC(name, hi4, lo4, hi45, lo45, hi5, lo5, hi6, lo6, \
177 hi7, lo7, hi8, lo8, hi12ex, lo12ex, hi12, lo12, true)
178
179 /* Macro for fields that didn't move across generations until Gen12, and then
180 * gained extra discontiguous bits.
181 */
182 #define FDC(name, hi4, lo4, hi12ex, lo12ex, hi12, lo12, assertions) \
183 FFDC(name, hi4, lo4, hi4, lo4, hi4, lo4, hi4, lo4, \
184 hi4, lo4, hi4, lo4, hi12ex, lo12ex, hi12, lo12, assertions)
185
186
187 /* Macro for the 2-bit register file field, which on Gen12+ is stored as the
188 * variable length combination of an IsImm (hi12) bit and an additional file
189 * (lo12) bit.
190 */
191 #define FI(name, hi4, lo4, hi8, lo8, hi12, lo12) \
192 static inline void \
193 brw_inst_set_##name(const struct gen_device_info *devinfo, \
194 brw_inst *inst, uint64_t value) \
195 { \
196 if (devinfo->gen >= 12) { \
197 brw_inst_set_bits(inst, hi12, hi12, value >> 1); \
198 if ((value >> 1) == 0) \
199 brw_inst_set_bits(inst, lo12, lo12, value & 1); \
200 } else { \
201 BOUNDS(hi4, lo4, hi4, lo4, hi4, lo4, hi4, lo4, \
202 hi4, lo4, hi8, lo8, -1, -1); \
203 brw_inst_set_bits(inst, high, low, value); \
204 } \
205 } \
206 static inline uint64_t \
207 brw_inst_##name(const struct gen_device_info *devinfo, const brw_inst *inst) \
208 { \
209 if (devinfo->gen >= 12) { \
210 return (brw_inst_bits(inst, hi12, hi12) << 1) | \
211 (brw_inst_bits(inst, hi12, hi12) == 0 ? \
212 brw_inst_bits(inst, lo12, lo12) : 1); \
213 } else { \
214 BOUNDS(hi4, lo4, hi4, lo4, hi4, lo4, hi4, lo4, \
215 hi4, lo4, hi8, lo8, -1, -1); \
216 return brw_inst_bits(inst, high, low); \
217 } \
218 }
219
220 /* Macro for fields that become a constant in Gen12+ not actually represented
221 * in the instruction.
222 */
223 #define FK(name, hi4, lo4, const12) \
224 static inline void \
225 brw_inst_set_##name(const struct gen_device_info *devinfo, \
226 brw_inst *inst, uint64_t v) \
227 { \
228 if (devinfo->gen >= 12) \
229 assert(v == (const12)); \
230 else \
231 brw_inst_set_bits(inst, hi4, lo4, v); \
232 } \
233 static inline uint64_t \
234 brw_inst_##name(const struct gen_device_info *devinfo, \
235 const brw_inst *inst) \
236 { \
237 if (devinfo->gen >= 12) \
238 return (const12); \
239 else \
240 return brw_inst_bits(inst, hi4, lo4); \
241 }
242
243 F(src1_vstride, /* 4+ */ 120, 117, /* 12+ */ 119, 116)
244 F(src1_width, /* 4+ */ 116, 114, /* 12+ */ 115, 113)
245 F(src1_da16_swiz_w, /* 4+ */ 115, 114, /* 12+ */ -1, -1)
246 F(src1_da16_swiz_z, /* 4+ */ 113, 112, /* 12+ */ -1, -1)
247 F(src1_hstride, /* 4+ */ 113, 112, /* 12+ */ 97, 96)
248 F(src1_address_mode, /* 4+ */ 111, 111, /* 12+ */ 112, 112)
249 /** Src1.SrcMod @{ */
250 F(src1_negate, /* 4+ */ 110, 110, /* 12+ */ 121, 121)
251 F(src1_abs, /* 4+ */ 109, 109, /* 12+ */ 120, 120)
252 /** @} */
253 F8(src1_ia_subreg_nr, /* 4+ */ 108, 106, /* 8+ */ 108, 105, /* 12+ */ 111, 108)
254 F(src1_da_reg_nr, /* 4+ */ 108, 101, /* 12+ */ 111, 104)
255 F(src1_da16_subreg_nr, /* 4+ */ 100, 100, /* 12+ */ -1, -1)
256 F(src1_da1_subreg_nr, /* 4+ */ 100, 96, /* 12+ */ 103, 99)
257 F(src1_da16_swiz_y, /* 4+ */ 99, 98, /* 12+ */ -1, -1)
258 F(src1_da16_swiz_x, /* 4+ */ 97, 96, /* 12+ */ -1, -1)
259 F8(src1_reg_hw_type, /* 4+ */ 46, 44, /* 8+ */ 94, 91, /* 12+ */ 91, 88)
260 FI(src1_reg_file, /* 4+ */ 43, 42, /* 8+ */ 90, 89, /* 12+ */ 47, 98)
261 F(src1_is_imm, /* 4+ */ -1, -1, /* 12+ */ 47, 47)
262 F(src0_vstride, /* 4+ */ 88, 85, /* 12+ */ 87, 84)
263 F(src0_width, /* 4+ */ 84, 82, /* 12+ */ 83, 81)
264 F(src0_da16_swiz_w, /* 4+ */ 83, 82, /* 12+ */ -1, -1)
265 F(src0_da16_swiz_z, /* 4+ */ 81, 80, /* 12+ */ -1, -1)
266 F(src0_hstride, /* 4+ */ 81, 80, /* 12+ */ 65, 64)
267 F(src0_address_mode, /* 4+ */ 79, 79, /* 12+ */ 80, 80)
268 /** Src0.SrcMod @{ */
269 F(src0_negate, /* 4+ */ 78, 78, /* 12+ */ 45, 45)
270 F(src0_abs, /* 4+ */ 77, 77, /* 12+ */ 44, 44)
271 /** @} */
272 F8(src0_ia_subreg_nr, /* 4+ */ 76, 74, /* 8+ */ 76, 73, /* 12+ */ 79, 76)
273 F(src0_da_reg_nr, /* 4+ */ 76, 69, /* 12+ */ 79, 72)
274 F(src0_da16_subreg_nr, /* 4+ */ 68, 68, /* 12+ */ -1, -1)
275 F(src0_da1_subreg_nr, /* 4+ */ 68, 64, /* 12+ */ 71, 67)
276 F(src0_da16_swiz_y, /* 4+ */ 67, 66, /* 12+ */ -1, -1)
277 F(src0_da16_swiz_x, /* 4+ */ 65, 64, /* 12+ */ -1, -1)
278 F(dst_address_mode, /* 4+ */ 63, 63, /* 12+ */ 35, 35)
279 F(dst_hstride, /* 4+ */ 62, 61, /* 12+ */ 49, 48)
280 F8(dst_ia_subreg_nr, /* 4+ */ 60, 58, /* 8+ */ 60, 57, /* 12+ */ 63, 60)
281 F(dst_da_reg_nr, /* 4+ */ 60, 53, /* 12+ */ 63, 56)
282 F(dst_da16_subreg_nr, /* 4+ */ 52, 52, /* 12+ */ -1, -1)
283 F(dst_da1_subreg_nr, /* 4+ */ 52, 48, /* 12+ */ 55, 51)
284 F(da16_writemask, /* 4+ */ 51, 48, /* 12+ */ -1, -1) /* Dst.ChanEn */
285 F8(src0_reg_hw_type, /* 4+ */ 41, 39, /* 8+ */ 46, 43, /* 12+ */ 43, 40)
286 FI(src0_reg_file, /* 4+ */ 38, 37, /* 8+ */ 42, 41, /* 12+ */ 46, 66)
287 F(src0_is_imm, /* 4+ */ -1, -1, /* 12+ */ 46, 46)
288 F8(dst_reg_hw_type, /* 4+ */ 36, 34, /* 8+ */ 40, 37, /* 12+ */ 39, 36)
289 F8(dst_reg_file, /* 4+ */ 33, 32, /* 8+ */ 36, 35, /* 12+ */ 50, 50)
290 F8(mask_control, /* 4+ */ 9, 9, /* 8+ */ 34, 34, /* 12+ */ 31, 31)
291 FF(flag_reg_nr,
292 /* 4-6: doesn't exist */ -1, -1, -1, -1, -1, -1, -1, -1,
293 /* 7: */ 90, 90,
294 /* 8: */ 33, 33,
295 /* 12: */ 23, 23)
296 F8(flag_subreg_nr, /* 4+ */ 89, 89, /* 8+ */ 32, 32, /* 12+ */ 22, 22)
297 F(saturate, /* 4+ */ 31, 31, /* 12+ */ 34, 34)
298 F(debug_control, /* 4+ */ 30, 30, /* 12+ */ 30, 30)
299 F(cmpt_control, /* 4+ */ 29, 29, /* 12+ */ 29, 29)
300 FC(branch_control, /* 4+ */ 28, 28, /* 12+ */ 33, 33, devinfo->gen >= 8)
301 FC(acc_wr_control, /* 4+ */ 28, 28, /* 12+ */ 33, 33, devinfo->gen >= 6)
302 FC(mask_control_ex, /* 4+ */ 28, 28, /* 12+ */ -1, -1, devinfo->is_g4x || devinfo->gen == 5)
303 F(cond_modifier, /* 4+ */ 27, 24, /* 12+ */ 95, 92)
304 FC(math_function, /* 4+ */ 27, 24, /* 12+ */ 95, 92, devinfo->gen >= 6)
305 F(exec_size, /* 4+ */ 23, 21, /* 12+ */ 18, 16)
306 F(pred_inv, /* 4+ */ 20, 20, /* 12+ */ 28, 28)
307 F(pred_control, /* 4+ */ 19, 16, /* 12+ */ 27, 24)
308 F(thread_control, /* 4+ */ 15, 14, /* 12+ */ -1, -1)
309 F(atomic_control, /* 4+ */ -1, -1, /* 12+ */ 32, 32)
310 F(qtr_control, /* 4+ */ 13, 12, /* 12+ */ 21, 20)
311 FF(nib_control,
312 /* 4-6: doesn't exist */ -1, -1, -1, -1, -1, -1, -1, -1,
313 /* 7: */ 47, 47,
314 /* 8: */ 11, 11,
315 /* 12: */ 19, 19)
316 F8(no_dd_check, /* 4+ */ 11, 11, /* 8+ */ 10, 10, /* 12+ */ -1, -1)
317 F8(no_dd_clear, /* 4+ */ 10, 10, /* 8+ */ 9, 9, /* 12+ */ -1, -1)
318 F(swsb, /* 4+ */ -1, -1, /* 12+ */ 15, 8)
319 FK(access_mode, /* 4+ */ 8, 8, /* 12+ */ BRW_ALIGN_1)
320 /* Bit 7 is Reserved (for future Opcode expansion) */
321 F(hw_opcode, /* 4+ */ 6, 0, /* 12+ */ 6, 0)
322
323 /**
324 * Three-source instructions:
325 * @{
326 */
327 F(3src_src2_reg_nr, /* 4+ */ 125, 118, /* 12+ */ -1, -1) /* same in align1 */
328 F(3src_a16_src2_subreg_nr, /* 4+ */ 117, 115, /* 12+ */ -1, -1) /* Extra discontiguous bit on CHV? */
329 F(3src_a16_src2_swizzle, /* 4+ */ 114, 107, /* 12+ */ -1, -1)
330 F(3src_a16_src2_rep_ctrl, /* 4+ */ 106, 106, /* 12+ */ -1, -1)
331 F(3src_src1_reg_nr, /* 4+ */ 104, 97, /* 12+ */ -1, -1) /* same in align1 */
332 F(3src_a16_src1_subreg_nr, /* 4+ */ 96, 94, /* 12+ */ -1, -1) /* Extra discontiguous bit on CHV? */
333 F(3src_a16_src1_swizzle, /* 4+ */ 93, 86, /* 12+ */ -1, -1)
334 F(3src_a16_src1_rep_ctrl, /* 4+ */ 85, 85, /* 12+ */ -1, -1)
335 F(3src_src0_reg_nr, /* 4+ */ 83, 76, /* 12+ */ -1, -1) /* same in align1 */
336 F(3src_a16_src0_subreg_nr, /* 4+ */ 75, 73, /* 12+ */ -1, -1) /* Extra discontiguous bit on CHV? */
337 F(3src_a16_src0_swizzle, /* 4+ */ 72, 65, /* 12+ */ -1, -1)
338 F(3src_a16_src0_rep_ctrl, /* 4+ */ 64, 64, /* 12+ */ -1, -1)
339 F(3src_dst_reg_nr, /* 4+ */ 63, 56, /* 12+ */ -1, -1) /* same in align1 */
340 F(3src_a16_dst_subreg_nr, /* 4+ */ 55, 53, /* 12+ */ -1, -1)
341 F(3src_a16_dst_writemask, /* 4+ */ 52, 49, /* 12+ */ -1, -1)
342 F8(3src_a16_nib_ctrl, /* 4+ */ 47, 47, /* 8+ */ 11, 11, /* 12+ */ -1, -1) /* only exists on IVB+ */
343 F8(3src_a16_dst_hw_type, /* 4+ */ 45, 44, /* 8+ */ 48, 46, /* 12+ */ -1, -1) /* only exists on IVB+ */
344 F8(3src_a16_src_hw_type, /* 4+ */ 43, 42, /* 8+ */ 45, 43, /* 12+ */ -1, -1)
345 F8(3src_src2_negate, /* 4+ */ 41, 41, /* 8+ */ 42, 42, /* 12+ */ -1, -1)
346 F8(3src_src2_abs, /* 4+ */ 40, 40, /* 8+ */ 41, 41, /* 12+ */ -1, -1)
347 F8(3src_src1_negate, /* 4+ */ 39, 39, /* 8+ */ 40, 40, /* 12+ */ -1, -1)
348 F8(3src_src1_abs, /* 4+ */ 38, 38, /* 8+ */ 39, 39, /* 12+ */ -1, -1)
349 F8(3src_src0_negate, /* 4+ */ 37, 37, /* 8+ */ 38, 38, /* 12+ */ -1, -1)
350 F8(3src_src0_abs, /* 4+ */ 36, 36, /* 8+ */ 37, 37, /* 12+ */ -1, -1)
351 F8(3src_a16_src1_type, /* 4+ */ -1, -1, /* 8+ */ 36, 36, /* 12+ */ -1, -1)
352 F8(3src_a16_src2_type, /* 4+ */ -1, -1, /* 8+ */ 35, 35, /* 12+ */ -1, -1)
353 F8(3src_a16_flag_reg_nr, /* 4+ */ 34, 34, /* 8+ */ 33, 33, /* 12+ */ -1, -1)
354 F8(3src_a16_flag_subreg_nr,/* 4+ */ 33, 33, /* 8+ */ 32, 32, /* 12+ */ -1, -1)
355 FF(3src_a16_dst_reg_file,
356 /* 4-5: doesn't exist - no 3-source instructions */ -1, -1, -1, -1, -1, -1,
357 /* 6: */ 32, 32,
358 /* 7-8: doesn't exist - no MRFs */ -1, -1, -1, -1,
359 /* 12: */ -1, -1)
360 F(3src_saturate, /* 4+ */ 31, 31, /* 12+ */ -1, -1)
361 F(3src_debug_control, /* 4+ */ 30, 30, /* 12+ */ -1, -1)
362 F(3src_cmpt_control, /* 4+ */ 29, 29, /* 12+ */ -1, -1)
363 F(3src_acc_wr_control, /* 4+ */ 28, 28, /* 12+ */ -1, -1)
364 F(3src_cond_modifier, /* 4+ */ 27, 24, /* 12+ */ -1, -1)
365 F(3src_exec_size, /* 4+ */ 23, 21, /* 12+ */ -1, -1)
366 F(3src_pred_inv, /* 4+ */ 20, 20, /* 12+ */ -1, -1)
367 F(3src_pred_control, /* 4+ */ 19, 16, /* 12+ */ -1, -1)
368 F(3src_thread_control, /* 4+ */ 15, 14, /* 12+ */ -1, -1)
369 F(3src_qtr_control, /* 4+ */ 13, 12, /* 12+ */ -1, -1)
370 F8(3src_no_dd_check, /* 4+ */ 11, 11, /* 8+ */ 10, 10, /* 12+ */ -1, -1)
371 F8(3src_no_dd_clear, /* 4+ */ 10, 10, /* 8+ */ 9, 9, /* 12+ */ -1, -1)
372 F8(3src_mask_control, /* 4+ */ 9, 9, /* 8+ */ 34, 34, /* 12+ */ -1, -1)
373 F(3src_access_mode, /* 4+ */ 8, 8, /* 12+ */ -1, -1)
374 /* Bit 7 is Reserved (for future Opcode expansion) */
375 F(3src_hw_opcode, /* 4+ */ 6, 0, /* 12+ */ -1, -1)
376 /** @} */
377
378 #define REG_TYPE(reg) \
379 static inline void \
380 brw_inst_set_3src_a16_##reg##_type(const struct gen_device_info *devinfo, \
381 brw_inst *inst, enum brw_reg_type type) \
382 { \
383 unsigned hw_type = brw_reg_type_to_a16_hw_3src_type(devinfo, type); \
384 brw_inst_set_3src_a16_##reg##_hw_type(devinfo, inst, hw_type); \
385 } \
386 \
387 static inline enum brw_reg_type \
388 brw_inst_3src_a16_##reg##_type(const struct gen_device_info *devinfo, \
389 const brw_inst *inst) \
390 { \
391 unsigned hw_type = brw_inst_3src_a16_##reg##_hw_type(devinfo, inst); \
392 return brw_a16_hw_3src_type_to_reg_type(devinfo, hw_type); \
393 }
394
395 REG_TYPE(dst)
396 REG_TYPE(src)
397 #undef REG_TYPE
398
399 /**
400 * Three-source align1 instructions:
401 * @{
402 */
403 /* Reserved 127:126 */
404 /* src2_reg_nr same in align16 */
405 FC(3src_a1_src2_subreg_nr, /* 4+ */ 117, 113, /* 12+ */ -1, -1, devinfo->gen >= 10)
406 FC(3src_a1_src2_hstride, /* 4+ */ 112, 111, /* 12+ */ -1, -1, devinfo->gen >= 10)
407 /* Reserved 110:109. src2 vstride is an implied parameter */
408 FC(3src_a1_src2_hw_type, /* 4+ */ 108, 106, /* 12+ */ -1, -1, devinfo->gen >= 10)
409 /* Reserved 105 */
410 /* src1_reg_nr same in align16 */
411 FC(3src_a1_src1_subreg_nr, /* 4+ */ 96, 92, /* 12+ */ -1, -1, devinfo->gen >= 10)
412 FC(3src_a1_src1_hstride, /* 4+ */ 91, 90, /* 12+ */ -1, -1, devinfo->gen >= 10)
413 FC(3src_a1_src1_vstride, /* 4+ */ 89, 88, /* 12+ */ -1, -1, devinfo->gen >= 10)
414 FC(3src_a1_src1_hw_type, /* 4+ */ 87, 85, /* 12+ */ -1, -1, devinfo->gen >= 10)
415 /* Reserved 84 */
416 /* src0_reg_nr same in align16 */
417 FC(3src_a1_src0_subreg_nr, /* 4+ */ 75, 71, /* 12+ */ -1, -1, devinfo->gen >= 10)
418 FC(3src_a1_src0_hstride, /* 4+ */ 70, 69, /* 12+ */ -1, -1, devinfo->gen >= 10)
419 FC(3src_a1_src0_vstride, /* 4+ */ 68, 67, /* 12+ */ -1, -1, devinfo->gen >= 10)
420 FC(3src_a1_src0_hw_type, /* 4+ */ 66, 64, /* 12+ */ -1, -1, devinfo->gen >= 10)
421 /* dst_reg_nr same in align16 */
422 FC(3src_a1_dst_subreg_nr, /* 4+ */ 55, 54, /* 12+ */ -1, -1, devinfo->gen >= 10)
423 FC(3src_a1_special_acc, /* 4+ */ 55, 52, /* 12+ */ -1, -1, devinfo->gen >= 10) /* aliases dst_subreg_nr */
424 /* Reserved 51:50 */
425 FC(3src_a1_dst_hstride, /* 4+ */ 49, 49, /* 12+ */ -1, -1, devinfo->gen >= 10)
426 FC(3src_a1_dst_hw_type, /* 4+ */ 48, 46, /* 12+ */ -1, -1, devinfo->gen >= 10)
427 FC(3src_a1_src2_reg_file, /* 4+ */ 45, 45, /* 12+ */ -1, -1, devinfo->gen >= 10)
428 FC(3src_a1_src1_reg_file, /* 4+ */ 44, 44, /* 12+ */ -1, -1, devinfo->gen >= 10)
429 FC(3src_a1_src0_reg_file, /* 4+ */ 43, 43, /* 12+ */ -1, -1, devinfo->gen >= 10)
430 /* Source Modifier fields same in align16 */
431 FC(3src_a1_dst_reg_file, /* 4+ */ 36, 36, /* 12+ */ -1, -1, devinfo->gen >= 10)
432 FC(3src_a1_exec_type, /* 4+ */ 35, 35, /* 12+ */ -1, -1, devinfo->gen >= 10)
433 /* Fields below this same in align16 */
434 /** @} */
435
436 #define REG_TYPE(reg) \
437 static inline void \
438 brw_inst_set_3src_a1_##reg##_type(const struct gen_device_info *devinfo, \
439 brw_inst *inst, enum brw_reg_type type) \
440 { \
441 UNUSED enum gen10_align1_3src_exec_type exec_type = \
442 (enum gen10_align1_3src_exec_type) brw_inst_3src_a1_exec_type(devinfo, \
443 inst); \
444 if (brw_reg_type_is_floating_point(type)) { \
445 assert(exec_type == BRW_ALIGN1_3SRC_EXEC_TYPE_FLOAT); \
446 } else { \
447 assert(exec_type == BRW_ALIGN1_3SRC_EXEC_TYPE_INT); \
448 } \
449 unsigned hw_type = brw_reg_type_to_a1_hw_3src_type(devinfo, type); \
450 brw_inst_set_3src_a1_##reg##_hw_type(devinfo, inst, hw_type); \
451 } \
452 \
453 static inline enum brw_reg_type \
454 brw_inst_3src_a1_##reg##_type(const struct gen_device_info *devinfo, \
455 const brw_inst *inst) \
456 { \
457 enum gen10_align1_3src_exec_type exec_type = \
458 (enum gen10_align1_3src_exec_type) brw_inst_3src_a1_exec_type(devinfo, \
459 inst); \
460 unsigned hw_type = brw_inst_3src_a1_##reg##_hw_type(devinfo, inst); \
461 return brw_a1_hw_3src_type_to_reg_type(devinfo, hw_type, exec_type); \
462 }
463
464 REG_TYPE(dst)
465 REG_TYPE(src0)
466 REG_TYPE(src1)
467 REG_TYPE(src2)
468 #undef REG_TYPE
469
470 /**
471 * Three-source align1 instruction immediates:
472 * @{
473 */
474 static inline uint16_t
475 brw_inst_3src_a1_src0_imm(ASSERTED const struct gen_device_info *devinfo,
476 const brw_inst *insn)
477 {
478 assert(devinfo->gen >= 10);
479 return brw_inst_bits(insn, 82, 67);
480 }
481
482 static inline uint16_t
483 brw_inst_3src_a1_src2_imm(ASSERTED const struct gen_device_info *devinfo,
484 const brw_inst *insn)
485 {
486 assert(devinfo->gen >= 10);
487 return brw_inst_bits(insn, 124, 109);
488 }
489
490 static inline void
491 brw_inst_set_3src_a1_src0_imm(ASSERTED const struct gen_device_info *devinfo,
492 brw_inst *insn, uint16_t value)
493 {
494 assert(devinfo->gen >= 10);
495 brw_inst_set_bits(insn, 82, 67, value);
496 }
497
498 static inline void
499 brw_inst_set_3src_a1_src2_imm(ASSERTED const struct gen_device_info *devinfo,
500 brw_inst *insn, uint16_t value)
501 {
502 assert(devinfo->gen >= 10);
503 brw_inst_set_bits(insn, 124, 109, value);
504 }
505 /** @} */
506
507 /**
508 * Flow control instruction bits:
509 * @{
510 */
511 static inline void
512 brw_inst_set_uip(const struct gen_device_info *devinfo,
513 brw_inst *inst, int32_t value)
514 {
515 assert(devinfo->gen >= 6);
516
517 if (devinfo->gen >= 8) {
518 brw_inst_set_bits(inst, 95, 64, (uint32_t)value);
519 } else {
520 assert(value <= (1 << 16) - 1);
521 assert(value > -(1 << 16));
522 brw_inst_set_bits(inst, 127, 112, (uint16_t)value);
523 }
524 }
525
526 static inline int32_t
527 brw_inst_uip(const struct gen_device_info *devinfo, const brw_inst *inst)
528 {
529 assert(devinfo->gen >= 6);
530
531 if (devinfo->gen >= 8) {
532 return brw_inst_bits(inst, 95, 64);
533 } else {
534 return (int16_t)brw_inst_bits(inst, 127, 112);
535 }
536 }
537
538 static inline void
539 brw_inst_set_jip(const struct gen_device_info *devinfo,
540 brw_inst *inst, int32_t value)
541 {
542 assert(devinfo->gen >= 6);
543
544 if (devinfo->gen >= 8) {
545 brw_inst_set_bits(inst, 127, 96, (uint32_t)value);
546 } else {
547 assert(value <= (1 << 15) - 1);
548 assert(value >= -(1 << 15));
549 brw_inst_set_bits(inst, 111, 96, (uint16_t)value);
550 }
551 }
552
553 static inline int32_t
554 brw_inst_jip(const struct gen_device_info *devinfo, const brw_inst *inst)
555 {
556 assert(devinfo->gen >= 6);
557
558 if (devinfo->gen >= 8) {
559 return brw_inst_bits(inst, 127, 96);
560 } else {
561 return (int16_t)brw_inst_bits(inst, 111, 96);
562 }
563 }
564
565 /** Like FC, but using int16_t to handle negative jump targets. */
566 #define FJ(name, high, low, assertions) \
567 static inline void \
568 brw_inst_set_##name(const struct gen_device_info *devinfo, brw_inst *inst, int16_t v) \
569 { \
570 assert(assertions); \
571 (void) devinfo; \
572 brw_inst_set_bits(inst, high, low, (uint16_t) v); \
573 } \
574 static inline int16_t \
575 brw_inst_##name(const struct gen_device_info *devinfo, const brw_inst *inst) \
576 { \
577 assert(assertions); \
578 (void) devinfo; \
579 return brw_inst_bits(inst, high, low); \
580 }
581
582 FJ(gen6_jump_count, 63, 48, devinfo->gen == 6)
583 FJ(gen4_jump_count, 111, 96, devinfo->gen < 6)
584 FC(gen4_pop_count, /* 4+ */ 115, 112, /* 12+ */ -1, -1, devinfo->gen < 6)
585 /** @} */
586
587 /**
588 * SEND instructions:
589 * @{
590 */
591 FC(send_ex_desc_ia_subreg_nr, /* 4+ */ 82, 80, /* 12+ */ -1, -1, devinfo->gen >= 9)
592 FC(send_src0_address_mode, /* 4+ */ 79, 79, /* 12+ */ -1, -1, devinfo->gen >= 9)
593 FC(send_sel_reg32_desc, /* 4+ */ 77, 77, /* 12+ */ -1, -1, devinfo->gen >= 9)
594 FC(send_sel_reg32_ex_desc, /* 4+ */ 61, 61, /* 12+ */ -1, -1, devinfo->gen >= 9)
595 FC(send_src1_reg_nr, /* 4+ */ 51, 44, /* 12+ */ -1, -1, devinfo->gen >= 9)
596 FC(send_src1_reg_file, /* 4+ */ 36, 36, /* 12+ */ -1, -1, devinfo->gen >= 9)
597 FC(send_dst_reg_file, /* 4+ */ 35, 35, /* 12+ */ -1, -1, devinfo->gen >= 9)
598 /** @} */
599
600 /* Message descriptor bits */
601 #define MD(x) ((x) + 96)
602
603 /**
604 * Set the SEND(C) message descriptor immediate.
605 *
606 * This doesn't include the SFID nor the EOT field that were considered to be
607 * part of the message descriptor by ancient versions of the BSpec, because
608 * they are present in the instruction even if the message descriptor is
609 * provided indirectly in the address register, so we want to specify them
610 * separately.
611 */
612 static inline void
613 brw_inst_set_send_desc(const struct gen_device_info *devinfo,
614 brw_inst *inst, uint32_t value)
615 {
616 if (devinfo->gen >= 9) {
617 brw_inst_set_bits(inst, 126, 96, value);
618 assert(value >> 31 == 0);
619 } else if (devinfo->gen >= 5) {
620 brw_inst_set_bits(inst, 124, 96, value);
621 assert(value >> 29 == 0);
622 } else {
623 brw_inst_set_bits(inst, 119, 96, value);
624 assert(value >> 24 == 0);
625 }
626 }
627
628 /**
629 * Get the SEND(C) message descriptor immediate.
630 *
631 * \sa brw_inst_set_send_desc().
632 */
633 static inline uint32_t
634 brw_inst_send_desc(const struct gen_device_info *devinfo, const brw_inst *inst)
635 {
636 if (devinfo->gen >= 9)
637 return brw_inst_bits(inst, 126, 96);
638 else if (devinfo->gen >= 5)
639 return brw_inst_bits(inst, 124, 96);
640 else
641 return brw_inst_bits(inst, 119, 96);
642 }
643
644 /**
645 * Set the SEND(C) message extended descriptor immediate.
646 *
647 * This doesn't include the SFID nor the EOT field that were considered to be
648 * part of the extended message descriptor by some versions of the BSpec,
649 * because they are present in the instruction even if the extended message
650 * descriptor is provided indirectly in a register, so we want to specify them
651 * separately.
652 */
653 static inline void
654 brw_inst_set_send_ex_desc(const struct gen_device_info *devinfo,
655 brw_inst *inst, uint32_t value)
656 {
657 assert(devinfo->gen >= 9);
658 brw_inst_set_bits(inst, 94, 91, GET_BITS(value, 31, 28));
659 brw_inst_set_bits(inst, 88, 85, GET_BITS(value, 27, 24));
660 brw_inst_set_bits(inst, 83, 80, GET_BITS(value, 23, 20));
661 brw_inst_set_bits(inst, 67, 64, GET_BITS(value, 19, 16));
662 assert(GET_BITS(value, 15, 0) == 0);
663 }
664
665 /**
666 * Set the SENDS(C) message extended descriptor immediate.
667 *
668 * This doesn't include the SFID nor the EOT field that were considered to be
669 * part of the extended message descriptor by some versions of the BSpec,
670 * because they are present in the instruction even if the extended message
671 * descriptor is provided indirectly in a register, so we want to specify them
672 * separately.
673 */
674 static inline void
675 brw_inst_set_sends_ex_desc(const struct gen_device_info *devinfo,
676 brw_inst *inst, uint32_t value)
677 {
678 brw_inst_set_bits(inst, 95, 80, GET_BITS(value, 31, 16));
679 assert(GET_BITS(value, 15, 10) == 0);
680 brw_inst_set_bits(inst, 67, 64, GET_BITS(value, 9, 6));
681 assert(GET_BITS(value, 5, 0) == 0);
682 }
683
684 /**
685 * Get the SEND(C) message extended descriptor immediate.
686 *
687 * \sa brw_inst_set_send_ex_desc().
688 */
689 static inline uint32_t
690 brw_inst_send_ex_desc(const struct gen_device_info *devinfo,
691 const brw_inst *inst)
692 {
693 assert(devinfo->gen >= 9);
694 return (brw_inst_bits(inst, 94, 91) << 28 |
695 brw_inst_bits(inst, 88, 85) << 24 |
696 brw_inst_bits(inst, 83, 80) << 20 |
697 brw_inst_bits(inst, 67, 64) << 16);
698 }
699
700 /**
701 * Get the SENDS(C) message extended descriptor immediate.
702 *
703 * \sa brw_inst_set_send_ex_desc().
704 */
705 static inline uint32_t
706 brw_inst_sends_ex_desc(const struct gen_device_info *devinfo,
707 const brw_inst *inst)
708 {
709 return (brw_inst_bits(inst, 95, 80) << 16 |
710 brw_inst_bits(inst, 67, 64) << 6);
711 }
712
713 /**
714 * Fields for SEND messages:
715 * @{
716 */
717 F(eot, /* 4+ */ 127, 127, /* 12+ */ -1, -1)
718 FF(mlen,
719 /* 4: */ 119, 116,
720 /* 4.5: */ 119, 116,
721 /* 5: */ 124, 121,
722 /* 6: */ 124, 121,
723 /* 7: */ 124, 121,
724 /* 8: */ 124, 121,
725 /* 12: */ -1, -1);
726 FF(rlen,
727 /* 4: */ 115, 112,
728 /* 4.5: */ 115, 112,
729 /* 5: */ 120, 116,
730 /* 6: */ 120, 116,
731 /* 7: */ 120, 116,
732 /* 8: */ 120, 116,
733 /* 12: */ -1, -1);
734 FF(header_present,
735 /* 4: doesn't exist */ -1, -1, -1, -1,
736 /* 5: */ 115, 115,
737 /* 6: */ 115, 115,
738 /* 7: */ 115, 115,
739 /* 8: */ 115, 115,
740 /* 12: */ -1, -1)
741 F(gateway_notify, /* 4+ */ MD(16), MD(15), /* 12+ */ -1, -1)
742 FF(function_control,
743 /* 4: */ 111, 96,
744 /* 4.5: */ 111, 96,
745 /* 5: */ 114, 96,
746 /* 6: */ 114, 96,
747 /* 7: */ 114, 96,
748 /* 8: */ 114, 96,
749 /* 12: */ -1, -1)
750 FF(gateway_subfuncid,
751 /* 4: */ MD(1), MD(0),
752 /* 4.5: */ MD(1), MD(0),
753 /* 5: */ MD(1), MD(0), /* 2:0, but bit 2 is reserved MBZ */
754 /* 6: */ MD(2), MD(0),
755 /* 7: */ MD(2), MD(0),
756 /* 8: */ MD(2), MD(0),
757 /* 12: */ -1, -1)
758 FF(sfid,
759 /* 4: */ 123, 120, /* called msg_target */
760 /* 4.5 */ 123, 120,
761 /* 5: */ 95, 92,
762 /* 6: */ 27, 24,
763 /* 7: */ 27, 24,
764 /* 8: */ 27, 24,
765 /* 12: */ -1, -1)
766 FF(null_rt,
767 /* 4-7: */ -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
768 /* 8: */ 80, 80,
769 /* 12: */ -1, -1) /* actually only Gen11+ */
770 FC(base_mrf, /* 4+ */ 27, 24, /* 12+ */ -1, -1, devinfo->gen < 6);
771 /** @} */
772
773 /**
774 * URB message function control bits:
775 * @{
776 */
777 FF(urb_per_slot_offset,
778 /* 4-6: */ -1, -1, -1, -1, -1, -1, -1, -1,
779 /* 7: */ MD(16), MD(16),
780 /* 8: */ MD(17), MD(17),
781 /* 12: */ -1, -1)
782 FC(urb_channel_mask_present, /* 4+ */ MD(15), MD(15), /* 12+ */ -1, -1, devinfo->gen >= 8)
783 FC(urb_complete, /* 4+ */ MD(15), MD(15), /* 12+ */ -1, -1, devinfo->gen < 8)
784 FC(urb_used, /* 4+ */ MD(14), MD(14), /* 12+ */ -1, -1, devinfo->gen < 7)
785 FC(urb_allocate, /* 4+ */ MD(13), MD(13), /* 12+ */ -1, -1, devinfo->gen < 7)
786 FF(urb_swizzle_control,
787 /* 4: */ MD(11), MD(10),
788 /* 4.5: */ MD(11), MD(10),
789 /* 5: */ MD(11), MD(10),
790 /* 6: */ MD(11), MD(10),
791 /* 7: */ MD(14), MD(14),
792 /* 8: */ MD(15), MD(15),
793 /* 12: */ -1, -1)
794 FF(urb_global_offset,
795 /* 4: */ MD( 9), MD(4),
796 /* 4.5: */ MD( 9), MD(4),
797 /* 5: */ MD( 9), MD(4),
798 /* 6: */ MD( 9), MD(4),
799 /* 7: */ MD(13), MD(3),
800 /* 8: */ MD(14), MD(4),
801 /* 12: */ -1, -1)
802 FF(urb_opcode,
803 /* 4: */ MD( 3), MD(0),
804 /* 4.5: */ MD( 3), MD(0),
805 /* 5: */ MD( 3), MD(0),
806 /* 6: */ MD( 3), MD(0),
807 /* 7: */ MD( 2), MD(0),
808 /* 8: */ MD( 3), MD(0),
809 /* 12: */ -1, -1)
810 /** @} */
811
812 /**
813 * Gen4-5 math messages:
814 * @{
815 */
816 FC(math_msg_data_type, /* 4+ */ MD(7), MD(7), /* 12+ */ -1, -1, devinfo->gen < 6)
817 FC(math_msg_saturate, /* 4+ */ MD(6), MD(6), /* 12+ */ -1, -1, devinfo->gen < 6)
818 FC(math_msg_precision, /* 4+ */ MD(5), MD(5), /* 12+ */ -1, -1, devinfo->gen < 6)
819 FC(math_msg_signed_int, /* 4+ */ MD(4), MD(4), /* 12+ */ -1, -1, devinfo->gen < 6)
820 FC(math_msg_function, /* 4+ */ MD(3), MD(0), /* 12+ */ -1, -1, devinfo->gen < 6)
821 /** @} */
822
823 /**
824 * Sampler message function control bits:
825 * @{
826 */
827 FF(sampler_simd_mode,
828 /* 4: doesn't exist */ -1, -1, -1, -1,
829 /* 5: */ MD(17), MD(16),
830 /* 6: */ MD(17), MD(16),
831 /* 7: */ MD(18), MD(17),
832 /* 8: */ MD(18), MD(17),
833 /* 12: */ -1, -1)
834 FF(sampler_msg_type,
835 /* 4: */ MD(15), MD(14),
836 /* 4.5: */ MD(15), MD(12),
837 /* 5: */ MD(15), MD(12),
838 /* 6: */ MD(15), MD(12),
839 /* 7: */ MD(16), MD(12),
840 /* 8: */ MD(16), MD(12),
841 /* 12: */ -1, -1)
842 FC(sampler_return_format, /* 4+ */ MD(13), MD(12), /* 12+ */ -1, -1, devinfo->gen == 4 && !devinfo->is_g4x)
843 F(sampler, /* 4+ */ MD(11), MD(8), /* 12+ */ -1, -1)
844 F(binding_table_index, /* 4+ */ MD( 7), MD(0), /* 12+ */ -1, -1) /* also used by other messages */
845 /** @} */
846
847 /**
848 * Data port message function control bits:
849 * @{
850 */
851 FC(dp_category, /* 4+ */ MD(18), MD(18), /* 12+ */ -1, -1, devinfo->gen >= 7)
852
853 /* Gen4-5 store fields in different bits for read/write messages. */
854 FF(dp_read_msg_type,
855 /* 4: */ MD(13), MD(12),
856 /* 4.5: */ MD(13), MD(11),
857 /* 5: */ MD(13), MD(11),
858 /* 6: */ MD(16), MD(13),
859 /* 7: */ MD(17), MD(14),
860 /* 8: */ MD(17), MD(14),
861 /* 12: */ -1, -1)
862 FF(dp_write_msg_type,
863 /* 4: */ MD(14), MD(12),
864 /* 4.5: */ MD(14), MD(12),
865 /* 5: */ MD(14), MD(12),
866 /* 6: */ MD(16), MD(13),
867 /* 7: */ MD(17), MD(14),
868 /* 8: */ MD(17), MD(14),
869 /* 12: */ -1, -1)
870 FF(dp_read_msg_control,
871 /* 4: */ MD(11), MD( 8),
872 /* 4.5: */ MD(10), MD( 8),
873 /* 5: */ MD(10), MD( 8),
874 /* 6: */ MD(12), MD( 8),
875 /* 7: */ MD(13), MD( 8),
876 /* 8: */ MD(13), MD( 8),
877 /* 12: */ -1, -1)
878 FF(dp_write_msg_control,
879 /* 4: */ MD(11), MD( 8),
880 /* 4.5: */ MD(11), MD( 8),
881 /* 5: */ MD(11), MD( 8),
882 /* 6: */ MD(12), MD( 8),
883 /* 7: */ MD(13), MD( 8),
884 /* 8: */ MD(13), MD( 8),
885 /* 12: */ -1, -1)
886 FC(dp_read_target_cache, /* 4+ */ MD(15), MD(14), /* 12+ */ -1, -1, devinfo->gen < 6);
887
888 FF(dp_write_commit,
889 /* 4: */ MD(15), MD(15),
890 /* 4.5: */ MD(15), MD(15),
891 /* 5: */ MD(15), MD(15),
892 /* 6: */ MD(17), MD(17),
893 /* 7+: does not exist */ -1, -1, -1, -1,
894 /* 12: */ -1, -1)
895
896 /* Gen6+ use the same bit locations for everything. */
897 FF(dp_msg_type,
898 /* 4-5: use dp_read_msg_type or dp_write_msg_type instead */
899 -1, -1, -1, -1, -1, -1,
900 /* 6: */ MD(16), MD(13),
901 /* 7: */ MD(17), MD(14),
902 /* 8: */ MD(18), MD(14),
903 /* 12: */ -1, -1)
904 FF(dp_msg_control,
905 /* 4: */ MD(11), MD( 8),
906 /* 4.5-5: use dp_read_msg_control or dp_write_msg_control */ -1, -1, -1, -1,
907 /* 6: */ MD(12), MD( 8),
908 /* 7: */ MD(13), MD( 8),
909 /* 8: */ MD(13), MD( 8),
910 /* 12: */ -1, -1)
911 /** @} */
912
913 /**
914 * Scratch message bits (Gen7+):
915 * @{
916 */
917 FC(scratch_read_write, /* 4+ */ MD(17), MD(17), /* 12+ */ -1, -1, devinfo->gen >= 7) /* 0 = read, 1 = write */
918 FC(scratch_type, /* 4+ */ MD(16), MD(16), /* 12+ */ -1, -1, devinfo->gen >= 7) /* 0 = OWord, 1 = DWord */
919 FC(scratch_invalidate_after_read, /* 4+ */ MD(15), MD(15), /* 12+ */ -1, -1, devinfo->gen >= 7)
920 FC(scratch_block_size, /* 4+ */ MD(13), MD(12), /* 12+ */ -1, -1, devinfo->gen >= 7)
921 FC(scratch_addr_offset, /* 4+ */ MD(11), MD( 0), /* 12+ */ -1, -1, devinfo->gen >= 7)
922 /** @} */
923
924 /**
925 * Render Target message function control bits:
926 * @{
927 */
928 FF(rt_last,
929 /* 4: */ MD(11), MD(11),
930 /* 4.5: */ MD(11), MD(11),
931 /* 5: */ MD(11), MD(11),
932 /* 6: */ MD(12), MD(12),
933 /* 7: */ MD(12), MD(12),
934 /* 8: */ MD(12), MD(12),
935 /* 12: */ -1, -1)
936 FC(rt_slot_group, /* 4+ */ MD(11), MD(11), /* 12+ */ -1, -1, devinfo->gen >= 6)
937 F(rt_message_type, /* 4+ */ MD(10), MD( 8), /* 12+ */ -1, -1)
938 /** @} */
939
940 /**
941 * Thread Spawn message function control bits:
942 * @{
943 */
944 F(ts_resource_select, /* 4+ */ MD( 4), MD( 4), /* 12+ */ -1, -1)
945 F(ts_request_type, /* 4+ */ MD( 1), MD( 1), /* 12+ */ -1, -1)
946 F(ts_opcode, /* 4+ */ MD( 0), MD( 0), /* 12+ */ -1, -1)
947 /** @} */
948
949 /**
950 * Pixel Interpolator message function control bits:
951 * @{
952 */
953 F(pi_simd_mode, /* 4+ */ MD(16), MD(16), /* 12+ */ -1, -1)
954 F(pi_nopersp, /* 4+ */ MD(14), MD(14), /* 12+ */ -1, -1)
955 F(pi_message_type, /* 4+ */ MD(13), MD(12), /* 12+ */ -1, -1)
956 F(pi_slot_group, /* 4+ */ MD(11), MD(11), /* 12+ */ -1, -1)
957 F(pi_message_data, /* 4+ */ MD(7), MD(0), /* 12+ */ -1, -1)
958 /** @} */
959
960 /**
961 * Immediates:
962 * @{
963 */
964 static inline int
965 brw_inst_imm_d(const struct gen_device_info *devinfo, const brw_inst *insn)
966 {
967 (void) devinfo;
968 return brw_inst_bits(insn, 127, 96);
969 }
970
971 static inline unsigned
972 brw_inst_imm_ud(const struct gen_device_info *devinfo, const brw_inst *insn)
973 {
974 (void) devinfo;
975 return brw_inst_bits(insn, 127, 96);
976 }
977
978 static inline uint64_t
979 brw_inst_imm_uq(ASSERTED const struct gen_device_info *devinfo,
980 const brw_inst *insn)
981 {
982 assert(devinfo->gen >= 8);
983 return brw_inst_bits(insn, 127, 64);
984 }
985
986 static inline float
987 brw_inst_imm_f(const struct gen_device_info *devinfo, const brw_inst *insn)
988 {
989 union {
990 float f;
991 uint32_t u;
992 } ft;
993 (void) devinfo;
994 ft.u = brw_inst_bits(insn, 127, 96);
995 return ft.f;
996 }
997
998 static inline double
999 brw_inst_imm_df(const struct gen_device_info *devinfo, const brw_inst *insn)
1000 {
1001 union {
1002 double d;
1003 uint64_t u;
1004 } dt;
1005 (void) devinfo;
1006 dt.u = brw_inst_bits(insn, 127, 64);
1007 return dt.d;
1008 }
1009
1010 static inline void
1011 brw_inst_set_imm_d(const struct gen_device_info *devinfo,
1012 brw_inst *insn, int value)
1013 {
1014 (void) devinfo;
1015 return brw_inst_set_bits(insn, 127, 96, value);
1016 }
1017
1018 static inline void
1019 brw_inst_set_imm_ud(const struct gen_device_info *devinfo,
1020 brw_inst *insn, unsigned value)
1021 {
1022 (void) devinfo;
1023 return brw_inst_set_bits(insn, 127, 96, value);
1024 }
1025
1026 static inline void
1027 brw_inst_set_imm_f(const struct gen_device_info *devinfo,
1028 brw_inst *insn, float value)
1029 {
1030 union {
1031 float f;
1032 uint32_t u;
1033 } ft;
1034 (void) devinfo;
1035 ft.f = value;
1036 brw_inst_set_bits(insn, 127, 96, ft.u);
1037 }
1038
1039 static inline void
1040 brw_inst_set_imm_df(const struct gen_device_info *devinfo,
1041 brw_inst *insn, double value)
1042 {
1043 union {
1044 double d;
1045 uint64_t u;
1046 } dt;
1047 (void) devinfo;
1048 dt.d = value;
1049 brw_inst_set_bits(insn, 127, 64, dt.u);
1050 }
1051
1052 static inline void
1053 brw_inst_set_imm_uq(const struct gen_device_info *devinfo,
1054 brw_inst *insn, uint64_t value)
1055 {
1056 (void) devinfo;
1057 brw_inst_set_bits(insn, 127, 64, value);
1058 }
1059
1060 /** @} */
1061
1062 #define REG_TYPE(reg) \
1063 static inline void \
1064 brw_inst_set_##reg##_file_type(const struct gen_device_info *devinfo, \
1065 brw_inst *inst, enum brw_reg_file file, \
1066 enum brw_reg_type type) \
1067 { \
1068 assert(file <= BRW_IMMEDIATE_VALUE); \
1069 unsigned hw_type = brw_reg_type_to_hw_type(devinfo, file, type); \
1070 brw_inst_set_##reg##_reg_file(devinfo, inst, file); \
1071 brw_inst_set_##reg##_reg_hw_type(devinfo, inst, hw_type); \
1072 } \
1073 \
1074 static inline enum brw_reg_type \
1075 brw_inst_##reg##_type(const struct gen_device_info *devinfo, \
1076 const brw_inst *inst) \
1077 { \
1078 unsigned file = __builtin_strcmp("dst", #reg) == 0 ? \
1079 (unsigned) BRW_GENERAL_REGISTER_FILE : \
1080 brw_inst_##reg##_reg_file(devinfo, inst); \
1081 unsigned hw_type = brw_inst_##reg##_reg_hw_type(devinfo, inst); \
1082 return brw_hw_type_to_reg_type(devinfo, (enum brw_reg_file)file, hw_type); \
1083 }
1084
1085 REG_TYPE(dst)
1086 REG_TYPE(src0)
1087 REG_TYPE(src1)
1088 #undef REG_TYPE
1089
1090
1091 /* The AddrImm fields are split into two discontiguous sections on Gen8+ */
1092 #define BRW_IA1_ADDR_IMM(reg, g4_high, g4_low, g8_nine, g8_high, g8_low) \
1093 static inline void \
1094 brw_inst_set_##reg##_ia1_addr_imm(const struct gen_device_info *devinfo, \
1095 brw_inst *inst, \
1096 unsigned value) \
1097 { \
1098 assert((value & ~0x3ff) == 0); \
1099 if (devinfo->gen >= 8) { \
1100 brw_inst_set_bits(inst, g8_high, g8_low, value & 0x1ff); \
1101 brw_inst_set_bits(inst, g8_nine, g8_nine, value >> 9); \
1102 } else { \
1103 brw_inst_set_bits(inst, g4_high, g4_low, value); \
1104 } \
1105 } \
1106 static inline unsigned \
1107 brw_inst_##reg##_ia1_addr_imm(const struct gen_device_info *devinfo, \
1108 const brw_inst *inst) \
1109 { \
1110 if (devinfo->gen >= 8) { \
1111 return brw_inst_bits(inst, g8_high, g8_low) | \
1112 (brw_inst_bits(inst, g8_nine, g8_nine) << 9); \
1113 } else { \
1114 return brw_inst_bits(inst, g4_high, g4_low); \
1115 } \
1116 }
1117
1118 /* AddrImm[9:0] for Align1 Indirect Addressing */
1119 /* -Gen 4- ----Gen8---- */
1120 BRW_IA1_ADDR_IMM(src1, 105, 96, 121, 104, 96)
1121 BRW_IA1_ADDR_IMM(src0, 73, 64, 95, 72, 64)
1122 BRW_IA1_ADDR_IMM(dst, 57, 48, 47, 56, 48)
1123
1124 #define BRW_IA16_ADDR_IMM(reg, g4_high, g4_low, g8_nine, g8_high, g8_low) \
1125 static inline void \
1126 brw_inst_set_##reg##_ia16_addr_imm(const struct gen_device_info *devinfo, \
1127 brw_inst *inst, unsigned value) \
1128 { \
1129 assert((value & ~0x3ff) == 0); \
1130 if (devinfo->gen >= 8) { \
1131 assert(GET_BITS(value, 3, 0) == 0); \
1132 brw_inst_set_bits(inst, g8_high, g8_low, GET_BITS(value, 8, 4)); \
1133 brw_inst_set_bits(inst, g8_nine, g8_nine, GET_BITS(value, 9, 9)); \
1134 } else { \
1135 brw_inst_set_bits(inst, g4_high, g4_low, value); \
1136 } \
1137 } \
1138 static inline unsigned \
1139 brw_inst_##reg##_ia16_addr_imm(const struct gen_device_info *devinfo, \
1140 const brw_inst *inst) \
1141 { \
1142 if (devinfo->gen >= 8) { \
1143 return (brw_inst_bits(inst, g8_high, g8_low) << 4) | \
1144 (brw_inst_bits(inst, g8_nine, g8_nine) << 9); \
1145 } else { \
1146 return brw_inst_bits(inst, g4_high, g4_low); \
1147 } \
1148 }
1149
1150 /* AddrImm[9:0] for Align16 Indirect Addressing:
1151 * Compared to Align1, these are missing the low 4 bits.
1152 * -Gen 4- ----Gen8----
1153 */
1154 BRW_IA16_ADDR_IMM(src1, 105, 96, 121, 104, 100)
1155 BRW_IA16_ADDR_IMM(src0, 73, 64, 95, 72, 68)
1156 BRW_IA16_ADDR_IMM(dst, 57, 52, 47, 56, 52)
1157 BRW_IA16_ADDR_IMM(send_src0, -1, -1, 78, 72, 68)
1158 BRW_IA16_ADDR_IMM(send_dst, -1, -1, 62, 56, 52)
1159
1160 /**
1161 * Fetch a set of contiguous bits from the instruction.
1162 *
1163 * Bits indices range from 0..127; fields may not cross 64-bit boundaries.
1164 */
1165 static inline uint64_t
1166 brw_inst_bits(const brw_inst *inst, unsigned high, unsigned low)
1167 {
1168 assert(high >= low);
1169 /* We assume the field doesn't cross 64-bit boundaries. */
1170 const unsigned word = high / 64;
1171 assert(word == low / 64);
1172
1173 high %= 64;
1174 low %= 64;
1175
1176 const uint64_t mask = (~0ull >> (64 - (high - low + 1)));
1177
1178 return (inst->data[word] >> low) & mask;
1179 }
1180
1181 /**
1182 * Set bits in the instruction, with proper shifting and masking.
1183 *
1184 * Bits indices range from 0..127; fields may not cross 64-bit boundaries.
1185 */
1186 static inline void
1187 brw_inst_set_bits(brw_inst *inst, unsigned high, unsigned low, uint64_t value)
1188 {
1189 assert(high >= low);
1190 const unsigned word = high / 64;
1191 assert(word == low / 64);
1192
1193 high %= 64;
1194 low %= 64;
1195
1196 const uint64_t mask = (~0ull >> (64 - (high - low + 1))) << low;
1197
1198 /* Make sure the supplied value actually fits in the given bitfield. */
1199 assert((value & (mask >> low)) == value);
1200
1201 inst->data[word] = (inst->data[word] & ~mask) | (value << low);
1202 }
1203
1204 #undef BRW_IA16_ADDR_IMM
1205 #undef BRW_IA1_ADDR_IMM
1206 #undef MD
1207 #undef F8
1208 #undef FF
1209 #undef BOUNDS
1210 #undef F
1211 #undef FC
1212
1213 typedef struct {
1214 uint64_t data;
1215 } brw_compact_inst;
1216
1217 /**
1218 * Fetch a set of contiguous bits from the compacted instruction.
1219 *
1220 * Bits indices range from 0..63.
1221 */
1222 static inline unsigned
1223 brw_compact_inst_bits(const brw_compact_inst *inst, unsigned high, unsigned low)
1224 {
1225 const uint64_t mask = (1ull << (high - low + 1)) - 1;
1226
1227 return (inst->data >> low) & mask;
1228 }
1229
1230 /**
1231 * Set bits in the compacted instruction.
1232 *
1233 * Bits indices range from 0..63.
1234 */
1235 static inline void
1236 brw_compact_inst_set_bits(brw_compact_inst *inst, unsigned high, unsigned low,
1237 uint64_t value)
1238 {
1239 const uint64_t mask = ((1ull << (high - low + 1)) - 1) << low;
1240
1241 /* Make sure the supplied value actually fits in the given bitfield. */
1242 assert((value & (mask >> low)) == value);
1243
1244 inst->data = (inst->data & ~mask) | (value << low);
1245 }
1246
1247 #define FC(name, high, low, assertions) \
1248 static inline void \
1249 brw_compact_inst_set_##name(const struct gen_device_info *devinfo, \
1250 brw_compact_inst *inst, unsigned v) \
1251 { \
1252 assert(assertions); \
1253 (void) devinfo; \
1254 brw_compact_inst_set_bits(inst, high, low, v); \
1255 } \
1256 static inline unsigned \
1257 brw_compact_inst_##name(const struct gen_device_info *devinfo, \
1258 const brw_compact_inst *inst) \
1259 { \
1260 assert(assertions); \
1261 (void) devinfo; \
1262 return brw_compact_inst_bits(inst, high, low); \
1263 }
1264
1265 /* A simple macro for fields which stay in the same place on all generations. */
1266 #define F(name, high, low) FC(name, high, low, true)
1267
1268 F(src1_reg_nr, 63, 56)
1269 F(src0_reg_nr, 55, 48)
1270 F(dst_reg_nr, 47, 40)
1271 F(src1_index, 39, 35)
1272 F(src0_index, 34, 30)
1273 F(cmpt_control, 29, 29) /* Same location as brw_inst */
1274 FC(flag_subreg_nr, 28, 28, devinfo->gen <= 6)
1275 F(cond_modifier, 27, 24) /* Same location as brw_inst */
1276 FC(acc_wr_control, 23, 23, devinfo->gen >= 6)
1277 FC(mask_control_ex, 23, 23, devinfo->is_g4x || devinfo->gen == 5)
1278 F(subreg_index, 22, 18)
1279 F(datatype_index, 17, 13)
1280 F(control_index, 12, 8)
1281 F(debug_control, 7, 7)
1282 F(hw_opcode, 6, 0) /* Same location as brw_inst */
1283
1284 /**
1285 * (Gen8+) Compacted three-source instructions:
1286 * @{
1287 */
1288 FC(3src_src2_reg_nr, 63, 57, devinfo->gen >= 8)
1289 FC(3src_src1_reg_nr, 56, 50, devinfo->gen >= 8)
1290 FC(3src_src0_reg_nr, 49, 43, devinfo->gen >= 8)
1291 FC(3src_src2_subreg_nr, 42, 40, devinfo->gen >= 8)
1292 FC(3src_src1_subreg_nr, 39, 37, devinfo->gen >= 8)
1293 FC(3src_src0_subreg_nr, 36, 34, devinfo->gen >= 8)
1294 FC(3src_src2_rep_ctrl, 33, 33, devinfo->gen >= 8)
1295 FC(3src_src1_rep_ctrl, 32, 32, devinfo->gen >= 8)
1296 FC(3src_saturate, 31, 31, devinfo->gen >= 8)
1297 FC(3src_debug_control, 30, 30, devinfo->gen >= 8)
1298 FC(3src_cmpt_control, 29, 29, devinfo->gen >= 8)
1299 FC(3src_src0_rep_ctrl, 28, 28, devinfo->gen >= 8)
1300 /* Reserved */
1301 FC(3src_dst_reg_nr, 18, 12, devinfo->gen >= 8)
1302 FC(3src_source_index, 11, 10, devinfo->gen >= 8)
1303 FC(3src_control_index, 9, 8, devinfo->gen >= 8)
1304 /* Bit 7 is Reserved (for future Opcode expansion) */
1305 FC(3src_hw_opcode, 6, 0, devinfo->gen >= 8)
1306 /** @} */
1307
1308 #undef F
1309
1310 #ifdef __cplusplus
1311 }
1312 #endif
1313
1314 #endif