2 * Copyright © 2014 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
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9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
27 * A representation of i965 EU assembly instructions, with helper methods to
28 * get and set various fields. This is the actual hardware format.
37 #include "brw_eu_defines.h"
38 #include "common/gen_device_info.h"
44 /* brw_context.h has a forward declaration of brw_inst, so name the struct. */
45 typedef struct brw_inst
{
49 static inline uint64_t brw_inst_bits(const brw_inst
*inst
,
50 unsigned high
, unsigned low
);
51 static inline void brw_inst_set_bits(brw_inst
*inst
,
52 unsigned high
, unsigned low
,
55 #define FC(name, high, low, assertions) \
57 brw_inst_set_##name(const struct gen_device_info *devinfo, \
58 brw_inst *inst, uint64_t v) \
62 brw_inst_set_bits(inst, high, low, v); \
64 static inline uint64_t \
65 brw_inst_##name(const struct gen_device_info *devinfo, \
66 const brw_inst *inst) \
70 return brw_inst_bits(inst, high, low); \
73 /* A simple macro for fields which stay in the same place on all generations. */
74 #define F(name, high, low) FC(name, high, low, true)
76 #define BOUNDS(hi4, lo4, hi45, lo45, hi5, lo5, hi6, lo6, hi7, lo7, hi8, lo8) \
78 if (devinfo->gen >= 8) { \
79 high = hi8; low = lo8; \
80 } else if (devinfo->gen >= 7) { \
81 high = hi7; low = lo7; \
82 } else if (devinfo->gen >= 6) { \
83 high = hi6; low = lo6; \
84 } else if (devinfo->gen >= 5) { \
85 high = hi5; low = lo5; \
86 } else if (devinfo->is_g4x) { \
87 high = hi45; low = lo45; \
89 high = hi4; low = lo4; \
91 assert(((int) high) != -1 && ((int) low) != -1); \
93 /* A general macro for cases where the field has moved to several different
94 * bit locations across generations. GCC appears to combine cases where the
95 * bits are identical, removing some of the inefficiency.
97 #define FF(name, hi4, lo4, hi45, lo45, hi5, lo5, hi6, lo6, hi7, lo7, hi8, lo8)\
99 brw_inst_set_##name(const struct gen_device_info *devinfo, \
100 brw_inst *inst, uint64_t value) \
102 BOUNDS(hi4, lo4, hi45, lo45, hi5, lo5, hi6, lo6, hi7, lo7, hi8, lo8) \
103 brw_inst_set_bits(inst, high, low, value); \
105 static inline uint64_t \
106 brw_inst_##name(const struct gen_device_info *devinfo, const brw_inst *inst) \
108 BOUNDS(hi4, lo4, hi45, lo45, hi5, lo5, hi6, lo6, hi7, lo7, hi8, lo8) \
109 return brw_inst_bits(inst, high, low); \
112 /* A macro for fields which moved as of Gen8+. */
113 #define F8(name, gen4_high, gen4_low, gen8_high, gen8_low) \
115 /* 4: */ gen4_high, gen4_low, \
116 /* 4.5: */ gen4_high, gen4_low, \
117 /* 5: */ gen4_high, gen4_low, \
118 /* 6: */ gen4_high, gen4_low, \
119 /* 7: */ gen4_high, gen4_low, \
120 /* 8: */ gen8_high, gen8_low);
122 F(src1_vstride
, 120, 117)
123 F(src1_width
, 116, 114)
124 F(src1_da16_swiz_w
, 115, 114)
125 F(src1_da16_swiz_z
, 113, 112)
126 F(src1_hstride
, 113, 112)
127 F(src1_address_mode
, 111, 111)
128 /** Src1.SrcMod @{ */
129 F(src1_negate
, 110, 110)
130 F(src1_abs
, 109, 109)
132 F8(src1_ia_subreg_nr
, /* 4+ */ 108, 106, /* 8+ */ 108, 105)
133 F(src1_da_reg_nr
, 108, 101)
134 F(src1_da16_subreg_nr
, 100, 100)
135 F(src1_da1_subreg_nr
, 100, 96)
136 F(src1_da16_swiz_y
, 99, 98)
137 F(src1_da16_swiz_x
, 97, 96)
138 F8(src1_reg_type
, /* 4+ */ 46, 44, /* 8+ */ 94, 91)
139 F8(src1_reg_file
, /* 4+ */ 43, 42, /* 8+ */ 90, 89)
140 F(src0_vstride
, 88, 85)
141 F(src0_width
, 84, 82)
142 F(src0_da16_swiz_w
, 83, 82)
143 F(src0_da16_swiz_z
, 81, 80)
144 F(src0_hstride
, 81, 80)
145 F(src0_address_mode
, 79, 79)
146 /** Src0.SrcMod @{ */
147 F(src0_negate
, 78, 78)
150 F8(src0_ia_subreg_nr
, /* 4+ */ 76, 74, /* 8+ */ 76, 73)
151 F(src0_da_reg_nr
, 76, 69)
152 F(src0_da16_subreg_nr
, 68, 68)
153 F(src0_da1_subreg_nr
, 68, 64)
154 F(src0_da16_swiz_y
, 67, 66)
155 F(src0_da16_swiz_x
, 65, 64)
156 F(dst_address_mode
, 63, 63)
157 F(dst_hstride
, 62, 61)
158 F8(dst_ia_subreg_nr
, /* 4+ */ 60, 58, /* 8+ */ 60, 57)
159 F(dst_da_reg_nr
, 60, 53)
160 F(dst_da16_subreg_nr
, 52, 52)
161 F(dst_da1_subreg_nr
, 52, 48)
162 F(da16_writemask
, 51, 48) /* Dst.ChanEn */
163 F8(src0_reg_type
, /* 4+ */ 41, 39, /* 8+ */ 46, 43)
164 F8(src0_reg_file
, /* 4+ */ 38, 37, /* 8+ */ 42, 41)
165 F8(dst_reg_type
, /* 4+ */ 36, 34, /* 8+ */ 40, 37)
166 F8(dst_reg_file
, /* 4+ */ 33, 32, /* 8+ */ 36, 35)
167 F8(mask_control
, /* 4+ */ 9, 9, /* 8+ */ 34, 34)
169 /* 4-6: doesn't exist */ -1, -1, -1, -1, -1, -1, -1, -1,
172 F8(flag_subreg_nr
, /* 4+ */ 89, 89, /* 8+ */ 32, 32)
174 F(debug_control
, 30, 30)
175 F(cmpt_control
, 29, 29)
176 FC(branch_control
, 28, 28, devinfo
->gen
>= 8)
177 FC(acc_wr_control
, 28, 28, devinfo
->gen
>= 6)
178 FC(mask_control_ex
, 28, 28, devinfo
->is_g4x
|| devinfo
->gen
== 5)
179 F(cond_modifier
, 27, 24)
180 FC(math_function
, 27, 24, devinfo
->gen
>= 6)
183 F(pred_control
, 19, 16)
184 F(thread_control
, 15, 14)
185 F(qtr_control
, 13, 12)
187 /* 4-6: doesn't exist */ -1, -1, -1, -1, -1, -1, -1, -1,
190 F8(no_dd_check
, /* 4+ */ 11, 11, /* 8+ */ 10, 10)
191 F8(no_dd_clear
, /* 4+ */ 10, 10, /* 8+ */ 9, 9)
193 /* Bit 7 is Reserved (for future Opcode expansion) */
197 * Three-source instructions:
200 F(3src_src2_reg_nr
, 125, 118)
201 F(3src_src2_subreg_nr
, 117, 115) /* Extra discontiguous bit on CHV? */
202 F(3src_src2_swizzle
, 114, 107)
203 F(3src_src2_rep_ctrl
, 106, 106)
204 F(3src_src1_reg_nr
, 104, 97)
205 F(3src_src1_subreg_nr
, 96, 94) /* Extra discontiguous bit on CHV? */
206 F(3src_src1_swizzle
, 93, 86)
207 F(3src_src1_rep_ctrl
, 85, 85)
208 F(3src_src0_reg_nr
, 83, 76)
209 F(3src_src0_subreg_nr
, 75, 73) /* Extra discontiguous bit on CHV? */
210 F(3src_src0_swizzle
, 72, 65)
211 F(3src_src0_rep_ctrl
, 64, 64)
212 F(3src_dst_reg_nr
, 63, 56)
213 F(3src_dst_subreg_nr
, 55, 53)
214 F(3src_dst_writemask
, 52, 49)
215 F8(3src_nib_ctrl
, 47, 47, 11, 11) /* only exists on IVB+ */
216 F8(3src_dst_type
, 45, 44, 48, 46) /* only exists on IVB+ */
217 F8(3src_src_type
, 43, 42, 45, 43)
218 F8(3src_src2_negate
, 41, 41, 42, 42)
219 F8(3src_src2_abs
, 40, 40, 41, 41)
220 F8(3src_src1_negate
, 39, 39, 40, 40)
221 F8(3src_src1_abs
, 38, 38, 39, 39)
222 F8(3src_src0_negate
, 37, 37, 38, 38)
223 F8(3src_src0_abs
, 36, 36, 37, 37)
224 F8(3src_flag_reg_nr
, 34, 34, 33, 33)
225 F8(3src_flag_subreg_nr
, 33, 33, 32, 32)
226 FF(3src_dst_reg_file
,
227 /* 4-5: doesn't exist - no 3-source instructions */ -1, -1, -1, -1, -1, -1,
229 /* 7-8: doesn't exist - no MRFs */ -1, -1, -1, -1)
230 F(3src_saturate
, 31, 31)
231 F(3src_debug_control
, 30, 30)
232 F(3src_cmpt_control
, 29, 29)
233 F(3src_acc_wr_control
, 28, 28)
234 F(3src_cond_modifier
, 27, 24)
235 F(3src_exec_size
, 23, 21)
236 F(3src_pred_inv
, 20, 20)
237 F(3src_pred_control
, 19, 16)
238 F(3src_thread_control
, 15, 14)
239 F(3src_qtr_control
, 13, 12)
240 F8(3src_no_dd_check
, 11, 11, 10, 10)
241 F8(3src_no_dd_clear
, 10, 10, 9, 9)
242 F8(3src_mask_control
, 9, 9, 34, 34)
243 F(3src_access_mode
, 8, 8)
244 /* Bit 7 is Reserved (for future Opcode expansion) */
249 * Flow control instruction bits:
253 brw_inst_set_uip(const struct gen_device_info
*devinfo
,
254 brw_inst
*inst
, int32_t value
)
256 assert(devinfo
->gen
>= 6);
258 if (devinfo
->gen
>= 8) {
259 brw_inst_set_bits(inst
, 95, 64, (uint32_t)value
);
261 assert(value
<= (1 << 16) - 1);
262 assert(value
> -(1 << 16));
263 brw_inst_set_bits(inst
, 127, 112, (uint16_t)value
);
267 static inline int32_t
268 brw_inst_uip(const struct gen_device_info
*devinfo
, const brw_inst
*inst
)
270 assert(devinfo
->gen
>= 6);
272 if (devinfo
->gen
>= 8) {
273 return brw_inst_bits(inst
, 95, 64);
275 return (int16_t)brw_inst_bits(inst
, 127, 112);
280 brw_inst_set_jip(const struct gen_device_info
*devinfo
,
281 brw_inst
*inst
, int32_t value
)
283 assert(devinfo
->gen
>= 6);
285 if (devinfo
->gen
>= 8) {
286 brw_inst_set_bits(inst
, 127, 96, (uint32_t)value
);
288 assert(value
<= (1 << 15) - 1);
289 assert(value
>= -(1 << 15));
290 brw_inst_set_bits(inst
, 111, 96, (uint16_t)value
);
294 static inline int32_t
295 brw_inst_jip(const struct gen_device_info
*devinfo
, const brw_inst
*inst
)
297 assert(devinfo
->gen
>= 6);
299 if (devinfo
->gen
>= 8) {
300 return brw_inst_bits(inst
, 127, 96);
302 return (int16_t)brw_inst_bits(inst
, 111, 96);
306 /** Like FC, but using int16_t to handle negative jump targets. */
307 #define FJ(name, high, low, assertions) \
309 brw_inst_set_##name(const struct gen_device_info *devinfo, brw_inst *inst, int16_t v) \
311 assert(assertions); \
313 brw_inst_set_bits(inst, high, low, (uint16_t) v); \
315 static inline int16_t \
316 brw_inst_##name(const struct gen_device_info *devinfo, const brw_inst *inst) \
318 assert(assertions); \
320 return brw_inst_bits(inst, high, low); \
323 FJ(gen6_jump_count
, 63, 48, devinfo
->gen
== 6)
324 FJ(gen4_jump_count
, 111, 96, devinfo
->gen
< 6)
325 FC(gen4_pop_count
, 115, 112, devinfo
->gen
< 6)
328 /* Message descriptor bits */
329 #define MD(x) ((x) + 96)
332 * Fields for SEND messages:
351 /* 4: doesn't exist */ -1, -1, -1, -1,
356 F(gateway_notify
, MD(16), MD(15))
364 FF(gateway_subfuncid
,
365 /* 4: */ MD(1), MD(0),
366 /* 4.5: */ MD(1), MD(0),
367 /* 5: */ MD(1), MD(0), /* 2:0, but bit 2 is reserved MBZ */
368 /* 6: */ MD(2), MD(0),
369 /* 7: */ MD(2), MD(0),
370 /* 8: */ MD(2), MD(0))
372 /* 4: */ 123, 120, /* called msg_target */
378 FC(base_mrf
, 27, 24, devinfo
->gen
< 6);
382 * URB message function control bits:
385 FF(urb_per_slot_offset
,
386 /* 4-6: */ -1, -1, -1, -1, -1, -1, -1, -1,
387 /* 7: */ MD(16), MD(16),
388 /* 8: */ MD(17), MD(17))
389 FC(urb_channel_mask_present
, MD(15), MD(15), devinfo
->gen
>= 8)
390 FC(urb_complete
, MD(15), MD(15), devinfo
->gen
< 8)
391 FC(urb_used
, MD(14), MD(14), devinfo
->gen
< 7)
392 FC(urb_allocate
, MD(13), MD(13), devinfo
->gen
< 7)
393 FF(urb_swizzle_control
,
394 /* 4: */ MD(11), MD(10),
395 /* 4.5: */ MD(11), MD(10),
396 /* 5: */ MD(11), MD(10),
397 /* 6: */ MD(11), MD(10),
398 /* 7: */ MD(14), MD(14),
399 /* 8: */ MD(15), MD(15))
400 FF(urb_global_offset
,
401 /* 4: */ MD( 9), MD(4),
402 /* 4.5: */ MD( 9), MD(4),
403 /* 5: */ MD( 9), MD(4),
404 /* 6: */ MD( 9), MD(4),
405 /* 7: */ MD(13), MD(3),
406 /* 8: */ MD(14), MD(4))
408 /* 4: */ MD( 3), MD(0),
409 /* 4.5: */ MD( 3), MD(0),
410 /* 5: */ MD( 3), MD(0),
411 /* 6: */ MD( 3), MD(0),
412 /* 7: */ MD( 2), MD(0),
413 /* 8: */ MD( 3), MD(0))
417 * Gen4-5 math messages:
420 FC(math_msg_data_type
, MD(7), MD(7), devinfo
->gen
< 6)
421 FC(math_msg_saturate
, MD(6), MD(6), devinfo
->gen
< 6)
422 FC(math_msg_precision
, MD(5), MD(5), devinfo
->gen
< 6)
423 FC(math_msg_signed_int
, MD(4), MD(4), devinfo
->gen
< 6)
424 FC(math_msg_function
, MD(3), MD(0), devinfo
->gen
< 6)
428 * Sampler message function control bits:
431 FF(sampler_simd_mode
,
432 /* 4: doesn't exist */ -1, -1, -1, -1,
433 /* 5: */ MD(17), MD(16),
434 /* 6: */ MD(17), MD(16),
435 /* 7: */ MD(18), MD(17),
436 /* 8: */ MD(18), MD(17))
438 /* 4: */ MD(15), MD(14),
439 /* 4.5: */ MD(15), MD(12),
440 /* 5: */ MD(15), MD(12),
441 /* 6: */ MD(15), MD(12),
442 /* 7: */ MD(16), MD(12),
443 /* 8: */ MD(16), MD(12))
444 FC(sampler_return_format
, MD(13), MD(12), devinfo
->gen
== 4 && !devinfo
->is_g4x
)
445 F(sampler
, MD(11), MD(8))
446 F(binding_table_index
, MD( 7), MD(0)) /* also used by other messages */
450 * Data port message function control bits:
453 FC(dp_category
, MD(18), MD(18), devinfo
->gen
>= 7)
455 /* Gen4-5 store fields in different bits for read/write messages. */
457 /* 4: */ MD(13), MD(12),
458 /* 4.5: */ MD(13), MD(11),
459 /* 5: */ MD(13), MD(11),
460 /* 6: */ MD(16), MD(13),
461 /* 7: */ MD(17), MD(14),
462 /* 8: */ MD(17), MD(14))
463 FF(dp_write_msg_type
,
464 /* 4: */ MD(14), MD(12),
465 /* 4.5: */ MD(14), MD(12),
466 /* 5: */ MD(14), MD(12),
467 /* 6: */ MD(16), MD(13),
468 /* 7: */ MD(17), MD(14),
469 /* 8: */ MD(17), MD(14))
470 FF(dp_read_msg_control
,
471 /* 4: */ MD(11), MD( 8),
472 /* 4.5: */ MD(10), MD( 8),
473 /* 5: */ MD(10), MD( 8),
474 /* 6: */ MD(12), MD( 8),
475 /* 7: */ MD(13), MD( 8),
476 /* 8: */ MD(13), MD( 8))
477 FF(dp_write_msg_control
,
478 /* 4: */ MD(11), MD( 8),
479 /* 4.5: */ MD(11), MD( 8),
480 /* 5: */ MD(11), MD( 8),
481 /* 6: */ MD(12), MD( 8),
482 /* 7: */ MD(13), MD( 8),
483 /* 8: */ MD(13), MD( 8))
484 FC(dp_read_target_cache
, MD(15), MD(14), devinfo
->gen
< 6);
487 /* 4: */ MD(15), MD(15),
488 /* 4.5: */ MD(15), MD(15),
489 /* 5: */ MD(15), MD(15),
490 /* 6: */ MD(17), MD(17),
491 /* 7+: does not exist */ -1, -1, -1, -1)
493 /* Gen6+ use the same bit locations for everything. */
495 /* 4-5: use dp_read_msg_type or dp_write_msg_type instead */
496 -1, -1, -1, -1, -1, -1,
497 /* 6: */ MD(16), MD(13),
498 /* 7: */ MD(17), MD(14),
499 /* 8: */ MD(17), MD(14))
501 /* 4: */ MD(11), MD( 8),
502 /* 4.5-5: use dp_read_msg_control or dp_write_msg_control */ -1, -1, -1, -1,
503 /* 6: */ MD(12), MD( 8),
504 /* 7: */ MD(13), MD( 8),
505 /* 8: */ MD(13), MD( 8))
509 * Scratch message bits (Gen7+):
512 FC(scratch_read_write
, MD(17), MD(17), devinfo
->gen
>= 7) /* 0 = read, 1 = write */
513 FC(scratch_type
, MD(16), MD(16), devinfo
->gen
>= 7) /* 0 = OWord, 1 = DWord */
514 FC(scratch_invalidate_after_read
, MD(15), MD(15), devinfo
->gen
>= 7)
515 FC(scratch_block_size
, MD(13), MD(12), devinfo
->gen
>= 7)
516 FC(scratch_addr_offset
, MD(11), MD( 0), devinfo
->gen
>= 7)
520 * Render Target message function control bits:
524 /* 4: */ MD(11), MD(11),
525 /* 4.5: */ MD(11), MD(11),
526 /* 5: */ MD(11), MD(11),
527 /* 6: */ MD(12), MD(12),
528 /* 7: */ MD(12), MD(12),
529 /* 8: */ MD(12), MD(12))
530 FC(rt_slot_group
, MD(11), MD(11), devinfo
->gen
>= 6)
531 F(rt_message_type
, MD(10), MD( 8))
535 * Thread Spawn message function control bits:
538 F(ts_resource_select
, MD( 4), MD( 4))
539 F(ts_request_type
, MD( 1), MD( 1))
540 F(ts_opcode
, MD( 0), MD( 0))
544 * Pixel Interpolator message function control bits:
547 F(pi_simd_mode
, MD(16), MD(16))
548 F(pi_nopersp
, MD(14), MD(14))
549 F(pi_message_type
, MD(13), MD(12))
550 F(pi_slot_group
, MD(11), MD(11))
551 F(pi_message_data
, MD(7), MD(0))
559 brw_inst_imm_d(const struct gen_device_info
*devinfo
, const brw_inst
*insn
)
562 return brw_inst_bits(insn
, 127, 96);
565 static inline unsigned
566 brw_inst_imm_ud(const struct gen_device_info
*devinfo
, const brw_inst
*insn
)
569 return brw_inst_bits(insn
, 127, 96);
573 brw_inst_imm_f(const struct gen_device_info
*devinfo
, const brw_inst
*insn
)
580 ft
.u
= brw_inst_bits(insn
, 127, 96);
585 brw_inst_imm_df(const struct gen_device_info
*devinfo
, const brw_inst
*insn
)
592 dt
.u
= brw_inst_bits(insn
, 127, 64);
597 brw_inst_set_imm_d(const struct gen_device_info
*devinfo
,
598 brw_inst
*insn
, int value
)
601 return brw_inst_set_bits(insn
, 127, 96, value
);
605 brw_inst_set_imm_ud(const struct gen_device_info
*devinfo
,
606 brw_inst
*insn
, unsigned value
)
609 return brw_inst_set_bits(insn
, 127, 96, value
);
613 brw_inst_set_imm_f(const struct gen_device_info
*devinfo
,
614 brw_inst
*insn
, float value
)
622 brw_inst_set_bits(insn
, 127, 96, ft
.u
);
626 brw_inst_set_imm_df(const struct gen_device_info
*devinfo
,
627 brw_inst
*insn
, double value
)
635 brw_inst_set_bits(insn
, 127, 64, dt
.u
);
639 brw_inst_set_imm_uq(const struct gen_device_info
*devinfo
,
640 brw_inst
*insn
, uint64_t value
)
643 brw_inst_set_bits(insn
, 127, 64, value
);
648 /* The AddrImm fields are split into two discontiguous sections on Gen8+ */
649 #define BRW_IA1_ADDR_IMM(reg, g4_high, g4_low, g8_nine, g8_high, g8_low) \
651 brw_inst_set_##reg##_ia1_addr_imm(const struct gen_device_info *devinfo, \
655 assert((value & ~0x3ff) == 0); \
656 if (devinfo->gen >= 8) { \
657 brw_inst_set_bits(inst, g8_high, g8_low, value & 0x1ff); \
658 brw_inst_set_bits(inst, g8_nine, g8_nine, value >> 9); \
660 brw_inst_set_bits(inst, g4_high, g4_low, value); \
663 static inline unsigned \
664 brw_inst_##reg##_ia1_addr_imm(const struct gen_device_info *devinfo, \
665 const brw_inst *inst) \
667 if (devinfo->gen >= 8) { \
668 return brw_inst_bits(inst, g8_high, g8_low) | \
669 (brw_inst_bits(inst, g8_nine, g8_nine) << 9); \
671 return brw_inst_bits(inst, g4_high, g4_low); \
675 /* AddrImm[9:0] for Align1 Indirect Addressing */
676 /* -Gen 4- ----Gen8---- */
677 BRW_IA1_ADDR_IMM(src1
, 105, 96, 121, 104, 96)
678 BRW_IA1_ADDR_IMM(src0
, 73, 64, 95, 72, 64)
679 BRW_IA1_ADDR_IMM(dst
, 57, 48, 47, 56, 48)
681 #define BRW_IA16_ADDR_IMM(reg, g4_high, g4_low, g8_nine, g8_high, g8_low) \
683 brw_inst_set_##reg##_ia16_addr_imm(const struct gen_device_info *devinfo, \
684 brw_inst *inst, unsigned value) \
686 assert((value & ~0x3ff) == 0); \
687 if (devinfo->gen >= 8) { \
688 brw_inst_set_bits(inst, g8_high, g8_low, value & 0x1ff); \
689 brw_inst_set_bits(inst, g8_nine, g8_nine, value >> 9); \
691 brw_inst_set_bits(inst, g4_high, g4_low, value >> 9); \
694 static inline unsigned \
695 brw_inst_##reg##_ia16_addr_imm(const struct gen_device_info *devinfo, \
696 const brw_inst *inst) \
698 if (devinfo->gen >= 8) { \
699 return brw_inst_bits(inst, g8_high, g8_low) | \
700 (brw_inst_bits(inst, g8_nine, g8_nine) << 9); \
702 return brw_inst_bits(inst, g4_high, g4_low); \
706 /* AddrImm[9:0] for Align16 Indirect Addressing:
707 * Compared to Align1, these are missing the low 4 bits.
708 * -Gen 4- ----Gen8----
710 BRW_IA16_ADDR_IMM(src1
, 105, 96, 121, 104, 100)
711 BRW_IA16_ADDR_IMM(src0
, 73, 64, 95, 72, 68)
712 BRW_IA16_ADDR_IMM(dst
, 57, 52, 47, 56, 52)
715 * Fetch a set of contiguous bits from the instruction.
717 * Bits indices range from 0..127; fields may not cross 64-bit boundaries.
719 static inline uint64_t
720 brw_inst_bits(const brw_inst
*inst
, unsigned high
, unsigned low
)
722 /* We assume the field doesn't cross 64-bit boundaries. */
723 const unsigned word
= high
/ 64;
724 assert(word
== low
/ 64);
729 const uint64_t mask
= (~0ull >> (64 - (high
- low
+ 1)));
731 return (inst
->data
[word
] >> low
) & mask
;
735 * Set bits in the instruction, with proper shifting and masking.
737 * Bits indices range from 0..127; fields may not cross 64-bit boundaries.
740 brw_inst_set_bits(brw_inst
*inst
, unsigned high
, unsigned low
, uint64_t value
)
742 const unsigned word
= high
/ 64;
743 assert(word
== low
/ 64);
748 const uint64_t mask
= (~0ull >> (64 - (high
- low
+ 1))) << low
;
750 /* Make sure the supplied value actually fits in the given bitfield. */
751 assert((value
& (mask
>> low
)) == value
);
753 inst
->data
[word
] = (inst
->data
[word
] & ~mask
) | (value
<< low
);
756 #undef BRW_IA16_ADDR_IMM
757 #undef BRW_IA1_ADDR_IMM
770 * Fetch a set of contiguous bits from the compacted instruction.
772 * Bits indices range from 0..63.
774 static inline unsigned
775 brw_compact_inst_bits(const brw_compact_inst
*inst
, unsigned high
, unsigned low
)
777 const uint64_t mask
= (1ull << (high
- low
+ 1)) - 1;
779 return (inst
->data
>> low
) & mask
;
783 * Set bits in the compacted instruction.
785 * Bits indices range from 0..63.
788 brw_compact_inst_set_bits(brw_compact_inst
*inst
, unsigned high
, unsigned low
,
791 const uint64_t mask
= ((1ull << (high
- low
+ 1)) - 1) << low
;
793 /* Make sure the supplied value actually fits in the given bitfield. */
794 assert((value
& (mask
>> low
)) == value
);
796 inst
->data
= (inst
->data
& ~mask
) | (value
<< low
);
799 #define FC(name, high, low, assertions) \
801 brw_compact_inst_set_##name(const struct gen_device_info *devinfo, \
802 brw_compact_inst *inst, unsigned v) \
804 assert(assertions); \
806 brw_compact_inst_set_bits(inst, high, low, v); \
808 static inline unsigned \
809 brw_compact_inst_##name(const struct gen_device_info *devinfo, \
810 const brw_compact_inst *inst) \
812 assert(assertions); \
814 return brw_compact_inst_bits(inst, high, low); \
817 /* A simple macro for fields which stay in the same place on all generations. */
818 #define F(name, high, low) FC(name, high, low, true)
820 F(src1_reg_nr
, 63, 56)
821 F(src0_reg_nr
, 55, 48)
822 F(dst_reg_nr
, 47, 40)
823 F(src1_index
, 39, 35)
824 F(src0_index
, 34, 30)
825 F(cmpt_control
, 29, 29) /* Same location as brw_inst */
826 FC(flag_subreg_nr
, 28, 28, devinfo
->gen
<= 6)
827 F(cond_modifier
, 27, 24) /* Same location as brw_inst */
828 FC(acc_wr_control
, 23, 23, devinfo
->gen
>= 6)
829 FC(mask_control_ex
, 23, 23, devinfo
->is_g4x
|| devinfo
->gen
== 5)
830 F(subreg_index
, 22, 18)
831 F(datatype_index
, 17, 13)
832 F(control_index
, 12, 8)
833 F(debug_control
, 7, 7)
834 F(opcode
, 6, 0) /* Same location as brw_inst */
837 * (Gen8+) Compacted three-source instructions:
840 FC(3src_src2_reg_nr
, 63, 57, devinfo
->gen
>= 8)
841 FC(3src_src1_reg_nr
, 56, 50, devinfo
->gen
>= 8)
842 FC(3src_src0_reg_nr
, 49, 43, devinfo
->gen
>= 8)
843 FC(3src_src2_subreg_nr
, 42, 40, devinfo
->gen
>= 8)
844 FC(3src_src1_subreg_nr
, 39, 37, devinfo
->gen
>= 8)
845 FC(3src_src0_subreg_nr
, 36, 34, devinfo
->gen
>= 8)
846 FC(3src_src2_rep_ctrl
, 33, 33, devinfo
->gen
>= 8)
847 FC(3src_src1_rep_ctrl
, 32, 32, devinfo
->gen
>= 8)
848 FC(3src_saturate
, 31, 31, devinfo
->gen
>= 8)
849 FC(3src_debug_control
, 30, 30, devinfo
->gen
>= 8)
850 FC(3src_cmpt_control
, 29, 29, devinfo
->gen
>= 8)
851 FC(3src_src0_rep_ctrl
, 28, 28, devinfo
->gen
>= 8)
853 FC(3src_dst_reg_nr
, 18, 12, devinfo
->gen
>= 8)
854 FC(3src_source_index
, 11, 10, devinfo
->gen
>= 8)
855 FC(3src_control_index
, 9, 8, devinfo
->gen
>= 8)
856 /* Bit 7 is Reserved (for future Opcode expansion) */
857 FC(3src_opcode
, 6, 0, devinfo
->gen
>= 8)