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intel/eu/gen12: Add sanity-check asserts to brw_inst_bits() and brw_inst_set_bits().
[mesa.git] / src / intel / compiler / brw_inst.h
1 /*
2 * Copyright © 2014 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 */
23
24 /**
25 * @file brw_inst.h
26 *
27 * A representation of i965 EU assembly instructions, with helper methods to
28 * get and set various fields. This is the actual hardware format.
29 */
30
31 #ifndef BRW_INST_H
32 #define BRW_INST_H
33
34 #include <assert.h>
35 #include <stdint.h>
36
37 #include "brw_eu_defines.h"
38 #include "brw_reg_type.h"
39 #include "dev/gen_device_info.h"
40
41 #ifdef __cplusplus
42 extern "C" {
43 #endif
44
45 /* brw_context.h has a forward declaration of brw_inst, so name the struct. */
46 typedef struct brw_inst {
47 uint64_t data[2];
48 } brw_inst;
49
50 static inline uint64_t brw_inst_bits(const brw_inst *inst,
51 unsigned high, unsigned low);
52 static inline void brw_inst_set_bits(brw_inst *inst,
53 unsigned high, unsigned low,
54 uint64_t value);
55
56 #define FC(name, hi4, lo4, hi12, lo12, assertions) \
57 static inline void \
58 brw_inst_set_##name(const struct gen_device_info *devinfo, \
59 brw_inst *inst, uint64_t v) \
60 { \
61 assert(assertions); \
62 if (devinfo->gen >= 12) \
63 brw_inst_set_bits(inst, hi12, lo12, v); \
64 else \
65 brw_inst_set_bits(inst, hi4, lo4, v); \
66 } \
67 static inline uint64_t \
68 brw_inst_##name(const struct gen_device_info *devinfo, \
69 const brw_inst *inst) \
70 { \
71 assert(assertions); \
72 if (devinfo->gen >= 12) \
73 return brw_inst_bits(inst, hi12, lo12); \
74 else \
75 return brw_inst_bits(inst, hi4, lo4); \
76 }
77
78 /* A simple macro for fields which stay in the same place on all generations,
79 * except for Gen12!
80 */
81 #define F(name, hi4, lo4, hi12, lo12) FC(name, hi4, lo4, hi12, lo12, true)
82
83 #define BOUNDS(hi4, lo4, hi45, lo45, hi5, lo5, hi6, lo6, \
84 hi7, lo7, hi8, lo8, hi12, lo12) \
85 unsigned high, low; \
86 if (devinfo->gen >= 12) { \
87 high = hi12; low = lo12; \
88 } else if (devinfo->gen >= 8) { \
89 high = hi8; low = lo8; \
90 } else if (devinfo->gen >= 7) { \
91 high = hi7; low = lo7; \
92 } else if (devinfo->gen >= 6) { \
93 high = hi6; low = lo6; \
94 } else if (devinfo->gen >= 5) { \
95 high = hi5; low = lo5; \
96 } else if (devinfo->is_g4x) { \
97 high = hi45; low = lo45; \
98 } else { \
99 high = hi4; low = lo4; \
100 } \
101 assert(((int) high) != -1 && ((int) low) != -1);
102
103 /* A general macro for cases where the field has moved to several different
104 * bit locations across generations. GCC appears to combine cases where the
105 * bits are identical, removing some of the inefficiency.
106 */
107 #define FF(name, hi4, lo4, hi45, lo45, hi5, lo5, hi6, lo6, \
108 hi7, lo7, hi8, lo8, hi12, lo12) \
109 static inline void \
110 brw_inst_set_##name(const struct gen_device_info *devinfo, \
111 brw_inst *inst, uint64_t value) \
112 { \
113 BOUNDS(hi4, lo4, hi45, lo45, hi5, lo5, hi6, lo6, \
114 hi7, lo7, hi8, lo8, hi12, lo12) \
115 brw_inst_set_bits(inst, high, low, value); \
116 } \
117 static inline uint64_t \
118 brw_inst_##name(const struct gen_device_info *devinfo, const brw_inst *inst) \
119 { \
120 BOUNDS(hi4, lo4, hi45, lo45, hi5, lo5, hi6, lo6, \
121 hi7, lo7, hi8, lo8, hi12, lo12) \
122 return brw_inst_bits(inst, high, low); \
123 }
124
125 /* A macro for fields which moved as of Gen8+. */
126 #define F8(name, gen4_high, gen4_low, gen8_high, gen8_low, \
127 gen12_high, gen12_low) \
128 FF(name, \
129 /* 4: */ gen4_high, gen4_low, \
130 /* 4.5: */ gen4_high, gen4_low, \
131 /* 5: */ gen4_high, gen4_low, \
132 /* 6: */ gen4_high, gen4_low, \
133 /* 7: */ gen4_high, gen4_low, \
134 /* 8: */ gen8_high, gen8_low, \
135 /* 12: */ gen12_high, gen12_low);
136
137 /* Macro for fields that gained extra discontiguous MSBs in Gen12 (specified
138 * by hi12ex-lo12ex).
139 */
140 #define FFDC(name, hi4, lo4, hi45, lo45, hi5, lo5, hi6, lo6, \
141 hi7, lo7, hi8, lo8, hi12ex, lo12ex, hi12, lo12, assertions) \
142 static inline void \
143 brw_inst_set_##name(const struct gen_device_info *devinfo, \
144 brw_inst *inst, uint64_t value) \
145 { \
146 assert(assertions); \
147 if (devinfo->gen >= 12) { \
148 const unsigned k = hi12 - lo12 + 1; \
149 if (hi12ex != -1 && lo12ex != -1) \
150 brw_inst_set_bits(inst, hi12ex, lo12ex, value >> k); \
151 brw_inst_set_bits(inst, hi12, lo12, value & ((1ull << k) - 1)); \
152 } else { \
153 BOUNDS(hi4, lo4, hi45, lo45, hi5, lo5, hi6, lo6, \
154 hi7, lo7, hi8, lo8, -1, -1); \
155 brw_inst_set_bits(inst, high, low, value); \
156 } \
157 } \
158 static inline uint64_t \
159 brw_inst_##name(const struct gen_device_info *devinfo, const brw_inst *inst) \
160 { \
161 assert(assertions); \
162 if (devinfo->gen >= 12) { \
163 const unsigned k = hi12 - lo12 + 1; \
164 return (hi12ex == -1 || lo12ex == -1 ? 0 : \
165 brw_inst_bits(inst, hi12ex, lo12ex) << k) | \
166 brw_inst_bits(inst, hi12, lo12); \
167 } else { \
168 BOUNDS(hi4, lo4, hi45, lo45, hi5, lo5, hi6, lo6, \
169 hi7, lo7, hi8, lo8, -1, -1); \
170 return brw_inst_bits(inst, high, low); \
171 } \
172 }
173
174 #define FD(name, hi4, lo4, hi45, lo45, hi5, lo5, hi6, lo6, \
175 hi7, lo7, hi8, lo8, hi12ex, lo12ex, hi12, lo12) \
176 FFDC(name, hi4, lo4, hi45, lo45, hi5, lo5, hi6, lo6, \
177 hi7, lo7, hi8, lo8, hi12ex, lo12ex, hi12, lo12, true)
178
179 /* Macro for fields that didn't move across generations until Gen12, and then
180 * gained extra discontiguous bits.
181 */
182 #define FDC(name, hi4, lo4, hi12ex, lo12ex, hi12, lo12, assertions) \
183 FFDC(name, hi4, lo4, hi4, lo4, hi4, lo4, hi4, lo4, \
184 hi4, lo4, hi4, lo4, hi12ex, lo12ex, hi12, lo12, assertions)
185
186
187 /* Macro for the 2-bit register file field, which on Gen12+ is stored as the
188 * variable length combination of an IsImm (hi12) bit and an additional file
189 * (lo12) bit.
190 */
191 #define FI(name, hi4, lo4, hi8, lo8, hi12, lo12) \
192 static inline void \
193 brw_inst_set_##name(const struct gen_device_info *devinfo, \
194 brw_inst *inst, uint64_t value) \
195 { \
196 if (devinfo->gen >= 12) { \
197 brw_inst_set_bits(inst, hi12, hi12, value >> 1); \
198 if ((value >> 1) == 0) \
199 brw_inst_set_bits(inst, lo12, lo12, value & 1); \
200 } else { \
201 BOUNDS(hi4, lo4, hi4, lo4, hi4, lo4, hi4, lo4, \
202 hi4, lo4, hi8, lo8, -1, -1); \
203 brw_inst_set_bits(inst, high, low, value); \
204 } \
205 } \
206 static inline uint64_t \
207 brw_inst_##name(const struct gen_device_info *devinfo, const brw_inst *inst) \
208 { \
209 if (devinfo->gen >= 12) { \
210 return (brw_inst_bits(inst, hi12, hi12) << 1) | \
211 (brw_inst_bits(inst, hi12, hi12) == 0 ? \
212 brw_inst_bits(inst, lo12, lo12) : 1); \
213 } else { \
214 BOUNDS(hi4, lo4, hi4, lo4, hi4, lo4, hi4, lo4, \
215 hi4, lo4, hi8, lo8, -1, -1); \
216 return brw_inst_bits(inst, high, low); \
217 } \
218 }
219
220 /* Macro for fields that become a constant in Gen12+ not actually represented
221 * in the instruction.
222 */
223 #define FK(name, hi4, lo4, const12) \
224 static inline void \
225 brw_inst_set_##name(const struct gen_device_info *devinfo, \
226 brw_inst *inst, uint64_t v) \
227 { \
228 if (devinfo->gen >= 12) \
229 assert(v == (const12)); \
230 else \
231 brw_inst_set_bits(inst, hi4, lo4, v); \
232 } \
233 static inline uint64_t \
234 brw_inst_##name(const struct gen_device_info *devinfo, \
235 const brw_inst *inst) \
236 { \
237 if (devinfo->gen >= 12) \
238 return (const12); \
239 else \
240 return brw_inst_bits(inst, hi4, lo4); \
241 }
242
243 F(src1_vstride, /* 4+ */ 120, 117, /* 12+ */ -1, -1)
244 F(src1_width, /* 4+ */ 116, 114, /* 12+ */ -1, -1)
245 F(src1_da16_swiz_w, /* 4+ */ 115, 114, /* 12+ */ -1, -1)
246 F(src1_da16_swiz_z, /* 4+ */ 113, 112, /* 12+ */ -1, -1)
247 F(src1_hstride, /* 4+ */ 113, 112, /* 12+ */ -1, -1)
248 F(src1_address_mode, /* 4+ */ 111, 111, /* 12+ */ -1, -1)
249 /** Src1.SrcMod @{ */
250 F(src1_negate, /* 4+ */ 110, 110, /* 12+ */ -1, -1)
251 F(src1_abs, /* 4+ */ 109, 109, /* 12+ */ -1, -1)
252 /** @} */
253 F8(src1_ia_subreg_nr, /* 4+ */ 108, 106, /* 8+ */ 108, 105, /* 12+ */ -1, -1)
254 F(src1_da_reg_nr, /* 4+ */ 108, 101, /* 12+ */ -1, -1)
255 F(src1_da16_subreg_nr, /* 4+ */ 100, 100, /* 12+ */ -1, -1)
256 F(src1_da1_subreg_nr, /* 4+ */ 100, 96, /* 12+ */ -1, -1)
257 F(src1_da16_swiz_y, /* 4+ */ 99, 98, /* 12+ */ -1, -1)
258 F(src1_da16_swiz_x, /* 4+ */ 97, 96, /* 12+ */ -1, -1)
259 F8(src1_reg_hw_type, /* 4+ */ 46, 44, /* 8+ */ 94, 91, /* 12+ */ -1, -1)
260 F8(src1_reg_file, /* 4+ */ 43, 42, /* 8+ */ 90, 89, /* 12+ */ -1, -1)
261 F(src0_vstride, /* 4+ */ 88, 85, /* 12+ */ -1, -1)
262 F(src0_width, /* 4+ */ 84, 82, /* 12+ */ -1, -1)
263 F(src0_da16_swiz_w, /* 4+ */ 83, 82, /* 12+ */ -1, -1)
264 F(src0_da16_swiz_z, /* 4+ */ 81, 80, /* 12+ */ -1, -1)
265 F(src0_hstride, /* 4+ */ 81, 80, /* 12+ */ -1, -1)
266 F(src0_address_mode, /* 4+ */ 79, 79, /* 12+ */ -1, -1)
267 /** Src0.SrcMod @{ */
268 F(src0_negate, /* 4+ */ 78, 78, /* 12+ */ -1, -1)
269 F(src0_abs, /* 4+ */ 77, 77, /* 12+ */ -1, -1)
270 /** @} */
271 F8(src0_ia_subreg_nr, /* 4+ */ 76, 74, /* 8+ */ 76, 73, /* 12+ */ -1, -1)
272 F(src0_da_reg_nr, /* 4+ */ 76, 69, /* 12+ */ -1, -1)
273 F(src0_da16_subreg_nr /* 4+ */ 68, 68, /* 12+ */ -1, -1)
274 F(src0_da1_subreg_nr, /* 4+ */ 68, 64, /* 12+ */ -1, -1)
275 F(src0_da16_swiz_y, /* 4+ */ 67, 66, /* 12+ */ -1, -1)
276 F(src0_da16_swiz_x, /* 4+ */ 65, 64, /* 12+ */ -1, -1)
277 F(dst_address_mode, /* 4+ */ 63, 63, /* 12+ */ -1, -1)
278 F(dst_hstride, /* 4+ */ 62, 61, /* 12+ */ -1, -1)
279 F8(dst_ia_subreg_nr, /* 4+ */ 60, 58, /* 8+ */ 60, 57, /* 12+ */ -1, -1)
280 F(dst_da_reg_nr, /* 4+ */ 60, 53, /* 12+ */ -1, -1)
281 F(dst_da16_subreg_nr, /* 4+ */ 52, 52, /* 12+ */ -1, -1)
282 F(dst_da1_subreg_nr, /* 4+ */ 52, 48, /* 12+ */ -1, -1)
283 F(da16_writemask, /* 4+ */ 51, 48, /* 12+ */ -1, -1) /* Dst.ChanEn */
284 F8(src0_reg_hw_type, /* 4+ */ 41, 39, /* 8+ */ 46, 43, /* 12+ */ -1, -1)
285 F8(src0_reg_file, /* 4+ */ 38, 37, /* 8+ */ 42, 41, /* 12+ */ -1, -1)
286 F8(dst_reg_hw_type, /* 4+ */ 36, 34, /* 8+ */ 40, 37, /* 12+ */ -1, -1)
287 F8(dst_reg_file, /* 4+ */ 33, 32, /* 8+ */ 36, 35, /* 12+ */ -1, -1)
288 F8(mask_control, /* 4+ */ 9, 9, /* 8+ */ 34, 34, /* 12+ */ -1, -1)
289 FF(flag_reg_nr,
290 /* 4-6: doesn't exist */ -1, -1, -1, -1, -1, -1, -1, -1,
291 /* 7: */ 90, 90,
292 /* 8: */ 33, 33,
293 /* 12: */ -1, -1)
294 F8(flag_subreg_nr, /* 4+ */ 89, 89, /* 8+ */ 32, 32, /* 12+ */ -1, -1)
295 F(saturate, /* 4+ */ 31, 31, /* 12+ */ -1, -1)
296 F(debug_control, /* 4+ */ 30, 30, /* 12+ */ -1, -1)
297 F(cmpt_control, /* 4+ */ 29, 29, /* 12+ */ -1, -1)
298 FC(branch_control, /* 4+ */ 28, 28, /* 12+ */ -1, -1, devinfo->gen >= 8)
299 FC(acc_wr_control, /* 4+ */ 28, 28, /* 12+ */ -1, -1, devinfo->gen >= 6)
300 FC(mask_control_ex, /* 4+ */ 28, 28, /* 12+ */ -1, -1, devinfo->is_g4x || devinfo->gen == 5)
301 F(cond_modifier, /* 4+ */ 27, 24, /* 12+ */ -1, -1)
302 FC(math_function, /* 4+ */ 27, 24, /* 12+ */ -1, -1, devinfo->gen >= 6)
303 F(exec_size, /* 4+ */ 23, 21, /* 12+ */ -1, -1)
304 F(pred_inv, /* 4+ */ 20, 20, /* 12+ */ -1, -1)
305 F(pred_control, /* 4+ */ 19, 16, /* 12+ */ -1, -1)
306 F(thread_control, /* 4+ */ 15, 14, /* 12+ */ -1, -1)
307 F(qtr_control, /* 4+ */ 13, 12, /* 12+ */ -1, -1)
308 FF(nib_control,
309 /* 4-6: doesn't exist */ -1, -1, -1, -1, -1, -1, -1, -1,
310 /* 7: */ 47, 47,
311 /* 8: */ 11, 11,
312 /* 12: */ -1, -1)
313 F8(no_dd_check, /* 4+ */ 11, 11, /* 8+ */ 10, 10, /* 12+ */ -1, -1)
314 F8(no_dd_clear, /* 4+ */ 10, 10, /* 8+ */ 9, 9, /* 12+ */ -1, -1)
315 F(access_mode, /* 4+ */ 8, 8, /* 12+ */ -1, -1)
316 /* Bit 7 is Reserved (for future Opcode expansion) */
317 F(hw_opcode, /* 4+ */ 6, 0, /* 12+ */ -1, -1)
318
319 /**
320 * Three-source instructions:
321 * @{
322 */
323 F(3src_src2_reg_nr, /* 4+ */ 125, 118, /* 12+ */ -1, -1) /* same in align1 */
324 F(3src_a16_src2_subreg_nr, /* 4+ */ 117, 115, /* 12+ */ -1, -1) /* Extra discontiguous bit on CHV? */
325 F(3src_a16_src2_swizzle, /* 4+ */ 114, 107, /* 12+ */ -1, -1)
326 F(3src_a16_src2_rep_ctrl, /* 4+ */ 106, 106, /* 12+ */ -1, -1)
327 F(3src_src1_reg_nr, /* 4+ */ 104, 97, /* 12+ */ -1, -1) /* same in align1 */
328 F(3src_a16_src1_subreg_nr, /* 4+ */ 96, 94, /* 12+ */ -1, -1) /* Extra discontiguous bit on CHV? */
329 F(3src_a16_src1_swizzle, /* 4+ */ 93, 86, /* 12+ */ -1, -1)
330 F(3src_a16_src1_rep_ctrl, /* 4+ */ 85, 85, /* 12+ */ -1, -1)
331 F(3src_src0_reg_nr, /* 4+ */ 83, 76, /* 12+ */ -1, -1) /* same in align1 */
332 F(3src_a16_src0_subreg_nr, /* 4+ */ 75, 73, /* 12+ */ -1, -1) /* Extra discontiguous bit on CHV? */
333 F(3src_a16_src0_swizzle, /* 4+ */ 72, 65, /* 12+ */ -1, -1)
334 F(3src_a16_src0_rep_ctrl, /* 4+ */ 64, 64, /* 12+ */ -1, -1)
335 F(3src_dst_reg_nr, /* 4+ */ 63, 56, /* 12+ */ -1, -1) /* same in align1 */
336 F(3src_a16_dst_subreg_nr, /* 4+ */ 55, 53, /* 12+ */ -1, -1)
337 F(3src_a16_dst_writemask, /* 4+ */ 52, 49, /* 12+ */ -1, -1)
338 F8(3src_a16_nib_ctrl, /* 4+ */ 47, 47, /* 8+ */ 11, 11, /* 12+ */ -1, -1) /* only exists on IVB+ */
339 F8(3src_a16_dst_hw_type, /* 4+ */ 45, 44, /* 8+ */ 48, 46, /* 12+ */ -1, -1) /* only exists on IVB+ */
340 F8(3src_a16_src_hw_type, /* 4+ */ 43, 42, /* 8+ */ 45, 43, /* 12+ */ -1, -1)
341 F8(3src_src2_negate, /* 4+ */ 41, 41, /* 8+ */ 42, 42, /* 12+ */ -1, -1)
342 F8(3src_src2_abs, /* 4+ */ 40, 40, /* 8+ */ 41, 41, /* 12+ */ -1, -1)
343 F8(3src_src1_negate, /* 4+ */ 39, 39, /* 8+ */ 40, 40, /* 12+ */ -1, -1)
344 F8(3src_src1_abs, /* 4+ */ 38, 38, /* 8+ */ 39, 39, /* 12+ */ -1, -1)
345 F8(3src_src0_negate, /* 4+ */ 37, 37, /* 8+ */ 38, 38, /* 12+ */ -1, -1)
346 F8(3src_src0_abs, /* 4+ */ 36, 36, /* 8+ */ 37, 37, /* 12+ */ -1, -1)
347 F8(3src_a16_src1_type, /* 4+ */ -1, -1, /* 8+ */ 36, 36, /* 12+ */ -1, -1)
348 F8(3src_a16_src2_type, /* 4+ */ -1, -1, /* 8+ */ 35, 35, /* 12+ */ -1, -1)
349 F8(3src_a16_flag_reg_nr, /* 4+ */ 34, 34, /* 8+ */ 33, 33, /* 12+ */ -1, -1)
350 F8(3src_a16_flag_subreg_nr,/* 4+ */ 33, 33, /* 8+ */ 32, 32, /* 12+ */ -1, -1)
351 FF(3src_a16_dst_reg_file,
352 /* 4-5: doesn't exist - no 3-source instructions */ -1, -1, -1, -1, -1, -1,
353 /* 6: */ 32, 32,
354 /* 7-8: doesn't exist - no MRFs */ -1, -1, -1, -1,
355 /* 12: */ -1, -1)
356 F(3src_saturate, /* 4+ */ 31, 31, /* 12+ */ -1, -1)
357 F(3src_debug_control, /* 4+ */ 30, 30, /* 12+ */ -1, -1)
358 F(3src_cmpt_control, /* 4+ */ 29, 29, /* 12+ */ -1, -1)
359 F(3src_acc_wr_control, /* 4+ */ 28, 28, /* 12+ */ -1, -1)
360 F(3src_cond_modifier, /* 4+ */ 27, 24, /* 12+ */ -1, -1)
361 F(3src_exec_size, /* 4+ */ 23, 21, /* 12+ */ -1, -1)
362 F(3src_pred_inv, /* 4+ */ 20, 20, /* 12+ */ -1, -1)
363 F(3src_pred_control, /* 4+ */ 19, 16, /* 12+ */ -1, -1)
364 F(3src_thread_control, /* 4+ */ 15, 14, /* 12+ */ -1, -1)
365 F(3src_qtr_control, /* 4+ */ 13, 12, /* 12+ */ -1, -1)
366 F8(3src_no_dd_check, /* 4+ */ 11, 11, /* 8+ */ 10, 10, /* 12+ */ -1, -1)
367 F8(3src_no_dd_clear, /* 4+ */ 10, 10, /* 8+ */ 9, 9, /* 12+ */ -1, -1)
368 F8(3src_mask_control, /* 4+ */ 9, 9, /* 8+ */ 34, 34, /* 12+ */ -1, -1)
369 F(3src_access_mode, /* 4+ */ 8, 8, /* 12+ */ -1, -1)
370 /* Bit 7 is Reserved (for future Opcode expansion) */
371 F(3src_hw_opcode, /* 4+ */ 6, 0, /* 12+ */ -1, -1)
372 /** @} */
373
374 #define REG_TYPE(reg) \
375 static inline void \
376 brw_inst_set_3src_a16_##reg##_type(const struct gen_device_info *devinfo, \
377 brw_inst *inst, enum brw_reg_type type) \
378 { \
379 unsigned hw_type = brw_reg_type_to_a16_hw_3src_type(devinfo, type); \
380 brw_inst_set_3src_a16_##reg##_hw_type(devinfo, inst, hw_type); \
381 } \
382 \
383 static inline enum brw_reg_type \
384 brw_inst_3src_a16_##reg##_type(const struct gen_device_info *devinfo, \
385 const brw_inst *inst) \
386 { \
387 unsigned hw_type = brw_inst_3src_a16_##reg##_hw_type(devinfo, inst); \
388 return brw_a16_hw_3src_type_to_reg_type(devinfo, hw_type); \
389 }
390
391 REG_TYPE(dst)
392 REG_TYPE(src)
393 #undef REG_TYPE
394
395 /**
396 * Three-source align1 instructions:
397 * @{
398 */
399 /* Reserved 127:126 */
400 /* src2_reg_nr same in align16 */
401 FC(3src_a1_src2_subreg_nr, /* 4+ */ 117, 113, /* 12+ */ -1, -1, devinfo->gen >= 10)
402 FC(3src_a1_src2_hstride, /* 4+ */ 112, 111, /* 12+ */ -1, -1, devinfo->gen >= 10)
403 /* Reserved 110:109. src2 vstride is an implied parameter */
404 FC(3src_a1_src2_hw_type, /* 4+ */ 108, 106, /* 12+ */ -1, -1, devinfo->gen >= 10)
405 /* Reserved 105 */
406 /* src1_reg_nr same in align16 */
407 FC(3src_a1_src1_subreg_nr, /* 4+ */ 96, 92, /* 12+ */ -1, -1, devinfo->gen >= 10)
408 FC(3src_a1_src1_hstride, /* 4+ */ 91, 90, /* 12+ */ -1, -1, devinfo->gen >= 10)
409 FC(3src_a1_src1_vstride, /* 4+ */ 89, 88, /* 12+ */ -1, -1, devinfo->gen >= 10)
410 FC(3src_a1_src1_hw_type, /* 4+ */ 87, 85, /* 12+ */ -1, -1, devinfo->gen >= 10)
411 /* Reserved 84 */
412 /* src0_reg_nr same in align16 */
413 FC(3src_a1_src0_subreg_nr, /* 4+ */ 75, 71, /* 12+ */ -1, -1, devinfo->gen >= 10)
414 FC(3src_a1_src0_hstride, /* 4+ */ 70, 69, /* 12+ */ -1, -1, devinfo->gen >= 10)
415 FC(3src_a1_src0_vstride, /* 4+ */ 68, 67, /* 12+ */ -1, -1, devinfo->gen >= 10)
416 FC(3src_a1_src0_hw_type, /* 4+ */ 66, 64, /* 12+ */ -1, -1, devinfo->gen >= 10)
417 /* dst_reg_nr same in align16 */
418 FC(3src_a1_dst_subreg_nr, /* 4+ */ 55, 54, /* 12+ */ -1, -1, devinfo->gen >= 10)
419 FC(3src_a1_special_acc, /* 4+ */ 55, 52, /* 12+ */ -1, -1, devinfo->gen >= 10) /* aliases dst_subreg_nr */
420 /* Reserved 51:50 */
421 FC(3src_a1_dst_hstride, /* 4+ */ 49, 49, /* 12+ */ -1, -1, devinfo->gen >= 10)
422 FC(3src_a1_dst_hw_type, /* 4+ */ 48, 46, /* 12+ */ -1, -1, devinfo->gen >= 10)
423 FC(3src_a1_src2_reg_file, /* 4+ */ 45, 45, /* 12+ */ -1, -1, devinfo->gen >= 10)
424 FC(3src_a1_src1_reg_file, /* 4+ */ 44, 44, /* 12+ */ -1, -1, devinfo->gen >= 10)
425 FC(3src_a1_src0_reg_file, /* 4+ */ 43, 43, /* 12+ */ -1, -1, devinfo->gen >= 10)
426 /* Source Modifier fields same in align16 */
427 FC(3src_a1_dst_reg_file, /* 4+ */ 36, 36, /* 12+ */ -1, -1, devinfo->gen >= 10)
428 FC(3src_a1_exec_type, /* 4+ */ 35, 35, /* 12+ */ -1, -1, devinfo->gen >= 10)
429 /* Fields below this same in align16 */
430 /** @} */
431
432 #define REG_TYPE(reg) \
433 static inline void \
434 brw_inst_set_3src_a1_##reg##_type(const struct gen_device_info *devinfo, \
435 brw_inst *inst, enum brw_reg_type type) \
436 { \
437 UNUSED enum gen10_align1_3src_exec_type exec_type = \
438 (enum gen10_align1_3src_exec_type) brw_inst_3src_a1_exec_type(devinfo, \
439 inst); \
440 if (brw_reg_type_is_floating_point(type)) { \
441 assert(exec_type == BRW_ALIGN1_3SRC_EXEC_TYPE_FLOAT); \
442 } else { \
443 assert(exec_type == BRW_ALIGN1_3SRC_EXEC_TYPE_INT); \
444 } \
445 unsigned hw_type = brw_reg_type_to_a1_hw_3src_type(devinfo, type); \
446 brw_inst_set_3src_a1_##reg##_hw_type(devinfo, inst, hw_type); \
447 } \
448 \
449 static inline enum brw_reg_type \
450 brw_inst_3src_a1_##reg##_type(const struct gen_device_info *devinfo, \
451 const brw_inst *inst) \
452 { \
453 enum gen10_align1_3src_exec_type exec_type = \
454 (enum gen10_align1_3src_exec_type) brw_inst_3src_a1_exec_type(devinfo, \
455 inst); \
456 unsigned hw_type = brw_inst_3src_a1_##reg##_hw_type(devinfo, inst); \
457 return brw_a1_hw_3src_type_to_reg_type(devinfo, hw_type, exec_type); \
458 }
459
460 REG_TYPE(dst)
461 REG_TYPE(src0)
462 REG_TYPE(src1)
463 REG_TYPE(src2)
464 #undef REG_TYPE
465
466 /**
467 * Three-source align1 instruction immediates:
468 * @{
469 */
470 static inline uint16_t
471 brw_inst_3src_a1_src0_imm(ASSERTED const struct gen_device_info *devinfo,
472 const brw_inst *insn)
473 {
474 assert(devinfo->gen >= 10);
475 return brw_inst_bits(insn, 82, 67);
476 }
477
478 static inline uint16_t
479 brw_inst_3src_a1_src2_imm(ASSERTED const struct gen_device_info *devinfo,
480 const brw_inst *insn)
481 {
482 assert(devinfo->gen >= 10);
483 return brw_inst_bits(insn, 124, 109);
484 }
485
486 static inline void
487 brw_inst_set_3src_a1_src0_imm(ASSERTED const struct gen_device_info *devinfo,
488 brw_inst *insn, uint16_t value)
489 {
490 assert(devinfo->gen >= 10);
491 brw_inst_set_bits(insn, 82, 67, value);
492 }
493
494 static inline void
495 brw_inst_set_3src_a1_src2_imm(ASSERTED const struct gen_device_info *devinfo,
496 brw_inst *insn, uint16_t value)
497 {
498 assert(devinfo->gen >= 10);
499 brw_inst_set_bits(insn, 124, 109, value);
500 }
501 /** @} */
502
503 /**
504 * Flow control instruction bits:
505 * @{
506 */
507 static inline void
508 brw_inst_set_uip(const struct gen_device_info *devinfo,
509 brw_inst *inst, int32_t value)
510 {
511 assert(devinfo->gen >= 6);
512
513 if (devinfo->gen >= 8) {
514 brw_inst_set_bits(inst, 95, 64, (uint32_t)value);
515 } else {
516 assert(value <= (1 << 16) - 1);
517 assert(value > -(1 << 16));
518 brw_inst_set_bits(inst, 127, 112, (uint16_t)value);
519 }
520 }
521
522 static inline int32_t
523 brw_inst_uip(const struct gen_device_info *devinfo, const brw_inst *inst)
524 {
525 assert(devinfo->gen >= 6);
526
527 if (devinfo->gen >= 8) {
528 return brw_inst_bits(inst, 95, 64);
529 } else {
530 return (int16_t)brw_inst_bits(inst, 127, 112);
531 }
532 }
533
534 static inline void
535 brw_inst_set_jip(const struct gen_device_info *devinfo,
536 brw_inst *inst, int32_t value)
537 {
538 assert(devinfo->gen >= 6);
539
540 if (devinfo->gen >= 8) {
541 brw_inst_set_bits(inst, 127, 96, (uint32_t)value);
542 } else {
543 assert(value <= (1 << 15) - 1);
544 assert(value >= -(1 << 15));
545 brw_inst_set_bits(inst, 111, 96, (uint16_t)value);
546 }
547 }
548
549 static inline int32_t
550 brw_inst_jip(const struct gen_device_info *devinfo, const brw_inst *inst)
551 {
552 assert(devinfo->gen >= 6);
553
554 if (devinfo->gen >= 8) {
555 return brw_inst_bits(inst, 127, 96);
556 } else {
557 return (int16_t)brw_inst_bits(inst, 111, 96);
558 }
559 }
560
561 /** Like FC, but using int16_t to handle negative jump targets. */
562 #define FJ(name, high, low, assertions) \
563 static inline void \
564 brw_inst_set_##name(const struct gen_device_info *devinfo, brw_inst *inst, int16_t v) \
565 { \
566 assert(assertions); \
567 (void) devinfo; \
568 brw_inst_set_bits(inst, high, low, (uint16_t) v); \
569 } \
570 static inline int16_t \
571 brw_inst_##name(const struct gen_device_info *devinfo, const brw_inst *inst) \
572 { \
573 assert(assertions); \
574 (void) devinfo; \
575 return brw_inst_bits(inst, high, low); \
576 }
577
578 FJ(gen6_jump_count, 63, 48, devinfo->gen == 6)
579 FJ(gen4_jump_count, 111, 96, devinfo->gen < 6)
580 FC(gen4_pop_count, /* 4+ */ 115, 112, /* 12+ */ -1, -1, devinfo->gen < 6)
581 /** @} */
582
583 /**
584 * SEND instructions:
585 * @{
586 */
587 FC(send_ex_desc_ia_subreg_nr, /* 4+ */ 82, 80, /* 12+ */ -1, -1, devinfo->gen >= 9)
588 FC(send_src0_address_mode, /* 4+ */ 79, 79, /* 12+ */ -1, -1, devinfo->gen >= 9)
589 FC(send_sel_reg32_desc, /* 4+ */ 77, 77, /* 12+ */ -1, -1, devinfo->gen >= 9)
590 FC(send_sel_reg32_ex_desc, /* 4+ */ 61, 61, /* 12+ */ -1, -1, devinfo->gen >= 9)
591 FC(send_src1_reg_nr, /* 4+ */ 51, 44, /* 12+ */ -1, -1, devinfo->gen >= 9)
592 FC(send_src1_reg_file, /* 4+ */ 36, 36, /* 12+ */ -1, -1, devinfo->gen >= 9)
593 FC(send_dst_reg_file, /* 4+ */ 35, 35, /* 12+ */ -1, -1, devinfo->gen >= 9)
594 /** @} */
595
596 /* Message descriptor bits */
597 #define MD(x) ((x) + 96)
598
599 /**
600 * Set the SEND(C) message descriptor immediate.
601 *
602 * This doesn't include the SFID nor the EOT field that were considered to be
603 * part of the message descriptor by ancient versions of the BSpec, because
604 * they are present in the instruction even if the message descriptor is
605 * provided indirectly in the address register, so we want to specify them
606 * separately.
607 */
608 static inline void
609 brw_inst_set_send_desc(const struct gen_device_info *devinfo,
610 brw_inst *inst, uint32_t value)
611 {
612 if (devinfo->gen >= 9) {
613 brw_inst_set_bits(inst, 126, 96, value);
614 assert(value >> 31 == 0);
615 } else if (devinfo->gen >= 5) {
616 brw_inst_set_bits(inst, 124, 96, value);
617 assert(value >> 29 == 0);
618 } else {
619 brw_inst_set_bits(inst, 119, 96, value);
620 assert(value >> 24 == 0);
621 }
622 }
623
624 /**
625 * Get the SEND(C) message descriptor immediate.
626 *
627 * \sa brw_inst_set_send_desc().
628 */
629 static inline uint32_t
630 brw_inst_send_desc(const struct gen_device_info *devinfo, const brw_inst *inst)
631 {
632 if (devinfo->gen >= 9)
633 return brw_inst_bits(inst, 126, 96);
634 else if (devinfo->gen >= 5)
635 return brw_inst_bits(inst, 124, 96);
636 else
637 return brw_inst_bits(inst, 119, 96);
638 }
639
640 /**
641 * Set the SEND(C) message extended descriptor immediate.
642 *
643 * This doesn't include the SFID nor the EOT field that were considered to be
644 * part of the extended message descriptor by some versions of the BSpec,
645 * because they are present in the instruction even if the extended message
646 * descriptor is provided indirectly in a register, so we want to specify them
647 * separately.
648 */
649 static inline void
650 brw_inst_set_send_ex_desc(const struct gen_device_info *devinfo,
651 brw_inst *inst, uint32_t value)
652 {
653 assert(devinfo->gen >= 9);
654 brw_inst_set_bits(inst, 94, 91, GET_BITS(value, 31, 28));
655 brw_inst_set_bits(inst, 88, 85, GET_BITS(value, 27, 24));
656 brw_inst_set_bits(inst, 83, 80, GET_BITS(value, 23, 20));
657 brw_inst_set_bits(inst, 67, 64, GET_BITS(value, 19, 16));
658 assert(GET_BITS(value, 15, 0) == 0);
659 }
660
661 /**
662 * Set the SENDS(C) message extended descriptor immediate.
663 *
664 * This doesn't include the SFID nor the EOT field that were considered to be
665 * part of the extended message descriptor by some versions of the BSpec,
666 * because they are present in the instruction even if the extended message
667 * descriptor is provided indirectly in a register, so we want to specify them
668 * separately.
669 */
670 static inline void
671 brw_inst_set_sends_ex_desc(const struct gen_device_info *devinfo,
672 brw_inst *inst, uint32_t value)
673 {
674 brw_inst_set_bits(inst, 95, 80, GET_BITS(value, 31, 16));
675 assert(GET_BITS(value, 15, 10) == 0);
676 brw_inst_set_bits(inst, 67, 64, GET_BITS(value, 9, 6));
677 assert(GET_BITS(value, 5, 0) == 0);
678 }
679
680 /**
681 * Get the SEND(C) message extended descriptor immediate.
682 *
683 * \sa brw_inst_set_send_ex_desc().
684 */
685 static inline uint32_t
686 brw_inst_send_ex_desc(const struct gen_device_info *devinfo,
687 const brw_inst *inst)
688 {
689 assert(devinfo->gen >= 9);
690 return (brw_inst_bits(inst, 94, 91) << 28 |
691 brw_inst_bits(inst, 88, 85) << 24 |
692 brw_inst_bits(inst, 83, 80) << 20 |
693 brw_inst_bits(inst, 67, 64) << 16);
694 }
695
696 /**
697 * Get the SENDS(C) message extended descriptor immediate.
698 *
699 * \sa brw_inst_set_send_ex_desc().
700 */
701 static inline uint32_t
702 brw_inst_sends_ex_desc(const struct gen_device_info *devinfo,
703 const brw_inst *inst)
704 {
705 return (brw_inst_bits(inst, 95, 80) << 16 |
706 brw_inst_bits(inst, 67, 64) << 6);
707 }
708
709 /**
710 * Fields for SEND messages:
711 * @{
712 */
713 F(eot, /* 4+ */ 127, 127, /* 12+ */ -1, -1)
714 FF(mlen,
715 /* 4: */ 119, 116,
716 /* 4.5: */ 119, 116,
717 /* 5: */ 124, 121,
718 /* 6: */ 124, 121,
719 /* 7: */ 124, 121,
720 /* 8: */ 124, 121,
721 /* 12: */ -1, -1);
722 FF(rlen,
723 /* 4: */ 115, 112,
724 /* 4.5: */ 115, 112,
725 /* 5: */ 120, 116,
726 /* 6: */ 120, 116,
727 /* 7: */ 120, 116,
728 /* 8: */ 120, 116,
729 /* 12: */ -1, -1);
730 FF(header_present,
731 /* 4: doesn't exist */ -1, -1, -1, -1,
732 /* 5: */ 115, 115,
733 /* 6: */ 115, 115,
734 /* 7: */ 115, 115,
735 /* 8: */ 115, 115,
736 /* 12: */ -1, -1)
737 F(gateway_notify, /* 4+ */ MD(16), MD(15), /* 12+ */ -1, -1)
738 FF(function_control,
739 /* 4: */ 111, 96,
740 /* 4.5: */ 111, 96,
741 /* 5: */ 114, 96,
742 /* 6: */ 114, 96,
743 /* 7: */ 114, 96,
744 /* 8: */ 114, 96,
745 /* 12: */ -1, -1)
746 FF(gateway_subfuncid,
747 /* 4: */ MD(1), MD(0),
748 /* 4.5: */ MD(1), MD(0),
749 /* 5: */ MD(1), MD(0), /* 2:0, but bit 2 is reserved MBZ */
750 /* 6: */ MD(2), MD(0),
751 /* 7: */ MD(2), MD(0),
752 /* 8: */ MD(2), MD(0),
753 /* 12: */ -1, -1)
754 FF(sfid,
755 /* 4: */ 123, 120, /* called msg_target */
756 /* 4.5 */ 123, 120,
757 /* 5: */ 95, 92,
758 /* 6: */ 27, 24,
759 /* 7: */ 27, 24,
760 /* 8: */ 27, 24,
761 /* 12: */ -1, -1)
762 FF(null_rt,
763 /* 4-7: */ -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
764 /* 8: */ 80, 80,
765 /* 12: */ -1, -1) /* actually only Gen11+ */
766 FC(base_mrf, /* 4+ */ 27, 24, /* 12+ */ -1, -1, devinfo->gen < 6);
767 /** @} */
768
769 /**
770 * URB message function control bits:
771 * @{
772 */
773 FF(urb_per_slot_offset,
774 /* 4-6: */ -1, -1, -1, -1, -1, -1, -1, -1,
775 /* 7: */ MD(16), MD(16),
776 /* 8: */ MD(17), MD(17),
777 /* 12: */ -1, -1)
778 FC(urb_channel_mask_present, /* 4+ */ MD(15), MD(15), /* 12+ */ -1, -1, devinfo->gen >= 8)
779 FC(urb_complete, /* 4+ */ MD(15), MD(15), /* 12+ */ -1, -1, devinfo->gen < 8)
780 FC(urb_used, /* 4+ */ MD(14), MD(14), /* 12+ */ -1, -1, devinfo->gen < 7)
781 FC(urb_allocate, /* 4+ */ MD(13), MD(13), /* 12+ */ -1, -1, devinfo->gen < 7)
782 FF(urb_swizzle_control,
783 /* 4: */ MD(11), MD(10),
784 /* 4.5: */ MD(11), MD(10),
785 /* 5: */ MD(11), MD(10),
786 /* 6: */ MD(11), MD(10),
787 /* 7: */ MD(14), MD(14),
788 /* 8: */ MD(15), MD(15),
789 /* 12: */ -1, -1)
790 FF(urb_global_offset,
791 /* 4: */ MD( 9), MD(4),
792 /* 4.5: */ MD( 9), MD(4),
793 /* 5: */ MD( 9), MD(4),
794 /* 6: */ MD( 9), MD(4),
795 /* 7: */ MD(13), MD(3),
796 /* 8: */ MD(14), MD(4),
797 /* 12: */ -1, -1)
798 FF(urb_opcode,
799 /* 4: */ MD( 3), MD(0),
800 /* 4.5: */ MD( 3), MD(0),
801 /* 5: */ MD( 3), MD(0),
802 /* 6: */ MD( 3), MD(0),
803 /* 7: */ MD( 2), MD(0),
804 /* 8: */ MD( 3), MD(0),
805 /* 12: */ -1, -1)
806 /** @} */
807
808 /**
809 * Gen4-5 math messages:
810 * @{
811 */
812 FC(math_msg_data_type, /* 4+ */ MD(7), MD(7), /* 12+ */ -1, -1, devinfo->gen < 6)
813 FC(math_msg_saturate, /* 4+ */ MD(6), MD(6), /* 12+ */ -1, -1, devinfo->gen < 6)
814 FC(math_msg_precision, /* 4+ */ MD(5), MD(5), /* 12+ */ -1, -1, devinfo->gen < 6)
815 FC(math_msg_signed_int, /* 4+ */ MD(4), MD(4), /* 12+ */ -1, -1, devinfo->gen < 6)
816 FC(math_msg_function, /* 4+ */ MD(3), MD(0), /* 12+ */ -1, -1, devinfo->gen < 6)
817 /** @} */
818
819 /**
820 * Sampler message function control bits:
821 * @{
822 */
823 FF(sampler_simd_mode,
824 /* 4: doesn't exist */ -1, -1, -1, -1,
825 /* 5: */ MD(17), MD(16),
826 /* 6: */ MD(17), MD(16),
827 /* 7: */ MD(18), MD(17),
828 /* 8: */ MD(18), MD(17),
829 /* 12: */ -1, -1)
830 FF(sampler_msg_type,
831 /* 4: */ MD(15), MD(14),
832 /* 4.5: */ MD(15), MD(12),
833 /* 5: */ MD(15), MD(12),
834 /* 6: */ MD(15), MD(12),
835 /* 7: */ MD(16), MD(12),
836 /* 8: */ MD(16), MD(12),
837 /* 12: */ -1, -1)
838 FC(sampler_return_format, /* 4+ */ MD(13), MD(12), /* 12+ */ -1, -1, devinfo->gen == 4 && !devinfo->is_g4x)
839 F(sampler, /* 4+ */ MD(11), MD(8), /* 12+ */ -1, -1)
840 F(binding_table_index, /* 4+ */ MD( 7), MD(0), /* 12+ */ -1, -1) /* also used by other messages */
841 /** @} */
842
843 /**
844 * Data port message function control bits:
845 * @{
846 */
847 FC(dp_category, /* 4+ */ MD(18), MD(18), /* 12+ */ -1, -1, devinfo->gen >= 7)
848
849 /* Gen4-5 store fields in different bits for read/write messages. */
850 FF(dp_read_msg_type,
851 /* 4: */ MD(13), MD(12),
852 /* 4.5: */ MD(13), MD(11),
853 /* 5: */ MD(13), MD(11),
854 /* 6: */ MD(16), MD(13),
855 /* 7: */ MD(17), MD(14),
856 /* 8: */ MD(17), MD(14),
857 /* 12: */ -1, -1)
858 FF(dp_write_msg_type,
859 /* 4: */ MD(14), MD(12),
860 /* 4.5: */ MD(14), MD(12),
861 /* 5: */ MD(14), MD(12),
862 /* 6: */ MD(16), MD(13),
863 /* 7: */ MD(17), MD(14),
864 /* 8: */ MD(17), MD(14),
865 /* 12: */ -1, -1)
866 FF(dp_read_msg_control,
867 /* 4: */ MD(11), MD( 8),
868 /* 4.5: */ MD(10), MD( 8),
869 /* 5: */ MD(10), MD( 8),
870 /* 6: */ MD(12), MD( 8),
871 /* 7: */ MD(13), MD( 8),
872 /* 8: */ MD(13), MD( 8),
873 /* 12: */ -1, -1)
874 FF(dp_write_msg_control,
875 /* 4: */ MD(11), MD( 8),
876 /* 4.5: */ MD(11), MD( 8),
877 /* 5: */ MD(11), MD( 8),
878 /* 6: */ MD(12), MD( 8),
879 /* 7: */ MD(13), MD( 8),
880 /* 8: */ MD(13), MD( 8),
881 /* 12: */ -1, -1)
882 FC(dp_read_target_cache, /* 4+ */ MD(15), MD(14), /* 12+ */ -1, -1, devinfo->gen < 6);
883
884 FF(dp_write_commit,
885 /* 4: */ MD(15), MD(15),
886 /* 4.5: */ MD(15), MD(15),
887 /* 5: */ MD(15), MD(15),
888 /* 6: */ MD(17), MD(17),
889 /* 7+: does not exist */ -1, -1, -1, -1,
890 /* 12: */ -1, -1)
891
892 /* Gen6+ use the same bit locations for everything. */
893 FF(dp_msg_type,
894 /* 4-5: use dp_read_msg_type or dp_write_msg_type instead */
895 -1, -1, -1, -1, -1, -1,
896 /* 6: */ MD(16), MD(13),
897 /* 7: */ MD(17), MD(14),
898 /* 8: */ MD(18), MD(14),
899 /* 12: */ -1, -1)
900 FF(dp_msg_control,
901 /* 4: */ MD(11), MD( 8),
902 /* 4.5-5: use dp_read_msg_control or dp_write_msg_control */ -1, -1, -1, -1,
903 /* 6: */ MD(12), MD( 8),
904 /* 7: */ MD(13), MD( 8),
905 /* 8: */ MD(13), MD( 8),
906 /* 12: */ -1, -1)
907 /** @} */
908
909 /**
910 * Scratch message bits (Gen7+):
911 * @{
912 */
913 FC(scratch_read_write, /* 4+ */ MD(17), MD(17), /* 12+ */ -1, -1, devinfo->gen >= 7) /* 0 = read, 1 = write */
914 FC(scratch_type, /* 4+ */ MD(16), MD(16), /* 12+ */ -1, -1, devinfo->gen >= 7) /* 0 = OWord, 1 = DWord */
915 FC(scratch_invalidate_after_read, /* 4+ */ MD(15), MD(15), /* 12+ */ -1, -1, devinfo->gen >= 7)
916 FC(scratch_block_size, /* 4+ */ MD(13), MD(12), /* 12+ */ -1, -1, devinfo->gen >= 7)
917 FC(scratch_addr_offset, /* 4+ */ MD(11), MD( 0), /* 12+ */ -1, -1, devinfo->gen >= 7)
918 /** @} */
919
920 /**
921 * Render Target message function control bits:
922 * @{
923 */
924 FF(rt_last,
925 /* 4: */ MD(11), MD(11),
926 /* 4.5: */ MD(11), MD(11),
927 /* 5: */ MD(11), MD(11),
928 /* 6: */ MD(12), MD(12),
929 /* 7: */ MD(12), MD(12),
930 /* 8: */ MD(12), MD(12),
931 /* 12: */ -1, -1)
932 FC(rt_slot_group, /* 4+ */ MD(11), MD(11), /* 12+ */ -1, -1, devinfo->gen >= 6)
933 F(rt_message_type, /* 4+ */ MD(10), MD( 8), /* 12+ */ -1, -1)
934 /** @} */
935
936 /**
937 * Thread Spawn message function control bits:
938 * @{
939 */
940 F(ts_resource_select, /* 4+ */ MD( 4), MD( 4), /* 12+ */ -1, -1)
941 F(ts_request_type, /* 4+ */ MD( 1), MD( 1), /* 12+ */ -1, -1)
942 F(ts_opcode, /* 4+ */ MD( 0), MD( 0), /* 12+ */ -1, -1)
943 /** @} */
944
945 /**
946 * Pixel Interpolator message function control bits:
947 * @{
948 */
949 F(pi_simd_mode, /* 4+ */ MD(16), MD(16), /* 12+ */ -1, -1)
950 F(pi_nopersp, /* 4+ */ MD(14), MD(14), /* 12+ */ -1, -1)
951 F(pi_message_type, /* 4+ */ MD(13), MD(12), /* 12+ */ -1, -1)
952 F(pi_slot_group, /* 4+ */ MD(11), MD(11), /* 12+ */ -1, -1)
953 F(pi_message_data, /* 4+ */ MD(7), MD(0), /* 12+ */ -1, -1)
954 /** @} */
955
956 /**
957 * Immediates:
958 * @{
959 */
960 static inline int
961 brw_inst_imm_d(const struct gen_device_info *devinfo, const brw_inst *insn)
962 {
963 (void) devinfo;
964 return brw_inst_bits(insn, 127, 96);
965 }
966
967 static inline unsigned
968 brw_inst_imm_ud(const struct gen_device_info *devinfo, const brw_inst *insn)
969 {
970 (void) devinfo;
971 return brw_inst_bits(insn, 127, 96);
972 }
973
974 static inline uint64_t
975 brw_inst_imm_uq(ASSERTED const struct gen_device_info *devinfo,
976 const brw_inst *insn)
977 {
978 assert(devinfo->gen >= 8);
979 return brw_inst_bits(insn, 127, 64);
980 }
981
982 static inline float
983 brw_inst_imm_f(const struct gen_device_info *devinfo, const brw_inst *insn)
984 {
985 union {
986 float f;
987 uint32_t u;
988 } ft;
989 (void) devinfo;
990 ft.u = brw_inst_bits(insn, 127, 96);
991 return ft.f;
992 }
993
994 static inline double
995 brw_inst_imm_df(const struct gen_device_info *devinfo, const brw_inst *insn)
996 {
997 union {
998 double d;
999 uint64_t u;
1000 } dt;
1001 (void) devinfo;
1002 dt.u = brw_inst_bits(insn, 127, 64);
1003 return dt.d;
1004 }
1005
1006 static inline void
1007 brw_inst_set_imm_d(const struct gen_device_info *devinfo,
1008 brw_inst *insn, int value)
1009 {
1010 (void) devinfo;
1011 return brw_inst_set_bits(insn, 127, 96, value);
1012 }
1013
1014 static inline void
1015 brw_inst_set_imm_ud(const struct gen_device_info *devinfo,
1016 brw_inst *insn, unsigned value)
1017 {
1018 (void) devinfo;
1019 return brw_inst_set_bits(insn, 127, 96, value);
1020 }
1021
1022 static inline void
1023 brw_inst_set_imm_f(const struct gen_device_info *devinfo,
1024 brw_inst *insn, float value)
1025 {
1026 union {
1027 float f;
1028 uint32_t u;
1029 } ft;
1030 (void) devinfo;
1031 ft.f = value;
1032 brw_inst_set_bits(insn, 127, 96, ft.u);
1033 }
1034
1035 static inline void
1036 brw_inst_set_imm_df(const struct gen_device_info *devinfo,
1037 brw_inst *insn, double value)
1038 {
1039 union {
1040 double d;
1041 uint64_t u;
1042 } dt;
1043 (void) devinfo;
1044 dt.d = value;
1045 brw_inst_set_bits(insn, 127, 64, dt.u);
1046 }
1047
1048 static inline void
1049 brw_inst_set_imm_uq(const struct gen_device_info *devinfo,
1050 brw_inst *insn, uint64_t value)
1051 {
1052 (void) devinfo;
1053 brw_inst_set_bits(insn, 127, 64, value);
1054 }
1055
1056 /** @} */
1057
1058 #define REG_TYPE(reg) \
1059 static inline void \
1060 brw_inst_set_##reg##_file_type(const struct gen_device_info *devinfo, \
1061 brw_inst *inst, enum brw_reg_file file, \
1062 enum brw_reg_type type) \
1063 { \
1064 assert(file <= BRW_IMMEDIATE_VALUE); \
1065 unsigned hw_type = brw_reg_type_to_hw_type(devinfo, file, type); \
1066 brw_inst_set_##reg##_reg_file(devinfo, inst, file); \
1067 brw_inst_set_##reg##_reg_hw_type(devinfo, inst, hw_type); \
1068 } \
1069 \
1070 static inline enum brw_reg_type \
1071 brw_inst_##reg##_type(const struct gen_device_info *devinfo, \
1072 const brw_inst *inst) \
1073 { \
1074 unsigned file = __builtin_strcmp("dst", #reg) == 0 ? \
1075 (unsigned) BRW_GENERAL_REGISTER_FILE : \
1076 brw_inst_##reg##_reg_file(devinfo, inst); \
1077 unsigned hw_type = brw_inst_##reg##_reg_hw_type(devinfo, inst); \
1078 return brw_hw_type_to_reg_type(devinfo, (enum brw_reg_file)file, hw_type); \
1079 }
1080
1081 REG_TYPE(dst)
1082 REG_TYPE(src0)
1083 REG_TYPE(src1)
1084 #undef REG_TYPE
1085
1086
1087 /* The AddrImm fields are split into two discontiguous sections on Gen8+ */
1088 #define BRW_IA1_ADDR_IMM(reg, g4_high, g4_low, g8_nine, g8_high, g8_low) \
1089 static inline void \
1090 brw_inst_set_##reg##_ia1_addr_imm(const struct gen_device_info *devinfo, \
1091 brw_inst *inst, \
1092 unsigned value) \
1093 { \
1094 assert((value & ~0x3ff) == 0); \
1095 if (devinfo->gen >= 8) { \
1096 brw_inst_set_bits(inst, g8_high, g8_low, value & 0x1ff); \
1097 brw_inst_set_bits(inst, g8_nine, g8_nine, value >> 9); \
1098 } else { \
1099 brw_inst_set_bits(inst, g4_high, g4_low, value); \
1100 } \
1101 } \
1102 static inline unsigned \
1103 brw_inst_##reg##_ia1_addr_imm(const struct gen_device_info *devinfo, \
1104 const brw_inst *inst) \
1105 { \
1106 if (devinfo->gen >= 8) { \
1107 return brw_inst_bits(inst, g8_high, g8_low) | \
1108 (brw_inst_bits(inst, g8_nine, g8_nine) << 9); \
1109 } else { \
1110 return brw_inst_bits(inst, g4_high, g4_low); \
1111 } \
1112 }
1113
1114 /* AddrImm[9:0] for Align1 Indirect Addressing */
1115 /* -Gen 4- ----Gen8---- */
1116 BRW_IA1_ADDR_IMM(src1, 105, 96, 121, 104, 96)
1117 BRW_IA1_ADDR_IMM(src0, 73, 64, 95, 72, 64)
1118 BRW_IA1_ADDR_IMM(dst, 57, 48, 47, 56, 48)
1119
1120 #define BRW_IA16_ADDR_IMM(reg, g4_high, g4_low, g8_nine, g8_high, g8_low) \
1121 static inline void \
1122 brw_inst_set_##reg##_ia16_addr_imm(const struct gen_device_info *devinfo, \
1123 brw_inst *inst, unsigned value) \
1124 { \
1125 assert((value & ~0x3ff) == 0); \
1126 if (devinfo->gen >= 8) { \
1127 assert(GET_BITS(value, 3, 0) == 0); \
1128 brw_inst_set_bits(inst, g8_high, g8_low, GET_BITS(value, 8, 4)); \
1129 brw_inst_set_bits(inst, g8_nine, g8_nine, GET_BITS(value, 9, 9)); \
1130 } else { \
1131 brw_inst_set_bits(inst, g4_high, g4_low, value); \
1132 } \
1133 } \
1134 static inline unsigned \
1135 brw_inst_##reg##_ia16_addr_imm(const struct gen_device_info *devinfo, \
1136 const brw_inst *inst) \
1137 { \
1138 if (devinfo->gen >= 8) { \
1139 return (brw_inst_bits(inst, g8_high, g8_low) << 4) | \
1140 (brw_inst_bits(inst, g8_nine, g8_nine) << 9); \
1141 } else { \
1142 return brw_inst_bits(inst, g4_high, g4_low); \
1143 } \
1144 }
1145
1146 /* AddrImm[9:0] for Align16 Indirect Addressing:
1147 * Compared to Align1, these are missing the low 4 bits.
1148 * -Gen 4- ----Gen8----
1149 */
1150 BRW_IA16_ADDR_IMM(src1, 105, 96, 121, 104, 100)
1151 BRW_IA16_ADDR_IMM(src0, 73, 64, 95, 72, 68)
1152 BRW_IA16_ADDR_IMM(dst, 57, 52, 47, 56, 52)
1153 BRW_IA16_ADDR_IMM(send_src0, -1, -1, 78, 72, 68)
1154 BRW_IA16_ADDR_IMM(send_dst, -1, -1, 62, 56, 52)
1155
1156 /**
1157 * Fetch a set of contiguous bits from the instruction.
1158 *
1159 * Bits indices range from 0..127; fields may not cross 64-bit boundaries.
1160 */
1161 static inline uint64_t
1162 brw_inst_bits(const brw_inst *inst, unsigned high, unsigned low)
1163 {
1164 assert(high >= low);
1165 /* We assume the field doesn't cross 64-bit boundaries. */
1166 const unsigned word = high / 64;
1167 assert(word == low / 64);
1168
1169 high %= 64;
1170 low %= 64;
1171
1172 const uint64_t mask = (~0ull >> (64 - (high - low + 1)));
1173
1174 return (inst->data[word] >> low) & mask;
1175 }
1176
1177 /**
1178 * Set bits in the instruction, with proper shifting and masking.
1179 *
1180 * Bits indices range from 0..127; fields may not cross 64-bit boundaries.
1181 */
1182 static inline void
1183 brw_inst_set_bits(brw_inst *inst, unsigned high, unsigned low, uint64_t value)
1184 {
1185 assert(high >= low);
1186 const unsigned word = high / 64;
1187 assert(word == low / 64);
1188
1189 high %= 64;
1190 low %= 64;
1191
1192 const uint64_t mask = (~0ull >> (64 - (high - low + 1))) << low;
1193
1194 /* Make sure the supplied value actually fits in the given bitfield. */
1195 assert((value & (mask >> low)) == value);
1196
1197 inst->data[word] = (inst->data[word] & ~mask) | (value << low);
1198 }
1199
1200 #undef BRW_IA16_ADDR_IMM
1201 #undef BRW_IA1_ADDR_IMM
1202 #undef MD
1203 #undef F8
1204 #undef FF
1205 #undef BOUNDS
1206 #undef F
1207 #undef FC
1208
1209 typedef struct {
1210 uint64_t data;
1211 } brw_compact_inst;
1212
1213 /**
1214 * Fetch a set of contiguous bits from the compacted instruction.
1215 *
1216 * Bits indices range from 0..63.
1217 */
1218 static inline unsigned
1219 brw_compact_inst_bits(const brw_compact_inst *inst, unsigned high, unsigned low)
1220 {
1221 const uint64_t mask = (1ull << (high - low + 1)) - 1;
1222
1223 return (inst->data >> low) & mask;
1224 }
1225
1226 /**
1227 * Set bits in the compacted instruction.
1228 *
1229 * Bits indices range from 0..63.
1230 */
1231 static inline void
1232 brw_compact_inst_set_bits(brw_compact_inst *inst, unsigned high, unsigned low,
1233 uint64_t value)
1234 {
1235 const uint64_t mask = ((1ull << (high - low + 1)) - 1) << low;
1236
1237 /* Make sure the supplied value actually fits in the given bitfield. */
1238 assert((value & (mask >> low)) == value);
1239
1240 inst->data = (inst->data & ~mask) | (value << low);
1241 }
1242
1243 #define FC(name, high, low, assertions) \
1244 static inline void \
1245 brw_compact_inst_set_##name(const struct gen_device_info *devinfo, \
1246 brw_compact_inst *inst, unsigned v) \
1247 { \
1248 assert(assertions); \
1249 (void) devinfo; \
1250 brw_compact_inst_set_bits(inst, high, low, v); \
1251 } \
1252 static inline unsigned \
1253 brw_compact_inst_##name(const struct gen_device_info *devinfo, \
1254 const brw_compact_inst *inst) \
1255 { \
1256 assert(assertions); \
1257 (void) devinfo; \
1258 return brw_compact_inst_bits(inst, high, low); \
1259 }
1260
1261 /* A simple macro for fields which stay in the same place on all generations. */
1262 #define F(name, high, low) FC(name, high, low, true)
1263
1264 F(src1_reg_nr, 63, 56)
1265 F(src0_reg_nr, 55, 48)
1266 F(dst_reg_nr, 47, 40)
1267 F(src1_index, 39, 35)
1268 F(src0_index, 34, 30)
1269 F(cmpt_control, 29, 29) /* Same location as brw_inst */
1270 FC(flag_subreg_nr, 28, 28, devinfo->gen <= 6)
1271 F(cond_modifier, 27, 24) /* Same location as brw_inst */
1272 FC(acc_wr_control, 23, 23, devinfo->gen >= 6)
1273 FC(mask_control_ex, 23, 23, devinfo->is_g4x || devinfo->gen == 5)
1274 F(subreg_index, 22, 18)
1275 F(datatype_index, 17, 13)
1276 F(control_index, 12, 8)
1277 F(debug_control, 7, 7)
1278 F(hw_opcode, 6, 0) /* Same location as brw_inst */
1279
1280 /**
1281 * (Gen8+) Compacted three-source instructions:
1282 * @{
1283 */
1284 FC(3src_src2_reg_nr, 63, 57, devinfo->gen >= 8)
1285 FC(3src_src1_reg_nr, 56, 50, devinfo->gen >= 8)
1286 FC(3src_src0_reg_nr, 49, 43, devinfo->gen >= 8)
1287 FC(3src_src2_subreg_nr, 42, 40, devinfo->gen >= 8)
1288 FC(3src_src1_subreg_nr, 39, 37, devinfo->gen >= 8)
1289 FC(3src_src0_subreg_nr, 36, 34, devinfo->gen >= 8)
1290 FC(3src_src2_rep_ctrl, 33, 33, devinfo->gen >= 8)
1291 FC(3src_src1_rep_ctrl, 32, 32, devinfo->gen >= 8)
1292 FC(3src_saturate, 31, 31, devinfo->gen >= 8)
1293 FC(3src_debug_control, 30, 30, devinfo->gen >= 8)
1294 FC(3src_cmpt_control, 29, 29, devinfo->gen >= 8)
1295 FC(3src_src0_rep_ctrl, 28, 28, devinfo->gen >= 8)
1296 /* Reserved */
1297 FC(3src_dst_reg_nr, 18, 12, devinfo->gen >= 8)
1298 FC(3src_source_index, 11, 10, devinfo->gen >= 8)
1299 FC(3src_control_index, 9, 8, devinfo->gen >= 8)
1300 /* Bit 7 is Reserved (for future Opcode expansion) */
1301 FC(3src_hw_opcode, 6, 0, devinfo->gen >= 8)
1302 /** @} */
1303
1304 #undef F
1305
1306 #ifdef __cplusplus
1307 }
1308 #endif
1309
1310 #endif