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intel/eu: Split brw_inst ex_desc accessors for SEND(C) vs. SENDS(C).
[mesa.git] / src / intel / compiler / brw_inst.h
1 /*
2 * Copyright © 2014 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 */
23
24 /**
25 * @file brw_inst.h
26 *
27 * A representation of i965 EU assembly instructions, with helper methods to
28 * get and set various fields. This is the actual hardware format.
29 */
30
31 #ifndef BRW_INST_H
32 #define BRW_INST_H
33
34 #include <assert.h>
35 #include <stdint.h>
36
37 #include "brw_eu_defines.h"
38 #include "brw_reg_type.h"
39 #include "dev/gen_device_info.h"
40
41 #ifdef __cplusplus
42 extern "C" {
43 #endif
44
45 /* brw_context.h has a forward declaration of brw_inst, so name the struct. */
46 typedef struct brw_inst {
47 uint64_t data[2];
48 } brw_inst;
49
50 static inline uint64_t brw_inst_bits(const brw_inst *inst,
51 unsigned high, unsigned low);
52 static inline void brw_inst_set_bits(brw_inst *inst,
53 unsigned high, unsigned low,
54 uint64_t value);
55
56 #define FC(name, high, low, assertions) \
57 static inline void \
58 brw_inst_set_##name(const struct gen_device_info *devinfo, \
59 brw_inst *inst, uint64_t v) \
60 { \
61 assert(assertions); \
62 (void) devinfo; \
63 brw_inst_set_bits(inst, high, low, v); \
64 } \
65 static inline uint64_t \
66 brw_inst_##name(const struct gen_device_info *devinfo, \
67 const brw_inst *inst) \
68 { \
69 assert(assertions); \
70 (void) devinfo; \
71 return brw_inst_bits(inst, high, low); \
72 }
73
74 /* A simple macro for fields which stay in the same place on all generations. */
75 #define F(name, high, low) FC(name, high, low, true)
76
77 #define BOUNDS(hi4, lo4, hi45, lo45, hi5, lo5, hi6, lo6, hi7, lo7, hi8, lo8) \
78 unsigned high, low; \
79 if (devinfo->gen >= 8) { \
80 high = hi8; low = lo8; \
81 } else if (devinfo->gen >= 7) { \
82 high = hi7; low = lo7; \
83 } else if (devinfo->gen >= 6) { \
84 high = hi6; low = lo6; \
85 } else if (devinfo->gen >= 5) { \
86 high = hi5; low = lo5; \
87 } else if (devinfo->is_g4x) { \
88 high = hi45; low = lo45; \
89 } else { \
90 high = hi4; low = lo4; \
91 } \
92 assert(((int) high) != -1 && ((int) low) != -1);
93
94 /* A general macro for cases where the field has moved to several different
95 * bit locations across generations. GCC appears to combine cases where the
96 * bits are identical, removing some of the inefficiency.
97 */
98 #define FF(name, hi4, lo4, hi45, lo45, hi5, lo5, hi6, lo6, hi7, lo7, hi8, lo8)\
99 static inline void \
100 brw_inst_set_##name(const struct gen_device_info *devinfo, \
101 brw_inst *inst, uint64_t value) \
102 { \
103 BOUNDS(hi4, lo4, hi45, lo45, hi5, lo5, hi6, lo6, hi7, lo7, hi8, lo8) \
104 brw_inst_set_bits(inst, high, low, value); \
105 } \
106 static inline uint64_t \
107 brw_inst_##name(const struct gen_device_info *devinfo, const brw_inst *inst) \
108 { \
109 BOUNDS(hi4, lo4, hi45, lo45, hi5, lo5, hi6, lo6, hi7, lo7, hi8, lo8) \
110 return brw_inst_bits(inst, high, low); \
111 }
112
113 /* A macro for fields which moved as of Gen8+. */
114 #define F8(name, gen4_high, gen4_low, gen8_high, gen8_low) \
115 FF(name, \
116 /* 4: */ gen4_high, gen4_low, \
117 /* 4.5: */ gen4_high, gen4_low, \
118 /* 5: */ gen4_high, gen4_low, \
119 /* 6: */ gen4_high, gen4_low, \
120 /* 7: */ gen4_high, gen4_low, \
121 /* 8: */ gen8_high, gen8_low);
122
123 F(src1_vstride, 120, 117)
124 F(src1_width, 116, 114)
125 F(src1_da16_swiz_w, 115, 114)
126 F(src1_da16_swiz_z, 113, 112)
127 F(src1_hstride, 113, 112)
128 F(src1_address_mode, 111, 111)
129 /** Src1.SrcMod @{ */
130 F(src1_negate, 110, 110)
131 F(src1_abs, 109, 109)
132 /** @} */
133 F8(src1_ia_subreg_nr, /* 4+ */ 108, 106, /* 8+ */ 108, 105)
134 F(src1_da_reg_nr, 108, 101)
135 F(src1_da16_subreg_nr, 100, 100)
136 F(src1_da1_subreg_nr, 100, 96)
137 F(src1_da16_swiz_y, 99, 98)
138 F(src1_da16_swiz_x, 97, 96)
139 F8(src1_reg_hw_type, /* 4+ */ 46, 44, /* 8+ */ 94, 91)
140 F8(src1_reg_file, /* 4+ */ 43, 42, /* 8+ */ 90, 89)
141 F(src0_vstride, 88, 85)
142 F(src0_width, 84, 82)
143 F(src0_da16_swiz_w, 83, 82)
144 F(src0_da16_swiz_z, 81, 80)
145 F(src0_hstride, 81, 80)
146 F(src0_address_mode, 79, 79)
147 /** Src0.SrcMod @{ */
148 F(src0_negate, 78, 78)
149 F(src0_abs, 77, 77)
150 /** @} */
151 F8(src0_ia_subreg_nr, /* 4+ */ 76, 74, /* 8+ */ 76, 73)
152 F(src0_da_reg_nr, 76, 69)
153 F(src0_da16_subreg_nr, 68, 68)
154 F(src0_da1_subreg_nr, 68, 64)
155 F(src0_da16_swiz_y, 67, 66)
156 F(src0_da16_swiz_x, 65, 64)
157 F(dst_address_mode, 63, 63)
158 F(dst_hstride, 62, 61)
159 F8(dst_ia_subreg_nr, /* 4+ */ 60, 58, /* 8+ */ 60, 57)
160 F(dst_da_reg_nr, 60, 53)
161 F(dst_da16_subreg_nr, 52, 52)
162 F(dst_da1_subreg_nr, 52, 48)
163 F(da16_writemask, 51, 48) /* Dst.ChanEn */
164 F8(src0_reg_hw_type, /* 4+ */ 41, 39, /* 8+ */ 46, 43)
165 F8(src0_reg_file, /* 4+ */ 38, 37, /* 8+ */ 42, 41)
166 F8(dst_reg_hw_type, /* 4+ */ 36, 34, /* 8+ */ 40, 37)
167 F8(dst_reg_file, /* 4+ */ 33, 32, /* 8+ */ 36, 35)
168 F8(mask_control, /* 4+ */ 9, 9, /* 8+ */ 34, 34)
169 FF(flag_reg_nr,
170 /* 4-6: doesn't exist */ -1, -1, -1, -1, -1, -1, -1, -1,
171 /* 7: */ 90, 90,
172 /* 8: */ 33, 33)
173 F8(flag_subreg_nr, /* 4+ */ 89, 89, /* 8+ */ 32, 32)
174 F(saturate, 31, 31)
175 F(debug_control, 30, 30)
176 F(cmpt_control, 29, 29)
177 FC(branch_control, 28, 28, devinfo->gen >= 8)
178 FC(acc_wr_control, 28, 28, devinfo->gen >= 6)
179 FC(mask_control_ex, 28, 28, devinfo->is_g4x || devinfo->gen == 5)
180 F(cond_modifier, 27, 24)
181 FC(math_function, 27, 24, devinfo->gen >= 6)
182 F(exec_size, 23, 21)
183 F(pred_inv, 20, 20)
184 F(pred_control, 19, 16)
185 F(thread_control, 15, 14)
186 F(qtr_control, 13, 12)
187 FF(nib_control,
188 /* 4-6: doesn't exist */ -1, -1, -1, -1, -1, -1, -1, -1,
189 /* 7: */ 47, 47,
190 /* 8: */ 11, 11)
191 F8(no_dd_check, /* 4+ */ 11, 11, /* 8+ */ 10, 10)
192 F8(no_dd_clear, /* 4+ */ 10, 10, /* 8+ */ 9, 9)
193 F(access_mode, 8, 8)
194 /* Bit 7 is Reserved (for future Opcode expansion) */
195 F(opcode, 6, 0)
196
197 /**
198 * Three-source instructions:
199 * @{
200 */
201 F(3src_src2_reg_nr, 125, 118) /* same in align1 */
202 F(3src_a16_src2_subreg_nr, 117, 115) /* Extra discontiguous bit on CHV? */
203 F(3src_a16_src2_swizzle, 114, 107)
204 F(3src_a16_src2_rep_ctrl, 106, 106)
205 F(3src_src1_reg_nr, 104, 97) /* same in align1 */
206 F(3src_a16_src1_subreg_nr, 96, 94) /* Extra discontiguous bit on CHV? */
207 F(3src_a16_src1_swizzle, 93, 86)
208 F(3src_a16_src1_rep_ctrl, 85, 85)
209 F(3src_src0_reg_nr, 83, 76) /* same in align1 */
210 F(3src_a16_src0_subreg_nr, 75, 73) /* Extra discontiguous bit on CHV? */
211 F(3src_a16_src0_swizzle, 72, 65)
212 F(3src_a16_src0_rep_ctrl, 64, 64)
213 F(3src_dst_reg_nr, 63, 56) /* same in align1 */
214 F(3src_a16_dst_subreg_nr, 55, 53)
215 F(3src_a16_dst_writemask, 52, 49)
216 F8(3src_a16_nib_ctrl, 47, 47, 11, 11) /* only exists on IVB+ */
217 F8(3src_a16_dst_hw_type, 45, 44, 48, 46) /* only exists on IVB+ */
218 F8(3src_a16_src_hw_type, 43, 42, 45, 43)
219 F8(3src_src2_negate, 41, 41, 42, 42)
220 F8(3src_src2_abs, 40, 40, 41, 41)
221 F8(3src_src1_negate, 39, 39, 40, 40)
222 F8(3src_src1_abs, 38, 38, 39, 39)
223 F8(3src_src0_negate, 37, 37, 38, 38)
224 F8(3src_src0_abs, 36, 36, 37, 37)
225 F8(3src_a16_src1_type, -1, -1, 36, 36)
226 F8(3src_a16_src2_type, -1, -1, 35, 35)
227 F8(3src_a16_flag_reg_nr, 34, 34, 33, 33)
228 F8(3src_a16_flag_subreg_nr, 33, 33, 32, 32)
229 FF(3src_a16_dst_reg_file,
230 /* 4-5: doesn't exist - no 3-source instructions */ -1, -1, -1, -1, -1, -1,
231 /* 6: */ 32, 32,
232 /* 7-8: doesn't exist - no MRFs */ -1, -1, -1, -1)
233 F(3src_saturate, 31, 31)
234 F(3src_debug_control, 30, 30)
235 F(3src_cmpt_control, 29, 29)
236 F(3src_acc_wr_control, 28, 28)
237 F(3src_cond_modifier, 27, 24)
238 F(3src_exec_size, 23, 21)
239 F(3src_pred_inv, 20, 20)
240 F(3src_pred_control, 19, 16)
241 F(3src_thread_control, 15, 14)
242 F(3src_qtr_control, 13, 12)
243 F8(3src_no_dd_check, 11, 11, 10, 10)
244 F8(3src_no_dd_clear, 10, 10, 9, 9)
245 F8(3src_mask_control, 9, 9, 34, 34)
246 F(3src_access_mode, 8, 8)
247 /* Bit 7 is Reserved (for future Opcode expansion) */
248 F(3src_opcode, 6, 0)
249 /** @} */
250
251 #define REG_TYPE(reg) \
252 static inline void \
253 brw_inst_set_3src_a16_##reg##_type(const struct gen_device_info *devinfo, \
254 brw_inst *inst, enum brw_reg_type type) \
255 { \
256 unsigned hw_type = brw_reg_type_to_a16_hw_3src_type(devinfo, type); \
257 brw_inst_set_3src_a16_##reg##_hw_type(devinfo, inst, hw_type); \
258 } \
259 \
260 static inline enum brw_reg_type \
261 brw_inst_3src_a16_##reg##_type(const struct gen_device_info *devinfo, \
262 const brw_inst *inst) \
263 { \
264 unsigned hw_type = brw_inst_3src_a16_##reg##_hw_type(devinfo, inst); \
265 return brw_a16_hw_3src_type_to_reg_type(devinfo, hw_type); \
266 }
267
268 REG_TYPE(dst)
269 REG_TYPE(src)
270 #undef REG_TYPE
271
272 /**
273 * Three-source align1 instructions:
274 * @{
275 */
276 /* Reserved 127:126 */
277 /* src2_reg_nr same in align16 */
278 FC(3src_a1_src2_subreg_nr, 117, 113, devinfo->gen >= 10)
279 FC(3src_a1_src2_hstride, 112, 111, devinfo->gen >= 10)
280 /* Reserved 110:109. src2 vstride is an implied parameter */
281 FC(3src_a1_src2_hw_type, 108, 106, devinfo->gen >= 10)
282 /* Reserved 105 */
283 /* src1_reg_nr same in align16 */
284 FC(3src_a1_src1_subreg_nr, 96, 92, devinfo->gen >= 10)
285 FC(3src_a1_src1_hstride, 91, 90, devinfo->gen >= 10)
286 FC(3src_a1_src1_vstride, 89, 88, devinfo->gen >= 10)
287 FC(3src_a1_src1_hw_type, 87, 85, devinfo->gen >= 10)
288 /* Reserved 84 */
289 /* src0_reg_nr same in align16 */
290 FC(3src_a1_src0_subreg_nr, 75, 71, devinfo->gen >= 10)
291 FC(3src_a1_src0_hstride, 70, 69, devinfo->gen >= 10)
292 FC(3src_a1_src0_vstride, 68, 67, devinfo->gen >= 10)
293 FC(3src_a1_src0_hw_type, 66, 64, devinfo->gen >= 10)
294 /* dst_reg_nr same in align16 */
295 FC(3src_a1_dst_subreg_nr, 55, 54, devinfo->gen >= 10)
296 FC(3src_a1_special_acc, 55, 52, devinfo->gen >= 10) /* aliases dst_subreg_nr */
297 /* Reserved 51:50 */
298 FC(3src_a1_dst_hstride, 49, 49, devinfo->gen >= 10)
299 FC(3src_a1_dst_hw_type, 48, 46, devinfo->gen >= 10)
300 FC(3src_a1_src2_reg_file, 45, 45, devinfo->gen >= 10)
301 FC(3src_a1_src1_reg_file, 44, 44, devinfo->gen >= 10)
302 FC(3src_a1_src0_reg_file, 43, 43, devinfo->gen >= 10)
303 /* Source Modifier fields same in align16 */
304 FC(3src_a1_dst_reg_file, 36, 36, devinfo->gen >= 10)
305 FC(3src_a1_exec_type, 35, 35, devinfo->gen >= 10)
306 /* Fields below this same in align16 */
307 /** @} */
308
309 #define REG_TYPE(reg) \
310 static inline void \
311 brw_inst_set_3src_a1_##reg##_type(const struct gen_device_info *devinfo, \
312 brw_inst *inst, enum brw_reg_type type) \
313 { \
314 UNUSED enum gen10_align1_3src_exec_type exec_type = \
315 (enum gen10_align1_3src_exec_type) brw_inst_3src_a1_exec_type(devinfo, \
316 inst); \
317 if (brw_reg_type_is_floating_point(type)) { \
318 assert(exec_type == BRW_ALIGN1_3SRC_EXEC_TYPE_FLOAT); \
319 } else { \
320 assert(exec_type == BRW_ALIGN1_3SRC_EXEC_TYPE_INT); \
321 } \
322 unsigned hw_type = brw_reg_type_to_a1_hw_3src_type(devinfo, type); \
323 brw_inst_set_3src_a1_##reg##_hw_type(devinfo, inst, hw_type); \
324 } \
325 \
326 static inline enum brw_reg_type \
327 brw_inst_3src_a1_##reg##_type(const struct gen_device_info *devinfo, \
328 const brw_inst *inst) \
329 { \
330 enum gen10_align1_3src_exec_type exec_type = \
331 (enum gen10_align1_3src_exec_type) brw_inst_3src_a1_exec_type(devinfo, \
332 inst); \
333 unsigned hw_type = brw_inst_3src_a1_##reg##_hw_type(devinfo, inst); \
334 return brw_a1_hw_3src_type_to_reg_type(devinfo, hw_type, exec_type); \
335 }
336
337 REG_TYPE(dst)
338 REG_TYPE(src0)
339 REG_TYPE(src1)
340 REG_TYPE(src2)
341 #undef REG_TYPE
342
343 /**
344 * Three-source align1 instruction immediates:
345 * @{
346 */
347 static inline uint16_t
348 brw_inst_3src_a1_src0_imm(ASSERTED const struct gen_device_info *devinfo,
349 const brw_inst *insn)
350 {
351 assert(devinfo->gen >= 10);
352 return brw_inst_bits(insn, 82, 67);
353 }
354
355 static inline uint16_t
356 brw_inst_3src_a1_src2_imm(ASSERTED const struct gen_device_info *devinfo,
357 const brw_inst *insn)
358 {
359 assert(devinfo->gen >= 10);
360 return brw_inst_bits(insn, 124, 109);
361 }
362
363 static inline void
364 brw_inst_set_3src_a1_src0_imm(ASSERTED const struct gen_device_info *devinfo,
365 brw_inst *insn, uint16_t value)
366 {
367 assert(devinfo->gen >= 10);
368 brw_inst_set_bits(insn, 82, 67, value);
369 }
370
371 static inline void
372 brw_inst_set_3src_a1_src2_imm(ASSERTED const struct gen_device_info *devinfo,
373 brw_inst *insn, uint16_t value)
374 {
375 assert(devinfo->gen >= 10);
376 brw_inst_set_bits(insn, 124, 109, value);
377 }
378 /** @} */
379
380 /**
381 * Flow control instruction bits:
382 * @{
383 */
384 static inline void
385 brw_inst_set_uip(const struct gen_device_info *devinfo,
386 brw_inst *inst, int32_t value)
387 {
388 assert(devinfo->gen >= 6);
389
390 if (devinfo->gen >= 8) {
391 brw_inst_set_bits(inst, 95, 64, (uint32_t)value);
392 } else {
393 assert(value <= (1 << 16) - 1);
394 assert(value > -(1 << 16));
395 brw_inst_set_bits(inst, 127, 112, (uint16_t)value);
396 }
397 }
398
399 static inline int32_t
400 brw_inst_uip(const struct gen_device_info *devinfo, const brw_inst *inst)
401 {
402 assert(devinfo->gen >= 6);
403
404 if (devinfo->gen >= 8) {
405 return brw_inst_bits(inst, 95, 64);
406 } else {
407 return (int16_t)brw_inst_bits(inst, 127, 112);
408 }
409 }
410
411 static inline void
412 brw_inst_set_jip(const struct gen_device_info *devinfo,
413 brw_inst *inst, int32_t value)
414 {
415 assert(devinfo->gen >= 6);
416
417 if (devinfo->gen >= 8) {
418 brw_inst_set_bits(inst, 127, 96, (uint32_t)value);
419 } else {
420 assert(value <= (1 << 15) - 1);
421 assert(value >= -(1 << 15));
422 brw_inst_set_bits(inst, 111, 96, (uint16_t)value);
423 }
424 }
425
426 static inline int32_t
427 brw_inst_jip(const struct gen_device_info *devinfo, const brw_inst *inst)
428 {
429 assert(devinfo->gen >= 6);
430
431 if (devinfo->gen >= 8) {
432 return brw_inst_bits(inst, 127, 96);
433 } else {
434 return (int16_t)brw_inst_bits(inst, 111, 96);
435 }
436 }
437
438 /** Like FC, but using int16_t to handle negative jump targets. */
439 #define FJ(name, high, low, assertions) \
440 static inline void \
441 brw_inst_set_##name(const struct gen_device_info *devinfo, brw_inst *inst, int16_t v) \
442 { \
443 assert(assertions); \
444 (void) devinfo; \
445 brw_inst_set_bits(inst, high, low, (uint16_t) v); \
446 } \
447 static inline int16_t \
448 brw_inst_##name(const struct gen_device_info *devinfo, const brw_inst *inst) \
449 { \
450 assert(assertions); \
451 (void) devinfo; \
452 return brw_inst_bits(inst, high, low); \
453 }
454
455 FJ(gen6_jump_count, 63, 48, devinfo->gen == 6)
456 FJ(gen4_jump_count, 111, 96, devinfo->gen < 6)
457 FC(gen4_pop_count, 115, 112, devinfo->gen < 6)
458 /** @} */
459
460 /**
461 * SEND instructions:
462 * @{
463 */
464 FC(send_ex_desc_ia_subreg_nr, 82, 80, devinfo->gen >= 9)
465 FC(send_src0_address_mode, 79, 79, devinfo->gen >= 9)
466 FC(send_sel_reg32_desc, 77, 77, devinfo->gen >= 9)
467 FC(send_sel_reg32_ex_desc, 61, 61, devinfo->gen >= 9)
468 FC(send_src1_reg_nr, 51, 44, devinfo->gen >= 9)
469 FC(send_src1_reg_file, 36, 36, devinfo->gen >= 9)
470 FC(send_dst_reg_file, 35, 35, devinfo->gen >= 9)
471 /** @} */
472
473 /* Message descriptor bits */
474 #define MD(x) ((x) + 96)
475
476 /**
477 * Set the SEND(C) message descriptor immediate.
478 *
479 * This doesn't include the SFID nor the EOT field that were considered to be
480 * part of the message descriptor by ancient versions of the BSpec, because
481 * they are present in the instruction even if the message descriptor is
482 * provided indirectly in the address register, so we want to specify them
483 * separately.
484 */
485 static inline void
486 brw_inst_set_send_desc(const struct gen_device_info *devinfo,
487 brw_inst *inst, uint32_t value)
488 {
489 if (devinfo->gen >= 9) {
490 brw_inst_set_bits(inst, 126, 96, value);
491 assert(value >> 31 == 0);
492 } else if (devinfo->gen >= 5) {
493 brw_inst_set_bits(inst, 124, 96, value);
494 assert(value >> 29 == 0);
495 } else {
496 brw_inst_set_bits(inst, 119, 96, value);
497 assert(value >> 24 == 0);
498 }
499 }
500
501 /**
502 * Get the SEND(C) message descriptor immediate.
503 *
504 * \sa brw_inst_set_send_desc().
505 */
506 static inline uint32_t
507 brw_inst_send_desc(const struct gen_device_info *devinfo, const brw_inst *inst)
508 {
509 if (devinfo->gen >= 9)
510 return brw_inst_bits(inst, 126, 96);
511 else if (devinfo->gen >= 5)
512 return brw_inst_bits(inst, 124, 96);
513 else
514 return brw_inst_bits(inst, 119, 96);
515 }
516
517 /**
518 * Set the SEND(C) message extended descriptor immediate.
519 *
520 * This doesn't include the SFID nor the EOT field that were considered to be
521 * part of the extended message descriptor by some versions of the BSpec,
522 * because they are present in the instruction even if the extended message
523 * descriptor is provided indirectly in a register, so we want to specify them
524 * separately.
525 */
526 static inline void
527 brw_inst_set_send_ex_desc(const struct gen_device_info *devinfo,
528 brw_inst *inst, uint32_t value)
529 {
530 assert(devinfo->gen >= 9);
531 brw_inst_set_bits(inst, 94, 91, GET_BITS(value, 31, 28));
532 brw_inst_set_bits(inst, 88, 85, GET_BITS(value, 27, 24));
533 brw_inst_set_bits(inst, 83, 80, GET_BITS(value, 23, 20));
534 brw_inst_set_bits(inst, 67, 64, GET_BITS(value, 19, 16));
535 assert(GET_BITS(value, 15, 0) == 0);
536 }
537
538 /**
539 * Set the SENDS(C) message extended descriptor immediate.
540 *
541 * This doesn't include the SFID nor the EOT field that were considered to be
542 * part of the extended message descriptor by some versions of the BSpec,
543 * because they are present in the instruction even if the extended message
544 * descriptor is provided indirectly in a register, so we want to specify them
545 * separately.
546 */
547 static inline void
548 brw_inst_set_sends_ex_desc(const struct gen_device_info *devinfo,
549 brw_inst *inst, uint32_t value)
550 {
551 brw_inst_set_bits(inst, 95, 80, GET_BITS(value, 31, 16));
552 assert(GET_BITS(value, 15, 10) == 0);
553 brw_inst_set_bits(inst, 67, 64, GET_BITS(value, 9, 6));
554 assert(GET_BITS(value, 5, 0) == 0);
555 }
556
557 /**
558 * Get the SEND(C) message extended descriptor immediate.
559 *
560 * \sa brw_inst_set_send_ex_desc().
561 */
562 static inline uint32_t
563 brw_inst_send_ex_desc(const struct gen_device_info *devinfo,
564 const brw_inst *inst)
565 {
566 assert(devinfo->gen >= 9);
567 return (brw_inst_bits(inst, 94, 91) << 28 |
568 brw_inst_bits(inst, 88, 85) << 24 |
569 brw_inst_bits(inst, 83, 80) << 20 |
570 brw_inst_bits(inst, 67, 64) << 16);
571 }
572
573 /**
574 * Get the SENDS(C) message extended descriptor immediate.
575 *
576 * \sa brw_inst_set_send_ex_desc().
577 */
578 static inline uint32_t
579 brw_inst_sends_ex_desc(const struct gen_device_info *devinfo,
580 const brw_inst *inst)
581 {
582 return (brw_inst_bits(inst, 95, 80) << 16 |
583 brw_inst_bits(inst, 67, 64) << 6);
584 }
585
586 /**
587 * Fields for SEND messages:
588 * @{
589 */
590 F(eot, 127, 127)
591 FF(mlen,
592 /* 4: */ 119, 116,
593 /* 4.5: */ 119, 116,
594 /* 5: */ 124, 121,
595 /* 6: */ 124, 121,
596 /* 7: */ 124, 121,
597 /* 8: */ 124, 121);
598 FF(rlen,
599 /* 4: */ 115, 112,
600 /* 4.5: */ 115, 112,
601 /* 5: */ 120, 116,
602 /* 6: */ 120, 116,
603 /* 7: */ 120, 116,
604 /* 8: */ 120, 116);
605 FF(header_present,
606 /* 4: doesn't exist */ -1, -1, -1, -1,
607 /* 5: */ 115, 115,
608 /* 6: */ 115, 115,
609 /* 7: */ 115, 115,
610 /* 8: */ 115, 115)
611 F(gateway_notify, MD(16), MD(15))
612 FF(function_control,
613 /* 4: */ 111, 96,
614 /* 4.5: */ 111, 96,
615 /* 5: */ 114, 96,
616 /* 6: */ 114, 96,
617 /* 7: */ 114, 96,
618 /* 8: */ 114, 96)
619 FF(gateway_subfuncid,
620 /* 4: */ MD(1), MD(0),
621 /* 4.5: */ MD(1), MD(0),
622 /* 5: */ MD(1), MD(0), /* 2:0, but bit 2 is reserved MBZ */
623 /* 6: */ MD(2), MD(0),
624 /* 7: */ MD(2), MD(0),
625 /* 8: */ MD(2), MD(0))
626 FF(sfid,
627 /* 4: */ 123, 120, /* called msg_target */
628 /* 4.5 */ 123, 120,
629 /* 5: */ 95, 92,
630 /* 6: */ 27, 24,
631 /* 7: */ 27, 24,
632 /* 8: */ 27, 24)
633 FF(null_rt,
634 /* 4-7: */ -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
635 /* 8: */ 80, 80) /* actually only Gen11+ */
636 FC(base_mrf, 27, 24, devinfo->gen < 6);
637 /** @} */
638
639 /**
640 * URB message function control bits:
641 * @{
642 */
643 FF(urb_per_slot_offset,
644 /* 4-6: */ -1, -1, -1, -1, -1, -1, -1, -1,
645 /* 7: */ MD(16), MD(16),
646 /* 8: */ MD(17), MD(17))
647 FC(urb_channel_mask_present, MD(15), MD(15), devinfo->gen >= 8)
648 FC(urb_complete, MD(15), MD(15), devinfo->gen < 8)
649 FC(urb_used, MD(14), MD(14), devinfo->gen < 7)
650 FC(urb_allocate, MD(13), MD(13), devinfo->gen < 7)
651 FF(urb_swizzle_control,
652 /* 4: */ MD(11), MD(10),
653 /* 4.5: */ MD(11), MD(10),
654 /* 5: */ MD(11), MD(10),
655 /* 6: */ MD(11), MD(10),
656 /* 7: */ MD(14), MD(14),
657 /* 8: */ MD(15), MD(15))
658 FF(urb_global_offset,
659 /* 4: */ MD( 9), MD(4),
660 /* 4.5: */ MD( 9), MD(4),
661 /* 5: */ MD( 9), MD(4),
662 /* 6: */ MD( 9), MD(4),
663 /* 7: */ MD(13), MD(3),
664 /* 8: */ MD(14), MD(4))
665 FF(urb_opcode,
666 /* 4: */ MD( 3), MD(0),
667 /* 4.5: */ MD( 3), MD(0),
668 /* 5: */ MD( 3), MD(0),
669 /* 6: */ MD( 3), MD(0),
670 /* 7: */ MD( 2), MD(0),
671 /* 8: */ MD( 3), MD(0))
672 /** @} */
673
674 /**
675 * Gen4-5 math messages:
676 * @{
677 */
678 FC(math_msg_data_type, MD(7), MD(7), devinfo->gen < 6)
679 FC(math_msg_saturate, MD(6), MD(6), devinfo->gen < 6)
680 FC(math_msg_precision, MD(5), MD(5), devinfo->gen < 6)
681 FC(math_msg_signed_int, MD(4), MD(4), devinfo->gen < 6)
682 FC(math_msg_function, MD(3), MD(0), devinfo->gen < 6)
683 /** @} */
684
685 /**
686 * Sampler message function control bits:
687 * @{
688 */
689 FF(sampler_simd_mode,
690 /* 4: doesn't exist */ -1, -1, -1, -1,
691 /* 5: */ MD(17), MD(16),
692 /* 6: */ MD(17), MD(16),
693 /* 7: */ MD(18), MD(17),
694 /* 8: */ MD(18), MD(17))
695 FF(sampler_msg_type,
696 /* 4: */ MD(15), MD(14),
697 /* 4.5: */ MD(15), MD(12),
698 /* 5: */ MD(15), MD(12),
699 /* 6: */ MD(15), MD(12),
700 /* 7: */ MD(16), MD(12),
701 /* 8: */ MD(16), MD(12))
702 FC(sampler_return_format, MD(13), MD(12), devinfo->gen == 4 && !devinfo->is_g4x)
703 F(sampler, MD(11), MD(8))
704 F(binding_table_index, MD( 7), MD(0)) /* also used by other messages */
705 /** @} */
706
707 /**
708 * Data port message function control bits:
709 * @{
710 */
711 FC(dp_category, MD(18), MD(18), devinfo->gen >= 7)
712
713 /* Gen4-5 store fields in different bits for read/write messages. */
714 FF(dp_read_msg_type,
715 /* 4: */ MD(13), MD(12),
716 /* 4.5: */ MD(13), MD(11),
717 /* 5: */ MD(13), MD(11),
718 /* 6: */ MD(16), MD(13),
719 /* 7: */ MD(17), MD(14),
720 /* 8: */ MD(17), MD(14))
721 FF(dp_write_msg_type,
722 /* 4: */ MD(14), MD(12),
723 /* 4.5: */ MD(14), MD(12),
724 /* 5: */ MD(14), MD(12),
725 /* 6: */ MD(16), MD(13),
726 /* 7: */ MD(17), MD(14),
727 /* 8: */ MD(17), MD(14))
728 FF(dp_read_msg_control,
729 /* 4: */ MD(11), MD( 8),
730 /* 4.5: */ MD(10), MD( 8),
731 /* 5: */ MD(10), MD( 8),
732 /* 6: */ MD(12), MD( 8),
733 /* 7: */ MD(13), MD( 8),
734 /* 8: */ MD(13), MD( 8))
735 FF(dp_write_msg_control,
736 /* 4: */ MD(11), MD( 8),
737 /* 4.5: */ MD(11), MD( 8),
738 /* 5: */ MD(11), MD( 8),
739 /* 6: */ MD(12), MD( 8),
740 /* 7: */ MD(13), MD( 8),
741 /* 8: */ MD(13), MD( 8))
742 FC(dp_read_target_cache, MD(15), MD(14), devinfo->gen < 6);
743
744 FF(dp_write_commit,
745 /* 4: */ MD(15), MD(15),
746 /* 4.5: */ MD(15), MD(15),
747 /* 5: */ MD(15), MD(15),
748 /* 6: */ MD(17), MD(17),
749 /* 7+: does not exist */ -1, -1, -1, -1)
750
751 /* Gen6+ use the same bit locations for everything. */
752 FF(dp_msg_type,
753 /* 4-5: use dp_read_msg_type or dp_write_msg_type instead */
754 -1, -1, -1, -1, -1, -1,
755 /* 6: */ MD(16), MD(13),
756 /* 7: */ MD(17), MD(14),
757 /* 8: */ MD(18), MD(14))
758 FF(dp_msg_control,
759 /* 4: */ MD(11), MD( 8),
760 /* 4.5-5: use dp_read_msg_control or dp_write_msg_control */ -1, -1, -1, -1,
761 /* 6: */ MD(12), MD( 8),
762 /* 7: */ MD(13), MD( 8),
763 /* 8: */ MD(13), MD( 8))
764 /** @} */
765
766 /**
767 * Scratch message bits (Gen7+):
768 * @{
769 */
770 FC(scratch_read_write, MD(17), MD(17), devinfo->gen >= 7) /* 0 = read, 1 = write */
771 FC(scratch_type, MD(16), MD(16), devinfo->gen >= 7) /* 0 = OWord, 1 = DWord */
772 FC(scratch_invalidate_after_read, MD(15), MD(15), devinfo->gen >= 7)
773 FC(scratch_block_size, MD(13), MD(12), devinfo->gen >= 7)
774 FC(scratch_addr_offset, MD(11), MD( 0), devinfo->gen >= 7)
775 /** @} */
776
777 /**
778 * Render Target message function control bits:
779 * @{
780 */
781 FF(rt_last,
782 /* 4: */ MD(11), MD(11),
783 /* 4.5: */ MD(11), MD(11),
784 /* 5: */ MD(11), MD(11),
785 /* 6: */ MD(12), MD(12),
786 /* 7: */ MD(12), MD(12),
787 /* 8: */ MD(12), MD(12))
788 FC(rt_slot_group, MD(11), MD(11), devinfo->gen >= 6)
789 F(rt_message_type, MD(10), MD( 8))
790 /** @} */
791
792 /**
793 * Thread Spawn message function control bits:
794 * @{
795 */
796 F(ts_resource_select, MD( 4), MD( 4))
797 F(ts_request_type, MD( 1), MD( 1))
798 F(ts_opcode, MD( 0), MD( 0))
799 /** @} */
800
801 /**
802 * Pixel Interpolator message function control bits:
803 * @{
804 */
805 F(pi_simd_mode, MD(16), MD(16))
806 F(pi_nopersp, MD(14), MD(14))
807 F(pi_message_type, MD(13), MD(12))
808 F(pi_slot_group, MD(11), MD(11))
809 F(pi_message_data, MD(7), MD(0))
810 /** @} */
811
812 /**
813 * Immediates:
814 * @{
815 */
816 static inline int
817 brw_inst_imm_d(const struct gen_device_info *devinfo, const brw_inst *insn)
818 {
819 (void) devinfo;
820 return brw_inst_bits(insn, 127, 96);
821 }
822
823 static inline unsigned
824 brw_inst_imm_ud(const struct gen_device_info *devinfo, const brw_inst *insn)
825 {
826 (void) devinfo;
827 return brw_inst_bits(insn, 127, 96);
828 }
829
830 static inline uint64_t
831 brw_inst_imm_uq(ASSERTED const struct gen_device_info *devinfo,
832 const brw_inst *insn)
833 {
834 assert(devinfo->gen >= 8);
835 return brw_inst_bits(insn, 127, 64);
836 }
837
838 static inline float
839 brw_inst_imm_f(const struct gen_device_info *devinfo, const brw_inst *insn)
840 {
841 union {
842 float f;
843 uint32_t u;
844 } ft;
845 (void) devinfo;
846 ft.u = brw_inst_bits(insn, 127, 96);
847 return ft.f;
848 }
849
850 static inline double
851 brw_inst_imm_df(const struct gen_device_info *devinfo, const brw_inst *insn)
852 {
853 union {
854 double d;
855 uint64_t u;
856 } dt;
857 (void) devinfo;
858 dt.u = brw_inst_bits(insn, 127, 64);
859 return dt.d;
860 }
861
862 static inline void
863 brw_inst_set_imm_d(const struct gen_device_info *devinfo,
864 brw_inst *insn, int value)
865 {
866 (void) devinfo;
867 return brw_inst_set_bits(insn, 127, 96, value);
868 }
869
870 static inline void
871 brw_inst_set_imm_ud(const struct gen_device_info *devinfo,
872 brw_inst *insn, unsigned value)
873 {
874 (void) devinfo;
875 return brw_inst_set_bits(insn, 127, 96, value);
876 }
877
878 static inline void
879 brw_inst_set_imm_f(const struct gen_device_info *devinfo,
880 brw_inst *insn, float value)
881 {
882 union {
883 float f;
884 uint32_t u;
885 } ft;
886 (void) devinfo;
887 ft.f = value;
888 brw_inst_set_bits(insn, 127, 96, ft.u);
889 }
890
891 static inline void
892 brw_inst_set_imm_df(const struct gen_device_info *devinfo,
893 brw_inst *insn, double value)
894 {
895 union {
896 double d;
897 uint64_t u;
898 } dt;
899 (void) devinfo;
900 dt.d = value;
901 brw_inst_set_bits(insn, 127, 64, dt.u);
902 }
903
904 static inline void
905 brw_inst_set_imm_uq(const struct gen_device_info *devinfo,
906 brw_inst *insn, uint64_t value)
907 {
908 (void) devinfo;
909 brw_inst_set_bits(insn, 127, 64, value);
910 }
911
912 /** @} */
913
914 #define REG_TYPE(reg) \
915 static inline void \
916 brw_inst_set_##reg##_file_type(const struct gen_device_info *devinfo, \
917 brw_inst *inst, enum brw_reg_file file, \
918 enum brw_reg_type type) \
919 { \
920 assert(file <= BRW_IMMEDIATE_VALUE); \
921 unsigned hw_type = brw_reg_type_to_hw_type(devinfo, file, type); \
922 brw_inst_set_##reg##_reg_file(devinfo, inst, file); \
923 brw_inst_set_##reg##_reg_hw_type(devinfo, inst, hw_type); \
924 } \
925 \
926 static inline enum brw_reg_type \
927 brw_inst_##reg##_type(const struct gen_device_info *devinfo, \
928 const brw_inst *inst) \
929 { \
930 unsigned file = __builtin_strcmp("dst", #reg) == 0 ? \
931 (unsigned) BRW_GENERAL_REGISTER_FILE : \
932 brw_inst_##reg##_reg_file(devinfo, inst); \
933 unsigned hw_type = brw_inst_##reg##_reg_hw_type(devinfo, inst); \
934 return brw_hw_type_to_reg_type(devinfo, (enum brw_reg_file)file, hw_type); \
935 }
936
937 REG_TYPE(dst)
938 REG_TYPE(src0)
939 REG_TYPE(src1)
940 #undef REG_TYPE
941
942
943 /* The AddrImm fields are split into two discontiguous sections on Gen8+ */
944 #define BRW_IA1_ADDR_IMM(reg, g4_high, g4_low, g8_nine, g8_high, g8_low) \
945 static inline void \
946 brw_inst_set_##reg##_ia1_addr_imm(const struct gen_device_info *devinfo, \
947 brw_inst *inst, \
948 unsigned value) \
949 { \
950 assert((value & ~0x3ff) == 0); \
951 if (devinfo->gen >= 8) { \
952 brw_inst_set_bits(inst, g8_high, g8_low, value & 0x1ff); \
953 brw_inst_set_bits(inst, g8_nine, g8_nine, value >> 9); \
954 } else { \
955 brw_inst_set_bits(inst, g4_high, g4_low, value); \
956 } \
957 } \
958 static inline unsigned \
959 brw_inst_##reg##_ia1_addr_imm(const struct gen_device_info *devinfo, \
960 const brw_inst *inst) \
961 { \
962 if (devinfo->gen >= 8) { \
963 return brw_inst_bits(inst, g8_high, g8_low) | \
964 (brw_inst_bits(inst, g8_nine, g8_nine) << 9); \
965 } else { \
966 return brw_inst_bits(inst, g4_high, g4_low); \
967 } \
968 }
969
970 /* AddrImm[9:0] for Align1 Indirect Addressing */
971 /* -Gen 4- ----Gen8---- */
972 BRW_IA1_ADDR_IMM(src1, 105, 96, 121, 104, 96)
973 BRW_IA1_ADDR_IMM(src0, 73, 64, 95, 72, 64)
974 BRW_IA1_ADDR_IMM(dst, 57, 48, 47, 56, 48)
975
976 #define BRW_IA16_ADDR_IMM(reg, g4_high, g4_low, g8_nine, g8_high, g8_low) \
977 static inline void \
978 brw_inst_set_##reg##_ia16_addr_imm(const struct gen_device_info *devinfo, \
979 brw_inst *inst, unsigned value) \
980 { \
981 assert((value & ~0x3ff) == 0); \
982 if (devinfo->gen >= 8) { \
983 assert(GET_BITS(value, 3, 0) == 0); \
984 brw_inst_set_bits(inst, g8_high, g8_low, GET_BITS(value, 8, 4)); \
985 brw_inst_set_bits(inst, g8_nine, g8_nine, GET_BITS(value, 9, 9)); \
986 } else { \
987 brw_inst_set_bits(inst, g4_high, g4_low, value); \
988 } \
989 } \
990 static inline unsigned \
991 brw_inst_##reg##_ia16_addr_imm(const struct gen_device_info *devinfo, \
992 const brw_inst *inst) \
993 { \
994 if (devinfo->gen >= 8) { \
995 return (brw_inst_bits(inst, g8_high, g8_low) << 4) | \
996 (brw_inst_bits(inst, g8_nine, g8_nine) << 9); \
997 } else { \
998 return brw_inst_bits(inst, g4_high, g4_low); \
999 } \
1000 }
1001
1002 /* AddrImm[9:0] for Align16 Indirect Addressing:
1003 * Compared to Align1, these are missing the low 4 bits.
1004 * -Gen 4- ----Gen8----
1005 */
1006 BRW_IA16_ADDR_IMM(src1, 105, 96, 121, 104, 100)
1007 BRW_IA16_ADDR_IMM(src0, 73, 64, 95, 72, 68)
1008 BRW_IA16_ADDR_IMM(dst, 57, 52, 47, 56, 52)
1009 BRW_IA16_ADDR_IMM(send_src0, -1, -1, 78, 72, 68)
1010 BRW_IA16_ADDR_IMM(send_dst, -1, -1, 62, 56, 52)
1011
1012 /**
1013 * Fetch a set of contiguous bits from the instruction.
1014 *
1015 * Bits indices range from 0..127; fields may not cross 64-bit boundaries.
1016 */
1017 static inline uint64_t
1018 brw_inst_bits(const brw_inst *inst, unsigned high, unsigned low)
1019 {
1020 /* We assume the field doesn't cross 64-bit boundaries. */
1021 const unsigned word = high / 64;
1022 assert(word == low / 64);
1023
1024 high %= 64;
1025 low %= 64;
1026
1027 const uint64_t mask = (~0ull >> (64 - (high - low + 1)));
1028
1029 return (inst->data[word] >> low) & mask;
1030 }
1031
1032 /**
1033 * Set bits in the instruction, with proper shifting and masking.
1034 *
1035 * Bits indices range from 0..127; fields may not cross 64-bit boundaries.
1036 */
1037 static inline void
1038 brw_inst_set_bits(brw_inst *inst, unsigned high, unsigned low, uint64_t value)
1039 {
1040 const unsigned word = high / 64;
1041 assert(word == low / 64);
1042
1043 high %= 64;
1044 low %= 64;
1045
1046 const uint64_t mask = (~0ull >> (64 - (high - low + 1))) << low;
1047
1048 /* Make sure the supplied value actually fits in the given bitfield. */
1049 assert((value & (mask >> low)) == value);
1050
1051 inst->data[word] = (inst->data[word] & ~mask) | (value << low);
1052 }
1053
1054 #undef BRW_IA16_ADDR_IMM
1055 #undef BRW_IA1_ADDR_IMM
1056 #undef MD
1057 #undef F8
1058 #undef FF
1059 #undef BOUNDS
1060 #undef F
1061 #undef FC
1062
1063 typedef struct {
1064 uint64_t data;
1065 } brw_compact_inst;
1066
1067 /**
1068 * Fetch a set of contiguous bits from the compacted instruction.
1069 *
1070 * Bits indices range from 0..63.
1071 */
1072 static inline unsigned
1073 brw_compact_inst_bits(const brw_compact_inst *inst, unsigned high, unsigned low)
1074 {
1075 const uint64_t mask = (1ull << (high - low + 1)) - 1;
1076
1077 return (inst->data >> low) & mask;
1078 }
1079
1080 /**
1081 * Set bits in the compacted instruction.
1082 *
1083 * Bits indices range from 0..63.
1084 */
1085 static inline void
1086 brw_compact_inst_set_bits(brw_compact_inst *inst, unsigned high, unsigned low,
1087 uint64_t value)
1088 {
1089 const uint64_t mask = ((1ull << (high - low + 1)) - 1) << low;
1090
1091 /* Make sure the supplied value actually fits in the given bitfield. */
1092 assert((value & (mask >> low)) == value);
1093
1094 inst->data = (inst->data & ~mask) | (value << low);
1095 }
1096
1097 #define FC(name, high, low, assertions) \
1098 static inline void \
1099 brw_compact_inst_set_##name(const struct gen_device_info *devinfo, \
1100 brw_compact_inst *inst, unsigned v) \
1101 { \
1102 assert(assertions); \
1103 (void) devinfo; \
1104 brw_compact_inst_set_bits(inst, high, low, v); \
1105 } \
1106 static inline unsigned \
1107 brw_compact_inst_##name(const struct gen_device_info *devinfo, \
1108 const brw_compact_inst *inst) \
1109 { \
1110 assert(assertions); \
1111 (void) devinfo; \
1112 return brw_compact_inst_bits(inst, high, low); \
1113 }
1114
1115 /* A simple macro for fields which stay in the same place on all generations. */
1116 #define F(name, high, low) FC(name, high, low, true)
1117
1118 F(src1_reg_nr, 63, 56)
1119 F(src0_reg_nr, 55, 48)
1120 F(dst_reg_nr, 47, 40)
1121 F(src1_index, 39, 35)
1122 F(src0_index, 34, 30)
1123 F(cmpt_control, 29, 29) /* Same location as brw_inst */
1124 FC(flag_subreg_nr, 28, 28, devinfo->gen <= 6)
1125 F(cond_modifier, 27, 24) /* Same location as brw_inst */
1126 FC(acc_wr_control, 23, 23, devinfo->gen >= 6)
1127 FC(mask_control_ex, 23, 23, devinfo->is_g4x || devinfo->gen == 5)
1128 F(subreg_index, 22, 18)
1129 F(datatype_index, 17, 13)
1130 F(control_index, 12, 8)
1131 F(debug_control, 7, 7)
1132 F(opcode, 6, 0) /* Same location as brw_inst */
1133
1134 /**
1135 * (Gen8+) Compacted three-source instructions:
1136 * @{
1137 */
1138 FC(3src_src2_reg_nr, 63, 57, devinfo->gen >= 8)
1139 FC(3src_src1_reg_nr, 56, 50, devinfo->gen >= 8)
1140 FC(3src_src0_reg_nr, 49, 43, devinfo->gen >= 8)
1141 FC(3src_src2_subreg_nr, 42, 40, devinfo->gen >= 8)
1142 FC(3src_src1_subreg_nr, 39, 37, devinfo->gen >= 8)
1143 FC(3src_src0_subreg_nr, 36, 34, devinfo->gen >= 8)
1144 FC(3src_src2_rep_ctrl, 33, 33, devinfo->gen >= 8)
1145 FC(3src_src1_rep_ctrl, 32, 32, devinfo->gen >= 8)
1146 FC(3src_saturate, 31, 31, devinfo->gen >= 8)
1147 FC(3src_debug_control, 30, 30, devinfo->gen >= 8)
1148 FC(3src_cmpt_control, 29, 29, devinfo->gen >= 8)
1149 FC(3src_src0_rep_ctrl, 28, 28, devinfo->gen >= 8)
1150 /* Reserved */
1151 FC(3src_dst_reg_nr, 18, 12, devinfo->gen >= 8)
1152 FC(3src_source_index, 11, 10, devinfo->gen >= 8)
1153 FC(3src_control_index, 9, 8, devinfo->gen >= 8)
1154 /* Bit 7 is Reserved (for future Opcode expansion) */
1155 FC(3src_opcode, 6, 0, devinfo->gen >= 8)
1156 /** @} */
1157
1158 #undef F
1159
1160 #ifdef __cplusplus
1161 }
1162 #endif
1163
1164 #endif