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intel/eu/gen12: Implement SEND instruction binary encoding.
[mesa.git] / src / intel / compiler / brw_inst.h
1 /*
2 * Copyright © 2014 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 */
23
24 /**
25 * @file brw_inst.h
26 *
27 * A representation of i965 EU assembly instructions, with helper methods to
28 * get and set various fields. This is the actual hardware format.
29 */
30
31 #ifndef BRW_INST_H
32 #define BRW_INST_H
33
34 #include <assert.h>
35 #include <stdint.h>
36
37 #include "brw_eu_defines.h"
38 #include "brw_reg_type.h"
39 #include "dev/gen_device_info.h"
40
41 #ifdef __cplusplus
42 extern "C" {
43 #endif
44
45 /* brw_context.h has a forward declaration of brw_inst, so name the struct. */
46 typedef struct brw_inst {
47 uint64_t data[2];
48 } brw_inst;
49
50 static inline uint64_t brw_inst_bits(const brw_inst *inst,
51 unsigned high, unsigned low);
52 static inline void brw_inst_set_bits(brw_inst *inst,
53 unsigned high, unsigned low,
54 uint64_t value);
55
56 #define FC(name, hi4, lo4, hi12, lo12, assertions) \
57 static inline void \
58 brw_inst_set_##name(const struct gen_device_info *devinfo, \
59 brw_inst *inst, uint64_t v) \
60 { \
61 assert(assertions); \
62 if (devinfo->gen >= 12) \
63 brw_inst_set_bits(inst, hi12, lo12, v); \
64 else \
65 brw_inst_set_bits(inst, hi4, lo4, v); \
66 } \
67 static inline uint64_t \
68 brw_inst_##name(const struct gen_device_info *devinfo, \
69 const brw_inst *inst) \
70 { \
71 assert(assertions); \
72 if (devinfo->gen >= 12) \
73 return brw_inst_bits(inst, hi12, lo12); \
74 else \
75 return brw_inst_bits(inst, hi4, lo4); \
76 }
77
78 /* A simple macro for fields which stay in the same place on all generations,
79 * except for Gen12!
80 */
81 #define F(name, hi4, lo4, hi12, lo12) FC(name, hi4, lo4, hi12, lo12, true)
82
83 #define BOUNDS(hi4, lo4, hi45, lo45, hi5, lo5, hi6, lo6, \
84 hi7, lo7, hi8, lo8, hi12, lo12) \
85 unsigned high, low; \
86 if (devinfo->gen >= 12) { \
87 high = hi12; low = lo12; \
88 } else if (devinfo->gen >= 8) { \
89 high = hi8; low = lo8; \
90 } else if (devinfo->gen >= 7) { \
91 high = hi7; low = lo7; \
92 } else if (devinfo->gen >= 6) { \
93 high = hi6; low = lo6; \
94 } else if (devinfo->gen >= 5) { \
95 high = hi5; low = lo5; \
96 } else if (devinfo->is_g4x) { \
97 high = hi45; low = lo45; \
98 } else { \
99 high = hi4; low = lo4; \
100 } \
101 assert(((int) high) != -1 && ((int) low) != -1);
102
103 /* A general macro for cases where the field has moved to several different
104 * bit locations across generations. GCC appears to combine cases where the
105 * bits are identical, removing some of the inefficiency.
106 */
107 #define FF(name, hi4, lo4, hi45, lo45, hi5, lo5, hi6, lo6, \
108 hi7, lo7, hi8, lo8, hi12, lo12) \
109 static inline void \
110 brw_inst_set_##name(const struct gen_device_info *devinfo, \
111 brw_inst *inst, uint64_t value) \
112 { \
113 BOUNDS(hi4, lo4, hi45, lo45, hi5, lo5, hi6, lo6, \
114 hi7, lo7, hi8, lo8, hi12, lo12) \
115 brw_inst_set_bits(inst, high, low, value); \
116 } \
117 static inline uint64_t \
118 brw_inst_##name(const struct gen_device_info *devinfo, const brw_inst *inst) \
119 { \
120 BOUNDS(hi4, lo4, hi45, lo45, hi5, lo5, hi6, lo6, \
121 hi7, lo7, hi8, lo8, hi12, lo12) \
122 return brw_inst_bits(inst, high, low); \
123 }
124
125 /* A macro for fields which moved as of Gen8+. */
126 #define F8(name, gen4_high, gen4_low, gen8_high, gen8_low, \
127 gen12_high, gen12_low) \
128 FF(name, \
129 /* 4: */ gen4_high, gen4_low, \
130 /* 4.5: */ gen4_high, gen4_low, \
131 /* 5: */ gen4_high, gen4_low, \
132 /* 6: */ gen4_high, gen4_low, \
133 /* 7: */ gen4_high, gen4_low, \
134 /* 8: */ gen8_high, gen8_low, \
135 /* 12: */ gen12_high, gen12_low);
136
137 /* Macro for fields that gained extra discontiguous MSBs in Gen12 (specified
138 * by hi12ex-lo12ex).
139 */
140 #define FFDC(name, hi4, lo4, hi45, lo45, hi5, lo5, hi6, lo6, \
141 hi7, lo7, hi8, lo8, hi12ex, lo12ex, hi12, lo12, assertions) \
142 static inline void \
143 brw_inst_set_##name(const struct gen_device_info *devinfo, \
144 brw_inst *inst, uint64_t value) \
145 { \
146 assert(assertions); \
147 if (devinfo->gen >= 12) { \
148 const unsigned k = hi12 - lo12 + 1; \
149 if (hi12ex != -1 && lo12ex != -1) \
150 brw_inst_set_bits(inst, hi12ex, lo12ex, value >> k); \
151 brw_inst_set_bits(inst, hi12, lo12, value & ((1ull << k) - 1)); \
152 } else { \
153 BOUNDS(hi4, lo4, hi45, lo45, hi5, lo5, hi6, lo6, \
154 hi7, lo7, hi8, lo8, -1, -1); \
155 brw_inst_set_bits(inst, high, low, value); \
156 } \
157 } \
158 static inline uint64_t \
159 brw_inst_##name(const struct gen_device_info *devinfo, const brw_inst *inst) \
160 { \
161 assert(assertions); \
162 if (devinfo->gen >= 12) { \
163 const unsigned k = hi12 - lo12 + 1; \
164 return (hi12ex == -1 || lo12ex == -1 ? 0 : \
165 brw_inst_bits(inst, hi12ex, lo12ex) << k) | \
166 brw_inst_bits(inst, hi12, lo12); \
167 } else { \
168 BOUNDS(hi4, lo4, hi45, lo45, hi5, lo5, hi6, lo6, \
169 hi7, lo7, hi8, lo8, -1, -1); \
170 return brw_inst_bits(inst, high, low); \
171 } \
172 }
173
174 #define FD(name, hi4, lo4, hi45, lo45, hi5, lo5, hi6, lo6, \
175 hi7, lo7, hi8, lo8, hi12ex, lo12ex, hi12, lo12) \
176 FFDC(name, hi4, lo4, hi45, lo45, hi5, lo5, hi6, lo6, \
177 hi7, lo7, hi8, lo8, hi12ex, lo12ex, hi12, lo12, true)
178
179 /* Macro for fields that didn't move across generations until Gen12, and then
180 * gained extra discontiguous bits.
181 */
182 #define FDC(name, hi4, lo4, hi12ex, lo12ex, hi12, lo12, assertions) \
183 FFDC(name, hi4, lo4, hi4, lo4, hi4, lo4, hi4, lo4, \
184 hi4, lo4, hi4, lo4, hi12ex, lo12ex, hi12, lo12, assertions)
185
186
187 /* Macro for the 2-bit register file field, which on Gen12+ is stored as the
188 * variable length combination of an IsImm (hi12) bit and an additional file
189 * (lo12) bit.
190 */
191 #define FI(name, hi4, lo4, hi8, lo8, hi12, lo12) \
192 static inline void \
193 brw_inst_set_##name(const struct gen_device_info *devinfo, \
194 brw_inst *inst, uint64_t value) \
195 { \
196 if (devinfo->gen >= 12) { \
197 brw_inst_set_bits(inst, hi12, hi12, value >> 1); \
198 if ((value >> 1) == 0) \
199 brw_inst_set_bits(inst, lo12, lo12, value & 1); \
200 } else { \
201 BOUNDS(hi4, lo4, hi4, lo4, hi4, lo4, hi4, lo4, \
202 hi4, lo4, hi8, lo8, -1, -1); \
203 brw_inst_set_bits(inst, high, low, value); \
204 } \
205 } \
206 static inline uint64_t \
207 brw_inst_##name(const struct gen_device_info *devinfo, const brw_inst *inst) \
208 { \
209 if (devinfo->gen >= 12) { \
210 return (brw_inst_bits(inst, hi12, hi12) << 1) | \
211 (brw_inst_bits(inst, hi12, hi12) == 0 ? \
212 brw_inst_bits(inst, lo12, lo12) : 1); \
213 } else { \
214 BOUNDS(hi4, lo4, hi4, lo4, hi4, lo4, hi4, lo4, \
215 hi4, lo4, hi8, lo8, -1, -1); \
216 return brw_inst_bits(inst, high, low); \
217 } \
218 }
219
220 /* Macro for fields that become a constant in Gen12+ not actually represented
221 * in the instruction.
222 */
223 #define FK(name, hi4, lo4, const12) \
224 static inline void \
225 brw_inst_set_##name(const struct gen_device_info *devinfo, \
226 brw_inst *inst, uint64_t v) \
227 { \
228 if (devinfo->gen >= 12) \
229 assert(v == (const12)); \
230 else \
231 brw_inst_set_bits(inst, hi4, lo4, v); \
232 } \
233 static inline uint64_t \
234 brw_inst_##name(const struct gen_device_info *devinfo, \
235 const brw_inst *inst) \
236 { \
237 if (devinfo->gen >= 12) \
238 return (const12); \
239 else \
240 return brw_inst_bits(inst, hi4, lo4); \
241 }
242
243 F(src1_vstride, /* 4+ */ 120, 117, /* 12+ */ 119, 116)
244 F(src1_width, /* 4+ */ 116, 114, /* 12+ */ 115, 113)
245 F(src1_da16_swiz_w, /* 4+ */ 115, 114, /* 12+ */ -1, -1)
246 F(src1_da16_swiz_z, /* 4+ */ 113, 112, /* 12+ */ -1, -1)
247 F(src1_hstride, /* 4+ */ 113, 112, /* 12+ */ 97, 96)
248 F(src1_address_mode, /* 4+ */ 111, 111, /* 12+ */ 112, 112)
249 /** Src1.SrcMod @{ */
250 F(src1_negate, /* 4+ */ 110, 110, /* 12+ */ 121, 121)
251 F(src1_abs, /* 4+ */ 109, 109, /* 12+ */ 120, 120)
252 /** @} */
253 F8(src1_ia_subreg_nr, /* 4+ */ 108, 106, /* 8+ */ 108, 105, /* 12+ */ 111, 108)
254 F(src1_da_reg_nr, /* 4+ */ 108, 101, /* 12+ */ 111, 104)
255 F(src1_da16_subreg_nr, /* 4+ */ 100, 100, /* 12+ */ -1, -1)
256 F(src1_da1_subreg_nr, /* 4+ */ 100, 96, /* 12+ */ 103, 99)
257 F(src1_da16_swiz_y, /* 4+ */ 99, 98, /* 12+ */ -1, -1)
258 F(src1_da16_swiz_x, /* 4+ */ 97, 96, /* 12+ */ -1, -1)
259 F8(src1_reg_hw_type, /* 4+ */ 46, 44, /* 8+ */ 94, 91, /* 12+ */ 91, 88)
260 FI(src1_reg_file, /* 4+ */ 43, 42, /* 8+ */ 90, 89, /* 12+ */ 47, 98)
261 F(src1_is_imm, /* 4+ */ -1, -1, /* 12+ */ 47, 47)
262 F(src0_vstride, /* 4+ */ 88, 85, /* 12+ */ 87, 84)
263 F(src0_width, /* 4+ */ 84, 82, /* 12+ */ 83, 81)
264 F(src0_da16_swiz_w, /* 4+ */ 83, 82, /* 12+ */ -1, -1)
265 F(src0_da16_swiz_z, /* 4+ */ 81, 80, /* 12+ */ -1, -1)
266 F(src0_hstride, /* 4+ */ 81, 80, /* 12+ */ 65, 64)
267 F(src0_address_mode, /* 4+ */ 79, 79, /* 12+ */ 80, 80)
268 /** Src0.SrcMod @{ */
269 F(src0_negate, /* 4+ */ 78, 78, /* 12+ */ 45, 45)
270 F(src0_abs, /* 4+ */ 77, 77, /* 12+ */ 44, 44)
271 /** @} */
272 F8(src0_ia_subreg_nr, /* 4+ */ 76, 74, /* 8+ */ 76, 73, /* 12+ */ 79, 76)
273 F(src0_da_reg_nr, /* 4+ */ 76, 69, /* 12+ */ 79, 72)
274 F(src0_da16_subreg_nr, /* 4+ */ 68, 68, /* 12+ */ -1, -1)
275 F(src0_da1_subreg_nr, /* 4+ */ 68, 64, /* 12+ */ 71, 67)
276 F(src0_da16_swiz_y, /* 4+ */ 67, 66, /* 12+ */ -1, -1)
277 F(src0_da16_swiz_x, /* 4+ */ 65, 64, /* 12+ */ -1, -1)
278 F(dst_address_mode, /* 4+ */ 63, 63, /* 12+ */ 35, 35)
279 F(dst_hstride, /* 4+ */ 62, 61, /* 12+ */ 49, 48)
280 F8(dst_ia_subreg_nr, /* 4+ */ 60, 58, /* 8+ */ 60, 57, /* 12+ */ 63, 60)
281 F(dst_da_reg_nr, /* 4+ */ 60, 53, /* 12+ */ 63, 56)
282 F(dst_da16_subreg_nr, /* 4+ */ 52, 52, /* 12+ */ -1, -1)
283 F(dst_da1_subreg_nr, /* 4+ */ 52, 48, /* 12+ */ 55, 51)
284 F(da16_writemask, /* 4+ */ 51, 48, /* 12+ */ -1, -1) /* Dst.ChanEn */
285 F8(src0_reg_hw_type, /* 4+ */ 41, 39, /* 8+ */ 46, 43, /* 12+ */ 43, 40)
286 FI(src0_reg_file, /* 4+ */ 38, 37, /* 8+ */ 42, 41, /* 12+ */ 46, 66)
287 F(src0_is_imm, /* 4+ */ -1, -1, /* 12+ */ 46, 46)
288 F8(dst_reg_hw_type, /* 4+ */ 36, 34, /* 8+ */ 40, 37, /* 12+ */ 39, 36)
289 F8(dst_reg_file, /* 4+ */ 33, 32, /* 8+ */ 36, 35, /* 12+ */ 50, 50)
290 F8(mask_control, /* 4+ */ 9, 9, /* 8+ */ 34, 34, /* 12+ */ 31, 31)
291 FF(flag_reg_nr,
292 /* 4-6: doesn't exist */ -1, -1, -1, -1, -1, -1, -1, -1,
293 /* 7: */ 90, 90,
294 /* 8: */ 33, 33,
295 /* 12: */ 23, 23)
296 F8(flag_subreg_nr, /* 4+ */ 89, 89, /* 8+ */ 32, 32, /* 12+ */ 22, 22)
297 F(saturate, /* 4+ */ 31, 31, /* 12+ */ 34, 34)
298 F(debug_control, /* 4+ */ 30, 30, /* 12+ */ 30, 30)
299 F(cmpt_control, /* 4+ */ 29, 29, /* 12+ */ 29, 29)
300 FC(branch_control, /* 4+ */ 28, 28, /* 12+ */ 33, 33, devinfo->gen >= 8)
301 FC(acc_wr_control, /* 4+ */ 28, 28, /* 12+ */ 33, 33, devinfo->gen >= 6)
302 FC(mask_control_ex, /* 4+ */ 28, 28, /* 12+ */ -1, -1, devinfo->is_g4x || devinfo->gen == 5)
303 F(cond_modifier, /* 4+ */ 27, 24, /* 12+ */ 95, 92)
304 FC(math_function, /* 4+ */ 27, 24, /* 12+ */ 95, 92, devinfo->gen >= 6)
305 F(exec_size, /* 4+ */ 23, 21, /* 12+ */ 18, 16)
306 F(pred_inv, /* 4+ */ 20, 20, /* 12+ */ 28, 28)
307 F(pred_control, /* 4+ */ 19, 16, /* 12+ */ 27, 24)
308 F(thread_control, /* 4+ */ 15, 14, /* 12+ */ -1, -1)
309 F(atomic_control, /* 4+ */ -1, -1, /* 12+ */ 32, 32)
310 F(qtr_control, /* 4+ */ 13, 12, /* 12+ */ 21, 20)
311 FF(nib_control,
312 /* 4-6: doesn't exist */ -1, -1, -1, -1, -1, -1, -1, -1,
313 /* 7: */ 47, 47,
314 /* 8: */ 11, 11,
315 /* 12: */ 19, 19)
316 F8(no_dd_check, /* 4+ */ 11, 11, /* 8+ */ 10, 10, /* 12+ */ -1, -1)
317 F8(no_dd_clear, /* 4+ */ 10, 10, /* 8+ */ 9, 9, /* 12+ */ -1, -1)
318 F(swsb, /* 4+ */ -1, -1, /* 12+ */ 15, 8)
319 FK(access_mode, /* 4+ */ 8, 8, /* 12+ */ BRW_ALIGN_1)
320 /* Bit 7 is Reserved (for future Opcode expansion) */
321 F(hw_opcode, /* 4+ */ 6, 0, /* 12+ */ 6, 0)
322
323 /**
324 * Three-source instructions:
325 * @{
326 */
327 F(3src_src2_reg_nr, /* 4+ */ 125, 118, /* 12+ */ 127, 120) /* same in align1 */
328 F(3src_a16_src2_subreg_nr, /* 4+ */ 117, 115, /* 12+ */ -1, -1) /* Extra discontiguous bit on CHV? */
329 F(3src_a16_src2_swizzle, /* 4+ */ 114, 107, /* 12+ */ -1, -1)
330 F(3src_a16_src2_rep_ctrl, /* 4+ */ 106, 106, /* 12+ */ -1, -1)
331 F(3src_src1_reg_nr, /* 4+ */ 104, 97, /* 12+ */ 111, 104) /* same in align1 */
332 F(3src_a16_src1_subreg_nr, /* 4+ */ 96, 94, /* 12+ */ -1, -1) /* Extra discontiguous bit on CHV? */
333 F(3src_a16_src1_swizzle, /* 4+ */ 93, 86, /* 12+ */ -1, -1)
334 F(3src_a16_src1_rep_ctrl, /* 4+ */ 85, 85, /* 12+ */ -1, -1)
335 F(3src_src0_reg_nr, /* 4+ */ 83, 76, /* 12+ */ 79, 72) /* same in align1 */
336 F(3src_a16_src0_subreg_nr, /* 4+ */ 75, 73, /* 12+ */ -1, -1) /* Extra discontiguous bit on CHV? */
337 F(3src_a16_src0_swizzle, /* 4+ */ 72, 65, /* 12+ */ -1, -1)
338 F(3src_a16_src0_rep_ctrl, /* 4+ */ 64, 64, /* 12+ */ -1, -1)
339 F(3src_dst_reg_nr, /* 4+ */ 63, 56, /* 12+ */ 63, 56) /* same in align1 */
340 F(3src_a16_dst_subreg_nr, /* 4+ */ 55, 53, /* 12+ */ -1, -1)
341 F(3src_a16_dst_writemask, /* 4+ */ 52, 49, /* 12+ */ -1, -1)
342 F8(3src_a16_nib_ctrl, /* 4+ */ 47, 47, /* 8+ */ 11, 11, /* 12+ */ -1, -1) /* only exists on IVB+ */
343 F8(3src_a16_dst_hw_type, /* 4+ */ 45, 44, /* 8+ */ 48, 46, /* 12+ */ -1, -1) /* only exists on IVB+ */
344 F8(3src_a16_src_hw_type, /* 4+ */ 43, 42, /* 8+ */ 45, 43, /* 12+ */ -1, -1)
345 F8(3src_src2_negate, /* 4+ */ 41, 41, /* 8+ */ 42, 42, /* 12+ */ 85, 85)
346 F8(3src_src2_abs, /* 4+ */ 40, 40, /* 8+ */ 41, 41, /* 12+ */ 84, 84)
347 F8(3src_src1_negate, /* 4+ */ 39, 39, /* 8+ */ 40, 40, /* 12+ */ 87, 87)
348 F8(3src_src1_abs, /* 4+ */ 38, 38, /* 8+ */ 39, 39, /* 12+ */ 86, 86)
349 F8(3src_src0_negate, /* 4+ */ 37, 37, /* 8+ */ 38, 38, /* 12+ */ 45, 45)
350 F8(3src_src0_abs, /* 4+ */ 36, 36, /* 8+ */ 37, 37, /* 12+ */ 44, 44)
351 F8(3src_a16_src1_type, /* 4+ */ -1, -1, /* 8+ */ 36, 36, /* 12+ */ -1, -1)
352 F8(3src_a16_src2_type, /* 4+ */ -1, -1, /* 8+ */ 35, 35, /* 12+ */ -1, -1)
353 F8(3src_a16_flag_reg_nr, /* 4+ */ 34, 34, /* 8+ */ 33, 33, /* 12+ */ -1, -1)
354 F8(3src_a16_flag_subreg_nr, /* 4+ */ 33, 33, /* 8+ */ 32, 32, /* 12+ */ -1, -1)
355 FF(3src_a16_dst_reg_file,
356 /* 4-5: doesn't exist - no 3-source instructions */ -1, -1, -1, -1, -1, -1,
357 /* 6: */ 32, 32,
358 /* 7-8: doesn't exist - no MRFs */ -1, -1, -1, -1,
359 /* 12: */ -1, -1)
360 F(3src_saturate, /* 4+ */ 31, 31, /* 12+ */ 34, 34)
361 F(3src_debug_control, /* 4+ */ 30, 30, /* 12+ */ 30, 30)
362 F(3src_cmpt_control, /* 4+ */ 29, 29, /* 12+ */ 29, 29)
363 F(3src_acc_wr_control, /* 4+ */ 28, 28, /* 12+ */ 33, 33)
364 F(3src_cond_modifier, /* 4+ */ 27, 24, /* 12+ */ 95, 92)
365 F(3src_exec_size, /* 4+ */ 23, 21, /* 12+ */ 18, 16)
366 F(3src_pred_inv, /* 4+ */ 20, 20, /* 12+ */ 28, 28)
367 F(3src_pred_control, /* 4+ */ 19, 16, /* 12+ */ 27, 24)
368 F(3src_thread_control, /* 4+ */ 15, 14, /* 12+ */ -1, -1)
369 F(3src_atomic_control, /* 4+ */ -1, -1, /* 12+ */ 32, 32)
370 F(3src_qtr_control, /* 4+ */ 13, 12, /* 12+ */ 21, 20)
371 F8(3src_no_dd_check, /* 4+ */ 11, 11, /* 8+ */ 10, 10, /* 12+ */ -1, -1)
372 F8(3src_no_dd_clear, /* 4+ */ 10, 10, /* 8+ */ 9, 9, /* 12+ */ -1, -1)
373 F8(3src_mask_control, /* 4+ */ 9, 9, /* 8+ */ 34, 34, /* 12+ */ 31, 31)
374 FK(3src_access_mode, /* 4+ */ 8, 8, /* 12+ */ BRW_ALIGN_1)
375 F(3src_swsb, /* 4+ */ -1, -1, /* 12+ */ 15, 8)
376 /* Bit 7 is Reserved (for future Opcode expansion) */
377 F(3src_hw_opcode, /* 4+ */ 6, 0, /* 12+ */ 6, 0)
378 /** @} */
379
380 #define REG_TYPE(reg) \
381 static inline void \
382 brw_inst_set_3src_a16_##reg##_type(const struct gen_device_info *devinfo, \
383 brw_inst *inst, enum brw_reg_type type) \
384 { \
385 unsigned hw_type = brw_reg_type_to_a16_hw_3src_type(devinfo, type); \
386 brw_inst_set_3src_a16_##reg##_hw_type(devinfo, inst, hw_type); \
387 } \
388 \
389 static inline enum brw_reg_type \
390 brw_inst_3src_a16_##reg##_type(const struct gen_device_info *devinfo, \
391 const brw_inst *inst) \
392 { \
393 unsigned hw_type = brw_inst_3src_a16_##reg##_hw_type(devinfo, inst); \
394 return brw_a16_hw_3src_type_to_reg_type(devinfo, hw_type); \
395 }
396
397 REG_TYPE(dst)
398 REG_TYPE(src)
399 #undef REG_TYPE
400
401 /**
402 * Three-source align1 instructions:
403 * @{
404 */
405 /* Reserved 127:126 */
406 /* src2_reg_nr same in align16 */
407 FC(3src_a1_src2_subreg_nr, /* 4+ */ 117, 113, /* 12+ */ 119, 115, devinfo->gen >= 10)
408 FC(3src_a1_src2_hstride, /* 4+ */ 112, 111, /* 12+ */ 113, 112, devinfo->gen >= 10)
409 /* Reserved 110:109. src2 vstride is an implied parameter */
410 FC(3src_a1_src2_hw_type, /* 4+ */ 108, 106, /* 12+ */ 82, 80, devinfo->gen >= 10)
411 /* Reserved 105 */
412 /* src1_reg_nr same in align16 */
413 FC(3src_a1_src1_subreg_nr, /* 4+ */ 96, 92, /* 12+ */ 103, 99, devinfo->gen >= 10)
414 FC(3src_a1_src1_hstride, /* 4+ */ 91, 90, /* 12+ */ 97, 96, devinfo->gen >= 10)
415 FDC(3src_a1_src1_vstride, /* 4+ */ 89, 88, /* 12+ */ 91, 91, 83, 83, devinfo->gen >= 10)
416 FC(3src_a1_src1_hw_type, /* 4+ */ 87, 85, /* 12+ */ 90, 88, devinfo->gen >= 10)
417 /* Reserved 84 */
418 /* src0_reg_nr same in align16 */
419 FC(3src_a1_src0_subreg_nr, /* 4+ */ 75, 71, /* 12+ */ 71, 67, devinfo->gen >= 10)
420 FC(3src_a1_src0_hstride, /* 4+ */ 70, 69, /* 12+ */ 65, 64, devinfo->gen >= 10)
421 FDC(3src_a1_src0_vstride, /* 4+ */ 68, 67, /* 12+ */ 43, 43, 35, 35, devinfo->gen >= 10)
422 FC(3src_a1_src0_hw_type, /* 4+ */ 66, 64, /* 12+ */ 42, 40, devinfo->gen >= 10)
423 /* dst_reg_nr same in align16 */
424 FC(3src_a1_dst_subreg_nr, /* 4+ */ 55, 54, /* 12+ */ 55, 54, devinfo->gen >= 10)
425 FC(3src_a1_special_acc, /* 4+ */ 55, 52, /* 12+ */ 54, 51, devinfo->gen >= 10) /* aliases dst_subreg_nr */
426 /* Reserved 51:50 */
427 FC(3src_a1_dst_hstride, /* 4+ */ 49, 49, /* 12+ */ 48, 48, devinfo->gen >= 10)
428 FC(3src_a1_dst_hw_type, /* 4+ */ 48, 46, /* 12+ */ 38, 36, devinfo->gen >= 10)
429 FI(3src_a1_src2_reg_file, /* 4+ */ -1, -1, /* 8+ */ 45, 45, /* 12+ */ 47, 114)
430 FC(3src_a1_src1_reg_file, /* 4+ */ 44, 44, /* 12+ */ 98, 98, devinfo->gen >= 10)
431 FI(3src_a1_src0_reg_file, /* 4+ */ -1, -1, /* 8+ */ 43, 43, /* 12+ */ 46, 66)
432
433 F(3src_a1_src2_is_imm, /* 4+ */ -1, -1, /* 12+ */ 47, 47)
434 F(3src_a1_src0_is_imm, /* 4+ */ -1, -1, /* 12+ */ 46, 46)
435
436 /* Source Modifier fields same in align16 */
437 FC(3src_a1_dst_reg_file, /* 4+ */ 36, 36, /* 12+ */ 50, 50, devinfo->gen >= 10)
438 FC(3src_a1_exec_type, /* 4+ */ 35, 35, /* 12+ */ 39, 39, devinfo->gen >= 10)
439 /* Fields below this same in align16 */
440 /** @} */
441
442 #define REG_TYPE(reg) \
443 static inline void \
444 brw_inst_set_3src_a1_##reg##_type(const struct gen_device_info *devinfo, \
445 brw_inst *inst, enum brw_reg_type type) \
446 { \
447 UNUSED enum gen10_align1_3src_exec_type exec_type = \
448 (enum gen10_align1_3src_exec_type) brw_inst_3src_a1_exec_type(devinfo, \
449 inst); \
450 if (brw_reg_type_is_floating_point(type)) { \
451 assert(exec_type == BRW_ALIGN1_3SRC_EXEC_TYPE_FLOAT); \
452 } else { \
453 assert(exec_type == BRW_ALIGN1_3SRC_EXEC_TYPE_INT); \
454 } \
455 unsigned hw_type = brw_reg_type_to_a1_hw_3src_type(devinfo, type); \
456 brw_inst_set_3src_a1_##reg##_hw_type(devinfo, inst, hw_type); \
457 } \
458 \
459 static inline enum brw_reg_type \
460 brw_inst_3src_a1_##reg##_type(const struct gen_device_info *devinfo, \
461 const brw_inst *inst) \
462 { \
463 enum gen10_align1_3src_exec_type exec_type = \
464 (enum gen10_align1_3src_exec_type) brw_inst_3src_a1_exec_type(devinfo, \
465 inst); \
466 unsigned hw_type = brw_inst_3src_a1_##reg##_hw_type(devinfo, inst); \
467 return brw_a1_hw_3src_type_to_reg_type(devinfo, hw_type, exec_type); \
468 }
469
470 REG_TYPE(dst)
471 REG_TYPE(src0)
472 REG_TYPE(src1)
473 REG_TYPE(src2)
474 #undef REG_TYPE
475
476 /**
477 * Three-source align1 instruction immediates:
478 * @{
479 */
480 static inline uint16_t
481 brw_inst_3src_a1_src0_imm(ASSERTED const struct gen_device_info *devinfo,
482 const brw_inst *insn)
483 {
484 assert(devinfo->gen >= 10);
485 if (devinfo->gen >= 12)
486 return brw_inst_bits(insn, 79, 64);
487 else
488 return brw_inst_bits(insn, 82, 67);
489 }
490
491 static inline uint16_t
492 brw_inst_3src_a1_src2_imm(ASSERTED const struct gen_device_info *devinfo,
493 const brw_inst *insn)
494 {
495 assert(devinfo->gen >= 10);
496 if (devinfo->gen >= 12)
497 return brw_inst_bits(insn, 127, 112);
498 else
499 return brw_inst_bits(insn, 124, 109);
500 }
501
502 static inline void
503 brw_inst_set_3src_a1_src0_imm(ASSERTED const struct gen_device_info *devinfo,
504 brw_inst *insn, uint16_t value)
505 {
506 assert(devinfo->gen >= 10);
507 if (devinfo->gen >= 12)
508 brw_inst_set_bits(insn, 79, 64, value);
509 else
510 brw_inst_set_bits(insn, 82, 67, value);
511 }
512
513 static inline void
514 brw_inst_set_3src_a1_src2_imm(ASSERTED const struct gen_device_info *devinfo,
515 brw_inst *insn, uint16_t value)
516 {
517 assert(devinfo->gen >= 10);
518 if (devinfo->gen >= 12)
519 brw_inst_set_bits(insn, 127, 112, value);
520 else
521 brw_inst_set_bits(insn, 124, 109, value);
522 }
523 /** @} */
524
525 /**
526 * Flow control instruction bits:
527 * @{
528 */
529 static inline void
530 brw_inst_set_uip(const struct gen_device_info *devinfo,
531 brw_inst *inst, int32_t value)
532 {
533 assert(devinfo->gen >= 6);
534
535 if (devinfo->gen >= 12)
536 brw_inst_set_src1_is_imm(devinfo, inst, 1);
537
538 if (devinfo->gen >= 8) {
539 brw_inst_set_bits(inst, 95, 64, (uint32_t)value);
540 } else {
541 assert(value <= (1 << 16) - 1);
542 assert(value > -(1 << 16));
543 brw_inst_set_bits(inst, 127, 112, (uint16_t)value);
544 }
545 }
546
547 static inline int32_t
548 brw_inst_uip(const struct gen_device_info *devinfo, const brw_inst *inst)
549 {
550 assert(devinfo->gen >= 6);
551
552 if (devinfo->gen >= 8) {
553 return brw_inst_bits(inst, 95, 64);
554 } else {
555 return (int16_t)brw_inst_bits(inst, 127, 112);
556 }
557 }
558
559 static inline void
560 brw_inst_set_jip(const struct gen_device_info *devinfo,
561 brw_inst *inst, int32_t value)
562 {
563 assert(devinfo->gen >= 6);
564
565 if (devinfo->gen >= 12)
566 brw_inst_set_src0_is_imm(devinfo, inst, 1);
567
568 if (devinfo->gen >= 8) {
569 brw_inst_set_bits(inst, 127, 96, (uint32_t)value);
570 } else {
571 assert(value <= (1 << 15) - 1);
572 assert(value >= -(1 << 15));
573 brw_inst_set_bits(inst, 111, 96, (uint16_t)value);
574 }
575 }
576
577 static inline int32_t
578 brw_inst_jip(const struct gen_device_info *devinfo, const brw_inst *inst)
579 {
580 assert(devinfo->gen >= 6);
581
582 if (devinfo->gen >= 8) {
583 return brw_inst_bits(inst, 127, 96);
584 } else {
585 return (int16_t)brw_inst_bits(inst, 111, 96);
586 }
587 }
588
589 /** Like FC, but using int16_t to handle negative jump targets. */
590 #define FJ(name, high, low, assertions) \
591 static inline void \
592 brw_inst_set_##name(const struct gen_device_info *devinfo, brw_inst *inst, int16_t v) \
593 { \
594 assert(assertions); \
595 (void) devinfo; \
596 brw_inst_set_bits(inst, high, low, (uint16_t) v); \
597 } \
598 static inline int16_t \
599 brw_inst_##name(const struct gen_device_info *devinfo, const brw_inst *inst) \
600 { \
601 assert(assertions); \
602 (void) devinfo; \
603 return brw_inst_bits(inst, high, low); \
604 }
605
606 FJ(gen6_jump_count, 63, 48, devinfo->gen == 6)
607 FJ(gen4_jump_count, 111, 96, devinfo->gen < 6)
608 FC(gen4_pop_count, /* 4+ */ 115, 112, /* 12+ */ -1, -1, devinfo->gen < 6)
609 /** @} */
610
611 /**
612 * SEND instructions:
613 * @{
614 */
615 FC(send_ex_desc_ia_subreg_nr, /* 4+ */ 82, 80, /* 12+ */ 42, 40, devinfo->gen >= 9)
616 FC(send_src0_address_mode, /* 4+ */ 79, 79, /* 12+ */ -1, -1, devinfo->gen >= 9)
617 FC(send_sel_reg32_desc, /* 4+ */ 77, 77, /* 12+ */ 48, 48, devinfo->gen >= 9)
618 FC(send_sel_reg32_ex_desc, /* 4+ */ 61, 61, /* 12+ */ 49, 49, devinfo->gen >= 9)
619 F8(send_src0_reg_file, /* 4+ */ 38, 37, /* 8+ */ 42, 41, /* 12+ */ 66, 66)
620 FC(send_src1_reg_nr, /* 4+ */ 51, 44, /* 12+ */ 111, 104, devinfo->gen >= 9)
621 FC(send_src1_reg_file, /* 4+ */ 36, 36, /* 12+ */ 98, 98, devinfo->gen >= 9)
622 FC(send_dst_reg_file, /* 4+ */ 35, 35, /* 12+ */ 50, 50, devinfo->gen >= 9)
623 /** @} */
624
625 /* Message descriptor bits */
626 #define MD(x) ((x) + 96)
627 #define MD12(x) ((x) >= 30 ? (x) - 30 + 122 : \
628 (x) >= 25 ? (x) - 25 + 67 : \
629 (x) >= 20 ? (x) - 20 + 51 : \
630 (x) >= 11 ? (x) - 11 + 113 : \
631 (x) - 0 + 81)
632
633 /**
634 * Set the SEND(C) message descriptor immediate.
635 *
636 * This doesn't include the SFID nor the EOT field that were considered to be
637 * part of the message descriptor by ancient versions of the BSpec, because
638 * they are present in the instruction even if the message descriptor is
639 * provided indirectly in the address register, so we want to specify them
640 * separately.
641 */
642 static inline void
643 brw_inst_set_send_desc(const struct gen_device_info *devinfo,
644 brw_inst *inst, uint32_t value)
645 {
646 if (devinfo->gen >= 12) {
647 brw_inst_set_bits(inst, 123, 122, GET_BITS(value, 31, 30));
648 brw_inst_set_bits(inst, 71, 67, GET_BITS(value, 29, 25));
649 brw_inst_set_bits(inst, 55, 51, GET_BITS(value, 24, 20));
650 brw_inst_set_bits(inst, 121, 113, GET_BITS(value, 19, 11));
651 brw_inst_set_bits(inst, 91, 81, GET_BITS(value, 10, 0));
652 } else if (devinfo->gen >= 9) {
653 brw_inst_set_bits(inst, 126, 96, value);
654 assert(value >> 31 == 0);
655 } else if (devinfo->gen >= 5) {
656 brw_inst_set_bits(inst, 124, 96, value);
657 assert(value >> 29 == 0);
658 } else {
659 brw_inst_set_bits(inst, 119, 96, value);
660 assert(value >> 24 == 0);
661 }
662 }
663
664 /**
665 * Get the SEND(C) message descriptor immediate.
666 *
667 * \sa brw_inst_set_send_desc().
668 */
669 static inline uint32_t
670 brw_inst_send_desc(const struct gen_device_info *devinfo, const brw_inst *inst)
671 {
672 if (devinfo->gen >= 12) {
673 return (brw_inst_bits(inst, 123, 122) << 30 |
674 brw_inst_bits(inst, 71, 67) << 25 |
675 brw_inst_bits(inst, 55, 51) << 20 |
676 brw_inst_bits(inst, 121, 113) << 11 |
677 brw_inst_bits(inst, 91, 81));
678 } else if (devinfo->gen >= 9) {
679 return brw_inst_bits(inst, 126, 96);
680 } else if (devinfo->gen >= 5) {
681 return brw_inst_bits(inst, 124, 96);
682 } else {
683 return brw_inst_bits(inst, 119, 96);
684 }
685 }
686
687 /**
688 * Set the SEND(C) message extended descriptor immediate.
689 *
690 * This doesn't include the SFID nor the EOT field that were considered to be
691 * part of the extended message descriptor by some versions of the BSpec,
692 * because they are present in the instruction even if the extended message
693 * descriptor is provided indirectly in a register, so we want to specify them
694 * separately.
695 */
696 static inline void
697 brw_inst_set_send_ex_desc(const struct gen_device_info *devinfo,
698 brw_inst *inst, uint32_t value)
699 {
700 if (devinfo->gen >= 12) {
701 brw_inst_set_bits(inst, 127, 124, GET_BITS(value, 31, 28));
702 brw_inst_set_bits(inst, 97, 96, GET_BITS(value, 27, 26));
703 brw_inst_set_bits(inst, 65, 64, GET_BITS(value, 25, 24));
704 brw_inst_set_bits(inst, 47, 35, GET_BITS(value, 23, 11));
705 brw_inst_set_bits(inst, 103, 99, GET_BITS(value, 10, 6));
706 assert(GET_BITS(value, 5, 0) == 0);
707 } else {
708 assert(devinfo->gen >= 9);
709 brw_inst_set_bits(inst, 94, 91, GET_BITS(value, 31, 28));
710 brw_inst_set_bits(inst, 88, 85, GET_BITS(value, 27, 24));
711 brw_inst_set_bits(inst, 83, 80, GET_BITS(value, 23, 20));
712 brw_inst_set_bits(inst, 67, 64, GET_BITS(value, 19, 16));
713 assert(GET_BITS(value, 15, 0) == 0);
714 }
715 }
716
717 /**
718 * Set the SENDS(C) message extended descriptor immediate.
719 *
720 * This doesn't include the SFID nor the EOT field that were considered to be
721 * part of the extended message descriptor by some versions of the BSpec,
722 * because they are present in the instruction even if the extended message
723 * descriptor is provided indirectly in a register, so we want to specify them
724 * separately.
725 */
726 static inline void
727 brw_inst_set_sends_ex_desc(const struct gen_device_info *devinfo,
728 brw_inst *inst, uint32_t value)
729 {
730 if (devinfo->gen >= 12) {
731 brw_inst_set_send_ex_desc(devinfo, inst, value);
732 } else {
733 brw_inst_set_bits(inst, 95, 80, GET_BITS(value, 31, 16));
734 assert(GET_BITS(value, 15, 10) == 0);
735 brw_inst_set_bits(inst, 67, 64, GET_BITS(value, 9, 6));
736 assert(GET_BITS(value, 5, 0) == 0);
737 }
738 }
739
740 /**
741 * Get the SEND(C) message extended descriptor immediate.
742 *
743 * \sa brw_inst_set_send_ex_desc().
744 */
745 static inline uint32_t
746 brw_inst_send_ex_desc(const struct gen_device_info *devinfo,
747 const brw_inst *inst)
748 {
749 if (devinfo->gen >= 12) {
750 return (brw_inst_bits(inst, 127, 124) << 28 |
751 brw_inst_bits(inst, 97, 96) << 26 |
752 brw_inst_bits(inst, 65, 64) << 24 |
753 brw_inst_bits(inst, 47, 35) << 11 |
754 brw_inst_bits(inst, 103, 99) << 6);
755 } else {
756 assert(devinfo->gen >= 9);
757 return (brw_inst_bits(inst, 94, 91) << 28 |
758 brw_inst_bits(inst, 88, 85) << 24 |
759 brw_inst_bits(inst, 83, 80) << 20 |
760 brw_inst_bits(inst, 67, 64) << 16);
761 }
762 }
763
764 /**
765 * Get the SENDS(C) message extended descriptor immediate.
766 *
767 * \sa brw_inst_set_send_ex_desc().
768 */
769 static inline uint32_t
770 brw_inst_sends_ex_desc(const struct gen_device_info *devinfo,
771 const brw_inst *inst)
772 {
773 if (devinfo->gen >= 12) {
774 return brw_inst_send_ex_desc(devinfo, inst);
775 } else {
776 return (brw_inst_bits(inst, 95, 80) << 16 |
777 brw_inst_bits(inst, 67, 64) << 6);
778 }
779 }
780
781 /**
782 * Fields for SEND messages:
783 * @{
784 */
785 F(eot, /* 4+ */ 127, 127, /* 12+ */ 34, 34)
786 FF(mlen,
787 /* 4: */ 119, 116,
788 /* 4.5: */ 119, 116,
789 /* 5: */ 124, 121,
790 /* 6: */ 124, 121,
791 /* 7: */ 124, 121,
792 /* 8: */ 124, 121,
793 /* 12: */ MD12(28), MD12(25));
794 FF(rlen,
795 /* 4: */ 115, 112,
796 /* 4.5: */ 115, 112,
797 /* 5: */ 120, 116,
798 /* 6: */ 120, 116,
799 /* 7: */ 120, 116,
800 /* 8: */ 120, 116,
801 /* 12: */ MD12(24), MD12(20));
802 FF(header_present,
803 /* 4: doesn't exist */ -1, -1, -1, -1,
804 /* 5: */ 115, 115,
805 /* 6: */ 115, 115,
806 /* 7: */ 115, 115,
807 /* 8: */ 115, 115,
808 /* 12: */ MD12(19), MD12(19))
809 F(gateway_notify, /* 4+ */ MD(16), MD(15), /* 12+ */ -1, -1)
810 FD(function_control,
811 /* 4: */ 111, 96,
812 /* 4.5: */ 111, 96,
813 /* 5: */ 114, 96,
814 /* 6: */ 114, 96,
815 /* 7: */ 114, 96,
816 /* 8: */ 114, 96,
817 /* 12: */ MD12(18), MD12(11), MD12(10), MD12(0))
818 FF(gateway_subfuncid,
819 /* 4: */ MD(1), MD(0),
820 /* 4.5: */ MD(1), MD(0),
821 /* 5: */ MD(1), MD(0), /* 2:0, but bit 2 is reserved MBZ */
822 /* 6: */ MD(2), MD(0),
823 /* 7: */ MD(2), MD(0),
824 /* 8: */ MD(2), MD(0),
825 /* 12: */ MD12(2), MD12(0))
826 FF(sfid,
827 /* 4: */ 123, 120, /* called msg_target */
828 /* 4.5 */ 123, 120,
829 /* 5: */ 95, 92,
830 /* 6: */ 27, 24,
831 /* 7: */ 27, 24,
832 /* 8: */ 27, 24,
833 /* 12: */ 95, 92)
834 FF(null_rt,
835 /* 4-7: */ -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
836 /* 8: */ 80, 80,
837 /* 12: */ 44, 44) /* actually only Gen11+ */
838 FC(base_mrf, /* 4+ */ 27, 24, /* 12+ */ -1, -1, devinfo->gen < 6);
839 FF(send_rta_index,
840 /* 4: */ -1, -1,
841 /* 4.5 */ -1, -1,
842 /* 5: */ -1, -1,
843 /* 6: */ -1, -1,
844 /* 7: */ -1, -1,
845 /* 8: */ -1, -1,
846 /* 12: */ 38, 36)
847 /** @} */
848
849 /**
850 * URB message function control bits:
851 * @{
852 */
853 FF(urb_per_slot_offset,
854 /* 4-6: */ -1, -1, -1, -1, -1, -1, -1, -1,
855 /* 7: */ MD(16), MD(16),
856 /* 8: */ MD(17), MD(17),
857 /* 12: */ MD12(17), MD12(17))
858 FC(urb_channel_mask_present, /* 4+ */ MD(15), MD(15), /* 12+ */ MD12(15), MD12(15), devinfo->gen >= 8)
859 FC(urb_complete, /* 4+ */ MD(15), MD(15), /* 12+ */ -1, -1, devinfo->gen < 8)
860 FC(urb_used, /* 4+ */ MD(14), MD(14), /* 12+ */ -1, -1, devinfo->gen < 7)
861 FC(urb_allocate, /* 4+ */ MD(13), MD(13), /* 12+ */ -1, -1, devinfo->gen < 7)
862 FF(urb_swizzle_control,
863 /* 4: */ MD(11), MD(10),
864 /* 4.5: */ MD(11), MD(10),
865 /* 5: */ MD(11), MD(10),
866 /* 6: */ MD(11), MD(10),
867 /* 7: */ MD(14), MD(14),
868 /* 8: */ MD(15), MD(15),
869 /* 12: */ -1, -1)
870 FD(urb_global_offset,
871 /* 4: */ MD( 9), MD(4),
872 /* 4.5: */ MD( 9), MD(4),
873 /* 5: */ MD( 9), MD(4),
874 /* 6: */ MD( 9), MD(4),
875 /* 7: */ MD(13), MD(3),
876 /* 8: */ MD(14), MD(4),
877 /* 12: */ MD12(14), MD12(11), MD12(10), MD12(4))
878 FF(urb_opcode,
879 /* 4: */ MD( 3), MD(0),
880 /* 4.5: */ MD( 3), MD(0),
881 /* 5: */ MD( 3), MD(0),
882 /* 6: */ MD( 3), MD(0),
883 /* 7: */ MD( 2), MD(0),
884 /* 8: */ MD( 3), MD(0),
885 /* 12: */ MD12(3), MD12(0))
886 /** @} */
887
888 /**
889 * Gen4-5 math messages:
890 * @{
891 */
892 FC(math_msg_data_type, /* 4+ */ MD(7), MD(7), /* 12+ */ -1, -1, devinfo->gen < 6)
893 FC(math_msg_saturate, /* 4+ */ MD(6), MD(6), /* 12+ */ -1, -1, devinfo->gen < 6)
894 FC(math_msg_precision, /* 4+ */ MD(5), MD(5), /* 12+ */ -1, -1, devinfo->gen < 6)
895 FC(math_msg_signed_int, /* 4+ */ MD(4), MD(4), /* 12+ */ -1, -1, devinfo->gen < 6)
896 FC(math_msg_function, /* 4+ */ MD(3), MD(0), /* 12+ */ -1, -1, devinfo->gen < 6)
897 /** @} */
898
899 /**
900 * Sampler message function control bits:
901 * @{
902 */
903 FF(sampler_simd_mode,
904 /* 4: doesn't exist */ -1, -1, -1, -1,
905 /* 5: */ MD(17), MD(16),
906 /* 6: */ MD(17), MD(16),
907 /* 7: */ MD(18), MD(17),
908 /* 8: */ MD(18), MD(17),
909 /* 12: */ MD12(18), MD12(17))
910 FF(sampler_msg_type,
911 /* 4: */ MD(15), MD(14),
912 /* 4.5: */ MD(15), MD(12),
913 /* 5: */ MD(15), MD(12),
914 /* 6: */ MD(15), MD(12),
915 /* 7: */ MD(16), MD(12),
916 /* 8: */ MD(16), MD(12),
917 /* 12: */ MD12(16), MD12(12))
918 FC(sampler_return_format, /* 4+ */ MD(13), MD(12), /* 12+ */ -1, -1, devinfo->gen == 4 && !devinfo->is_g4x)
919 FD(sampler,
920 /* 4: */ MD(11), MD(8),
921 /* 4.5: */ MD(11), MD(8),
922 /* 5: */ MD(11), MD(8),
923 /* 6: */ MD(11), MD(8),
924 /* 7: */ MD(11), MD(8),
925 /* 8: */ MD(11), MD(8),
926 /* 12: */ MD12(11), MD12(11), MD12(10), MD12(8))
927 F(binding_table_index, /* 4+ */ MD(7), MD(0), /* 12+ */ MD12(7), MD12(0)) /* also used by other messages */
928 /** @} */
929
930 /**
931 * Data port message function control bits:
932 * @{
933 */
934 FC(dp_category, /* 4+ */ MD(18), MD(18), /* 12+ */ MD12(18), MD12(18), devinfo->gen >= 7)
935
936 /* Gen4-5 store fields in different bits for read/write messages. */
937 FF(dp_read_msg_type,
938 /* 4: */ MD(13), MD(12),
939 /* 4.5: */ MD(13), MD(11),
940 /* 5: */ MD(13), MD(11),
941 /* 6: */ MD(16), MD(13),
942 /* 7: */ MD(17), MD(14),
943 /* 8: */ MD(17), MD(14),
944 /* 12: */ MD12(17), MD12(14))
945 FF(dp_write_msg_type,
946 /* 4: */ MD(14), MD(12),
947 /* 4.5: */ MD(14), MD(12),
948 /* 5: */ MD(14), MD(12),
949 /* 6: */ MD(16), MD(13),
950 /* 7: */ MD(17), MD(14),
951 /* 8: */ MD(17), MD(14),
952 /* 12: */ MD12(17), MD12(14))
953 FD(dp_read_msg_control,
954 /* 4: */ MD(11), MD( 8),
955 /* 4.5: */ MD(10), MD( 8),
956 /* 5: */ MD(10), MD( 8),
957 /* 6: */ MD(12), MD( 8),
958 /* 7: */ MD(13), MD( 8),
959 /* 8: */ MD(13), MD( 8),
960 /* 12: */ MD12(13), MD12(11), MD12(10), MD12(8))
961 FD(dp_write_msg_control,
962 /* 4: */ MD(11), MD( 8),
963 /* 4.5: */ MD(11), MD( 8),
964 /* 5: */ MD(11), MD( 8),
965 /* 6: */ MD(12), MD( 8),
966 /* 7: */ MD(13), MD( 8),
967 /* 8: */ MD(13), MD( 8),
968 /* 12: */ MD12(13), MD12(11), MD12(10), MD12(8))
969 FC(dp_read_target_cache, /* 4+ */ MD(15), MD(14), /* 12+ */ -1, -1, devinfo->gen < 6);
970
971 FF(dp_write_commit,
972 /* 4: */ MD(15), MD(15),
973 /* 4.5: */ MD(15), MD(15),
974 /* 5: */ MD(15), MD(15),
975 /* 6: */ MD(17), MD(17),
976 /* 7+: does not exist */ -1, -1, -1, -1,
977 /* 12: */ -1, -1)
978
979 /* Gen6+ use the same bit locations for everything. */
980 FF(dp_msg_type,
981 /* 4-5: use dp_read_msg_type or dp_write_msg_type instead */
982 -1, -1, -1, -1, -1, -1,
983 /* 6: */ MD(16), MD(13),
984 /* 7: */ MD(17), MD(14),
985 /* 8: */ MD(18), MD(14),
986 /* 12: */ MD12(18), MD12(14))
987 FD(dp_msg_control,
988 /* 4: */ MD(11), MD( 8),
989 /* 4.5-5: use dp_read_msg_control or dp_write_msg_control */ -1, -1, -1, -1,
990 /* 6: */ MD(12), MD( 8),
991 /* 7: */ MD(13), MD( 8),
992 /* 8: */ MD(13), MD( 8),
993 /* 12: */ MD12(13), MD12(11), MD12(10), MD12(8))
994 /** @} */
995
996 /**
997 * Scratch message bits (Gen7+):
998 * @{
999 */
1000 FC(scratch_read_write, /* 4+ */ MD(17), MD(17), /* 12+ */ MD12(17), MD12(17), devinfo->gen >= 7) /* 0 = read, 1 = write */
1001 FC(scratch_type, /* 4+ */ MD(16), MD(16), /* 12+ */ -1, -1, devinfo->gen >= 7) /* 0 = OWord, 1 = DWord */
1002 FC(scratch_invalidate_after_read, /* 4+ */ MD(15), MD(15), /* 12+ */ MD12(15), MD12(15), devinfo->gen >= 7)
1003 FC(scratch_block_size, /* 4+ */ MD(13), MD(12), /* 12+ */ MD12(13), MD12(12), devinfo->gen >= 7)
1004 FD(scratch_addr_offset,
1005 /* 4: */ -1, -1,
1006 /* 4.5: */ -1, -1,
1007 /* 5: */ -1, -1,
1008 /* 6: */ -1, -1,
1009 /* 7: */ MD(11), MD(0),
1010 /* 8: */ MD(11), MD(0),
1011 /* 12: */ MD12(11), MD12(11), MD12(10), MD12(0))
1012 /** @} */
1013
1014 /**
1015 * Render Target message function control bits:
1016 * @{
1017 */
1018 FF(rt_last,
1019 /* 4: */ MD(11), MD(11),
1020 /* 4.5: */ MD(11), MD(11),
1021 /* 5: */ MD(11), MD(11),
1022 /* 6: */ MD(12), MD(12),
1023 /* 7: */ MD(12), MD(12),
1024 /* 8: */ MD(12), MD(12),
1025 /* 12: */ MD12(12), MD12(12))
1026 FC(rt_slot_group, /* 4+ */ MD(11), MD(11), /* 12+ */ MD12(11), MD12(11), devinfo->gen >= 6)
1027 F(rt_message_type, /* 4+ */ MD(10), MD( 8), /* 12+ */ MD12(10), MD12(8))
1028 /** @} */
1029
1030 /**
1031 * Thread Spawn message function control bits:
1032 * @{
1033 */
1034 F(ts_resource_select, /* 4+ */ MD( 4), MD( 4), /* 12+ */ -1, -1)
1035 F(ts_request_type, /* 4+ */ MD( 1), MD( 1), /* 12+ */ -1, -1)
1036 F(ts_opcode, /* 4+ */ MD( 0), MD( 0), /* 12+ */ MD12(0), MD12(0))
1037 /** @} */
1038
1039 /**
1040 * Pixel Interpolator message function control bits:
1041 * @{
1042 */
1043 F(pi_simd_mode, /* 4+ */ MD(16), MD(16), /* 12+ */ MD12(16), MD12(16))
1044 F(pi_nopersp, /* 4+ */ MD(14), MD(14), /* 12+ */ MD12(14), MD12(14))
1045 F(pi_message_type, /* 4+ */ MD(13), MD(12), /* 12+ */ MD12(13), MD12(12))
1046 F(pi_slot_group, /* 4+ */ MD(11), MD(11), /* 12+ */ MD12(11), MD12(11))
1047 F(pi_message_data, /* 4+ */ MD(7), MD(0), /* 12+ */ MD12(7), MD12(0))
1048 /** @} */
1049
1050 /**
1051 * Immediates:
1052 * @{
1053 */
1054 static inline int
1055 brw_inst_imm_d(const struct gen_device_info *devinfo, const brw_inst *insn)
1056 {
1057 (void) devinfo;
1058 return brw_inst_bits(insn, 127, 96);
1059 }
1060
1061 static inline unsigned
1062 brw_inst_imm_ud(const struct gen_device_info *devinfo, const brw_inst *insn)
1063 {
1064 (void) devinfo;
1065 return brw_inst_bits(insn, 127, 96);
1066 }
1067
1068 static inline uint64_t
1069 brw_inst_imm_uq(ASSERTED const struct gen_device_info *devinfo,
1070 const brw_inst *insn)
1071 {
1072 assert(devinfo->gen >= 8);
1073 return brw_inst_bits(insn, 127, 64);
1074 }
1075
1076 static inline float
1077 brw_inst_imm_f(const struct gen_device_info *devinfo, const brw_inst *insn)
1078 {
1079 union {
1080 float f;
1081 uint32_t u;
1082 } ft;
1083 (void) devinfo;
1084 ft.u = brw_inst_bits(insn, 127, 96);
1085 return ft.f;
1086 }
1087
1088 static inline double
1089 brw_inst_imm_df(const struct gen_device_info *devinfo, const brw_inst *insn)
1090 {
1091 union {
1092 double d;
1093 uint64_t u;
1094 } dt;
1095 (void) devinfo;
1096 dt.u = brw_inst_bits(insn, 127, 64);
1097 return dt.d;
1098 }
1099
1100 static inline void
1101 brw_inst_set_imm_d(const struct gen_device_info *devinfo,
1102 brw_inst *insn, int value)
1103 {
1104 (void) devinfo;
1105 return brw_inst_set_bits(insn, 127, 96, value);
1106 }
1107
1108 static inline void
1109 brw_inst_set_imm_ud(const struct gen_device_info *devinfo,
1110 brw_inst *insn, unsigned value)
1111 {
1112 (void) devinfo;
1113 return brw_inst_set_bits(insn, 127, 96, value);
1114 }
1115
1116 static inline void
1117 brw_inst_set_imm_f(const struct gen_device_info *devinfo,
1118 brw_inst *insn, float value)
1119 {
1120 union {
1121 float f;
1122 uint32_t u;
1123 } ft;
1124 (void) devinfo;
1125 ft.f = value;
1126 brw_inst_set_bits(insn, 127, 96, ft.u);
1127 }
1128
1129 static inline void
1130 brw_inst_set_imm_df(const struct gen_device_info *devinfo,
1131 brw_inst *insn, double value)
1132 {
1133 union {
1134 double d;
1135 uint64_t u;
1136 } dt;
1137 (void) devinfo;
1138 dt.d = value;
1139 brw_inst_set_bits(insn, 127, 64, dt.u);
1140 }
1141
1142 static inline void
1143 brw_inst_set_imm_uq(const struct gen_device_info *devinfo,
1144 brw_inst *insn, uint64_t value)
1145 {
1146 (void) devinfo;
1147 brw_inst_set_bits(insn, 127, 64, value);
1148 }
1149
1150 /** @} */
1151
1152 #define REG_TYPE(reg) \
1153 static inline void \
1154 brw_inst_set_##reg##_file_type(const struct gen_device_info *devinfo, \
1155 brw_inst *inst, enum brw_reg_file file, \
1156 enum brw_reg_type type) \
1157 { \
1158 assert(file <= BRW_IMMEDIATE_VALUE); \
1159 unsigned hw_type = brw_reg_type_to_hw_type(devinfo, file, type); \
1160 brw_inst_set_##reg##_reg_file(devinfo, inst, file); \
1161 brw_inst_set_##reg##_reg_hw_type(devinfo, inst, hw_type); \
1162 } \
1163 \
1164 static inline enum brw_reg_type \
1165 brw_inst_##reg##_type(const struct gen_device_info *devinfo, \
1166 const brw_inst *inst) \
1167 { \
1168 unsigned file = __builtin_strcmp("dst", #reg) == 0 ? \
1169 (unsigned) BRW_GENERAL_REGISTER_FILE : \
1170 brw_inst_##reg##_reg_file(devinfo, inst); \
1171 unsigned hw_type = brw_inst_##reg##_reg_hw_type(devinfo, inst); \
1172 return brw_hw_type_to_reg_type(devinfo, (enum brw_reg_file)file, hw_type); \
1173 }
1174
1175 REG_TYPE(dst)
1176 REG_TYPE(src0)
1177 REG_TYPE(src1)
1178 #undef REG_TYPE
1179
1180
1181 /* The AddrImm fields are split into two discontiguous sections on Gen8+ */
1182 #define BRW_IA1_ADDR_IMM(reg, g4_high, g4_low, g8_nine, g8_high, g8_low) \
1183 static inline void \
1184 brw_inst_set_##reg##_ia1_addr_imm(const struct gen_device_info *devinfo, \
1185 brw_inst *inst, \
1186 unsigned value) \
1187 { \
1188 assert((value & ~0x3ff) == 0); \
1189 if (devinfo->gen >= 8) { \
1190 brw_inst_set_bits(inst, g8_high, g8_low, value & 0x1ff); \
1191 brw_inst_set_bits(inst, g8_nine, g8_nine, value >> 9); \
1192 } else { \
1193 brw_inst_set_bits(inst, g4_high, g4_low, value); \
1194 } \
1195 } \
1196 static inline unsigned \
1197 brw_inst_##reg##_ia1_addr_imm(const struct gen_device_info *devinfo, \
1198 const brw_inst *inst) \
1199 { \
1200 if (devinfo->gen >= 8) { \
1201 return brw_inst_bits(inst, g8_high, g8_low) | \
1202 (brw_inst_bits(inst, g8_nine, g8_nine) << 9); \
1203 } else { \
1204 return brw_inst_bits(inst, g4_high, g4_low); \
1205 } \
1206 }
1207
1208 /* AddrImm[9:0] for Align1 Indirect Addressing */
1209 /* -Gen 4- ----Gen8---- */
1210 BRW_IA1_ADDR_IMM(src1, 105, 96, 121, 104, 96)
1211 BRW_IA1_ADDR_IMM(src0, 73, 64, 95, 72, 64)
1212 BRW_IA1_ADDR_IMM(dst, 57, 48, 47, 56, 48)
1213
1214 #define BRW_IA16_ADDR_IMM(reg, g4_high, g4_low, g8_nine, g8_high, g8_low) \
1215 static inline void \
1216 brw_inst_set_##reg##_ia16_addr_imm(const struct gen_device_info *devinfo, \
1217 brw_inst *inst, unsigned value) \
1218 { \
1219 assert((value & ~0x3ff) == 0); \
1220 if (devinfo->gen >= 8) { \
1221 assert(GET_BITS(value, 3, 0) == 0); \
1222 brw_inst_set_bits(inst, g8_high, g8_low, GET_BITS(value, 8, 4)); \
1223 brw_inst_set_bits(inst, g8_nine, g8_nine, GET_BITS(value, 9, 9)); \
1224 } else { \
1225 brw_inst_set_bits(inst, g4_high, g4_low, value); \
1226 } \
1227 } \
1228 static inline unsigned \
1229 brw_inst_##reg##_ia16_addr_imm(const struct gen_device_info *devinfo, \
1230 const brw_inst *inst) \
1231 { \
1232 if (devinfo->gen >= 8) { \
1233 return (brw_inst_bits(inst, g8_high, g8_low) << 4) | \
1234 (brw_inst_bits(inst, g8_nine, g8_nine) << 9); \
1235 } else { \
1236 return brw_inst_bits(inst, g4_high, g4_low); \
1237 } \
1238 }
1239
1240 /* AddrImm[9:0] for Align16 Indirect Addressing:
1241 * Compared to Align1, these are missing the low 4 bits.
1242 * -Gen 4- ----Gen8----
1243 */
1244 BRW_IA16_ADDR_IMM(src1, 105, 96, 121, 104, 100)
1245 BRW_IA16_ADDR_IMM(src0, 73, 64, 95, 72, 68)
1246 BRW_IA16_ADDR_IMM(dst, 57, 52, 47, 56, 52)
1247 BRW_IA16_ADDR_IMM(send_src0, -1, -1, 78, 72, 68)
1248 BRW_IA16_ADDR_IMM(send_dst, -1, -1, 62, 56, 52)
1249
1250 /**
1251 * Fetch a set of contiguous bits from the instruction.
1252 *
1253 * Bits indices range from 0..127; fields may not cross 64-bit boundaries.
1254 */
1255 static inline uint64_t
1256 brw_inst_bits(const brw_inst *inst, unsigned high, unsigned low)
1257 {
1258 assert(high >= low);
1259 /* We assume the field doesn't cross 64-bit boundaries. */
1260 const unsigned word = high / 64;
1261 assert(word == low / 64);
1262
1263 high %= 64;
1264 low %= 64;
1265
1266 const uint64_t mask = (~0ull >> (64 - (high - low + 1)));
1267
1268 return (inst->data[word] >> low) & mask;
1269 }
1270
1271 /**
1272 * Set bits in the instruction, with proper shifting and masking.
1273 *
1274 * Bits indices range from 0..127; fields may not cross 64-bit boundaries.
1275 */
1276 static inline void
1277 brw_inst_set_bits(brw_inst *inst, unsigned high, unsigned low, uint64_t value)
1278 {
1279 assert(high >= low);
1280 const unsigned word = high / 64;
1281 assert(word == low / 64);
1282
1283 high %= 64;
1284 low %= 64;
1285
1286 const uint64_t mask = (~0ull >> (64 - (high - low + 1))) << low;
1287
1288 /* Make sure the supplied value actually fits in the given bitfield. */
1289 assert((value & (mask >> low)) == value);
1290
1291 inst->data[word] = (inst->data[word] & ~mask) | (value << low);
1292 }
1293
1294 #undef BRW_IA16_ADDR_IMM
1295 #undef BRW_IA1_ADDR_IMM
1296 #undef MD
1297 #undef F8
1298 #undef FF
1299 #undef BOUNDS
1300 #undef F
1301 #undef FC
1302
1303 typedef struct {
1304 uint64_t data;
1305 } brw_compact_inst;
1306
1307 /**
1308 * Fetch a set of contiguous bits from the compacted instruction.
1309 *
1310 * Bits indices range from 0..63.
1311 */
1312 static inline unsigned
1313 brw_compact_inst_bits(const brw_compact_inst *inst, unsigned high, unsigned low)
1314 {
1315 const uint64_t mask = (1ull << (high - low + 1)) - 1;
1316
1317 return (inst->data >> low) & mask;
1318 }
1319
1320 /**
1321 * Set bits in the compacted instruction.
1322 *
1323 * Bits indices range from 0..63.
1324 */
1325 static inline void
1326 brw_compact_inst_set_bits(brw_compact_inst *inst, unsigned high, unsigned low,
1327 uint64_t value)
1328 {
1329 const uint64_t mask = ((1ull << (high - low + 1)) - 1) << low;
1330
1331 /* Make sure the supplied value actually fits in the given bitfield. */
1332 assert((value & (mask >> low)) == value);
1333
1334 inst->data = (inst->data & ~mask) | (value << low);
1335 }
1336
1337 #define FC(name, high, low, assertions) \
1338 static inline void \
1339 brw_compact_inst_set_##name(const struct gen_device_info *devinfo, \
1340 brw_compact_inst *inst, unsigned v) \
1341 { \
1342 assert(assertions); \
1343 (void) devinfo; \
1344 brw_compact_inst_set_bits(inst, high, low, v); \
1345 } \
1346 static inline unsigned \
1347 brw_compact_inst_##name(const struct gen_device_info *devinfo, \
1348 const brw_compact_inst *inst) \
1349 { \
1350 assert(assertions); \
1351 (void) devinfo; \
1352 return brw_compact_inst_bits(inst, high, low); \
1353 }
1354
1355 /* A simple macro for fields which stay in the same place on all generations. */
1356 #define F(name, high, low) FC(name, high, low, true)
1357
1358 F(src1_reg_nr, 63, 56)
1359 F(src0_reg_nr, 55, 48)
1360 F(dst_reg_nr, 47, 40)
1361 F(src1_index, 39, 35)
1362 F(src0_index, 34, 30)
1363 F(cmpt_control, 29, 29) /* Same location as brw_inst */
1364 FC(flag_subreg_nr, 28, 28, devinfo->gen <= 6)
1365 F(cond_modifier, 27, 24) /* Same location as brw_inst */
1366 FC(acc_wr_control, 23, 23, devinfo->gen >= 6)
1367 FC(mask_control_ex, 23, 23, devinfo->is_g4x || devinfo->gen == 5)
1368 F(subreg_index, 22, 18)
1369 F(datatype_index, 17, 13)
1370 F(control_index, 12, 8)
1371 F(debug_control, 7, 7)
1372 F(hw_opcode, 6, 0) /* Same location as brw_inst */
1373
1374 /**
1375 * (Gen8+) Compacted three-source instructions:
1376 * @{
1377 */
1378 FC(3src_src2_reg_nr, 63, 57, devinfo->gen >= 8)
1379 FC(3src_src1_reg_nr, 56, 50, devinfo->gen >= 8)
1380 FC(3src_src0_reg_nr, 49, 43, devinfo->gen >= 8)
1381 FC(3src_src2_subreg_nr, 42, 40, devinfo->gen >= 8)
1382 FC(3src_src1_subreg_nr, 39, 37, devinfo->gen >= 8)
1383 FC(3src_src0_subreg_nr, 36, 34, devinfo->gen >= 8)
1384 FC(3src_src2_rep_ctrl, 33, 33, devinfo->gen >= 8)
1385 FC(3src_src1_rep_ctrl, 32, 32, devinfo->gen >= 8)
1386 FC(3src_saturate, 31, 31, devinfo->gen >= 8)
1387 FC(3src_debug_control, 30, 30, devinfo->gen >= 8)
1388 FC(3src_cmpt_control, 29, 29, devinfo->gen >= 8)
1389 FC(3src_src0_rep_ctrl, 28, 28, devinfo->gen >= 8)
1390 /* Reserved */
1391 FC(3src_dst_reg_nr, 18, 12, devinfo->gen >= 8)
1392 FC(3src_source_index, 11, 10, devinfo->gen >= 8)
1393 FC(3src_control_index, 9, 8, devinfo->gen >= 8)
1394 /* Bit 7 is Reserved (for future Opcode expansion) */
1395 FC(3src_hw_opcode, 6, 0, devinfo->gen >= 8)
1396 /** @} */
1397
1398 #undef F
1399
1400 #ifdef __cplusplus
1401 }
1402 #endif
1403
1404 #endif