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intel/eu/gen12: Implement three-source instruction binary encoding.
[mesa.git] / src / intel / compiler / brw_inst.h
1 /*
2 * Copyright © 2014 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 */
23
24 /**
25 * @file brw_inst.h
26 *
27 * A representation of i965 EU assembly instructions, with helper methods to
28 * get and set various fields. This is the actual hardware format.
29 */
30
31 #ifndef BRW_INST_H
32 #define BRW_INST_H
33
34 #include <assert.h>
35 #include <stdint.h>
36
37 #include "brw_eu_defines.h"
38 #include "brw_reg_type.h"
39 #include "dev/gen_device_info.h"
40
41 #ifdef __cplusplus
42 extern "C" {
43 #endif
44
45 /* brw_context.h has a forward declaration of brw_inst, so name the struct. */
46 typedef struct brw_inst {
47 uint64_t data[2];
48 } brw_inst;
49
50 static inline uint64_t brw_inst_bits(const brw_inst *inst,
51 unsigned high, unsigned low);
52 static inline void brw_inst_set_bits(brw_inst *inst,
53 unsigned high, unsigned low,
54 uint64_t value);
55
56 #define FC(name, hi4, lo4, hi12, lo12, assertions) \
57 static inline void \
58 brw_inst_set_##name(const struct gen_device_info *devinfo, \
59 brw_inst *inst, uint64_t v) \
60 { \
61 assert(assertions); \
62 if (devinfo->gen >= 12) \
63 brw_inst_set_bits(inst, hi12, lo12, v); \
64 else \
65 brw_inst_set_bits(inst, hi4, lo4, v); \
66 } \
67 static inline uint64_t \
68 brw_inst_##name(const struct gen_device_info *devinfo, \
69 const brw_inst *inst) \
70 { \
71 assert(assertions); \
72 if (devinfo->gen >= 12) \
73 return brw_inst_bits(inst, hi12, lo12); \
74 else \
75 return brw_inst_bits(inst, hi4, lo4); \
76 }
77
78 /* A simple macro for fields which stay in the same place on all generations,
79 * except for Gen12!
80 */
81 #define F(name, hi4, lo4, hi12, lo12) FC(name, hi4, lo4, hi12, lo12, true)
82
83 #define BOUNDS(hi4, lo4, hi45, lo45, hi5, lo5, hi6, lo6, \
84 hi7, lo7, hi8, lo8, hi12, lo12) \
85 unsigned high, low; \
86 if (devinfo->gen >= 12) { \
87 high = hi12; low = lo12; \
88 } else if (devinfo->gen >= 8) { \
89 high = hi8; low = lo8; \
90 } else if (devinfo->gen >= 7) { \
91 high = hi7; low = lo7; \
92 } else if (devinfo->gen >= 6) { \
93 high = hi6; low = lo6; \
94 } else if (devinfo->gen >= 5) { \
95 high = hi5; low = lo5; \
96 } else if (devinfo->is_g4x) { \
97 high = hi45; low = lo45; \
98 } else { \
99 high = hi4; low = lo4; \
100 } \
101 assert(((int) high) != -1 && ((int) low) != -1);
102
103 /* A general macro for cases where the field has moved to several different
104 * bit locations across generations. GCC appears to combine cases where the
105 * bits are identical, removing some of the inefficiency.
106 */
107 #define FF(name, hi4, lo4, hi45, lo45, hi5, lo5, hi6, lo6, \
108 hi7, lo7, hi8, lo8, hi12, lo12) \
109 static inline void \
110 brw_inst_set_##name(const struct gen_device_info *devinfo, \
111 brw_inst *inst, uint64_t value) \
112 { \
113 BOUNDS(hi4, lo4, hi45, lo45, hi5, lo5, hi6, lo6, \
114 hi7, lo7, hi8, lo8, hi12, lo12) \
115 brw_inst_set_bits(inst, high, low, value); \
116 } \
117 static inline uint64_t \
118 brw_inst_##name(const struct gen_device_info *devinfo, const brw_inst *inst) \
119 { \
120 BOUNDS(hi4, lo4, hi45, lo45, hi5, lo5, hi6, lo6, \
121 hi7, lo7, hi8, lo8, hi12, lo12) \
122 return brw_inst_bits(inst, high, low); \
123 }
124
125 /* A macro for fields which moved as of Gen8+. */
126 #define F8(name, gen4_high, gen4_low, gen8_high, gen8_low, \
127 gen12_high, gen12_low) \
128 FF(name, \
129 /* 4: */ gen4_high, gen4_low, \
130 /* 4.5: */ gen4_high, gen4_low, \
131 /* 5: */ gen4_high, gen4_low, \
132 /* 6: */ gen4_high, gen4_low, \
133 /* 7: */ gen4_high, gen4_low, \
134 /* 8: */ gen8_high, gen8_low, \
135 /* 12: */ gen12_high, gen12_low);
136
137 /* Macro for fields that gained extra discontiguous MSBs in Gen12 (specified
138 * by hi12ex-lo12ex).
139 */
140 #define FFDC(name, hi4, lo4, hi45, lo45, hi5, lo5, hi6, lo6, \
141 hi7, lo7, hi8, lo8, hi12ex, lo12ex, hi12, lo12, assertions) \
142 static inline void \
143 brw_inst_set_##name(const struct gen_device_info *devinfo, \
144 brw_inst *inst, uint64_t value) \
145 { \
146 assert(assertions); \
147 if (devinfo->gen >= 12) { \
148 const unsigned k = hi12 - lo12 + 1; \
149 if (hi12ex != -1 && lo12ex != -1) \
150 brw_inst_set_bits(inst, hi12ex, lo12ex, value >> k); \
151 brw_inst_set_bits(inst, hi12, lo12, value & ((1ull << k) - 1)); \
152 } else { \
153 BOUNDS(hi4, lo4, hi45, lo45, hi5, lo5, hi6, lo6, \
154 hi7, lo7, hi8, lo8, -1, -1); \
155 brw_inst_set_bits(inst, high, low, value); \
156 } \
157 } \
158 static inline uint64_t \
159 brw_inst_##name(const struct gen_device_info *devinfo, const brw_inst *inst) \
160 { \
161 assert(assertions); \
162 if (devinfo->gen >= 12) { \
163 const unsigned k = hi12 - lo12 + 1; \
164 return (hi12ex == -1 || lo12ex == -1 ? 0 : \
165 brw_inst_bits(inst, hi12ex, lo12ex) << k) | \
166 brw_inst_bits(inst, hi12, lo12); \
167 } else { \
168 BOUNDS(hi4, lo4, hi45, lo45, hi5, lo5, hi6, lo6, \
169 hi7, lo7, hi8, lo8, -1, -1); \
170 return brw_inst_bits(inst, high, low); \
171 } \
172 }
173
174 #define FD(name, hi4, lo4, hi45, lo45, hi5, lo5, hi6, lo6, \
175 hi7, lo7, hi8, lo8, hi12ex, lo12ex, hi12, lo12) \
176 FFDC(name, hi4, lo4, hi45, lo45, hi5, lo5, hi6, lo6, \
177 hi7, lo7, hi8, lo8, hi12ex, lo12ex, hi12, lo12, true)
178
179 /* Macro for fields that didn't move across generations until Gen12, and then
180 * gained extra discontiguous bits.
181 */
182 #define FDC(name, hi4, lo4, hi12ex, lo12ex, hi12, lo12, assertions) \
183 FFDC(name, hi4, lo4, hi4, lo4, hi4, lo4, hi4, lo4, \
184 hi4, lo4, hi4, lo4, hi12ex, lo12ex, hi12, lo12, assertions)
185
186
187 /* Macro for the 2-bit register file field, which on Gen12+ is stored as the
188 * variable length combination of an IsImm (hi12) bit and an additional file
189 * (lo12) bit.
190 */
191 #define FI(name, hi4, lo4, hi8, lo8, hi12, lo12) \
192 static inline void \
193 brw_inst_set_##name(const struct gen_device_info *devinfo, \
194 brw_inst *inst, uint64_t value) \
195 { \
196 if (devinfo->gen >= 12) { \
197 brw_inst_set_bits(inst, hi12, hi12, value >> 1); \
198 if ((value >> 1) == 0) \
199 brw_inst_set_bits(inst, lo12, lo12, value & 1); \
200 } else { \
201 BOUNDS(hi4, lo4, hi4, lo4, hi4, lo4, hi4, lo4, \
202 hi4, lo4, hi8, lo8, -1, -1); \
203 brw_inst_set_bits(inst, high, low, value); \
204 } \
205 } \
206 static inline uint64_t \
207 brw_inst_##name(const struct gen_device_info *devinfo, const brw_inst *inst) \
208 { \
209 if (devinfo->gen >= 12) { \
210 return (brw_inst_bits(inst, hi12, hi12) << 1) | \
211 (brw_inst_bits(inst, hi12, hi12) == 0 ? \
212 brw_inst_bits(inst, lo12, lo12) : 1); \
213 } else { \
214 BOUNDS(hi4, lo4, hi4, lo4, hi4, lo4, hi4, lo4, \
215 hi4, lo4, hi8, lo8, -1, -1); \
216 return brw_inst_bits(inst, high, low); \
217 } \
218 }
219
220 /* Macro for fields that become a constant in Gen12+ not actually represented
221 * in the instruction.
222 */
223 #define FK(name, hi4, lo4, const12) \
224 static inline void \
225 brw_inst_set_##name(const struct gen_device_info *devinfo, \
226 brw_inst *inst, uint64_t v) \
227 { \
228 if (devinfo->gen >= 12) \
229 assert(v == (const12)); \
230 else \
231 brw_inst_set_bits(inst, hi4, lo4, v); \
232 } \
233 static inline uint64_t \
234 brw_inst_##name(const struct gen_device_info *devinfo, \
235 const brw_inst *inst) \
236 { \
237 if (devinfo->gen >= 12) \
238 return (const12); \
239 else \
240 return brw_inst_bits(inst, hi4, lo4); \
241 }
242
243 F(src1_vstride, /* 4+ */ 120, 117, /* 12+ */ 119, 116)
244 F(src1_width, /* 4+ */ 116, 114, /* 12+ */ 115, 113)
245 F(src1_da16_swiz_w, /* 4+ */ 115, 114, /* 12+ */ -1, -1)
246 F(src1_da16_swiz_z, /* 4+ */ 113, 112, /* 12+ */ -1, -1)
247 F(src1_hstride, /* 4+ */ 113, 112, /* 12+ */ 97, 96)
248 F(src1_address_mode, /* 4+ */ 111, 111, /* 12+ */ 112, 112)
249 /** Src1.SrcMod @{ */
250 F(src1_negate, /* 4+ */ 110, 110, /* 12+ */ 121, 121)
251 F(src1_abs, /* 4+ */ 109, 109, /* 12+ */ 120, 120)
252 /** @} */
253 F8(src1_ia_subreg_nr, /* 4+ */ 108, 106, /* 8+ */ 108, 105, /* 12+ */ 111, 108)
254 F(src1_da_reg_nr, /* 4+ */ 108, 101, /* 12+ */ 111, 104)
255 F(src1_da16_subreg_nr, /* 4+ */ 100, 100, /* 12+ */ -1, -1)
256 F(src1_da1_subreg_nr, /* 4+ */ 100, 96, /* 12+ */ 103, 99)
257 F(src1_da16_swiz_y, /* 4+ */ 99, 98, /* 12+ */ -1, -1)
258 F(src1_da16_swiz_x, /* 4+ */ 97, 96, /* 12+ */ -1, -1)
259 F8(src1_reg_hw_type, /* 4+ */ 46, 44, /* 8+ */ 94, 91, /* 12+ */ 91, 88)
260 FI(src1_reg_file, /* 4+ */ 43, 42, /* 8+ */ 90, 89, /* 12+ */ 47, 98)
261 F(src1_is_imm, /* 4+ */ -1, -1, /* 12+ */ 47, 47)
262 F(src0_vstride, /* 4+ */ 88, 85, /* 12+ */ 87, 84)
263 F(src0_width, /* 4+ */ 84, 82, /* 12+ */ 83, 81)
264 F(src0_da16_swiz_w, /* 4+ */ 83, 82, /* 12+ */ -1, -1)
265 F(src0_da16_swiz_z, /* 4+ */ 81, 80, /* 12+ */ -1, -1)
266 F(src0_hstride, /* 4+ */ 81, 80, /* 12+ */ 65, 64)
267 F(src0_address_mode, /* 4+ */ 79, 79, /* 12+ */ 80, 80)
268 /** Src0.SrcMod @{ */
269 F(src0_negate, /* 4+ */ 78, 78, /* 12+ */ 45, 45)
270 F(src0_abs, /* 4+ */ 77, 77, /* 12+ */ 44, 44)
271 /** @} */
272 F8(src0_ia_subreg_nr, /* 4+ */ 76, 74, /* 8+ */ 76, 73, /* 12+ */ 79, 76)
273 F(src0_da_reg_nr, /* 4+ */ 76, 69, /* 12+ */ 79, 72)
274 F(src0_da16_subreg_nr, /* 4+ */ 68, 68, /* 12+ */ -1, -1)
275 F(src0_da1_subreg_nr, /* 4+ */ 68, 64, /* 12+ */ 71, 67)
276 F(src0_da16_swiz_y, /* 4+ */ 67, 66, /* 12+ */ -1, -1)
277 F(src0_da16_swiz_x, /* 4+ */ 65, 64, /* 12+ */ -1, -1)
278 F(dst_address_mode, /* 4+ */ 63, 63, /* 12+ */ 35, 35)
279 F(dst_hstride, /* 4+ */ 62, 61, /* 12+ */ 49, 48)
280 F8(dst_ia_subreg_nr, /* 4+ */ 60, 58, /* 8+ */ 60, 57, /* 12+ */ 63, 60)
281 F(dst_da_reg_nr, /* 4+ */ 60, 53, /* 12+ */ 63, 56)
282 F(dst_da16_subreg_nr, /* 4+ */ 52, 52, /* 12+ */ -1, -1)
283 F(dst_da1_subreg_nr, /* 4+ */ 52, 48, /* 12+ */ 55, 51)
284 F(da16_writemask, /* 4+ */ 51, 48, /* 12+ */ -1, -1) /* Dst.ChanEn */
285 F8(src0_reg_hw_type, /* 4+ */ 41, 39, /* 8+ */ 46, 43, /* 12+ */ 43, 40)
286 FI(src0_reg_file, /* 4+ */ 38, 37, /* 8+ */ 42, 41, /* 12+ */ 46, 66)
287 F(src0_is_imm, /* 4+ */ -1, -1, /* 12+ */ 46, 46)
288 F8(dst_reg_hw_type, /* 4+ */ 36, 34, /* 8+ */ 40, 37, /* 12+ */ 39, 36)
289 F8(dst_reg_file, /* 4+ */ 33, 32, /* 8+ */ 36, 35, /* 12+ */ 50, 50)
290 F8(mask_control, /* 4+ */ 9, 9, /* 8+ */ 34, 34, /* 12+ */ 31, 31)
291 FF(flag_reg_nr,
292 /* 4-6: doesn't exist */ -1, -1, -1, -1, -1, -1, -1, -1,
293 /* 7: */ 90, 90,
294 /* 8: */ 33, 33,
295 /* 12: */ 23, 23)
296 F8(flag_subreg_nr, /* 4+ */ 89, 89, /* 8+ */ 32, 32, /* 12+ */ 22, 22)
297 F(saturate, /* 4+ */ 31, 31, /* 12+ */ 34, 34)
298 F(debug_control, /* 4+ */ 30, 30, /* 12+ */ 30, 30)
299 F(cmpt_control, /* 4+ */ 29, 29, /* 12+ */ 29, 29)
300 FC(branch_control, /* 4+ */ 28, 28, /* 12+ */ 33, 33, devinfo->gen >= 8)
301 FC(acc_wr_control, /* 4+ */ 28, 28, /* 12+ */ 33, 33, devinfo->gen >= 6)
302 FC(mask_control_ex, /* 4+ */ 28, 28, /* 12+ */ -1, -1, devinfo->is_g4x || devinfo->gen == 5)
303 F(cond_modifier, /* 4+ */ 27, 24, /* 12+ */ 95, 92)
304 FC(math_function, /* 4+ */ 27, 24, /* 12+ */ 95, 92, devinfo->gen >= 6)
305 F(exec_size, /* 4+ */ 23, 21, /* 12+ */ 18, 16)
306 F(pred_inv, /* 4+ */ 20, 20, /* 12+ */ 28, 28)
307 F(pred_control, /* 4+ */ 19, 16, /* 12+ */ 27, 24)
308 F(thread_control, /* 4+ */ 15, 14, /* 12+ */ -1, -1)
309 F(atomic_control, /* 4+ */ -1, -1, /* 12+ */ 32, 32)
310 F(qtr_control, /* 4+ */ 13, 12, /* 12+ */ 21, 20)
311 FF(nib_control,
312 /* 4-6: doesn't exist */ -1, -1, -1, -1, -1, -1, -1, -1,
313 /* 7: */ 47, 47,
314 /* 8: */ 11, 11,
315 /* 12: */ 19, 19)
316 F8(no_dd_check, /* 4+ */ 11, 11, /* 8+ */ 10, 10, /* 12+ */ -1, -1)
317 F8(no_dd_clear, /* 4+ */ 10, 10, /* 8+ */ 9, 9, /* 12+ */ -1, -1)
318 F(swsb, /* 4+ */ -1, -1, /* 12+ */ 15, 8)
319 FK(access_mode, /* 4+ */ 8, 8, /* 12+ */ BRW_ALIGN_1)
320 /* Bit 7 is Reserved (for future Opcode expansion) */
321 F(hw_opcode, /* 4+ */ 6, 0, /* 12+ */ 6, 0)
322
323 /**
324 * Three-source instructions:
325 * @{
326 */
327 F(3src_src2_reg_nr, /* 4+ */ 125, 118, /* 12+ */ 127, 120) /* same in align1 */
328 F(3src_a16_src2_subreg_nr, /* 4+ */ 117, 115, /* 12+ */ -1, -1) /* Extra discontiguous bit on CHV? */
329 F(3src_a16_src2_swizzle, /* 4+ */ 114, 107, /* 12+ */ -1, -1)
330 F(3src_a16_src2_rep_ctrl, /* 4+ */ 106, 106, /* 12+ */ -1, -1)
331 F(3src_src1_reg_nr, /* 4+ */ 104, 97, /* 12+ */ 111, 104) /* same in align1 */
332 F(3src_a16_src1_subreg_nr, /* 4+ */ 96, 94, /* 12+ */ -1, -1) /* Extra discontiguous bit on CHV? */
333 F(3src_a16_src1_swizzle, /* 4+ */ 93, 86, /* 12+ */ -1, -1)
334 F(3src_a16_src1_rep_ctrl, /* 4+ */ 85, 85, /* 12+ */ -1, -1)
335 F(3src_src0_reg_nr, /* 4+ */ 83, 76, /* 12+ */ 79, 72) /* same in align1 */
336 F(3src_a16_src0_subreg_nr, /* 4+ */ 75, 73, /* 12+ */ -1, -1) /* Extra discontiguous bit on CHV? */
337 F(3src_a16_src0_swizzle, /* 4+ */ 72, 65, /* 12+ */ -1, -1)
338 F(3src_a16_src0_rep_ctrl, /* 4+ */ 64, 64, /* 12+ */ -1, -1)
339 F(3src_dst_reg_nr, /* 4+ */ 63, 56, /* 12+ */ 63, 56) /* same in align1 */
340 F(3src_a16_dst_subreg_nr, /* 4+ */ 55, 53, /* 12+ */ -1, -1)
341 F(3src_a16_dst_writemask, /* 4+ */ 52, 49, /* 12+ */ -1, -1)
342 F8(3src_a16_nib_ctrl, /* 4+ */ 47, 47, /* 8+ */ 11, 11, /* 12+ */ -1, -1) /* only exists on IVB+ */
343 F8(3src_a16_dst_hw_type, /* 4+ */ 45, 44, /* 8+ */ 48, 46, /* 12+ */ -1, -1) /* only exists on IVB+ */
344 F8(3src_a16_src_hw_type, /* 4+ */ 43, 42, /* 8+ */ 45, 43, /* 12+ */ -1, -1)
345 F8(3src_src2_negate, /* 4+ */ 41, 41, /* 8+ */ 42, 42, /* 12+ */ 85, 85)
346 F8(3src_src2_abs, /* 4+ */ 40, 40, /* 8+ */ 41, 41, /* 12+ */ 84, 84)
347 F8(3src_src1_negate, /* 4+ */ 39, 39, /* 8+ */ 40, 40, /* 12+ */ 87, 87)
348 F8(3src_src1_abs, /* 4+ */ 38, 38, /* 8+ */ 39, 39, /* 12+ */ 86, 86)
349 F8(3src_src0_negate, /* 4+ */ 37, 37, /* 8+ */ 38, 38, /* 12+ */ 45, 45)
350 F8(3src_src0_abs, /* 4+ */ 36, 36, /* 8+ */ 37, 37, /* 12+ */ 44, 44)
351 F8(3src_a16_src1_type, /* 4+ */ -1, -1, /* 8+ */ 36, 36, /* 12+ */ -1, -1)
352 F8(3src_a16_src2_type, /* 4+ */ -1, -1, /* 8+ */ 35, 35, /* 12+ */ -1, -1)
353 F8(3src_a16_flag_reg_nr, /* 4+ */ 34, 34, /* 8+ */ 33, 33, /* 12+ */ -1, -1)
354 F8(3src_a16_flag_subreg_nr, /* 4+ */ 33, 33, /* 8+ */ 32, 32, /* 12+ */ -1, -1)
355 FF(3src_a16_dst_reg_file,
356 /* 4-5: doesn't exist - no 3-source instructions */ -1, -1, -1, -1, -1, -1,
357 /* 6: */ 32, 32,
358 /* 7-8: doesn't exist - no MRFs */ -1, -1, -1, -1,
359 /* 12: */ -1, -1)
360 F(3src_saturate, /* 4+ */ 31, 31, /* 12+ */ 34, 34)
361 F(3src_debug_control, /* 4+ */ 30, 30, /* 12+ */ 30, 30)
362 F(3src_cmpt_control, /* 4+ */ 29, 29, /* 12+ */ 29, 29)
363 F(3src_acc_wr_control, /* 4+ */ 28, 28, /* 12+ */ 33, 33)
364 F(3src_cond_modifier, /* 4+ */ 27, 24, /* 12+ */ 95, 92)
365 F(3src_exec_size, /* 4+ */ 23, 21, /* 12+ */ 18, 16)
366 F(3src_pred_inv, /* 4+ */ 20, 20, /* 12+ */ 28, 28)
367 F(3src_pred_control, /* 4+ */ 19, 16, /* 12+ */ 27, 24)
368 F(3src_thread_control, /* 4+ */ 15, 14, /* 12+ */ -1, -1)
369 F(3src_atomic_control, /* 4+ */ -1, -1, /* 12+ */ 32, 32)
370 F(3src_qtr_control, /* 4+ */ 13, 12, /* 12+ */ 21, 20)
371 F8(3src_no_dd_check, /* 4+ */ 11, 11, /* 8+ */ 10, 10, /* 12+ */ -1, -1)
372 F8(3src_no_dd_clear, /* 4+ */ 10, 10, /* 8+ */ 9, 9, /* 12+ */ -1, -1)
373 F8(3src_mask_control, /* 4+ */ 9, 9, /* 8+ */ 34, 34, /* 12+ */ 31, 31)
374 FK(3src_access_mode, /* 4+ */ 8, 8, /* 12+ */ BRW_ALIGN_1)
375 F(3src_swsb, /* 4+ */ -1, -1, /* 12+ */ 15, 8)
376 /* Bit 7 is Reserved (for future Opcode expansion) */
377 F(3src_hw_opcode, /* 4+ */ 6, 0, /* 12+ */ 6, 0)
378 /** @} */
379
380 #define REG_TYPE(reg) \
381 static inline void \
382 brw_inst_set_3src_a16_##reg##_type(const struct gen_device_info *devinfo, \
383 brw_inst *inst, enum brw_reg_type type) \
384 { \
385 unsigned hw_type = brw_reg_type_to_a16_hw_3src_type(devinfo, type); \
386 brw_inst_set_3src_a16_##reg##_hw_type(devinfo, inst, hw_type); \
387 } \
388 \
389 static inline enum brw_reg_type \
390 brw_inst_3src_a16_##reg##_type(const struct gen_device_info *devinfo, \
391 const brw_inst *inst) \
392 { \
393 unsigned hw_type = brw_inst_3src_a16_##reg##_hw_type(devinfo, inst); \
394 return brw_a16_hw_3src_type_to_reg_type(devinfo, hw_type); \
395 }
396
397 REG_TYPE(dst)
398 REG_TYPE(src)
399 #undef REG_TYPE
400
401 /**
402 * Three-source align1 instructions:
403 * @{
404 */
405 /* Reserved 127:126 */
406 /* src2_reg_nr same in align16 */
407 FC(3src_a1_src2_subreg_nr, /* 4+ */ 117, 113, /* 12+ */ 119, 115, devinfo->gen >= 10)
408 FC(3src_a1_src2_hstride, /* 4+ */ 112, 111, /* 12+ */ 113, 112, devinfo->gen >= 10)
409 /* Reserved 110:109. src2 vstride is an implied parameter */
410 FC(3src_a1_src2_hw_type, /* 4+ */ 108, 106, /* 12+ */ 82, 80, devinfo->gen >= 10)
411 /* Reserved 105 */
412 /* src1_reg_nr same in align16 */
413 FC(3src_a1_src1_subreg_nr, /* 4+ */ 96, 92, /* 12+ */ 103, 99, devinfo->gen >= 10)
414 FC(3src_a1_src1_hstride, /* 4+ */ 91, 90, /* 12+ */ 97, 96, devinfo->gen >= 10)
415 FDC(3src_a1_src1_vstride, /* 4+ */ 89, 88, /* 12+ */ 91, 91, 83, 83, devinfo->gen >= 10)
416 FC(3src_a1_src1_hw_type, /* 4+ */ 87, 85, /* 12+ */ 90, 88, devinfo->gen >= 10)
417 /* Reserved 84 */
418 /* src0_reg_nr same in align16 */
419 FC(3src_a1_src0_subreg_nr, /* 4+ */ 75, 71, /* 12+ */ 71, 67, devinfo->gen >= 10)
420 FC(3src_a1_src0_hstride, /* 4+ */ 70, 69, /* 12+ */ 65, 64, devinfo->gen >= 10)
421 FDC(3src_a1_src0_vstride, /* 4+ */ 68, 67, /* 12+ */ 43, 43, 35, 35, devinfo->gen >= 10)
422 FC(3src_a1_src0_hw_type, /* 4+ */ 66, 64, /* 12+ */ 42, 40, devinfo->gen >= 10)
423 /* dst_reg_nr same in align16 */
424 FC(3src_a1_dst_subreg_nr, /* 4+ */ 55, 54, /* 12+ */ 55, 54, devinfo->gen >= 10)
425 FC(3src_a1_special_acc, /* 4+ */ 55, 52, /* 12+ */ 54, 51, devinfo->gen >= 10) /* aliases dst_subreg_nr */
426 /* Reserved 51:50 */
427 FC(3src_a1_dst_hstride, /* 4+ */ 49, 49, /* 12+ */ 48, 48, devinfo->gen >= 10)
428 FC(3src_a1_dst_hw_type, /* 4+ */ 48, 46, /* 12+ */ 38, 36, devinfo->gen >= 10)
429 FI(3src_a1_src2_reg_file, /* 4+ */ -1, -1, /* 8+ */ 45, 45, /* 12+ */ 47, 114)
430 FC(3src_a1_src1_reg_file, /* 4+ */ 44, 44, /* 12+ */ 98, 98, devinfo->gen >= 10)
431 FI(3src_a1_src0_reg_file, /* 4+ */ -1, -1, /* 8+ */ 43, 43, /* 12+ */ 46, 66)
432
433 F(3src_a1_src2_is_imm, /* 4+ */ -1, -1, /* 12+ */ 47, 47)
434 F(3src_a1_src0_is_imm, /* 4+ */ -1, -1, /* 12+ */ 46, 46)
435
436 /* Source Modifier fields same in align16 */
437 FC(3src_a1_dst_reg_file, /* 4+ */ 36, 36, /* 12+ */ 50, 50, devinfo->gen >= 10)
438 FC(3src_a1_exec_type, /* 4+ */ 35, 35, /* 12+ */ 39, 39, devinfo->gen >= 10)
439 /* Fields below this same in align16 */
440 /** @} */
441
442 #define REG_TYPE(reg) \
443 static inline void \
444 brw_inst_set_3src_a1_##reg##_type(const struct gen_device_info *devinfo, \
445 brw_inst *inst, enum brw_reg_type type) \
446 { \
447 UNUSED enum gen10_align1_3src_exec_type exec_type = \
448 (enum gen10_align1_3src_exec_type) brw_inst_3src_a1_exec_type(devinfo, \
449 inst); \
450 if (brw_reg_type_is_floating_point(type)) { \
451 assert(exec_type == BRW_ALIGN1_3SRC_EXEC_TYPE_FLOAT); \
452 } else { \
453 assert(exec_type == BRW_ALIGN1_3SRC_EXEC_TYPE_INT); \
454 } \
455 unsigned hw_type = brw_reg_type_to_a1_hw_3src_type(devinfo, type); \
456 brw_inst_set_3src_a1_##reg##_hw_type(devinfo, inst, hw_type); \
457 } \
458 \
459 static inline enum brw_reg_type \
460 brw_inst_3src_a1_##reg##_type(const struct gen_device_info *devinfo, \
461 const brw_inst *inst) \
462 { \
463 enum gen10_align1_3src_exec_type exec_type = \
464 (enum gen10_align1_3src_exec_type) brw_inst_3src_a1_exec_type(devinfo, \
465 inst); \
466 unsigned hw_type = brw_inst_3src_a1_##reg##_hw_type(devinfo, inst); \
467 return brw_a1_hw_3src_type_to_reg_type(devinfo, hw_type, exec_type); \
468 }
469
470 REG_TYPE(dst)
471 REG_TYPE(src0)
472 REG_TYPE(src1)
473 REG_TYPE(src2)
474 #undef REG_TYPE
475
476 /**
477 * Three-source align1 instruction immediates:
478 * @{
479 */
480 static inline uint16_t
481 brw_inst_3src_a1_src0_imm(ASSERTED const struct gen_device_info *devinfo,
482 const brw_inst *insn)
483 {
484 assert(devinfo->gen >= 10);
485 if (devinfo->gen >= 12)
486 return brw_inst_bits(insn, 79, 64);
487 else
488 return brw_inst_bits(insn, 82, 67);
489 }
490
491 static inline uint16_t
492 brw_inst_3src_a1_src2_imm(ASSERTED const struct gen_device_info *devinfo,
493 const brw_inst *insn)
494 {
495 assert(devinfo->gen >= 10);
496 if (devinfo->gen >= 12)
497 return brw_inst_bits(insn, 127, 112);
498 else
499 return brw_inst_bits(insn, 124, 109);
500 }
501
502 static inline void
503 brw_inst_set_3src_a1_src0_imm(ASSERTED const struct gen_device_info *devinfo,
504 brw_inst *insn, uint16_t value)
505 {
506 assert(devinfo->gen >= 10);
507 if (devinfo->gen >= 12)
508 brw_inst_set_bits(insn, 79, 64, value);
509 else
510 brw_inst_set_bits(insn, 82, 67, value);
511 }
512
513 static inline void
514 brw_inst_set_3src_a1_src2_imm(ASSERTED const struct gen_device_info *devinfo,
515 brw_inst *insn, uint16_t value)
516 {
517 assert(devinfo->gen >= 10);
518 if (devinfo->gen >= 12)
519 brw_inst_set_bits(insn, 127, 112, value);
520 else
521 brw_inst_set_bits(insn, 124, 109, value);
522 }
523 /** @} */
524
525 /**
526 * Flow control instruction bits:
527 * @{
528 */
529 static inline void
530 brw_inst_set_uip(const struct gen_device_info *devinfo,
531 brw_inst *inst, int32_t value)
532 {
533 assert(devinfo->gen >= 6);
534
535 if (devinfo->gen >= 8) {
536 brw_inst_set_bits(inst, 95, 64, (uint32_t)value);
537 } else {
538 assert(value <= (1 << 16) - 1);
539 assert(value > -(1 << 16));
540 brw_inst_set_bits(inst, 127, 112, (uint16_t)value);
541 }
542 }
543
544 static inline int32_t
545 brw_inst_uip(const struct gen_device_info *devinfo, const brw_inst *inst)
546 {
547 assert(devinfo->gen >= 6);
548
549 if (devinfo->gen >= 8) {
550 return brw_inst_bits(inst, 95, 64);
551 } else {
552 return (int16_t)brw_inst_bits(inst, 127, 112);
553 }
554 }
555
556 static inline void
557 brw_inst_set_jip(const struct gen_device_info *devinfo,
558 brw_inst *inst, int32_t value)
559 {
560 assert(devinfo->gen >= 6);
561
562 if (devinfo->gen >= 8) {
563 brw_inst_set_bits(inst, 127, 96, (uint32_t)value);
564 } else {
565 assert(value <= (1 << 15) - 1);
566 assert(value >= -(1 << 15));
567 brw_inst_set_bits(inst, 111, 96, (uint16_t)value);
568 }
569 }
570
571 static inline int32_t
572 brw_inst_jip(const struct gen_device_info *devinfo, const brw_inst *inst)
573 {
574 assert(devinfo->gen >= 6);
575
576 if (devinfo->gen >= 8) {
577 return brw_inst_bits(inst, 127, 96);
578 } else {
579 return (int16_t)brw_inst_bits(inst, 111, 96);
580 }
581 }
582
583 /** Like FC, but using int16_t to handle negative jump targets. */
584 #define FJ(name, high, low, assertions) \
585 static inline void \
586 brw_inst_set_##name(const struct gen_device_info *devinfo, brw_inst *inst, int16_t v) \
587 { \
588 assert(assertions); \
589 (void) devinfo; \
590 brw_inst_set_bits(inst, high, low, (uint16_t) v); \
591 } \
592 static inline int16_t \
593 brw_inst_##name(const struct gen_device_info *devinfo, const brw_inst *inst) \
594 { \
595 assert(assertions); \
596 (void) devinfo; \
597 return brw_inst_bits(inst, high, low); \
598 }
599
600 FJ(gen6_jump_count, 63, 48, devinfo->gen == 6)
601 FJ(gen4_jump_count, 111, 96, devinfo->gen < 6)
602 FC(gen4_pop_count, /* 4+ */ 115, 112, /* 12+ */ -1, -1, devinfo->gen < 6)
603 /** @} */
604
605 /**
606 * SEND instructions:
607 * @{
608 */
609 FC(send_ex_desc_ia_subreg_nr, /* 4+ */ 82, 80, /* 12+ */ -1, -1, devinfo->gen >= 9)
610 FC(send_src0_address_mode, /* 4+ */ 79, 79, /* 12+ */ -1, -1, devinfo->gen >= 9)
611 FC(send_sel_reg32_desc, /* 4+ */ 77, 77, /* 12+ */ -1, -1, devinfo->gen >= 9)
612 FC(send_sel_reg32_ex_desc, /* 4+ */ 61, 61, /* 12+ */ -1, -1, devinfo->gen >= 9)
613 FC(send_src1_reg_nr, /* 4+ */ 51, 44, /* 12+ */ -1, -1, devinfo->gen >= 9)
614 FC(send_src1_reg_file, /* 4+ */ 36, 36, /* 12+ */ -1, -1, devinfo->gen >= 9)
615 FC(send_dst_reg_file, /* 4+ */ 35, 35, /* 12+ */ -1, -1, devinfo->gen >= 9)
616 /** @} */
617
618 /* Message descriptor bits */
619 #define MD(x) ((x) + 96)
620
621 /**
622 * Set the SEND(C) message descriptor immediate.
623 *
624 * This doesn't include the SFID nor the EOT field that were considered to be
625 * part of the message descriptor by ancient versions of the BSpec, because
626 * they are present in the instruction even if the message descriptor is
627 * provided indirectly in the address register, so we want to specify them
628 * separately.
629 */
630 static inline void
631 brw_inst_set_send_desc(const struct gen_device_info *devinfo,
632 brw_inst *inst, uint32_t value)
633 {
634 if (devinfo->gen >= 9) {
635 brw_inst_set_bits(inst, 126, 96, value);
636 assert(value >> 31 == 0);
637 } else if (devinfo->gen >= 5) {
638 brw_inst_set_bits(inst, 124, 96, value);
639 assert(value >> 29 == 0);
640 } else {
641 brw_inst_set_bits(inst, 119, 96, value);
642 assert(value >> 24 == 0);
643 }
644 }
645
646 /**
647 * Get the SEND(C) message descriptor immediate.
648 *
649 * \sa brw_inst_set_send_desc().
650 */
651 static inline uint32_t
652 brw_inst_send_desc(const struct gen_device_info *devinfo, const brw_inst *inst)
653 {
654 if (devinfo->gen >= 9)
655 return brw_inst_bits(inst, 126, 96);
656 else if (devinfo->gen >= 5)
657 return brw_inst_bits(inst, 124, 96);
658 else
659 return brw_inst_bits(inst, 119, 96);
660 }
661
662 /**
663 * Set the SEND(C) message extended descriptor immediate.
664 *
665 * This doesn't include the SFID nor the EOT field that were considered to be
666 * part of the extended message descriptor by some versions of the BSpec,
667 * because they are present in the instruction even if the extended message
668 * descriptor is provided indirectly in a register, so we want to specify them
669 * separately.
670 */
671 static inline void
672 brw_inst_set_send_ex_desc(const struct gen_device_info *devinfo,
673 brw_inst *inst, uint32_t value)
674 {
675 assert(devinfo->gen >= 9);
676 brw_inst_set_bits(inst, 94, 91, GET_BITS(value, 31, 28));
677 brw_inst_set_bits(inst, 88, 85, GET_BITS(value, 27, 24));
678 brw_inst_set_bits(inst, 83, 80, GET_BITS(value, 23, 20));
679 brw_inst_set_bits(inst, 67, 64, GET_BITS(value, 19, 16));
680 assert(GET_BITS(value, 15, 0) == 0);
681 }
682
683 /**
684 * Set the SENDS(C) message extended descriptor immediate.
685 *
686 * This doesn't include the SFID nor the EOT field that were considered to be
687 * part of the extended message descriptor by some versions of the BSpec,
688 * because they are present in the instruction even if the extended message
689 * descriptor is provided indirectly in a register, so we want to specify them
690 * separately.
691 */
692 static inline void
693 brw_inst_set_sends_ex_desc(const struct gen_device_info *devinfo,
694 brw_inst *inst, uint32_t value)
695 {
696 brw_inst_set_bits(inst, 95, 80, GET_BITS(value, 31, 16));
697 assert(GET_BITS(value, 15, 10) == 0);
698 brw_inst_set_bits(inst, 67, 64, GET_BITS(value, 9, 6));
699 assert(GET_BITS(value, 5, 0) == 0);
700 }
701
702 /**
703 * Get the SEND(C) message extended descriptor immediate.
704 *
705 * \sa brw_inst_set_send_ex_desc().
706 */
707 static inline uint32_t
708 brw_inst_send_ex_desc(const struct gen_device_info *devinfo,
709 const brw_inst *inst)
710 {
711 assert(devinfo->gen >= 9);
712 return (brw_inst_bits(inst, 94, 91) << 28 |
713 brw_inst_bits(inst, 88, 85) << 24 |
714 brw_inst_bits(inst, 83, 80) << 20 |
715 brw_inst_bits(inst, 67, 64) << 16);
716 }
717
718 /**
719 * Get the SENDS(C) message extended descriptor immediate.
720 *
721 * \sa brw_inst_set_send_ex_desc().
722 */
723 static inline uint32_t
724 brw_inst_sends_ex_desc(const struct gen_device_info *devinfo,
725 const brw_inst *inst)
726 {
727 return (brw_inst_bits(inst, 95, 80) << 16 |
728 brw_inst_bits(inst, 67, 64) << 6);
729 }
730
731 /**
732 * Fields for SEND messages:
733 * @{
734 */
735 F(eot, /* 4+ */ 127, 127, /* 12+ */ -1, -1)
736 FF(mlen,
737 /* 4: */ 119, 116,
738 /* 4.5: */ 119, 116,
739 /* 5: */ 124, 121,
740 /* 6: */ 124, 121,
741 /* 7: */ 124, 121,
742 /* 8: */ 124, 121,
743 /* 12: */ -1, -1);
744 FF(rlen,
745 /* 4: */ 115, 112,
746 /* 4.5: */ 115, 112,
747 /* 5: */ 120, 116,
748 /* 6: */ 120, 116,
749 /* 7: */ 120, 116,
750 /* 8: */ 120, 116,
751 /* 12: */ -1, -1);
752 FF(header_present,
753 /* 4: doesn't exist */ -1, -1, -1, -1,
754 /* 5: */ 115, 115,
755 /* 6: */ 115, 115,
756 /* 7: */ 115, 115,
757 /* 8: */ 115, 115,
758 /* 12: */ -1, -1)
759 F(gateway_notify, /* 4+ */ MD(16), MD(15), /* 12+ */ -1, -1)
760 FF(function_control,
761 /* 4: */ 111, 96,
762 /* 4.5: */ 111, 96,
763 /* 5: */ 114, 96,
764 /* 6: */ 114, 96,
765 /* 7: */ 114, 96,
766 /* 8: */ 114, 96,
767 /* 12: */ -1, -1)
768 FF(gateway_subfuncid,
769 /* 4: */ MD(1), MD(0),
770 /* 4.5: */ MD(1), MD(0),
771 /* 5: */ MD(1), MD(0), /* 2:0, but bit 2 is reserved MBZ */
772 /* 6: */ MD(2), MD(0),
773 /* 7: */ MD(2), MD(0),
774 /* 8: */ MD(2), MD(0),
775 /* 12: */ -1, -1)
776 FF(sfid,
777 /* 4: */ 123, 120, /* called msg_target */
778 /* 4.5 */ 123, 120,
779 /* 5: */ 95, 92,
780 /* 6: */ 27, 24,
781 /* 7: */ 27, 24,
782 /* 8: */ 27, 24,
783 /* 12: */ -1, -1)
784 FF(null_rt,
785 /* 4-7: */ -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
786 /* 8: */ 80, 80,
787 /* 12: */ -1, -1) /* actually only Gen11+ */
788 FC(base_mrf, /* 4+ */ 27, 24, /* 12+ */ -1, -1, devinfo->gen < 6);
789 /** @} */
790
791 /**
792 * URB message function control bits:
793 * @{
794 */
795 FF(urb_per_slot_offset,
796 /* 4-6: */ -1, -1, -1, -1, -1, -1, -1, -1,
797 /* 7: */ MD(16), MD(16),
798 /* 8: */ MD(17), MD(17),
799 /* 12: */ -1, -1)
800 FC(urb_channel_mask_present, /* 4+ */ MD(15), MD(15), /* 12+ */ -1, -1, devinfo->gen >= 8)
801 FC(urb_complete, /* 4+ */ MD(15), MD(15), /* 12+ */ -1, -1, devinfo->gen < 8)
802 FC(urb_used, /* 4+ */ MD(14), MD(14), /* 12+ */ -1, -1, devinfo->gen < 7)
803 FC(urb_allocate, /* 4+ */ MD(13), MD(13), /* 12+ */ -1, -1, devinfo->gen < 7)
804 FF(urb_swizzle_control,
805 /* 4: */ MD(11), MD(10),
806 /* 4.5: */ MD(11), MD(10),
807 /* 5: */ MD(11), MD(10),
808 /* 6: */ MD(11), MD(10),
809 /* 7: */ MD(14), MD(14),
810 /* 8: */ MD(15), MD(15),
811 /* 12: */ -1, -1)
812 FF(urb_global_offset,
813 /* 4: */ MD( 9), MD(4),
814 /* 4.5: */ MD( 9), MD(4),
815 /* 5: */ MD( 9), MD(4),
816 /* 6: */ MD( 9), MD(4),
817 /* 7: */ MD(13), MD(3),
818 /* 8: */ MD(14), MD(4),
819 /* 12: */ -1, -1)
820 FF(urb_opcode,
821 /* 4: */ MD( 3), MD(0),
822 /* 4.5: */ MD( 3), MD(0),
823 /* 5: */ MD( 3), MD(0),
824 /* 6: */ MD( 3), MD(0),
825 /* 7: */ MD( 2), MD(0),
826 /* 8: */ MD( 3), MD(0),
827 /* 12: */ -1, -1)
828 /** @} */
829
830 /**
831 * Gen4-5 math messages:
832 * @{
833 */
834 FC(math_msg_data_type, /* 4+ */ MD(7), MD(7), /* 12+ */ -1, -1, devinfo->gen < 6)
835 FC(math_msg_saturate, /* 4+ */ MD(6), MD(6), /* 12+ */ -1, -1, devinfo->gen < 6)
836 FC(math_msg_precision, /* 4+ */ MD(5), MD(5), /* 12+ */ -1, -1, devinfo->gen < 6)
837 FC(math_msg_signed_int, /* 4+ */ MD(4), MD(4), /* 12+ */ -1, -1, devinfo->gen < 6)
838 FC(math_msg_function, /* 4+ */ MD(3), MD(0), /* 12+ */ -1, -1, devinfo->gen < 6)
839 /** @} */
840
841 /**
842 * Sampler message function control bits:
843 * @{
844 */
845 FF(sampler_simd_mode,
846 /* 4: doesn't exist */ -1, -1, -1, -1,
847 /* 5: */ MD(17), MD(16),
848 /* 6: */ MD(17), MD(16),
849 /* 7: */ MD(18), MD(17),
850 /* 8: */ MD(18), MD(17),
851 /* 12: */ -1, -1)
852 FF(sampler_msg_type,
853 /* 4: */ MD(15), MD(14),
854 /* 4.5: */ MD(15), MD(12),
855 /* 5: */ MD(15), MD(12),
856 /* 6: */ MD(15), MD(12),
857 /* 7: */ MD(16), MD(12),
858 /* 8: */ MD(16), MD(12),
859 /* 12: */ -1, -1)
860 FC(sampler_return_format, /* 4+ */ MD(13), MD(12), /* 12+ */ -1, -1, devinfo->gen == 4 && !devinfo->is_g4x)
861 F(sampler, /* 4+ */ MD(11), MD(8), /* 12+ */ -1, -1)
862 F(binding_table_index, /* 4+ */ MD( 7), MD(0), /* 12+ */ -1, -1) /* also used by other messages */
863 /** @} */
864
865 /**
866 * Data port message function control bits:
867 * @{
868 */
869 FC(dp_category, /* 4+ */ MD(18), MD(18), /* 12+ */ -1, -1, devinfo->gen >= 7)
870
871 /* Gen4-5 store fields in different bits for read/write messages. */
872 FF(dp_read_msg_type,
873 /* 4: */ MD(13), MD(12),
874 /* 4.5: */ MD(13), MD(11),
875 /* 5: */ MD(13), MD(11),
876 /* 6: */ MD(16), MD(13),
877 /* 7: */ MD(17), MD(14),
878 /* 8: */ MD(17), MD(14),
879 /* 12: */ -1, -1)
880 FF(dp_write_msg_type,
881 /* 4: */ MD(14), MD(12),
882 /* 4.5: */ MD(14), MD(12),
883 /* 5: */ MD(14), MD(12),
884 /* 6: */ MD(16), MD(13),
885 /* 7: */ MD(17), MD(14),
886 /* 8: */ MD(17), MD(14),
887 /* 12: */ -1, -1)
888 FF(dp_read_msg_control,
889 /* 4: */ MD(11), MD( 8),
890 /* 4.5: */ MD(10), MD( 8),
891 /* 5: */ MD(10), MD( 8),
892 /* 6: */ MD(12), MD( 8),
893 /* 7: */ MD(13), MD( 8),
894 /* 8: */ MD(13), MD( 8),
895 /* 12: */ -1, -1)
896 FF(dp_write_msg_control,
897 /* 4: */ MD(11), MD( 8),
898 /* 4.5: */ MD(11), MD( 8),
899 /* 5: */ MD(11), MD( 8),
900 /* 6: */ MD(12), MD( 8),
901 /* 7: */ MD(13), MD( 8),
902 /* 8: */ MD(13), MD( 8),
903 /* 12: */ -1, -1)
904 FC(dp_read_target_cache, /* 4+ */ MD(15), MD(14), /* 12+ */ -1, -1, devinfo->gen < 6);
905
906 FF(dp_write_commit,
907 /* 4: */ MD(15), MD(15),
908 /* 4.5: */ MD(15), MD(15),
909 /* 5: */ MD(15), MD(15),
910 /* 6: */ MD(17), MD(17),
911 /* 7+: does not exist */ -1, -1, -1, -1,
912 /* 12: */ -1, -1)
913
914 /* Gen6+ use the same bit locations for everything. */
915 FF(dp_msg_type,
916 /* 4-5: use dp_read_msg_type or dp_write_msg_type instead */
917 -1, -1, -1, -1, -1, -1,
918 /* 6: */ MD(16), MD(13),
919 /* 7: */ MD(17), MD(14),
920 /* 8: */ MD(18), MD(14),
921 /* 12: */ -1, -1)
922 FF(dp_msg_control,
923 /* 4: */ MD(11), MD( 8),
924 /* 4.5-5: use dp_read_msg_control or dp_write_msg_control */ -1, -1, -1, -1,
925 /* 6: */ MD(12), MD( 8),
926 /* 7: */ MD(13), MD( 8),
927 /* 8: */ MD(13), MD( 8),
928 /* 12: */ -1, -1)
929 /** @} */
930
931 /**
932 * Scratch message bits (Gen7+):
933 * @{
934 */
935 FC(scratch_read_write, /* 4+ */ MD(17), MD(17), /* 12+ */ -1, -1, devinfo->gen >= 7) /* 0 = read, 1 = write */
936 FC(scratch_type, /* 4+ */ MD(16), MD(16), /* 12+ */ -1, -1, devinfo->gen >= 7) /* 0 = OWord, 1 = DWord */
937 FC(scratch_invalidate_after_read, /* 4+ */ MD(15), MD(15), /* 12+ */ -1, -1, devinfo->gen >= 7)
938 FC(scratch_block_size, /* 4+ */ MD(13), MD(12), /* 12+ */ -1, -1, devinfo->gen >= 7)
939 FC(scratch_addr_offset, /* 4+ */ MD(11), MD( 0), /* 12+ */ -1, -1, devinfo->gen >= 7)
940 /** @} */
941
942 /**
943 * Render Target message function control bits:
944 * @{
945 */
946 FF(rt_last,
947 /* 4: */ MD(11), MD(11),
948 /* 4.5: */ MD(11), MD(11),
949 /* 5: */ MD(11), MD(11),
950 /* 6: */ MD(12), MD(12),
951 /* 7: */ MD(12), MD(12),
952 /* 8: */ MD(12), MD(12),
953 /* 12: */ -1, -1)
954 FC(rt_slot_group, /* 4+ */ MD(11), MD(11), /* 12+ */ -1, -1, devinfo->gen >= 6)
955 F(rt_message_type, /* 4+ */ MD(10), MD( 8), /* 12+ */ -1, -1)
956 /** @} */
957
958 /**
959 * Thread Spawn message function control bits:
960 * @{
961 */
962 F(ts_resource_select, /* 4+ */ MD( 4), MD( 4), /* 12+ */ -1, -1)
963 F(ts_request_type, /* 4+ */ MD( 1), MD( 1), /* 12+ */ -1, -1)
964 F(ts_opcode, /* 4+ */ MD( 0), MD( 0), /* 12+ */ -1, -1)
965 /** @} */
966
967 /**
968 * Pixel Interpolator message function control bits:
969 * @{
970 */
971 F(pi_simd_mode, /* 4+ */ MD(16), MD(16), /* 12+ */ -1, -1)
972 F(pi_nopersp, /* 4+ */ MD(14), MD(14), /* 12+ */ -1, -1)
973 F(pi_message_type, /* 4+ */ MD(13), MD(12), /* 12+ */ -1, -1)
974 F(pi_slot_group, /* 4+ */ MD(11), MD(11), /* 12+ */ -1, -1)
975 F(pi_message_data, /* 4+ */ MD(7), MD(0), /* 12+ */ -1, -1)
976 /** @} */
977
978 /**
979 * Immediates:
980 * @{
981 */
982 static inline int
983 brw_inst_imm_d(const struct gen_device_info *devinfo, const brw_inst *insn)
984 {
985 (void) devinfo;
986 return brw_inst_bits(insn, 127, 96);
987 }
988
989 static inline unsigned
990 brw_inst_imm_ud(const struct gen_device_info *devinfo, const brw_inst *insn)
991 {
992 (void) devinfo;
993 return brw_inst_bits(insn, 127, 96);
994 }
995
996 static inline uint64_t
997 brw_inst_imm_uq(ASSERTED const struct gen_device_info *devinfo,
998 const brw_inst *insn)
999 {
1000 assert(devinfo->gen >= 8);
1001 return brw_inst_bits(insn, 127, 64);
1002 }
1003
1004 static inline float
1005 brw_inst_imm_f(const struct gen_device_info *devinfo, const brw_inst *insn)
1006 {
1007 union {
1008 float f;
1009 uint32_t u;
1010 } ft;
1011 (void) devinfo;
1012 ft.u = brw_inst_bits(insn, 127, 96);
1013 return ft.f;
1014 }
1015
1016 static inline double
1017 brw_inst_imm_df(const struct gen_device_info *devinfo, const brw_inst *insn)
1018 {
1019 union {
1020 double d;
1021 uint64_t u;
1022 } dt;
1023 (void) devinfo;
1024 dt.u = brw_inst_bits(insn, 127, 64);
1025 return dt.d;
1026 }
1027
1028 static inline void
1029 brw_inst_set_imm_d(const struct gen_device_info *devinfo,
1030 brw_inst *insn, int value)
1031 {
1032 (void) devinfo;
1033 return brw_inst_set_bits(insn, 127, 96, value);
1034 }
1035
1036 static inline void
1037 brw_inst_set_imm_ud(const struct gen_device_info *devinfo,
1038 brw_inst *insn, unsigned value)
1039 {
1040 (void) devinfo;
1041 return brw_inst_set_bits(insn, 127, 96, value);
1042 }
1043
1044 static inline void
1045 brw_inst_set_imm_f(const struct gen_device_info *devinfo,
1046 brw_inst *insn, float value)
1047 {
1048 union {
1049 float f;
1050 uint32_t u;
1051 } ft;
1052 (void) devinfo;
1053 ft.f = value;
1054 brw_inst_set_bits(insn, 127, 96, ft.u);
1055 }
1056
1057 static inline void
1058 brw_inst_set_imm_df(const struct gen_device_info *devinfo,
1059 brw_inst *insn, double value)
1060 {
1061 union {
1062 double d;
1063 uint64_t u;
1064 } dt;
1065 (void) devinfo;
1066 dt.d = value;
1067 brw_inst_set_bits(insn, 127, 64, dt.u);
1068 }
1069
1070 static inline void
1071 brw_inst_set_imm_uq(const struct gen_device_info *devinfo,
1072 brw_inst *insn, uint64_t value)
1073 {
1074 (void) devinfo;
1075 brw_inst_set_bits(insn, 127, 64, value);
1076 }
1077
1078 /** @} */
1079
1080 #define REG_TYPE(reg) \
1081 static inline void \
1082 brw_inst_set_##reg##_file_type(const struct gen_device_info *devinfo, \
1083 brw_inst *inst, enum brw_reg_file file, \
1084 enum brw_reg_type type) \
1085 { \
1086 assert(file <= BRW_IMMEDIATE_VALUE); \
1087 unsigned hw_type = brw_reg_type_to_hw_type(devinfo, file, type); \
1088 brw_inst_set_##reg##_reg_file(devinfo, inst, file); \
1089 brw_inst_set_##reg##_reg_hw_type(devinfo, inst, hw_type); \
1090 } \
1091 \
1092 static inline enum brw_reg_type \
1093 brw_inst_##reg##_type(const struct gen_device_info *devinfo, \
1094 const brw_inst *inst) \
1095 { \
1096 unsigned file = __builtin_strcmp("dst", #reg) == 0 ? \
1097 (unsigned) BRW_GENERAL_REGISTER_FILE : \
1098 brw_inst_##reg##_reg_file(devinfo, inst); \
1099 unsigned hw_type = brw_inst_##reg##_reg_hw_type(devinfo, inst); \
1100 return brw_hw_type_to_reg_type(devinfo, (enum brw_reg_file)file, hw_type); \
1101 }
1102
1103 REG_TYPE(dst)
1104 REG_TYPE(src0)
1105 REG_TYPE(src1)
1106 #undef REG_TYPE
1107
1108
1109 /* The AddrImm fields are split into two discontiguous sections on Gen8+ */
1110 #define BRW_IA1_ADDR_IMM(reg, g4_high, g4_low, g8_nine, g8_high, g8_low) \
1111 static inline void \
1112 brw_inst_set_##reg##_ia1_addr_imm(const struct gen_device_info *devinfo, \
1113 brw_inst *inst, \
1114 unsigned value) \
1115 { \
1116 assert((value & ~0x3ff) == 0); \
1117 if (devinfo->gen >= 8) { \
1118 brw_inst_set_bits(inst, g8_high, g8_low, value & 0x1ff); \
1119 brw_inst_set_bits(inst, g8_nine, g8_nine, value >> 9); \
1120 } else { \
1121 brw_inst_set_bits(inst, g4_high, g4_low, value); \
1122 } \
1123 } \
1124 static inline unsigned \
1125 brw_inst_##reg##_ia1_addr_imm(const struct gen_device_info *devinfo, \
1126 const brw_inst *inst) \
1127 { \
1128 if (devinfo->gen >= 8) { \
1129 return brw_inst_bits(inst, g8_high, g8_low) | \
1130 (brw_inst_bits(inst, g8_nine, g8_nine) << 9); \
1131 } else { \
1132 return brw_inst_bits(inst, g4_high, g4_low); \
1133 } \
1134 }
1135
1136 /* AddrImm[9:0] for Align1 Indirect Addressing */
1137 /* -Gen 4- ----Gen8---- */
1138 BRW_IA1_ADDR_IMM(src1, 105, 96, 121, 104, 96)
1139 BRW_IA1_ADDR_IMM(src0, 73, 64, 95, 72, 64)
1140 BRW_IA1_ADDR_IMM(dst, 57, 48, 47, 56, 48)
1141
1142 #define BRW_IA16_ADDR_IMM(reg, g4_high, g4_low, g8_nine, g8_high, g8_low) \
1143 static inline void \
1144 brw_inst_set_##reg##_ia16_addr_imm(const struct gen_device_info *devinfo, \
1145 brw_inst *inst, unsigned value) \
1146 { \
1147 assert((value & ~0x3ff) == 0); \
1148 if (devinfo->gen >= 8) { \
1149 assert(GET_BITS(value, 3, 0) == 0); \
1150 brw_inst_set_bits(inst, g8_high, g8_low, GET_BITS(value, 8, 4)); \
1151 brw_inst_set_bits(inst, g8_nine, g8_nine, GET_BITS(value, 9, 9)); \
1152 } else { \
1153 brw_inst_set_bits(inst, g4_high, g4_low, value); \
1154 } \
1155 } \
1156 static inline unsigned \
1157 brw_inst_##reg##_ia16_addr_imm(const struct gen_device_info *devinfo, \
1158 const brw_inst *inst) \
1159 { \
1160 if (devinfo->gen >= 8) { \
1161 return (brw_inst_bits(inst, g8_high, g8_low) << 4) | \
1162 (brw_inst_bits(inst, g8_nine, g8_nine) << 9); \
1163 } else { \
1164 return brw_inst_bits(inst, g4_high, g4_low); \
1165 } \
1166 }
1167
1168 /* AddrImm[9:0] for Align16 Indirect Addressing:
1169 * Compared to Align1, these are missing the low 4 bits.
1170 * -Gen 4- ----Gen8----
1171 */
1172 BRW_IA16_ADDR_IMM(src1, 105, 96, 121, 104, 100)
1173 BRW_IA16_ADDR_IMM(src0, 73, 64, 95, 72, 68)
1174 BRW_IA16_ADDR_IMM(dst, 57, 52, 47, 56, 52)
1175 BRW_IA16_ADDR_IMM(send_src0, -1, -1, 78, 72, 68)
1176 BRW_IA16_ADDR_IMM(send_dst, -1, -1, 62, 56, 52)
1177
1178 /**
1179 * Fetch a set of contiguous bits from the instruction.
1180 *
1181 * Bits indices range from 0..127; fields may not cross 64-bit boundaries.
1182 */
1183 static inline uint64_t
1184 brw_inst_bits(const brw_inst *inst, unsigned high, unsigned low)
1185 {
1186 assert(high >= low);
1187 /* We assume the field doesn't cross 64-bit boundaries. */
1188 const unsigned word = high / 64;
1189 assert(word == low / 64);
1190
1191 high %= 64;
1192 low %= 64;
1193
1194 const uint64_t mask = (~0ull >> (64 - (high - low + 1)));
1195
1196 return (inst->data[word] >> low) & mask;
1197 }
1198
1199 /**
1200 * Set bits in the instruction, with proper shifting and masking.
1201 *
1202 * Bits indices range from 0..127; fields may not cross 64-bit boundaries.
1203 */
1204 static inline void
1205 brw_inst_set_bits(brw_inst *inst, unsigned high, unsigned low, uint64_t value)
1206 {
1207 assert(high >= low);
1208 const unsigned word = high / 64;
1209 assert(word == low / 64);
1210
1211 high %= 64;
1212 low %= 64;
1213
1214 const uint64_t mask = (~0ull >> (64 - (high - low + 1))) << low;
1215
1216 /* Make sure the supplied value actually fits in the given bitfield. */
1217 assert((value & (mask >> low)) == value);
1218
1219 inst->data[word] = (inst->data[word] & ~mask) | (value << low);
1220 }
1221
1222 #undef BRW_IA16_ADDR_IMM
1223 #undef BRW_IA1_ADDR_IMM
1224 #undef MD
1225 #undef F8
1226 #undef FF
1227 #undef BOUNDS
1228 #undef F
1229 #undef FC
1230
1231 typedef struct {
1232 uint64_t data;
1233 } brw_compact_inst;
1234
1235 /**
1236 * Fetch a set of contiguous bits from the compacted instruction.
1237 *
1238 * Bits indices range from 0..63.
1239 */
1240 static inline unsigned
1241 brw_compact_inst_bits(const brw_compact_inst *inst, unsigned high, unsigned low)
1242 {
1243 const uint64_t mask = (1ull << (high - low + 1)) - 1;
1244
1245 return (inst->data >> low) & mask;
1246 }
1247
1248 /**
1249 * Set bits in the compacted instruction.
1250 *
1251 * Bits indices range from 0..63.
1252 */
1253 static inline void
1254 brw_compact_inst_set_bits(brw_compact_inst *inst, unsigned high, unsigned low,
1255 uint64_t value)
1256 {
1257 const uint64_t mask = ((1ull << (high - low + 1)) - 1) << low;
1258
1259 /* Make sure the supplied value actually fits in the given bitfield. */
1260 assert((value & (mask >> low)) == value);
1261
1262 inst->data = (inst->data & ~mask) | (value << low);
1263 }
1264
1265 #define FC(name, high, low, assertions) \
1266 static inline void \
1267 brw_compact_inst_set_##name(const struct gen_device_info *devinfo, \
1268 brw_compact_inst *inst, unsigned v) \
1269 { \
1270 assert(assertions); \
1271 (void) devinfo; \
1272 brw_compact_inst_set_bits(inst, high, low, v); \
1273 } \
1274 static inline unsigned \
1275 brw_compact_inst_##name(const struct gen_device_info *devinfo, \
1276 const brw_compact_inst *inst) \
1277 { \
1278 assert(assertions); \
1279 (void) devinfo; \
1280 return brw_compact_inst_bits(inst, high, low); \
1281 }
1282
1283 /* A simple macro for fields which stay in the same place on all generations. */
1284 #define F(name, high, low) FC(name, high, low, true)
1285
1286 F(src1_reg_nr, 63, 56)
1287 F(src0_reg_nr, 55, 48)
1288 F(dst_reg_nr, 47, 40)
1289 F(src1_index, 39, 35)
1290 F(src0_index, 34, 30)
1291 F(cmpt_control, 29, 29) /* Same location as brw_inst */
1292 FC(flag_subreg_nr, 28, 28, devinfo->gen <= 6)
1293 F(cond_modifier, 27, 24) /* Same location as brw_inst */
1294 FC(acc_wr_control, 23, 23, devinfo->gen >= 6)
1295 FC(mask_control_ex, 23, 23, devinfo->is_g4x || devinfo->gen == 5)
1296 F(subreg_index, 22, 18)
1297 F(datatype_index, 17, 13)
1298 F(control_index, 12, 8)
1299 F(debug_control, 7, 7)
1300 F(hw_opcode, 6, 0) /* Same location as brw_inst */
1301
1302 /**
1303 * (Gen8+) Compacted three-source instructions:
1304 * @{
1305 */
1306 FC(3src_src2_reg_nr, 63, 57, devinfo->gen >= 8)
1307 FC(3src_src1_reg_nr, 56, 50, devinfo->gen >= 8)
1308 FC(3src_src0_reg_nr, 49, 43, devinfo->gen >= 8)
1309 FC(3src_src2_subreg_nr, 42, 40, devinfo->gen >= 8)
1310 FC(3src_src1_subreg_nr, 39, 37, devinfo->gen >= 8)
1311 FC(3src_src0_subreg_nr, 36, 34, devinfo->gen >= 8)
1312 FC(3src_src2_rep_ctrl, 33, 33, devinfo->gen >= 8)
1313 FC(3src_src1_rep_ctrl, 32, 32, devinfo->gen >= 8)
1314 FC(3src_saturate, 31, 31, devinfo->gen >= 8)
1315 FC(3src_debug_control, 30, 30, devinfo->gen >= 8)
1316 FC(3src_cmpt_control, 29, 29, devinfo->gen >= 8)
1317 FC(3src_src0_rep_ctrl, 28, 28, devinfo->gen >= 8)
1318 /* Reserved */
1319 FC(3src_dst_reg_nr, 18, 12, devinfo->gen >= 8)
1320 FC(3src_source_index, 11, 10, devinfo->gen >= 8)
1321 FC(3src_control_index, 9, 8, devinfo->gen >= 8)
1322 /* Bit 7 is Reserved (for future Opcode expansion) */
1323 FC(3src_hw_opcode, 6, 0, devinfo->gen >= 8)
1324 /** @} */
1325
1326 #undef F
1327
1328 #ifdef __cplusplus
1329 }
1330 #endif
1331
1332 #endif