2 * Copyright © 2014 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
27 * A representation of i965 EU assembly instructions, with helper methods to
28 * get and set various fields. This is the actual hardware format.
37 #include "brw_eu_defines.h"
38 #include "brw_reg_type.h"
39 #include "dev/gen_device_info.h"
45 /* brw_context.h has a forward declaration of brw_inst, so name the struct. */
46 typedef struct brw_inst
{
50 static inline uint64_t brw_inst_bits(const brw_inst
*inst
,
51 unsigned high
, unsigned low
);
52 static inline void brw_inst_set_bits(brw_inst
*inst
,
53 unsigned high
, unsigned low
,
56 #define FC(name, hi4, lo4, hi12, lo12, assertions) \
58 brw_inst_set_##name(const struct gen_device_info *devinfo, \
59 brw_inst *inst, uint64_t v) \
62 if (devinfo->gen >= 12) \
63 brw_inst_set_bits(inst, hi12, lo12, v); \
65 brw_inst_set_bits(inst, hi4, lo4, v); \
67 static inline uint64_t \
68 brw_inst_##name(const struct gen_device_info *devinfo, \
69 const brw_inst *inst) \
72 if (devinfo->gen >= 12) \
73 return brw_inst_bits(inst, hi12, lo12); \
75 return brw_inst_bits(inst, hi4, lo4); \
78 /* A simple macro for fields which stay in the same place on all generations,
81 #define F(name, hi4, lo4, hi12, lo12) FC(name, hi4, lo4, hi12, lo12, true)
83 #define BOUNDS(hi4, lo4, hi45, lo45, hi5, lo5, hi6, lo6, \
84 hi7, lo7, hi8, lo8, hi12, lo12) \
86 if (devinfo->gen >= 12) { \
87 high = hi12; low = lo12; \
88 } else if (devinfo->gen >= 8) { \
89 high = hi8; low = lo8; \
90 } else if (devinfo->gen >= 7) { \
91 high = hi7; low = lo7; \
92 } else if (devinfo->gen >= 6) { \
93 high = hi6; low = lo6; \
94 } else if (devinfo->gen >= 5) { \
95 high = hi5; low = lo5; \
96 } else if (devinfo->is_g4x) { \
97 high = hi45; low = lo45; \
99 high = hi4; low = lo4; \
101 assert(((int) high) != -1 && ((int) low) != -1);
103 /* A general macro for cases where the field has moved to several different
104 * bit locations across generations. GCC appears to combine cases where the
105 * bits are identical, removing some of the inefficiency.
107 #define FF(name, hi4, lo4, hi45, lo45, hi5, lo5, hi6, lo6, \
108 hi7, lo7, hi8, lo8, hi12, lo12) \
110 brw_inst_set_##name(const struct gen_device_info *devinfo, \
111 brw_inst *inst, uint64_t value) \
113 BOUNDS(hi4, lo4, hi45, lo45, hi5, lo5, hi6, lo6, \
114 hi7, lo7, hi8, lo8, hi12, lo12) \
115 brw_inst_set_bits(inst, high, low, value); \
117 static inline uint64_t \
118 brw_inst_##name(const struct gen_device_info *devinfo, const brw_inst *inst) \
120 BOUNDS(hi4, lo4, hi45, lo45, hi5, lo5, hi6, lo6, \
121 hi7, lo7, hi8, lo8, hi12, lo12) \
122 return brw_inst_bits(inst, high, low); \
125 /* A macro for fields which moved as of Gen8+. */
126 #define F8(name, gen4_high, gen4_low, gen8_high, gen8_low, \
127 gen12_high, gen12_low) \
129 /* 4: */ gen4_high, gen4_low, \
130 /* 4.5: */ gen4_high, gen4_low, \
131 /* 5: */ gen4_high, gen4_low, \
132 /* 6: */ gen4_high, gen4_low, \
133 /* 7: */ gen4_high, gen4_low, \
134 /* 8: */ gen8_high, gen8_low, \
135 /* 12: */ gen12_high, gen12_low);
137 /* Macro for fields that gained extra discontiguous MSBs in Gen12 (specified
140 #define FFDC(name, hi4, lo4, hi45, lo45, hi5, lo5, hi6, lo6, \
141 hi7, lo7, hi8, lo8, hi12ex, lo12ex, hi12, lo12, assertions) \
143 brw_inst_set_##name(const struct gen_device_info *devinfo, \
144 brw_inst *inst, uint64_t value) \
146 assert(assertions); \
147 if (devinfo->gen >= 12) { \
148 const unsigned k = hi12 - lo12 + 1; \
149 if (hi12ex != -1 && lo12ex != -1) \
150 brw_inst_set_bits(inst, hi12ex, lo12ex, value >> k); \
151 brw_inst_set_bits(inst, hi12, lo12, value & ((1ull << k) - 1)); \
153 BOUNDS(hi4, lo4, hi45, lo45, hi5, lo5, hi6, lo6, \
154 hi7, lo7, hi8, lo8, -1, -1); \
155 brw_inst_set_bits(inst, high, low, value); \
158 static inline uint64_t \
159 brw_inst_##name(const struct gen_device_info *devinfo, const brw_inst *inst) \
161 assert(assertions); \
162 if (devinfo->gen >= 12) { \
163 const unsigned k = hi12 - lo12 + 1; \
164 return (hi12ex == -1 || lo12ex == -1 ? 0 : \
165 brw_inst_bits(inst, hi12ex, lo12ex) << k) | \
166 brw_inst_bits(inst, hi12, lo12); \
168 BOUNDS(hi4, lo4, hi45, lo45, hi5, lo5, hi6, lo6, \
169 hi7, lo7, hi8, lo8, -1, -1); \
170 return brw_inst_bits(inst, high, low); \
174 #define FD(name, hi4, lo4, hi45, lo45, hi5, lo5, hi6, lo6, \
175 hi7, lo7, hi8, lo8, hi12ex, lo12ex, hi12, lo12) \
176 FFDC(name, hi4, lo4, hi45, lo45, hi5, lo5, hi6, lo6, \
177 hi7, lo7, hi8, lo8, hi12ex, lo12ex, hi12, lo12, true)
179 /* Macro for fields that didn't move across generations until Gen12, and then
180 * gained extra discontiguous bits.
182 #define FDC(name, hi4, lo4, hi12ex, lo12ex, hi12, lo12, assertions) \
183 FFDC(name, hi4, lo4, hi4, lo4, hi4, lo4, hi4, lo4, \
184 hi4, lo4, hi4, lo4, hi12ex, lo12ex, hi12, lo12, assertions)
187 /* Macro for the 2-bit register file field, which on Gen12+ is stored as the
188 * variable length combination of an IsImm (hi12) bit and an additional file
191 #define FI(name, hi4, lo4, hi8, lo8, hi12, lo12) \
193 brw_inst_set_##name(const struct gen_device_info *devinfo, \
194 brw_inst *inst, uint64_t value) \
196 if (devinfo->gen >= 12) { \
197 brw_inst_set_bits(inst, hi12, hi12, value >> 1); \
198 if ((value >> 1) == 0) \
199 brw_inst_set_bits(inst, lo12, lo12, value & 1); \
201 BOUNDS(hi4, lo4, hi4, lo4, hi4, lo4, hi4, lo4, \
202 hi4, lo4, hi8, lo8, -1, -1); \
203 brw_inst_set_bits(inst, high, low, value); \
206 static inline uint64_t \
207 brw_inst_##name(const struct gen_device_info *devinfo, const brw_inst *inst) \
209 if (devinfo->gen >= 12) { \
210 return (brw_inst_bits(inst, hi12, hi12) << 1) | \
211 (brw_inst_bits(inst, hi12, hi12) == 0 ? \
212 brw_inst_bits(inst, lo12, lo12) : 1); \
214 BOUNDS(hi4, lo4, hi4, lo4, hi4, lo4, hi4, lo4, \
215 hi4, lo4, hi8, lo8, -1, -1); \
216 return brw_inst_bits(inst, high, low); \
220 /* Macro for fields that become a constant in Gen12+ not actually represented
221 * in the instruction.
223 #define FK(name, hi4, lo4, const12) \
225 brw_inst_set_##name(const struct gen_device_info *devinfo, \
226 brw_inst *inst, uint64_t v) \
228 if (devinfo->gen >= 12) \
229 assert(v == (const12)); \
231 brw_inst_set_bits(inst, hi4, lo4, v); \
233 static inline uint64_t \
234 brw_inst_##name(const struct gen_device_info *devinfo, \
235 const brw_inst *inst) \
237 if (devinfo->gen >= 12) \
240 return brw_inst_bits(inst, hi4, lo4); \
243 F(src1_vstride
, /* 4+ */ 120, 117, /* 12+ */ 119, 116)
244 F(src1_width
, /* 4+ */ 116, 114, /* 12+ */ 115, 113)
245 F(src1_da16_swiz_w
, /* 4+ */ 115, 114, /* 12+ */ -1, -1)
246 F(src1_da16_swiz_z
, /* 4+ */ 113, 112, /* 12+ */ -1, -1)
247 F(src1_hstride
, /* 4+ */ 113, 112, /* 12+ */ 97, 96)
248 F(src1_address_mode
, /* 4+ */ 111, 111, /* 12+ */ 112, 112)
249 /** Src1.SrcMod @{ */
250 F(src1_negate
, /* 4+ */ 110, 110, /* 12+ */ 121, 121)
251 F(src1_abs
, /* 4+ */ 109, 109, /* 12+ */ 120, 120)
253 F8(src1_ia_subreg_nr
, /* 4+ */ 108, 106, /* 8+ */ 108, 105, /* 12+ */ 111, 108)
254 F(src1_da_reg_nr
, /* 4+ */ 108, 101, /* 12+ */ 111, 104)
255 F(src1_da16_subreg_nr
, /* 4+ */ 100, 100, /* 12+ */ -1, -1)
256 F(src1_da1_subreg_nr
, /* 4+ */ 100, 96, /* 12+ */ 103, 99)
257 F(src1_da16_swiz_y
, /* 4+ */ 99, 98, /* 12+ */ -1, -1)
258 F(src1_da16_swiz_x
, /* 4+ */ 97, 96, /* 12+ */ -1, -1)
259 F8(src1_reg_hw_type
, /* 4+ */ 46, 44, /* 8+ */ 94, 91, /* 12+ */ 91, 88)
260 FI(src1_reg_file
, /* 4+ */ 43, 42, /* 8+ */ 90, 89, /* 12+ */ 47, 98)
261 F(src1_is_imm
, /* 4+ */ -1, -1, /* 12+ */ 47, 47)
262 F(src0_vstride
, /* 4+ */ 88, 85, /* 12+ */ 87, 84)
263 F(src0_width
, /* 4+ */ 84, 82, /* 12+ */ 83, 81)
264 F(src0_da16_swiz_w
, /* 4+ */ 83, 82, /* 12+ */ -1, -1)
265 F(src0_da16_swiz_z
, /* 4+ */ 81, 80, /* 12+ */ -1, -1)
266 F(src0_hstride
, /* 4+ */ 81, 80, /* 12+ */ 65, 64)
267 F(src0_address_mode
, /* 4+ */ 79, 79, /* 12+ */ 80, 80)
268 /** Src0.SrcMod @{ */
269 F(src0_negate
, /* 4+ */ 78, 78, /* 12+ */ 45, 45)
270 F(src0_abs
, /* 4+ */ 77, 77, /* 12+ */ 44, 44)
272 F8(src0_ia_subreg_nr
, /* 4+ */ 76, 74, /* 8+ */ 76, 73, /* 12+ */ 79, 76)
273 F(src0_da_reg_nr
, /* 4+ */ 76, 69, /* 12+ */ 79, 72)
274 F(src0_da16_subreg_nr
, /* 4+ */ 68, 68, /* 12+ */ -1, -1)
275 F(src0_da1_subreg_nr
, /* 4+ */ 68, 64, /* 12+ */ 71, 67)
276 F(src0_da16_swiz_y
, /* 4+ */ 67, 66, /* 12+ */ -1, -1)
277 F(src0_da16_swiz_x
, /* 4+ */ 65, 64, /* 12+ */ -1, -1)
278 F(dst_address_mode
, /* 4+ */ 63, 63, /* 12+ */ 35, 35)
279 F(dst_hstride
, /* 4+ */ 62, 61, /* 12+ */ 49, 48)
280 F8(dst_ia_subreg_nr
, /* 4+ */ 60, 58, /* 8+ */ 60, 57, /* 12+ */ 63, 60)
281 F(dst_da_reg_nr
, /* 4+ */ 60, 53, /* 12+ */ 63, 56)
282 F(dst_da16_subreg_nr
, /* 4+ */ 52, 52, /* 12+ */ -1, -1)
283 F(dst_da1_subreg_nr
, /* 4+ */ 52, 48, /* 12+ */ 55, 51)
284 F(da16_writemask
, /* 4+ */ 51, 48, /* 12+ */ -1, -1) /* Dst.ChanEn */
285 F8(src0_reg_hw_type
, /* 4+ */ 41, 39, /* 8+ */ 46, 43, /* 12+ */ 43, 40)
286 FI(src0_reg_file
, /* 4+ */ 38, 37, /* 8+ */ 42, 41, /* 12+ */ 46, 66)
287 F(src0_is_imm
, /* 4+ */ -1, -1, /* 12+ */ 46, 46)
288 F8(dst_reg_hw_type
, /* 4+ */ 36, 34, /* 8+ */ 40, 37, /* 12+ */ 39, 36)
289 F8(dst_reg_file
, /* 4+ */ 33, 32, /* 8+ */ 36, 35, /* 12+ */ 50, 50)
290 F8(mask_control
, /* 4+ */ 9, 9, /* 8+ */ 34, 34, /* 12+ */ 31, 31)
292 /* 4-6: doesn't exist */ -1, -1, -1, -1, -1, -1, -1, -1,
296 F8(flag_subreg_nr
, /* 4+ */ 89, 89, /* 8+ */ 32, 32, /* 12+ */ 22, 22)
297 F(saturate
, /* 4+ */ 31, 31, /* 12+ */ 34, 34)
298 F(debug_control
, /* 4+ */ 30, 30, /* 12+ */ 30, 30)
299 F(cmpt_control
, /* 4+ */ 29, 29, /* 12+ */ 29, 29)
300 FC(branch_control
, /* 4+ */ 28, 28, /* 12+ */ 33, 33, devinfo
->gen
>= 8)
301 FC(acc_wr_control
, /* 4+ */ 28, 28, /* 12+ */ 33, 33, devinfo
->gen
>= 6)
302 FC(mask_control_ex
, /* 4+ */ 28, 28, /* 12+ */ -1, -1, devinfo
->is_g4x
|| devinfo
->gen
== 5)
303 F(cond_modifier
, /* 4+ */ 27, 24, /* 12+ */ 95, 92)
304 FC(math_function
, /* 4+ */ 27, 24, /* 12+ */ 95, 92, devinfo
->gen
>= 6)
305 F(exec_size
, /* 4+ */ 23, 21, /* 12+ */ 18, 16)
306 F(pred_inv
, /* 4+ */ 20, 20, /* 12+ */ 28, 28)
307 F(pred_control
, /* 4+ */ 19, 16, /* 12+ */ 27, 24)
308 F(thread_control
, /* 4+ */ 15, 14, /* 12+ */ -1, -1)
309 F(atomic_control
, /* 4+ */ -1, -1, /* 12+ */ 32, 32)
310 F(qtr_control
, /* 4+ */ 13, 12, /* 12+ */ 21, 20)
312 /* 4-6: doesn't exist */ -1, -1, -1, -1, -1, -1, -1, -1,
316 F8(no_dd_check
, /* 4+ */ 11, 11, /* 8+ */ 10, 10, /* 12+ */ -1, -1)
317 F8(no_dd_clear
, /* 4+ */ 10, 10, /* 8+ */ 9, 9, /* 12+ */ -1, -1)
318 F(swsb
, /* 4+ */ -1, -1, /* 12+ */ 15, 8)
319 FK(access_mode
, /* 4+ */ 8, 8, /* 12+ */ BRW_ALIGN_1
)
320 /* Bit 7 is Reserved (for future Opcode expansion) */
321 F(hw_opcode
, /* 4+ */ 6, 0, /* 12+ */ 6, 0)
324 * Three-source instructions:
327 F(3src_src2_reg_nr
, /* 4+ */ 125, 118, /* 12+ */ 127, 120) /* same in align1 */
328 F(3src_a16_src2_subreg_nr
, /* 4+ */ 117, 115, /* 12+ */ -1, -1) /* Extra discontiguous bit on CHV? */
329 F(3src_a16_src2_swizzle
, /* 4+ */ 114, 107, /* 12+ */ -1, -1)
330 F(3src_a16_src2_rep_ctrl
, /* 4+ */ 106, 106, /* 12+ */ -1, -1)
331 F(3src_src1_reg_nr
, /* 4+ */ 104, 97, /* 12+ */ 111, 104) /* same in align1 */
332 F(3src_a16_src1_subreg_nr
, /* 4+ */ 96, 94, /* 12+ */ -1, -1) /* Extra discontiguous bit on CHV? */
333 F(3src_a16_src1_swizzle
, /* 4+ */ 93, 86, /* 12+ */ -1, -1)
334 F(3src_a16_src1_rep_ctrl
, /* 4+ */ 85, 85, /* 12+ */ -1, -1)
335 F(3src_src0_reg_nr
, /* 4+ */ 83, 76, /* 12+ */ 79, 72) /* same in align1 */
336 F(3src_a16_src0_subreg_nr
, /* 4+ */ 75, 73, /* 12+ */ -1, -1) /* Extra discontiguous bit on CHV? */
337 F(3src_a16_src0_swizzle
, /* 4+ */ 72, 65, /* 12+ */ -1, -1)
338 F(3src_a16_src0_rep_ctrl
, /* 4+ */ 64, 64, /* 12+ */ -1, -1)
339 F(3src_dst_reg_nr
, /* 4+ */ 63, 56, /* 12+ */ 63, 56) /* same in align1 */
340 F(3src_a16_dst_subreg_nr
, /* 4+ */ 55, 53, /* 12+ */ -1, -1)
341 F(3src_a16_dst_writemask
, /* 4+ */ 52, 49, /* 12+ */ -1, -1)
342 F8(3src_a16_nib_ctrl
, /* 4+ */ 47, 47, /* 8+ */ 11, 11, /* 12+ */ -1, -1) /* only exists on IVB+ */
343 F8(3src_a16_dst_hw_type
, /* 4+ */ 45, 44, /* 8+ */ 48, 46, /* 12+ */ -1, -1) /* only exists on IVB+ */
344 F8(3src_a16_src_hw_type
, /* 4+ */ 43, 42, /* 8+ */ 45, 43, /* 12+ */ -1, -1)
345 F8(3src_src2_negate
, /* 4+ */ 41, 41, /* 8+ */ 42, 42, /* 12+ */ 85, 85)
346 F8(3src_src2_abs
, /* 4+ */ 40, 40, /* 8+ */ 41, 41, /* 12+ */ 84, 84)
347 F8(3src_src1_negate
, /* 4+ */ 39, 39, /* 8+ */ 40, 40, /* 12+ */ 87, 87)
348 F8(3src_src1_abs
, /* 4+ */ 38, 38, /* 8+ */ 39, 39, /* 12+ */ 86, 86)
349 F8(3src_src0_negate
, /* 4+ */ 37, 37, /* 8+ */ 38, 38, /* 12+ */ 45, 45)
350 F8(3src_src0_abs
, /* 4+ */ 36, 36, /* 8+ */ 37, 37, /* 12+ */ 44, 44)
351 F8(3src_a16_src1_type
, /* 4+ */ -1, -1, /* 8+ */ 36, 36, /* 12+ */ -1, -1)
352 F8(3src_a16_src2_type
, /* 4+ */ -1, -1, /* 8+ */ 35, 35, /* 12+ */ -1, -1)
353 F8(3src_a16_flag_reg_nr
, /* 4+ */ 34, 34, /* 8+ */ 33, 33, /* 12+ */ -1, -1)
354 F8(3src_a16_flag_subreg_nr
, /* 4+ */ 33, 33, /* 8+ */ 32, 32, /* 12+ */ -1, -1)
355 FF(3src_a16_dst_reg_file
,
356 /* 4-5: doesn't exist - no 3-source instructions */ -1, -1, -1, -1, -1, -1,
358 /* 7-8: doesn't exist - no MRFs */ -1, -1, -1, -1,
360 F(3src_saturate
, /* 4+ */ 31, 31, /* 12+ */ 34, 34)
361 F(3src_debug_control
, /* 4+ */ 30, 30, /* 12+ */ 30, 30)
362 F(3src_cmpt_control
, /* 4+ */ 29, 29, /* 12+ */ 29, 29)
363 F(3src_acc_wr_control
, /* 4+ */ 28, 28, /* 12+ */ 33, 33)
364 F(3src_cond_modifier
, /* 4+ */ 27, 24, /* 12+ */ 95, 92)
365 F(3src_exec_size
, /* 4+ */ 23, 21, /* 12+ */ 18, 16)
366 F(3src_pred_inv
, /* 4+ */ 20, 20, /* 12+ */ 28, 28)
367 F(3src_pred_control
, /* 4+ */ 19, 16, /* 12+ */ 27, 24)
368 F(3src_thread_control
, /* 4+ */ 15, 14, /* 12+ */ -1, -1)
369 F(3src_atomic_control
, /* 4+ */ -1, -1, /* 12+ */ 32, 32)
370 F(3src_qtr_control
, /* 4+ */ 13, 12, /* 12+ */ 21, 20)
371 F8(3src_no_dd_check
, /* 4+ */ 11, 11, /* 8+ */ 10, 10, /* 12+ */ -1, -1)
372 F8(3src_no_dd_clear
, /* 4+ */ 10, 10, /* 8+ */ 9, 9, /* 12+ */ -1, -1)
373 F8(3src_mask_control
, /* 4+ */ 9, 9, /* 8+ */ 34, 34, /* 12+ */ 31, 31)
374 FK(3src_access_mode
, /* 4+ */ 8, 8, /* 12+ */ BRW_ALIGN_1
)
375 F(3src_swsb
, /* 4+ */ -1, -1, /* 12+ */ 15, 8)
376 /* Bit 7 is Reserved (for future Opcode expansion) */
377 F(3src_hw_opcode
, /* 4+ */ 6, 0, /* 12+ */ 6, 0)
380 #define REG_TYPE(reg) \
382 brw_inst_set_3src_a16_##reg##_type(const struct gen_device_info *devinfo, \
383 brw_inst *inst, enum brw_reg_type type) \
385 unsigned hw_type = brw_reg_type_to_a16_hw_3src_type(devinfo, type); \
386 brw_inst_set_3src_a16_##reg##_hw_type(devinfo, inst, hw_type); \
389 static inline enum brw_reg_type \
390 brw_inst_3src_a16_##reg##_type(const struct gen_device_info *devinfo, \
391 const brw_inst *inst) \
393 unsigned hw_type = brw_inst_3src_a16_##reg##_hw_type(devinfo, inst); \
394 return brw_a16_hw_3src_type_to_reg_type(devinfo, hw_type); \
402 * Three-source align1 instructions:
405 /* Reserved 127:126 */
406 /* src2_reg_nr same in align16 */
407 FC(3src_a1_src2_subreg_nr
, /* 4+ */ 117, 113, /* 12+ */ 119, 115, devinfo
->gen
>= 10)
408 FC(3src_a1_src2_hstride
, /* 4+ */ 112, 111, /* 12+ */ 113, 112, devinfo
->gen
>= 10)
409 /* Reserved 110:109. src2 vstride is an implied parameter */
410 FC(3src_a1_src2_hw_type
, /* 4+ */ 108, 106, /* 12+ */ 82, 80, devinfo
->gen
>= 10)
412 /* src1_reg_nr same in align16 */
413 FC(3src_a1_src1_subreg_nr
, /* 4+ */ 96, 92, /* 12+ */ 103, 99, devinfo
->gen
>= 10)
414 FC(3src_a1_src1_hstride
, /* 4+ */ 91, 90, /* 12+ */ 97, 96, devinfo
->gen
>= 10)
415 FDC(3src_a1_src1_vstride
, /* 4+ */ 89, 88, /* 12+ */ 91, 91, 83, 83, devinfo
->gen
>= 10)
416 FC(3src_a1_src1_hw_type
, /* 4+ */ 87, 85, /* 12+ */ 90, 88, devinfo
->gen
>= 10)
418 /* src0_reg_nr same in align16 */
419 FC(3src_a1_src0_subreg_nr
, /* 4+ */ 75, 71, /* 12+ */ 71, 67, devinfo
->gen
>= 10)
420 FC(3src_a1_src0_hstride
, /* 4+ */ 70, 69, /* 12+ */ 65, 64, devinfo
->gen
>= 10)
421 FDC(3src_a1_src0_vstride
, /* 4+ */ 68, 67, /* 12+ */ 43, 43, 35, 35, devinfo
->gen
>= 10)
422 FC(3src_a1_src0_hw_type
, /* 4+ */ 66, 64, /* 12+ */ 42, 40, devinfo
->gen
>= 10)
423 /* dst_reg_nr same in align16 */
424 FC(3src_a1_dst_subreg_nr
, /* 4+ */ 55, 54, /* 12+ */ 55, 54, devinfo
->gen
>= 10)
425 FC(3src_a1_special_acc
, /* 4+ */ 55, 52, /* 12+ */ 54, 51, devinfo
->gen
>= 10) /* aliases dst_subreg_nr */
427 FC(3src_a1_dst_hstride
, /* 4+ */ 49, 49, /* 12+ */ 48, 48, devinfo
->gen
>= 10)
428 FC(3src_a1_dst_hw_type
, /* 4+ */ 48, 46, /* 12+ */ 38, 36, devinfo
->gen
>= 10)
429 FI(3src_a1_src2_reg_file
, /* 4+ */ -1, -1, /* 8+ */ 45, 45, /* 12+ */ 47, 114)
430 FC(3src_a1_src1_reg_file
, /* 4+ */ 44, 44, /* 12+ */ 98, 98, devinfo
->gen
>= 10)
431 FI(3src_a1_src0_reg_file
, /* 4+ */ -1, -1, /* 8+ */ 43, 43, /* 12+ */ 46, 66)
433 F(3src_a1_src2_is_imm
, /* 4+ */ -1, -1, /* 12+ */ 47, 47)
434 F(3src_a1_src0_is_imm
, /* 4+ */ -1, -1, /* 12+ */ 46, 46)
436 /* Source Modifier fields same in align16 */
437 FC(3src_a1_dst_reg_file
, /* 4+ */ 36, 36, /* 12+ */ 50, 50, devinfo
->gen
>= 10)
438 FC(3src_a1_exec_type
, /* 4+ */ 35, 35, /* 12+ */ 39, 39, devinfo
->gen
>= 10)
439 /* Fields below this same in align16 */
442 #define REG_TYPE(reg) \
444 brw_inst_set_3src_a1_##reg##_type(const struct gen_device_info *devinfo, \
445 brw_inst *inst, enum brw_reg_type type) \
447 UNUSED enum gen10_align1_3src_exec_type exec_type = \
448 (enum gen10_align1_3src_exec_type) brw_inst_3src_a1_exec_type(devinfo, \
450 if (brw_reg_type_is_floating_point(type)) { \
451 assert(exec_type == BRW_ALIGN1_3SRC_EXEC_TYPE_FLOAT); \
453 assert(exec_type == BRW_ALIGN1_3SRC_EXEC_TYPE_INT); \
455 unsigned hw_type = brw_reg_type_to_a1_hw_3src_type(devinfo, type); \
456 brw_inst_set_3src_a1_##reg##_hw_type(devinfo, inst, hw_type); \
459 static inline enum brw_reg_type \
460 brw_inst_3src_a1_##reg##_type(const struct gen_device_info *devinfo, \
461 const brw_inst *inst) \
463 enum gen10_align1_3src_exec_type exec_type = \
464 (enum gen10_align1_3src_exec_type) brw_inst_3src_a1_exec_type(devinfo, \
466 unsigned hw_type = brw_inst_3src_a1_##reg##_hw_type(devinfo, inst); \
467 return brw_a1_hw_3src_type_to_reg_type(devinfo, hw_type, exec_type); \
477 * Three-source align1 instruction immediates:
480 static inline uint16_t
481 brw_inst_3src_a1_src0_imm(ASSERTED
const struct gen_device_info
*devinfo
,
482 const brw_inst
*insn
)
484 assert(devinfo
->gen
>= 10);
485 if (devinfo
->gen
>= 12)
486 return brw_inst_bits(insn
, 79, 64);
488 return brw_inst_bits(insn
, 82, 67);
491 static inline uint16_t
492 brw_inst_3src_a1_src2_imm(ASSERTED
const struct gen_device_info
*devinfo
,
493 const brw_inst
*insn
)
495 assert(devinfo
->gen
>= 10);
496 if (devinfo
->gen
>= 12)
497 return brw_inst_bits(insn
, 127, 112);
499 return brw_inst_bits(insn
, 124, 109);
503 brw_inst_set_3src_a1_src0_imm(ASSERTED
const struct gen_device_info
*devinfo
,
504 brw_inst
*insn
, uint16_t value
)
506 assert(devinfo
->gen
>= 10);
507 if (devinfo
->gen
>= 12)
508 brw_inst_set_bits(insn
, 79, 64, value
);
510 brw_inst_set_bits(insn
, 82, 67, value
);
514 brw_inst_set_3src_a1_src2_imm(ASSERTED
const struct gen_device_info
*devinfo
,
515 brw_inst
*insn
, uint16_t value
)
517 assert(devinfo
->gen
>= 10);
518 if (devinfo
->gen
>= 12)
519 brw_inst_set_bits(insn
, 127, 112, value
);
521 brw_inst_set_bits(insn
, 124, 109, value
);
526 * Flow control instruction bits:
530 brw_inst_set_uip(const struct gen_device_info
*devinfo
,
531 brw_inst
*inst
, int32_t value
)
533 assert(devinfo
->gen
>= 6);
535 if (devinfo
->gen
>= 12)
536 brw_inst_set_src1_is_imm(devinfo
, inst
, 1);
538 if (devinfo
->gen
>= 8) {
539 brw_inst_set_bits(inst
, 95, 64, (uint32_t)value
);
541 assert(value
<= (1 << 16) - 1);
542 assert(value
> -(1 << 16));
543 brw_inst_set_bits(inst
, 127, 112, (uint16_t)value
);
547 static inline int32_t
548 brw_inst_uip(const struct gen_device_info
*devinfo
, const brw_inst
*inst
)
550 assert(devinfo
->gen
>= 6);
552 if (devinfo
->gen
>= 8) {
553 return brw_inst_bits(inst
, 95, 64);
555 return (int16_t)brw_inst_bits(inst
, 127, 112);
560 brw_inst_set_jip(const struct gen_device_info
*devinfo
,
561 brw_inst
*inst
, int32_t value
)
563 assert(devinfo
->gen
>= 6);
565 if (devinfo
->gen
>= 12)
566 brw_inst_set_src0_is_imm(devinfo
, inst
, 1);
568 if (devinfo
->gen
>= 8) {
569 brw_inst_set_bits(inst
, 127, 96, (uint32_t)value
);
571 assert(value
<= (1 << 15) - 1);
572 assert(value
>= -(1 << 15));
573 brw_inst_set_bits(inst
, 111, 96, (uint16_t)value
);
577 static inline int32_t
578 brw_inst_jip(const struct gen_device_info
*devinfo
, const brw_inst
*inst
)
580 assert(devinfo
->gen
>= 6);
582 if (devinfo
->gen
>= 8) {
583 return brw_inst_bits(inst
, 127, 96);
585 return (int16_t)brw_inst_bits(inst
, 111, 96);
589 /** Like FC, but using int16_t to handle negative jump targets. */
590 #define FJ(name, high, low, assertions) \
592 brw_inst_set_##name(const struct gen_device_info *devinfo, brw_inst *inst, int16_t v) \
594 assert(assertions); \
596 brw_inst_set_bits(inst, high, low, (uint16_t) v); \
598 static inline int16_t \
599 brw_inst_##name(const struct gen_device_info *devinfo, const brw_inst *inst) \
601 assert(assertions); \
603 return brw_inst_bits(inst, high, low); \
606 FJ(gen6_jump_count
, 63, 48, devinfo
->gen
== 6)
607 FJ(gen4_jump_count
, 111, 96, devinfo
->gen
< 6)
608 FC(gen4_pop_count
, /* 4+ */ 115, 112, /* 12+ */ -1, -1, devinfo
->gen
< 6)
615 FC(send_ex_desc_ia_subreg_nr
, /* 4+ */ 82, 80, /* 12+ */ -1, -1, devinfo
->gen
>= 9)
616 FC(send_src0_address_mode
, /* 4+ */ 79, 79, /* 12+ */ -1, -1, devinfo
->gen
>= 9)
617 FC(send_sel_reg32_desc
, /* 4+ */ 77, 77, /* 12+ */ -1, -1, devinfo
->gen
>= 9)
618 FC(send_sel_reg32_ex_desc
, /* 4+ */ 61, 61, /* 12+ */ -1, -1, devinfo
->gen
>= 9)
619 FC(send_src1_reg_nr
, /* 4+ */ 51, 44, /* 12+ */ -1, -1, devinfo
->gen
>= 9)
620 FC(send_src1_reg_file
, /* 4+ */ 36, 36, /* 12+ */ -1, -1, devinfo
->gen
>= 9)
621 FC(send_dst_reg_file
, /* 4+ */ 35, 35, /* 12+ */ -1, -1, devinfo
->gen
>= 9)
624 /* Message descriptor bits */
625 #define MD(x) ((x) + 96)
628 * Set the SEND(C) message descriptor immediate.
630 * This doesn't include the SFID nor the EOT field that were considered to be
631 * part of the message descriptor by ancient versions of the BSpec, because
632 * they are present in the instruction even if the message descriptor is
633 * provided indirectly in the address register, so we want to specify them
637 brw_inst_set_send_desc(const struct gen_device_info
*devinfo
,
638 brw_inst
*inst
, uint32_t value
)
640 if (devinfo
->gen
>= 9) {
641 brw_inst_set_bits(inst
, 126, 96, value
);
642 assert(value
>> 31 == 0);
643 } else if (devinfo
->gen
>= 5) {
644 brw_inst_set_bits(inst
, 124, 96, value
);
645 assert(value
>> 29 == 0);
647 brw_inst_set_bits(inst
, 119, 96, value
);
648 assert(value
>> 24 == 0);
653 * Get the SEND(C) message descriptor immediate.
655 * \sa brw_inst_set_send_desc().
657 static inline uint32_t
658 brw_inst_send_desc(const struct gen_device_info
*devinfo
, const brw_inst
*inst
)
660 if (devinfo
->gen
>= 9)
661 return brw_inst_bits(inst
, 126, 96);
662 else if (devinfo
->gen
>= 5)
663 return brw_inst_bits(inst
, 124, 96);
665 return brw_inst_bits(inst
, 119, 96);
669 * Set the SEND(C) message extended descriptor immediate.
671 * This doesn't include the SFID nor the EOT field that were considered to be
672 * part of the extended message descriptor by some versions of the BSpec,
673 * because they are present in the instruction even if the extended message
674 * descriptor is provided indirectly in a register, so we want to specify them
678 brw_inst_set_send_ex_desc(const struct gen_device_info
*devinfo
,
679 brw_inst
*inst
, uint32_t value
)
681 assert(devinfo
->gen
>= 9);
682 brw_inst_set_bits(inst
, 94, 91, GET_BITS(value
, 31, 28));
683 brw_inst_set_bits(inst
, 88, 85, GET_BITS(value
, 27, 24));
684 brw_inst_set_bits(inst
, 83, 80, GET_BITS(value
, 23, 20));
685 brw_inst_set_bits(inst
, 67, 64, GET_BITS(value
, 19, 16));
686 assert(GET_BITS(value
, 15, 0) == 0);
690 * Set the SENDS(C) message extended descriptor immediate.
692 * This doesn't include the SFID nor the EOT field that were considered to be
693 * part of the extended message descriptor by some versions of the BSpec,
694 * because they are present in the instruction even if the extended message
695 * descriptor is provided indirectly in a register, so we want to specify them
699 brw_inst_set_sends_ex_desc(const struct gen_device_info
*devinfo
,
700 brw_inst
*inst
, uint32_t value
)
702 brw_inst_set_bits(inst
, 95, 80, GET_BITS(value
, 31, 16));
703 assert(GET_BITS(value
, 15, 10) == 0);
704 brw_inst_set_bits(inst
, 67, 64, GET_BITS(value
, 9, 6));
705 assert(GET_BITS(value
, 5, 0) == 0);
709 * Get the SEND(C) message extended descriptor immediate.
711 * \sa brw_inst_set_send_ex_desc().
713 static inline uint32_t
714 brw_inst_send_ex_desc(const struct gen_device_info
*devinfo
,
715 const brw_inst
*inst
)
717 assert(devinfo
->gen
>= 9);
718 return (brw_inst_bits(inst
, 94, 91) << 28 |
719 brw_inst_bits(inst
, 88, 85) << 24 |
720 brw_inst_bits(inst
, 83, 80) << 20 |
721 brw_inst_bits(inst
, 67, 64) << 16);
725 * Get the SENDS(C) message extended descriptor immediate.
727 * \sa brw_inst_set_send_ex_desc().
729 static inline uint32_t
730 brw_inst_sends_ex_desc(const struct gen_device_info
*devinfo
,
731 const brw_inst
*inst
)
733 return (brw_inst_bits(inst
, 95, 80) << 16 |
734 brw_inst_bits(inst
, 67, 64) << 6);
738 * Fields for SEND messages:
741 F(eot
, /* 4+ */ 127, 127, /* 12+ */ -1, -1)
759 /* 4: doesn't exist */ -1, -1, -1, -1,
765 F(gateway_notify
, /* 4+ */ MD(16), MD(15), /* 12+ */ -1, -1)
774 FF(gateway_subfuncid
,
775 /* 4: */ MD(1), MD(0),
776 /* 4.5: */ MD(1), MD(0),
777 /* 5: */ MD(1), MD(0), /* 2:0, but bit 2 is reserved MBZ */
778 /* 6: */ MD(2), MD(0),
779 /* 7: */ MD(2), MD(0),
780 /* 8: */ MD(2), MD(0),
783 /* 4: */ 123, 120, /* called msg_target */
791 /* 4-7: */ -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
793 /* 12: */ -1, -1) /* actually only Gen11+ */
794 FC(base_mrf
, /* 4+ */ 27, 24, /* 12+ */ -1, -1, devinfo
->gen
< 6);
798 * URB message function control bits:
801 FF(urb_per_slot_offset
,
802 /* 4-6: */ -1, -1, -1, -1, -1, -1, -1, -1,
803 /* 7: */ MD(16), MD(16),
804 /* 8: */ MD(17), MD(17),
806 FC(urb_channel_mask_present
, /* 4+ */ MD(15), MD(15), /* 12+ */ -1, -1, devinfo
->gen
>= 8)
807 FC(urb_complete
, /* 4+ */ MD(15), MD(15), /* 12+ */ -1, -1, devinfo
->gen
< 8)
808 FC(urb_used
, /* 4+ */ MD(14), MD(14), /* 12+ */ -1, -1, devinfo
->gen
< 7)
809 FC(urb_allocate
, /* 4+ */ MD(13), MD(13), /* 12+ */ -1, -1, devinfo
->gen
< 7)
810 FF(urb_swizzle_control
,
811 /* 4: */ MD(11), MD(10),
812 /* 4.5: */ MD(11), MD(10),
813 /* 5: */ MD(11), MD(10),
814 /* 6: */ MD(11), MD(10),
815 /* 7: */ MD(14), MD(14),
816 /* 8: */ MD(15), MD(15),
818 FF(urb_global_offset
,
819 /* 4: */ MD( 9), MD(4),
820 /* 4.5: */ MD( 9), MD(4),
821 /* 5: */ MD( 9), MD(4),
822 /* 6: */ MD( 9), MD(4),
823 /* 7: */ MD(13), MD(3),
824 /* 8: */ MD(14), MD(4),
827 /* 4: */ MD( 3), MD(0),
828 /* 4.5: */ MD( 3), MD(0),
829 /* 5: */ MD( 3), MD(0),
830 /* 6: */ MD( 3), MD(0),
831 /* 7: */ MD( 2), MD(0),
832 /* 8: */ MD( 3), MD(0),
837 * Gen4-5 math messages:
840 FC(math_msg_data_type
, /* 4+ */ MD(7), MD(7), /* 12+ */ -1, -1, devinfo
->gen
< 6)
841 FC(math_msg_saturate
, /* 4+ */ MD(6), MD(6), /* 12+ */ -1, -1, devinfo
->gen
< 6)
842 FC(math_msg_precision
, /* 4+ */ MD(5), MD(5), /* 12+ */ -1, -1, devinfo
->gen
< 6)
843 FC(math_msg_signed_int
, /* 4+ */ MD(4), MD(4), /* 12+ */ -1, -1, devinfo
->gen
< 6)
844 FC(math_msg_function
, /* 4+ */ MD(3), MD(0), /* 12+ */ -1, -1, devinfo
->gen
< 6)
848 * Sampler message function control bits:
851 FF(sampler_simd_mode
,
852 /* 4: doesn't exist */ -1, -1, -1, -1,
853 /* 5: */ MD(17), MD(16),
854 /* 6: */ MD(17), MD(16),
855 /* 7: */ MD(18), MD(17),
856 /* 8: */ MD(18), MD(17),
859 /* 4: */ MD(15), MD(14),
860 /* 4.5: */ MD(15), MD(12),
861 /* 5: */ MD(15), MD(12),
862 /* 6: */ MD(15), MD(12),
863 /* 7: */ MD(16), MD(12),
864 /* 8: */ MD(16), MD(12),
866 FC(sampler_return_format
, /* 4+ */ MD(13), MD(12), /* 12+ */ -1, -1, devinfo
->gen
== 4 && !devinfo
->is_g4x
)
867 F(sampler
, /* 4+ */ MD(11), MD(8), /* 12+ */ -1, -1)
868 F(binding_table_index
, /* 4+ */ MD( 7), MD(0), /* 12+ */ -1, -1) /* also used by other messages */
872 * Data port message function control bits:
875 FC(dp_category
, /* 4+ */ MD(18), MD(18), /* 12+ */ -1, -1, devinfo
->gen
>= 7)
877 /* Gen4-5 store fields in different bits for read/write messages. */
879 /* 4: */ MD(13), MD(12),
880 /* 4.5: */ MD(13), MD(11),
881 /* 5: */ MD(13), MD(11),
882 /* 6: */ MD(16), MD(13),
883 /* 7: */ MD(17), MD(14),
884 /* 8: */ MD(17), MD(14),
886 FF(dp_write_msg_type
,
887 /* 4: */ MD(14), MD(12),
888 /* 4.5: */ MD(14), MD(12),
889 /* 5: */ MD(14), MD(12),
890 /* 6: */ MD(16), MD(13),
891 /* 7: */ MD(17), MD(14),
892 /* 8: */ MD(17), MD(14),
894 FF(dp_read_msg_control
,
895 /* 4: */ MD(11), MD( 8),
896 /* 4.5: */ MD(10), MD( 8),
897 /* 5: */ MD(10), MD( 8),
898 /* 6: */ MD(12), MD( 8),
899 /* 7: */ MD(13), MD( 8),
900 /* 8: */ MD(13), MD( 8),
902 FF(dp_write_msg_control
,
903 /* 4: */ MD(11), MD( 8),
904 /* 4.5: */ MD(11), MD( 8),
905 /* 5: */ MD(11), MD( 8),
906 /* 6: */ MD(12), MD( 8),
907 /* 7: */ MD(13), MD( 8),
908 /* 8: */ MD(13), MD( 8),
910 FC(dp_read_target_cache
, /* 4+ */ MD(15), MD(14), /* 12+ */ -1, -1, devinfo
->gen
< 6);
913 /* 4: */ MD(15), MD(15),
914 /* 4.5: */ MD(15), MD(15),
915 /* 5: */ MD(15), MD(15),
916 /* 6: */ MD(17), MD(17),
917 /* 7+: does not exist */ -1, -1, -1, -1,
920 /* Gen6+ use the same bit locations for everything. */
922 /* 4-5: use dp_read_msg_type or dp_write_msg_type instead */
923 -1, -1, -1, -1, -1, -1,
924 /* 6: */ MD(16), MD(13),
925 /* 7: */ MD(17), MD(14),
926 /* 8: */ MD(18), MD(14),
929 /* 4: */ MD(11), MD( 8),
930 /* 4.5-5: use dp_read_msg_control or dp_write_msg_control */ -1, -1, -1, -1,
931 /* 6: */ MD(12), MD( 8),
932 /* 7: */ MD(13), MD( 8),
933 /* 8: */ MD(13), MD( 8),
938 * Scratch message bits (Gen7+):
941 FC(scratch_read_write
, /* 4+ */ MD(17), MD(17), /* 12+ */ -1, -1, devinfo
->gen
>= 7) /* 0 = read, 1 = write */
942 FC(scratch_type
, /* 4+ */ MD(16), MD(16), /* 12+ */ -1, -1, devinfo
->gen
>= 7) /* 0 = OWord, 1 = DWord */
943 FC(scratch_invalidate_after_read
, /* 4+ */ MD(15), MD(15), /* 12+ */ -1, -1, devinfo
->gen
>= 7)
944 FC(scratch_block_size
, /* 4+ */ MD(13), MD(12), /* 12+ */ -1, -1, devinfo
->gen
>= 7)
945 FC(scratch_addr_offset
, /* 4+ */ MD(11), MD( 0), /* 12+ */ -1, -1, devinfo
->gen
>= 7)
949 * Render Target message function control bits:
953 /* 4: */ MD(11), MD(11),
954 /* 4.5: */ MD(11), MD(11),
955 /* 5: */ MD(11), MD(11),
956 /* 6: */ MD(12), MD(12),
957 /* 7: */ MD(12), MD(12),
958 /* 8: */ MD(12), MD(12),
960 FC(rt_slot_group
, /* 4+ */ MD(11), MD(11), /* 12+ */ -1, -1, devinfo
->gen
>= 6)
961 F(rt_message_type
, /* 4+ */ MD(10), MD( 8), /* 12+ */ -1, -1)
965 * Thread Spawn message function control bits:
968 F(ts_resource_select
, /* 4+ */ MD( 4), MD( 4), /* 12+ */ -1, -1)
969 F(ts_request_type
, /* 4+ */ MD( 1), MD( 1), /* 12+ */ -1, -1)
970 F(ts_opcode
, /* 4+ */ MD( 0), MD( 0), /* 12+ */ -1, -1)
974 * Pixel Interpolator message function control bits:
977 F(pi_simd_mode
, /* 4+ */ MD(16), MD(16), /* 12+ */ -1, -1)
978 F(pi_nopersp
, /* 4+ */ MD(14), MD(14), /* 12+ */ -1, -1)
979 F(pi_message_type
, /* 4+ */ MD(13), MD(12), /* 12+ */ -1, -1)
980 F(pi_slot_group
, /* 4+ */ MD(11), MD(11), /* 12+ */ -1, -1)
981 F(pi_message_data
, /* 4+ */ MD(7), MD(0), /* 12+ */ -1, -1)
989 brw_inst_imm_d(const struct gen_device_info
*devinfo
, const brw_inst
*insn
)
992 return brw_inst_bits(insn
, 127, 96);
995 static inline unsigned
996 brw_inst_imm_ud(const struct gen_device_info
*devinfo
, const brw_inst
*insn
)
999 return brw_inst_bits(insn
, 127, 96);
1002 static inline uint64_t
1003 brw_inst_imm_uq(ASSERTED
const struct gen_device_info
*devinfo
,
1004 const brw_inst
*insn
)
1006 assert(devinfo
->gen
>= 8);
1007 return brw_inst_bits(insn
, 127, 64);
1011 brw_inst_imm_f(const struct gen_device_info
*devinfo
, const brw_inst
*insn
)
1018 ft
.u
= brw_inst_bits(insn
, 127, 96);
1022 static inline double
1023 brw_inst_imm_df(const struct gen_device_info
*devinfo
, const brw_inst
*insn
)
1030 dt
.u
= brw_inst_bits(insn
, 127, 64);
1035 brw_inst_set_imm_d(const struct gen_device_info
*devinfo
,
1036 brw_inst
*insn
, int value
)
1039 return brw_inst_set_bits(insn
, 127, 96, value
);
1043 brw_inst_set_imm_ud(const struct gen_device_info
*devinfo
,
1044 brw_inst
*insn
, unsigned value
)
1047 return brw_inst_set_bits(insn
, 127, 96, value
);
1051 brw_inst_set_imm_f(const struct gen_device_info
*devinfo
,
1052 brw_inst
*insn
, float value
)
1060 brw_inst_set_bits(insn
, 127, 96, ft
.u
);
1064 brw_inst_set_imm_df(const struct gen_device_info
*devinfo
,
1065 brw_inst
*insn
, double value
)
1073 brw_inst_set_bits(insn
, 127, 64, dt
.u
);
1077 brw_inst_set_imm_uq(const struct gen_device_info
*devinfo
,
1078 brw_inst
*insn
, uint64_t value
)
1081 brw_inst_set_bits(insn
, 127, 64, value
);
1086 #define REG_TYPE(reg) \
1087 static inline void \
1088 brw_inst_set_##reg##_file_type(const struct gen_device_info *devinfo, \
1089 brw_inst *inst, enum brw_reg_file file, \
1090 enum brw_reg_type type) \
1092 assert(file <= BRW_IMMEDIATE_VALUE); \
1093 unsigned hw_type = brw_reg_type_to_hw_type(devinfo, file, type); \
1094 brw_inst_set_##reg##_reg_file(devinfo, inst, file); \
1095 brw_inst_set_##reg##_reg_hw_type(devinfo, inst, hw_type); \
1098 static inline enum brw_reg_type \
1099 brw_inst_##reg##_type(const struct gen_device_info *devinfo, \
1100 const brw_inst *inst) \
1102 unsigned file = __builtin_strcmp("dst", #reg) == 0 ? \
1103 (unsigned) BRW_GENERAL_REGISTER_FILE : \
1104 brw_inst_##reg##_reg_file(devinfo, inst); \
1105 unsigned hw_type = brw_inst_##reg##_reg_hw_type(devinfo, inst); \
1106 return brw_hw_type_to_reg_type(devinfo, (enum brw_reg_file)file, hw_type); \
1115 /* The AddrImm fields are split into two discontiguous sections on Gen8+ */
1116 #define BRW_IA1_ADDR_IMM(reg, g4_high, g4_low, g8_nine, g8_high, g8_low) \
1117 static inline void \
1118 brw_inst_set_##reg##_ia1_addr_imm(const struct gen_device_info *devinfo, \
1122 assert((value & ~0x3ff) == 0); \
1123 if (devinfo->gen >= 8) { \
1124 brw_inst_set_bits(inst, g8_high, g8_low, value & 0x1ff); \
1125 brw_inst_set_bits(inst, g8_nine, g8_nine, value >> 9); \
1127 brw_inst_set_bits(inst, g4_high, g4_low, value); \
1130 static inline unsigned \
1131 brw_inst_##reg##_ia1_addr_imm(const struct gen_device_info *devinfo, \
1132 const brw_inst *inst) \
1134 if (devinfo->gen >= 8) { \
1135 return brw_inst_bits(inst, g8_high, g8_low) | \
1136 (brw_inst_bits(inst, g8_nine, g8_nine) << 9); \
1138 return brw_inst_bits(inst, g4_high, g4_low); \
1142 /* AddrImm[9:0] for Align1 Indirect Addressing */
1143 /* -Gen 4- ----Gen8---- */
1144 BRW_IA1_ADDR_IMM(src1
, 105, 96, 121, 104, 96)
1145 BRW_IA1_ADDR_IMM(src0
, 73, 64, 95, 72, 64)
1146 BRW_IA1_ADDR_IMM(dst
, 57, 48, 47, 56, 48)
1148 #define BRW_IA16_ADDR_IMM(reg, g4_high, g4_low, g8_nine, g8_high, g8_low) \
1149 static inline void \
1150 brw_inst_set_##reg##_ia16_addr_imm(const struct gen_device_info *devinfo, \
1151 brw_inst *inst, unsigned value) \
1153 assert((value & ~0x3ff) == 0); \
1154 if (devinfo->gen >= 8) { \
1155 assert(GET_BITS(value, 3, 0) == 0); \
1156 brw_inst_set_bits(inst, g8_high, g8_low, GET_BITS(value, 8, 4)); \
1157 brw_inst_set_bits(inst, g8_nine, g8_nine, GET_BITS(value, 9, 9)); \
1159 brw_inst_set_bits(inst, g4_high, g4_low, value); \
1162 static inline unsigned \
1163 brw_inst_##reg##_ia16_addr_imm(const struct gen_device_info *devinfo, \
1164 const brw_inst *inst) \
1166 if (devinfo->gen >= 8) { \
1167 return (brw_inst_bits(inst, g8_high, g8_low) << 4) | \
1168 (brw_inst_bits(inst, g8_nine, g8_nine) << 9); \
1170 return brw_inst_bits(inst, g4_high, g4_low); \
1174 /* AddrImm[9:0] for Align16 Indirect Addressing:
1175 * Compared to Align1, these are missing the low 4 bits.
1176 * -Gen 4- ----Gen8----
1178 BRW_IA16_ADDR_IMM(src1
, 105, 96, 121, 104, 100)
1179 BRW_IA16_ADDR_IMM(src0
, 73, 64, 95, 72, 68)
1180 BRW_IA16_ADDR_IMM(dst
, 57, 52, 47, 56, 52)
1181 BRW_IA16_ADDR_IMM(send_src0
, -1, -1, 78, 72, 68)
1182 BRW_IA16_ADDR_IMM(send_dst
, -1, -1, 62, 56, 52)
1185 * Fetch a set of contiguous bits from the instruction.
1187 * Bits indices range from 0..127; fields may not cross 64-bit boundaries.
1189 static inline uint64_t
1190 brw_inst_bits(const brw_inst
*inst
, unsigned high
, unsigned low
)
1192 assert(high
>= low
);
1193 /* We assume the field doesn't cross 64-bit boundaries. */
1194 const unsigned word
= high
/ 64;
1195 assert(word
== low
/ 64);
1200 const uint64_t mask
= (~0ull >> (64 - (high
- low
+ 1)));
1202 return (inst
->data
[word
] >> low
) & mask
;
1206 * Set bits in the instruction, with proper shifting and masking.
1208 * Bits indices range from 0..127; fields may not cross 64-bit boundaries.
1211 brw_inst_set_bits(brw_inst
*inst
, unsigned high
, unsigned low
, uint64_t value
)
1213 assert(high
>= low
);
1214 const unsigned word
= high
/ 64;
1215 assert(word
== low
/ 64);
1220 const uint64_t mask
= (~0ull >> (64 - (high
- low
+ 1))) << low
;
1222 /* Make sure the supplied value actually fits in the given bitfield. */
1223 assert((value
& (mask
>> low
)) == value
);
1225 inst
->data
[word
] = (inst
->data
[word
] & ~mask
) | (value
<< low
);
1228 #undef BRW_IA16_ADDR_IMM
1229 #undef BRW_IA1_ADDR_IMM
1242 * Fetch a set of contiguous bits from the compacted instruction.
1244 * Bits indices range from 0..63.
1246 static inline unsigned
1247 brw_compact_inst_bits(const brw_compact_inst
*inst
, unsigned high
, unsigned low
)
1249 const uint64_t mask
= (1ull << (high
- low
+ 1)) - 1;
1251 return (inst
->data
>> low
) & mask
;
1255 * Set bits in the compacted instruction.
1257 * Bits indices range from 0..63.
1260 brw_compact_inst_set_bits(brw_compact_inst
*inst
, unsigned high
, unsigned low
,
1263 const uint64_t mask
= ((1ull << (high
- low
+ 1)) - 1) << low
;
1265 /* Make sure the supplied value actually fits in the given bitfield. */
1266 assert((value
& (mask
>> low
)) == value
);
1268 inst
->data
= (inst
->data
& ~mask
) | (value
<< low
);
1271 #define FC(name, high, low, assertions) \
1272 static inline void \
1273 brw_compact_inst_set_##name(const struct gen_device_info *devinfo, \
1274 brw_compact_inst *inst, unsigned v) \
1276 assert(assertions); \
1278 brw_compact_inst_set_bits(inst, high, low, v); \
1280 static inline unsigned \
1281 brw_compact_inst_##name(const struct gen_device_info *devinfo, \
1282 const brw_compact_inst *inst) \
1284 assert(assertions); \
1286 return brw_compact_inst_bits(inst, high, low); \
1289 /* A simple macro for fields which stay in the same place on all generations. */
1290 #define F(name, high, low) FC(name, high, low, true)
1292 F(src1_reg_nr
, 63, 56)
1293 F(src0_reg_nr
, 55, 48)
1294 F(dst_reg_nr
, 47, 40)
1295 F(src1_index
, 39, 35)
1296 F(src0_index
, 34, 30)
1297 F(cmpt_control
, 29, 29) /* Same location as brw_inst */
1298 FC(flag_subreg_nr
, 28, 28, devinfo
->gen
<= 6)
1299 F(cond_modifier
, 27, 24) /* Same location as brw_inst */
1300 FC(acc_wr_control
, 23, 23, devinfo
->gen
>= 6)
1301 FC(mask_control_ex
, 23, 23, devinfo
->is_g4x
|| devinfo
->gen
== 5)
1302 F(subreg_index
, 22, 18)
1303 F(datatype_index
, 17, 13)
1304 F(control_index
, 12, 8)
1305 F(debug_control
, 7, 7)
1306 F(hw_opcode
, 6, 0) /* Same location as brw_inst */
1309 * (Gen8+) Compacted three-source instructions:
1312 FC(3src_src2_reg_nr
, 63, 57, devinfo
->gen
>= 8)
1313 FC(3src_src1_reg_nr
, 56, 50, devinfo
->gen
>= 8)
1314 FC(3src_src0_reg_nr
, 49, 43, devinfo
->gen
>= 8)
1315 FC(3src_src2_subreg_nr
, 42, 40, devinfo
->gen
>= 8)
1316 FC(3src_src1_subreg_nr
, 39, 37, devinfo
->gen
>= 8)
1317 FC(3src_src0_subreg_nr
, 36, 34, devinfo
->gen
>= 8)
1318 FC(3src_src2_rep_ctrl
, 33, 33, devinfo
->gen
>= 8)
1319 FC(3src_src1_rep_ctrl
, 32, 32, devinfo
->gen
>= 8)
1320 FC(3src_saturate
, 31, 31, devinfo
->gen
>= 8)
1321 FC(3src_debug_control
, 30, 30, devinfo
->gen
>= 8)
1322 FC(3src_cmpt_control
, 29, 29, devinfo
->gen
>= 8)
1323 FC(3src_src0_rep_ctrl
, 28, 28, devinfo
->gen
>= 8)
1325 FC(3src_dst_reg_nr
, 18, 12, devinfo
->gen
>= 8)
1326 FC(3src_source_index
, 11, 10, devinfo
->gen
>= 8)
1327 FC(3src_control_index
, 9, 8, devinfo
->gen
>= 8)
1328 /* Bit 7 is Reserved (for future Opcode expansion) */
1329 FC(3src_hw_opcode
, 6, 0, devinfo
->gen
>= 8)