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intel/compiler: Expand untyped atomic message type field by a bit
[mesa.git] / src / intel / compiler / brw_inst.h
1 /*
2 * Copyright © 2014 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 */
23
24 /**
25 * @file brw_inst.h
26 *
27 * A representation of i965 EU assembly instructions, with helper methods to
28 * get and set various fields. This is the actual hardware format.
29 */
30
31 #ifndef BRW_INST_H
32 #define BRW_INST_H
33
34 #include <assert.h>
35 #include <stdint.h>
36
37 #include "brw_eu_defines.h"
38 #include "brw_reg_type.h"
39 #include "dev/gen_device_info.h"
40
41 #ifdef __cplusplus
42 extern "C" {
43 #endif
44
45 /* brw_context.h has a forward declaration of brw_inst, so name the struct. */
46 typedef struct brw_inst {
47 uint64_t data[2];
48 } brw_inst;
49
50 static inline uint64_t brw_inst_bits(const brw_inst *inst,
51 unsigned high, unsigned low);
52 static inline void brw_inst_set_bits(brw_inst *inst,
53 unsigned high, unsigned low,
54 uint64_t value);
55
56 #define FC(name, high, low, assertions) \
57 static inline void \
58 brw_inst_set_##name(const struct gen_device_info *devinfo, \
59 brw_inst *inst, uint64_t v) \
60 { \
61 assert(assertions); \
62 (void) devinfo; \
63 brw_inst_set_bits(inst, high, low, v); \
64 } \
65 static inline uint64_t \
66 brw_inst_##name(const struct gen_device_info *devinfo, \
67 const brw_inst *inst) \
68 { \
69 assert(assertions); \
70 (void) devinfo; \
71 return brw_inst_bits(inst, high, low); \
72 }
73
74 /* A simple macro for fields which stay in the same place on all generations. */
75 #define F(name, high, low) FC(name, high, low, true)
76
77 #define BOUNDS(hi4, lo4, hi45, lo45, hi5, lo5, hi6, lo6, hi7, lo7, hi8, lo8) \
78 unsigned high, low; \
79 if (devinfo->gen >= 8) { \
80 high = hi8; low = lo8; \
81 } else if (devinfo->gen >= 7) { \
82 high = hi7; low = lo7; \
83 } else if (devinfo->gen >= 6) { \
84 high = hi6; low = lo6; \
85 } else if (devinfo->gen >= 5) { \
86 high = hi5; low = lo5; \
87 } else if (devinfo->is_g4x) { \
88 high = hi45; low = lo45; \
89 } else { \
90 high = hi4; low = lo4; \
91 } \
92 assert(((int) high) != -1 && ((int) low) != -1);
93
94 /* A general macro for cases where the field has moved to several different
95 * bit locations across generations. GCC appears to combine cases where the
96 * bits are identical, removing some of the inefficiency.
97 */
98 #define FF(name, hi4, lo4, hi45, lo45, hi5, lo5, hi6, lo6, hi7, lo7, hi8, lo8)\
99 static inline void \
100 brw_inst_set_##name(const struct gen_device_info *devinfo, \
101 brw_inst *inst, uint64_t value) \
102 { \
103 BOUNDS(hi4, lo4, hi45, lo45, hi5, lo5, hi6, lo6, hi7, lo7, hi8, lo8) \
104 brw_inst_set_bits(inst, high, low, value); \
105 } \
106 static inline uint64_t \
107 brw_inst_##name(const struct gen_device_info *devinfo, const brw_inst *inst) \
108 { \
109 BOUNDS(hi4, lo4, hi45, lo45, hi5, lo5, hi6, lo6, hi7, lo7, hi8, lo8) \
110 return brw_inst_bits(inst, high, low); \
111 }
112
113 /* A macro for fields which moved as of Gen8+. */
114 #define F8(name, gen4_high, gen4_low, gen8_high, gen8_low) \
115 FF(name, \
116 /* 4: */ gen4_high, gen4_low, \
117 /* 4.5: */ gen4_high, gen4_low, \
118 /* 5: */ gen4_high, gen4_low, \
119 /* 6: */ gen4_high, gen4_low, \
120 /* 7: */ gen4_high, gen4_low, \
121 /* 8: */ gen8_high, gen8_low);
122
123 F(src1_vstride, 120, 117)
124 F(src1_width, 116, 114)
125 F(src1_da16_swiz_w, 115, 114)
126 F(src1_da16_swiz_z, 113, 112)
127 F(src1_hstride, 113, 112)
128 F(src1_address_mode, 111, 111)
129 /** Src1.SrcMod @{ */
130 F(src1_negate, 110, 110)
131 F(src1_abs, 109, 109)
132 /** @} */
133 F8(src1_ia_subreg_nr, /* 4+ */ 108, 106, /* 8+ */ 108, 105)
134 F(src1_da_reg_nr, 108, 101)
135 F(src1_da16_subreg_nr, 100, 100)
136 F(src1_da1_subreg_nr, 100, 96)
137 F(src1_da16_swiz_y, 99, 98)
138 F(src1_da16_swiz_x, 97, 96)
139 F8(src1_reg_hw_type, /* 4+ */ 46, 44, /* 8+ */ 94, 91)
140 F8(src1_reg_file, /* 4+ */ 43, 42, /* 8+ */ 90, 89)
141 F(src0_vstride, 88, 85)
142 F(src0_width, 84, 82)
143 F(src0_da16_swiz_w, 83, 82)
144 F(src0_da16_swiz_z, 81, 80)
145 F(src0_hstride, 81, 80)
146 F(src0_address_mode, 79, 79)
147 /** Src0.SrcMod @{ */
148 F(src0_negate, 78, 78)
149 F(src0_abs, 77, 77)
150 /** @} */
151 F8(src0_ia_subreg_nr, /* 4+ */ 76, 74, /* 8+ */ 76, 73)
152 F(src0_da_reg_nr, 76, 69)
153 F(src0_da16_subreg_nr, 68, 68)
154 F(src0_da1_subreg_nr, 68, 64)
155 F(src0_da16_swiz_y, 67, 66)
156 F(src0_da16_swiz_x, 65, 64)
157 F(dst_address_mode, 63, 63)
158 F(dst_hstride, 62, 61)
159 F8(dst_ia_subreg_nr, /* 4+ */ 60, 58, /* 8+ */ 60, 57)
160 F(dst_da_reg_nr, 60, 53)
161 F(dst_da16_subreg_nr, 52, 52)
162 F(dst_da1_subreg_nr, 52, 48)
163 F(da16_writemask, 51, 48) /* Dst.ChanEn */
164 F8(src0_reg_hw_type, /* 4+ */ 41, 39, /* 8+ */ 46, 43)
165 F8(src0_reg_file, /* 4+ */ 38, 37, /* 8+ */ 42, 41)
166 F8(dst_reg_hw_type, /* 4+ */ 36, 34, /* 8+ */ 40, 37)
167 F8(dst_reg_file, /* 4+ */ 33, 32, /* 8+ */ 36, 35)
168 F8(mask_control, /* 4+ */ 9, 9, /* 8+ */ 34, 34)
169 FF(flag_reg_nr,
170 /* 4-6: doesn't exist */ -1, -1, -1, -1, -1, -1, -1, -1,
171 /* 7: */ 90, 90,
172 /* 8: */ 33, 33)
173 F8(flag_subreg_nr, /* 4+ */ 89, 89, /* 8+ */ 32, 32)
174 F(saturate, 31, 31)
175 F(debug_control, 30, 30)
176 F(cmpt_control, 29, 29)
177 FC(branch_control, 28, 28, devinfo->gen >= 8)
178 FC(acc_wr_control, 28, 28, devinfo->gen >= 6)
179 FC(mask_control_ex, 28, 28, devinfo->is_g4x || devinfo->gen == 5)
180 F(cond_modifier, 27, 24)
181 FC(math_function, 27, 24, devinfo->gen >= 6)
182 F(exec_size, 23, 21)
183 F(pred_inv, 20, 20)
184 F(pred_control, 19, 16)
185 F(thread_control, 15, 14)
186 F(qtr_control, 13, 12)
187 FF(nib_control,
188 /* 4-6: doesn't exist */ -1, -1, -1, -1, -1, -1, -1, -1,
189 /* 7: */ 47, 47,
190 /* 8: */ 11, 11)
191 F8(no_dd_check, /* 4+ */ 11, 11, /* 8+ */ 10, 10)
192 F8(no_dd_clear, /* 4+ */ 10, 10, /* 8+ */ 9, 9)
193 F(access_mode, 8, 8)
194 /* Bit 7 is Reserved (for future Opcode expansion) */
195 F(opcode, 6, 0)
196
197 /**
198 * Three-source instructions:
199 * @{
200 */
201 F(3src_src2_reg_nr, 125, 118) /* same in align1 */
202 F(3src_a16_src2_subreg_nr, 117, 115) /* Extra discontiguous bit on CHV? */
203 F(3src_a16_src2_swizzle, 114, 107)
204 F(3src_a16_src2_rep_ctrl, 106, 106)
205 F(3src_src1_reg_nr, 104, 97) /* same in align1 */
206 F(3src_a16_src1_subreg_nr, 96, 94) /* Extra discontiguous bit on CHV? */
207 F(3src_a16_src1_swizzle, 93, 86)
208 F(3src_a16_src1_rep_ctrl, 85, 85)
209 F(3src_src0_reg_nr, 83, 76) /* same in align1 */
210 F(3src_a16_src0_subreg_nr, 75, 73) /* Extra discontiguous bit on CHV? */
211 F(3src_a16_src0_swizzle, 72, 65)
212 F(3src_a16_src0_rep_ctrl, 64, 64)
213 F(3src_dst_reg_nr, 63, 56) /* same in align1 */
214 F(3src_a16_dst_subreg_nr, 55, 53)
215 F(3src_a16_dst_writemask, 52, 49)
216 F8(3src_a16_nib_ctrl, 47, 47, 11, 11) /* only exists on IVB+ */
217 F8(3src_a16_dst_hw_type, 45, 44, 48, 46) /* only exists on IVB+ */
218 F8(3src_a16_src_hw_type, 43, 42, 45, 43)
219 F8(3src_src2_negate, 41, 41, 42, 42)
220 F8(3src_src2_abs, 40, 40, 41, 41)
221 F8(3src_src1_negate, 39, 39, 40, 40)
222 F8(3src_src1_abs, 38, 38, 39, 39)
223 F8(3src_src0_negate, 37, 37, 38, 38)
224 F8(3src_src0_abs, 36, 36, 37, 37)
225 F8(3src_a16_flag_reg_nr, 34, 34, 33, 33)
226 F8(3src_a16_flag_subreg_nr, 33, 33, 32, 32)
227 FF(3src_a16_dst_reg_file,
228 /* 4-5: doesn't exist - no 3-source instructions */ -1, -1, -1, -1, -1, -1,
229 /* 6: */ 32, 32,
230 /* 7-8: doesn't exist - no MRFs */ -1, -1, -1, -1)
231 F(3src_saturate, 31, 31)
232 F(3src_debug_control, 30, 30)
233 F(3src_cmpt_control, 29, 29)
234 F(3src_acc_wr_control, 28, 28)
235 F(3src_cond_modifier, 27, 24)
236 F(3src_exec_size, 23, 21)
237 F(3src_pred_inv, 20, 20)
238 F(3src_pred_control, 19, 16)
239 F(3src_thread_control, 15, 14)
240 F(3src_qtr_control, 13, 12)
241 F8(3src_no_dd_check, 11, 11, 10, 10)
242 F8(3src_no_dd_clear, 10, 10, 9, 9)
243 F8(3src_mask_control, 9, 9, 34, 34)
244 F(3src_access_mode, 8, 8)
245 /* Bit 7 is Reserved (for future Opcode expansion) */
246 F(3src_opcode, 6, 0)
247 /** @} */
248
249 #define REG_TYPE(reg) \
250 static inline void \
251 brw_inst_set_3src_a16_##reg##_type(const struct gen_device_info *devinfo, \
252 brw_inst *inst, enum brw_reg_type type) \
253 { \
254 unsigned hw_type = brw_reg_type_to_a16_hw_3src_type(devinfo, type); \
255 brw_inst_set_3src_a16_##reg##_hw_type(devinfo, inst, hw_type); \
256 } \
257 \
258 static inline enum brw_reg_type \
259 brw_inst_3src_a16_##reg##_type(const struct gen_device_info *devinfo, \
260 const brw_inst *inst) \
261 { \
262 unsigned hw_type = brw_inst_3src_a16_##reg##_hw_type(devinfo, inst); \
263 return brw_a16_hw_3src_type_to_reg_type(devinfo, hw_type); \
264 }
265
266 REG_TYPE(dst)
267 REG_TYPE(src)
268 #undef REG_TYPE
269
270 /**
271 * Three-source align1 instructions:
272 * @{
273 */
274 /* Reserved 127:126 */
275 /* src2_reg_nr same in align16 */
276 FC(3src_a1_src2_subreg_nr, 117, 113, devinfo->gen >= 10)
277 FC(3src_a1_src2_hstride, 112, 111, devinfo->gen >= 10)
278 /* Reserved 110:109. src2 vstride is an implied parameter */
279 FC(3src_a1_src2_hw_type, 108, 106, devinfo->gen >= 10)
280 /* Reserved 105 */
281 /* src1_reg_nr same in align16 */
282 FC(3src_a1_src1_subreg_nr, 96, 92, devinfo->gen >= 10)
283 FC(3src_a1_src1_hstride, 91, 90, devinfo->gen >= 10)
284 FC(3src_a1_src1_vstride, 89, 88, devinfo->gen >= 10)
285 FC(3src_a1_src1_hw_type, 87, 85, devinfo->gen >= 10)
286 /* Reserved 84 */
287 /* src0_reg_nr same in align16 */
288 FC(3src_a1_src0_subreg_nr, 75, 71, devinfo->gen >= 10)
289 FC(3src_a1_src0_hstride, 70, 69, devinfo->gen >= 10)
290 FC(3src_a1_src0_vstride, 68, 67, devinfo->gen >= 10)
291 FC(3src_a1_src0_hw_type, 66, 64, devinfo->gen >= 10)
292 /* dst_reg_nr same in align16 */
293 FC(3src_a1_dst_subreg_nr, 55, 54, devinfo->gen >= 10)
294 FC(3src_a1_special_acc, 55, 52, devinfo->gen >= 10) /* aliases dst_subreg_nr */
295 /* Reserved 51:50 */
296 FC(3src_a1_dst_hstride, 49, 49, devinfo->gen >= 10)
297 FC(3src_a1_dst_hw_type, 48, 46, devinfo->gen >= 10)
298 FC(3src_a1_src2_reg_file, 45, 45, devinfo->gen >= 10)
299 FC(3src_a1_src1_reg_file, 44, 44, devinfo->gen >= 10)
300 FC(3src_a1_src0_reg_file, 43, 43, devinfo->gen >= 10)
301 /* Source Modifier fields same in align16 */
302 FC(3src_a1_dst_reg_file, 36, 36, devinfo->gen >= 10)
303 FC(3src_a1_exec_type, 35, 35, devinfo->gen >= 10)
304 /* Fields below this same in align16 */
305 /** @} */
306
307 #define REG_TYPE(reg) \
308 static inline void \
309 brw_inst_set_3src_a1_##reg##_type(const struct gen_device_info *devinfo, \
310 brw_inst *inst, enum brw_reg_type type) \
311 { \
312 UNUSED enum gen10_align1_3src_exec_type exec_type = \
313 (enum gen10_align1_3src_exec_type) brw_inst_3src_a1_exec_type(devinfo, \
314 inst); \
315 if (brw_reg_type_is_floating_point(type)) { \
316 assert(exec_type == BRW_ALIGN1_3SRC_EXEC_TYPE_FLOAT); \
317 } else { \
318 assert(exec_type == BRW_ALIGN1_3SRC_EXEC_TYPE_INT); \
319 } \
320 unsigned hw_type = brw_reg_type_to_a1_hw_3src_type(devinfo, type); \
321 brw_inst_set_3src_a1_##reg##_hw_type(devinfo, inst, hw_type); \
322 } \
323 \
324 static inline enum brw_reg_type \
325 brw_inst_3src_a1_##reg##_type(const struct gen_device_info *devinfo, \
326 const brw_inst *inst) \
327 { \
328 enum gen10_align1_3src_exec_type exec_type = \
329 (enum gen10_align1_3src_exec_type) brw_inst_3src_a1_exec_type(devinfo, \
330 inst); \
331 unsigned hw_type = brw_inst_3src_a1_##reg##_hw_type(devinfo, inst); \
332 return brw_a1_hw_3src_type_to_reg_type(devinfo, hw_type, exec_type); \
333 }
334
335 REG_TYPE(dst)
336 REG_TYPE(src0)
337 REG_TYPE(src1)
338 REG_TYPE(src2)
339 #undef REG_TYPE
340
341 /**
342 * Three-source align1 instruction immediates:
343 * @{
344 */
345 static inline uint16_t
346 brw_inst_3src_a1_src0_imm(MAYBE_UNUSED const struct gen_device_info *devinfo,
347 const brw_inst *insn)
348 {
349 assert(devinfo->gen >= 10);
350 return brw_inst_bits(insn, 82, 67);
351 }
352
353 static inline uint16_t
354 brw_inst_3src_a1_src2_imm(MAYBE_UNUSED const struct gen_device_info *devinfo,
355 const brw_inst *insn)
356 {
357 assert(devinfo->gen >= 10);
358 return brw_inst_bits(insn, 124, 109);
359 }
360
361 static inline void
362 brw_inst_set_3src_a1_src0_imm(MAYBE_UNUSED const struct gen_device_info *devinfo,
363 brw_inst *insn, uint16_t value)
364 {
365 assert(devinfo->gen >= 10);
366 brw_inst_set_bits(insn, 82, 67, value);
367 }
368
369 static inline void
370 brw_inst_set_3src_a1_src2_imm(MAYBE_UNUSED const struct gen_device_info *devinfo,
371 brw_inst *insn, uint16_t value)
372 {
373 assert(devinfo->gen >= 10);
374 brw_inst_set_bits(insn, 124, 109, value);
375 }
376 /** @} */
377
378 /**
379 * Flow control instruction bits:
380 * @{
381 */
382 static inline void
383 brw_inst_set_uip(const struct gen_device_info *devinfo,
384 brw_inst *inst, int32_t value)
385 {
386 assert(devinfo->gen >= 6);
387
388 if (devinfo->gen >= 8) {
389 brw_inst_set_bits(inst, 95, 64, (uint32_t)value);
390 } else {
391 assert(value <= (1 << 16) - 1);
392 assert(value > -(1 << 16));
393 brw_inst_set_bits(inst, 127, 112, (uint16_t)value);
394 }
395 }
396
397 static inline int32_t
398 brw_inst_uip(const struct gen_device_info *devinfo, const brw_inst *inst)
399 {
400 assert(devinfo->gen >= 6);
401
402 if (devinfo->gen >= 8) {
403 return brw_inst_bits(inst, 95, 64);
404 } else {
405 return (int16_t)brw_inst_bits(inst, 127, 112);
406 }
407 }
408
409 static inline void
410 brw_inst_set_jip(const struct gen_device_info *devinfo,
411 brw_inst *inst, int32_t value)
412 {
413 assert(devinfo->gen >= 6);
414
415 if (devinfo->gen >= 8) {
416 brw_inst_set_bits(inst, 127, 96, (uint32_t)value);
417 } else {
418 assert(value <= (1 << 15) - 1);
419 assert(value >= -(1 << 15));
420 brw_inst_set_bits(inst, 111, 96, (uint16_t)value);
421 }
422 }
423
424 static inline int32_t
425 brw_inst_jip(const struct gen_device_info *devinfo, const brw_inst *inst)
426 {
427 assert(devinfo->gen >= 6);
428
429 if (devinfo->gen >= 8) {
430 return brw_inst_bits(inst, 127, 96);
431 } else {
432 return (int16_t)brw_inst_bits(inst, 111, 96);
433 }
434 }
435
436 /** Like FC, but using int16_t to handle negative jump targets. */
437 #define FJ(name, high, low, assertions) \
438 static inline void \
439 brw_inst_set_##name(const struct gen_device_info *devinfo, brw_inst *inst, int16_t v) \
440 { \
441 assert(assertions); \
442 (void) devinfo; \
443 brw_inst_set_bits(inst, high, low, (uint16_t) v); \
444 } \
445 static inline int16_t \
446 brw_inst_##name(const struct gen_device_info *devinfo, const brw_inst *inst) \
447 { \
448 assert(assertions); \
449 (void) devinfo; \
450 return brw_inst_bits(inst, high, low); \
451 }
452
453 FJ(gen6_jump_count, 63, 48, devinfo->gen == 6)
454 FJ(gen4_jump_count, 111, 96, devinfo->gen < 6)
455 FC(gen4_pop_count, 115, 112, devinfo->gen < 6)
456 /** @} */
457
458 /* Message descriptor bits */
459 #define MD(x) ((x) + 96)
460
461 /**
462 * Set the SEND(C) message descriptor immediate.
463 *
464 * This doesn't include the SFID nor the EOT field that were considered to be
465 * part of the message descriptor by ancient versions of the BSpec, because
466 * they are present in the instruction even if the message descriptor is
467 * provided indirectly in the address register, so we want to specify them
468 * separately.
469 */
470 static inline void
471 brw_inst_set_send_desc(const struct gen_device_info *devinfo,
472 brw_inst *inst, uint32_t value)
473 {
474 if (devinfo->gen >= 9) {
475 brw_inst_set_bits(inst, 126, 96, value);
476 assert(value >> 31 == 0);
477 } else if (devinfo->gen >= 5) {
478 brw_inst_set_bits(inst, 124, 96, value);
479 assert(value >> 29 == 0);
480 } else {
481 brw_inst_set_bits(inst, 119, 96, value);
482 assert(value >> 24 == 0);
483 }
484 }
485
486 /**
487 * Get the SEND(C) message descriptor immediate.
488 *
489 * \sa brw_inst_set_send_desc().
490 */
491 static inline uint32_t
492 brw_inst_send_desc(const struct gen_device_info *devinfo, const brw_inst *inst)
493 {
494 if (devinfo->gen >= 9)
495 return brw_inst_bits(inst, 126, 96);
496 else if (devinfo->gen >= 5)
497 return brw_inst_bits(inst, 124, 96);
498 else
499 return brw_inst_bits(inst, 119, 96);
500 }
501
502 /**
503 * Set the SEND(C) message extended descriptor immediate.
504 *
505 * This doesn't include the SFID nor the EOT field that were considered to be
506 * part of the extended message descriptor by some versions of the BSpec,
507 * because they are present in the instruction even if the extended message
508 * descriptor is provided indirectly in a register, so we want to specify them
509 * separately.
510 */
511 static inline void
512 brw_inst_set_send_ex_desc(const struct gen_device_info *devinfo,
513 brw_inst *inst, uint32_t value)
514 {
515 assert(devinfo->gen >= 9);
516 brw_inst_set_bits(inst, 94, 91, (value >> 28) & ((1u << 4) - 1));
517 brw_inst_set_bits(inst, 88, 85, (value >> 24) & ((1u << 4) - 1));
518 brw_inst_set_bits(inst, 83, 80, (value >> 20) & ((1u << 4) - 1));
519 brw_inst_set_bits(inst, 67, 64, (value >> 16) & ((1u << 4) - 1));
520 assert((value & ((1u << 16) - 1)) == 0);
521 }
522
523 /**
524 * Get the SEND(C) message extended descriptor immediate.
525 *
526 * \sa brw_inst_set_send_ex_desc().
527 */
528 static inline uint32_t
529 brw_inst_send_ex_desc(const struct gen_device_info *devinfo,
530 const brw_inst *inst)
531 {
532 assert(devinfo->gen >= 9);
533 return (brw_inst_bits(inst, 94, 91) << 28 |
534 brw_inst_bits(inst, 88, 85) << 24 |
535 brw_inst_bits(inst, 83, 80) << 20 |
536 brw_inst_bits(inst, 67, 64) << 16);
537 }
538
539 /**
540 * Fields for SEND messages:
541 * @{
542 */
543 F(eot, 127, 127)
544 FF(mlen,
545 /* 4: */ 119, 116,
546 /* 4.5: */ 119, 116,
547 /* 5: */ 124, 121,
548 /* 6: */ 124, 121,
549 /* 7: */ 124, 121,
550 /* 8: */ 124, 121);
551 FF(rlen,
552 /* 4: */ 115, 112,
553 /* 4.5: */ 115, 112,
554 /* 5: */ 120, 116,
555 /* 6: */ 120, 116,
556 /* 7: */ 120, 116,
557 /* 8: */ 120, 116);
558 FF(header_present,
559 /* 4: doesn't exist */ -1, -1, -1, -1,
560 /* 5: */ 115, 115,
561 /* 6: */ 115, 115,
562 /* 7: */ 115, 115,
563 /* 8: */ 115, 115)
564 F(gateway_notify, MD(16), MD(15))
565 FF(function_control,
566 /* 4: */ 111, 96,
567 /* 4.5: */ 111, 96,
568 /* 5: */ 114, 96,
569 /* 6: */ 114, 96,
570 /* 7: */ 114, 96,
571 /* 8: */ 114, 96)
572 FF(gateway_subfuncid,
573 /* 4: */ MD(1), MD(0),
574 /* 4.5: */ MD(1), MD(0),
575 /* 5: */ MD(1), MD(0), /* 2:0, but bit 2 is reserved MBZ */
576 /* 6: */ MD(2), MD(0),
577 /* 7: */ MD(2), MD(0),
578 /* 8: */ MD(2), MD(0))
579 FF(sfid,
580 /* 4: */ 123, 120, /* called msg_target */
581 /* 4.5 */ 123, 120,
582 /* 5: */ 95, 92,
583 /* 6: */ 27, 24,
584 /* 7: */ 27, 24,
585 /* 8: */ 27, 24)
586 FF(null_rt,
587 /* 4-7: */ -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
588 /* 8: */ 80, 80) /* actually only Gen11+ */
589 FC(base_mrf, 27, 24, devinfo->gen < 6);
590 /** @} */
591
592 /**
593 * URB message function control bits:
594 * @{
595 */
596 FF(urb_per_slot_offset,
597 /* 4-6: */ -1, -1, -1, -1, -1, -1, -1, -1,
598 /* 7: */ MD(16), MD(16),
599 /* 8: */ MD(17), MD(17))
600 FC(urb_channel_mask_present, MD(15), MD(15), devinfo->gen >= 8)
601 FC(urb_complete, MD(15), MD(15), devinfo->gen < 8)
602 FC(urb_used, MD(14), MD(14), devinfo->gen < 7)
603 FC(urb_allocate, MD(13), MD(13), devinfo->gen < 7)
604 FF(urb_swizzle_control,
605 /* 4: */ MD(11), MD(10),
606 /* 4.5: */ MD(11), MD(10),
607 /* 5: */ MD(11), MD(10),
608 /* 6: */ MD(11), MD(10),
609 /* 7: */ MD(14), MD(14),
610 /* 8: */ MD(15), MD(15))
611 FF(urb_global_offset,
612 /* 4: */ MD( 9), MD(4),
613 /* 4.5: */ MD( 9), MD(4),
614 /* 5: */ MD( 9), MD(4),
615 /* 6: */ MD( 9), MD(4),
616 /* 7: */ MD(13), MD(3),
617 /* 8: */ MD(14), MD(4))
618 FF(urb_opcode,
619 /* 4: */ MD( 3), MD(0),
620 /* 4.5: */ MD( 3), MD(0),
621 /* 5: */ MD( 3), MD(0),
622 /* 6: */ MD( 3), MD(0),
623 /* 7: */ MD( 2), MD(0),
624 /* 8: */ MD( 3), MD(0))
625 /** @} */
626
627 /**
628 * Gen4-5 math messages:
629 * @{
630 */
631 FC(math_msg_data_type, MD(7), MD(7), devinfo->gen < 6)
632 FC(math_msg_saturate, MD(6), MD(6), devinfo->gen < 6)
633 FC(math_msg_precision, MD(5), MD(5), devinfo->gen < 6)
634 FC(math_msg_signed_int, MD(4), MD(4), devinfo->gen < 6)
635 FC(math_msg_function, MD(3), MD(0), devinfo->gen < 6)
636 /** @} */
637
638 /**
639 * Sampler message function control bits:
640 * @{
641 */
642 FF(sampler_simd_mode,
643 /* 4: doesn't exist */ -1, -1, -1, -1,
644 /* 5: */ MD(17), MD(16),
645 /* 6: */ MD(17), MD(16),
646 /* 7: */ MD(18), MD(17),
647 /* 8: */ MD(18), MD(17))
648 FF(sampler_msg_type,
649 /* 4: */ MD(15), MD(14),
650 /* 4.5: */ MD(15), MD(12),
651 /* 5: */ MD(15), MD(12),
652 /* 6: */ MD(15), MD(12),
653 /* 7: */ MD(16), MD(12),
654 /* 8: */ MD(16), MD(12))
655 FC(sampler_return_format, MD(13), MD(12), devinfo->gen == 4 && !devinfo->is_g4x)
656 F(sampler, MD(11), MD(8))
657 F(binding_table_index, MD( 7), MD(0)) /* also used by other messages */
658 /** @} */
659
660 /**
661 * Data port message function control bits:
662 * @{
663 */
664 FC(dp_category, MD(18), MD(18), devinfo->gen >= 7)
665
666 /* Gen4-5 store fields in different bits for read/write messages. */
667 FF(dp_read_msg_type,
668 /* 4: */ MD(13), MD(12),
669 /* 4.5: */ MD(13), MD(11),
670 /* 5: */ MD(13), MD(11),
671 /* 6: */ MD(16), MD(13),
672 /* 7: */ MD(17), MD(14),
673 /* 8: */ MD(17), MD(14))
674 FF(dp_write_msg_type,
675 /* 4: */ MD(14), MD(12),
676 /* 4.5: */ MD(14), MD(12),
677 /* 5: */ MD(14), MD(12),
678 /* 6: */ MD(16), MD(13),
679 /* 7: */ MD(17), MD(14),
680 /* 8: */ MD(17), MD(14))
681 FF(dp_read_msg_control,
682 /* 4: */ MD(11), MD( 8),
683 /* 4.5: */ MD(10), MD( 8),
684 /* 5: */ MD(10), MD( 8),
685 /* 6: */ MD(12), MD( 8),
686 /* 7: */ MD(13), MD( 8),
687 /* 8: */ MD(13), MD( 8))
688 FF(dp_write_msg_control,
689 /* 4: */ MD(11), MD( 8),
690 /* 4.5: */ MD(11), MD( 8),
691 /* 5: */ MD(11), MD( 8),
692 /* 6: */ MD(12), MD( 8),
693 /* 7: */ MD(13), MD( 8),
694 /* 8: */ MD(13), MD( 8))
695 FC(dp_read_target_cache, MD(15), MD(14), devinfo->gen < 6);
696
697 FF(dp_write_commit,
698 /* 4: */ MD(15), MD(15),
699 /* 4.5: */ MD(15), MD(15),
700 /* 5: */ MD(15), MD(15),
701 /* 6: */ MD(17), MD(17),
702 /* 7+: does not exist */ -1, -1, -1, -1)
703
704 /* Gen6+ use the same bit locations for everything. */
705 FF(dp_msg_type,
706 /* 4-5: use dp_read_msg_type or dp_write_msg_type instead */
707 -1, -1, -1, -1, -1, -1,
708 /* 6: */ MD(16), MD(13),
709 /* 7: */ MD(17), MD(14),
710 /* 8: */ MD(18), MD(14))
711 FF(dp_msg_control,
712 /* 4: */ MD(11), MD( 8),
713 /* 4.5-5: use dp_read_msg_control or dp_write_msg_control */ -1, -1, -1, -1,
714 /* 6: */ MD(12), MD( 8),
715 /* 7: */ MD(13), MD( 8),
716 /* 8: */ MD(13), MD( 8))
717 /** @} */
718
719 /**
720 * Scratch message bits (Gen7+):
721 * @{
722 */
723 FC(scratch_read_write, MD(17), MD(17), devinfo->gen >= 7) /* 0 = read, 1 = write */
724 FC(scratch_type, MD(16), MD(16), devinfo->gen >= 7) /* 0 = OWord, 1 = DWord */
725 FC(scratch_invalidate_after_read, MD(15), MD(15), devinfo->gen >= 7)
726 FC(scratch_block_size, MD(13), MD(12), devinfo->gen >= 7)
727 FC(scratch_addr_offset, MD(11), MD( 0), devinfo->gen >= 7)
728 /** @} */
729
730 /**
731 * Render Target message function control bits:
732 * @{
733 */
734 FF(rt_last,
735 /* 4: */ MD(11), MD(11),
736 /* 4.5: */ MD(11), MD(11),
737 /* 5: */ MD(11), MD(11),
738 /* 6: */ MD(12), MD(12),
739 /* 7: */ MD(12), MD(12),
740 /* 8: */ MD(12), MD(12))
741 FC(rt_slot_group, MD(11), MD(11), devinfo->gen >= 6)
742 F(rt_message_type, MD(10), MD( 8))
743 /** @} */
744
745 /**
746 * Thread Spawn message function control bits:
747 * @{
748 */
749 F(ts_resource_select, MD( 4), MD( 4))
750 F(ts_request_type, MD( 1), MD( 1))
751 F(ts_opcode, MD( 0), MD( 0))
752 /** @} */
753
754 /**
755 * Pixel Interpolator message function control bits:
756 * @{
757 */
758 F(pi_simd_mode, MD(16), MD(16))
759 F(pi_nopersp, MD(14), MD(14))
760 F(pi_message_type, MD(13), MD(12))
761 F(pi_slot_group, MD(11), MD(11))
762 F(pi_message_data, MD(7), MD(0))
763 /** @} */
764
765 /**
766 * Immediates:
767 * @{
768 */
769 static inline int
770 brw_inst_imm_d(const struct gen_device_info *devinfo, const brw_inst *insn)
771 {
772 (void) devinfo;
773 return brw_inst_bits(insn, 127, 96);
774 }
775
776 static inline unsigned
777 brw_inst_imm_ud(const struct gen_device_info *devinfo, const brw_inst *insn)
778 {
779 (void) devinfo;
780 return brw_inst_bits(insn, 127, 96);
781 }
782
783 static inline uint64_t
784 brw_inst_imm_uq(MAYBE_UNUSED const struct gen_device_info *devinfo,
785 const brw_inst *insn)
786 {
787 assert(devinfo->gen >= 8);
788 return brw_inst_bits(insn, 127, 64);
789 }
790
791 static inline float
792 brw_inst_imm_f(const struct gen_device_info *devinfo, const brw_inst *insn)
793 {
794 union {
795 float f;
796 uint32_t u;
797 } ft;
798 (void) devinfo;
799 ft.u = brw_inst_bits(insn, 127, 96);
800 return ft.f;
801 }
802
803 static inline double
804 brw_inst_imm_df(const struct gen_device_info *devinfo, const brw_inst *insn)
805 {
806 union {
807 double d;
808 uint64_t u;
809 } dt;
810 (void) devinfo;
811 dt.u = brw_inst_bits(insn, 127, 64);
812 return dt.d;
813 }
814
815 static inline void
816 brw_inst_set_imm_d(const struct gen_device_info *devinfo,
817 brw_inst *insn, int value)
818 {
819 (void) devinfo;
820 return brw_inst_set_bits(insn, 127, 96, value);
821 }
822
823 static inline void
824 brw_inst_set_imm_ud(const struct gen_device_info *devinfo,
825 brw_inst *insn, unsigned value)
826 {
827 (void) devinfo;
828 return brw_inst_set_bits(insn, 127, 96, value);
829 }
830
831 static inline void
832 brw_inst_set_imm_f(const struct gen_device_info *devinfo,
833 brw_inst *insn, float value)
834 {
835 union {
836 float f;
837 uint32_t u;
838 } ft;
839 (void) devinfo;
840 ft.f = value;
841 brw_inst_set_bits(insn, 127, 96, ft.u);
842 }
843
844 static inline void
845 brw_inst_set_imm_df(const struct gen_device_info *devinfo,
846 brw_inst *insn, double value)
847 {
848 union {
849 double d;
850 uint64_t u;
851 } dt;
852 (void) devinfo;
853 dt.d = value;
854 brw_inst_set_bits(insn, 127, 64, dt.u);
855 }
856
857 static inline void
858 brw_inst_set_imm_uq(const struct gen_device_info *devinfo,
859 brw_inst *insn, uint64_t value)
860 {
861 (void) devinfo;
862 brw_inst_set_bits(insn, 127, 64, value);
863 }
864
865 /** @} */
866
867 #define REG_TYPE(reg) \
868 static inline void \
869 brw_inst_set_##reg##_file_type(const struct gen_device_info *devinfo, \
870 brw_inst *inst, enum brw_reg_file file, \
871 enum brw_reg_type type) \
872 { \
873 assert(file <= BRW_IMMEDIATE_VALUE); \
874 unsigned hw_type = brw_reg_type_to_hw_type(devinfo, file, type); \
875 brw_inst_set_##reg##_reg_file(devinfo, inst, file); \
876 brw_inst_set_##reg##_reg_hw_type(devinfo, inst, hw_type); \
877 } \
878 \
879 static inline enum brw_reg_type \
880 brw_inst_##reg##_type(const struct gen_device_info *devinfo, \
881 const brw_inst *inst) \
882 { \
883 unsigned file = __builtin_strcmp("dst", #reg) == 0 ? \
884 (unsigned) BRW_GENERAL_REGISTER_FILE : \
885 brw_inst_##reg##_reg_file(devinfo, inst); \
886 unsigned hw_type = brw_inst_##reg##_reg_hw_type(devinfo, inst); \
887 return brw_hw_type_to_reg_type(devinfo, (enum brw_reg_file)file, hw_type); \
888 }
889
890 REG_TYPE(dst)
891 REG_TYPE(src0)
892 REG_TYPE(src1)
893 #undef REG_TYPE
894
895
896 /* The AddrImm fields are split into two discontiguous sections on Gen8+ */
897 #define BRW_IA1_ADDR_IMM(reg, g4_high, g4_low, g8_nine, g8_high, g8_low) \
898 static inline void \
899 brw_inst_set_##reg##_ia1_addr_imm(const struct gen_device_info *devinfo, \
900 brw_inst *inst, \
901 unsigned value) \
902 { \
903 assert((value & ~0x3ff) == 0); \
904 if (devinfo->gen >= 8) { \
905 brw_inst_set_bits(inst, g8_high, g8_low, value & 0x1ff); \
906 brw_inst_set_bits(inst, g8_nine, g8_nine, value >> 9); \
907 } else { \
908 brw_inst_set_bits(inst, g4_high, g4_low, value); \
909 } \
910 } \
911 static inline unsigned \
912 brw_inst_##reg##_ia1_addr_imm(const struct gen_device_info *devinfo, \
913 const brw_inst *inst) \
914 { \
915 if (devinfo->gen >= 8) { \
916 return brw_inst_bits(inst, g8_high, g8_low) | \
917 (brw_inst_bits(inst, g8_nine, g8_nine) << 9); \
918 } else { \
919 return brw_inst_bits(inst, g4_high, g4_low); \
920 } \
921 }
922
923 /* AddrImm[9:0] for Align1 Indirect Addressing */
924 /* -Gen 4- ----Gen8---- */
925 BRW_IA1_ADDR_IMM(src1, 105, 96, 121, 104, 96)
926 BRW_IA1_ADDR_IMM(src0, 73, 64, 95, 72, 64)
927 BRW_IA1_ADDR_IMM(dst, 57, 48, 47, 56, 48)
928
929 #define BRW_IA16_ADDR_IMM(reg, g4_high, g4_low, g8_nine, g8_high, g8_low) \
930 static inline void \
931 brw_inst_set_##reg##_ia16_addr_imm(const struct gen_device_info *devinfo, \
932 brw_inst *inst, unsigned value) \
933 { \
934 assert((value & ~0x3ff) == 0); \
935 if (devinfo->gen >= 8) { \
936 brw_inst_set_bits(inst, g8_high, g8_low, value & 0x1ff); \
937 brw_inst_set_bits(inst, g8_nine, g8_nine, value >> 9); \
938 } else { \
939 brw_inst_set_bits(inst, g4_high, g4_low, value >> 9); \
940 } \
941 } \
942 static inline unsigned \
943 brw_inst_##reg##_ia16_addr_imm(const struct gen_device_info *devinfo, \
944 const brw_inst *inst) \
945 { \
946 if (devinfo->gen >= 8) { \
947 return brw_inst_bits(inst, g8_high, g8_low) | \
948 (brw_inst_bits(inst, g8_nine, g8_nine) << 9); \
949 } else { \
950 return brw_inst_bits(inst, g4_high, g4_low); \
951 } \
952 }
953
954 /* AddrImm[9:0] for Align16 Indirect Addressing:
955 * Compared to Align1, these are missing the low 4 bits.
956 * -Gen 4- ----Gen8----
957 */
958 BRW_IA16_ADDR_IMM(src1, 105, 96, 121, 104, 100)
959 BRW_IA16_ADDR_IMM(src0, 73, 64, 95, 72, 68)
960 BRW_IA16_ADDR_IMM(dst, 57, 52, 47, 56, 52)
961
962 /**
963 * Fetch a set of contiguous bits from the instruction.
964 *
965 * Bits indices range from 0..127; fields may not cross 64-bit boundaries.
966 */
967 static inline uint64_t
968 brw_inst_bits(const brw_inst *inst, unsigned high, unsigned low)
969 {
970 /* We assume the field doesn't cross 64-bit boundaries. */
971 const unsigned word = high / 64;
972 assert(word == low / 64);
973
974 high %= 64;
975 low %= 64;
976
977 const uint64_t mask = (~0ull >> (64 - (high - low + 1)));
978
979 return (inst->data[word] >> low) & mask;
980 }
981
982 /**
983 * Set bits in the instruction, with proper shifting and masking.
984 *
985 * Bits indices range from 0..127; fields may not cross 64-bit boundaries.
986 */
987 static inline void
988 brw_inst_set_bits(brw_inst *inst, unsigned high, unsigned low, uint64_t value)
989 {
990 const unsigned word = high / 64;
991 assert(word == low / 64);
992
993 high %= 64;
994 low %= 64;
995
996 const uint64_t mask = (~0ull >> (64 - (high - low + 1))) << low;
997
998 /* Make sure the supplied value actually fits in the given bitfield. */
999 assert((value & (mask >> low)) == value);
1000
1001 inst->data[word] = (inst->data[word] & ~mask) | (value << low);
1002 }
1003
1004 #undef BRW_IA16_ADDR_IMM
1005 #undef BRW_IA1_ADDR_IMM
1006 #undef MD
1007 #undef F8
1008 #undef FF
1009 #undef BOUNDS
1010 #undef F
1011 #undef FC
1012
1013 typedef struct {
1014 uint64_t data;
1015 } brw_compact_inst;
1016
1017 /**
1018 * Fetch a set of contiguous bits from the compacted instruction.
1019 *
1020 * Bits indices range from 0..63.
1021 */
1022 static inline unsigned
1023 brw_compact_inst_bits(const brw_compact_inst *inst, unsigned high, unsigned low)
1024 {
1025 const uint64_t mask = (1ull << (high - low + 1)) - 1;
1026
1027 return (inst->data >> low) & mask;
1028 }
1029
1030 /**
1031 * Set bits in the compacted instruction.
1032 *
1033 * Bits indices range from 0..63.
1034 */
1035 static inline void
1036 brw_compact_inst_set_bits(brw_compact_inst *inst, unsigned high, unsigned low,
1037 uint64_t value)
1038 {
1039 const uint64_t mask = ((1ull << (high - low + 1)) - 1) << low;
1040
1041 /* Make sure the supplied value actually fits in the given bitfield. */
1042 assert((value & (mask >> low)) == value);
1043
1044 inst->data = (inst->data & ~mask) | (value << low);
1045 }
1046
1047 #define FC(name, high, low, assertions) \
1048 static inline void \
1049 brw_compact_inst_set_##name(const struct gen_device_info *devinfo, \
1050 brw_compact_inst *inst, unsigned v) \
1051 { \
1052 assert(assertions); \
1053 (void) devinfo; \
1054 brw_compact_inst_set_bits(inst, high, low, v); \
1055 } \
1056 static inline unsigned \
1057 brw_compact_inst_##name(const struct gen_device_info *devinfo, \
1058 const brw_compact_inst *inst) \
1059 { \
1060 assert(assertions); \
1061 (void) devinfo; \
1062 return brw_compact_inst_bits(inst, high, low); \
1063 }
1064
1065 /* A simple macro for fields which stay in the same place on all generations. */
1066 #define F(name, high, low) FC(name, high, low, true)
1067
1068 F(src1_reg_nr, 63, 56)
1069 F(src0_reg_nr, 55, 48)
1070 F(dst_reg_nr, 47, 40)
1071 F(src1_index, 39, 35)
1072 F(src0_index, 34, 30)
1073 F(cmpt_control, 29, 29) /* Same location as brw_inst */
1074 FC(flag_subreg_nr, 28, 28, devinfo->gen <= 6)
1075 F(cond_modifier, 27, 24) /* Same location as brw_inst */
1076 FC(acc_wr_control, 23, 23, devinfo->gen >= 6)
1077 FC(mask_control_ex, 23, 23, devinfo->is_g4x || devinfo->gen == 5)
1078 F(subreg_index, 22, 18)
1079 F(datatype_index, 17, 13)
1080 F(control_index, 12, 8)
1081 F(debug_control, 7, 7)
1082 F(opcode, 6, 0) /* Same location as brw_inst */
1083
1084 /**
1085 * (Gen8+) Compacted three-source instructions:
1086 * @{
1087 */
1088 FC(3src_src2_reg_nr, 63, 57, devinfo->gen >= 8)
1089 FC(3src_src1_reg_nr, 56, 50, devinfo->gen >= 8)
1090 FC(3src_src0_reg_nr, 49, 43, devinfo->gen >= 8)
1091 FC(3src_src2_subreg_nr, 42, 40, devinfo->gen >= 8)
1092 FC(3src_src1_subreg_nr, 39, 37, devinfo->gen >= 8)
1093 FC(3src_src0_subreg_nr, 36, 34, devinfo->gen >= 8)
1094 FC(3src_src2_rep_ctrl, 33, 33, devinfo->gen >= 8)
1095 FC(3src_src1_rep_ctrl, 32, 32, devinfo->gen >= 8)
1096 FC(3src_saturate, 31, 31, devinfo->gen >= 8)
1097 FC(3src_debug_control, 30, 30, devinfo->gen >= 8)
1098 FC(3src_cmpt_control, 29, 29, devinfo->gen >= 8)
1099 FC(3src_src0_rep_ctrl, 28, 28, devinfo->gen >= 8)
1100 /* Reserved */
1101 FC(3src_dst_reg_nr, 18, 12, devinfo->gen >= 8)
1102 FC(3src_source_index, 11, 10, devinfo->gen >= 8)
1103 FC(3src_control_index, 9, 8, devinfo->gen >= 8)
1104 /* Bit 7 is Reserved (for future Opcode expansion) */
1105 FC(3src_opcode, 6, 0, devinfo->gen >= 8)
1106 /** @} */
1107
1108 #undef F
1109
1110 #ifdef __cplusplus
1111 }
1112 #endif
1113
1114 #endif