2 * Copyright © 2014 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 #include "brw_shader.h"
26 #include "dev/gen_debug.h"
27 #include "compiler/glsl_types.h"
28 #include "compiler/nir/nir_builder.h"
29 #include "util/u_math.h"
32 remap_tess_levels(nir_builder
*b
, nir_intrinsic_instr
*intr
,
33 GLenum primitive_mode
)
35 const int location
= nir_intrinsic_base(intr
);
36 const unsigned component
= nir_intrinsic_component(intr
);
39 if (location
== VARYING_SLOT_TESS_LEVEL_INNER
) {
40 switch (primitive_mode
) {
42 /* gl_TessLevelInner[0..1] lives at DWords 3-2 (reversed). */
43 nir_intrinsic_set_base(intr
, 0);
44 nir_intrinsic_set_component(intr
, 3 - component
);
45 out_of_bounds
= false;
48 /* gl_TessLevelInner[0] lives at DWord 4. */
49 nir_intrinsic_set_base(intr
, 1);
50 out_of_bounds
= component
> 0;
56 unreachable("Bogus tessellation domain");
58 } else if (location
== VARYING_SLOT_TESS_LEVEL_OUTER
) {
59 if (primitive_mode
== GL_ISOLINES
) {
60 /* gl_TessLevelOuter[0..1] lives at DWords 6-7 (in order). */
61 nir_intrinsic_set_base(intr
, 1);
62 nir_intrinsic_set_component(intr
, 2 + nir_intrinsic_component(intr
));
63 out_of_bounds
= component
> 1;
65 /* Triangles use DWords 7-5 (reversed); Quads use 7-4 (reversed) */
66 nir_intrinsic_set_base(intr
, 1);
67 nir_intrinsic_set_component(intr
, 3 - nir_intrinsic_component(intr
));
68 out_of_bounds
= component
== 3 && primitive_mode
== GL_TRIANGLES
;
75 if (nir_intrinsic_infos
[intr
->intrinsic
].has_dest
) {
76 b
->cursor
= nir_before_instr(&intr
->instr
);
77 nir_ssa_def
*undef
= nir_ssa_undef(b
, 1, 32);
78 nir_ssa_def_rewrite_uses(&intr
->dest
.ssa
, nir_src_for_ssa(undef
));
80 nir_instr_remove(&intr
->instr
);
87 is_input(nir_intrinsic_instr
*intrin
)
89 return intrin
->intrinsic
== nir_intrinsic_load_input
||
90 intrin
->intrinsic
== nir_intrinsic_load_per_vertex_input
||
91 intrin
->intrinsic
== nir_intrinsic_load_interpolated_input
;
95 is_output(nir_intrinsic_instr
*intrin
)
97 return intrin
->intrinsic
== nir_intrinsic_load_output
||
98 intrin
->intrinsic
== nir_intrinsic_load_per_vertex_output
||
99 intrin
->intrinsic
== nir_intrinsic_store_output
||
100 intrin
->intrinsic
== nir_intrinsic_store_per_vertex_output
;
105 remap_patch_urb_offsets(nir_block
*block
, nir_builder
*b
,
106 const struct brw_vue_map
*vue_map
,
107 GLenum tes_primitive_mode
)
109 const bool is_passthrough_tcs
= b
->shader
->info
.name
&&
110 strcmp(b
->shader
->info
.name
, "passthrough") == 0;
112 nir_foreach_instr_safe(instr
, block
) {
113 if (instr
->type
!= nir_instr_type_intrinsic
)
116 nir_intrinsic_instr
*intrin
= nir_instr_as_intrinsic(instr
);
118 gl_shader_stage stage
= b
->shader
->info
.stage
;
120 if ((stage
== MESA_SHADER_TESS_CTRL
&& is_output(intrin
)) ||
121 (stage
== MESA_SHADER_TESS_EVAL
&& is_input(intrin
))) {
123 if (!is_passthrough_tcs
&&
124 remap_tess_levels(b
, intrin
, tes_primitive_mode
))
127 int vue_slot
= vue_map
->varying_to_slot
[intrin
->const_index
[0]];
128 assert(vue_slot
!= -1);
129 intrin
->const_index
[0] = vue_slot
;
131 nir_src
*vertex
= nir_get_io_vertex_index_src(intrin
);
133 if (nir_src_is_const(*vertex
)) {
134 intrin
->const_index
[0] += nir_src_as_uint(*vertex
) *
135 vue_map
->num_per_vertex_slots
;
137 b
->cursor
= nir_before_instr(&intrin
->instr
);
139 /* Multiply by the number of per-vertex slots. */
140 nir_ssa_def
*vertex_offset
=
142 nir_ssa_for_src(b
, *vertex
, 1),
144 vue_map
->num_per_vertex_slots
));
146 /* Add it to the existing offset */
147 nir_src
*offset
= nir_get_io_offset_src(intrin
);
148 nir_ssa_def
*total_offset
=
149 nir_iadd(b
, vertex_offset
,
150 nir_ssa_for_src(b
, *offset
, 1));
152 nir_instr_rewrite_src(&intrin
->instr
, offset
,
153 nir_src_for_ssa(total_offset
));
162 brw_nir_lower_vs_inputs(nir_shader
*nir
,
163 const uint8_t *vs_attrib_wa_flags
)
165 /* Start with the location of the variable's base. */
166 foreach_list_typed(nir_variable
, var
, node
, &nir
->inputs
) {
167 var
->data
.driver_location
= var
->data
.location
;
170 /* Now use nir_lower_io to walk dereference chains. Attribute arrays are
171 * loaded as one vec4 or dvec4 per element (or matrix column), depending on
172 * whether it is a double-precision type or not.
174 nir_lower_io(nir
, nir_var_shader_in
, type_size_vec4
, 0);
176 /* This pass needs actual constants */
177 nir_opt_constant_folding(nir
);
179 nir_io_add_const_offset_to_base(nir
, nir_var_shader_in
);
181 brw_nir_apply_attribute_workarounds(nir
, vs_attrib_wa_flags
);
183 /* The last step is to remap VERT_ATTRIB_* to actual registers */
185 /* Whether or not we have any system generated values. gl_DrawID is not
186 * included here as it lives in its own vec4.
188 const bool has_sgvs
=
189 nir
->info
.system_values_read
&
190 (BITFIELD64_BIT(SYSTEM_VALUE_FIRST_VERTEX
) |
191 BITFIELD64_BIT(SYSTEM_VALUE_BASE_INSTANCE
) |
192 BITFIELD64_BIT(SYSTEM_VALUE_VERTEX_ID_ZERO_BASE
) |
193 BITFIELD64_BIT(SYSTEM_VALUE_INSTANCE_ID
));
195 const unsigned num_inputs
= util_bitcount64(nir
->info
.inputs_read
);
197 nir_foreach_function(function
, nir
) {
202 nir_builder_init(&b
, function
->impl
);
204 nir_foreach_block(block
, function
->impl
) {
205 nir_foreach_instr_safe(instr
, block
) {
206 if (instr
->type
!= nir_instr_type_intrinsic
)
209 nir_intrinsic_instr
*intrin
= nir_instr_as_intrinsic(instr
);
211 switch (intrin
->intrinsic
) {
212 case nir_intrinsic_load_first_vertex
:
213 case nir_intrinsic_load_base_instance
:
214 case nir_intrinsic_load_vertex_id_zero_base
:
215 case nir_intrinsic_load_instance_id
:
216 case nir_intrinsic_load_is_indexed_draw
:
217 case nir_intrinsic_load_draw_id
: {
218 b
.cursor
= nir_after_instr(&intrin
->instr
);
220 /* gl_VertexID and friends are stored by the VF as the last
221 * vertex element. We convert them to load_input intrinsics at
222 * the right location.
224 nir_intrinsic_instr
*load
=
225 nir_intrinsic_instr_create(nir
, nir_intrinsic_load_input
);
226 load
->src
[0] = nir_src_for_ssa(nir_imm_int(&b
, 0));
228 nir_intrinsic_set_base(load
, num_inputs
);
229 switch (intrin
->intrinsic
) {
230 case nir_intrinsic_load_first_vertex
:
231 nir_intrinsic_set_component(load
, 0);
233 case nir_intrinsic_load_base_instance
:
234 nir_intrinsic_set_component(load
, 1);
236 case nir_intrinsic_load_vertex_id_zero_base
:
237 nir_intrinsic_set_component(load
, 2);
239 case nir_intrinsic_load_instance_id
:
240 nir_intrinsic_set_component(load
, 3);
242 case nir_intrinsic_load_draw_id
:
243 case nir_intrinsic_load_is_indexed_draw
:
244 /* gl_DrawID and IsIndexedDraw are stored right after
245 * gl_VertexID and friends if any of them exist.
247 nir_intrinsic_set_base(load
, num_inputs
+ has_sgvs
);
248 if (intrin
->intrinsic
== nir_intrinsic_load_draw_id
)
249 nir_intrinsic_set_component(load
, 0);
251 nir_intrinsic_set_component(load
, 1);
254 unreachable("Invalid system value intrinsic");
257 load
->num_components
= 1;
258 nir_ssa_dest_init(&load
->instr
, &load
->dest
, 1, 32, NULL
);
259 nir_builder_instr_insert(&b
, &load
->instr
);
261 nir_ssa_def_rewrite_uses(&intrin
->dest
.ssa
,
262 nir_src_for_ssa(&load
->dest
.ssa
));
263 nir_instr_remove(&intrin
->instr
);
267 case nir_intrinsic_load_input
: {
268 /* Attributes come in a contiguous block, ordered by their
269 * gl_vert_attrib value. That means we can compute the slot
270 * number for an attribute by masking out the enabled attributes
271 * before it and counting the bits.
273 int attr
= nir_intrinsic_base(intrin
);
274 int slot
= util_bitcount64(nir
->info
.inputs_read
&
275 BITFIELD64_MASK(attr
));
276 nir_intrinsic_set_base(intrin
, slot
);
281 break; /* Nothing to do */
289 brw_nir_lower_vue_inputs(nir_shader
*nir
,
290 const struct brw_vue_map
*vue_map
)
292 foreach_list_typed(nir_variable
, var
, node
, &nir
->inputs
) {
293 var
->data
.driver_location
= var
->data
.location
;
296 /* Inputs are stored in vec4 slots, so use type_size_vec4(). */
297 nir_lower_io(nir
, nir_var_shader_in
, type_size_vec4
, 0);
299 /* This pass needs actual constants */
300 nir_opt_constant_folding(nir
);
302 nir_io_add_const_offset_to_base(nir
, nir_var_shader_in
);
304 nir_foreach_function(function
, nir
) {
308 nir_foreach_block(block
, function
->impl
) {
309 nir_foreach_instr(instr
, block
) {
310 if (instr
->type
!= nir_instr_type_intrinsic
)
313 nir_intrinsic_instr
*intrin
= nir_instr_as_intrinsic(instr
);
315 if (intrin
->intrinsic
== nir_intrinsic_load_input
||
316 intrin
->intrinsic
== nir_intrinsic_load_per_vertex_input
) {
317 /* Offset 0 is the VUE header, which contains
318 * VARYING_SLOT_LAYER [.y], VARYING_SLOT_VIEWPORT [.z], and
319 * VARYING_SLOT_PSIZ [.w].
321 int varying
= nir_intrinsic_base(intrin
);
324 case VARYING_SLOT_PSIZ
:
325 nir_intrinsic_set_base(intrin
, 0);
326 nir_intrinsic_set_component(intrin
, 3);
330 vue_slot
= vue_map
->varying_to_slot
[varying
];
331 assert(vue_slot
!= -1);
332 nir_intrinsic_set_base(intrin
, vue_slot
);
342 brw_nir_lower_tes_inputs(nir_shader
*nir
, const struct brw_vue_map
*vue_map
)
344 foreach_list_typed(nir_variable
, var
, node
, &nir
->inputs
) {
345 var
->data
.driver_location
= var
->data
.location
;
348 nir_lower_io(nir
, nir_var_shader_in
, type_size_vec4
, 0);
350 /* This pass needs actual constants */
351 nir_opt_constant_folding(nir
);
353 nir_io_add_const_offset_to_base(nir
, nir_var_shader_in
);
355 nir_foreach_function(function
, nir
) {
356 if (function
->impl
) {
358 nir_builder_init(&b
, function
->impl
);
359 nir_foreach_block(block
, function
->impl
) {
360 remap_patch_urb_offsets(block
, &b
, vue_map
,
361 nir
->info
.tess
.primitive_mode
);
368 brw_nir_lower_fs_inputs(nir_shader
*nir
,
369 const struct gen_device_info
*devinfo
,
370 const struct brw_wm_prog_key
*key
)
372 foreach_list_typed(nir_variable
, var
, node
, &nir
->inputs
) {
373 var
->data
.driver_location
= var
->data
.location
;
375 /* Apply default interpolation mode.
377 * Everything defaults to smooth except for the legacy GL color
378 * built-in variables, which might be flat depending on API state.
380 if (var
->data
.interpolation
== INTERP_MODE_NONE
) {
381 const bool flat
= key
->flat_shade
&&
382 (var
->data
.location
== VARYING_SLOT_COL0
||
383 var
->data
.location
== VARYING_SLOT_COL1
);
385 var
->data
.interpolation
= flat
? INTERP_MODE_FLAT
386 : INTERP_MODE_SMOOTH
;
389 /* On Ironlake and below, there is only one interpolation mode.
390 * Centroid interpolation doesn't mean anything on this hardware --
391 * there is no multisampling.
393 if (devinfo
->gen
< 6) {
394 var
->data
.centroid
= false;
395 var
->data
.sample
= false;
399 nir_lower_io_options lower_io_options
= 0;
400 if (key
->persample_interp
)
401 lower_io_options
|= nir_lower_io_force_sample_interpolation
;
403 nir_lower_io(nir
, nir_var_shader_in
, type_size_vec4
, lower_io_options
);
404 if (devinfo
->gen
>= 11)
405 nir_lower_interpolation(nir
, ~0);
407 /* This pass needs actual constants */
408 nir_opt_constant_folding(nir
);
410 nir_io_add_const_offset_to_base(nir
, nir_var_shader_in
);
414 brw_nir_lower_vue_outputs(nir_shader
*nir
)
416 nir_foreach_variable(var
, &nir
->outputs
) {
417 var
->data
.driver_location
= var
->data
.location
;
420 nir_lower_io(nir
, nir_var_shader_out
, type_size_vec4
, 0);
424 brw_nir_lower_tcs_outputs(nir_shader
*nir
, const struct brw_vue_map
*vue_map
,
425 GLenum tes_primitive_mode
)
427 nir_foreach_variable(var
, &nir
->outputs
) {
428 var
->data
.driver_location
= var
->data
.location
;
431 nir_lower_io(nir
, nir_var_shader_out
, type_size_vec4
, 0);
433 /* This pass needs actual constants */
434 nir_opt_constant_folding(nir
);
436 nir_io_add_const_offset_to_base(nir
, nir_var_shader_out
);
438 nir_foreach_function(function
, nir
) {
439 if (function
->impl
) {
441 nir_builder_init(&b
, function
->impl
);
442 nir_foreach_block(block
, function
->impl
) {
443 remap_patch_urb_offsets(block
, &b
, vue_map
, tes_primitive_mode
);
450 brw_nir_lower_fs_outputs(nir_shader
*nir
)
452 nir_foreach_variable(var
, &nir
->outputs
) {
453 var
->data
.driver_location
=
454 SET_FIELD(var
->data
.index
, BRW_NIR_FRAG_OUTPUT_INDEX
) |
455 SET_FIELD(var
->data
.location
, BRW_NIR_FRAG_OUTPUT_LOCATION
);
458 nir_lower_io(nir
, nir_var_shader_out
, type_size_dvec4
, 0);
461 #define OPT(pass, ...) ({ \
462 bool this_progress = false; \
463 NIR_PASS(this_progress, nir, pass, ##__VA_ARGS__); \
469 static nir_variable_mode
470 brw_nir_no_indirect_mask(const struct brw_compiler
*compiler
,
471 gl_shader_stage stage
)
473 nir_variable_mode indirect_mask
= 0;
475 if (compiler
->glsl_compiler_options
[stage
].EmitNoIndirectInput
)
476 indirect_mask
|= nir_var_shader_in
;
477 if (compiler
->glsl_compiler_options
[stage
].EmitNoIndirectOutput
)
478 indirect_mask
|= nir_var_shader_out
;
479 if (compiler
->glsl_compiler_options
[stage
].EmitNoIndirectTemp
)
480 indirect_mask
|= nir_var_function_temp
;
482 return indirect_mask
;
486 brw_nir_optimize(nir_shader
*nir
, const struct brw_compiler
*compiler
,
487 bool is_scalar
, bool allow_copies
)
489 nir_variable_mode indirect_mask
=
490 brw_nir_no_indirect_mask(compiler
, nir
->info
.stage
);
493 unsigned lower_flrp
=
494 (nir
->options
->lower_flrp16
? 16 : 0) |
495 (nir
->options
->lower_flrp32
? 32 : 0) |
496 (nir
->options
->lower_flrp64
? 64 : 0);
500 OPT(nir_split_array_vars
, nir_var_function_temp
);
501 OPT(nir_shrink_vec_array_vars
, nir_var_function_temp
);
503 OPT(nir_lower_vars_to_ssa
);
505 /* Only run this pass in the first call to brw_nir_optimize. Later
506 * calls assume that we've lowered away any copy_deref instructions
507 * and we don't want to introduce any more.
509 OPT(nir_opt_find_array_copies
);
511 OPT(nir_opt_copy_prop_vars
);
512 OPT(nir_opt_dead_write_vars
);
513 OPT(nir_opt_combine_stores
, nir_var_all
);
516 OPT(nir_lower_alu_to_scalar
, NULL
);
522 OPT(nir_lower_phis_to_scalar
);
528 OPT(nir_opt_combine_stores
, nir_var_all
);
530 /* Passing 0 to the peephole select pass causes it to convert
531 * if-statements that contain only move instructions in the branches
532 * regardless of the count.
534 * Passing 1 to the peephole select pass causes it to convert
535 * if-statements that contain at most a single ALU instruction (total)
536 * in both branches. Before Gen6, some math instructions were
537 * prohibitively expensive and the results of compare operations need an
538 * extra resolve step. For these reasons, this pass is more harmful
539 * than good on those platforms.
541 * For indirect loads of uniforms (push constants), we assume that array
542 * indices will nearly always be in bounds and the cost of the load is
543 * low. Therefore there shouldn't be a performance benefit to avoid it.
544 * However, in vec4 tessellation shaders, these loads operate by
545 * actually pulling from memory.
547 const bool is_vec4_tessellation
= !is_scalar
&&
548 (nir
->info
.stage
== MESA_SHADER_TESS_CTRL
||
549 nir
->info
.stage
== MESA_SHADER_TESS_EVAL
);
550 OPT(nir_opt_peephole_select
, 0, !is_vec4_tessellation
, false);
551 OPT(nir_opt_peephole_select
, 1, !is_vec4_tessellation
,
552 compiler
->devinfo
->gen
>= 6);
554 OPT(nir_opt_intrinsics
);
555 OPT(nir_opt_idiv_const
, 32);
556 OPT(nir_opt_algebraic
);
557 OPT(nir_opt_constant_folding
);
559 if (lower_flrp
!= 0) {
560 /* To match the old behavior, set always_precise only for scalar
563 if (OPT(nir_lower_flrp
,
565 false /* always_precise */,
566 compiler
->devinfo
->gen
>= 6)) {
567 OPT(nir_opt_constant_folding
);
570 /* Nothing should rematerialize any flrps, so we only need to do this
576 OPT(nir_opt_dead_cf
);
577 if (OPT(nir_opt_trivial_continues
)) {
578 /* If nir_opt_trivial_continues makes progress, then we need to clean
579 * things up if we want any hope of nir_opt_if or nir_opt_loop_unroll
585 OPT(nir_opt_if
, false);
586 if (nir
->options
->max_unroll_iterations
!= 0) {
587 OPT(nir_opt_loop_unroll
, indirect_mask
);
589 OPT(nir_opt_remove_phis
);
594 /* Workaround Gfxbench unused local sampler variable which will trigger an
595 * assert in the opt_large_constants pass.
597 OPT(nir_remove_dead_variables
, nir_var_function_temp
);
601 lower_bit_size_callback(const nir_alu_instr
*alu
, UNUSED
void *data
)
603 assert(alu
->dest
.dest
.is_ssa
);
604 if (alu
->dest
.dest
.ssa
.bit_size
>= 32)
607 const struct brw_compiler
*compiler
= (const struct brw_compiler
*) data
;
618 case nir_op_fround_even
:
629 return compiler
->devinfo
->gen
< 9 ? 32 : 0;
635 /* Does some simple lowering and runs the standard suite of optimizations
637 * This is intended to be called more-or-less directly after you get the
638 * shader out of GLSL or some other source. While it is geared towards i965,
639 * it is not at all generator-specific except for the is_scalar flag. Even
640 * there, it is safe to call with is_scalar = false for a shader that is
641 * intended for the FS backend as long as nir_optimize is called again with
642 * is_scalar = true to scalarize everything prior to code gen.
645 brw_preprocess_nir(const struct brw_compiler
*compiler
, nir_shader
*nir
,
646 const nir_shader
*softfp64
)
648 const struct gen_device_info
*devinfo
= compiler
->devinfo
;
649 UNUSED
bool progress
; /* Written by OPT */
651 const bool is_scalar
= compiler
->scalar_stage
[nir
->info
.stage
];
654 OPT(nir_lower_alu_to_scalar
, NULL
);
657 if (nir
->info
.stage
== MESA_SHADER_GEOMETRY
)
658 OPT(nir_lower_gs_intrinsics
);
660 /* See also brw_nir_trig_workarounds.py */
661 if (compiler
->precise_trig
&&
662 !(devinfo
->gen
>= 10 || devinfo
->is_kabylake
))
663 OPT(brw_nir_apply_trig_workarounds
);
665 static const nir_lower_tex_options tex_options
= {
667 .lower_txf_offset
= true,
668 .lower_rect_offset
= true,
669 .lower_tex_without_implicit_lod
= true,
670 .lower_txd_cube_map
= true,
671 .lower_txb_shadow_clamp
= true,
672 .lower_txd_shadow_clamp
= true,
673 .lower_txd_offset_clamp
= true,
674 .lower_tg4_offsets
= true,
677 OPT(nir_lower_tex
, &tex_options
);
678 OPT(nir_normalize_cubemap_coords
);
680 OPT(nir_lower_global_vars_to_local
);
682 OPT(nir_split_var_copies
);
683 OPT(nir_split_struct_vars
, nir_var_function_temp
);
685 brw_nir_optimize(nir
, compiler
, is_scalar
, true);
687 bool lowered_64bit_ops
= false;
691 OPT(nir_lower_int64
, nir
->options
->lower_int64_options
);
692 OPT(nir_lower_doubles
, softfp64
, nir
->options
->lower_doubles_options
);
694 /* Necessary to lower add -> sub and div -> mul/rcp */
695 OPT(nir_opt_algebraic
);
697 lowered_64bit_ops
|= progress
;
700 /* This needs to be run after the first optimization pass but before we
701 * lower indirect derefs away
703 if (compiler
->supports_shader_constants
) {
704 OPT(nir_opt_large_constants
, NULL
, 32);
707 OPT(nir_lower_bit_size
, lower_bit_size_callback
, (void *)compiler
);
710 OPT(nir_lower_load_const_to_scalar
);
713 /* Lower a bunch of stuff */
714 OPT(nir_lower_var_copies
);
716 OPT(nir_lower_system_values
);
718 const nir_lower_subgroups_options subgroups_options
= {
719 .subgroup_size
= BRW_SUBGROUP_SIZE
,
720 .ballot_bit_size
= 32,
721 .lower_to_scalar
= true,
722 .lower_subgroup_masks
= true,
723 .lower_vote_trivial
= !is_scalar
,
724 .lower_shuffle
= true,
726 OPT(nir_lower_subgroups
, &subgroups_options
);
728 OPT(nir_lower_clip_cull_distance_arrays
);
730 nir_variable_mode indirect_mask
=
731 brw_nir_no_indirect_mask(compiler
, nir
->info
.stage
);
732 OPT(nir_lower_indirect_derefs
, indirect_mask
);
734 /* Lower array derefs of vectors for SSBO and UBO loads. For both UBOs and
735 * SSBOs, our back-end is capable of loading an entire vec4 at a time and
736 * we would like to take advantage of that whenever possible regardless of
737 * whether or not the app gives us full loads. This should allow the
738 * optimizer to combine UBO and SSBO load operations and save us some send
741 OPT(nir_lower_array_deref_of_vec
,
742 nir_var_mem_ubo
| nir_var_mem_ssbo
,
743 nir_lower_direct_array_deref_of_vec_load
);
745 /* Get rid of split copies */
746 brw_nir_optimize(nir
, compiler
, is_scalar
, false);
750 brw_nir_link_shaders(const struct brw_compiler
*compiler
,
751 nir_shader
*producer
, nir_shader
*consumer
)
753 nir_lower_io_arrays_to_elements(producer
, consumer
);
754 nir_validate_shader(producer
, "after nir_lower_io_arrays_to_elements");
755 nir_validate_shader(consumer
, "after nir_lower_io_arrays_to_elements");
757 const bool p_is_scalar
= compiler
->scalar_stage
[producer
->info
.stage
];
758 const bool c_is_scalar
= compiler
->scalar_stage
[consumer
->info
.stage
];
760 if (p_is_scalar
&& c_is_scalar
) {
761 NIR_PASS_V(producer
, nir_lower_io_to_scalar_early
, nir_var_shader_out
);
762 NIR_PASS_V(consumer
, nir_lower_io_to_scalar_early
, nir_var_shader_in
);
763 brw_nir_optimize(producer
, compiler
, p_is_scalar
, false);
764 brw_nir_optimize(consumer
, compiler
, c_is_scalar
, false);
767 if (nir_link_opt_varyings(producer
, consumer
))
768 brw_nir_optimize(consumer
, compiler
, c_is_scalar
, false);
770 NIR_PASS_V(producer
, nir_remove_dead_variables
, nir_var_shader_out
);
771 NIR_PASS_V(consumer
, nir_remove_dead_variables
, nir_var_shader_in
);
773 if (nir_remove_unused_varyings(producer
, consumer
)) {
774 NIR_PASS_V(producer
, nir_lower_global_vars_to_local
);
775 NIR_PASS_V(consumer
, nir_lower_global_vars_to_local
);
777 /* The backend might not be able to handle indirects on
778 * temporaries so we need to lower indirects on any of the
779 * varyings we have demoted here.
781 NIR_PASS_V(producer
, nir_lower_indirect_derefs
,
782 brw_nir_no_indirect_mask(compiler
, producer
->info
.stage
));
783 NIR_PASS_V(consumer
, nir_lower_indirect_derefs
,
784 brw_nir_no_indirect_mask(compiler
, consumer
->info
.stage
));
786 brw_nir_optimize(producer
, compiler
, p_is_scalar
, false);
787 brw_nir_optimize(consumer
, compiler
, c_is_scalar
, false);
790 NIR_PASS_V(producer
, nir_lower_io_to_vector
, nir_var_shader_out
);
791 NIR_PASS_V(producer
, nir_opt_combine_stores
, nir_var_shader_out
);
792 NIR_PASS_V(consumer
, nir_lower_io_to_vector
, nir_var_shader_in
);
794 if (producer
->info
.stage
!= MESA_SHADER_TESS_CTRL
) {
795 /* Calling lower_io_to_vector creates output variable writes with
796 * write-masks. On non-TCS outputs, the back-end can't handle it and we
797 * need to call nir_lower_io_to_temporaries to get rid of them. This,
798 * in turn, creates temporary variables and extra copy_deref intrinsics
799 * that we need to clean up.
801 NIR_PASS_V(producer
, nir_lower_io_to_temporaries
,
802 nir_shader_get_entrypoint(producer
), true, false);
803 NIR_PASS_V(producer
, nir_lower_global_vars_to_local
);
804 NIR_PASS_V(producer
, nir_split_var_copies
);
805 NIR_PASS_V(producer
, nir_lower_var_copies
);
809 /* Prepare the given shader for codegen
811 * This function is intended to be called right before going into the actual
812 * backend and is highly backend-specific. Also, once this function has been
813 * called on a shader, it will no longer be in SSA form so most optimizations
817 brw_postprocess_nir(nir_shader
*nir
, const struct brw_compiler
*compiler
,
820 const struct gen_device_info
*devinfo
= compiler
->devinfo
;
822 (INTEL_DEBUG
& intel_debug_flag_for_shader_stage(nir
->info
.stage
));
824 UNUSED
bool progress
; /* Written by OPT */
826 OPT(brw_nir_lower_mem_access_bit_sizes
);
827 OPT(nir_lower_int64
, nir
->options
->lower_int64_options
);
831 OPT(nir_opt_algebraic_before_ffma
);
834 brw_nir_optimize(nir
, compiler
, is_scalar
, false);
836 if (devinfo
->gen
>= 6) {
837 /* Try and fuse multiply-adds */
838 OPT(brw_nir_opt_peephole_ffma
);
841 if (OPT(nir_opt_comparison_pre
)) {
846 /* Do the select peepehole again. nir_opt_comparison_pre (combined with
847 * the other optimization passes) will have removed at least one
848 * instruction from one of the branches of the if-statement, so now it
849 * might be under the threshold of conversion to bcsel.
851 * See brw_nir_optimize for the explanation of is_vec4_tessellation.
853 const bool is_vec4_tessellation
= !is_scalar
&&
854 (nir
->info
.stage
== MESA_SHADER_TESS_CTRL
||
855 nir
->info
.stage
== MESA_SHADER_TESS_EVAL
);
856 OPT(nir_opt_peephole_select
, 0, is_vec4_tessellation
, false);
857 OPT(nir_opt_peephole_select
, 1, is_vec4_tessellation
,
858 compiler
->devinfo
->gen
>= 6);
863 if (OPT(nir_opt_algebraic_late
)) {
864 /* At this late stage, anything that makes more constants will wreak
865 * havok on the vec4 backend. The handling of constants in the vec4
866 * backend is not good.
869 OPT(nir_opt_constant_folding
);
878 OPT(brw_nir_lower_conversions
);
881 OPT(nir_lower_alu_to_scalar
, NULL
);
882 OPT(nir_lower_to_source_mods
, nir_lower_all_source_mods
);
885 OPT(nir_opt_move_comparisons
);
887 OPT(nir_lower_bool_to_int32
);
889 OPT(nir_lower_locals_to_regs
);
891 if (unlikely(debug_enabled
)) {
892 /* Re-index SSA defs so we print more sensible numbers. */
893 nir_foreach_function(function
, nir
) {
895 nir_index_ssa_defs(function
->impl
);
898 fprintf(stderr
, "NIR (SSA form) for %s shader:\n",
899 _mesa_shader_stage_to_string(nir
->info
.stage
));
900 nir_print_shader(nir
, stderr
);
903 OPT(nir_convert_from_ssa
, true);
906 OPT(nir_move_vec_src_uses_to_dest
);
907 OPT(nir_lower_vec_to_movs
);
912 if (OPT(nir_opt_rematerialize_compares
))
915 /* This is the last pass we run before we start emitting stuff. It
916 * determines when we need to insert boolean resolves on Gen <= 5. We
917 * run it last because it stashes data in instr->pass_flags and we don't
918 * want that to be squashed by other NIR passes.
920 if (devinfo
->gen
<= 5)
921 brw_nir_analyze_boolean_resolves(nir
);
925 if (unlikely(debug_enabled
)) {
926 fprintf(stderr
, "NIR (final form) for %s shader:\n",
927 _mesa_shader_stage_to_string(nir
->info
.stage
));
928 nir_print_shader(nir
, stderr
);
933 brw_nir_apply_sampler_key(nir_shader
*nir
,
934 const struct brw_compiler
*compiler
,
935 const struct brw_sampler_prog_key_data
*key_tex
,
938 const struct gen_device_info
*devinfo
= compiler
->devinfo
;
939 nir_lower_tex_options tex_options
= {
940 .lower_txd_clamp_bindless_sampler
= true,
941 .lower_txd_clamp_if_sampler_index_not_lt_16
= true,
944 /* Iron Lake and prior require lowering of all rectangle textures */
945 if (devinfo
->gen
< 6)
946 tex_options
.lower_rect
= true;
948 /* Prior to Broadwell, our hardware can't actually do GL_CLAMP */
949 if (devinfo
->gen
< 8) {
950 tex_options
.saturate_s
= key_tex
->gl_clamp_mask
[0];
951 tex_options
.saturate_t
= key_tex
->gl_clamp_mask
[1];
952 tex_options
.saturate_r
= key_tex
->gl_clamp_mask
[2];
955 /* Prior to Haswell, we have to fake texture swizzle */
956 for (unsigned s
= 0; s
< MAX_SAMPLERS
; s
++) {
957 if (key_tex
->swizzles
[s
] == SWIZZLE_NOOP
)
960 tex_options
.swizzle_result
|= (1 << s
);
961 for (unsigned c
= 0; c
< 4; c
++)
962 tex_options
.swizzles
[s
][c
] = GET_SWZ(key_tex
->swizzles
[s
], c
);
965 /* Prior to Haswell, we have to lower gradients on shadow samplers */
966 tex_options
.lower_txd_shadow
= devinfo
->gen
< 8 && !devinfo
->is_haswell
;
968 tex_options
.lower_y_uv_external
= key_tex
->y_uv_image_mask
;
969 tex_options
.lower_y_u_v_external
= key_tex
->y_u_v_image_mask
;
970 tex_options
.lower_yx_xuxv_external
= key_tex
->yx_xuxv_image_mask
;
971 tex_options
.lower_xy_uxvx_external
= key_tex
->xy_uxvx_image_mask
;
972 tex_options
.lower_ayuv_external
= key_tex
->ayuv_image_mask
;
973 tex_options
.lower_xyuv_external
= key_tex
->xyuv_image_mask
;
975 /* Setup array of scaling factors for each texture. */
976 memcpy(&tex_options
.scale_factors
, &key_tex
->scale_factors
,
977 sizeof(tex_options
.scale_factors
));
979 if (nir_lower_tex(nir
, &tex_options
)) {
980 nir_validate_shader(nir
, "after nir_lower_tex");
981 brw_nir_optimize(nir
, compiler
, is_scalar
, false);
986 brw_type_for_nir_type(const struct gen_device_info
*devinfo
, nir_alu_type type
)
990 case nir_type_uint32
:
991 return BRW_REGISTER_TYPE_UD
;
994 case nir_type_bool32
:
996 return BRW_REGISTER_TYPE_D
;
998 case nir_type_float32
:
999 return BRW_REGISTER_TYPE_F
;
1000 case nir_type_float16
:
1001 return BRW_REGISTER_TYPE_HF
;
1002 case nir_type_float64
:
1003 return BRW_REGISTER_TYPE_DF
;
1004 case nir_type_int64
:
1005 return devinfo
->gen
< 8 ? BRW_REGISTER_TYPE_DF
: BRW_REGISTER_TYPE_Q
;
1006 case nir_type_uint64
:
1007 return devinfo
->gen
< 8 ? BRW_REGISTER_TYPE_DF
: BRW_REGISTER_TYPE_UQ
;
1008 case nir_type_int16
:
1009 return BRW_REGISTER_TYPE_W
;
1010 case nir_type_uint16
:
1011 return BRW_REGISTER_TYPE_UW
;
1013 return BRW_REGISTER_TYPE_B
;
1014 case nir_type_uint8
:
1015 return BRW_REGISTER_TYPE_UB
;
1017 unreachable("unknown type");
1020 return BRW_REGISTER_TYPE_F
;
1023 /* Returns the glsl_base_type corresponding to a nir_alu_type.
1024 * This is used by both brw_vec4_nir and brw_fs_nir.
1027 brw_glsl_base_type_for_nir_type(nir_alu_type type
)
1030 case nir_type_float
:
1031 case nir_type_float32
:
1032 return GLSL_TYPE_FLOAT
;
1034 case nir_type_float16
:
1035 return GLSL_TYPE_FLOAT16
;
1037 case nir_type_float64
:
1038 return GLSL_TYPE_DOUBLE
;
1041 case nir_type_int32
:
1042 return GLSL_TYPE_INT
;
1045 case nir_type_uint32
:
1046 return GLSL_TYPE_UINT
;
1048 case nir_type_int16
:
1049 return GLSL_TYPE_INT16
;
1051 case nir_type_uint16
:
1052 return GLSL_TYPE_UINT16
;
1055 unreachable("bad type");
1060 brw_nir_create_passthrough_tcs(void *mem_ctx
, const struct brw_compiler
*compiler
,
1061 const nir_shader_compiler_options
*options
,
1062 const struct brw_tcs_prog_key
*key
)
1065 nir_builder_init_simple_shader(&b
, mem_ctx
, MESA_SHADER_TESS_CTRL
,
1067 nir_shader
*nir
= b
.shader
;
1069 nir_intrinsic_instr
*load
;
1070 nir_intrinsic_instr
*store
;
1071 nir_ssa_def
*zero
= nir_imm_int(&b
, 0);
1072 nir_ssa_def
*invoc_id
= nir_load_invocation_id(&b
);
1074 nir
->info
.inputs_read
= key
->outputs_written
&
1075 ~(VARYING_BIT_TESS_LEVEL_INNER
| VARYING_BIT_TESS_LEVEL_OUTER
);
1076 nir
->info
.outputs_written
= key
->outputs_written
;
1077 nir
->info
.tess
.tcs_vertices_out
= key
->input_vertices
;
1078 nir
->info
.name
= ralloc_strdup(nir
, "passthrough");
1079 nir
->num_uniforms
= 8 * sizeof(uint32_t);
1081 var
= nir_variable_create(nir
, nir_var_uniform
, glsl_vec4_type(), "hdr_0");
1082 var
->data
.location
= 0;
1083 var
= nir_variable_create(nir
, nir_var_uniform
, glsl_vec4_type(), "hdr_1");
1084 var
->data
.location
= 1;
1086 /* Write the patch URB header. */
1087 for (int i
= 0; i
<= 1; i
++) {
1088 load
= nir_intrinsic_instr_create(nir
, nir_intrinsic_load_uniform
);
1089 load
->num_components
= 4;
1090 load
->src
[0] = nir_src_for_ssa(zero
);
1091 nir_ssa_dest_init(&load
->instr
, &load
->dest
, 4, 32, NULL
);
1092 nir_intrinsic_set_base(load
, i
* 4 * sizeof(uint32_t));
1093 nir_builder_instr_insert(&b
, &load
->instr
);
1095 store
= nir_intrinsic_instr_create(nir
, nir_intrinsic_store_output
);
1096 store
->num_components
= 4;
1097 store
->src
[0] = nir_src_for_ssa(&load
->dest
.ssa
);
1098 store
->src
[1] = nir_src_for_ssa(zero
);
1099 nir_intrinsic_set_base(store
, VARYING_SLOT_TESS_LEVEL_INNER
- i
);
1100 nir_intrinsic_set_write_mask(store
, WRITEMASK_XYZW
);
1101 nir_builder_instr_insert(&b
, &store
->instr
);
1104 /* Copy inputs to outputs. */
1105 uint64_t varyings
= nir
->info
.inputs_read
;
1107 while (varyings
!= 0) {
1108 const int varying
= ffsll(varyings
) - 1;
1110 load
= nir_intrinsic_instr_create(nir
,
1111 nir_intrinsic_load_per_vertex_input
);
1112 load
->num_components
= 4;
1113 load
->src
[0] = nir_src_for_ssa(invoc_id
);
1114 load
->src
[1] = nir_src_for_ssa(zero
);
1115 nir_ssa_dest_init(&load
->instr
, &load
->dest
, 4, 32, NULL
);
1116 nir_intrinsic_set_base(load
, varying
);
1117 nir_builder_instr_insert(&b
, &load
->instr
);
1119 store
= nir_intrinsic_instr_create(nir
,
1120 nir_intrinsic_store_per_vertex_output
);
1121 store
->num_components
= 4;
1122 store
->src
[0] = nir_src_for_ssa(&load
->dest
.ssa
);
1123 store
->src
[1] = nir_src_for_ssa(invoc_id
);
1124 store
->src
[2] = nir_src_for_ssa(zero
);
1125 nir_intrinsic_set_base(store
, varying
);
1126 nir_intrinsic_set_write_mask(store
, WRITEMASK_XYZW
);
1127 nir_builder_instr_insert(&b
, &store
->instr
);
1129 varyings
&= ~BITFIELD64_BIT(varying
);
1132 nir_validate_shader(nir
, "in brw_nir_create_passthrough_tcs");
1134 brw_preprocess_nir(compiler
, nir
, NULL
);