2 * Copyright © 2014 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 #include "brw_shader.h"
26 #include "common/gen_debug.h"
27 #include "compiler/glsl_types.h"
28 #include "compiler/nir/nir_builder.h"
29 #include "util/u_math.h"
32 is_input(nir_intrinsic_instr
*intrin
)
34 return intrin
->intrinsic
== nir_intrinsic_load_input
||
35 intrin
->intrinsic
== nir_intrinsic_load_per_vertex_input
||
36 intrin
->intrinsic
== nir_intrinsic_load_interpolated_input
;
40 is_output(nir_intrinsic_instr
*intrin
)
42 return intrin
->intrinsic
== nir_intrinsic_load_output
||
43 intrin
->intrinsic
== nir_intrinsic_load_per_vertex_output
||
44 intrin
->intrinsic
== nir_intrinsic_store_output
||
45 intrin
->intrinsic
== nir_intrinsic_store_per_vertex_output
;
49 * In many cases, we just add the base and offset together, so there's no
50 * reason to keep them separate. Sometimes, combining them is essential:
51 * if a shader only accesses part of a compound variable (such as a matrix
52 * or array), the variable's base may not actually exist in the VUE map.
54 * This pass adds constant offsets to instr->const_index[0], and resets
55 * the offset source to 0. Non-constant offsets remain unchanged - since
56 * we don't know what part of a compound variable is accessed, we allocate
57 * storage for the entire thing.
61 add_const_offset_to_base_block(nir_block
*block
, nir_builder
*b
,
62 nir_variable_mode mode
)
64 nir_foreach_instr_safe(instr
, block
) {
65 if (instr
->type
!= nir_instr_type_intrinsic
)
68 nir_intrinsic_instr
*intrin
= nir_instr_as_intrinsic(instr
);
70 if ((mode
== nir_var_shader_in
&& is_input(intrin
)) ||
71 (mode
== nir_var_shader_out
&& is_output(intrin
))) {
72 nir_src
*offset
= nir_get_io_offset_src(intrin
);
73 nir_const_value
*const_offset
= nir_src_as_const_value(*offset
);
76 intrin
->const_index
[0] += const_offset
->u32
[0];
77 b
->cursor
= nir_before_instr(&intrin
->instr
);
78 nir_instr_rewrite_src(&intrin
->instr
, offset
,
79 nir_src_for_ssa(nir_imm_int(b
, 0)));
87 add_const_offset_to_base(nir_shader
*nir
, nir_variable_mode mode
)
89 nir_foreach_function(f
, nir
) {
92 nir_builder_init(&b
, f
->impl
);
93 nir_foreach_block(block
, f
->impl
) {
94 add_const_offset_to_base_block(block
, &b
, mode
);
101 remap_tess_levels(nir_builder
*b
, nir_intrinsic_instr
*intr
,
102 GLenum primitive_mode
)
104 const int location
= nir_intrinsic_base(intr
);
105 const unsigned component
= nir_intrinsic_component(intr
);
108 if (location
== VARYING_SLOT_TESS_LEVEL_INNER
) {
109 switch (primitive_mode
) {
111 /* gl_TessLevelInner[0..1] lives at DWords 3-2 (reversed). */
112 nir_intrinsic_set_base(intr
, 0);
113 nir_intrinsic_set_component(intr
, 3 - component
);
114 out_of_bounds
= false;
117 /* gl_TessLevelInner[0] lives at DWord 4. */
118 nir_intrinsic_set_base(intr
, 1);
119 out_of_bounds
= component
> 0;
122 out_of_bounds
= true;
125 unreachable("Bogus tessellation domain");
127 } else if (location
== VARYING_SLOT_TESS_LEVEL_OUTER
) {
128 if (primitive_mode
== GL_ISOLINES
) {
129 /* gl_TessLevelOuter[0..1] lives at DWords 6-7 (in order). */
130 nir_intrinsic_set_base(intr
, 1);
131 nir_intrinsic_set_component(intr
, 2 + nir_intrinsic_component(intr
));
132 out_of_bounds
= component
> 1;
134 /* Triangles use DWords 7-5 (reversed); Quads use 7-4 (reversed) */
135 nir_intrinsic_set_base(intr
, 1);
136 nir_intrinsic_set_component(intr
, 3 - nir_intrinsic_component(intr
));
137 out_of_bounds
= component
== 3 && primitive_mode
== GL_TRIANGLES
;
144 if (nir_intrinsic_infos
[intr
->intrinsic
].has_dest
) {
145 b
->cursor
= nir_before_instr(&intr
->instr
);
146 nir_ssa_def
*undef
= nir_ssa_undef(b
, 1, 32);
147 nir_ssa_def_rewrite_uses(&intr
->dest
.ssa
, nir_src_for_ssa(undef
));
149 nir_instr_remove(&intr
->instr
);
156 remap_patch_urb_offsets(nir_block
*block
, nir_builder
*b
,
157 const struct brw_vue_map
*vue_map
,
158 GLenum tes_primitive_mode
)
160 const bool is_passthrough_tcs
= b
->shader
->info
.name
&&
161 strcmp(b
->shader
->info
.name
, "passthrough") == 0;
163 nir_foreach_instr_safe(instr
, block
) {
164 if (instr
->type
!= nir_instr_type_intrinsic
)
167 nir_intrinsic_instr
*intrin
= nir_instr_as_intrinsic(instr
);
169 gl_shader_stage stage
= b
->shader
->info
.stage
;
171 if ((stage
== MESA_SHADER_TESS_CTRL
&& is_output(intrin
)) ||
172 (stage
== MESA_SHADER_TESS_EVAL
&& is_input(intrin
))) {
174 if (!is_passthrough_tcs
&&
175 remap_tess_levels(b
, intrin
, tes_primitive_mode
))
178 int vue_slot
= vue_map
->varying_to_slot
[intrin
->const_index
[0]];
179 assert(vue_slot
!= -1);
180 intrin
->const_index
[0] = vue_slot
;
182 nir_src
*vertex
= nir_get_io_vertex_index_src(intrin
);
184 nir_const_value
*const_vertex
= nir_src_as_const_value(*vertex
);
186 intrin
->const_index
[0] += const_vertex
->u32
[0] *
187 vue_map
->num_per_vertex_slots
;
189 b
->cursor
= nir_before_instr(&intrin
->instr
);
191 /* Multiply by the number of per-vertex slots. */
192 nir_ssa_def
*vertex_offset
=
194 nir_ssa_for_src(b
, *vertex
, 1),
196 vue_map
->num_per_vertex_slots
));
198 /* Add it to the existing offset */
199 nir_src
*offset
= nir_get_io_offset_src(intrin
);
200 nir_ssa_def
*total_offset
=
201 nir_iadd(b
, vertex_offset
,
202 nir_ssa_for_src(b
, *offset
, 1));
204 nir_instr_rewrite_src(&intrin
->instr
, offset
,
205 nir_src_for_ssa(total_offset
));
214 brw_nir_lower_vs_inputs(nir_shader
*nir
,
215 const uint8_t *vs_attrib_wa_flags
)
217 /* Start with the location of the variable's base. */
218 foreach_list_typed(nir_variable
, var
, node
, &nir
->inputs
) {
219 var
->data
.driver_location
= var
->data
.location
;
222 /* Now use nir_lower_io to walk dereference chains. Attribute arrays are
223 * loaded as one vec4 or dvec4 per element (or matrix column), depending on
224 * whether it is a double-precision type or not.
226 nir_lower_io(nir
, nir_var_shader_in
, type_size_vec4
, 0);
228 /* This pass needs actual constants */
229 nir_opt_constant_folding(nir
);
231 add_const_offset_to_base(nir
, nir_var_shader_in
);
233 brw_nir_apply_attribute_workarounds(nir
, vs_attrib_wa_flags
);
235 /* The last step is to remap VERT_ATTRIB_* to actual registers */
237 /* Whether or not we have any system generated values. gl_DrawID is not
238 * included here as it lives in its own vec4.
240 const bool has_sgvs
=
241 nir
->info
.system_values_read
&
242 (BITFIELD64_BIT(SYSTEM_VALUE_FIRST_VERTEX
) |
243 BITFIELD64_BIT(SYSTEM_VALUE_BASE_INSTANCE
) |
244 BITFIELD64_BIT(SYSTEM_VALUE_VERTEX_ID_ZERO_BASE
) |
245 BITFIELD64_BIT(SYSTEM_VALUE_INSTANCE_ID
));
247 const unsigned num_inputs
= util_bitcount64(nir
->info
.inputs_read
);
249 nir_foreach_function(function
, nir
) {
254 nir_builder_init(&b
, function
->impl
);
256 nir_foreach_block(block
, function
->impl
) {
257 nir_foreach_instr_safe(instr
, block
) {
258 if (instr
->type
!= nir_instr_type_intrinsic
)
261 nir_intrinsic_instr
*intrin
= nir_instr_as_intrinsic(instr
);
263 switch (intrin
->intrinsic
) {
264 case nir_intrinsic_load_first_vertex
:
265 case nir_intrinsic_load_base_instance
:
266 case nir_intrinsic_load_vertex_id_zero_base
:
267 case nir_intrinsic_load_instance_id
:
268 case nir_intrinsic_load_is_indexed_draw
:
269 case nir_intrinsic_load_draw_id
: {
270 b
.cursor
= nir_after_instr(&intrin
->instr
);
272 /* gl_VertexID and friends are stored by the VF as the last
273 * vertex element. We convert them to load_input intrinsics at
274 * the right location.
276 nir_intrinsic_instr
*load
=
277 nir_intrinsic_instr_create(nir
, nir_intrinsic_load_input
);
278 load
->src
[0] = nir_src_for_ssa(nir_imm_int(&b
, 0));
280 nir_intrinsic_set_base(load
, num_inputs
);
281 switch (intrin
->intrinsic
) {
282 case nir_intrinsic_load_first_vertex
:
283 nir_intrinsic_set_component(load
, 0);
285 case nir_intrinsic_load_base_instance
:
286 nir_intrinsic_set_component(load
, 1);
288 case nir_intrinsic_load_vertex_id_zero_base
:
289 nir_intrinsic_set_component(load
, 2);
291 case nir_intrinsic_load_instance_id
:
292 nir_intrinsic_set_component(load
, 3);
294 case nir_intrinsic_load_draw_id
:
295 case nir_intrinsic_load_is_indexed_draw
:
296 /* gl_DrawID and IsIndexedDraw are stored right after
297 * gl_VertexID and friends if any of them exist.
299 nir_intrinsic_set_base(load
, num_inputs
+ has_sgvs
);
300 if (intrin
->intrinsic
== nir_intrinsic_load_draw_id
)
301 nir_intrinsic_set_component(load
, 0);
303 nir_intrinsic_set_component(load
, 1);
306 unreachable("Invalid system value intrinsic");
309 load
->num_components
= 1;
310 nir_ssa_dest_init(&load
->instr
, &load
->dest
, 1, 32, NULL
);
311 nir_builder_instr_insert(&b
, &load
->instr
);
313 nir_ssa_def_rewrite_uses(&intrin
->dest
.ssa
,
314 nir_src_for_ssa(&load
->dest
.ssa
));
315 nir_instr_remove(&intrin
->instr
);
319 case nir_intrinsic_load_input
: {
320 /* Attributes come in a contiguous block, ordered by their
321 * gl_vert_attrib value. That means we can compute the slot
322 * number for an attribute by masking out the enabled attributes
323 * before it and counting the bits.
325 int attr
= nir_intrinsic_base(intrin
);
326 int slot
= util_bitcount64(nir
->info
.inputs_read
&
327 BITFIELD64_MASK(attr
));
328 nir_intrinsic_set_base(intrin
, slot
);
333 break; /* Nothing to do */
341 brw_nir_lower_vue_inputs(nir_shader
*nir
,
342 const struct brw_vue_map
*vue_map
)
344 foreach_list_typed(nir_variable
, var
, node
, &nir
->inputs
) {
345 var
->data
.driver_location
= var
->data
.location
;
348 /* Inputs are stored in vec4 slots, so use type_size_vec4(). */
349 nir_lower_io(nir
, nir_var_shader_in
, type_size_vec4
, 0);
351 /* This pass needs actual constants */
352 nir_opt_constant_folding(nir
);
354 add_const_offset_to_base(nir
, nir_var_shader_in
);
356 nir_foreach_function(function
, nir
) {
360 nir_foreach_block(block
, function
->impl
) {
361 nir_foreach_instr(instr
, block
) {
362 if (instr
->type
!= nir_instr_type_intrinsic
)
365 nir_intrinsic_instr
*intrin
= nir_instr_as_intrinsic(instr
);
367 if (intrin
->intrinsic
== nir_intrinsic_load_input
||
368 intrin
->intrinsic
== nir_intrinsic_load_per_vertex_input
) {
369 /* Offset 0 is the VUE header, which contains
370 * VARYING_SLOT_LAYER [.y], VARYING_SLOT_VIEWPORT [.z], and
371 * VARYING_SLOT_PSIZ [.w].
373 int varying
= nir_intrinsic_base(intrin
);
376 case VARYING_SLOT_PSIZ
:
377 nir_intrinsic_set_base(intrin
, 0);
378 nir_intrinsic_set_component(intrin
, 3);
382 vue_slot
= vue_map
->varying_to_slot
[varying
];
383 assert(vue_slot
!= -1);
384 nir_intrinsic_set_base(intrin
, vue_slot
);
394 brw_nir_lower_tes_inputs(nir_shader
*nir
, const struct brw_vue_map
*vue_map
)
396 foreach_list_typed(nir_variable
, var
, node
, &nir
->inputs
) {
397 var
->data
.driver_location
= var
->data
.location
;
400 nir_lower_io(nir
, nir_var_shader_in
, type_size_vec4
, 0);
402 /* This pass needs actual constants */
403 nir_opt_constant_folding(nir
);
405 add_const_offset_to_base(nir
, nir_var_shader_in
);
407 nir_foreach_function(function
, nir
) {
408 if (function
->impl
) {
410 nir_builder_init(&b
, function
->impl
);
411 nir_foreach_block(block
, function
->impl
) {
412 remap_patch_urb_offsets(block
, &b
, vue_map
,
413 nir
->info
.tess
.primitive_mode
);
420 brw_nir_lower_fs_inputs(nir_shader
*nir
,
421 const struct gen_device_info
*devinfo
,
422 const struct brw_wm_prog_key
*key
)
424 foreach_list_typed(nir_variable
, var
, node
, &nir
->inputs
) {
425 var
->data
.driver_location
= var
->data
.location
;
427 /* Apply default interpolation mode.
429 * Everything defaults to smooth except for the legacy GL color
430 * built-in variables, which might be flat depending on API state.
432 if (var
->data
.interpolation
== INTERP_MODE_NONE
) {
433 const bool flat
= key
->flat_shade
&&
434 (var
->data
.location
== VARYING_SLOT_COL0
||
435 var
->data
.location
== VARYING_SLOT_COL1
);
437 var
->data
.interpolation
= flat
? INTERP_MODE_FLAT
438 : INTERP_MODE_SMOOTH
;
441 /* On Ironlake and below, there is only one interpolation mode.
442 * Centroid interpolation doesn't mean anything on this hardware --
443 * there is no multisampling.
445 if (devinfo
->gen
< 6) {
446 var
->data
.centroid
= false;
447 var
->data
.sample
= false;
451 nir_lower_io_options lower_io_options
= 0;
452 if (key
->persample_interp
)
453 lower_io_options
|= nir_lower_io_force_sample_interpolation
;
455 nir_lower_io(nir
, nir_var_shader_in
, type_size_vec4
, lower_io_options
);
457 /* This pass needs actual constants */
458 nir_opt_constant_folding(nir
);
460 add_const_offset_to_base(nir
, nir_var_shader_in
);
464 brw_nir_lower_vue_outputs(nir_shader
*nir
)
466 nir_foreach_variable(var
, &nir
->outputs
) {
467 var
->data
.driver_location
= var
->data
.location
;
470 nir_lower_io(nir
, nir_var_shader_out
, type_size_vec4
, 0);
474 brw_nir_lower_tcs_outputs(nir_shader
*nir
, const struct brw_vue_map
*vue_map
,
475 GLenum tes_primitive_mode
)
477 nir_foreach_variable(var
, &nir
->outputs
) {
478 var
->data
.driver_location
= var
->data
.location
;
481 nir_lower_io(nir
, nir_var_shader_out
, type_size_vec4
, 0);
483 /* This pass needs actual constants */
484 nir_opt_constant_folding(nir
);
486 add_const_offset_to_base(nir
, nir_var_shader_out
);
488 nir_foreach_function(function
, nir
) {
489 if (function
->impl
) {
491 nir_builder_init(&b
, function
->impl
);
492 nir_foreach_block(block
, function
->impl
) {
493 remap_patch_urb_offsets(block
, &b
, vue_map
, tes_primitive_mode
);
500 brw_nir_lower_fs_outputs(nir_shader
*nir
)
502 nir_foreach_variable(var
, &nir
->outputs
) {
503 var
->data
.driver_location
=
504 SET_FIELD(var
->data
.index
, BRW_NIR_FRAG_OUTPUT_INDEX
) |
505 SET_FIELD(var
->data
.location
, BRW_NIR_FRAG_OUTPUT_LOCATION
);
508 nir_lower_io(nir
, nir_var_shader_out
, type_size_dvec4
, 0);
511 #define OPT(pass, ...) ({ \
512 bool this_progress = false; \
513 NIR_PASS(this_progress, nir, pass, ##__VA_ARGS__); \
519 static nir_variable_mode
520 brw_nir_no_indirect_mask(const struct brw_compiler
*compiler
,
521 gl_shader_stage stage
)
523 nir_variable_mode indirect_mask
= 0;
525 if (compiler
->glsl_compiler_options
[stage
].EmitNoIndirectInput
)
526 indirect_mask
|= nir_var_shader_in
;
527 if (compiler
->glsl_compiler_options
[stage
].EmitNoIndirectOutput
)
528 indirect_mask
|= nir_var_shader_out
;
529 if (compiler
->glsl_compiler_options
[stage
].EmitNoIndirectTemp
)
530 indirect_mask
|= nir_var_function_temp
;
532 return indirect_mask
;
536 brw_nir_optimize(nir_shader
*nir
, const struct brw_compiler
*compiler
,
537 bool is_scalar
, bool allow_copies
)
539 nir_variable_mode indirect_mask
=
540 brw_nir_no_indirect_mask(compiler
, nir
->info
.stage
);
545 OPT(nir_split_array_vars
, nir_var_function_temp
);
546 OPT(nir_shrink_vec_array_vars
, nir_var_function_temp
);
548 OPT(nir_lower_vars_to_ssa
);
550 /* Only run this pass in the first call to brw_nir_optimize. Later
551 * calls assume that we've lowered away any copy_deref instructions
552 * and we don't want to introduce any more.
554 OPT(nir_opt_find_array_copies
);
556 OPT(nir_opt_copy_prop_vars
);
557 OPT(nir_opt_dead_write_vars
);
558 OPT(nir_opt_combine_stores
, nir_var_all
);
561 OPT(nir_lower_alu_to_scalar
);
567 OPT(nir_lower_phis_to_scalar
);
573 OPT(nir_opt_combine_stores
, nir_var_all
);
575 /* Passing 0 to the peephole select pass causes it to convert
576 * if-statements that contain only move instructions in the branches
577 * regardless of the count.
579 * Passing 1 to the peephole select pass causes it to convert
580 * if-statements that contain at most a single ALU instruction (total)
581 * in both branches. Before Gen6, some math instructions were
582 * prohibitively expensive and the results of compare operations need an
583 * extra resolve step. For these reasons, this pass is more harmful
584 * than good on those platforms.
586 * For indirect loads of uniforms (push constants), we assume that array
587 * indices will nearly always be in bounds and the cost of the load is
588 * low. Therefore there shouldn't be a performance benefit to avoid it.
589 * However, in vec4 tessellation shaders, these loads operate by
590 * actually pulling from memory.
592 const bool is_vec4_tessellation
= !is_scalar
&&
593 (nir
->info
.stage
== MESA_SHADER_TESS_CTRL
||
594 nir
->info
.stage
== MESA_SHADER_TESS_EVAL
);
595 OPT(nir_opt_peephole_select
, 0, !is_vec4_tessellation
, false);
596 OPT(nir_opt_peephole_select
, 1, !is_vec4_tessellation
,
597 compiler
->devinfo
->gen
>= 6);
599 OPT(nir_opt_intrinsics
);
600 OPT(nir_opt_idiv_const
, 32);
601 OPT(nir_opt_algebraic
);
602 OPT(nir_opt_constant_folding
);
603 OPT(nir_opt_dead_cf
);
604 if (OPT(nir_opt_trivial_continues
)) {
605 /* If nir_opt_trivial_continues makes progress, then we need to clean
606 * things up if we want any hope of nir_opt_if or nir_opt_loop_unroll
612 OPT(nir_opt_if
, false);
613 if (nir
->options
->max_unroll_iterations
!= 0) {
614 OPT(nir_opt_loop_unroll
, indirect_mask
);
616 OPT(nir_opt_remove_phis
);
621 /* Workaround Gfxbench unused local sampler variable which will trigger an
622 * assert in the opt_large_constants pass.
624 OPT(nir_remove_dead_variables
, nir_var_function_temp
);
630 lower_bit_size_callback(const nir_alu_instr
*alu
, UNUSED
void *data
)
632 assert(alu
->dest
.dest
.is_ssa
);
633 if (alu
->dest
.dest
.ssa
.bit_size
!= 16)
648 /* Does some simple lowering and runs the standard suite of optimizations
650 * This is intended to be called more-or-less directly after you get the
651 * shader out of GLSL or some other source. While it is geared towards i965,
652 * it is not at all generator-specific except for the is_scalar flag. Even
653 * there, it is safe to call with is_scalar = false for a shader that is
654 * intended for the FS backend as long as nir_optimize is called again with
655 * is_scalar = true to scalarize everything prior to code gen.
658 brw_preprocess_nir(const struct brw_compiler
*compiler
, nir_shader
*nir
,
659 const nir_shader
*softfp64
)
661 const struct gen_device_info
*devinfo
= compiler
->devinfo
;
662 UNUSED
bool progress
; /* Written by OPT */
664 const bool is_scalar
= compiler
->scalar_stage
[nir
->info
.stage
];
667 OPT(nir_lower_alu_to_scalar
);
670 if (nir
->info
.stage
== MESA_SHADER_GEOMETRY
)
671 OPT(nir_lower_gs_intrinsics
);
673 /* See also brw_nir_trig_workarounds.py */
674 if (compiler
->precise_trig
&&
675 !(devinfo
->gen
>= 10 || devinfo
->is_kabylake
))
676 OPT(brw_nir_apply_trig_workarounds
);
678 static const nir_lower_tex_options tex_options
= {
680 .lower_txf_offset
= true,
681 .lower_rect_offset
= true,
682 .lower_txd_cube_map
= true,
683 .lower_txb_shadow_clamp
= true,
684 .lower_txd_shadow_clamp
= true,
685 .lower_txd_offset_clamp
= true,
686 .lower_tg4_offsets
= true,
689 OPT(nir_lower_tex
, &tex_options
);
690 OPT(nir_normalize_cubemap_coords
);
692 OPT(nir_lower_global_vars_to_local
);
694 OPT(nir_split_var_copies
);
695 OPT(nir_split_struct_vars
, nir_var_function_temp
);
697 nir
= brw_nir_optimize(nir
, compiler
, is_scalar
, true);
699 bool lowered_64bit_ops
= false;
703 OPT(nir_lower_int64
, nir
->options
->lower_int64_options
);
704 OPT(nir_lower_doubles
, softfp64
, nir
->options
->lower_doubles_options
);
706 /* Necessary to lower add -> sub and div -> mul/rcp */
707 OPT(nir_opt_algebraic
);
709 lowered_64bit_ops
|= progress
;
712 /* This needs to be run after the first optimization pass but before we
713 * lower indirect derefs away
715 if (compiler
->supports_shader_constants
) {
716 OPT(nir_opt_large_constants
, NULL
, 32);
719 OPT(nir_lower_bit_size
, lower_bit_size_callback
, NULL
);
722 OPT(nir_lower_load_const_to_scalar
);
725 /* Lower a bunch of stuff */
726 OPT(nir_lower_var_copies
);
728 OPT(nir_lower_system_values
);
730 const nir_lower_subgroups_options subgroups_options
= {
731 .subgroup_size
= BRW_SUBGROUP_SIZE
,
732 .ballot_bit_size
= 32,
733 .lower_to_scalar
= true,
734 .lower_subgroup_masks
= true,
735 .lower_vote_trivial
= !is_scalar
,
736 .lower_shuffle
= true,
738 OPT(nir_lower_subgroups
, &subgroups_options
);
740 OPT(nir_lower_clip_cull_distance_arrays
);
742 nir_variable_mode indirect_mask
=
743 brw_nir_no_indirect_mask(compiler
, nir
->info
.stage
);
744 OPT(nir_lower_indirect_derefs
, indirect_mask
);
746 /* Lower array derefs of vectors for SSBO and UBO loads. For both UBOs and
747 * SSBOs, our back-end is capable of loading an entire vec4 at a time and
748 * we would like to take advantage of that whenever possible regardless of
749 * whether or not the app gives us full loads. This should allow the
750 * optimizer to combine UBO and SSBO load operations and save us some send
753 OPT(nir_lower_array_deref_of_vec
,
754 nir_var_mem_ubo
| nir_var_mem_ssbo
,
755 nir_lower_direct_array_deref_of_vec_load
);
757 /* Get rid of split copies */
758 nir
= brw_nir_optimize(nir
, compiler
, is_scalar
, false);
764 brw_nir_link_shaders(const struct brw_compiler
*compiler
,
765 nir_shader
**producer
, nir_shader
**consumer
)
767 nir_lower_io_arrays_to_elements(*producer
, *consumer
);
768 nir_validate_shader(*producer
, "after nir_lower_io_arrays_to_elements");
769 nir_validate_shader(*consumer
, "after nir_lower_io_arrays_to_elements");
771 const bool p_is_scalar
=
772 compiler
->scalar_stage
[(*producer
)->info
.stage
];
773 const bool c_is_scalar
=
774 compiler
->scalar_stage
[(*consumer
)->info
.stage
];
776 if (p_is_scalar
&& c_is_scalar
) {
777 NIR_PASS_V(*producer
, nir_lower_io_to_scalar_early
, nir_var_shader_out
);
778 NIR_PASS_V(*consumer
, nir_lower_io_to_scalar_early
, nir_var_shader_in
);
779 *producer
= brw_nir_optimize(*producer
, compiler
, p_is_scalar
, false);
780 *consumer
= brw_nir_optimize(*consumer
, compiler
, c_is_scalar
, false);
783 if (nir_link_opt_varyings(*producer
, *consumer
))
784 *consumer
= brw_nir_optimize(*consumer
, compiler
, c_is_scalar
, false);
786 NIR_PASS_V(*producer
, nir_remove_dead_variables
, nir_var_shader_out
);
787 NIR_PASS_V(*consumer
, nir_remove_dead_variables
, nir_var_shader_in
);
789 if (nir_remove_unused_varyings(*producer
, *consumer
)) {
790 NIR_PASS_V(*producer
, nir_lower_global_vars_to_local
);
791 NIR_PASS_V(*consumer
, nir_lower_global_vars_to_local
);
793 /* The backend might not be able to handle indirects on
794 * temporaries so we need to lower indirects on any of the
795 * varyings we have demoted here.
797 NIR_PASS_V(*producer
, nir_lower_indirect_derefs
,
798 brw_nir_no_indirect_mask(compiler
, (*producer
)->info
.stage
));
799 NIR_PASS_V(*consumer
, nir_lower_indirect_derefs
,
800 brw_nir_no_indirect_mask(compiler
, (*consumer
)->info
.stage
));
802 *producer
= brw_nir_optimize(*producer
, compiler
, p_is_scalar
, false);
803 *consumer
= brw_nir_optimize(*consumer
, compiler
, c_is_scalar
, false);
806 NIR_PASS_V(*producer
, nir_lower_io_to_vector
, nir_var_shader_out
);
807 NIR_PASS_V(*producer
, nir_opt_combine_stores
, nir_var_shader_out
);
808 NIR_PASS_V(*consumer
, nir_lower_io_to_vector
, nir_var_shader_in
);
810 if ((*producer
)->info
.stage
!= MESA_SHADER_TESS_CTRL
) {
811 /* Calling lower_io_to_vector creates output variable writes with
812 * write-masks. On non-TCS outputs, the back-end can't handle it and we
813 * need to call nir_lower_io_to_temporaries to get rid of them. This,
814 * in turn, creates temporary variables and extra copy_deref intrinsics
815 * that we need to clean up.
817 NIR_PASS_V(*producer
, nir_lower_io_to_temporaries
,
818 nir_shader_get_entrypoint(*producer
), true, false);
819 NIR_PASS_V(*producer
, nir_lower_global_vars_to_local
);
820 NIR_PASS_V(*producer
, nir_split_var_copies
);
821 NIR_PASS_V(*producer
, nir_lower_var_copies
);
825 /* Prepare the given shader for codegen
827 * This function is intended to be called right before going into the actual
828 * backend and is highly backend-specific. Also, once this function has been
829 * called on a shader, it will no longer be in SSA form so most optimizations
833 brw_postprocess_nir(nir_shader
*nir
, const struct brw_compiler
*compiler
,
836 const struct gen_device_info
*devinfo
= compiler
->devinfo
;
838 (INTEL_DEBUG
& intel_debug_flag_for_shader_stage(nir
->info
.stage
));
840 UNUSED
bool progress
; /* Written by OPT */
842 OPT(brw_nir_lower_mem_access_bit_sizes
);
846 OPT(nir_opt_algebraic_before_ffma
);
849 nir
= brw_nir_optimize(nir
, compiler
, is_scalar
, false);
851 if (devinfo
->gen
>= 6) {
852 /* Try and fuse multiply-adds */
853 OPT(brw_nir_opt_peephole_ffma
);
856 if (OPT(nir_opt_comparison_pre
)) {
861 /* Do the select peepehole again. nir_opt_comparison_pre (combined with
862 * the other optimization passes) will have removed at least one
863 * instruction from one of the branches of the if-statement, so now it
864 * might be under the threshold of conversion to bcsel.
866 * See brw_nir_optimize for the explanation of is_vec4_tessellation.
868 const bool is_vec4_tessellation
= !is_scalar
&&
869 (nir
->info
.stage
== MESA_SHADER_TESS_CTRL
||
870 nir
->info
.stage
== MESA_SHADER_TESS_EVAL
);
871 OPT(nir_opt_peephole_select
, 0, is_vec4_tessellation
, false);
872 OPT(nir_opt_peephole_select
, 1, is_vec4_tessellation
,
873 compiler
->devinfo
->gen
>= 6);
876 OPT(nir_opt_algebraic_late
);
878 OPT(nir_lower_to_source_mods
, nir_lower_all_source_mods
);
881 OPT(nir_opt_move_comparisons
);
883 OPT(nir_lower_bool_to_int32
);
885 OPT(nir_lower_locals_to_regs
);
887 if (unlikely(debug_enabled
)) {
888 /* Re-index SSA defs so we print more sensible numbers. */
889 nir_foreach_function(function
, nir
) {
891 nir_index_ssa_defs(function
->impl
);
894 fprintf(stderr
, "NIR (SSA form) for %s shader:\n",
895 _mesa_shader_stage_to_string(nir
->info
.stage
));
896 nir_print_shader(nir
, stderr
);
899 OPT(nir_convert_from_ssa
, true);
902 OPT(nir_move_vec_src_uses_to_dest
);
903 OPT(nir_lower_vec_to_movs
);
908 /* This is the last pass we run before we start emitting stuff. It
909 * determines when we need to insert boolean resolves on Gen <= 5. We
910 * run it last because it stashes data in instr->pass_flags and we don't
911 * want that to be squashed by other NIR passes.
913 if (devinfo
->gen
<= 5)
914 brw_nir_analyze_boolean_resolves(nir
);
918 if (unlikely(debug_enabled
)) {
919 fprintf(stderr
, "NIR (final form) for %s shader:\n",
920 _mesa_shader_stage_to_string(nir
->info
.stage
));
921 nir_print_shader(nir
, stderr
);
928 brw_nir_apply_sampler_key(nir_shader
*nir
,
929 const struct brw_compiler
*compiler
,
930 const struct brw_sampler_prog_key_data
*key_tex
,
933 const struct gen_device_info
*devinfo
= compiler
->devinfo
;
934 nir_lower_tex_options tex_options
= {
935 .lower_txd_clamp_if_sampler_index_not_lt_16
= true,
938 /* Iron Lake and prior require lowering of all rectangle textures */
939 if (devinfo
->gen
< 6)
940 tex_options
.lower_rect
= true;
942 /* Prior to Broadwell, our hardware can't actually do GL_CLAMP */
943 if (devinfo
->gen
< 8) {
944 tex_options
.saturate_s
= key_tex
->gl_clamp_mask
[0];
945 tex_options
.saturate_t
= key_tex
->gl_clamp_mask
[1];
946 tex_options
.saturate_r
= key_tex
->gl_clamp_mask
[2];
949 /* Prior to Haswell, we have to fake texture swizzle */
950 for (unsigned s
= 0; s
< MAX_SAMPLERS
; s
++) {
951 if (key_tex
->swizzles
[s
] == SWIZZLE_NOOP
)
954 tex_options
.swizzle_result
|= (1 << s
);
955 for (unsigned c
= 0; c
< 4; c
++)
956 tex_options
.swizzles
[s
][c
] = GET_SWZ(key_tex
->swizzles
[s
], c
);
959 /* Prior to Haswell, we have to lower gradients on shadow samplers */
960 tex_options
.lower_txd_shadow
= devinfo
->gen
< 8 && !devinfo
->is_haswell
;
962 tex_options
.lower_y_uv_external
= key_tex
->y_uv_image_mask
;
963 tex_options
.lower_y_u_v_external
= key_tex
->y_u_v_image_mask
;
964 tex_options
.lower_yx_xuxv_external
= key_tex
->yx_xuxv_image_mask
;
965 tex_options
.lower_xy_uxvx_external
= key_tex
->xy_uxvx_image_mask
;
966 tex_options
.lower_ayuv_external
= key_tex
->ayuv_image_mask
;
967 tex_options
.lower_xyuv_external
= key_tex
->xyuv_image_mask
;
969 /* Setup array of scaling factors for each texture. */
970 memcpy(&tex_options
.scale_factors
, &key_tex
->scale_factors
,
971 sizeof(tex_options
.scale_factors
));
973 if (nir_lower_tex(nir
, &tex_options
)) {
974 nir_validate_shader(nir
, "after nir_lower_tex");
975 nir
= brw_nir_optimize(nir
, compiler
, is_scalar
, false);
982 brw_type_for_nir_type(const struct gen_device_info
*devinfo
, nir_alu_type type
)
986 case nir_type_uint32
:
987 return BRW_REGISTER_TYPE_UD
;
990 case nir_type_bool32
:
992 return BRW_REGISTER_TYPE_D
;
994 case nir_type_float32
:
995 return BRW_REGISTER_TYPE_F
;
996 case nir_type_float16
:
997 return BRW_REGISTER_TYPE_HF
;
998 case nir_type_float64
:
999 return BRW_REGISTER_TYPE_DF
;
1000 case nir_type_int64
:
1001 return devinfo
->gen
< 8 ? BRW_REGISTER_TYPE_DF
: BRW_REGISTER_TYPE_Q
;
1002 case nir_type_uint64
:
1003 return devinfo
->gen
< 8 ? BRW_REGISTER_TYPE_DF
: BRW_REGISTER_TYPE_UQ
;
1004 case nir_type_int16
:
1005 return BRW_REGISTER_TYPE_W
;
1006 case nir_type_uint16
:
1007 return BRW_REGISTER_TYPE_UW
;
1009 return BRW_REGISTER_TYPE_B
;
1010 case nir_type_uint8
:
1011 return BRW_REGISTER_TYPE_UB
;
1013 unreachable("unknown type");
1016 return BRW_REGISTER_TYPE_F
;
1019 /* Returns the glsl_base_type corresponding to a nir_alu_type.
1020 * This is used by both brw_vec4_nir and brw_fs_nir.
1023 brw_glsl_base_type_for_nir_type(nir_alu_type type
)
1026 case nir_type_float
:
1027 case nir_type_float32
:
1028 return GLSL_TYPE_FLOAT
;
1030 case nir_type_float16
:
1031 return GLSL_TYPE_FLOAT16
;
1033 case nir_type_float64
:
1034 return GLSL_TYPE_DOUBLE
;
1037 case nir_type_int32
:
1038 return GLSL_TYPE_INT
;
1041 case nir_type_uint32
:
1042 return GLSL_TYPE_UINT
;
1044 case nir_type_int16
:
1045 return GLSL_TYPE_INT16
;
1047 case nir_type_uint16
:
1048 return GLSL_TYPE_UINT16
;
1051 unreachable("bad type");
1056 brw_nir_create_passthrough_tcs(void *mem_ctx
, const struct brw_compiler
*compiler
,
1057 const nir_shader_compiler_options
*options
,
1058 const struct brw_tcs_prog_key
*key
)
1061 nir_builder_init_simple_shader(&b
, mem_ctx
, MESA_SHADER_TESS_CTRL
,
1063 nir_shader
*nir
= b
.shader
;
1065 nir_intrinsic_instr
*load
;
1066 nir_intrinsic_instr
*store
;
1067 nir_ssa_def
*zero
= nir_imm_int(&b
, 0);
1068 nir_ssa_def
*invoc_id
= nir_load_invocation_id(&b
);
1070 nir
->info
.inputs_read
= key
->outputs_written
&
1071 ~(VARYING_BIT_TESS_LEVEL_INNER
| VARYING_BIT_TESS_LEVEL_OUTER
);
1072 nir
->info
.outputs_written
= key
->outputs_written
;
1073 nir
->info
.tess
.tcs_vertices_out
= key
->input_vertices
;
1074 nir
->info
.name
= ralloc_strdup(nir
, "passthrough");
1075 nir
->num_uniforms
= 8 * sizeof(uint32_t);
1077 var
= nir_variable_create(nir
, nir_var_uniform
, glsl_vec4_type(), "hdr_0");
1078 var
->data
.location
= 0;
1079 var
= nir_variable_create(nir
, nir_var_uniform
, glsl_vec4_type(), "hdr_1");
1080 var
->data
.location
= 1;
1082 /* Write the patch URB header. */
1083 for (int i
= 0; i
<= 1; i
++) {
1084 load
= nir_intrinsic_instr_create(nir
, nir_intrinsic_load_uniform
);
1085 load
->num_components
= 4;
1086 load
->src
[0] = nir_src_for_ssa(zero
);
1087 nir_ssa_dest_init(&load
->instr
, &load
->dest
, 4, 32, NULL
);
1088 nir_intrinsic_set_base(load
, i
* 4 * sizeof(uint32_t));
1089 nir_builder_instr_insert(&b
, &load
->instr
);
1091 store
= nir_intrinsic_instr_create(nir
, nir_intrinsic_store_output
);
1092 store
->num_components
= 4;
1093 store
->src
[0] = nir_src_for_ssa(&load
->dest
.ssa
);
1094 store
->src
[1] = nir_src_for_ssa(zero
);
1095 nir_intrinsic_set_base(store
, VARYING_SLOT_TESS_LEVEL_INNER
- i
);
1096 nir_intrinsic_set_write_mask(store
, WRITEMASK_XYZW
);
1097 nir_builder_instr_insert(&b
, &store
->instr
);
1100 /* Copy inputs to outputs. */
1101 uint64_t varyings
= nir
->info
.inputs_read
;
1103 while (varyings
!= 0) {
1104 const int varying
= ffsll(varyings
) - 1;
1106 load
= nir_intrinsic_instr_create(nir
,
1107 nir_intrinsic_load_per_vertex_input
);
1108 load
->num_components
= 4;
1109 load
->src
[0] = nir_src_for_ssa(invoc_id
);
1110 load
->src
[1] = nir_src_for_ssa(zero
);
1111 nir_ssa_dest_init(&load
->instr
, &load
->dest
, 4, 32, NULL
);
1112 nir_intrinsic_set_base(load
, varying
);
1113 nir_builder_instr_insert(&b
, &load
->instr
);
1115 store
= nir_intrinsic_instr_create(nir
,
1116 nir_intrinsic_store_per_vertex_output
);
1117 store
->num_components
= 4;
1118 store
->src
[0] = nir_src_for_ssa(&load
->dest
.ssa
);
1119 store
->src
[1] = nir_src_for_ssa(invoc_id
);
1120 store
->src
[2] = nir_src_for_ssa(zero
);
1121 nir_intrinsic_set_base(store
, varying
);
1122 nir_intrinsic_set_write_mask(store
, WRITEMASK_XYZW
);
1123 nir_builder_instr_insert(&b
, &store
->instr
);
1125 varyings
&= ~BITFIELD64_BIT(varying
);
1128 nir_validate_shader(nir
, "in brw_nir_create_passthrough_tcs");
1130 nir
= brw_preprocess_nir(compiler
, nir
, NULL
);