2 * Copyright © 2014 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 #include "brw_shader.h"
26 #include "common/gen_debug.h"
27 #include "compiler/glsl_types.h"
28 #include "compiler/nir/nir_builder.h"
31 is_input(nir_intrinsic_instr
*intrin
)
33 return intrin
->intrinsic
== nir_intrinsic_load_input
||
34 intrin
->intrinsic
== nir_intrinsic_load_per_vertex_input
||
35 intrin
->intrinsic
== nir_intrinsic_load_interpolated_input
;
39 is_output(nir_intrinsic_instr
*intrin
)
41 return intrin
->intrinsic
== nir_intrinsic_load_output
||
42 intrin
->intrinsic
== nir_intrinsic_load_per_vertex_output
||
43 intrin
->intrinsic
== nir_intrinsic_store_output
||
44 intrin
->intrinsic
== nir_intrinsic_store_per_vertex_output
;
48 * In many cases, we just add the base and offset together, so there's no
49 * reason to keep them separate. Sometimes, combining them is essential:
50 * if a shader only accesses part of a compound variable (such as a matrix
51 * or array), the variable's base may not actually exist in the VUE map.
53 * This pass adds constant offsets to instr->const_index[0], and resets
54 * the offset source to 0. Non-constant offsets remain unchanged - since
55 * we don't know what part of a compound variable is accessed, we allocate
56 * storage for the entire thing.
60 add_const_offset_to_base_block(nir_block
*block
, nir_builder
*b
,
61 nir_variable_mode mode
)
63 nir_foreach_instr_safe(instr
, block
) {
64 if (instr
->type
!= nir_instr_type_intrinsic
)
67 nir_intrinsic_instr
*intrin
= nir_instr_as_intrinsic(instr
);
69 if ((mode
== nir_var_shader_in
&& is_input(intrin
)) ||
70 (mode
== nir_var_shader_out
&& is_output(intrin
))) {
71 nir_src
*offset
= nir_get_io_offset_src(intrin
);
72 nir_const_value
*const_offset
= nir_src_as_const_value(*offset
);
75 intrin
->const_index
[0] += const_offset
->u32
[0];
76 b
->cursor
= nir_before_instr(&intrin
->instr
);
77 nir_instr_rewrite_src(&intrin
->instr
, offset
,
78 nir_src_for_ssa(nir_imm_int(b
, 0)));
86 add_const_offset_to_base(nir_shader
*nir
, nir_variable_mode mode
)
88 nir_foreach_function(f
, nir
) {
91 nir_builder_init(&b
, f
->impl
);
92 nir_foreach_block(block
, f
->impl
) {
93 add_const_offset_to_base_block(block
, &b
, mode
);
100 remap_tess_levels(nir_builder
*b
, nir_intrinsic_instr
*intr
,
101 GLenum primitive_mode
)
103 const int location
= nir_intrinsic_base(intr
);
104 const unsigned component
= nir_intrinsic_component(intr
);
107 if (location
== VARYING_SLOT_TESS_LEVEL_INNER
) {
108 switch (primitive_mode
) {
110 /* gl_TessLevelInner[0..1] lives at DWords 3-2 (reversed). */
111 nir_intrinsic_set_base(intr
, 0);
112 nir_intrinsic_set_component(intr
, 3 - component
);
113 out_of_bounds
= false;
116 /* gl_TessLevelInner[0] lives at DWord 4. */
117 nir_intrinsic_set_base(intr
, 1);
118 out_of_bounds
= component
> 0;
121 out_of_bounds
= true;
124 unreachable("Bogus tessellation domain");
126 } else if (location
== VARYING_SLOT_TESS_LEVEL_OUTER
) {
127 if (primitive_mode
== GL_ISOLINES
) {
128 /* gl_TessLevelOuter[0..1] lives at DWords 6-7 (in order). */
129 nir_intrinsic_set_base(intr
, 1);
130 nir_intrinsic_set_component(intr
, 2 + nir_intrinsic_component(intr
));
131 out_of_bounds
= component
> 1;
133 /* Triangles use DWords 7-5 (reversed); Quads use 7-4 (reversed) */
134 nir_intrinsic_set_base(intr
, 1);
135 nir_intrinsic_set_component(intr
, 3 - nir_intrinsic_component(intr
));
136 out_of_bounds
= component
== 3 && primitive_mode
== GL_TRIANGLES
;
143 if (nir_intrinsic_infos
[intr
->intrinsic
].has_dest
) {
144 b
->cursor
= nir_before_instr(&intr
->instr
);
145 nir_ssa_def
*undef
= nir_ssa_undef(b
, 1, 32);
146 nir_ssa_def_rewrite_uses(&intr
->dest
.ssa
, nir_src_for_ssa(undef
));
148 nir_instr_remove(&intr
->instr
);
155 remap_patch_urb_offsets(nir_block
*block
, nir_builder
*b
,
156 const struct brw_vue_map
*vue_map
,
157 GLenum tes_primitive_mode
)
159 const bool is_passthrough_tcs
= b
->shader
->info
.name
&&
160 strcmp(b
->shader
->info
.name
, "passthrough") == 0;
162 nir_foreach_instr_safe(instr
, block
) {
163 if (instr
->type
!= nir_instr_type_intrinsic
)
166 nir_intrinsic_instr
*intrin
= nir_instr_as_intrinsic(instr
);
168 gl_shader_stage stage
= b
->shader
->info
.stage
;
170 if ((stage
== MESA_SHADER_TESS_CTRL
&& is_output(intrin
)) ||
171 (stage
== MESA_SHADER_TESS_EVAL
&& is_input(intrin
))) {
173 if (!is_passthrough_tcs
&&
174 remap_tess_levels(b
, intrin
, tes_primitive_mode
))
177 int vue_slot
= vue_map
->varying_to_slot
[intrin
->const_index
[0]];
178 assert(vue_slot
!= -1);
179 intrin
->const_index
[0] = vue_slot
;
181 nir_src
*vertex
= nir_get_io_vertex_index_src(intrin
);
183 nir_const_value
*const_vertex
= nir_src_as_const_value(*vertex
);
185 intrin
->const_index
[0] += const_vertex
->u32
[0] *
186 vue_map
->num_per_vertex_slots
;
188 b
->cursor
= nir_before_instr(&intrin
->instr
);
190 /* Multiply by the number of per-vertex slots. */
191 nir_ssa_def
*vertex_offset
=
193 nir_ssa_for_src(b
, *vertex
, 1),
195 vue_map
->num_per_vertex_slots
));
197 /* Add it to the existing offset */
198 nir_src
*offset
= nir_get_io_offset_src(intrin
);
199 nir_ssa_def
*total_offset
=
200 nir_iadd(b
, vertex_offset
,
201 nir_ssa_for_src(b
, *offset
, 1));
203 nir_instr_rewrite_src(&intrin
->instr
, offset
,
204 nir_src_for_ssa(total_offset
));
213 brw_nir_lower_vs_inputs(nir_shader
*nir
,
214 const uint8_t *vs_attrib_wa_flags
)
216 /* Start with the location of the variable's base. */
217 foreach_list_typed(nir_variable
, var
, node
, &nir
->inputs
) {
218 var
->data
.driver_location
= var
->data
.location
;
221 /* Now use nir_lower_io to walk dereference chains. Attribute arrays are
222 * loaded as one vec4 or dvec4 per element (or matrix column), depending on
223 * whether it is a double-precision type or not.
225 nir_lower_io(nir
, nir_var_shader_in
, type_size_vec4
, 0);
227 /* This pass needs actual constants */
228 nir_opt_constant_folding(nir
);
230 add_const_offset_to_base(nir
, nir_var_shader_in
);
232 brw_nir_apply_attribute_workarounds(nir
, vs_attrib_wa_flags
);
234 /* The last step is to remap VERT_ATTRIB_* to actual registers */
236 /* Whether or not we have any system generated values. gl_DrawID is not
237 * included here as it lives in its own vec4.
239 const bool has_sgvs
=
240 nir
->info
.system_values_read
&
241 (BITFIELD64_BIT(SYSTEM_VALUE_FIRST_VERTEX
) |
242 BITFIELD64_BIT(SYSTEM_VALUE_BASE_INSTANCE
) |
243 BITFIELD64_BIT(SYSTEM_VALUE_VERTEX_ID_ZERO_BASE
) |
244 BITFIELD64_BIT(SYSTEM_VALUE_INSTANCE_ID
));
246 const unsigned num_inputs
= _mesa_bitcount_64(nir
->info
.inputs_read
);
248 nir_foreach_function(function
, nir
) {
253 nir_builder_init(&b
, function
->impl
);
255 nir_foreach_block(block
, function
->impl
) {
256 nir_foreach_instr_safe(instr
, block
) {
257 if (instr
->type
!= nir_instr_type_intrinsic
)
260 nir_intrinsic_instr
*intrin
= nir_instr_as_intrinsic(instr
);
262 switch (intrin
->intrinsic
) {
263 case nir_intrinsic_load_first_vertex
:
264 case nir_intrinsic_load_base_instance
:
265 case nir_intrinsic_load_vertex_id_zero_base
:
266 case nir_intrinsic_load_instance_id
:
267 case nir_intrinsic_load_is_indexed_draw
:
268 case nir_intrinsic_load_draw_id
: {
269 b
.cursor
= nir_after_instr(&intrin
->instr
);
271 /* gl_VertexID and friends are stored by the VF as the last
272 * vertex element. We convert them to load_input intrinsics at
273 * the right location.
275 nir_intrinsic_instr
*load
=
276 nir_intrinsic_instr_create(nir
, nir_intrinsic_load_input
);
277 load
->src
[0] = nir_src_for_ssa(nir_imm_int(&b
, 0));
279 nir_intrinsic_set_base(load
, num_inputs
);
280 switch (intrin
->intrinsic
) {
281 case nir_intrinsic_load_first_vertex
:
282 nir_intrinsic_set_component(load
, 0);
284 case nir_intrinsic_load_base_instance
:
285 nir_intrinsic_set_component(load
, 1);
287 case nir_intrinsic_load_vertex_id_zero_base
:
288 nir_intrinsic_set_component(load
, 2);
290 case nir_intrinsic_load_instance_id
:
291 nir_intrinsic_set_component(load
, 3);
293 case nir_intrinsic_load_draw_id
:
294 case nir_intrinsic_load_is_indexed_draw
:
295 /* gl_DrawID and IsIndexedDraw are stored right after
296 * gl_VertexID and friends if any of them exist.
298 nir_intrinsic_set_base(load
, num_inputs
+ has_sgvs
);
299 if (intrin
->intrinsic
== nir_intrinsic_load_draw_id
)
300 nir_intrinsic_set_component(load
, 0);
302 nir_intrinsic_set_component(load
, 1);
305 unreachable("Invalid system value intrinsic");
308 load
->num_components
= 1;
309 nir_ssa_dest_init(&load
->instr
, &load
->dest
, 1, 32, NULL
);
310 nir_builder_instr_insert(&b
, &load
->instr
);
312 nir_ssa_def_rewrite_uses(&intrin
->dest
.ssa
,
313 nir_src_for_ssa(&load
->dest
.ssa
));
314 nir_instr_remove(&intrin
->instr
);
318 case nir_intrinsic_load_input
: {
319 /* Attributes come in a contiguous block, ordered by their
320 * gl_vert_attrib value. That means we can compute the slot
321 * number for an attribute by masking out the enabled attributes
322 * before it and counting the bits.
324 int attr
= nir_intrinsic_base(intrin
);
325 int slot
= _mesa_bitcount_64(nir
->info
.inputs_read
&
326 BITFIELD64_MASK(attr
));
327 nir_intrinsic_set_base(intrin
, slot
);
332 break; /* Nothing to do */
340 brw_nir_lower_vue_inputs(nir_shader
*nir
,
341 const struct brw_vue_map
*vue_map
)
343 foreach_list_typed(nir_variable
, var
, node
, &nir
->inputs
) {
344 var
->data
.driver_location
= var
->data
.location
;
347 /* Inputs are stored in vec4 slots, so use type_size_vec4(). */
348 nir_lower_io(nir
, nir_var_shader_in
, type_size_vec4
, 0);
350 /* This pass needs actual constants */
351 nir_opt_constant_folding(nir
);
353 add_const_offset_to_base(nir
, nir_var_shader_in
);
355 nir_foreach_function(function
, nir
) {
359 nir_foreach_block(block
, function
->impl
) {
360 nir_foreach_instr(instr
, block
) {
361 if (instr
->type
!= nir_instr_type_intrinsic
)
364 nir_intrinsic_instr
*intrin
= nir_instr_as_intrinsic(instr
);
366 if (intrin
->intrinsic
== nir_intrinsic_load_input
||
367 intrin
->intrinsic
== nir_intrinsic_load_per_vertex_input
) {
368 /* Offset 0 is the VUE header, which contains
369 * VARYING_SLOT_LAYER [.y], VARYING_SLOT_VIEWPORT [.z], and
370 * VARYING_SLOT_PSIZ [.w].
372 int varying
= nir_intrinsic_base(intrin
);
375 case VARYING_SLOT_PSIZ
:
376 nir_intrinsic_set_base(intrin
, 0);
377 nir_intrinsic_set_component(intrin
, 3);
381 vue_slot
= vue_map
->varying_to_slot
[varying
];
382 assert(vue_slot
!= -1);
383 nir_intrinsic_set_base(intrin
, vue_slot
);
393 brw_nir_lower_tes_inputs(nir_shader
*nir
, const struct brw_vue_map
*vue_map
)
395 foreach_list_typed(nir_variable
, var
, node
, &nir
->inputs
) {
396 var
->data
.driver_location
= var
->data
.location
;
399 nir_lower_io(nir
, nir_var_shader_in
, type_size_vec4
, 0);
401 /* This pass needs actual constants */
402 nir_opt_constant_folding(nir
);
404 add_const_offset_to_base(nir
, nir_var_shader_in
);
406 nir_foreach_function(function
, nir
) {
407 if (function
->impl
) {
409 nir_builder_init(&b
, function
->impl
);
410 nir_foreach_block(block
, function
->impl
) {
411 remap_patch_urb_offsets(block
, &b
, vue_map
,
412 nir
->info
.tess
.primitive_mode
);
419 brw_nir_lower_fs_inputs(nir_shader
*nir
,
420 const struct gen_device_info
*devinfo
,
421 const struct brw_wm_prog_key
*key
)
423 foreach_list_typed(nir_variable
, var
, node
, &nir
->inputs
) {
424 var
->data
.driver_location
= var
->data
.location
;
426 /* Apply default interpolation mode.
428 * Everything defaults to smooth except for the legacy GL color
429 * built-in variables, which might be flat depending on API state.
431 if (var
->data
.interpolation
== INTERP_MODE_NONE
) {
432 const bool flat
= key
->flat_shade
&&
433 (var
->data
.location
== VARYING_SLOT_COL0
||
434 var
->data
.location
== VARYING_SLOT_COL1
);
436 var
->data
.interpolation
= flat
? INTERP_MODE_FLAT
437 : INTERP_MODE_SMOOTH
;
440 /* On Ironlake and below, there is only one interpolation mode.
441 * Centroid interpolation doesn't mean anything on this hardware --
442 * there is no multisampling.
444 if (devinfo
->gen
< 6) {
445 var
->data
.centroid
= false;
446 var
->data
.sample
= false;
450 nir_lower_io_options lower_io_options
= 0;
451 if (key
->persample_interp
)
452 lower_io_options
|= nir_lower_io_force_sample_interpolation
;
454 nir_lower_io(nir
, nir_var_shader_in
, type_size_vec4
, lower_io_options
);
456 /* This pass needs actual constants */
457 nir_opt_constant_folding(nir
);
459 add_const_offset_to_base(nir
, nir_var_shader_in
);
463 brw_nir_lower_vue_outputs(nir_shader
*nir
)
465 nir_foreach_variable(var
, &nir
->outputs
) {
466 var
->data
.driver_location
= var
->data
.location
;
469 nir_lower_io(nir
, nir_var_shader_out
, type_size_vec4
, 0);
473 brw_nir_lower_tcs_outputs(nir_shader
*nir
, const struct brw_vue_map
*vue_map
,
474 GLenum tes_primitive_mode
)
476 nir_foreach_variable(var
, &nir
->outputs
) {
477 var
->data
.driver_location
= var
->data
.location
;
480 nir_lower_io(nir
, nir_var_shader_out
, type_size_vec4
, 0);
482 /* This pass needs actual constants */
483 nir_opt_constant_folding(nir
);
485 add_const_offset_to_base(nir
, nir_var_shader_out
);
487 nir_foreach_function(function
, nir
) {
488 if (function
->impl
) {
490 nir_builder_init(&b
, function
->impl
);
491 nir_foreach_block(block
, function
->impl
) {
492 remap_patch_urb_offsets(block
, &b
, vue_map
, tes_primitive_mode
);
499 brw_nir_lower_fs_outputs(nir_shader
*nir
)
501 nir_foreach_variable(var
, &nir
->outputs
) {
502 var
->data
.driver_location
=
503 SET_FIELD(var
->data
.index
, BRW_NIR_FRAG_OUTPUT_INDEX
) |
504 SET_FIELD(var
->data
.location
, BRW_NIR_FRAG_OUTPUT_LOCATION
);
507 nir_lower_io(nir
, nir_var_shader_out
, type_size_dvec4
, 0);
510 #define OPT(pass, ...) ({ \
511 bool this_progress = false; \
512 NIR_PASS(this_progress, nir, pass, ##__VA_ARGS__); \
518 static nir_variable_mode
519 brw_nir_no_indirect_mask(const struct brw_compiler
*compiler
,
520 gl_shader_stage stage
)
522 nir_variable_mode indirect_mask
= 0;
524 if (compiler
->glsl_compiler_options
[stage
].EmitNoIndirectInput
)
525 indirect_mask
|= nir_var_shader_in
;
526 if (compiler
->glsl_compiler_options
[stage
].EmitNoIndirectOutput
)
527 indirect_mask
|= nir_var_shader_out
;
528 if (compiler
->glsl_compiler_options
[stage
].EmitNoIndirectTemp
)
529 indirect_mask
|= nir_var_local
;
531 return indirect_mask
;
535 brw_nir_optimize(nir_shader
*nir
, const struct brw_compiler
*compiler
,
538 nir_variable_mode indirect_mask
=
539 brw_nir_no_indirect_mask(compiler
, nir
->info
.stage
);
544 OPT(nir_lower_vars_to_ssa
);
545 OPT(nir_opt_copy_prop_vars
);
548 OPT(nir_lower_alu_to_scalar
);
554 OPT(nir_lower_phis_to_scalar
);
560 OPT(nir_opt_peephole_select
, 0);
561 OPT(nir_opt_intrinsics
);
562 OPT(nir_opt_algebraic
);
563 OPT(nir_opt_constant_folding
);
564 OPT(nir_opt_dead_cf
);
565 if (OPT(nir_opt_trivial_continues
)) {
566 /* If nir_opt_trivial_continues makes progress, then we need to clean
567 * things up if we want any hope of nir_opt_if or nir_opt_loop_unroll
574 if (nir
->options
->max_unroll_iterations
!= 0) {
575 OPT(nir_opt_loop_unroll
, indirect_mask
);
577 OPT(nir_opt_remove_phis
);
579 OPT(nir_lower_doubles
, nir_lower_drcp
|
586 nir_lower_dround_even
|
595 lower_bit_size_callback(const nir_alu_instr
*alu
, UNUSED
void *data
)
597 assert(alu
->dest
.dest
.is_ssa
);
598 if (alu
->dest
.dest
.ssa
.bit_size
!= 16)
613 /* Does some simple lowering and runs the standard suite of optimizations
615 * This is intended to be called more-or-less directly after you get the
616 * shader out of GLSL or some other source. While it is geared towards i965,
617 * it is not at all generator-specific except for the is_scalar flag. Even
618 * there, it is safe to call with is_scalar = false for a shader that is
619 * intended for the FS backend as long as nir_optimize is called again with
620 * is_scalar = true to scalarize everything prior to code gen.
623 brw_preprocess_nir(const struct brw_compiler
*compiler
, nir_shader
*nir
)
625 const struct gen_device_info
*devinfo
= compiler
->devinfo
;
626 UNUSED
bool progress
; /* Written by OPT */
628 const bool is_scalar
= compiler
->scalar_stage
[nir
->info
.stage
];
630 if (nir
->info
.stage
== MESA_SHADER_GEOMETRY
)
631 OPT(nir_lower_gs_intrinsics
);
633 /* See also brw_nir_trig_workarounds.py */
634 if (compiler
->precise_trig
&&
635 !(devinfo
->gen
>= 10 || devinfo
->is_kabylake
))
636 OPT(brw_nir_apply_trig_workarounds
);
638 static const nir_lower_tex_options tex_options
= {
640 .lower_txf_offset
= true,
641 .lower_rect_offset
= true,
642 .lower_txd_cube_map
= true,
645 OPT(nir_lower_tex
, &tex_options
);
646 OPT(nir_normalize_cubemap_coords
);
648 OPT(nir_lower_global_vars_to_local
);
650 OPT(nir_split_var_copies
);
652 /* Run opt_algebraic before int64 lowering so we can hopefully get rid
653 * of some int64 instructions.
655 OPT(nir_opt_algebraic
);
657 /* Lower int64 instructions before nir_optimize so that loop unrolling
658 * sees their actual cost.
660 nir_lower_int64(nir
, nir_lower_imul64
|
664 nir
= brw_nir_optimize(nir
, compiler
, is_scalar
);
666 /* This needs to be run after the first optimization pass but before we
667 * lower indirect derefs away
669 if (compiler
->supports_shader_constants
) {
670 OPT(nir_opt_large_constants
, NULL
, 32);
673 nir_lower_bit_size(nir
, lower_bit_size_callback
, NULL
);
676 OPT(nir_lower_load_const_to_scalar
);
679 /* Lower a bunch of stuff */
680 OPT(nir_lower_var_copies
);
682 OPT(nir_lower_system_values
);
684 const nir_lower_subgroups_options subgroups_options
= {
685 .subgroup_size
= BRW_SUBGROUP_SIZE
,
686 .ballot_bit_size
= 32,
687 .lower_to_scalar
= true,
688 .lower_subgroup_masks
= true,
689 .lower_vote_trivial
= !is_scalar
,
690 .lower_shuffle
= true,
692 OPT(nir_lower_subgroups
, &subgroups_options
);
694 OPT(nir_lower_clip_cull_distance_arrays
);
696 nir_variable_mode indirect_mask
=
697 brw_nir_no_indirect_mask(compiler
, nir
->info
.stage
);
698 nir_lower_indirect_derefs(nir
, indirect_mask
);
700 /* Get rid of split copies */
701 nir
= brw_nir_optimize(nir
, compiler
, is_scalar
);
703 OPT(nir_remove_dead_variables
, nir_var_local
);
709 brw_nir_link_shaders(const struct brw_compiler
*compiler
,
710 nir_shader
**producer
, nir_shader
**consumer
)
712 nir_lower_io_arrays_to_elements(*producer
, *consumer
);
713 nir_validate_shader(*producer
);
714 nir_validate_shader(*consumer
);
716 NIR_PASS_V(*producer
, nir_remove_dead_variables
, nir_var_shader_out
);
717 NIR_PASS_V(*consumer
, nir_remove_dead_variables
, nir_var_shader_in
);
719 if (nir_remove_unused_varyings(*producer
, *consumer
)) {
720 NIR_PASS_V(*producer
, nir_lower_global_vars_to_local
);
721 NIR_PASS_V(*consumer
, nir_lower_global_vars_to_local
);
723 /* The backend might not be able to handle indirects on
724 * temporaries so we need to lower indirects on any of the
725 * varyings we have demoted here.
727 NIR_PASS_V(*producer
, nir_lower_indirect_derefs
,
728 brw_nir_no_indirect_mask(compiler
, (*producer
)->info
.stage
));
729 NIR_PASS_V(*consumer
, nir_lower_indirect_derefs
,
730 brw_nir_no_indirect_mask(compiler
, (*consumer
)->info
.stage
));
732 const bool p_is_scalar
=
733 compiler
->scalar_stage
[(*producer
)->info
.stage
];
734 *producer
= brw_nir_optimize(*producer
, compiler
, p_is_scalar
);
736 const bool c_is_scalar
=
737 compiler
->scalar_stage
[(*consumer
)->info
.stage
];
738 *consumer
= brw_nir_optimize(*consumer
, compiler
, c_is_scalar
);
742 /* Prepare the given shader for codegen
744 * This function is intended to be called right before going into the actual
745 * backend and is highly backend-specific. Also, once this function has been
746 * called on a shader, it will no longer be in SSA form so most optimizations
750 brw_postprocess_nir(nir_shader
*nir
, const struct brw_compiler
*compiler
,
753 const struct gen_device_info
*devinfo
= compiler
->devinfo
;
755 (INTEL_DEBUG
& intel_debug_flag_for_shader_stage(nir
->info
.stage
));
757 UNUSED
bool progress
; /* Written by OPT */
762 OPT(nir_opt_algebraic_before_ffma
);
765 nir
= brw_nir_optimize(nir
, compiler
, is_scalar
);
767 if (devinfo
->gen
>= 6) {
768 /* Try and fuse multiply-adds */
769 OPT(brw_nir_opt_peephole_ffma
);
772 OPT(nir_opt_algebraic_late
);
774 OPT(nir_lower_to_source_mods
);
777 OPT(nir_opt_move_comparisons
);
779 OPT(nir_lower_locals_to_regs
);
781 if (unlikely(debug_enabled
)) {
782 /* Re-index SSA defs so we print more sensible numbers. */
783 nir_foreach_function(function
, nir
) {
785 nir_index_ssa_defs(function
->impl
);
788 fprintf(stderr
, "NIR (SSA form) for %s shader:\n",
789 _mesa_shader_stage_to_string(nir
->info
.stage
));
790 nir_print_shader(nir
, stderr
);
793 OPT(nir_convert_from_ssa
, true);
796 OPT(nir_move_vec_src_uses_to_dest
);
797 OPT(nir_lower_vec_to_movs
);
802 /* This is the last pass we run before we start emitting stuff. It
803 * determines when we need to insert boolean resolves on Gen <= 5. We
804 * run it last because it stashes data in instr->pass_flags and we don't
805 * want that to be squashed by other NIR passes.
807 if (devinfo
->gen
<= 5)
808 brw_nir_analyze_boolean_resolves(nir
);
812 if (unlikely(debug_enabled
)) {
813 fprintf(stderr
, "NIR (final form) for %s shader:\n",
814 _mesa_shader_stage_to_string(nir
->info
.stage
));
815 nir_print_shader(nir
, stderr
);
822 brw_nir_apply_sampler_key(nir_shader
*nir
,
823 const struct brw_compiler
*compiler
,
824 const struct brw_sampler_prog_key_data
*key_tex
,
827 const struct gen_device_info
*devinfo
= compiler
->devinfo
;
828 nir_lower_tex_options tex_options
= { 0 };
830 /* Iron Lake and prior require lowering of all rectangle textures */
831 if (devinfo
->gen
< 6)
832 tex_options
.lower_rect
= true;
834 /* Prior to Broadwell, our hardware can't actually do GL_CLAMP */
835 if (devinfo
->gen
< 8) {
836 tex_options
.saturate_s
= key_tex
->gl_clamp_mask
[0];
837 tex_options
.saturate_t
= key_tex
->gl_clamp_mask
[1];
838 tex_options
.saturate_r
= key_tex
->gl_clamp_mask
[2];
841 /* Prior to Haswell, we have to fake texture swizzle */
842 for (unsigned s
= 0; s
< MAX_SAMPLERS
; s
++) {
843 if (key_tex
->swizzles
[s
] == SWIZZLE_NOOP
)
846 tex_options
.swizzle_result
|= (1 << s
);
847 for (unsigned c
= 0; c
< 4; c
++)
848 tex_options
.swizzles
[s
][c
] = GET_SWZ(key_tex
->swizzles
[s
], c
);
851 /* Prior to Haswell, we have to lower gradients on shadow samplers */
852 tex_options
.lower_txd_shadow
= devinfo
->gen
< 8 && !devinfo
->is_haswell
;
854 tex_options
.lower_y_uv_external
= key_tex
->y_uv_image_mask
;
855 tex_options
.lower_y_u_v_external
= key_tex
->y_u_v_image_mask
;
856 tex_options
.lower_yx_xuxv_external
= key_tex
->yx_xuxv_image_mask
;
857 tex_options
.lower_xy_uxvx_external
= key_tex
->xy_uxvx_image_mask
;
859 if (nir_lower_tex(nir
, &tex_options
)) {
860 nir_validate_shader(nir
);
861 nir
= brw_nir_optimize(nir
, compiler
, is_scalar
);
868 brw_type_for_nir_type(const struct gen_device_info
*devinfo
, nir_alu_type type
)
872 case nir_type_uint32
:
873 return BRW_REGISTER_TYPE_UD
;
876 case nir_type_bool32
:
878 return BRW_REGISTER_TYPE_D
;
880 case nir_type_float32
:
881 return BRW_REGISTER_TYPE_F
;
882 case nir_type_float16
:
883 return BRW_REGISTER_TYPE_HF
;
884 case nir_type_float64
:
885 return BRW_REGISTER_TYPE_DF
;
887 return devinfo
->gen
< 8 ? BRW_REGISTER_TYPE_DF
: BRW_REGISTER_TYPE_Q
;
888 case nir_type_uint64
:
889 return devinfo
->gen
< 8 ? BRW_REGISTER_TYPE_DF
: BRW_REGISTER_TYPE_UQ
;
891 return BRW_REGISTER_TYPE_W
;
892 case nir_type_uint16
:
893 return BRW_REGISTER_TYPE_UW
;
895 return BRW_REGISTER_TYPE_B
;
897 return BRW_REGISTER_TYPE_UB
;
899 unreachable("unknown type");
902 return BRW_REGISTER_TYPE_F
;
905 /* Returns the glsl_base_type corresponding to a nir_alu_type.
906 * This is used by both brw_vec4_nir and brw_fs_nir.
909 brw_glsl_base_type_for_nir_type(nir_alu_type type
)
913 case nir_type_float32
:
914 return GLSL_TYPE_FLOAT
;
916 case nir_type_float16
:
917 return GLSL_TYPE_FLOAT16
;
919 case nir_type_float64
:
920 return GLSL_TYPE_DOUBLE
;
924 return GLSL_TYPE_INT
;
927 case nir_type_uint32
:
928 return GLSL_TYPE_UINT
;
931 return GLSL_TYPE_INT16
;
933 case nir_type_uint16
:
934 return GLSL_TYPE_UINT16
;
937 unreachable("bad type");