2 * Copyright © 2015 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
28 #include "compiler/nir/nir.h"
29 #include "brw_compiler.h"
35 int type_size_vec4(const struct glsl_type
*type
, bool bindless
);
36 int type_size_dvec4(const struct glsl_type
*type
, bool bindless
);
39 type_size_scalar_bytes(const struct glsl_type
*type
, bool bindless
)
41 return glsl_count_dword_slots(type
, bindless
) * 4;
45 type_size_vec4_bytes(const struct glsl_type
*type
, bool bindless
)
47 return type_size_vec4(type
, bindless
) * 16;
50 /* Flags set in the instr->pass_flags field by i965 analysis passes */
52 BRW_NIR_NON_BOOLEAN
= 0x0,
54 /* Indicates that the given instruction's destination is a boolean
55 * value but that it needs to be resolved before it can be used.
56 * On Gen <= 5, CMP instructions return a 32-bit value where the bottom
57 * bit represents the actual true/false value of the compare and the top
58 * 31 bits are undefined. In order to use this value, we have to do a
59 * "resolve" operation by replacing the value of the CMP with -(x & 1)
60 * to sign-extend the bottom bit to 0/~0.
62 BRW_NIR_BOOLEAN_NEEDS_RESOLVE
= 0x1,
64 /* Indicates that the given instruction's destination is a boolean
65 * value that has intentionally been left unresolved. Not all boolean
66 * values need to be resolved immediately. For instance, if we have
72 * We don't have to resolve the result of the two CMP instructions
73 * immediately because the AND still does an AND of the bottom bits.
74 * Instead, we can save ourselves instructions by delaying the resolve
75 * until after the AND. The result of the two CMP instructions is left
76 * as BRW_NIR_BOOLEAN_UNRESOLVED.
78 BRW_NIR_BOOLEAN_UNRESOLVED
= 0x2,
80 /* Indicates a that the given instruction's destination is a boolean
81 * value that does not need a resolve. For instance, if you AND two
82 * values that are BRW_NIR_BOOLEAN_NEEDS_RESOLVE then we know that both
83 * values will be 0/~0 before we get them and the result of the AND is
84 * also guaranteed to be 0/~0 and does not need a resolve.
86 BRW_NIR_BOOLEAN_NO_RESOLVE
= 0x3,
88 /* A mask to mask the boolean status values off of instr->pass_flags */
89 BRW_NIR_BOOLEAN_MASK
= 0x3,
92 void brw_nir_analyze_boolean_resolves(nir_shader
*nir
);
94 void brw_preprocess_nir(const struct brw_compiler
*compiler
,
96 const nir_shader
*softfp64
);
99 brw_nir_link_shaders(const struct brw_compiler
*compiler
,
100 nir_shader
*producer
, nir_shader
*consumer
);
102 bool brw_nir_lower_cs_intrinsics(nir_shader
*nir
,
103 unsigned dispatch_width
);
104 void brw_nir_lower_alpha_to_coverage(nir_shader
*shader
);
105 void brw_nir_lower_legacy_clipping(nir_shader
*nir
,
106 int nr_userclip_plane_consts
,
107 struct brw_stage_prog_data
*prog_data
);
108 void brw_nir_lower_vs_inputs(nir_shader
*nir
,
109 const uint8_t *vs_attrib_wa_flags
);
110 void brw_nir_lower_vue_inputs(nir_shader
*nir
,
111 const struct brw_vue_map
*vue_map
);
112 void brw_nir_lower_tes_inputs(nir_shader
*nir
, const struct brw_vue_map
*vue
);
113 void brw_nir_lower_fs_inputs(nir_shader
*nir
,
114 const struct gen_device_info
*devinfo
,
115 const struct brw_wm_prog_key
*key
);
116 void brw_nir_lower_vue_outputs(nir_shader
*nir
);
117 void brw_nir_lower_tcs_outputs(nir_shader
*nir
, const struct brw_vue_map
*vue
,
118 GLenum tes_primitive_mode
);
119 void brw_nir_lower_fs_outputs(nir_shader
*nir
);
121 bool brw_nir_lower_conversions(nir_shader
*nir
);
123 bool brw_nir_lower_image_load_store(nir_shader
*nir
,
124 const struct gen_device_info
*devinfo
);
125 void brw_nir_rewrite_image_intrinsic(nir_intrinsic_instr
*intrin
,
127 void brw_nir_rewrite_bindless_image_intrinsic(nir_intrinsic_instr
*intrin
,
128 nir_ssa_def
*handle
);
130 bool brw_nir_lower_mem_access_bit_sizes(nir_shader
*shader
,
131 const struct gen_device_info
*devinfo
);
133 void brw_postprocess_nir(nir_shader
*nir
,
134 const struct brw_compiler
*compiler
,
137 bool brw_nir_clamp_image_1d_2d_array_sizes(nir_shader
*shader
);
139 bool brw_nir_apply_attribute_workarounds(nir_shader
*nir
,
140 const uint8_t *attrib_wa_flags
);
142 bool brw_nir_apply_trig_workarounds(nir_shader
*nir
);
144 void brw_nir_apply_tcs_quads_workaround(nir_shader
*nir
);
146 void brw_nir_apply_key(nir_shader
*nir
,
147 const struct brw_compiler
*compiler
,
148 const struct brw_base_prog_key
*key
,
149 unsigned max_subgroup_size
,
152 enum brw_conditional_mod
brw_cmod_for_nir_comparison(nir_op op
);
153 uint32_t brw_aop_for_nir_intrinsic(const nir_intrinsic_instr
*atomic
);
154 enum brw_reg_type
brw_type_for_nir_type(const struct gen_device_info
*devinfo
,
157 enum glsl_base_type
brw_glsl_base_type_for_nir_type(nir_alu_type type
);
159 void brw_nir_setup_glsl_uniforms(void *mem_ctx
, nir_shader
*shader
,
160 const struct gl_program
*prog
,
161 struct brw_stage_prog_data
*stage_prog_data
,
164 void brw_nir_setup_arb_uniforms(void *mem_ctx
, nir_shader
*shader
,
165 struct gl_program
*prog
,
166 struct brw_stage_prog_data
*stage_prog_data
);
168 void brw_nir_lower_gl_images(nir_shader
*shader
,
169 const struct gl_program
*prog
);
171 void brw_nir_analyze_ubo_ranges(const struct brw_compiler
*compiler
,
173 const struct brw_vs_prog_key
*vs_key
,
174 struct brw_ubo_range out_ranges
[4]);
176 bool brw_nir_opt_peephole_ffma(nir_shader
*shader
);
178 void brw_nir_optimize(nir_shader
*nir
,
179 const struct brw_compiler
*compiler
,
183 nir_shader
*brw_nir_create_passthrough_tcs(void *mem_ctx
,
184 const struct brw_compiler
*compiler
,
185 const nir_shader_compiler_options
*options
,
186 const struct brw_tcs_prog_key
*key
);
188 #define BRW_NIR_FRAG_OUTPUT_INDEX_SHIFT 0
189 #define BRW_NIR_FRAG_OUTPUT_INDEX_MASK INTEL_MASK(0, 0)
190 #define BRW_NIR_FRAG_OUTPUT_LOCATION_SHIFT 1
191 #define BRW_NIR_FRAG_OUTPUT_LOCATION_MASK INTEL_MASK(31, 1)
197 #endif /* BRW_NIR_H */