2 * Copyright © 2015 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
28 #include "compiler/nir/nir.h"
29 #include "brw_compiler.h"
35 int type_size_scalar(const struct glsl_type
*type
, bool bindless
);
36 int type_size_vec4(const struct glsl_type
*type
, bool bindless
);
37 int type_size_dvec4(const struct glsl_type
*type
, bool bindless
);
40 type_size_scalar_bytes(const struct glsl_type
*type
, bool bindless
)
42 return type_size_scalar(type
, bindless
) * 4;
46 type_size_vec4_bytes(const struct glsl_type
*type
, bool bindless
)
48 return type_size_vec4(type
, bindless
) * 16;
51 /* Flags set in the instr->pass_flags field by i965 analysis passes */
53 BRW_NIR_NON_BOOLEAN
= 0x0,
55 /* Indicates that the given instruction's destination is a boolean
56 * value but that it needs to be resolved before it can be used.
57 * On Gen <= 5, CMP instructions return a 32-bit value where the bottom
58 * bit represents the actual true/false value of the compare and the top
59 * 31 bits are undefined. In order to use this value, we have to do a
60 * "resolve" operation by replacing the value of the CMP with -(x & 1)
61 * to sign-extend the bottom bit to 0/~0.
63 BRW_NIR_BOOLEAN_NEEDS_RESOLVE
= 0x1,
65 /* Indicates that the given instruction's destination is a boolean
66 * value that has intentionally been left unresolved. Not all boolean
67 * values need to be resolved immediately. For instance, if we have
73 * We don't have to resolve the result of the two CMP instructions
74 * immediately because the AND still does an AND of the bottom bits.
75 * Instead, we can save ourselves instructions by delaying the resolve
76 * until after the AND. The result of the two CMP instructions is left
77 * as BRW_NIR_BOOLEAN_UNRESOLVED.
79 BRW_NIR_BOOLEAN_UNRESOLVED
= 0x2,
81 /* Indicates a that the given instruction's destination is a boolean
82 * value that does not need a resolve. For instance, if you AND two
83 * values that are BRW_NIR_BOOLEAN_NEEDS_RESOLVE then we know that both
84 * values will be 0/~0 before we get them and the result of the AND is
85 * also guaranteed to be 0/~0 and does not need a resolve.
87 BRW_NIR_BOOLEAN_NO_RESOLVE
= 0x3,
89 /* A mask to mask the boolean status values off of instr->pass_flags */
90 BRW_NIR_BOOLEAN_MASK
= 0x3,
93 void brw_nir_analyze_boolean_resolves(nir_shader
*nir
);
95 nir_shader
*brw_preprocess_nir(const struct brw_compiler
*compiler
,
97 const nir_shader
*softfp64
);
100 brw_nir_link_shaders(const struct brw_compiler
*compiler
,
101 nir_shader
**producer
, nir_shader
**consumer
);
103 bool brw_nir_lower_cs_intrinsics(nir_shader
*nir
,
104 unsigned dispatch_width
);
105 void brw_nir_lower_vs_inputs(nir_shader
*nir
,
106 const uint8_t *vs_attrib_wa_flags
);
107 void brw_nir_lower_vue_inputs(nir_shader
*nir
,
108 const struct brw_vue_map
*vue_map
);
109 void brw_nir_lower_tes_inputs(nir_shader
*nir
, const struct brw_vue_map
*vue
);
110 void brw_nir_lower_fs_inputs(nir_shader
*nir
,
111 const struct gen_device_info
*devinfo
,
112 const struct brw_wm_prog_key
*key
);
113 void brw_nir_lower_vue_outputs(nir_shader
*nir
);
114 void brw_nir_lower_tcs_outputs(nir_shader
*nir
, const struct brw_vue_map
*vue
,
115 GLenum tes_primitive_mode
);
116 void brw_nir_lower_fs_outputs(nir_shader
*nir
);
118 bool brw_nir_lower_image_load_store(nir_shader
*nir
,
119 const struct gen_device_info
*devinfo
);
120 void brw_nir_rewrite_image_intrinsic(nir_intrinsic_instr
*intrin
,
123 bool brw_nir_lower_mem_access_bit_sizes(nir_shader
*shader
);
125 nir_shader
*brw_postprocess_nir(nir_shader
*nir
,
126 const struct brw_compiler
*compiler
,
129 bool brw_nir_apply_attribute_workarounds(nir_shader
*nir
,
130 const uint8_t *attrib_wa_flags
);
132 bool brw_nir_apply_trig_workarounds(nir_shader
*nir
);
134 void brw_nir_apply_tcs_quads_workaround(nir_shader
*nir
);
136 nir_shader
*brw_nir_apply_sampler_key(nir_shader
*nir
,
137 const struct brw_compiler
*compiler
,
138 const struct brw_sampler_prog_key_data
*key
,
141 enum brw_reg_type
brw_type_for_nir_type(const struct gen_device_info
*devinfo
,
144 enum glsl_base_type
brw_glsl_base_type_for_nir_type(nir_alu_type type
);
146 void brw_nir_setup_glsl_uniforms(void *mem_ctx
, nir_shader
*shader
,
147 const struct gl_program
*prog
,
148 struct brw_stage_prog_data
*stage_prog_data
,
151 void brw_nir_setup_arb_uniforms(void *mem_ctx
, nir_shader
*shader
,
152 struct gl_program
*prog
,
153 struct brw_stage_prog_data
*stage_prog_data
);
155 void brw_nir_lower_gl_images(nir_shader
*shader
,
156 const struct gl_program
*prog
);
158 void brw_nir_analyze_ubo_ranges(const struct brw_compiler
*compiler
,
160 const struct brw_vs_prog_key
*vs_key
,
161 struct brw_ubo_range out_ranges
[4]);
163 bool brw_nir_opt_peephole_ffma(nir_shader
*shader
);
165 nir_shader
*brw_nir_optimize(nir_shader
*nir
,
166 const struct brw_compiler
*compiler
,
170 nir_shader
*brw_nir_create_passthrough_tcs(void *mem_ctx
,
171 const struct brw_compiler
*compiler
,
172 const nir_shader_compiler_options
*options
,
173 const struct brw_tcs_prog_key
*key
);
175 #define BRW_NIR_FRAG_OUTPUT_INDEX_SHIFT 0
176 #define BRW_NIR_FRAG_OUTPUT_INDEX_MASK INTEL_MASK(0, 0)
177 #define BRW_NIR_FRAG_OUTPUT_LOCATION_SHIFT 1
178 #define BRW_NIR_FRAG_OUTPUT_LOCATION_MASK INTEL_MASK(31, 1)
184 #endif /* BRW_NIR_H */