2 * Copyright © 2018 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
27 #include "compiler/nir/nir_builder.h"
28 #include "compiler/nir/nir_format_convert.h"
31 _load_image_param(nir_builder
*b
, nir_deref_instr
*deref
, unsigned offset
)
33 nir_intrinsic_instr
*load
=
34 nir_intrinsic_instr_create(b
->shader
,
35 nir_intrinsic_image_deref_load_param_intel
);
36 load
->src
[0] = nir_src_for_ssa(&deref
->dest
.ssa
);
37 nir_intrinsic_set_base(load
, offset
/ 4);
40 case BRW_IMAGE_PARAM_OFFSET_OFFSET
:
41 case BRW_IMAGE_PARAM_SWIZZLING_OFFSET
:
42 load
->num_components
= 2;
44 case BRW_IMAGE_PARAM_TILING_OFFSET
:
45 case BRW_IMAGE_PARAM_SIZE_OFFSET
:
46 load
->num_components
= 3;
48 case BRW_IMAGE_PARAM_STRIDE_OFFSET
:
49 load
->num_components
= 4;
52 unreachable("Invalid param offset");
54 nir_ssa_dest_init(&load
->instr
, &load
->dest
,
55 load
->num_components
, 32, NULL
);
57 nir_builder_instr_insert(b
, &load
->instr
);
58 return &load
->dest
.ssa
;
61 #define load_image_param(b, d, o) \
62 _load_image_param(b, d, BRW_IMAGE_PARAM_##o##_OFFSET)
65 image_coord_is_in_bounds(nir_builder
*b
, nir_deref_instr
*deref
,
68 nir_ssa_def
*size
= load_image_param(b
, deref
, SIZE
);
69 nir_ssa_def
*cmp
= nir_ilt(b
, coord
, size
);
71 unsigned coord_comps
= glsl_get_sampler_coordinate_components(deref
->type
);
72 nir_ssa_def
*in_bounds
= nir_imm_true(b
);
73 for (unsigned i
= 0; i
< coord_comps
; i
++)
74 in_bounds
= nir_iand(b
, in_bounds
, nir_channel(b
, cmp
, i
));
79 /** Calculate the offset in memory of the texel given by \p coord.
81 * This is meant to be used with untyped surface messages to access a tiled
82 * surface, what involves taking into account the tiling and swizzling modes
83 * of the surface manually so it will hopefully not happen very often.
85 * The tiling algorithm implemented here matches either the X or Y tiling
86 * layouts supported by the hardware depending on the tiling coefficients
87 * passed to the program as uniforms. See Volume 1 Part 2 Section 4.5
88 * "Address Tiling Function" of the IVB PRM for an in-depth explanation of
89 * the hardware tiling format.
92 image_address(nir_builder
*b
, const struct gen_device_info
*devinfo
,
93 nir_deref_instr
*deref
, nir_ssa_def
*coord
)
95 if (glsl_get_sampler_dim(deref
->type
) == GLSL_SAMPLER_DIM_1D
&&
96 glsl_sampler_type_is_array(deref
->type
)) {
97 /* It's easier if 1D arrays are treated like 2D arrays */
98 coord
= nir_vec3(b
, nir_channel(b
, coord
, 0),
100 nir_channel(b
, coord
, 1));
102 unsigned dims
= glsl_get_sampler_coordinate_components(deref
->type
);
103 coord
= nir_channels(b
, coord
, (1 << dims
) - 1);
106 nir_ssa_def
*offset
= load_image_param(b
, deref
, OFFSET
);
107 nir_ssa_def
*tiling
= load_image_param(b
, deref
, TILING
);
108 nir_ssa_def
*stride
= load_image_param(b
, deref
, STRIDE
);
110 /* Shift the coordinates by the fixed surface offset. It may be non-zero
111 * if the image is a single slice of a higher-dimensional surface, or if a
112 * non-zero mipmap level of the surface is bound to the pipeline. The
113 * offset needs to be applied here rather than at surface state set-up time
114 * because the desired slice-level may start mid-tile, so simply shifting
115 * the surface base address wouldn't give a well-formed tiled surface in
118 nir_ssa_def
*xypos
= (coord
->num_components
== 1) ?
119 nir_vec2(b
, coord
, nir_imm_int(b
, 0)) :
120 nir_channels(b
, coord
, 0x3);
121 xypos
= nir_iadd(b
, xypos
, offset
);
123 /* The layout of 3-D textures in memory is sort-of like a tiling
124 * format. At each miplevel, the slices are arranged in rows of
125 * 2^level slices per row. The slice row is stored in tmp.y and
126 * the slice within the row is stored in tmp.x.
128 * The layout of 2-D array textures and cubemaps is much simpler:
129 * Depending on whether the ARYSPC_LOD0 layout is in use it will be
130 * stored in memory as an array of slices, each one being a 2-D
131 * arrangement of miplevels, or as a 2D arrangement of miplevels,
132 * each one being an array of slices. In either case the separation
133 * between slices of the same LOD is equal to the qpitch value
134 * provided as stride.w.
136 * This code can be made to handle either 2D arrays and 3D textures
137 * by passing in the miplevel as tile.z for 3-D textures and 0 in
138 * tile.z for 2-D array textures.
140 * See Volume 1 Part 1 of the Gen7 PRM, sections 6.18.4.7 "Surface
141 * Arrays" and 6.18.6 "3D Surfaces" for a more extensive discussion
142 * of the hardware 3D texture and 2D array layouts.
144 if (coord
->num_components
> 2) {
145 /* Decompose z into a major (tmp.y) and a minor (tmp.x)
148 nir_ssa_def
*z
= nir_channel(b
, coord
, 2);
149 nir_ssa_def
*z_x
= nir_ubfe(b
, z
, nir_imm_int(b
, 0),
150 nir_channel(b
, tiling
, 2));
151 nir_ssa_def
*z_y
= nir_ushr(b
, z
, nir_channel(b
, tiling
, 2));
153 /* Take into account the horizontal (tmp.x) and vertical (tmp.y)
156 xypos
= nir_iadd(b
, xypos
, nir_imul(b
, nir_vec2(b
, z_x
, z_y
),
157 nir_channels(b
, stride
, 0xc)));
161 if (coord
->num_components
> 1) {
162 /* Calculate the major/minor x and y indices. In order to
163 * accommodate both X and Y tiling, the Y-major tiling format is
164 * treated as being a bunch of narrow X-tiles placed next to each
165 * other. This means that the tile width for Y-tiling is actually
166 * the width of one sub-column of the Y-major tile where each 4K
167 * tile has 8 512B sub-columns.
169 * The major Y value is the row of tiles in which the pixel lives.
170 * The major X value is the tile sub-column in which the pixel
171 * lives; for X tiling, this is the same as the tile column, for Y
172 * tiling, each tile has 8 sub-columns. The minor X and Y indices
173 * are the position within the sub-column.
176 /* Calculate the minor x and y indices. */
177 nir_ssa_def
*minor
= nir_ubfe(b
, xypos
, nir_imm_int(b
, 0),
178 nir_channels(b
, tiling
, 0x3));
179 nir_ssa_def
*major
= nir_ushr(b
, xypos
, nir_channels(b
, tiling
, 0x3));
181 /* Calculate the texel index from the start of the tile row and the
182 * vertical coordinate of the row.
184 * tmp.x = (major.x << tile.y << tile.x) +
185 * (minor.y << tile.x) + minor.x
186 * tmp.y = major.y << tile.y
188 nir_ssa_def
*idx_x
, *idx_y
;
189 idx_x
= nir_ishl(b
, nir_channel(b
, major
, 0), nir_channel(b
, tiling
, 1));
190 idx_x
= nir_iadd(b
, idx_x
, nir_channel(b
, minor
, 1));
191 idx_x
= nir_ishl(b
, idx_x
, nir_channel(b
, tiling
, 0));
192 idx_x
= nir_iadd(b
, idx_x
, nir_channel(b
, minor
, 0));
193 idx_y
= nir_ishl(b
, nir_channel(b
, major
, 1), nir_channel(b
, tiling
, 1));
195 /* Add it to the start of the tile row. */
197 idx
= nir_imul(b
, idx_y
, nir_channel(b
, stride
, 1));
198 idx
= nir_iadd(b
, idx
, idx_x
);
200 /* Multiply by the Bpp value. */
201 addr
= nir_imul(b
, idx
, nir_channel(b
, stride
, 0));
203 if (devinfo
->gen
< 8 && !devinfo
->is_baytrail
) {
204 /* Take into account the two dynamically specified shifts. Both are
205 * used to implement swizzling of X-tiled surfaces. For Y-tiled
206 * surfaces only one bit needs to be XOR-ed with bit 6 of the memory
207 * address, so a swz value of 0xff (actually interpreted as 31 by the
208 * hardware) will be provided to cause the relevant bit of tmp.y to
209 * be zero and turn the first XOR into the identity. For linear
210 * surfaces or platforms lacking address swizzling both shifts will
211 * be 0xff causing the relevant bits of both tmp.x and .y to be zero,
212 * what effectively disables swizzling.
214 nir_ssa_def
*swizzle
= load_image_param(b
, deref
, SWIZZLING
);
215 nir_ssa_def
*shift0
= nir_ushr(b
, addr
, nir_channel(b
, swizzle
, 0));
216 nir_ssa_def
*shift1
= nir_ushr(b
, addr
, nir_channel(b
, swizzle
, 1));
218 /* XOR tmp.x and tmp.y with bit 6 of the memory address. */
219 nir_ssa_def
*bit
= nir_iand(b
, nir_ixor(b
, shift0
, shift1
),
220 nir_imm_int(b
, 1 << 6));
221 addr
= nir_ixor(b
, addr
, bit
);
224 /* Multiply by the Bpp/stride value. Note that the addr.y may be
225 * non-zero even if the image is one-dimensional because a vertical
226 * offset may have been applied above to select a non-zero slice or
227 * level of a higher-dimensional texture.
230 idx
= nir_imul(b
, nir_channel(b
, xypos
, 1), nir_channel(b
, stride
, 1));
231 idx
= nir_iadd(b
, nir_channel(b
, xypos
, 0), idx
);
232 addr
= nir_imul(b
, idx
, nir_channel(b
, stride
, 0));
239 const struct isl_format_layout
*fmtl
;
244 static struct format_info
245 get_format_info(enum isl_format fmt
)
247 const struct isl_format_layout
*fmtl
= isl_format_get_layout(fmt
);
249 return (struct format_info
) {
251 .chans
= isl_format_get_num_channels(fmt
),
253 fmtl
->channels
.r
.bits
,
254 fmtl
->channels
.g
.bits
,
255 fmtl
->channels
.b
.bits
,
256 fmtl
->channels
.a
.bits
262 convert_color_for_load(nir_builder
*b
, const struct gen_device_info
*devinfo
,
264 enum isl_format image_fmt
, enum isl_format lower_fmt
,
265 unsigned dest_components
)
267 if (image_fmt
== lower_fmt
)
270 if (image_fmt
== ISL_FORMAT_R11G11B10_FLOAT
) {
271 assert(lower_fmt
== ISL_FORMAT_R32_UINT
);
272 color
= nir_format_unpack_11f11f10f(b
, color
);
276 struct format_info image
= get_format_info(image_fmt
);
277 struct format_info lower
= get_format_info(lower_fmt
);
279 const bool needs_sign_extension
=
280 isl_format_has_snorm_channel(image_fmt
) ||
281 isl_format_has_sint_channel(image_fmt
);
283 /* We only check the red channel to detect if we need to pack/unpack */
284 assert(image
.bits
[0] != lower
.bits
[0] ||
285 memcmp(image
.bits
, lower
.bits
, sizeof(image
.bits
)) == 0);
287 if (image
.bits
[0] != lower
.bits
[0] && lower_fmt
== ISL_FORMAT_R32_UINT
) {
288 if (needs_sign_extension
)
289 color
= nir_format_unpack_sint(b
, color
, image
.bits
, image
.chans
);
291 color
= nir_format_unpack_uint(b
, color
, image
.bits
, image
.chans
);
293 /* All these formats are homogeneous */
294 for (unsigned i
= 1; i
< image
.chans
; i
++)
295 assert(image
.bits
[i
] == image
.bits
[0]);
297 /* On IVB, we rely on the undocumented behavior that typed reads from
298 * surfaces of the unsupported R8 and R16 formats return useful data in
299 * their least significant bits. However, the data in the high bits is
300 * garbage so we have to discard it.
302 if (devinfo
->gen
== 7 && !devinfo
->is_haswell
&&
303 (lower_fmt
== ISL_FORMAT_R16_UINT
||
304 lower_fmt
== ISL_FORMAT_R8_UINT
))
305 color
= nir_format_mask_uvec(b
, color
, lower
.bits
);
307 if (image
.bits
[0] != lower
.bits
[0]) {
308 color
= nir_format_bitcast_uvec_unmasked(b
, color
, lower
.bits
[0],
312 if (needs_sign_extension
)
313 color
= nir_format_sign_extend_ivec(b
, color
, image
.bits
);
316 switch (image
.fmtl
->channels
.r
.type
) {
318 assert(isl_format_has_uint_channel(lower_fmt
));
319 color
= nir_format_unorm_to_float(b
, color
, image
.bits
);
323 assert(isl_format_has_uint_channel(lower_fmt
));
324 color
= nir_format_snorm_to_float(b
, color
, image
.bits
);
328 if (image
.bits
[0] == 16)
329 color
= nir_unpack_half_2x16_split_x(b
, color
);
337 unreachable("Invalid image channel type");
341 assert(dest_components
== 1 || dest_components
== 4);
342 assert(color
->num_components
<= dest_components
);
343 if (color
->num_components
== dest_components
)
346 nir_ssa_def
*comps
[4];
347 for (unsigned i
= 0; i
< color
->num_components
; i
++)
348 comps
[i
] = nir_channel(b
, color
, i
);
350 for (unsigned i
= color
->num_components
; i
< 3; i
++)
351 comps
[i
] = nir_imm_int(b
, 0);
353 if (color
->num_components
< 4) {
354 if (isl_format_has_int_channel(image_fmt
))
355 comps
[3] = nir_imm_int(b
, 1);
357 comps
[3] = nir_imm_float(b
, 1);
360 return nir_vec(b
, comps
, dest_components
);
364 lower_image_load_instr(nir_builder
*b
,
365 const struct gen_device_info
*devinfo
,
366 nir_intrinsic_instr
*intrin
)
368 nir_deref_instr
*deref
= nir_src_as_deref(intrin
->src
[0]);
369 nir_variable
*var
= nir_deref_instr_get_variable(deref
);
370 const enum isl_format image_fmt
=
371 isl_format_for_pipe_format(var
->data
.image
.format
);
373 if (isl_has_matching_typed_storage_image_format(devinfo
, image_fmt
)) {
374 const enum isl_format lower_fmt
=
375 isl_lower_storage_image_format(devinfo
, image_fmt
);
376 const unsigned dest_components
= intrin
->num_components
;
378 /* Use an undef to hold the uses of the load while we do the color
381 nir_ssa_def
*placeholder
= nir_ssa_undef(b
, 4, 32);
382 nir_ssa_def_rewrite_uses(&intrin
->dest
.ssa
, nir_src_for_ssa(placeholder
));
384 intrin
->num_components
= isl_format_get_num_channels(lower_fmt
);
385 intrin
->dest
.ssa
.num_components
= intrin
->num_components
;
387 b
->cursor
= nir_after_instr(&intrin
->instr
);
389 nir_ssa_def
*color
= convert_color_for_load(b
, devinfo
,
391 image_fmt
, lower_fmt
,
394 nir_ssa_def_rewrite_uses(placeholder
, nir_src_for_ssa(color
));
395 nir_instr_remove(placeholder
->parent_instr
);
397 const struct isl_format_layout
*image_fmtl
=
398 isl_format_get_layout(image_fmt
);
399 /* We have a matching typed format for everything 32b and below */
400 assert(image_fmtl
->bpb
== 64 || image_fmtl
->bpb
== 128);
401 enum isl_format raw_fmt
= (image_fmtl
->bpb
== 64) ?
402 ISL_FORMAT_R32G32_UINT
:
403 ISL_FORMAT_R32G32B32A32_UINT
;
404 const unsigned dest_components
= intrin
->num_components
;
406 b
->cursor
= nir_instr_remove(&intrin
->instr
);
408 nir_ssa_def
*coord
= intrin
->src
[1].ssa
;
410 nir_ssa_def
*do_load
= image_coord_is_in_bounds(b
, deref
, coord
);
411 if (devinfo
->gen
== 7 && !devinfo
->is_haswell
) {
412 /* Check whether the first stride component (i.e. the Bpp value)
413 * is greater than four, what on Gen7 indicates that a surface of
414 * type RAW has been bound for untyped access. Reading or writing
415 * to a surface of type other than RAW using untyped surface
416 * messages causes a hang on IVB and VLV.
418 nir_ssa_def
*stride
= load_image_param(b
, deref
, STRIDE
);
419 nir_ssa_def
*is_raw
=
420 nir_ilt(b
, nir_imm_int(b
, 4), nir_channel(b
, stride
, 0));
421 do_load
= nir_iand(b
, do_load
, is_raw
);
423 nir_push_if(b
, do_load
);
425 nir_ssa_def
*addr
= image_address(b
, devinfo
, deref
, coord
);
426 nir_intrinsic_instr
*load
=
427 nir_intrinsic_instr_create(b
->shader
,
428 nir_intrinsic_image_deref_load_raw_intel
);
429 load
->src
[0] = nir_src_for_ssa(&deref
->dest
.ssa
);
430 load
->src
[1] = nir_src_for_ssa(addr
);
431 load
->num_components
= image_fmtl
->bpb
/ 32;
432 nir_ssa_dest_init(&load
->instr
, &load
->dest
,
433 load
->num_components
, 32, NULL
);
434 nir_builder_instr_insert(b
, &load
->instr
);
436 nir_push_else(b
, NULL
);
438 nir_ssa_def
*zero
= nir_imm_zero(b
, load
->num_components
, 32);
442 nir_ssa_def
*value
= nir_if_phi(b
, &load
->dest
.ssa
, zero
);
444 nir_ssa_def
*color
= convert_color_for_load(b
, devinfo
, value
,
448 nir_ssa_def_rewrite_uses(&intrin
->dest
.ssa
, nir_src_for_ssa(color
));
455 convert_color_for_store(nir_builder
*b
, const struct gen_device_info
*devinfo
,
457 enum isl_format image_fmt
, enum isl_format lower_fmt
)
459 struct format_info image
= get_format_info(image_fmt
);
460 struct format_info lower
= get_format_info(lower_fmt
);
462 color
= nir_channels(b
, color
, (1 << image
.chans
) - 1);
464 if (image_fmt
== lower_fmt
)
467 if (image_fmt
== ISL_FORMAT_R11G11B10_FLOAT
) {
468 assert(lower_fmt
== ISL_FORMAT_R32_UINT
);
469 return nir_format_pack_11f11f10f(b
, color
);
472 switch (image
.fmtl
->channels
.r
.type
) {
474 assert(isl_format_has_uint_channel(lower_fmt
));
475 color
= nir_format_float_to_unorm(b
, color
, image
.bits
);
479 assert(isl_format_has_uint_channel(lower_fmt
));
480 color
= nir_format_float_to_snorm(b
, color
, image
.bits
);
484 if (image
.bits
[0] == 16)
485 color
= nir_format_float_to_half(b
, color
);
489 color
= nir_format_clamp_uint(b
, color
, image
.bits
);
493 color
= nir_format_clamp_sint(b
, color
, image
.bits
);
497 unreachable("Invalid image channel type");
500 if (image
.bits
[0] < 32 &&
501 (isl_format_has_snorm_channel(image_fmt
) ||
502 isl_format_has_sint_channel(image_fmt
)))
503 color
= nir_format_mask_uvec(b
, color
, image
.bits
);
505 if (image
.bits
[0] != lower
.bits
[0] && lower_fmt
== ISL_FORMAT_R32_UINT
) {
506 color
= nir_format_pack_uint(b
, color
, image
.bits
, image
.chans
);
508 /* All these formats are homogeneous */
509 for (unsigned i
= 1; i
< image
.chans
; i
++)
510 assert(image
.bits
[i
] == image
.bits
[0]);
512 if (image
.bits
[0] != lower
.bits
[0]) {
513 color
= nir_format_bitcast_uvec_unmasked(b
, color
, image
.bits
[0],
522 lower_image_store_instr(nir_builder
*b
,
523 const struct gen_device_info
*devinfo
,
524 nir_intrinsic_instr
*intrin
)
526 nir_deref_instr
*deref
= nir_src_as_deref(intrin
->src
[0]);
527 nir_variable
*var
= nir_deref_instr_get_variable(deref
);
529 /* For write-only surfaces, we trust that the hardware can just do the
532 if (var
->data
.access
& ACCESS_NON_READABLE
)
535 const enum isl_format image_fmt
=
536 isl_format_for_pipe_format(var
->data
.image
.format
);
538 if (isl_has_matching_typed_storage_image_format(devinfo
, image_fmt
)) {
539 const enum isl_format lower_fmt
=
540 isl_lower_storage_image_format(devinfo
, image_fmt
);
542 /* Color conversion goes before the store */
543 b
->cursor
= nir_before_instr(&intrin
->instr
);
545 nir_ssa_def
*color
= convert_color_for_store(b
, devinfo
,
547 image_fmt
, lower_fmt
);
548 intrin
->num_components
= isl_format_get_num_channels(lower_fmt
);
549 nir_instr_rewrite_src(&intrin
->instr
, &intrin
->src
[3],
550 nir_src_for_ssa(color
));
552 const struct isl_format_layout
*image_fmtl
=
553 isl_format_get_layout(image_fmt
);
554 /* We have a matching typed format for everything 32b and below */
555 assert(image_fmtl
->bpb
== 64 || image_fmtl
->bpb
== 128);
556 enum isl_format raw_fmt
= (image_fmtl
->bpb
== 64) ?
557 ISL_FORMAT_R32G32_UINT
:
558 ISL_FORMAT_R32G32B32A32_UINT
;
560 b
->cursor
= nir_instr_remove(&intrin
->instr
);
562 nir_ssa_def
*coord
= intrin
->src
[1].ssa
;
564 nir_ssa_def
*do_store
= image_coord_is_in_bounds(b
, deref
, coord
);
565 if (devinfo
->gen
== 7 && !devinfo
->is_haswell
) {
566 /* Check whether the first stride component (i.e. the Bpp value)
567 * is greater than four, what on Gen7 indicates that a surface of
568 * type RAW has been bound for untyped access. Reading or writing
569 * to a surface of type other than RAW using untyped surface
570 * messages causes a hang on IVB and VLV.
572 nir_ssa_def
*stride
= load_image_param(b
, deref
, STRIDE
);
573 nir_ssa_def
*is_raw
=
574 nir_ilt(b
, nir_imm_int(b
, 4), nir_channel(b
, stride
, 0));
575 do_store
= nir_iand(b
, do_store
, is_raw
);
577 nir_push_if(b
, do_store
);
579 nir_ssa_def
*addr
= image_address(b
, devinfo
, deref
, coord
);
580 nir_ssa_def
*color
= convert_color_for_store(b
, devinfo
,
584 nir_intrinsic_instr
*store
=
585 nir_intrinsic_instr_create(b
->shader
,
586 nir_intrinsic_image_deref_store_raw_intel
);
587 store
->src
[0] = nir_src_for_ssa(&deref
->dest
.ssa
);
588 store
->src
[1] = nir_src_for_ssa(addr
);
589 store
->src
[2] = nir_src_for_ssa(color
);
590 store
->num_components
= image_fmtl
->bpb
/ 32;
591 nir_builder_instr_insert(b
, &store
->instr
);
600 lower_image_atomic_instr(nir_builder
*b
,
601 const struct gen_device_info
*devinfo
,
602 nir_intrinsic_instr
*intrin
)
604 if (devinfo
->is_haswell
|| devinfo
->gen
>= 8)
607 nir_deref_instr
*deref
= nir_src_as_deref(intrin
->src
[0]);
609 b
->cursor
= nir_instr_remove(&intrin
->instr
);
611 /* Use an undef to hold the uses of the load conversion. */
612 nir_ssa_def
*placeholder
= nir_ssa_undef(b
, 4, 32);
613 nir_ssa_def_rewrite_uses(&intrin
->dest
.ssa
, nir_src_for_ssa(placeholder
));
615 /* Check the first component of the size field to find out if the
616 * image is bound. Necessary on IVB for typed atomics because
617 * they don't seem to respect null surfaces and will happily
618 * corrupt or read random memory when no image is bound.
620 nir_ssa_def
*size
= load_image_param(b
, deref
, SIZE
);
621 nir_ssa_def
*zero
= nir_imm_int(b
, 0);
622 nir_push_if(b
, nir_ine(b
, nir_channel(b
, size
, 0), zero
));
624 nir_builder_instr_insert(b
, &intrin
->instr
);
628 nir_ssa_def
*result
= nir_if_phi(b
, &intrin
->dest
.ssa
, zero
);
629 nir_ssa_def_rewrite_uses(placeholder
, nir_src_for_ssa(result
));
635 lower_image_size_instr(nir_builder
*b
,
636 const struct gen_device_info
*devinfo
,
637 nir_intrinsic_instr
*intrin
)
639 nir_deref_instr
*deref
= nir_src_as_deref(intrin
->src
[0]);
640 nir_variable
*var
= nir_deref_instr_get_variable(deref
);
642 /* For write-only images, we have an actual image surface so we fall back
643 * and let the back-end emit a TXS for this.
645 if (var
->data
.access
& ACCESS_NON_READABLE
)
648 /* If we have a matching typed format, then we have an actual image surface
649 * so we fall back and let the back-end emit a TXS for this.
651 const enum isl_format image_fmt
=
652 isl_format_for_pipe_format(var
->data
.image
.format
);
653 if (isl_has_matching_typed_storage_image_format(devinfo
, image_fmt
))
656 b
->cursor
= nir_instr_remove(&intrin
->instr
);
658 nir_ssa_def
*size
= load_image_param(b
, deref
, SIZE
);
660 nir_ssa_def
*comps
[4] = { NULL
, NULL
, NULL
, NULL
};
662 enum glsl_sampler_dim dim
= glsl_get_sampler_dim(deref
->type
);
663 unsigned coord_comps
= glsl_get_sampler_coordinate_components(deref
->type
);
664 for (unsigned c
= 0; c
< coord_comps
; c
++) {
665 if (c
== 2 && dim
== GLSL_SAMPLER_DIM_CUBE
) {
666 comps
[2] = nir_idiv(b
, nir_channel(b
, size
, 2), nir_imm_int(b
, 6));
668 comps
[c
] = nir_channel(b
, size
, c
);
672 for (unsigned c
= coord_comps
; c
< intrin
->dest
.ssa
.num_components
; ++c
)
673 comps
[c
] = nir_imm_int(b
, 1);
675 nir_ssa_def
*vec
= nir_vec(b
, comps
, intrin
->dest
.ssa
.num_components
);
676 nir_ssa_def_rewrite_uses(&intrin
->dest
.ssa
, nir_src_for_ssa(vec
));
682 brw_nir_lower_image_load_store(nir_shader
*shader
,
683 const struct gen_device_info
*devinfo
,
684 bool *uses_atomic_load_store
)
686 bool progress
= false;
688 nir_foreach_function(function
, shader
) {
689 if (function
->impl
== NULL
)
692 bool impl_progress
= false;
693 nir_foreach_block_safe(block
, function
->impl
) {
695 nir_builder_init(&b
, function
->impl
);
697 nir_foreach_instr_safe(instr
, block
) {
698 if (instr
->type
!= nir_instr_type_intrinsic
)
701 nir_intrinsic_instr
*intrin
= nir_instr_as_intrinsic(instr
);
702 switch (intrin
->intrinsic
) {
703 case nir_intrinsic_image_deref_load
:
704 if (lower_image_load_instr(&b
, devinfo
, intrin
))
705 impl_progress
= true;
708 case nir_intrinsic_image_deref_store
:
709 if (lower_image_store_instr(&b
, devinfo
, intrin
))
710 impl_progress
= true;
713 case nir_intrinsic_image_deref_atomic_add
:
714 case nir_intrinsic_image_deref_atomic_imin
:
715 case nir_intrinsic_image_deref_atomic_umin
:
716 case nir_intrinsic_image_deref_atomic_imax
:
717 case nir_intrinsic_image_deref_atomic_umax
:
718 case nir_intrinsic_image_deref_atomic_and
:
719 case nir_intrinsic_image_deref_atomic_or
:
720 case nir_intrinsic_image_deref_atomic_xor
:
721 case nir_intrinsic_image_deref_atomic_exchange
:
722 case nir_intrinsic_image_deref_atomic_comp_swap
:
723 if (uses_atomic_load_store
)
724 *uses_atomic_load_store
= true;
725 if (lower_image_atomic_instr(&b
, devinfo
, intrin
))
726 impl_progress
= true;
729 case nir_intrinsic_image_deref_size
:
730 if (lower_image_size_instr(&b
, devinfo
, intrin
))
731 impl_progress
= true;
743 nir_metadata_preserve(function
->impl
, nir_metadata_none
);
745 nir_metadata_preserve(function
->impl
, nir_metadata_all
);