src/intel/compiler/brw_nir_lower_mem_access_bit_sizes.c

   1 /*
   2  * Copyright © 2018 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  */
  23
  24 #include "brw_nir.h"
  25 #include "compiler/nir/nir_builder.h"
  26 #include "util/u_math.h"
  27 #include "util/bitscan.h"
  28
  29 static nir_ssa_def *
  30 dup_mem_intrinsic(nir_builder *b, nir_intrinsic_instr *intrin,
  31                   nir_ssa_def *store_src, int offset,
  32                   unsigned num_components, unsigned bit_size,
  33                   unsigned align)
  34 {
  35    const nir_intrinsic_info *info = &nir_intrinsic_infos[intrin->intrinsic];
  36
  37    nir_intrinsic_instr *dup =
  38       nir_intrinsic_instr_create(b->shader, intrin->intrinsic);
  39
  40    nir_src *intrin_offset_src = nir_get_io_offset_src(intrin);
  41    for (unsigned i = 0; i < info->num_srcs; i++) {
  42       assert(intrin->src[i].is_ssa);
  43       if (i == 0 && store_src) {
  44          assert(!info->has_dest);
  45          assert(&intrin->src[i] != intrin_offset_src);
  46          dup->src[i] = nir_src_for_ssa(store_src);
  47       } else if (&intrin->src[i] == intrin_offset_src) {
  48          dup->src[i] = nir_src_for_ssa(nir_iadd_imm(b, intrin->src[i].ssa,
  49                                                        offset));
  50       } else {
  51          dup->src[i] = nir_src_for_ssa(intrin->src[i].ssa);
  52       }
  53    }
  54
  55    dup->num_components = num_components;
  56
  57    for (unsigned i = 0; i < info->num_indices; i++)
  58       dup->const_index[i] = intrin->const_index[i];
  59
  60    nir_intrinsic_set_align(dup, align, 0);
  61
  62    if (info->has_dest) {
  63       assert(intrin->dest.is_ssa);
  64       nir_ssa_dest_init(&dup->instr, &dup->dest,
  65                         num_components, bit_size,
  66                         intrin->dest.ssa.name);
  67    } else {
  68       nir_intrinsic_set_write_mask(dup, (1 << num_components) - 1);
  69    }
  70
  71    nir_builder_instr_insert(b, &dup->instr);
  72
  73    return info->has_dest ? &dup->dest.ssa : NULL;
  74 }
  75
  76 static bool
  77 lower_mem_load_bit_size(nir_builder *b, nir_intrinsic_instr *intrin)
  78 {
  79    assert(intrin->dest.is_ssa);
  80    if (intrin->dest.ssa.bit_size == 32)
  81       return false;
  82
  83    const unsigned bit_size = intrin->dest.ssa.bit_size;
  84    const unsigned num_components = intrin->dest.ssa.num_components;
  85    const unsigned bytes_read = num_components * (bit_size / 8);
  86    const unsigned align = nir_intrinsic_align(intrin);
  87
  88    nir_ssa_def *result;
  89    nir_src *offset_src = nir_get_io_offset_src(intrin);
  90    if (bit_size < 32 && nir_src_is_const(*offset_src)) {
  91       /* The offset is constant so we can use a 32-bit load and just shift it
  92        * around as needed.
  93        */
  94       const int load_offset = nir_src_as_uint(*offset_src) % 4;
  95       assert(load_offset % (bit_size / 8) == 0);
  96       const unsigned load_comps32 = DIV_ROUND_UP(bytes_read + load_offset, 4);
  97       /* A 16-bit vec4 is a 32-bit vec2.  We add an extra component in case
  98        * we offset into a component with load_offset.
  99        */
 100       assert(load_comps32 <= 3);
 101
 102       nir_ssa_def *load = dup_mem_intrinsic(b, intrin, NULL, -load_offset,
 103                                             load_comps32, 32, 4);
 104       result = nir_extract_bits(b, &load, 1, load_offset * 8,
 105                                 num_components, bit_size);
 106    } else {
 107       /* Otherwise, we have to break it into smaller loads */
 108       nir_ssa_def *loads[8];
 109       unsigned num_loads = 0;
 110       int load_offset = 0;
 111       while (load_offset < bytes_read) {
 112          const unsigned bytes_left = bytes_read - load_offset;
 113          unsigned load_bit_size, load_comps;
 114          if (align < 4) {
 115             load_comps = 1;
 116             /* Choose a byte, word, or dword */
 117             load_bit_size = util_next_power_of_two(MIN2(bytes_left, 4)) * 8;
 118          } else {
 119             assert(load_offset % 4 == 0);
 120             load_bit_size = 32;
 121             load_comps = DIV_ROUND_UP(MIN2(bytes_left, 16), 4);
 122          }
 123
 124          loads[num_loads++] = dup_mem_intrinsic(b, intrin, NULL, load_offset,
 125                                                 load_comps, load_bit_size,
 126                                                 align);
 127
 128          load_offset += load_comps * (load_bit_size / 8);
 129       }
 130       assert(num_loads <= ARRAY_SIZE(loads));
 131       result = nir_extract_bits(b, loads, num_loads, 0,
 132                                 num_components, bit_size);
 133    }
 134
 135    nir_ssa_def_rewrite_uses(&intrin->dest.ssa,
 136                             nir_src_for_ssa(result));
 137    nir_instr_remove(&intrin->instr);
 138
 139    return true;
 140 }
 141
 142 static bool
 143 lower_mem_store_bit_size(nir_builder *b, nir_intrinsic_instr *intrin)
 144 {
 145    assert(intrin->src[0].is_ssa);
 146    nir_ssa_def *value = intrin->src[0].ssa;
 147
 148    assert(intrin->num_components == value->num_components);
 149    const unsigned bit_size = value->bit_size;
 150    const unsigned num_components = intrin->num_components;
 151    const unsigned bytes_written = num_components * (bit_size / 8);
 152    const unsigned align_mul = nir_intrinsic_align_mul(intrin);
 153    const unsigned align_offset = nir_intrinsic_align_offset(intrin);
 154    const unsigned align = nir_intrinsic_align(intrin);
 155
 156    nir_component_mask_t writemask = nir_intrinsic_write_mask(intrin);
 157    assert(writemask < (1 << num_components));
 158
 159    if ((value->bit_size <= 32 && num_components == 1) ||
 160        (value->bit_size == 32 && writemask == (1 << num_components) - 1))
 161       return false;
 162
 163    nir_src *offset_src = nir_get_io_offset_src(intrin);
 164    const bool offset_is_const = nir_src_is_const(*offset_src);
 165    const unsigned const_offset =
 166       offset_is_const ? nir_src_as_uint(*offset_src) : 0;
 167
 168    const unsigned byte_size = bit_size / 8;
 169    assert(byte_size <= sizeof(uint64_t));
 170
 171    BITSET_DECLARE(mask, NIR_MAX_VEC_COMPONENTS * sizeof(uint64_t));
 172    BITSET_ZERO(mask);
 173
 174    for (unsigned i = 0; i < num_components; i++) {
 175       if (writemask & (1u << i))
 176          BITSET_SET_RANGE(mask, i * byte_size, ((i + 1) * byte_size) - 1);
 177    }
 178
 179    while (BITSET_FFS(mask) != 0) {
 180       const int start = BITSET_FFS(mask) - 1;
 181       assert(start % byte_size == 0);
 182
 183       int end;
 184       for (end = start + 1; end < bytes_written; end++) {
 185          if (!(BITSET_TEST(mask, end)))
 186             break;
 187       }
 188       /* The size of the current contiguous chunk in bytes */
 189       const unsigned chunk_bytes = end - start;
 190
 191       const bool is_dword_aligned =
 192          (align_mul >= 4 && (align_offset + start) % 4 == 0) ||
 193          (offset_is_const && (start + const_offset) % 4 == 0);
 194
 195       unsigned store_comps, store_bit_size, store_align;
 196       if (chunk_bytes >= 4 && is_dword_aligned) {
 197          store_align = MAX2(align, 4);
 198          store_bit_size = 32;
 199          store_comps = MIN2(chunk_bytes, 16) / 4;
 200       } else {
 201          store_align = align;
 202          store_comps = 1;
 203          store_bit_size = MIN2(chunk_bytes, 4) * 8;
 204          /* The bit size must be a power of two */
 205          if (store_bit_size == 24)
 206             store_bit_size = 16;
 207       }
 208       const unsigned store_bytes = store_comps * (store_bit_size / 8);
 209       assert(store_bytes % byte_size == 0);
 210
 211       nir_ssa_def *packed = nir_extract_bits(b, &value, 1, start * 8,
 212                                              store_comps, store_bit_size);
 213
 214       dup_mem_intrinsic(b, intrin, packed, start,
 215                         store_comps, store_bit_size, store_align);
 216
 217       BITSET_CLEAR_RANGE(mask, start, (start + store_bytes - 1));
 218    }
 219
 220    nir_instr_remove(&intrin->instr);
 221
 222    return true;
 223 }
 224
 225 static bool
 226 lower_mem_access_bit_sizes_impl(nir_function_impl *impl)
 227 {
 228    bool progress = false;
 229
 230    nir_builder b;
 231    nir_builder_init(&b, impl);
 232
 233    nir_foreach_block(block, impl) {
 234       nir_foreach_instr_safe(instr, block) {
 235          if (instr->type != nir_instr_type_intrinsic)
 236             continue;
 237
 238          b.cursor = nir_after_instr(instr);
 239
 240          nir_intrinsic_instr *intrin = nir_instr_as_intrinsic(instr);
 241          switch (intrin->intrinsic) {
 242          case nir_intrinsic_load_global:
 243          case nir_intrinsic_load_ssbo:
 244          case nir_intrinsic_load_shared:
 245             if (lower_mem_load_bit_size(&b, intrin))
 246                progress = true;
 247             break;
 248
 249          case nir_intrinsic_store_global:
 250          case nir_intrinsic_store_ssbo:
 251          case nir_intrinsic_store_shared:
 252             if (lower_mem_store_bit_size(&b, intrin))
 253                progress = true;
 254             break;
 255
 256          default:
 257             break;
 258          }
 259       }
 260    }
 261
 262    if (progress) {
 263       nir_metadata_preserve(impl, nir_metadata_block_index |
 264                                   nir_metadata_dominance);
 265    }
 266
 267    return progress;
 268 }
 269
 270 /**
 271  * This pass loads arbitrary SSBO and shared memory load/store operations to
 272  * intrinsics which are natively handleable by GEN hardware.  In particular,
 273  * we have two general types of memory load/store messages:
 274  *
 275  *  - Untyped surface read/write:  These can load/store between one and four
 276  *    dword components to/from a dword-aligned offset.
 277  *
 278  *  - Byte scattered read/write:  These can load/store a single byte, word, or
 279  *    dword scalar to/from an unaligned byte offset.
 280  *
 281  * Neither type of message can do a write-masked store.  This pass converts
 282  * all nir load/store intrinsics into a series of either 8 or 32-bit
 283  * load/store intrinsics with a number of components that we can directly
 284  * handle in hardware and with a trivial write-mask.
 285  */
 286 bool
 287 brw_nir_lower_mem_access_bit_sizes(nir_shader *shader)
 288 {
 289    bool progress = false;
 290
 291    nir_foreach_function(func, shader) {
 292       if (func->impl && lower_mem_access_bit_sizes_impl(func->impl))
 293          progress = true;
 294    }
 295
 296    return progress;
 297 }