2 Copyright (C) Intel Corp. 2006. All Rights Reserved.
3 Intel funded Tungsten Graphics to
4 develop this 3D driver.
6 Permission is hereby granted, free of charge, to any person obtaining
7 a copy of this software and associated documentation files (the
8 "Software"), to deal in the Software without restriction, including
9 without limitation the rights to use, copy, modify, merge, publish,
10 distribute, sublicense, and/or sell copies of the Software, and to
11 permit persons to whom the Software is furnished to do so, subject to
12 the following conditions:
14 The above copyright notice and this permission notice (including the
15 next paragraph) shall be included in all copies or substantial
16 portions of the Software.
18 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
19 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
20 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
21 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
22 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
23 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
24 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
26 **********************************************************************/
29 * Keith Whitwell <keithw@vmware.com>
34 * This file defines struct brw_reg, which is our representation for EU
35 * registers. They're not a hardware specific format, just an abstraction
36 * that intends to capture the full flexibility of the hardware registers.
38 * The brw_eu_emit.c layer's brw_set_dest/brw_set_src[01] functions encode
39 * the abstract brw_reg type into the actual hardware instruction encoding.
46 #include "main/compiler.h"
47 #include "main/macros.h"
48 #include "program/prog_instruction.h"
49 #include "brw_eu_defines.h"
50 #include "brw_reg_type.h"
56 struct gen_device_info
;
58 /** Number of general purpose registers (VS, WM, etc) */
59 #define BRW_MAX_GRF 128
62 * First GRF used for the MRF hack.
64 * On gen7, MRFs are no longer used, and contiguous GRFs are used instead. We
65 * haven't converted our compiler to be aware of this, so it asks for MRFs and
66 * brw_eu_emit.c quietly converts them to be accesses of the top GRFs. The
67 * register allocators have to be careful of this to avoid corrupting the "MRF"s
68 * with actual GRF allocations.
70 #define GEN7_MRF_HACK_START 112
72 /** Number of message register file registers */
73 #define BRW_MAX_MRF(gen) (gen == 6 ? 24 : 16)
75 #define BRW_SWIZZLE4(a,b,c,d) (((a)<<0) | ((b)<<2) | ((c)<<4) | ((d)<<6))
76 #define BRW_GET_SWZ(swz, idx) (((swz) >> ((idx)*2)) & 0x3)
78 #define BRW_SWIZZLE_NOOP BRW_SWIZZLE4(0,1,2,3)
79 #define BRW_SWIZZLE_XYZW BRW_SWIZZLE4(0,1,2,3)
80 #define BRW_SWIZZLE_XXXX BRW_SWIZZLE4(0,0,0,0)
81 #define BRW_SWIZZLE_YYYY BRW_SWIZZLE4(1,1,1,1)
82 #define BRW_SWIZZLE_ZZZZ BRW_SWIZZLE4(2,2,2,2)
83 #define BRW_SWIZZLE_WWWW BRW_SWIZZLE4(3,3,3,3)
84 #define BRW_SWIZZLE_XYXY BRW_SWIZZLE4(0,1,0,1)
85 #define BRW_SWIZZLE_YXYX BRW_SWIZZLE4(1,0,1,0)
86 #define BRW_SWIZZLE_XZXZ BRW_SWIZZLE4(0,2,0,2)
87 #define BRW_SWIZZLE_YZXW BRW_SWIZZLE4(1,2,0,3)
88 #define BRW_SWIZZLE_YWYW BRW_SWIZZLE4(1,3,1,3)
89 #define BRW_SWIZZLE_ZXYW BRW_SWIZZLE4(2,0,1,3)
90 #define BRW_SWIZZLE_ZWZW BRW_SWIZZLE4(2,3,2,3)
91 #define BRW_SWIZZLE_WZWZ BRW_SWIZZLE4(3,2,3,2)
92 #define BRW_SWIZZLE_WZYX BRW_SWIZZLE4(3,2,1,0)
93 #define BRW_SWIZZLE_XXZZ BRW_SWIZZLE4(0,0,2,2)
94 #define BRW_SWIZZLE_YYWW BRW_SWIZZLE4(1,1,3,3)
95 #define BRW_SWIZZLE_YXWZ BRW_SWIZZLE4(1,0,3,2)
97 #define BRW_SWZ_COMP_INPUT(comp) (BRW_SWIZZLE_XYZW >> ((comp)*2))
98 #define BRW_SWZ_COMP_OUTPUT(comp) (BRW_SWIZZLE_XYZW << ((comp)*2))
101 brw_is_single_value_swizzle(unsigned swiz
)
103 return (swiz
== BRW_SWIZZLE_XXXX
||
104 swiz
== BRW_SWIZZLE_YYYY
||
105 swiz
== BRW_SWIZZLE_ZZZZ
||
106 swiz
== BRW_SWIZZLE_WWWW
);
110 * Compute the swizzle obtained from the application of \p swz0 on the result
111 * of \p swz1. The argument ordering is expected to match function
114 static inline unsigned
115 brw_compose_swizzle(unsigned swz0
, unsigned swz1
)
118 BRW_GET_SWZ(swz1
, BRW_GET_SWZ(swz0
, 0)),
119 BRW_GET_SWZ(swz1
, BRW_GET_SWZ(swz0
, 1)),
120 BRW_GET_SWZ(swz1
, BRW_GET_SWZ(swz0
, 2)),
121 BRW_GET_SWZ(swz1
, BRW_GET_SWZ(swz0
, 3)));
125 * Return the result of applying swizzle \p swz to shuffle the bits of \p mask
128 static inline unsigned
129 brw_apply_swizzle_to_mask(unsigned swz
, unsigned mask
)
133 for (unsigned i
= 0; i
< 4; i
++) {
134 if (mask
& (1 << BRW_GET_SWZ(swz
, i
)))
142 * Return the result of applying the inverse of swizzle \p swz to shuffle the
143 * bits of \p mask (AKA preimage). Useful to find out which components are
144 * read from a swizzled source given the instruction writemask.
146 static inline unsigned
147 brw_apply_inv_swizzle_to_mask(unsigned swz
, unsigned mask
)
151 for (unsigned i
= 0; i
< 4; i
++) {
153 result
|= 1 << BRW_GET_SWZ(swz
, i
);
160 * Construct an identity swizzle for the set of enabled channels given by \p
161 * mask. The result will only reference channels enabled in the provided \p
162 * mask, assuming that \p mask is non-zero. The constructed swizzle will
163 * satisfy the property that for any instruction OP and any mask:
165 * brw_OP(p, brw_writemask(dst, mask),
166 * brw_swizzle(src, brw_swizzle_for_mask(mask)));
168 * will be equivalent to the same instruction without swizzle:
170 * brw_OP(p, brw_writemask(dst, mask), src);
172 static inline unsigned
173 brw_swizzle_for_mask(unsigned mask
)
175 unsigned last
= (mask
? ffs(mask
) - 1 : 0);
178 for (unsigned i
= 0; i
< 4; i
++)
179 last
= swz
[i
] = (mask
& (1 << i
) ? i
: last
);
181 return BRW_SWIZZLE4(swz
[0], swz
[1], swz
[2], swz
[3]);
185 * Construct an identity swizzle for the first \p n components of a vector.
186 * When only a subset of channels of a vec4 are used we don't want to
187 * reference the other channels, as that will tell optimization passes that
188 * those other channels are used.
190 static inline unsigned
191 brw_swizzle_for_size(unsigned n
)
193 return brw_swizzle_for_mask((1 << n
) - 1);
197 * Converse of brw_swizzle_for_mask(). Returns the mask of components
198 * accessed by the specified swizzle \p swz.
200 static inline unsigned
201 brw_mask_for_swizzle(unsigned swz
)
203 return brw_apply_inv_swizzle_to_mask(swz
, ~0);
206 uint32_t brw_swizzle_immediate(enum brw_reg_type type
, uint32_t x
, unsigned swz
);
208 #define REG_SIZE (8*4)
210 /* These aren't hardware structs, just something useful for us to pass around:
212 * Align1 operation has a lot of control over input ranges. Used in
213 * WM programs to implement shaders decomposed into "channel serial"
214 * or "structure of array" form:
219 enum brw_reg_type type
:4;
220 enum brw_reg_file file
:3; /* :2 hardware format */
221 unsigned negate
:1; /* source only */
222 unsigned abs
:1; /* source only */
223 unsigned address_mode
:1; /* relative addressing, hopefully! */
225 unsigned subnr
:5; /* :1 in align16 */
233 unsigned swizzle
:8; /* src only, align16 only */
234 unsigned writemask
:4; /* dest only, align16 only */
235 int indirect_offset
:10; /* relative addressing offset */
236 unsigned vstride
:4; /* source only */
237 unsigned width
:3; /* src only, align1 only */
238 unsigned hstride
:2; /* align1 only */
252 brw_regs_equal(const struct brw_reg
*a
, const struct brw_reg
*b
)
254 const bool df
= a
->type
== BRW_REGISTER_TYPE_DF
&& a
->file
== IMM
;
255 return a
->bits
== b
->bits
&& (df
? a
->u64
== b
->u64
: a
->ud
== b
->ud
);
258 struct brw_indirect
{
259 unsigned addr_subnr
:4;
265 static inline unsigned
266 type_sz(unsigned type
)
269 case BRW_REGISTER_TYPE_UQ
:
270 case BRW_REGISTER_TYPE_Q
:
271 case BRW_REGISTER_TYPE_DF
:
273 case BRW_REGISTER_TYPE_UD
:
274 case BRW_REGISTER_TYPE_D
:
275 case BRW_REGISTER_TYPE_F
:
276 case BRW_REGISTER_TYPE_VF
:
278 case BRW_REGISTER_TYPE_UW
:
279 case BRW_REGISTER_TYPE_W
:
280 case BRW_REGISTER_TYPE_UV
:
281 case BRW_REGISTER_TYPE_V
:
282 case BRW_REGISTER_TYPE_HF
:
284 case BRW_REGISTER_TYPE_UB
:
285 case BRW_REGISTER_TYPE_B
:
288 unreachable("not reached");
293 brw_reg_type_is_floating_point(enum brw_reg_type type
)
296 case BRW_REGISTER_TYPE_F
:
297 case BRW_REGISTER_TYPE_HF
:
298 case BRW_REGISTER_TYPE_DF
:
305 static inline enum brw_reg_type
306 get_exec_type(const enum brw_reg_type type
)
309 case BRW_REGISTER_TYPE_B
:
310 case BRW_REGISTER_TYPE_V
:
311 return BRW_REGISTER_TYPE_W
;
312 case BRW_REGISTER_TYPE_UB
:
313 case BRW_REGISTER_TYPE_UV
:
314 return BRW_REGISTER_TYPE_UW
;
315 case BRW_REGISTER_TYPE_VF
:
316 return BRW_REGISTER_TYPE_F
;
323 * Return an integer type of the requested size and signedness.
325 static inline enum brw_reg_type
326 brw_int_type(unsigned sz
, bool is_signed
)
330 return (is_signed
? BRW_REGISTER_TYPE_B
: BRW_REGISTER_TYPE_UB
);
332 return (is_signed
? BRW_REGISTER_TYPE_W
: BRW_REGISTER_TYPE_UW
);
334 return (is_signed
? BRW_REGISTER_TYPE_D
: BRW_REGISTER_TYPE_UD
);
336 return (is_signed
? BRW_REGISTER_TYPE_Q
: BRW_REGISTER_TYPE_UQ
);
338 unreachable("Not reached.");
343 * Construct a brw_reg.
344 * \param file one of the BRW_x_REGISTER_FILE values
345 * \param nr register number/index
346 * \param subnr register sub number
347 * \param negate register negate modifier
348 * \param abs register abs modifier
349 * \param type one of BRW_REGISTER_TYPE_x
350 * \param vstride one of BRW_VERTICAL_STRIDE_x
351 * \param width one of BRW_WIDTH_x
352 * \param hstride one of BRW_HORIZONTAL_STRIDE_x
353 * \param swizzle one of BRW_SWIZZLE_x
354 * \param writemask WRITEMASK_X/Y/Z/W bitfield
356 static inline struct brw_reg
357 brw_reg(enum brw_reg_file file
,
362 enum brw_reg_type type
,
370 if (file
== BRW_GENERAL_REGISTER_FILE
)
371 assert(nr
< BRW_MAX_GRF
);
372 else if (file
== BRW_ARCHITECTURE_REGISTER_FILE
)
373 assert(nr
<= BRW_ARF_TIMESTAMP
);
374 /* Asserting on the MRF register number requires to know the hardware gen
375 * (gen6 has 24 MRF registers), which we don't know here, so we assert
376 * for that in the generators and in brw_eu_emit.c
383 reg
.address_mode
= BRW_ADDRESS_DIRECT
;
385 reg
.subnr
= subnr
* type_sz(type
);
388 /* Could do better: If the reg is r5.3<0;1,0>, we probably want to
389 * set swizzle and writemask to W, as the lower bits of subnr will
390 * be lost when converted to align16. This is probably too much to
391 * keep track of as you'd want it adjusted by suboffset(), etc.
392 * Perhaps fix up when converting to align16?
394 reg
.swizzle
= swizzle
;
395 reg
.writemask
= writemask
;
396 reg
.indirect_offset
= 0;
397 reg
.vstride
= vstride
;
399 reg
.hstride
= hstride
;
404 /** Construct float[16] register */
405 static inline struct brw_reg
406 brw_vec16_reg(enum brw_reg_file file
, unsigned nr
, unsigned subnr
)
414 BRW_VERTICAL_STRIDE_16
,
416 BRW_HORIZONTAL_STRIDE_1
,
421 /** Construct float[8] register */
422 static inline struct brw_reg
423 brw_vec8_reg(enum brw_reg_file file
, unsigned nr
, unsigned subnr
)
431 BRW_VERTICAL_STRIDE_8
,
433 BRW_HORIZONTAL_STRIDE_1
,
438 /** Construct float[4] register */
439 static inline struct brw_reg
440 brw_vec4_reg(enum brw_reg_file file
, unsigned nr
, unsigned subnr
)
448 BRW_VERTICAL_STRIDE_4
,
450 BRW_HORIZONTAL_STRIDE_1
,
455 /** Construct float[2] register */
456 static inline struct brw_reg
457 brw_vec2_reg(enum brw_reg_file file
, unsigned nr
, unsigned subnr
)
465 BRW_VERTICAL_STRIDE_2
,
467 BRW_HORIZONTAL_STRIDE_1
,
472 /** Construct float[1] register */
473 static inline struct brw_reg
474 brw_vec1_reg(enum brw_reg_file file
, unsigned nr
, unsigned subnr
)
482 BRW_VERTICAL_STRIDE_0
,
484 BRW_HORIZONTAL_STRIDE_0
,
489 static inline struct brw_reg
490 brw_vecn_reg(unsigned width
, enum brw_reg_file file
,
491 unsigned nr
, unsigned subnr
)
495 return brw_vec1_reg(file
, nr
, subnr
);
497 return brw_vec2_reg(file
, nr
, subnr
);
499 return brw_vec4_reg(file
, nr
, subnr
);
501 return brw_vec8_reg(file
, nr
, subnr
);
503 return brw_vec16_reg(file
, nr
, subnr
);
505 unreachable("Invalid register width");
509 static inline struct brw_reg
510 retype(struct brw_reg reg
, enum brw_reg_type type
)
516 static inline struct brw_reg
517 firsthalf(struct brw_reg reg
)
522 static inline struct brw_reg
523 sechalf(struct brw_reg reg
)
530 static inline struct brw_reg
531 offset(struct brw_reg reg
, unsigned delta
)
538 static inline struct brw_reg
539 byte_offset(struct brw_reg reg
, unsigned bytes
)
541 unsigned newoffset
= reg
.nr
* REG_SIZE
+ reg
.subnr
+ bytes
;
542 reg
.nr
= newoffset
/ REG_SIZE
;
543 reg
.subnr
= newoffset
% REG_SIZE
;
547 static inline struct brw_reg
548 suboffset(struct brw_reg reg
, unsigned delta
)
550 return byte_offset(reg
, delta
* type_sz(reg
.type
));
553 /** Construct unsigned word[16] register */
554 static inline struct brw_reg
555 brw_uw16_reg(enum brw_reg_file file
, unsigned nr
, unsigned subnr
)
557 return suboffset(retype(brw_vec16_reg(file
, nr
, 0), BRW_REGISTER_TYPE_UW
), subnr
);
560 /** Construct unsigned word[8] register */
561 static inline struct brw_reg
562 brw_uw8_reg(enum brw_reg_file file
, unsigned nr
, unsigned subnr
)
564 return suboffset(retype(brw_vec8_reg(file
, nr
, 0), BRW_REGISTER_TYPE_UW
), subnr
);
567 /** Construct unsigned word[1] register */
568 static inline struct brw_reg
569 brw_uw1_reg(enum brw_reg_file file
, unsigned nr
, unsigned subnr
)
571 return suboffset(retype(brw_vec1_reg(file
, nr
, 0), BRW_REGISTER_TYPE_UW
), subnr
);
574 static inline struct brw_reg
575 brw_ud1_reg(enum brw_reg_file file
, unsigned nr
, unsigned subnr
)
577 return retype(brw_vec1_reg(file
, nr
, subnr
), BRW_REGISTER_TYPE_UD
);
580 static inline struct brw_reg
581 brw_imm_reg(enum brw_reg_type type
)
583 return brw_reg(BRW_IMMEDIATE_VALUE
,
589 BRW_VERTICAL_STRIDE_0
,
591 BRW_HORIZONTAL_STRIDE_0
,
596 /** Construct float immediate register */
597 static inline struct brw_reg
598 brw_imm_df(double df
)
600 struct brw_reg imm
= brw_imm_reg(BRW_REGISTER_TYPE_DF
);
605 static inline struct brw_reg
608 struct brw_reg imm
= brw_imm_reg(BRW_REGISTER_TYPE_F
);
613 /** Construct integer immediate register */
614 static inline struct brw_reg
617 struct brw_reg imm
= brw_imm_reg(BRW_REGISTER_TYPE_D
);
622 /** Construct uint immediate register */
623 static inline struct brw_reg
624 brw_imm_ud(unsigned ud
)
626 struct brw_reg imm
= brw_imm_reg(BRW_REGISTER_TYPE_UD
);
631 /** Construct ushort immediate register */
632 static inline struct brw_reg
633 brw_imm_uw(uint16_t uw
)
635 struct brw_reg imm
= brw_imm_reg(BRW_REGISTER_TYPE_UW
);
636 imm
.ud
= uw
| (uw
<< 16);
640 /** Construct short immediate register */
641 static inline struct brw_reg
644 struct brw_reg imm
= brw_imm_reg(BRW_REGISTER_TYPE_W
);
645 imm
.d
= w
| (w
<< 16);
649 /* brw_imm_b and brw_imm_ub aren't supported by hardware - the type
650 * numbers alias with _V and _VF below:
653 /** Construct vector of eight signed half-byte values */
654 static inline struct brw_reg
655 brw_imm_v(unsigned v
)
657 struct brw_reg imm
= brw_imm_reg(BRW_REGISTER_TYPE_V
);
662 /** Construct vector of eight unsigned half-byte values */
663 static inline struct brw_reg
664 brw_imm_uv(unsigned uv
)
666 struct brw_reg imm
= brw_imm_reg(BRW_REGISTER_TYPE_UV
);
671 /** Construct vector of four 8-bit float values */
672 static inline struct brw_reg
673 brw_imm_vf(unsigned v
)
675 struct brw_reg imm
= brw_imm_reg(BRW_REGISTER_TYPE_VF
);
680 static inline struct brw_reg
681 brw_imm_vf4(unsigned v0
, unsigned v1
, unsigned v2
, unsigned v3
)
683 struct brw_reg imm
= brw_imm_reg(BRW_REGISTER_TYPE_VF
);
684 imm
.vstride
= BRW_VERTICAL_STRIDE_0
;
685 imm
.width
= BRW_WIDTH_4
;
686 imm
.hstride
= BRW_HORIZONTAL_STRIDE_1
;
687 imm
.ud
= ((v0
<< 0) | (v1
<< 8) | (v2
<< 16) | (v3
<< 24));
692 static inline struct brw_reg
693 brw_address(struct brw_reg reg
)
695 return brw_imm_uw(reg
.nr
* REG_SIZE
+ reg
.subnr
);
698 /** Construct float[1] general-purpose register */
699 static inline struct brw_reg
700 brw_vec1_grf(unsigned nr
, unsigned subnr
)
702 return brw_vec1_reg(BRW_GENERAL_REGISTER_FILE
, nr
, subnr
);
705 /** Construct float[2] general-purpose register */
706 static inline struct brw_reg
707 brw_vec2_grf(unsigned nr
, unsigned subnr
)
709 return brw_vec2_reg(BRW_GENERAL_REGISTER_FILE
, nr
, subnr
);
712 /** Construct float[4] general-purpose register */
713 static inline struct brw_reg
714 brw_vec4_grf(unsigned nr
, unsigned subnr
)
716 return brw_vec4_reg(BRW_GENERAL_REGISTER_FILE
, nr
, subnr
);
719 /** Construct float[8] general-purpose register */
720 static inline struct brw_reg
721 brw_vec8_grf(unsigned nr
, unsigned subnr
)
723 return brw_vec8_reg(BRW_GENERAL_REGISTER_FILE
, nr
, subnr
);
726 /** Construct float[16] general-purpose register */
727 static inline struct brw_reg
728 brw_vec16_grf(unsigned nr
, unsigned subnr
)
730 return brw_vec16_reg(BRW_GENERAL_REGISTER_FILE
, nr
, subnr
);
733 static inline struct brw_reg
734 brw_vecn_grf(unsigned width
, unsigned nr
, unsigned subnr
)
736 return brw_vecn_reg(width
, BRW_GENERAL_REGISTER_FILE
, nr
, subnr
);
740 static inline struct brw_reg
741 brw_uw8_grf(unsigned nr
, unsigned subnr
)
743 return brw_uw8_reg(BRW_GENERAL_REGISTER_FILE
, nr
, subnr
);
746 static inline struct brw_reg
747 brw_uw16_grf(unsigned nr
, unsigned subnr
)
749 return brw_uw16_reg(BRW_GENERAL_REGISTER_FILE
, nr
, subnr
);
753 /** Construct null register (usually used for setting condition codes) */
754 static inline struct brw_reg
757 return brw_vec8_reg(BRW_ARCHITECTURE_REGISTER_FILE
, BRW_ARF_NULL
, 0);
760 static inline struct brw_reg
761 brw_null_vec(unsigned width
)
763 return brw_vecn_reg(width
, BRW_ARCHITECTURE_REGISTER_FILE
, BRW_ARF_NULL
, 0);
766 static inline struct brw_reg
767 brw_address_reg(unsigned subnr
)
769 return brw_uw1_reg(BRW_ARCHITECTURE_REGISTER_FILE
, BRW_ARF_ADDRESS
, subnr
);
772 /* If/else instructions break in align16 mode if writemask & swizzle
773 * aren't xyzw. This goes against the convention for other scalar
776 static inline struct brw_reg
779 return brw_reg(BRW_ARCHITECTURE_REGISTER_FILE
,
784 BRW_REGISTER_TYPE_UD
,
785 BRW_VERTICAL_STRIDE_4
, /* ? */
787 BRW_HORIZONTAL_STRIDE_0
,
788 BRW_SWIZZLE_XYZW
, /* NOTE! */
789 WRITEMASK_XYZW
); /* NOTE! */
792 static inline struct brw_reg
793 brw_notification_reg(void)
795 return brw_reg(BRW_ARCHITECTURE_REGISTER_FILE
,
796 BRW_ARF_NOTIFICATION_COUNT
,
800 BRW_REGISTER_TYPE_UD
,
801 BRW_VERTICAL_STRIDE_0
,
803 BRW_HORIZONTAL_STRIDE_0
,
808 static inline struct brw_reg
809 brw_sr0_reg(unsigned subnr
)
811 return brw_ud1_reg(BRW_ARCHITECTURE_REGISTER_FILE
, BRW_ARF_STATE
, subnr
);
814 static inline struct brw_reg
815 brw_acc_reg(unsigned width
)
817 return brw_vecn_reg(width
, BRW_ARCHITECTURE_REGISTER_FILE
,
818 BRW_ARF_ACCUMULATOR
, 0);
821 static inline struct brw_reg
822 brw_flag_reg(int reg
, int subreg
)
824 return brw_uw1_reg(BRW_ARCHITECTURE_REGISTER_FILE
,
825 BRW_ARF_FLAG
+ reg
, subreg
);
829 * Return the mask register present in Gen4-5, or the related register present
830 * in Gen7.5 and later hardware referred to as "channel enable" register in
833 static inline struct brw_reg
834 brw_mask_reg(unsigned subnr
)
836 return brw_uw1_reg(BRW_ARCHITECTURE_REGISTER_FILE
, BRW_ARF_MASK
, subnr
);
839 static inline struct brw_reg
842 return brw_sr0_reg(3);
845 static inline struct brw_reg
848 return brw_sr0_reg(2);
851 static inline struct brw_reg
852 brw_message_reg(unsigned nr
)
854 return brw_vec8_reg(BRW_MESSAGE_REGISTER_FILE
, nr
, 0);
857 static inline struct brw_reg
858 brw_uvec_mrf(unsigned width
, unsigned nr
, unsigned subnr
)
860 return retype(brw_vecn_reg(width
, BRW_MESSAGE_REGISTER_FILE
, nr
, subnr
),
861 BRW_REGISTER_TYPE_UD
);
864 /* This is almost always called with a numeric constant argument, so
865 * make things easy to evaluate at compile time:
867 static inline unsigned cvt(unsigned val
)
881 static inline struct brw_reg
882 stride(struct brw_reg reg
, unsigned vstride
, unsigned width
, unsigned hstride
)
884 reg
.vstride
= cvt(vstride
);
885 reg
.width
= cvt(width
) - 1;
886 reg
.hstride
= cvt(hstride
);
891 * Multiply the vertical and horizontal stride of a register by the given
894 static inline struct brw_reg
895 spread(struct brw_reg reg
, unsigned s
)
898 assert(_mesa_is_pow_two(s
));
901 reg
.hstride
+= cvt(s
) - 1;
904 reg
.vstride
+= cvt(s
) - 1;
908 return stride(reg
, 0, 1, 0);
912 static inline struct brw_reg
913 vec16(struct brw_reg reg
)
915 return stride(reg
, 16,16,1);
918 static inline struct brw_reg
919 vec8(struct brw_reg reg
)
921 return stride(reg
, 8,8,1);
924 static inline struct brw_reg
925 vec4(struct brw_reg reg
)
927 return stride(reg
, 4,4,1);
930 static inline struct brw_reg
931 vec2(struct brw_reg reg
)
933 return stride(reg
, 2,2,1);
936 static inline struct brw_reg
937 vec1(struct brw_reg reg
)
939 return stride(reg
, 0,1,0);
943 static inline struct brw_reg
944 get_element(struct brw_reg reg
, unsigned elt
)
946 return vec1(suboffset(reg
, elt
));
949 static inline struct brw_reg
950 get_element_ud(struct brw_reg reg
, unsigned elt
)
952 return vec1(suboffset(retype(reg
, BRW_REGISTER_TYPE_UD
), elt
));
955 static inline struct brw_reg
956 get_element_d(struct brw_reg reg
, unsigned elt
)
958 return vec1(suboffset(retype(reg
, BRW_REGISTER_TYPE_D
), elt
));
961 static inline struct brw_reg
962 brw_swizzle(struct brw_reg reg
, unsigned swz
)
964 if (reg
.file
== BRW_IMMEDIATE_VALUE
)
965 reg
.ud
= brw_swizzle_immediate(reg
.type
, reg
.ud
, swz
);
967 reg
.swizzle
= brw_compose_swizzle(swz
, reg
.swizzle
);
972 static inline struct brw_reg
973 brw_writemask(struct brw_reg reg
, unsigned mask
)
975 assert(reg
.file
!= BRW_IMMEDIATE_VALUE
);
976 reg
.writemask
&= mask
;
980 static inline struct brw_reg
981 brw_set_writemask(struct brw_reg reg
, unsigned mask
)
983 assert(reg
.file
!= BRW_IMMEDIATE_VALUE
);
984 reg
.writemask
= mask
;
988 static inline unsigned
989 brw_writemask_for_size(unsigned n
)
994 static inline unsigned
995 brw_writemask_for_component_packing(unsigned n
, unsigned first_component
)
997 assert(first_component
+ n
<= 4);
998 return (((1 << n
) - 1) << first_component
);
1001 static inline struct brw_reg
1002 negate(struct brw_reg reg
)
1008 static inline struct brw_reg
1009 brw_abs(struct brw_reg reg
)
1016 /************************************************************************/
1018 static inline struct brw_reg
1019 brw_vec4_indirect(unsigned subnr
, int offset
)
1021 struct brw_reg reg
= brw_vec4_grf(0, 0);
1023 reg
.address_mode
= BRW_ADDRESS_REGISTER_INDIRECT_REGISTER
;
1024 reg
.indirect_offset
= offset
;
1028 static inline struct brw_reg
1029 brw_vec1_indirect(unsigned subnr
, int offset
)
1031 struct brw_reg reg
= brw_vec1_grf(0, 0);
1033 reg
.address_mode
= BRW_ADDRESS_REGISTER_INDIRECT_REGISTER
;
1034 reg
.indirect_offset
= offset
;
1038 static inline struct brw_reg
1039 brw_VxH_indirect(unsigned subnr
, int offset
)
1041 struct brw_reg reg
= brw_vec1_grf(0, 0);
1042 reg
.vstride
= BRW_VERTICAL_STRIDE_ONE_DIMENSIONAL
;
1044 reg
.address_mode
= BRW_ADDRESS_REGISTER_INDIRECT_REGISTER
;
1045 reg
.indirect_offset
= offset
;
1049 static inline struct brw_reg
1050 deref_4f(struct brw_indirect ptr
, int offset
)
1052 return brw_vec4_indirect(ptr
.addr_subnr
, ptr
.addr_offset
+ offset
);
1055 static inline struct brw_reg
1056 deref_1f(struct brw_indirect ptr
, int offset
)
1058 return brw_vec1_indirect(ptr
.addr_subnr
, ptr
.addr_offset
+ offset
);
1061 static inline struct brw_reg
1062 deref_4b(struct brw_indirect ptr
, int offset
)
1064 return retype(deref_4f(ptr
, offset
), BRW_REGISTER_TYPE_B
);
1067 static inline struct brw_reg
1068 deref_1uw(struct brw_indirect ptr
, int offset
)
1070 return retype(deref_1f(ptr
, offset
), BRW_REGISTER_TYPE_UW
);
1073 static inline struct brw_reg
1074 deref_1d(struct brw_indirect ptr
, int offset
)
1076 return retype(deref_1f(ptr
, offset
), BRW_REGISTER_TYPE_D
);
1079 static inline struct brw_reg
1080 deref_1ud(struct brw_indirect ptr
, int offset
)
1082 return retype(deref_1f(ptr
, offset
), BRW_REGISTER_TYPE_UD
);
1085 static inline struct brw_reg
1086 get_addr_reg(struct brw_indirect ptr
)
1088 return brw_address_reg(ptr
.addr_subnr
);
1091 static inline struct brw_indirect
1092 brw_indirect_offset(struct brw_indirect ptr
, int offset
)
1094 ptr
.addr_offset
+= offset
;
1098 static inline struct brw_indirect
1099 brw_indirect(unsigned addr_subnr
, int offset
)
1101 struct brw_indirect ptr
;
1102 ptr
.addr_subnr
= addr_subnr
;
1103 ptr
.addr_offset
= offset
;
1109 region_matches(struct brw_reg reg
, enum brw_vertical_stride v
,
1110 enum brw_width w
, enum brw_horizontal_stride h
)
1112 return reg
.vstride
== v
&&
1117 #define has_scalar_region(reg) \
1118 region_matches(reg, BRW_VERTICAL_STRIDE_0, BRW_WIDTH_1, \
1119 BRW_HORIZONTAL_STRIDE_0)
1121 /* brw_packed_float.c */
1122 int brw_float_to_vf(float f
);
1123 float brw_vf_to_float(unsigned char vf
);