2 Copyright (C) Intel Corp. 2006. All Rights Reserved.
3 Intel funded Tungsten Graphics to
4 develop this 3D driver.
6 Permission is hereby granted, free of charge, to any person obtaining
7 a copy of this software and associated documentation files (the
8 "Software"), to deal in the Software without restriction, including
9 without limitation the rights to use, copy, modify, merge, publish,
10 distribute, sublicense, and/or sell copies of the Software, and to
11 permit persons to whom the Software is furnished to do so, subject to
12 the following conditions:
14 The above copyright notice and this permission notice (including the
15 next paragraph) shall be included in all copies or substantial
16 portions of the Software.
18 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
19 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
20 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
21 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
22 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
23 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
24 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
26 **********************************************************************/
29 * Keith Whitwell <keithw@vmware.com>
34 * This file defines struct brw_reg, which is our representation for EU
35 * registers. They're not a hardware specific format, just an abstraction
36 * that intends to capture the full flexibility of the hardware registers.
38 * The brw_eu_emit.c layer's brw_set_dest/brw_set_src[01] functions encode
39 * the abstract brw_reg type into the actual hardware instruction encoding.
46 #include "util/compiler.h"
47 #include "main/macros.h"
48 #include "program/prog_instruction.h"
49 #include "brw_eu_defines.h"
50 #include "brw_reg_type.h"
56 struct gen_device_info
;
58 /** Number of general purpose registers (VS, WM, etc) */
59 #define BRW_MAX_GRF 128
62 * First GRF used for the MRF hack.
64 * On gen7, MRFs are no longer used, and contiguous GRFs are used instead. We
65 * haven't converted our compiler to be aware of this, so it asks for MRFs and
66 * brw_eu_emit.c quietly converts them to be accesses of the top GRFs. The
67 * register allocators have to be careful of this to avoid corrupting the "MRF"s
68 * with actual GRF allocations.
70 #define GEN7_MRF_HACK_START 112
72 /** Number of message register file registers */
73 #define BRW_MAX_MRF(gen) (gen == 6 ? 24 : 16)
75 #define BRW_SWIZZLE4(a,b,c,d) (((a)<<0) | ((b)<<2) | ((c)<<4) | ((d)<<6))
76 #define BRW_GET_SWZ(swz, idx) (((swz) >> ((idx)*2)) & 0x3)
78 #define BRW_SWIZZLE_NOOP BRW_SWIZZLE4(0,1,2,3)
79 #define BRW_SWIZZLE_XYZW BRW_SWIZZLE4(0,1,2,3)
80 #define BRW_SWIZZLE_XXXX BRW_SWIZZLE4(0,0,0,0)
81 #define BRW_SWIZZLE_YYYY BRW_SWIZZLE4(1,1,1,1)
82 #define BRW_SWIZZLE_ZZZZ BRW_SWIZZLE4(2,2,2,2)
83 #define BRW_SWIZZLE_WWWW BRW_SWIZZLE4(3,3,3,3)
84 #define BRW_SWIZZLE_XYXY BRW_SWIZZLE4(0,1,0,1)
85 #define BRW_SWIZZLE_YXYX BRW_SWIZZLE4(1,0,1,0)
86 #define BRW_SWIZZLE_XZXZ BRW_SWIZZLE4(0,2,0,2)
87 #define BRW_SWIZZLE_YZXW BRW_SWIZZLE4(1,2,0,3)
88 #define BRW_SWIZZLE_YWYW BRW_SWIZZLE4(1,3,1,3)
89 #define BRW_SWIZZLE_ZXYW BRW_SWIZZLE4(2,0,1,3)
90 #define BRW_SWIZZLE_ZWZW BRW_SWIZZLE4(2,3,2,3)
91 #define BRW_SWIZZLE_WZWZ BRW_SWIZZLE4(3,2,3,2)
92 #define BRW_SWIZZLE_WZYX BRW_SWIZZLE4(3,2,1,0)
93 #define BRW_SWIZZLE_XXZZ BRW_SWIZZLE4(0,0,2,2)
94 #define BRW_SWIZZLE_YYWW BRW_SWIZZLE4(1,1,3,3)
95 #define BRW_SWIZZLE_YXWZ BRW_SWIZZLE4(1,0,3,2)
97 #define BRW_SWZ_COMP_INPUT(comp) (BRW_SWIZZLE_XYZW >> ((comp)*2))
98 #define BRW_SWZ_COMP_OUTPUT(comp) (BRW_SWIZZLE_XYZW << ((comp)*2))
101 brw_is_single_value_swizzle(unsigned swiz
)
103 return (swiz
== BRW_SWIZZLE_XXXX
||
104 swiz
== BRW_SWIZZLE_YYYY
||
105 swiz
== BRW_SWIZZLE_ZZZZ
||
106 swiz
== BRW_SWIZZLE_WWWW
);
110 * Compute the swizzle obtained from the application of \p swz0 on the result
111 * of \p swz1. The argument ordering is expected to match function
114 static inline unsigned
115 brw_compose_swizzle(unsigned swz0
, unsigned swz1
)
118 BRW_GET_SWZ(swz1
, BRW_GET_SWZ(swz0
, 0)),
119 BRW_GET_SWZ(swz1
, BRW_GET_SWZ(swz0
, 1)),
120 BRW_GET_SWZ(swz1
, BRW_GET_SWZ(swz0
, 2)),
121 BRW_GET_SWZ(swz1
, BRW_GET_SWZ(swz0
, 3)));
125 * Return the result of applying swizzle \p swz to shuffle the bits of \p mask
128 static inline unsigned
129 brw_apply_swizzle_to_mask(unsigned swz
, unsigned mask
)
133 for (unsigned i
= 0; i
< 4; i
++) {
134 if (mask
& (1 << BRW_GET_SWZ(swz
, i
)))
142 * Return the result of applying the inverse of swizzle \p swz to shuffle the
143 * bits of \p mask (AKA preimage). Useful to find out which components are
144 * read from a swizzled source given the instruction writemask.
146 static inline unsigned
147 brw_apply_inv_swizzle_to_mask(unsigned swz
, unsigned mask
)
151 for (unsigned i
= 0; i
< 4; i
++) {
153 result
|= 1 << BRW_GET_SWZ(swz
, i
);
160 * Construct an identity swizzle for the set of enabled channels given by \p
161 * mask. The result will only reference channels enabled in the provided \p
162 * mask, assuming that \p mask is non-zero. The constructed swizzle will
163 * satisfy the property that for any instruction OP and any mask:
165 * brw_OP(p, brw_writemask(dst, mask),
166 * brw_swizzle(src, brw_swizzle_for_mask(mask)));
168 * will be equivalent to the same instruction without swizzle:
170 * brw_OP(p, brw_writemask(dst, mask), src);
172 static inline unsigned
173 brw_swizzle_for_mask(unsigned mask
)
175 unsigned last
= (mask
? ffs(mask
) - 1 : 0);
178 for (unsigned i
= 0; i
< 4; i
++)
179 last
= swz
[i
] = (mask
& (1 << i
) ? i
: last
);
181 return BRW_SWIZZLE4(swz
[0], swz
[1], swz
[2], swz
[3]);
185 * Construct an identity swizzle for the first \p n components of a vector.
186 * When only a subset of channels of a vec4 are used we don't want to
187 * reference the other channels, as that will tell optimization passes that
188 * those other channels are used.
190 static inline unsigned
191 brw_swizzle_for_size(unsigned n
)
193 return brw_swizzle_for_mask((1 << n
) - 1);
197 * Converse of brw_swizzle_for_mask(). Returns the mask of components
198 * accessed by the specified swizzle \p swz.
200 static inline unsigned
201 brw_mask_for_swizzle(unsigned swz
)
203 return brw_apply_inv_swizzle_to_mask(swz
, ~0);
206 uint32_t brw_swizzle_immediate(enum brw_reg_type type
, uint32_t x
, unsigned swz
);
208 #define REG_SIZE (8*4)
210 /* These aren't hardware structs, just something useful for us to pass around:
212 * Align1 operation has a lot of control over input ranges. Used in
213 * WM programs to implement shaders decomposed into "channel serial"
214 * or "structure of array" form:
219 enum brw_reg_type type
:4;
220 enum brw_reg_file file
:3; /* :2 hardware format */
221 unsigned negate
:1; /* source only */
222 unsigned abs
:1; /* source only */
223 unsigned address_mode
:1; /* relative addressing, hopefully! */
225 unsigned subnr
:5; /* :1 in align16 */
233 unsigned swizzle
:8; /* src only, align16 only */
234 unsigned writemask
:4; /* dest only, align16 only */
235 int indirect_offset
:10; /* relative addressing offset */
236 unsigned vstride
:4; /* source only */
237 unsigned width
:3; /* src only, align1 only */
238 unsigned hstride
:2; /* align1 only */
252 brw_regs_equal(const struct brw_reg
*a
, const struct brw_reg
*b
)
254 return a
->bits
== b
->bits
&& a
->u64
== b
->u64
;
258 brw_regs_negative_equal(const struct brw_reg
*a
, const struct brw_reg
*b
)
260 if (a
->file
== IMM
) {
261 if (a
->bits
!= b
->bits
)
264 switch ((enum brw_reg_type
) a
->type
) {
265 case BRW_REGISTER_TYPE_UQ
:
266 case BRW_REGISTER_TYPE_Q
:
267 return a
->d64
== -b
->d64
;
268 case BRW_REGISTER_TYPE_DF
:
269 return a
->df
== -b
->df
;
270 case BRW_REGISTER_TYPE_UD
:
271 case BRW_REGISTER_TYPE_D
:
272 return a
->d
== -b
->d
;
273 case BRW_REGISTER_TYPE_F
:
274 return a
->f
== -b
->f
;
275 case BRW_REGISTER_TYPE_VF
:
276 /* It is tempting to treat 0 as a negation of 0 (and -0 as a negation
277 * of -0). There are occasions where 0 or -0 is used and the exact
278 * bit pattern is desired. At the very least, changing this to allow
279 * 0 as a negation of 0 causes some fp64 tests to fail on IVB.
281 return a
->ud
== (b
->ud
^ 0x80808080);
282 case BRW_REGISTER_TYPE_UW
:
283 case BRW_REGISTER_TYPE_W
:
284 case BRW_REGISTER_TYPE_UV
:
285 case BRW_REGISTER_TYPE_V
:
286 case BRW_REGISTER_TYPE_HF
:
287 /* FINISHME: Implement support for these types once there is
288 * something in the compiler that can generate them. Until then,
289 * they cannot be tested.
292 case BRW_REGISTER_TYPE_UB
:
293 case BRW_REGISTER_TYPE_B
:
294 case BRW_REGISTER_TYPE_NF
:
296 unreachable("not reached");
299 struct brw_reg tmp
= *a
;
301 tmp
.negate
= !tmp
.negate
;
303 return brw_regs_equal(&tmp
, b
);
307 struct brw_indirect
{
308 unsigned addr_subnr
:4;
314 static inline unsigned
315 type_sz(unsigned type
)
318 case BRW_REGISTER_TYPE_UQ
:
319 case BRW_REGISTER_TYPE_Q
:
320 case BRW_REGISTER_TYPE_DF
:
321 case BRW_REGISTER_TYPE_NF
:
323 case BRW_REGISTER_TYPE_UD
:
324 case BRW_REGISTER_TYPE_D
:
325 case BRW_REGISTER_TYPE_F
:
326 case BRW_REGISTER_TYPE_VF
:
328 case BRW_REGISTER_TYPE_UW
:
329 case BRW_REGISTER_TYPE_W
:
330 case BRW_REGISTER_TYPE_UV
:
331 case BRW_REGISTER_TYPE_V
:
332 case BRW_REGISTER_TYPE_HF
:
334 case BRW_REGISTER_TYPE_UB
:
335 case BRW_REGISTER_TYPE_B
:
338 unreachable("not reached");
342 static inline enum brw_reg_type
343 get_exec_type(const enum brw_reg_type type
)
346 case BRW_REGISTER_TYPE_B
:
347 case BRW_REGISTER_TYPE_V
:
348 return BRW_REGISTER_TYPE_W
;
349 case BRW_REGISTER_TYPE_UB
:
350 case BRW_REGISTER_TYPE_UV
:
351 return BRW_REGISTER_TYPE_UW
;
352 case BRW_REGISTER_TYPE_VF
:
353 return BRW_REGISTER_TYPE_F
;
360 * Return an integer type of the requested size and signedness.
362 static inline enum brw_reg_type
363 brw_int_type(unsigned sz
, bool is_signed
)
367 return (is_signed
? BRW_REGISTER_TYPE_B
: BRW_REGISTER_TYPE_UB
);
369 return (is_signed
? BRW_REGISTER_TYPE_W
: BRW_REGISTER_TYPE_UW
);
371 return (is_signed
? BRW_REGISTER_TYPE_D
: BRW_REGISTER_TYPE_UD
);
373 return (is_signed
? BRW_REGISTER_TYPE_Q
: BRW_REGISTER_TYPE_UQ
);
375 unreachable("Not reached.");
380 type_is_unsigned_int(enum brw_reg_type tp
)
382 return tp
== BRW_REGISTER_TYPE_UB
||
383 tp
== BRW_REGISTER_TYPE_UW
||
384 tp
== BRW_REGISTER_TYPE_UD
||
385 tp
== BRW_REGISTER_TYPE_UQ
;
389 * Construct a brw_reg.
390 * \param file one of the BRW_x_REGISTER_FILE values
391 * \param nr register number/index
392 * \param subnr register sub number
393 * \param negate register negate modifier
394 * \param abs register abs modifier
395 * \param type one of BRW_REGISTER_TYPE_x
396 * \param vstride one of BRW_VERTICAL_STRIDE_x
397 * \param width one of BRW_WIDTH_x
398 * \param hstride one of BRW_HORIZONTAL_STRIDE_x
399 * \param swizzle one of BRW_SWIZZLE_x
400 * \param writemask WRITEMASK_X/Y/Z/W bitfield
402 static inline struct brw_reg
403 brw_reg(enum brw_reg_file file
,
408 enum brw_reg_type type
,
416 if (file
== BRW_GENERAL_REGISTER_FILE
)
417 assert(nr
< BRW_MAX_GRF
);
418 else if (file
== BRW_ARCHITECTURE_REGISTER_FILE
)
419 assert(nr
<= BRW_ARF_TIMESTAMP
);
420 /* Asserting on the MRF register number requires to know the hardware gen
421 * (gen6 has 24 MRF registers), which we don't know here, so we assert
422 * for that in the generators and in brw_eu_emit.c
429 reg
.address_mode
= BRW_ADDRESS_DIRECT
;
431 reg
.subnr
= subnr
* type_sz(type
);
434 /* Could do better: If the reg is r5.3<0;1,0>, we probably want to
435 * set swizzle and writemask to W, as the lower bits of subnr will
436 * be lost when converted to align16. This is probably too much to
437 * keep track of as you'd want it adjusted by suboffset(), etc.
438 * Perhaps fix up when converting to align16?
440 reg
.swizzle
= swizzle
;
441 reg
.writemask
= writemask
;
442 reg
.indirect_offset
= 0;
443 reg
.vstride
= vstride
;
445 reg
.hstride
= hstride
;
450 /** Construct float[16] register */
451 static inline struct brw_reg
452 brw_vec16_reg(enum brw_reg_file file
, unsigned nr
, unsigned subnr
)
460 BRW_VERTICAL_STRIDE_16
,
462 BRW_HORIZONTAL_STRIDE_1
,
467 /** Construct float[8] register */
468 static inline struct brw_reg
469 brw_vec8_reg(enum brw_reg_file file
, unsigned nr
, unsigned subnr
)
477 BRW_VERTICAL_STRIDE_8
,
479 BRW_HORIZONTAL_STRIDE_1
,
484 /** Construct float[4] register */
485 static inline struct brw_reg
486 brw_vec4_reg(enum brw_reg_file file
, unsigned nr
, unsigned subnr
)
494 BRW_VERTICAL_STRIDE_4
,
496 BRW_HORIZONTAL_STRIDE_1
,
501 /** Construct float[2] register */
502 static inline struct brw_reg
503 brw_vec2_reg(enum brw_reg_file file
, unsigned nr
, unsigned subnr
)
511 BRW_VERTICAL_STRIDE_2
,
513 BRW_HORIZONTAL_STRIDE_1
,
518 /** Construct float[1] register */
519 static inline struct brw_reg
520 brw_vec1_reg(enum brw_reg_file file
, unsigned nr
, unsigned subnr
)
528 BRW_VERTICAL_STRIDE_0
,
530 BRW_HORIZONTAL_STRIDE_0
,
535 static inline struct brw_reg
536 brw_vecn_reg(unsigned width
, enum brw_reg_file file
,
537 unsigned nr
, unsigned subnr
)
541 return brw_vec1_reg(file
, nr
, subnr
);
543 return brw_vec2_reg(file
, nr
, subnr
);
545 return brw_vec4_reg(file
, nr
, subnr
);
547 return brw_vec8_reg(file
, nr
, subnr
);
549 return brw_vec16_reg(file
, nr
, subnr
);
551 unreachable("Invalid register width");
555 static inline struct brw_reg
556 retype(struct brw_reg reg
, enum brw_reg_type type
)
562 static inline struct brw_reg
563 firsthalf(struct brw_reg reg
)
568 static inline struct brw_reg
569 sechalf(struct brw_reg reg
)
576 static inline struct brw_reg
577 offset(struct brw_reg reg
, unsigned delta
)
584 static inline struct brw_reg
585 byte_offset(struct brw_reg reg
, unsigned bytes
)
587 unsigned newoffset
= reg
.nr
* REG_SIZE
+ reg
.subnr
+ bytes
;
588 reg
.nr
= newoffset
/ REG_SIZE
;
589 reg
.subnr
= newoffset
% REG_SIZE
;
593 static inline struct brw_reg
594 suboffset(struct brw_reg reg
, unsigned delta
)
596 return byte_offset(reg
, delta
* type_sz(reg
.type
));
599 /** Construct unsigned word[16] register */
600 static inline struct brw_reg
601 brw_uw16_reg(enum brw_reg_file file
, unsigned nr
, unsigned subnr
)
603 return suboffset(retype(brw_vec16_reg(file
, nr
, 0), BRW_REGISTER_TYPE_UW
), subnr
);
606 /** Construct unsigned word[8] register */
607 static inline struct brw_reg
608 brw_uw8_reg(enum brw_reg_file file
, unsigned nr
, unsigned subnr
)
610 return suboffset(retype(brw_vec8_reg(file
, nr
, 0), BRW_REGISTER_TYPE_UW
), subnr
);
613 /** Construct unsigned word[1] register */
614 static inline struct brw_reg
615 brw_uw1_reg(enum brw_reg_file file
, unsigned nr
, unsigned subnr
)
617 return suboffset(retype(brw_vec1_reg(file
, nr
, 0), BRW_REGISTER_TYPE_UW
), subnr
);
620 static inline struct brw_reg
621 brw_ud1_reg(enum brw_reg_file file
, unsigned nr
, unsigned subnr
)
623 return retype(brw_vec1_reg(file
, nr
, subnr
), BRW_REGISTER_TYPE_UD
);
626 static inline struct brw_reg
627 brw_imm_reg(enum brw_reg_type type
)
629 return brw_reg(BRW_IMMEDIATE_VALUE
,
635 BRW_VERTICAL_STRIDE_0
,
637 BRW_HORIZONTAL_STRIDE_0
,
642 /** Construct float immediate register */
643 static inline struct brw_reg
644 brw_imm_df(double df
)
646 struct brw_reg imm
= brw_imm_reg(BRW_REGISTER_TYPE_DF
);
651 static inline struct brw_reg
652 brw_imm_u64(uint64_t u64
)
654 struct brw_reg imm
= brw_imm_reg(BRW_REGISTER_TYPE_UQ
);
659 static inline struct brw_reg
662 struct brw_reg imm
= brw_imm_reg(BRW_REGISTER_TYPE_F
);
667 /** Construct int64_t immediate register */
668 static inline struct brw_reg
671 struct brw_reg imm
= brw_imm_reg(BRW_REGISTER_TYPE_Q
);
676 /** Construct int64_t immediate register */
677 static inline struct brw_reg
678 brw_imm_uq(uint64_t uq
)
680 struct brw_reg imm
= brw_imm_reg(BRW_REGISTER_TYPE_UQ
);
685 /** Construct integer immediate register */
686 static inline struct brw_reg
689 struct brw_reg imm
= brw_imm_reg(BRW_REGISTER_TYPE_D
);
694 /** Construct uint immediate register */
695 static inline struct brw_reg
696 brw_imm_ud(unsigned ud
)
698 struct brw_reg imm
= brw_imm_reg(BRW_REGISTER_TYPE_UD
);
703 /** Construct ushort immediate register */
704 static inline struct brw_reg
705 brw_imm_uw(uint16_t uw
)
707 struct brw_reg imm
= brw_imm_reg(BRW_REGISTER_TYPE_UW
);
708 imm
.ud
= uw
| (uw
<< 16);
712 /** Construct short immediate register */
713 static inline struct brw_reg
716 struct brw_reg imm
= brw_imm_reg(BRW_REGISTER_TYPE_W
);
717 imm
.ud
= (uint16_t)w
| (uint32_t)(uint16_t)w
<< 16;
721 /* brw_imm_b and brw_imm_ub aren't supported by hardware - the type
722 * numbers alias with _V and _VF below:
725 /** Construct vector of eight signed half-byte values */
726 static inline struct brw_reg
727 brw_imm_v(unsigned v
)
729 struct brw_reg imm
= brw_imm_reg(BRW_REGISTER_TYPE_V
);
734 /** Construct vector of eight unsigned half-byte values */
735 static inline struct brw_reg
736 brw_imm_uv(unsigned uv
)
738 struct brw_reg imm
= brw_imm_reg(BRW_REGISTER_TYPE_UV
);
743 /** Construct vector of four 8-bit float values */
744 static inline struct brw_reg
745 brw_imm_vf(unsigned v
)
747 struct brw_reg imm
= brw_imm_reg(BRW_REGISTER_TYPE_VF
);
752 static inline struct brw_reg
753 brw_imm_vf4(unsigned v0
, unsigned v1
, unsigned v2
, unsigned v3
)
755 struct brw_reg imm
= brw_imm_reg(BRW_REGISTER_TYPE_VF
);
756 imm
.vstride
= BRW_VERTICAL_STRIDE_0
;
757 imm
.width
= BRW_WIDTH_4
;
758 imm
.hstride
= BRW_HORIZONTAL_STRIDE_1
;
759 imm
.ud
= ((v0
<< 0) | (v1
<< 8) | (v2
<< 16) | (v3
<< 24));
764 static inline struct brw_reg
765 brw_address(struct brw_reg reg
)
767 return brw_imm_uw(reg
.nr
* REG_SIZE
+ reg
.subnr
);
770 /** Construct float[1] general-purpose register */
771 static inline struct brw_reg
772 brw_vec1_grf(unsigned nr
, unsigned subnr
)
774 return brw_vec1_reg(BRW_GENERAL_REGISTER_FILE
, nr
, subnr
);
777 /** Construct float[2] general-purpose register */
778 static inline struct brw_reg
779 brw_vec2_grf(unsigned nr
, unsigned subnr
)
781 return brw_vec2_reg(BRW_GENERAL_REGISTER_FILE
, nr
, subnr
);
784 /** Construct float[4] general-purpose register */
785 static inline struct brw_reg
786 brw_vec4_grf(unsigned nr
, unsigned subnr
)
788 return brw_vec4_reg(BRW_GENERAL_REGISTER_FILE
, nr
, subnr
);
791 /** Construct float[8] general-purpose register */
792 static inline struct brw_reg
793 brw_vec8_grf(unsigned nr
, unsigned subnr
)
795 return brw_vec8_reg(BRW_GENERAL_REGISTER_FILE
, nr
, subnr
);
798 /** Construct float[16] general-purpose register */
799 static inline struct brw_reg
800 brw_vec16_grf(unsigned nr
, unsigned subnr
)
802 return brw_vec16_reg(BRW_GENERAL_REGISTER_FILE
, nr
, subnr
);
805 static inline struct brw_reg
806 brw_vecn_grf(unsigned width
, unsigned nr
, unsigned subnr
)
808 return brw_vecn_reg(width
, BRW_GENERAL_REGISTER_FILE
, nr
, subnr
);
812 static inline struct brw_reg
813 brw_uw8_grf(unsigned nr
, unsigned subnr
)
815 return brw_uw8_reg(BRW_GENERAL_REGISTER_FILE
, nr
, subnr
);
818 static inline struct brw_reg
819 brw_uw16_grf(unsigned nr
, unsigned subnr
)
821 return brw_uw16_reg(BRW_GENERAL_REGISTER_FILE
, nr
, subnr
);
825 /** Construct null register (usually used for setting condition codes) */
826 static inline struct brw_reg
829 return brw_vec8_reg(BRW_ARCHITECTURE_REGISTER_FILE
, BRW_ARF_NULL
, 0);
832 static inline struct brw_reg
833 brw_null_vec(unsigned width
)
835 return brw_vecn_reg(width
, BRW_ARCHITECTURE_REGISTER_FILE
, BRW_ARF_NULL
, 0);
838 static inline struct brw_reg
839 brw_address_reg(unsigned subnr
)
841 return brw_uw1_reg(BRW_ARCHITECTURE_REGISTER_FILE
, BRW_ARF_ADDRESS
, subnr
);
844 static inline struct brw_reg
847 return brw_uw1_reg(BRW_ARCHITECTURE_REGISTER_FILE
, BRW_ARF_TDR
, 0);
850 /* If/else instructions break in align16 mode if writemask & swizzle
851 * aren't xyzw. This goes against the convention for other scalar
854 static inline struct brw_reg
857 return brw_reg(BRW_ARCHITECTURE_REGISTER_FILE
,
862 BRW_REGISTER_TYPE_UD
,
863 BRW_VERTICAL_STRIDE_4
, /* ? */
865 BRW_HORIZONTAL_STRIDE_0
,
866 BRW_SWIZZLE_XYZW
, /* NOTE! */
867 WRITEMASK_XYZW
); /* NOTE! */
870 static inline struct brw_reg
871 brw_notification_reg(void)
873 return brw_reg(BRW_ARCHITECTURE_REGISTER_FILE
,
874 BRW_ARF_NOTIFICATION_COUNT
,
878 BRW_REGISTER_TYPE_UD
,
879 BRW_VERTICAL_STRIDE_0
,
881 BRW_HORIZONTAL_STRIDE_0
,
886 static inline struct brw_reg
887 brw_cr0_reg(unsigned subnr
)
889 return brw_ud1_reg(BRW_ARCHITECTURE_REGISTER_FILE
, BRW_ARF_CONTROL
, subnr
);
892 static inline struct brw_reg
893 brw_sr0_reg(unsigned subnr
)
895 return brw_ud1_reg(BRW_ARCHITECTURE_REGISTER_FILE
, BRW_ARF_STATE
, subnr
);
898 static inline struct brw_reg
899 brw_acc_reg(unsigned width
)
901 return brw_vecn_reg(width
, BRW_ARCHITECTURE_REGISTER_FILE
,
902 BRW_ARF_ACCUMULATOR
, 0);
905 static inline struct brw_reg
906 brw_flag_reg(int reg
, int subreg
)
908 return brw_uw1_reg(BRW_ARCHITECTURE_REGISTER_FILE
,
909 BRW_ARF_FLAG
+ reg
, subreg
);
912 static inline struct brw_reg
913 brw_flag_subreg(unsigned subreg
)
915 return brw_uw1_reg(BRW_ARCHITECTURE_REGISTER_FILE
,
916 BRW_ARF_FLAG
+ subreg
/ 2, subreg
% 2);
920 * Return the mask register present in Gen4-5, or the related register present
921 * in Gen7.5 and later hardware referred to as "channel enable" register in
924 static inline struct brw_reg
925 brw_mask_reg(unsigned subnr
)
927 return brw_uw1_reg(BRW_ARCHITECTURE_REGISTER_FILE
, BRW_ARF_MASK
, subnr
);
930 static inline struct brw_reg
933 return brw_sr0_reg(3);
936 static inline struct brw_reg
939 return brw_sr0_reg(2);
942 static inline struct brw_reg
943 brw_mask_stack_reg(unsigned subnr
)
945 return suboffset(retype(brw_vec16_reg(BRW_ARCHITECTURE_REGISTER_FILE
,
946 BRW_ARF_MASK_STACK
, 0),
947 BRW_REGISTER_TYPE_UB
), subnr
);
950 static inline struct brw_reg
951 brw_mask_stack_depth_reg(unsigned subnr
)
953 return brw_uw1_reg(BRW_ARCHITECTURE_REGISTER_FILE
,
954 BRW_ARF_MASK_STACK_DEPTH
, subnr
);
957 static inline struct brw_reg
958 brw_message_reg(unsigned nr
)
960 return brw_vec8_reg(BRW_MESSAGE_REGISTER_FILE
, nr
, 0);
963 static inline struct brw_reg
964 brw_uvec_mrf(unsigned width
, unsigned nr
, unsigned subnr
)
966 return retype(brw_vecn_reg(width
, BRW_MESSAGE_REGISTER_FILE
, nr
, subnr
),
967 BRW_REGISTER_TYPE_UD
);
970 /* This is almost always called with a numeric constant argument, so
971 * make things easy to evaluate at compile time:
973 static inline unsigned cvt(unsigned val
)
987 static inline struct brw_reg
988 stride(struct brw_reg reg
, unsigned vstride
, unsigned width
, unsigned hstride
)
990 reg
.vstride
= cvt(vstride
);
991 reg
.width
= cvt(width
) - 1;
992 reg
.hstride
= cvt(hstride
);
997 * Multiply the vertical and horizontal stride of a register by the given
1000 static inline struct brw_reg
1001 spread(struct brw_reg reg
, unsigned s
)
1004 assert(util_is_power_of_two_nonzero(s
));
1007 reg
.hstride
+= cvt(s
) - 1;
1010 reg
.vstride
+= cvt(s
) - 1;
1014 return stride(reg
, 0, 1, 0);
1019 * Reinterpret each channel of register \p reg as a vector of values of the
1020 * given smaller type and take the i-th subcomponent from each.
1022 static inline struct brw_reg
1023 subscript(struct brw_reg reg
, enum brw_reg_type type
, unsigned i
)
1025 if (reg
.file
== IMM
)
1028 unsigned scale
= type_sz(reg
.type
) / type_sz(type
);
1029 assert(scale
>= 1 && i
< scale
);
1031 return suboffset(retype(spread(reg
, scale
), type
), i
);
1034 static inline struct brw_reg
1035 vec16(struct brw_reg reg
)
1037 return stride(reg
, 16,16,1);
1040 static inline struct brw_reg
1041 vec8(struct brw_reg reg
)
1043 return stride(reg
, 8,8,1);
1046 static inline struct brw_reg
1047 vec4(struct brw_reg reg
)
1049 return stride(reg
, 4,4,1);
1052 static inline struct brw_reg
1053 vec2(struct brw_reg reg
)
1055 return stride(reg
, 2,2,1);
1058 static inline struct brw_reg
1059 vec1(struct brw_reg reg
)
1061 return stride(reg
, 0,1,0);
1065 static inline struct brw_reg
1066 get_element(struct brw_reg reg
, unsigned elt
)
1068 return vec1(suboffset(reg
, elt
));
1071 static inline struct brw_reg
1072 get_element_ud(struct brw_reg reg
, unsigned elt
)
1074 return vec1(suboffset(retype(reg
, BRW_REGISTER_TYPE_UD
), elt
));
1077 static inline struct brw_reg
1078 get_element_d(struct brw_reg reg
, unsigned elt
)
1080 return vec1(suboffset(retype(reg
, BRW_REGISTER_TYPE_D
), elt
));
1083 static inline struct brw_reg
1084 brw_swizzle(struct brw_reg reg
, unsigned swz
)
1086 if (reg
.file
== BRW_IMMEDIATE_VALUE
)
1087 reg
.ud
= brw_swizzle_immediate(reg
.type
, reg
.ud
, swz
);
1089 reg
.swizzle
= brw_compose_swizzle(swz
, reg
.swizzle
);
1094 static inline struct brw_reg
1095 brw_writemask(struct brw_reg reg
, unsigned mask
)
1097 assert(reg
.file
!= BRW_IMMEDIATE_VALUE
);
1098 reg
.writemask
&= mask
;
1102 static inline struct brw_reg
1103 brw_set_writemask(struct brw_reg reg
, unsigned mask
)
1105 assert(reg
.file
!= BRW_IMMEDIATE_VALUE
);
1106 reg
.writemask
= mask
;
1110 static inline unsigned
1111 brw_writemask_for_size(unsigned n
)
1113 return (1 << n
) - 1;
1116 static inline unsigned
1117 brw_writemask_for_component_packing(unsigned n
, unsigned first_component
)
1119 assert(first_component
+ n
<= 4);
1120 return (((1 << n
) - 1) << first_component
);
1123 static inline struct brw_reg
1124 negate(struct brw_reg reg
)
1130 static inline struct brw_reg
1131 brw_abs(struct brw_reg reg
)
1138 /************************************************************************/
1140 static inline struct brw_reg
1141 brw_vec4_indirect(unsigned subnr
, int offset
)
1143 struct brw_reg reg
= brw_vec4_grf(0, 0);
1145 reg
.address_mode
= BRW_ADDRESS_REGISTER_INDIRECT_REGISTER
;
1146 reg
.indirect_offset
= offset
;
1150 static inline struct brw_reg
1151 brw_vec1_indirect(unsigned subnr
, int offset
)
1153 struct brw_reg reg
= brw_vec1_grf(0, 0);
1155 reg
.address_mode
= BRW_ADDRESS_REGISTER_INDIRECT_REGISTER
;
1156 reg
.indirect_offset
= offset
;
1160 static inline struct brw_reg
1161 brw_VxH_indirect(unsigned subnr
, int offset
)
1163 struct brw_reg reg
= brw_vec1_grf(0, 0);
1164 reg
.vstride
= BRW_VERTICAL_STRIDE_ONE_DIMENSIONAL
;
1166 reg
.address_mode
= BRW_ADDRESS_REGISTER_INDIRECT_REGISTER
;
1167 reg
.indirect_offset
= offset
;
1171 static inline struct brw_reg
1172 deref_4f(struct brw_indirect ptr
, int offset
)
1174 return brw_vec4_indirect(ptr
.addr_subnr
, ptr
.addr_offset
+ offset
);
1177 static inline struct brw_reg
1178 deref_1f(struct brw_indirect ptr
, int offset
)
1180 return brw_vec1_indirect(ptr
.addr_subnr
, ptr
.addr_offset
+ offset
);
1183 static inline struct brw_reg
1184 deref_4b(struct brw_indirect ptr
, int offset
)
1186 return retype(deref_4f(ptr
, offset
), BRW_REGISTER_TYPE_B
);
1189 static inline struct brw_reg
1190 deref_1uw(struct brw_indirect ptr
, int offset
)
1192 return retype(deref_1f(ptr
, offset
), BRW_REGISTER_TYPE_UW
);
1195 static inline struct brw_reg
1196 deref_1d(struct brw_indirect ptr
, int offset
)
1198 return retype(deref_1f(ptr
, offset
), BRW_REGISTER_TYPE_D
);
1201 static inline struct brw_reg
1202 deref_1ud(struct brw_indirect ptr
, int offset
)
1204 return retype(deref_1f(ptr
, offset
), BRW_REGISTER_TYPE_UD
);
1207 static inline struct brw_reg
1208 get_addr_reg(struct brw_indirect ptr
)
1210 return brw_address_reg(ptr
.addr_subnr
);
1213 static inline struct brw_indirect
1214 brw_indirect_offset(struct brw_indirect ptr
, int offset
)
1216 ptr
.addr_offset
+= offset
;
1220 static inline struct brw_indirect
1221 brw_indirect(unsigned addr_subnr
, int offset
)
1223 struct brw_indirect ptr
;
1224 ptr
.addr_subnr
= addr_subnr
;
1225 ptr
.addr_offset
= offset
;
1231 region_matches(struct brw_reg reg
, enum brw_vertical_stride v
,
1232 enum brw_width w
, enum brw_horizontal_stride h
)
1234 return reg
.vstride
== v
&&
1239 #define has_scalar_region(reg) \
1240 region_matches(reg, BRW_VERTICAL_STRIDE_0, BRW_WIDTH_1, \
1241 BRW_HORIZONTAL_STRIDE_0)
1243 /* brw_packed_float.c */
1244 int brw_float_to_vf(float f
);
1245 float brw_vf_to_float(unsigned char vf
);