src/intel/compiler/brw_reg_type.c

   1 /*
   2  * Copyright © 2017 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  */
  23
  24 #include "brw_reg.h"
  25 #include "brw_eu_defines.h"
  26 #include "dev/gen_device_info.h"
  27
  28 #define INVALID (-1)
  29
  30 enum hw_reg_type {
  31    BRW_HW_REG_TYPE_UD  = 0,
  32    BRW_HW_REG_TYPE_D   = 1,
  33    BRW_HW_REG_TYPE_UW  = 2,
  34    BRW_HW_REG_TYPE_W   = 3,
  35    BRW_HW_REG_TYPE_F   = 7,
  36    GEN8_HW_REG_TYPE_UQ = 8,
  37    GEN8_HW_REG_TYPE_Q  = 9,
  38
  39    BRW_HW_REG_TYPE_UB  = 4,
  40    BRW_HW_REG_TYPE_B   = 5,
  41    GEN7_HW_REG_TYPE_DF = 6,
  42    GEN8_HW_REG_TYPE_HF = 10,
  43
  44    GEN11_HW_REG_TYPE_UD = 0,
  45    GEN11_HW_REG_TYPE_D  = 1,
  46    GEN11_HW_REG_TYPE_UW = 2,
  47    GEN11_HW_REG_TYPE_W  = 3,
  48    GEN11_HW_REG_TYPE_UB = 4,
  49    GEN11_HW_REG_TYPE_B  = 5,
  50    GEN11_HW_REG_TYPE_UQ = 6,
  51    GEN11_HW_REG_TYPE_Q  = 7,
  52    GEN11_HW_REG_TYPE_HF = 8,
  53    GEN11_HW_REG_TYPE_F  = 9,
  54    GEN11_HW_REG_TYPE_DF = 10,
  55    GEN11_HW_REG_TYPE_NF = 11,
  56 };
  57
  58 enum hw_imm_type {
  59    BRW_HW_IMM_TYPE_UD  = 0,
  60    BRW_HW_IMM_TYPE_D   = 1,
  61    BRW_HW_IMM_TYPE_UW  = 2,
  62    BRW_HW_IMM_TYPE_W   = 3,
  63    BRW_HW_IMM_TYPE_F   = 7,
  64    GEN8_HW_IMM_TYPE_UQ = 8,
  65    GEN8_HW_IMM_TYPE_Q  = 9,
  66
  67    BRW_HW_IMM_TYPE_UV  = 4,
  68    BRW_HW_IMM_TYPE_VF  = 5,
  69    BRW_HW_IMM_TYPE_V   = 6,
  70    GEN8_HW_IMM_TYPE_DF = 10,
  71    GEN8_HW_IMM_TYPE_HF = 11,
  72
  73    GEN11_HW_IMM_TYPE_UD = 0,
  74    GEN11_HW_IMM_TYPE_D  = 1,
  75    GEN11_HW_IMM_TYPE_UW = 2,
  76    GEN11_HW_IMM_TYPE_W  = 3,
  77    GEN11_HW_IMM_TYPE_UV = 4,
  78    GEN11_HW_IMM_TYPE_V  = 5,
  79    GEN11_HW_IMM_TYPE_UQ = 6,
  80    GEN11_HW_IMM_TYPE_Q  = 7,
  81    GEN11_HW_IMM_TYPE_HF = 8,
  82    GEN11_HW_IMM_TYPE_F  = 9,
  83    GEN11_HW_IMM_TYPE_DF = 10,
  84    GEN11_HW_IMM_TYPE_VF = 11,
  85 };
  86
  87 static const struct hw_type {
  88    enum hw_reg_type reg_type;
  89    enum hw_imm_type imm_type;
  90 } gen4_hw_type[] = {
  91    [0 ... BRW_REGISTER_TYPE_LAST] = {     INVALID, INVALID             },
  92
  93    [BRW_REGISTER_TYPE_DF] = { GEN7_HW_REG_TYPE_DF, GEN8_HW_IMM_TYPE_DF },
  94    [BRW_REGISTER_TYPE_F]  = { BRW_HW_REG_TYPE_F,   BRW_HW_IMM_TYPE_F   },
  95    [BRW_REGISTER_TYPE_HF] = { GEN8_HW_REG_TYPE_HF, GEN8_HW_IMM_TYPE_HF },
  96    [BRW_REGISTER_TYPE_VF] = { INVALID,             BRW_HW_IMM_TYPE_VF  },
  97
  98    [BRW_REGISTER_TYPE_Q]  = { GEN8_HW_REG_TYPE_Q,  GEN8_HW_IMM_TYPE_Q  },
  99    [BRW_REGISTER_TYPE_UQ] = { GEN8_HW_REG_TYPE_UQ, GEN8_HW_IMM_TYPE_UQ },
 100    [BRW_REGISTER_TYPE_D]  = { BRW_HW_REG_TYPE_D,   BRW_HW_IMM_TYPE_D   },
 101    [BRW_REGISTER_TYPE_UD] = { BRW_HW_REG_TYPE_UD,  BRW_HW_IMM_TYPE_UD  },
 102    [BRW_REGISTER_TYPE_W]  = { BRW_HW_REG_TYPE_W,   BRW_HW_IMM_TYPE_W   },
 103    [BRW_REGISTER_TYPE_UW] = { BRW_HW_REG_TYPE_UW,  BRW_HW_IMM_TYPE_UW  },
 104    [BRW_REGISTER_TYPE_B]  = { BRW_HW_REG_TYPE_B,   INVALID             },
 105    [BRW_REGISTER_TYPE_UB] = { BRW_HW_REG_TYPE_UB,  INVALID             },
 106    [BRW_REGISTER_TYPE_V]  = { INVALID,             BRW_HW_IMM_TYPE_V   },
 107    [BRW_REGISTER_TYPE_UV] = { INVALID,             BRW_HW_IMM_TYPE_UV  },
 108 }, gen11_hw_type[] = {
 109    [BRW_REGISTER_TYPE_NF] = { GEN11_HW_REG_TYPE_NF, INVALID              },
 110    [BRW_REGISTER_TYPE_DF] = { GEN11_HW_REG_TYPE_DF, GEN11_HW_IMM_TYPE_DF },
 111    [BRW_REGISTER_TYPE_F]  = { GEN11_HW_REG_TYPE_F,  GEN11_HW_IMM_TYPE_F  },
 112    [BRW_REGISTER_TYPE_HF] = { GEN11_HW_REG_TYPE_HF, GEN11_HW_IMM_TYPE_HF },
 113    [BRW_REGISTER_TYPE_VF] = { INVALID,              GEN11_HW_IMM_TYPE_VF },
 114
 115    [BRW_REGISTER_TYPE_Q]  = { GEN11_HW_REG_TYPE_Q,  GEN11_HW_IMM_TYPE_Q  },
 116    [BRW_REGISTER_TYPE_UQ] = { GEN11_HW_REG_TYPE_UQ, GEN11_HW_IMM_TYPE_UQ },
 117    [BRW_REGISTER_TYPE_D]  = { GEN11_HW_REG_TYPE_D,  GEN11_HW_IMM_TYPE_D  },
 118    [BRW_REGISTER_TYPE_UD] = { GEN11_HW_REG_TYPE_UD, GEN11_HW_IMM_TYPE_UD },
 119    [BRW_REGISTER_TYPE_W]  = { GEN11_HW_REG_TYPE_W,  GEN11_HW_IMM_TYPE_W  },
 120    [BRW_REGISTER_TYPE_UW] = { GEN11_HW_REG_TYPE_UW, GEN11_HW_IMM_TYPE_UW },
 121    [BRW_REGISTER_TYPE_B]  = { GEN11_HW_REG_TYPE_B,  INVALID              },
 122    [BRW_REGISTER_TYPE_UB] = { GEN11_HW_REG_TYPE_UB, INVALID              },
 123    [BRW_REGISTER_TYPE_V]  = { INVALID,              GEN11_HW_IMM_TYPE_V  },
 124    [BRW_REGISTER_TYPE_UV] = { INVALID,              GEN11_HW_IMM_TYPE_UV },
 125 };
 126
 127 /* SNB adds 3-src instructions (MAD and LRP) that only operate on floats, so
 128  * the types were implied. IVB adds BFE and BFI2 that operate on doublewords
 129  * and unsigned doublewords, so a new field is also available in the da3src
 130  * struct (part of struct brw_instruction.bits1 in brw_structs.h) to select
 131  * dst and shared-src types.
 132  *
 133  * CNL adds support for 3-src instructions in align1 mode, and with it support
 134  * for most register types.
 135  */
 136 enum hw_3src_reg_type {
 137    GEN7_3SRC_TYPE_F  = 0,
 138    GEN7_3SRC_TYPE_D  = 1,
 139    GEN7_3SRC_TYPE_UD = 2,
 140    GEN7_3SRC_TYPE_DF = 3,
 141
 142    /** When ExecutionDatatype is 1: @{ */
 143    GEN10_ALIGN1_3SRC_REG_TYPE_HF = 0b000,
 144    GEN10_ALIGN1_3SRC_REG_TYPE_F  = 0b001,
 145    GEN10_ALIGN1_3SRC_REG_TYPE_DF = 0b010,
 146    GEN11_ALIGN1_3SRC_REG_TYPE_NF = 0b011,
 147    /** @} */
 148
 149    /** When ExecutionDatatype is 0: @{ */
 150    GEN10_ALIGN1_3SRC_REG_TYPE_UD = 0b000,
 151    GEN10_ALIGN1_3SRC_REG_TYPE_D  = 0b001,
 152    GEN10_ALIGN1_3SRC_REG_TYPE_UW = 0b010,
 153    GEN10_ALIGN1_3SRC_REG_TYPE_W  = 0b011,
 154    GEN10_ALIGN1_3SRC_REG_TYPE_UB = 0b100,
 155    GEN10_ALIGN1_3SRC_REG_TYPE_B  = 0b101,
 156    /** @} */
 157 };
 158
 159 static const struct hw_3src_type {
 160    enum hw_3src_reg_type reg_type;
 161    enum gen10_align1_3src_exec_type exec_type;
 162 } gen7_hw_3src_type[] = {
 163    [0 ... BRW_REGISTER_TYPE_LAST] = { INVALID },
 164
 165    [BRW_REGISTER_TYPE_F]  = { GEN7_3SRC_TYPE_F  },
 166    [BRW_REGISTER_TYPE_D]  = { GEN7_3SRC_TYPE_D  },
 167    [BRW_REGISTER_TYPE_UD] = { GEN7_3SRC_TYPE_UD },
 168    [BRW_REGISTER_TYPE_DF] = { GEN7_3SRC_TYPE_DF },
 169 }, gen10_hw_3src_align1_type[] = {
 170 #define E(x) BRW_ALIGN1_3SRC_EXEC_TYPE_##x
 171    [0 ... BRW_REGISTER_TYPE_LAST] = { INVALID },
 172
 173    [BRW_REGISTER_TYPE_NF] = { GEN11_ALIGN1_3SRC_REG_TYPE_NF, E(FLOAT) },
 174    [BRW_REGISTER_TYPE_DF] = { GEN10_ALIGN1_3SRC_REG_TYPE_DF, E(FLOAT) },
 175    [BRW_REGISTER_TYPE_F]  = { GEN10_ALIGN1_3SRC_REG_TYPE_F,  E(FLOAT) },
 176    [BRW_REGISTER_TYPE_HF] = { GEN10_ALIGN1_3SRC_REG_TYPE_HF, E(FLOAT) },
 177
 178    [BRW_REGISTER_TYPE_D]  = { GEN10_ALIGN1_3SRC_REG_TYPE_D,  E(INT)   },
 179    [BRW_REGISTER_TYPE_UD] = { GEN10_ALIGN1_3SRC_REG_TYPE_UD, E(INT)   },
 180    [BRW_REGISTER_TYPE_W]  = { GEN10_ALIGN1_3SRC_REG_TYPE_W,  E(INT)   },
 181    [BRW_REGISTER_TYPE_UW] = { GEN10_ALIGN1_3SRC_REG_TYPE_UW, E(INT)   },
 182    [BRW_REGISTER_TYPE_B]  = { GEN10_ALIGN1_3SRC_REG_TYPE_B,  E(INT)   },
 183    [BRW_REGISTER_TYPE_UB] = { GEN10_ALIGN1_3SRC_REG_TYPE_UB, E(INT)   },
 184 #undef E
 185 };
 186
 187 /**
 188  * Convert a brw_reg_type enumeration value into the hardware representation.
 189  *
 190  * The hardware encoding may depend on whether the value is an immediate.
 191  */
 192 unsigned
 193 brw_reg_type_to_hw_type(const struct gen_device_info *devinfo,
 194                         enum brw_reg_file file,
 195                         enum brw_reg_type type)
 196 {
 197    const struct hw_type *table;
 198
 199    if (devinfo->gen >= 11) {
 200       assert(type < ARRAY_SIZE(gen11_hw_type));
 201       table = gen11_hw_type;
 202    } else {
 203       assert(type < ARRAY_SIZE(gen4_hw_type));
 204       table = gen4_hw_type;
 205    }
 206
 207    assert(devinfo->has_64bit_types || brw_reg_type_to_size(type) < 8 ||
 208           type == BRW_REGISTER_TYPE_NF);
 209
 210    if (file == BRW_IMMEDIATE_VALUE) {
 211       assert(table[type].imm_type != (enum hw_imm_type)INVALID);
 212       return table[type].imm_type;
 213    } else {
 214       assert(table[type].reg_type != (enum hw_reg_type)INVALID);
 215       return table[type].reg_type;
 216    }
 217 }
 218
 219 /**
 220  * Convert the hardware representation into a brw_reg_type enumeration value.
 221  *
 222  * The hardware encoding may depend on whether the value is an immediate.
 223  */
 224 enum brw_reg_type
 225 brw_hw_type_to_reg_type(const struct gen_device_info *devinfo,
 226                         enum brw_reg_file file, unsigned hw_type)
 227 {
 228    const struct hw_type *table;
 229
 230    if (devinfo->gen >= 11) {
 231       table = gen11_hw_type;
 232    } else {
 233       table = gen4_hw_type;
 234    }
 235
 236    if (file == BRW_IMMEDIATE_VALUE) {
 237       for (enum brw_reg_type i = 0; i <= BRW_REGISTER_TYPE_LAST; i++) {
 238          if (table[i].imm_type == (enum hw_imm_type)hw_type) {
 239             return i;
 240          }
 241       }
 242    } else {
 243       for (enum brw_reg_type i = 0; i <= BRW_REGISTER_TYPE_LAST; i++) {
 244          if (table[i].reg_type == (enum hw_reg_type)hw_type) {
 245             return i;
 246          }
 247       }
 248    }
 249    unreachable("not reached");
 250 }
 251
 252 /**
 253  * Convert a brw_reg_type enumeration value into the hardware representation
 254  * for a 3-src align16 instruction
 255  */
 256 unsigned
 257 brw_reg_type_to_a16_hw_3src_type(const struct gen_device_info *devinfo,
 258                                  enum brw_reg_type type)
 259 {
 260    assert(type < ARRAY_SIZE(gen7_hw_3src_type));
 261    assert(gen7_hw_3src_type[type].reg_type != (enum hw_3src_reg_type)INVALID);
 262    return gen7_hw_3src_type[type].reg_type;
 263 }
 264
 265 /**
 266  * Convert a brw_reg_type enumeration value into the hardware representation
 267  * for a 3-src align1 instruction
 268  */
 269 unsigned
 270 brw_reg_type_to_a1_hw_3src_type(const struct gen_device_info *devinfo,
 271                                 enum brw_reg_type type)
 272 {
 273    assert(type < ARRAY_SIZE(gen10_hw_3src_align1_type));
 274    assert(gen10_hw_3src_align1_type[type].reg_type != (enum hw_3src_reg_type)INVALID);
 275    return gen10_hw_3src_align1_type[type].reg_type;
 276 }
 277
 278 /**
 279  * Convert the hardware representation for a 3-src align16 instruction into a
 280  * brw_reg_type enumeration value.
 281  */
 282 enum brw_reg_type
 283 brw_a16_hw_3src_type_to_reg_type(const struct gen_device_info *devinfo,
 284                                  unsigned hw_type)
 285 {
 286    for (enum brw_reg_type i = 0; i <= BRW_REGISTER_TYPE_LAST; i++) {
 287       if (gen7_hw_3src_type[i].reg_type == hw_type) {
 288          return i;
 289       }
 290    }
 291    unreachable("not reached");
 292 }
 293
 294 /**
 295  * Convert the hardware representation for a 3-src align1 instruction into a
 296  * brw_reg_type enumeration value.
 297  */
 298 enum brw_reg_type
 299 brw_a1_hw_3src_type_to_reg_type(const struct gen_device_info *devinfo,
 300                                 unsigned hw_type, unsigned exec_type)
 301 {
 302    for (enum brw_reg_type i = 0; i <= BRW_REGISTER_TYPE_LAST; i++) {
 303       if (gen10_hw_3src_align1_type[i].reg_type == hw_type &&
 304           gen10_hw_3src_align1_type[i].exec_type == exec_type) {
 305          return i;
 306       }
 307    }
 308    unreachable("not reached");
 309 }
 310
 311 /**
 312  * Return the element size given a register type.
 313  */
 314 unsigned
 315 brw_reg_type_to_size(enum brw_reg_type type)
 316 {
 317    static const unsigned type_size[] = {
 318       [BRW_REGISTER_TYPE_NF] = 8,
 319       [BRW_REGISTER_TYPE_DF] = 8,
 320       [BRW_REGISTER_TYPE_F]  = 4,
 321       [BRW_REGISTER_TYPE_HF] = 2,
 322       [BRW_REGISTER_TYPE_VF] = 4,
 323
 324       [BRW_REGISTER_TYPE_Q]  = 8,
 325       [BRW_REGISTER_TYPE_UQ] = 8,
 326       [BRW_REGISTER_TYPE_D]  = 4,
 327       [BRW_REGISTER_TYPE_UD] = 4,
 328       [BRW_REGISTER_TYPE_W]  = 2,
 329       [BRW_REGISTER_TYPE_UW] = 2,
 330       [BRW_REGISTER_TYPE_B]  = 1,
 331       [BRW_REGISTER_TYPE_UB] = 1,
 332       [BRW_REGISTER_TYPE_V]  = 2,
 333       [BRW_REGISTER_TYPE_UV] = 2,
 334    };
 335    return type_size[type];
 336 }
 337
 338 /**
 339  * Converts a BRW_REGISTER_TYPE_* enum to a short string (F, UD, and so on).
 340  *
 341  * This is different than reg_encoding from brw_disasm.c in that it operates
 342  * on the abstract enum values, rather than the generation-specific encoding.
 343  */
 344 const char *
 345 brw_reg_type_to_letters(enum brw_reg_type type)
 346 {
 347    static const char letters[][3] = {
 348       [BRW_REGISTER_TYPE_NF] = "NF",
 349       [BRW_REGISTER_TYPE_DF] = "DF",
 350       [BRW_REGISTER_TYPE_F]  = "F",
 351       [BRW_REGISTER_TYPE_HF] = "HF",
 352       [BRW_REGISTER_TYPE_VF] = "VF",
 353
 354       [BRW_REGISTER_TYPE_Q]  = "Q",
 355       [BRW_REGISTER_TYPE_UQ] = "UQ",
 356       [BRW_REGISTER_TYPE_D]  = "D",
 357       [BRW_REGISTER_TYPE_UD] = "UD",
 358       [BRW_REGISTER_TYPE_W]  = "W",
 359       [BRW_REGISTER_TYPE_UW] = "UW",
 360       [BRW_REGISTER_TYPE_B]  = "B",
 361       [BRW_REGISTER_TYPE_UB] = "UB",
 362       [BRW_REGISTER_TYPE_V]  = "V",
 363       [BRW_REGISTER_TYPE_UV] = "UV",
 364    };
 365    assert(type < ARRAY_SIZE(letters));
 366    return letters[type];
 367 }