7dbff8f08f22df6f09454a147761a1dc4e8a9fd9
[mesa.git] / src / intel / compiler / brw_reg_type.c
1 /*
2 * Copyright © 2017 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 */
23
24 #include "brw_reg.h"
25 #include "brw_eu_defines.h"
26 #include "common/gen_device_info.h"
27
28 #define INVALID (-1)
29
30 static const struct {
31 enum hw_reg_type reg_type;
32 enum hw_imm_type imm_type;
33 } gen4_hw_type[] = {
34 [BRW_REGISTER_TYPE_DF] = { GEN7_HW_REG_TYPE_DF, GEN8_HW_IMM_TYPE_DF },
35 [BRW_REGISTER_TYPE_F] = { BRW_HW_REG_TYPE_F, BRW_HW_IMM_TYPE_F },
36 [BRW_REGISTER_TYPE_HF] = { GEN8_HW_REG_TYPE_HF, GEN8_HW_IMM_TYPE_HF },
37 [BRW_REGISTER_TYPE_VF] = { INVALID, BRW_HW_IMM_TYPE_VF },
38
39 [BRW_REGISTER_TYPE_Q] = { GEN8_HW_REG_TYPE_Q, GEN8_HW_IMM_TYPE_Q },
40 [BRW_REGISTER_TYPE_UQ] = { GEN8_HW_REG_TYPE_UQ, GEN8_HW_IMM_TYPE_UQ },
41 [BRW_REGISTER_TYPE_D] = { BRW_HW_REG_TYPE_D, BRW_HW_IMM_TYPE_D },
42 [BRW_REGISTER_TYPE_UD] = { BRW_HW_REG_TYPE_UD, BRW_HW_IMM_TYPE_UD },
43 [BRW_REGISTER_TYPE_W] = { BRW_HW_REG_TYPE_W, BRW_HW_IMM_TYPE_W },
44 [BRW_REGISTER_TYPE_UW] = { BRW_HW_REG_TYPE_UW, BRW_HW_IMM_TYPE_UW },
45 [BRW_REGISTER_TYPE_B] = { BRW_HW_REG_TYPE_B, INVALID },
46 [BRW_REGISTER_TYPE_UB] = { BRW_HW_REG_TYPE_UB, INVALID },
47 [BRW_REGISTER_TYPE_V] = { INVALID, BRW_HW_IMM_TYPE_V },
48 [BRW_REGISTER_TYPE_UV] = { INVALID, BRW_HW_IMM_TYPE_UV },
49 };
50
51 /**
52 * Convert a brw_reg_type enumeration value into the hardware representation.
53 *
54 * The hardware encoding may depend on whether the value is an immediate.
55 */
56 unsigned
57 brw_reg_type_to_hw_type(const struct gen_device_info *devinfo,
58 enum brw_reg_file file,
59 enum brw_reg_type type)
60 {
61 assert(type < ARRAY_SIZE(gen4_hw_type));
62
63 if (file == BRW_IMMEDIATE_VALUE) {
64 assert(gen4_hw_type[type].imm_type != (enum hw_imm_type)INVALID);
65 return gen4_hw_type[type].imm_type;
66 } else {
67 assert(gen4_hw_type[type].reg_type != (enum hw_reg_type)INVALID);
68 return gen4_hw_type[type].reg_type;
69 }
70 }
71
72 /**
73 * Convert the hardware representation into a brw_reg_type enumeration value.
74 *
75 * The hardware encoding may depend on whether the value is an immediate.
76 */
77 enum brw_reg_type
78 brw_hw_type_to_reg_type(const struct gen_device_info *devinfo,
79 enum brw_reg_file file, unsigned hw_type)
80 {
81 if (file == BRW_IMMEDIATE_VALUE) {
82 for (enum brw_reg_type i = 0; i <= BRW_REGISTER_TYPE_LAST; i++) {
83 if (gen4_hw_type[i].imm_type == hw_type) {
84 return i;
85 }
86 }
87 } else {
88 for (enum brw_reg_type i = 0; i <= BRW_REGISTER_TYPE_LAST; i++) {
89 if (gen4_hw_type[i].reg_type == hw_type) {
90 return i;
91 }
92 }
93 }
94 unreachable("not reached");
95 }
96
97 /**
98 * Return the element size given a hardware register type and file.
99 *
100 * The hardware encoding may depend on whether the value is an immediate.
101 */
102 unsigned
103 brw_hw_reg_type_to_size(const struct gen_device_info *devinfo,
104 enum brw_reg_file file,
105 unsigned hw_type)
106 {
107 if (file == BRW_IMMEDIATE_VALUE) {
108 static const int hw_sizes[] = {
109 [0 ... 15] = -1,
110 [BRW_HW_IMM_TYPE_UD] = 4,
111 [BRW_HW_IMM_TYPE_D] = 4,
112 [BRW_HW_IMM_TYPE_UW] = 2,
113 [BRW_HW_IMM_TYPE_W] = 2,
114 [BRW_HW_IMM_TYPE_UV] = 2,
115 [BRW_HW_IMM_TYPE_VF] = 4,
116 [BRW_HW_IMM_TYPE_V] = 2,
117 [BRW_HW_IMM_TYPE_F] = 4,
118 [GEN8_HW_IMM_TYPE_UQ] = 8,
119 [GEN8_HW_IMM_TYPE_Q] = 8,
120 [GEN8_HW_IMM_TYPE_DF] = 8,
121 [GEN8_HW_IMM_TYPE_HF] = 2,
122 };
123 assert(hw_type < ARRAY_SIZE(hw_sizes));
124 assert(hw_sizes[hw_type] != -1);
125 return hw_sizes[hw_type];
126 } else {
127 /* Non-immediate registers */
128 static const int hw_sizes[] = {
129 [0 ... 15] = -1,
130 [BRW_HW_REG_TYPE_UD] = 4,
131 [BRW_HW_REG_TYPE_D] = 4,
132 [BRW_HW_REG_TYPE_UW] = 2,
133 [BRW_HW_REG_TYPE_W] = 2,
134 [BRW_HW_REG_TYPE_UB] = 1,
135 [BRW_HW_REG_TYPE_B] = 1,
136 [GEN7_HW_REG_TYPE_DF] = 8,
137 [BRW_HW_REG_TYPE_F] = 4,
138 [GEN8_HW_REG_TYPE_UQ] = 8,
139 [GEN8_HW_REG_TYPE_Q] = 8,
140 [GEN8_HW_REG_TYPE_HF] = 2,
141 };
142 assert(hw_type < ARRAY_SIZE(hw_sizes));
143 assert(hw_sizes[hw_type] != -1);
144 return hw_sizes[hw_type];
145 }
146 }