src/intel/compiler/brw_reg_type.c

   1 /*
   2  * Copyright © 2017 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  */
  23
  24 #include "brw_reg.h"
  25 #include "brw_eu_defines.h"
  26 #include "common/gen_device_info.h"
  27
  28 #define INVALID (-1)
  29
  30 enum hw_reg_type {
  31    BRW_HW_REG_TYPE_UD  = 0,
  32    BRW_HW_REG_TYPE_D   = 1,
  33    BRW_HW_REG_TYPE_UW  = 2,
  34    BRW_HW_REG_TYPE_W   = 3,
  35    BRW_HW_REG_TYPE_F   = 7,
  36    GEN8_HW_REG_TYPE_UQ = 8,
  37    GEN8_HW_REG_TYPE_Q  = 9,
  38
  39    BRW_HW_REG_TYPE_UB  = 4,
  40    BRW_HW_REG_TYPE_B   = 5,
  41    GEN7_HW_REG_TYPE_DF = 6,
  42    GEN8_HW_REG_TYPE_HF = 10,
  43 };
  44
  45 enum hw_imm_type {
  46    BRW_HW_IMM_TYPE_UD  = 0,
  47    BRW_HW_IMM_TYPE_D   = 1,
  48    BRW_HW_IMM_TYPE_UW  = 2,
  49    BRW_HW_IMM_TYPE_W   = 3,
  50    BRW_HW_IMM_TYPE_F   = 7,
  51    GEN8_HW_IMM_TYPE_UQ = 8,
  52    GEN8_HW_IMM_TYPE_Q  = 9,
  53
  54    BRW_HW_IMM_TYPE_UV  = 4,
  55    BRW_HW_IMM_TYPE_VF  = 5,
  56    BRW_HW_IMM_TYPE_V   = 6,
  57    GEN8_HW_IMM_TYPE_DF = 10,
  58    GEN8_HW_IMM_TYPE_HF = 11,
  59 };
  60
  61 static const struct {
  62    enum hw_reg_type reg_type;
  63    enum hw_imm_type imm_type;
  64 } gen4_hw_type[] = {
  65    [BRW_REGISTER_TYPE_DF] = { GEN7_HW_REG_TYPE_DF, GEN8_HW_IMM_TYPE_DF },
  66    [BRW_REGISTER_TYPE_F]  = { BRW_HW_REG_TYPE_F,   BRW_HW_IMM_TYPE_F   },
  67    [BRW_REGISTER_TYPE_HF] = { GEN8_HW_REG_TYPE_HF, GEN8_HW_IMM_TYPE_HF },
  68    [BRW_REGISTER_TYPE_VF] = { INVALID,             BRW_HW_IMM_TYPE_VF  },
  69
  70    [BRW_REGISTER_TYPE_Q]  = { GEN8_HW_REG_TYPE_Q,  GEN8_HW_IMM_TYPE_Q  },
  71    [BRW_REGISTER_TYPE_UQ] = { GEN8_HW_REG_TYPE_UQ, GEN8_HW_IMM_TYPE_UQ },
  72    [BRW_REGISTER_TYPE_D]  = { BRW_HW_REG_TYPE_D,   BRW_HW_IMM_TYPE_D   },
  73    [BRW_REGISTER_TYPE_UD] = { BRW_HW_REG_TYPE_UD,  BRW_HW_IMM_TYPE_UD  },
  74    [BRW_REGISTER_TYPE_W]  = { BRW_HW_REG_TYPE_W,   BRW_HW_IMM_TYPE_W   },
  75    [BRW_REGISTER_TYPE_UW] = { BRW_HW_REG_TYPE_UW,  BRW_HW_IMM_TYPE_UW  },
  76    [BRW_REGISTER_TYPE_B]  = { BRW_HW_REG_TYPE_B,   INVALID             },
  77    [BRW_REGISTER_TYPE_UB] = { BRW_HW_REG_TYPE_UB,  INVALID             },
  78    [BRW_REGISTER_TYPE_V]  = { INVALID,             BRW_HW_IMM_TYPE_V   },
  79    [BRW_REGISTER_TYPE_UV] = { INVALID,             BRW_HW_IMM_TYPE_UV  },
  80 };
  81
  82 /* SNB adds 3-src instructions (MAD and LRP) that only operate on floats, so
  83  * the types were implied. IVB adds BFE and BFI2 that operate on doublewords
  84  * and unsigned doublewords, so a new field is also available in the da3src
  85  * struct (part of struct brw_instruction.bits1 in brw_structs.h) to select
  86  * dst and shared-src types.
  87  */
  88 enum hw_3src_reg_type {
  89    GEN7_3SRC_TYPE_F  = 0,
  90    GEN7_3SRC_TYPE_D  = 1,
  91    GEN7_3SRC_TYPE_UD = 2,
  92    GEN7_3SRC_TYPE_DF = 3,
  93 };
  94
  95 static const enum hw_3src_reg_type gen7_3src_type[] = {
  96    [0 ... BRW_REGISTER_TYPE_LAST] = INVALID,
  97    [BRW_REGISTER_TYPE_F]  = GEN7_3SRC_TYPE_F,
  98    [BRW_REGISTER_TYPE_D]  = GEN7_3SRC_TYPE_D,
  99    [BRW_REGISTER_TYPE_UD] = GEN7_3SRC_TYPE_UD,
 100    [BRW_REGISTER_TYPE_DF] = GEN7_3SRC_TYPE_DF,
 101 };
 102
 103 /**
 104  * Convert a brw_reg_type enumeration value into the hardware representation.
 105  *
 106  * The hardware encoding may depend on whether the value is an immediate.
 107  */
 108 unsigned
 109 brw_reg_type_to_hw_type(const struct gen_device_info *devinfo,
 110                         enum brw_reg_file file,
 111                         enum brw_reg_type type)
 112 {
 113    assert(type < ARRAY_SIZE(gen4_hw_type));
 114
 115    if (file == BRW_IMMEDIATE_VALUE) {
 116       assert(gen4_hw_type[type].imm_type != (enum hw_imm_type)INVALID);
 117       return gen4_hw_type[type].imm_type;
 118    } else {
 119       assert(gen4_hw_type[type].reg_type != (enum hw_reg_type)INVALID);
 120       return gen4_hw_type[type].reg_type;
 121    }
 122 }
 123
 124 /**
 125  * Convert the hardware representation into a brw_reg_type enumeration value.
 126  *
 127  * The hardware encoding may depend on whether the value is an immediate.
 128  */
 129 enum brw_reg_type
 130 brw_hw_type_to_reg_type(const struct gen_device_info *devinfo,
 131                         enum brw_reg_file file, unsigned hw_type)
 132 {
 133    if (file == BRW_IMMEDIATE_VALUE) {
 134       for (enum brw_reg_type i = 0; i <= BRW_REGISTER_TYPE_LAST; i++) {
 135          if (gen4_hw_type[i].imm_type == (enum hw_imm_type)hw_type) {
 136             return i;
 137          }
 138       }
 139    } else {
 140       for (enum brw_reg_type i = 0; i <= BRW_REGISTER_TYPE_LAST; i++) {
 141          if (gen4_hw_type[i].reg_type == (enum hw_reg_type)hw_type) {
 142             return i;
 143          }
 144       }
 145    }
 146    unreachable("not reached");
 147 }
 148
 149 /**
 150  * Convert a brw_reg_type enumeration value into the hardware representation
 151  * for a 3-src instruction
 152  */
 153 unsigned
 154 brw_reg_type_to_hw_3src_type(const struct gen_device_info *devinfo,
 155                              enum brw_reg_type type)
 156 {
 157    assert(type < ARRAY_SIZE(gen7_3src_type));
 158    assert(gen7_3src_type[type] != -1);
 159    return gen7_3src_type[type];
 160 }
 161
 162 /**
 163  * Convert the hardware representation for a 3-src instruction into a
 164  * brw_reg_type enumeration value.
 165  */
 166 enum brw_reg_type
 167 brw_hw_3src_type_to_reg_type(const struct gen_device_info *devinfo,
 168                              unsigned hw_type)
 169 {
 170    for (enum brw_reg_type i = 0; i <= BRW_REGISTER_TYPE_LAST; i++) {
 171       if (gen7_3src_type[i] == hw_type) {
 172          return i;
 173       }
 174    }
 175    unreachable("not reached");
 176 }
 177
 178 /**
 179  * Return the element size given a register type.
 180  */
 181 unsigned
 182 brw_reg_type_to_size(enum brw_reg_type type)
 183 {
 184    static const unsigned type_size[] = {
 185       [BRW_REGISTER_TYPE_DF] = 8,
 186       [BRW_REGISTER_TYPE_F]  = 4,
 187       [BRW_REGISTER_TYPE_HF] = 2,
 188       [BRW_REGISTER_TYPE_VF] = 4,
 189
 190       [BRW_REGISTER_TYPE_Q]  = 8,
 191       [BRW_REGISTER_TYPE_UQ] = 8,
 192       [BRW_REGISTER_TYPE_D]  = 4,
 193       [BRW_REGISTER_TYPE_UD] = 4,
 194       [BRW_REGISTER_TYPE_W]  = 2,
 195       [BRW_REGISTER_TYPE_UW] = 2,
 196       [BRW_REGISTER_TYPE_B]  = 1,
 197       [BRW_REGISTER_TYPE_UB] = 1,
 198       [BRW_REGISTER_TYPE_V]  = 2,
 199       [BRW_REGISTER_TYPE_UV] = 2,
 200    };
 201    return type_size[type];
 202 }
 203
 204 /**
 205  * Converts a BRW_REGISTER_TYPE_* enum to a short string (F, UD, and so on).
 206  *
 207  * This is different than reg_encoding from brw_disasm.c in that it operates
 208  * on the abstract enum values, rather than the generation-specific encoding.
 209  */
 210 const char *
 211 brw_reg_type_to_letters(enum brw_reg_type type)
 212 {
 213    static const char letters[][3] = {
 214       [BRW_REGISTER_TYPE_DF] = "DF",
 215       [BRW_REGISTER_TYPE_F]  = "F",
 216       [BRW_REGISTER_TYPE_HF] = "HF",
 217       [BRW_REGISTER_TYPE_VF] = "VF",
 218
 219       [BRW_REGISTER_TYPE_Q]  = "Q",
 220       [BRW_REGISTER_TYPE_UQ] = "UQ",
 221       [BRW_REGISTER_TYPE_D]  = "D",
 222       [BRW_REGISTER_TYPE_UD] = "UD",
 223       [BRW_REGISTER_TYPE_W]  = "W",
 224       [BRW_REGISTER_TYPE_UW] = "UW",
 225       [BRW_REGISTER_TYPE_B]  = "B",
 226       [BRW_REGISTER_TYPE_UB] = "UB",
 227       [BRW_REGISTER_TYPE_V]  = "V",
 228       [BRW_REGISTER_TYPE_UV] = "UV",
 229    };
 230    assert(type < ARRAY_SIZE(letters));
 231    return letters[type];
 232 }