2 * Copyright © 2010 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Eric Anholt <eric@anholt.net>
29 #include "brw_fs_live_variables.h"
32 #include "brw_shader.h"
36 /** @file brw_fs_schedule_instructions.cpp
38 * List scheduling of FS instructions.
40 * The basic model of the list scheduler is to take a basic block,
41 * compute a DAG of the dependencies (RAW ordering with latency, WAW
42 * ordering with latency, WAR ordering), and make a list of the DAG heads.
43 * Heuristically pick a DAG head, then put all the children that are
44 * now DAG heads into the list of things to schedule.
46 * The heuristic is the important part. We're trying to be cheap,
47 * since actually computing the optimal scheduling is NP complete.
48 * What we do is track a "current clock". When we schedule a node, we
49 * update the earliest-unblocked clock time of its children, and
50 * increment the clock. Then, when trying to schedule, we just pick
51 * the earliest-unblocked instruction to schedule.
53 * Note that often there will be many things which could execute
54 * immediately, and there are a range of heuristic options to choose
55 * from in picking among those.
58 static bool debug
= false;
60 class instruction_scheduler
;
62 class schedule_node
: public exec_node
65 schedule_node(backend_instruction
*inst
, instruction_scheduler
*sched
);
66 void set_latency_gen4();
67 void set_latency_gen7(bool is_haswell
);
69 backend_instruction
*inst
;
70 schedule_node
**children
;
79 * Which iteration of pushing groups of children onto the candidates list
80 * this node was a part of.
82 unsigned cand_generation
;
85 * This is the sum of the instruction's latency plus the maximum delay of
86 * its children, or just the issue_time if it's a leaf node.
91 * Preferred exit node among the (direct or indirect) successors of this
92 * node. Among the scheduler nodes blocked by this node, this will be the
93 * one that may cause earliest program termination, or NULL if none of the
94 * successors is an exit node.
100 * Lower bound of the scheduling time after which one of the instructions
101 * blocked by this node may lead to program termination.
103 * exit_unblocked_time() determines a strict partial ordering relation '«' on
104 * the set of scheduler nodes as follows:
106 * n « m <-> exit_unblocked_time(n) < exit_unblocked_time(m)
108 * which can be used to heuristically order nodes according to how early they
109 * can unblock an exit node and lead to program termination.
112 exit_unblocked_time(const schedule_node
*n
)
114 return n
->exit
? n
->exit
->unblocked_time
: INT_MAX
;
118 schedule_node::set_latency_gen4()
121 int math_latency
= 22;
123 switch (inst
->opcode
) {
124 case SHADER_OPCODE_RCP
:
125 this->latency
= 1 * chans
* math_latency
;
127 case SHADER_OPCODE_RSQ
:
128 this->latency
= 2 * chans
* math_latency
;
130 case SHADER_OPCODE_INT_QUOTIENT
:
131 case SHADER_OPCODE_SQRT
:
132 case SHADER_OPCODE_LOG2
:
133 /* full precision log. partial is 2. */
134 this->latency
= 3 * chans
* math_latency
;
136 case SHADER_OPCODE_INT_REMAINDER
:
137 case SHADER_OPCODE_EXP2
:
138 /* full precision. partial is 3, same throughput. */
139 this->latency
= 4 * chans
* math_latency
;
141 case SHADER_OPCODE_POW
:
142 this->latency
= 8 * chans
* math_latency
;
144 case SHADER_OPCODE_SIN
:
145 case SHADER_OPCODE_COS
:
146 /* minimum latency, max is 12 rounds. */
147 this->latency
= 5 * chans
* math_latency
;
156 schedule_node::set_latency_gen7(bool is_haswell
)
158 switch (inst
->opcode
) {
161 * (since the last two src operands are in different register banks):
162 * mad(8) g4<1>F g2.2<4,4,1>F.x g2<4,4,1>F.x g3.1<4,4,1>F.x { align16 WE_normal 1Q };
164 * 3 cycles on IVB, 4 on HSW
165 * (since the last two src operands are in the same register bank):
166 * mad(8) g4<1>F g2.2<4,4,1>F.x g2<4,4,1>F.x g2.1<4,4,1>F.x { align16 WE_normal 1Q };
168 * 18 cycles on IVB, 16 on HSW
169 * (since the last two src operands are in different register banks):
170 * mad(8) g4<1>F g2.2<4,4,1>F.x g2<4,4,1>F.x g3.1<4,4,1>F.x { align16 WE_normal 1Q };
171 * mov(8) null g4<4,5,1>F { align16 WE_normal 1Q };
173 * 20 cycles on IVB, 18 on HSW
174 * (since the last two src operands are in the same register bank):
175 * mad(8) g4<1>F g2.2<4,4,1>F.x g2<4,4,1>F.x g2.1<4,4,1>F.x { align16 WE_normal 1Q };
176 * mov(8) null g4<4,4,1>F { align16 WE_normal 1Q };
179 /* Our register allocator doesn't know about register banks, so use the
182 latency
= is_haswell
? 16 : 18;
187 * (since the last two src operands are in different register banks):
188 * lrp(8) g4<1>F g2.2<4,4,1>F.x g2<4,4,1>F.x g3.1<4,4,1>F.x { align16 WE_normal 1Q };
190 * 3 cycles on IVB, 4 on HSW
191 * (since the last two src operands are in the same register bank):
192 * lrp(8) g4<1>F g2.2<4,4,1>F.x g2<4,4,1>F.x g2.1<4,4,1>F.x { align16 WE_normal 1Q };
194 * 16 cycles on IVB, 14 on HSW
195 * (since the last two src operands are in different register banks):
196 * lrp(8) g4<1>F g2.2<4,4,1>F.x g2<4,4,1>F.x g3.1<4,4,1>F.x { align16 WE_normal 1Q };
197 * mov(8) null g4<4,4,1>F { align16 WE_normal 1Q };
200 * (since the last two src operands are in the same register bank):
201 * lrp(8) g4<1>F g2.2<4,4,1>F.x g2<4,4,1>F.x g2.1<4,4,1>F.x { align16 WE_normal 1Q };
202 * mov(8) null g4<4,4,1>F { align16 WE_normal 1Q };
205 /* Our register allocator doesn't know about register banks, so use the
211 case SHADER_OPCODE_RCP
:
212 case SHADER_OPCODE_RSQ
:
213 case SHADER_OPCODE_SQRT
:
214 case SHADER_OPCODE_LOG2
:
215 case SHADER_OPCODE_EXP2
:
216 case SHADER_OPCODE_SIN
:
217 case SHADER_OPCODE_COS
:
219 * math inv(8) g4<1>F g2<0,1,0>F null { align1 WE_normal 1Q };
222 * math inv(8) g4<1>F g2<0,1,0>F null { align1 WE_normal 1Q };
223 * mov(8) null g4<8,8,1>F { align1 WE_normal 1Q };
225 * Same for exp2, log2, rsq, sqrt, sin, cos.
227 latency
= is_haswell
? 14 : 16;
230 case SHADER_OPCODE_POW
:
232 * math pow(8) g4<1>F g2<0,1,0>F g2.1<0,1,0>F { align1 WE_normal 1Q };
235 * math pow(8) g4<1>F g2<0,1,0>F g2.1<0,1,0>F { align1 WE_normal 1Q };
236 * mov(8) null g4<8,8,1>F { align1 WE_normal 1Q };
238 latency
= is_haswell
? 22 : 24;
241 case SHADER_OPCODE_TEX
:
242 case SHADER_OPCODE_TXD
:
243 case SHADER_OPCODE_TXF
:
244 case SHADER_OPCODE_TXF_LZ
:
245 case SHADER_OPCODE_TXL
:
246 case SHADER_OPCODE_TXL_LZ
:
248 * mov(8) g115<1>F 0F { align1 WE_normal 1Q };
249 * mov(8) g114<1>F 0F { align1 WE_normal 1Q };
250 * send(8) g4<1>UW g114<8,8,1>F
251 * sampler (10, 0, 0, 1) mlen 2 rlen 4 { align1 WE_normal 1Q };
253 * 697 +/-49 cycles (min 610, n=26):
254 * mov(8) g115<1>F 0F { align1 WE_normal 1Q };
255 * mov(8) g114<1>F 0F { align1 WE_normal 1Q };
256 * send(8) g4<1>UW g114<8,8,1>F
257 * sampler (10, 0, 0, 1) mlen 2 rlen 4 { align1 WE_normal 1Q };
258 * mov(8) null g4<8,8,1>F { align1 WE_normal 1Q };
260 * So the latency on our first texture load of the batchbuffer takes
261 * ~700 cycles, since the caches are cold at that point.
263 * 840 +/- 92 cycles (min 720, n=25):
264 * mov(8) g115<1>F 0F { align1 WE_normal 1Q };
265 * mov(8) g114<1>F 0F { align1 WE_normal 1Q };
266 * send(8) g4<1>UW g114<8,8,1>F
267 * sampler (10, 0, 0, 1) mlen 2 rlen 4 { align1 WE_normal 1Q };
268 * mov(8) null g4<8,8,1>F { align1 WE_normal 1Q };
269 * send(8) g4<1>UW g114<8,8,1>F
270 * sampler (10, 0, 0, 1) mlen 2 rlen 4 { align1 WE_normal 1Q };
271 * mov(8) null g4<8,8,1>F { align1 WE_normal 1Q };
273 * On the second load, it takes just an extra ~140 cycles, and after
274 * accounting for the 14 cycles of the MOV's latency, that makes ~130.
276 * 683 +/- 49 cycles (min = 602, n=47):
277 * mov(8) g115<1>F 0F { align1 WE_normal 1Q };
278 * mov(8) g114<1>F 0F { align1 WE_normal 1Q };
279 * send(8) g4<1>UW g114<8,8,1>F
280 * sampler (10, 0, 0, 1) mlen 2 rlen 4 { align1 WE_normal 1Q };
281 * send(8) g50<1>UW g114<8,8,1>F
282 * sampler (10, 0, 0, 1) mlen 2 rlen 4 { align1 WE_normal 1Q };
283 * mov(8) null g4<8,8,1>F { align1 WE_normal 1Q };
285 * The unit appears to be pipelined, since this matches up with the
286 * cache-cold case, despite there being two loads here. If you replace
287 * the g4 in the MOV to null with g50, it's still 693 +/- 52 (n=39).
289 * So, take some number between the cache-hot 140 cycles and the
290 * cache-cold 700 cycles. No particular tuning was done on this.
292 * I haven't done significant testing of the non-TEX opcodes. TXL at
293 * least looked about the same as TEX.
298 case SHADER_OPCODE_TXS
:
299 /* Testing textureSize(sampler2D, 0), one load was 420 +/- 41
301 * mov(8) g114<1>UD 0D { align1 WE_normal 1Q };
302 * send(8) g6<1>UW g114<8,8,1>F
303 * sampler (10, 0, 10, 1) mlen 1 rlen 4 { align1 WE_normal 1Q };
304 * mov(16) g6<1>F g6<8,8,1>D { align1 WE_normal 1Q };
307 * Two loads was 535 +/- 30 cycles (n=19):
308 * mov(16) g114<1>UD 0D { align1 WE_normal 1H };
309 * send(16) g6<1>UW g114<8,8,1>F
310 * sampler (10, 0, 10, 2) mlen 2 rlen 8 { align1 WE_normal 1H };
311 * mov(16) g114<1>UD 0D { align1 WE_normal 1H };
312 * mov(16) g6<1>F g6<8,8,1>D { align1 WE_normal 1H };
313 * send(16) g8<1>UW g114<8,8,1>F
314 * sampler (10, 0, 10, 2) mlen 2 rlen 8 { align1 WE_normal 1H };
315 * mov(16) g8<1>F g8<8,8,1>D { align1 WE_normal 1H };
316 * add(16) g6<1>F g6<8,8,1>F g8<8,8,1>F { align1 WE_normal 1H };
318 * Since the only caches that should matter are just the
319 * instruction/state cache containing the surface state, assume that we
320 * always have hot caches.
325 case FS_OPCODE_VARYING_PULL_CONSTANT_LOAD_GEN4
:
326 case FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD
:
327 case FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD_GEN7
:
328 case VS_OPCODE_PULL_CONSTANT_LOAD
:
329 /* testing using varying-index pull constants:
332 * mov(8) g4<1>D g2.1<0,1,0>F { align1 WE_normal 1Q };
333 * send(8) g4<1>F g4<8,8,1>D
334 * data (9, 2, 3) mlen 1 rlen 1 { align1 WE_normal 1Q };
337 * mov(8) g4<1>D g2.1<0,1,0>F { align1 WE_normal 1Q };
338 * send(8) g4<1>F g4<8,8,1>D
339 * data (9, 2, 3) mlen 1 rlen 1 { align1 WE_normal 1Q };
340 * mov(8) null g4<8,8,1>F { align1 WE_normal 1Q };
343 * mov(8) g4<1>D g2.1<0,1,0>F { align1 WE_normal 1Q };
344 * send(8) g4<1>F g4<8,8,1>D
345 * data (9, 2, 3) mlen 1 rlen 1 { align1 WE_normal 1Q };
346 * mov(8) null g4<8,8,1>F { align1 WE_normal 1Q };
347 * send(8) g4<1>F g4<8,8,1>D
348 * data (9, 2, 3) mlen 1 rlen 1 { align1 WE_normal 1Q };
349 * mov(8) null g4<8,8,1>F { align1 WE_normal 1Q };
351 * So, if it's cache-hot, it's about 140. If it's cache cold, it's
352 * about 460. We expect to mostly be cache hot, so pick something more
358 case SHADER_OPCODE_GEN7_SCRATCH_READ
:
359 /* Testing a load from offset 0, that had been previously written:
361 * send(8) g114<1>UW g0<8,8,1>F data (0, 0, 0) mlen 1 rlen 1 { align1 WE_normal 1Q };
362 * mov(8) null g114<8,8,1>F { align1 WE_normal 1Q };
364 * The cycles spent seemed to be grouped around 40-50 (as low as 38),
365 * then around 140. Presumably this is cache hit vs miss.
370 case VEC4_OPCODE_UNTYPED_ATOMIC
:
371 /* See GEN7_DATAPORT_DC_UNTYPED_ATOMIC_OP */
375 case VEC4_OPCODE_UNTYPED_SURFACE_READ
:
376 case VEC4_OPCODE_UNTYPED_SURFACE_WRITE
:
377 /* See also GEN7_DATAPORT_DC_UNTYPED_SURFACE_READ */
378 latency
= is_haswell
? 300 : 600;
381 case SHADER_OPCODE_SEND
:
382 switch (inst
->sfid
) {
383 case BRW_SFID_SAMPLER
: {
384 unsigned msg_type
= (inst
->desc
>> 12) & 0x1f;
386 case GEN5_SAMPLER_MESSAGE_SAMPLE_RESINFO
:
387 case GEN6_SAMPLER_MESSAGE_SAMPLE_SAMPLEINFO
:
388 /* See also SHADER_OPCODE_TXS */
393 /* See also SHADER_OPCODE_TEX */
400 case GEN6_SFID_DATAPORT_RENDER_CACHE
:
401 switch ((inst
->desc
>> 14) & 0x1f) {
402 case GEN7_DATAPORT_RC_TYPED_SURFACE_WRITE
:
403 case GEN7_DATAPORT_RC_TYPED_SURFACE_READ
:
404 /* See also SHADER_OPCODE_TYPED_SURFACE_READ */
409 case GEN7_DATAPORT_RC_TYPED_ATOMIC_OP
:
410 /* See also SHADER_OPCODE_TYPED_ATOMIC */
415 case GEN6_DATAPORT_WRITE_MESSAGE_RENDER_TARGET_WRITE
:
416 /* completely fabricated number */
421 unreachable("Unknown render cache message");
425 case GEN7_SFID_DATAPORT_DATA_CACHE
:
426 switch ((inst
->desc
>> 14) & 0x1f) {
427 case HSW_DATAPORT_DC_PORT0_BYTE_SCATTERED_READ
:
428 case HSW_DATAPORT_DC_PORT0_BYTE_SCATTERED_WRITE
:
429 /* We have no data for this but assume it's roughly the same as
430 * untyped surface read/write.
435 case GEN7_DATAPORT_DC_UNTYPED_SURFACE_READ
:
436 case GEN7_DATAPORT_DC_UNTYPED_SURFACE_WRITE
:
438 * mov(8) g112<1>UD 0x00000000UD { align1 WE_all 1Q };
439 * mov(1) g112.7<1>UD g1.7<0,1,0>UD { align1 WE_all };
440 * mov(8) g113<1>UD 0x00000000UD { align1 WE_normal 1Q };
441 * send(8) g4<1>UD g112<8,8,1>UD
442 * data (38, 6, 5) mlen 2 rlen 1 { align1 WE_normal 1Q };
444 * . [repeats 8 times]
446 * mov(8) g112<1>UD 0x00000000UD { align1 WE_all 1Q };
447 * mov(1) g112.7<1>UD g1.7<0,1,0>UD { align1 WE_all };
448 * mov(8) g113<1>UD 0x00000000UD { align1 WE_normal 1Q };
449 * send(8) g4<1>UD g112<8,8,1>UD
450 * data (38, 6, 5) mlen 2 rlen 1 { align1 WE_normal 1Q };
452 * Running it 100 times as fragment shader on a 128x128 quad
453 * gives an average latency of 583 cycles per surface read,
454 * standard deviation 0.9%.
460 case GEN7_DATAPORT_DC_UNTYPED_ATOMIC_OP
:
462 * mov(8) g112<1>ud 0x00000000ud { align1 WE_all 1Q };
463 * mov(1) g112.7<1>ud g1.7<0,1,0>ud { align1 WE_all };
464 * mov(8) g113<1>ud 0x00000000ud { align1 WE_normal 1Q };
465 * send(8) g4<1>ud g112<8,8,1>ud
466 * data (38, 5, 6) mlen 2 rlen 1 { align1 WE_normal 1Q };
468 * Running it 100 times as fragment shader on a 128x128 quad
469 * gives an average latency of 13867 cycles per atomic op,
470 * standard deviation 3%. Note that this is a rather
471 * pessimistic estimate, the actual latency in cases with few
472 * collisions between threads and favorable pipelining has been
473 * seen to be reduced by a factor of 100.
480 unreachable("Unknown data cache message");
484 case HSW_SFID_DATAPORT_DATA_CACHE_1
:
485 switch ((inst
->desc
>> 14) & 0x1f) {
486 case HSW_DATAPORT_DC_PORT1_UNTYPED_SURFACE_READ
:
487 case HSW_DATAPORT_DC_PORT1_UNTYPED_SURFACE_WRITE
:
488 case HSW_DATAPORT_DC_PORT1_TYPED_SURFACE_READ
:
489 case HSW_DATAPORT_DC_PORT1_TYPED_SURFACE_WRITE
:
490 case GEN8_DATAPORT_DC_PORT1_A64_UNTYPED_SURFACE_WRITE
:
491 case GEN8_DATAPORT_DC_PORT1_A64_UNTYPED_SURFACE_READ
:
492 case GEN8_DATAPORT_DC_PORT1_A64_SCATTERED_WRITE
:
493 case GEN9_DATAPORT_DC_PORT1_A64_SCATTERED_READ
:
494 /* See also GEN7_DATAPORT_DC_UNTYPED_SURFACE_READ */
498 case HSW_DATAPORT_DC_PORT1_UNTYPED_ATOMIC_OP
:
499 case HSW_DATAPORT_DC_PORT1_UNTYPED_ATOMIC_OP_SIMD4X2
:
500 case HSW_DATAPORT_DC_PORT1_TYPED_ATOMIC_OP_SIMD4X2
:
501 case HSW_DATAPORT_DC_PORT1_TYPED_ATOMIC_OP
:
502 case GEN9_DATAPORT_DC_PORT1_UNTYPED_ATOMIC_FLOAT_OP
:
503 case GEN8_DATAPORT_DC_PORT1_A64_UNTYPED_ATOMIC_OP
:
504 case GEN9_DATAPORT_DC_PORT1_A64_UNTYPED_ATOMIC_FLOAT_OP
:
505 /* See also GEN7_DATAPORT_DC_UNTYPED_ATOMIC_OP */
510 unreachable("Unknown data cache message");
515 unreachable("Unknown SFID");
521 * mul(8) g4<1>F g2<0,1,0>F 0.5F { align1 WE_normal 1Q };
524 * mul(8) g4<1>F g2<0,1,0>F 0.5F { align1 WE_normal 1Q };
525 * mov(8) null g4<8,8,1>F { align1 WE_normal 1Q };
532 class instruction_scheduler
{
534 instruction_scheduler(backend_shader
*s
, int grf_count
,
535 unsigned hw_reg_count
, int block_count
,
536 instruction_scheduler_mode mode
)
539 this->mem_ctx
= ralloc_context(NULL
);
540 this->grf_count
= grf_count
;
541 this->hw_reg_count
= hw_reg_count
;
542 this->instructions
.make_empty();
543 this->instructions_to_schedule
= 0;
544 this->post_reg_alloc
= (mode
== SCHEDULE_POST
);
546 if (!post_reg_alloc
) {
547 this->reg_pressure_in
= rzalloc_array(mem_ctx
, int, block_count
);
549 this->livein
= ralloc_array(mem_ctx
, BITSET_WORD
*, block_count
);
550 for (int i
= 0; i
< block_count
; i
++)
551 this->livein
[i
] = rzalloc_array(mem_ctx
, BITSET_WORD
,
552 BITSET_WORDS(grf_count
));
554 this->liveout
= ralloc_array(mem_ctx
, BITSET_WORD
*, block_count
);
555 for (int i
= 0; i
< block_count
; i
++)
556 this->liveout
[i
] = rzalloc_array(mem_ctx
, BITSET_WORD
,
557 BITSET_WORDS(grf_count
));
559 this->hw_liveout
= ralloc_array(mem_ctx
, BITSET_WORD
*, block_count
);
560 for (int i
= 0; i
< block_count
; i
++)
561 this->hw_liveout
[i
] = rzalloc_array(mem_ctx
, BITSET_WORD
,
562 BITSET_WORDS(hw_reg_count
));
564 this->written
= rzalloc_array(mem_ctx
, bool, grf_count
);
566 this->reads_remaining
= rzalloc_array(mem_ctx
, int, grf_count
);
568 this->hw_reads_remaining
= rzalloc_array(mem_ctx
, int, hw_reg_count
);
570 this->reg_pressure_in
= NULL
;
572 this->liveout
= NULL
;
573 this->hw_liveout
= NULL
;
574 this->written
= NULL
;
575 this->reads_remaining
= NULL
;
576 this->hw_reads_remaining
= NULL
;
580 ~instruction_scheduler()
582 ralloc_free(this->mem_ctx
);
584 void add_barrier_deps(schedule_node
*n
);
585 void add_dep(schedule_node
*before
, schedule_node
*after
, int latency
);
586 void add_dep(schedule_node
*before
, schedule_node
*after
);
588 void run(cfg_t
*cfg
);
589 void add_insts_from_block(bblock_t
*block
);
590 void compute_delays();
591 void compute_exits();
592 virtual void calculate_deps() = 0;
593 virtual schedule_node
*choose_instruction_to_schedule() = 0;
596 * Returns how many cycles it takes the instruction to issue.
598 * Instructions in gen hardware are handled one simd4 vector at a time,
599 * with 1 cycle per vector dispatched. Thus SIMD8 pixel shaders take 2
600 * cycles to dispatch and SIMD16 (compressed) instructions take 4.
602 virtual int issue_time(backend_instruction
*inst
) = 0;
604 virtual void count_reads_remaining(backend_instruction
*inst
) = 0;
605 virtual void setup_liveness(cfg_t
*cfg
) = 0;
606 virtual void update_register_pressure(backend_instruction
*inst
) = 0;
607 virtual int get_register_pressure_benefit(backend_instruction
*inst
) = 0;
609 void schedule_instructions(bblock_t
*block
);
614 int instructions_to_schedule
;
616 unsigned hw_reg_count
;
619 exec_list instructions
;
622 instruction_scheduler_mode mode
;
625 * The register pressure at the beginning of each basic block.
628 int *reg_pressure_in
;
631 * The virtual GRF's whose range overlaps the beginning of each basic block.
634 BITSET_WORD
**livein
;
637 * The virtual GRF's whose range overlaps the end of each basic block.
640 BITSET_WORD
**liveout
;
643 * The hardware GRF's whose range overlaps the end of each basic block.
646 BITSET_WORD
**hw_liveout
;
649 * Whether we've scheduled a write for this virtual GRF yet.
655 * How many reads we haven't scheduled for this virtual GRF yet.
658 int *reads_remaining
;
661 * How many reads we haven't scheduled for this hardware GRF yet.
664 int *hw_reads_remaining
;
667 class fs_instruction_scheduler
: public instruction_scheduler
670 fs_instruction_scheduler(fs_visitor
*v
, int grf_count
, int hw_reg_count
,
672 instruction_scheduler_mode mode
);
673 void calculate_deps();
674 bool is_compressed(fs_inst
*inst
);
675 schedule_node
*choose_instruction_to_schedule();
676 int issue_time(backend_instruction
*inst
);
679 void count_reads_remaining(backend_instruction
*inst
);
680 void setup_liveness(cfg_t
*cfg
);
681 void update_register_pressure(backend_instruction
*inst
);
682 int get_register_pressure_benefit(backend_instruction
*inst
);
685 fs_instruction_scheduler::fs_instruction_scheduler(fs_visitor
*v
,
686 int grf_count
, int hw_reg_count
,
688 instruction_scheduler_mode mode
)
689 : instruction_scheduler(v
, grf_count
, hw_reg_count
, block_count
, mode
),
695 is_src_duplicate(fs_inst
*inst
, int src
)
697 for (int i
= 0; i
< src
; i
++)
698 if (inst
->src
[i
].equals(inst
->src
[src
]))
705 fs_instruction_scheduler::count_reads_remaining(backend_instruction
*be
)
707 fs_inst
*inst
= (fs_inst
*)be
;
709 if (!reads_remaining
)
712 for (int i
= 0; i
< inst
->sources
; i
++) {
713 if (is_src_duplicate(inst
, i
))
716 if (inst
->src
[i
].file
== VGRF
) {
717 reads_remaining
[inst
->src
[i
].nr
]++;
718 } else if (inst
->src
[i
].file
== FIXED_GRF
) {
719 if (inst
->src
[i
].nr
>= hw_reg_count
)
722 for (unsigned j
= 0; j
< regs_read(inst
, i
); j
++)
723 hw_reads_remaining
[inst
->src
[i
].nr
+ j
]++;
729 fs_instruction_scheduler::setup_liveness(cfg_t
*cfg
)
731 /* First, compute liveness on a per-GRF level using the in/out sets from
732 * liveness calculation.
734 for (int block
= 0; block
< cfg
->num_blocks
; block
++) {
735 for (int i
= 0; i
< v
->live_intervals
->num_vars
; i
++) {
736 if (BITSET_TEST(v
->live_intervals
->block_data
[block
].livein
, i
)) {
737 int vgrf
= v
->live_intervals
->vgrf_from_var
[i
];
738 if (!BITSET_TEST(livein
[block
], vgrf
)) {
739 reg_pressure_in
[block
] += v
->alloc
.sizes
[vgrf
];
740 BITSET_SET(livein
[block
], vgrf
);
744 if (BITSET_TEST(v
->live_intervals
->block_data
[block
].liveout
, i
))
745 BITSET_SET(liveout
[block
], v
->live_intervals
->vgrf_from_var
[i
]);
749 /* Now, extend the live in/live out sets for when a range crosses a block
750 * boundary, which matches what our register allocator/interference code
751 * does to account for force_writemask_all and incompatible exec_mask's.
753 for (int block
= 0; block
< cfg
->num_blocks
- 1; block
++) {
754 for (int i
= 0; i
< grf_count
; i
++) {
755 if (v
->virtual_grf_start
[i
] <= cfg
->blocks
[block
]->end_ip
&&
756 v
->virtual_grf_end
[i
] >= cfg
->blocks
[block
+ 1]->start_ip
) {
757 if (!BITSET_TEST(livein
[block
+ 1], i
)) {
758 reg_pressure_in
[block
+ 1] += v
->alloc
.sizes
[i
];
759 BITSET_SET(livein
[block
+ 1], i
);
762 BITSET_SET(liveout
[block
], i
);
767 int payload_last_use_ip
[hw_reg_count
];
768 v
->calculate_payload_ranges(hw_reg_count
, payload_last_use_ip
);
770 for (unsigned i
= 0; i
< hw_reg_count
; i
++) {
771 if (payload_last_use_ip
[i
] == -1)
774 for (int block
= 0; block
< cfg
->num_blocks
; block
++) {
775 if (cfg
->blocks
[block
]->start_ip
<= payload_last_use_ip
[i
])
776 reg_pressure_in
[block
]++;
778 if (cfg
->blocks
[block
]->end_ip
<= payload_last_use_ip
[i
])
779 BITSET_SET(hw_liveout
[block
], i
);
785 fs_instruction_scheduler::update_register_pressure(backend_instruction
*be
)
787 fs_inst
*inst
= (fs_inst
*)be
;
789 if (!reads_remaining
)
792 if (inst
->dst
.file
== VGRF
) {
793 written
[inst
->dst
.nr
] = true;
796 for (int i
= 0; i
< inst
->sources
; i
++) {
797 if (is_src_duplicate(inst
, i
))
800 if (inst
->src
[i
].file
== VGRF
) {
801 reads_remaining
[inst
->src
[i
].nr
]--;
802 } else if (inst
->src
[i
].file
== FIXED_GRF
&&
803 inst
->src
[i
].nr
< hw_reg_count
) {
804 for (unsigned off
= 0; off
< regs_read(inst
, i
); off
++)
805 hw_reads_remaining
[inst
->src
[i
].nr
+ off
]--;
811 fs_instruction_scheduler::get_register_pressure_benefit(backend_instruction
*be
)
813 fs_inst
*inst
= (fs_inst
*)be
;
816 if (inst
->dst
.file
== VGRF
) {
817 if (!BITSET_TEST(livein
[block_idx
], inst
->dst
.nr
) &&
818 !written
[inst
->dst
.nr
])
819 benefit
-= v
->alloc
.sizes
[inst
->dst
.nr
];
822 for (int i
= 0; i
< inst
->sources
; i
++) {
823 if (is_src_duplicate(inst
, i
))
826 if (inst
->src
[i
].file
== VGRF
&&
827 !BITSET_TEST(liveout
[block_idx
], inst
->src
[i
].nr
) &&
828 reads_remaining
[inst
->src
[i
].nr
] == 1)
829 benefit
+= v
->alloc
.sizes
[inst
->src
[i
].nr
];
831 if (inst
->src
[i
].file
== FIXED_GRF
&&
832 inst
->src
[i
].nr
< hw_reg_count
) {
833 for (unsigned off
= 0; off
< regs_read(inst
, i
); off
++) {
834 int reg
= inst
->src
[i
].nr
+ off
;
835 if (!BITSET_TEST(hw_liveout
[block_idx
], reg
) &&
836 hw_reads_remaining
[reg
] == 1) {
846 class vec4_instruction_scheduler
: public instruction_scheduler
849 vec4_instruction_scheduler(vec4_visitor
*v
, int grf_count
);
850 void calculate_deps();
851 schedule_node
*choose_instruction_to_schedule();
852 int issue_time(backend_instruction
*inst
);
855 void count_reads_remaining(backend_instruction
*inst
);
856 void setup_liveness(cfg_t
*cfg
);
857 void update_register_pressure(backend_instruction
*inst
);
858 int get_register_pressure_benefit(backend_instruction
*inst
);
861 vec4_instruction_scheduler::vec4_instruction_scheduler(vec4_visitor
*v
,
863 : instruction_scheduler(v
, grf_count
, 0, 0, SCHEDULE_POST
),
869 vec4_instruction_scheduler::count_reads_remaining(backend_instruction
*)
874 vec4_instruction_scheduler::setup_liveness(cfg_t
*)
879 vec4_instruction_scheduler::update_register_pressure(backend_instruction
*)
884 vec4_instruction_scheduler::get_register_pressure_benefit(backend_instruction
*)
889 schedule_node::schedule_node(backend_instruction
*inst
,
890 instruction_scheduler
*sched
)
892 const struct gen_device_info
*devinfo
= sched
->bs
->devinfo
;
895 this->child_array_size
= 0;
896 this->children
= NULL
;
897 this->child_latency
= NULL
;
898 this->child_count
= 0;
899 this->parent_count
= 0;
900 this->unblocked_time
= 0;
901 this->cand_generation
= 0;
905 /* We can't measure Gen6 timings directly but expect them to be much
906 * closer to Gen7 than Gen4.
908 if (!sched
->post_reg_alloc
)
910 else if (devinfo
->gen
>= 6)
911 set_latency_gen7(devinfo
->is_haswell
);
917 instruction_scheduler::add_insts_from_block(bblock_t
*block
)
919 foreach_inst_in_block(backend_instruction
, inst
, block
) {
920 schedule_node
*n
= new(mem_ctx
) schedule_node(inst
, this);
922 instructions
.push_tail(n
);
925 this->instructions_to_schedule
= block
->end_ip
- block
->start_ip
+ 1;
928 /** Computation of the delay member of each node. */
930 instruction_scheduler::compute_delays()
932 foreach_in_list_reverse(schedule_node
, n
, &instructions
) {
933 if (!n
->child_count
) {
934 n
->delay
= issue_time(n
->inst
);
936 for (int i
= 0; i
< n
->child_count
; i
++) {
937 assert(n
->children
[i
]->delay
);
938 n
->delay
= MAX2(n
->delay
, n
->latency
+ n
->children
[i
]->delay
);
945 instruction_scheduler::compute_exits()
947 /* Calculate a lower bound of the scheduling time of each node in the
948 * graph. This is analogous to the node's critical path but calculated
949 * from the top instead of from the bottom of the block.
951 foreach_in_list(schedule_node
, n
, &instructions
) {
952 for (int i
= 0; i
< n
->child_count
; i
++) {
953 n
->children
[i
]->unblocked_time
=
954 MAX2(n
->children
[i
]->unblocked_time
,
955 n
->unblocked_time
+ issue_time(n
->inst
) + n
->child_latency
[i
]);
959 /* Calculate the exit of each node by induction based on the exit nodes of
960 * its children. The preferred exit of a node is the one among the exit
961 * nodes of its children which can be unblocked first according to the
962 * optimistic unblocked time estimate calculated above.
964 foreach_in_list_reverse(schedule_node
, n
, &instructions
) {
965 n
->exit
= (n
->inst
->opcode
== FS_OPCODE_DISCARD_JUMP
? n
: NULL
);
967 for (int i
= 0; i
< n
->child_count
; i
++) {
968 if (exit_unblocked_time(n
->children
[i
]) < exit_unblocked_time(n
))
969 n
->exit
= n
->children
[i
]->exit
;
975 * Add a dependency between two instruction nodes.
977 * The @after node will be scheduled after @before. We will try to
978 * schedule it @latency cycles after @before, but no guarantees there.
981 instruction_scheduler::add_dep(schedule_node
*before
, schedule_node
*after
,
984 if (!before
|| !after
)
987 assert(before
!= after
);
989 for (int i
= 0; i
< before
->child_count
; i
++) {
990 if (before
->children
[i
] == after
) {
991 before
->child_latency
[i
] = MAX2(before
->child_latency
[i
], latency
);
996 if (before
->child_array_size
<= before
->child_count
) {
997 if (before
->child_array_size
< 16)
998 before
->child_array_size
= 16;
1000 before
->child_array_size
*= 2;
1002 before
->children
= reralloc(mem_ctx
, before
->children
,
1004 before
->child_array_size
);
1005 before
->child_latency
= reralloc(mem_ctx
, before
->child_latency
,
1006 int, before
->child_array_size
);
1009 before
->children
[before
->child_count
] = after
;
1010 before
->child_latency
[before
->child_count
] = latency
;
1011 before
->child_count
++;
1012 after
->parent_count
++;
1016 instruction_scheduler::add_dep(schedule_node
*before
, schedule_node
*after
)
1021 add_dep(before
, after
, before
->latency
);
1025 is_scheduling_barrier(const backend_instruction
*inst
)
1027 return inst
->opcode
== FS_OPCODE_PLACEHOLDER_HALT
||
1028 inst
->is_control_flow() ||
1029 inst
->has_side_effects();
1033 * Sometimes we really want this node to execute after everything that
1034 * was before it and before everything that followed it. This adds
1035 * the deps to do so.
1038 instruction_scheduler::add_barrier_deps(schedule_node
*n
)
1040 schedule_node
*prev
= (schedule_node
*)n
->prev
;
1041 schedule_node
*next
= (schedule_node
*)n
->next
;
1044 while (!prev
->is_head_sentinel()) {
1045 add_dep(prev
, n
, 0);
1046 if (is_scheduling_barrier(prev
->inst
))
1048 prev
= (schedule_node
*)prev
->prev
;
1053 while (!next
->is_tail_sentinel()) {
1054 add_dep(n
, next
, 0);
1055 if (is_scheduling_barrier(next
->inst
))
1057 next
= (schedule_node
*)next
->next
;
1062 /* instruction scheduling needs to be aware of when an MRF write
1063 * actually writes 2 MRFs.
1066 fs_instruction_scheduler::is_compressed(fs_inst
*inst
)
1068 return inst
->exec_size
== 16;
1072 fs_instruction_scheduler::calculate_deps()
1074 /* Pre-register-allocation, this tracks the last write per VGRF offset.
1075 * After register allocation, reg_offsets are gone and we track individual
1078 schedule_node
**last_grf_write
;
1079 schedule_node
*last_mrf_write
[BRW_MAX_MRF(v
->devinfo
->gen
)];
1080 schedule_node
*last_conditional_mod
[8] = {};
1081 schedule_node
*last_accumulator_write
= NULL
;
1082 /* Fixed HW registers are assumed to be separate from the virtual
1083 * GRFs, so they can be tracked separately. We don't really write
1084 * to fixed GRFs much, so don't bother tracking them on a more
1087 schedule_node
*last_fixed_grf_write
= NULL
;
1089 last_grf_write
= (schedule_node
**)calloc(sizeof(schedule_node
*), grf_count
* 16);
1090 memset(last_mrf_write
, 0, sizeof(last_mrf_write
));
1092 /* top-to-bottom dependencies: RAW and WAW. */
1093 foreach_in_list(schedule_node
, n
, &instructions
) {
1094 fs_inst
*inst
= (fs_inst
*)n
->inst
;
1096 if (is_scheduling_barrier(inst
))
1097 add_barrier_deps(n
);
1099 /* read-after-write deps. */
1100 for (int i
= 0; i
< inst
->sources
; i
++) {
1101 if (inst
->src
[i
].file
== VGRF
) {
1102 if (post_reg_alloc
) {
1103 for (unsigned r
= 0; r
< regs_read(inst
, i
); r
++)
1104 add_dep(last_grf_write
[inst
->src
[i
].nr
+ r
], n
);
1106 for (unsigned r
= 0; r
< regs_read(inst
, i
); r
++) {
1107 add_dep(last_grf_write
[inst
->src
[i
].nr
* 16 +
1108 inst
->src
[i
].offset
/ REG_SIZE
+ r
], n
);
1111 } else if (inst
->src
[i
].file
== FIXED_GRF
) {
1112 if (post_reg_alloc
) {
1113 for (unsigned r
= 0; r
< regs_read(inst
, i
); r
++)
1114 add_dep(last_grf_write
[inst
->src
[i
].nr
+ r
], n
);
1116 add_dep(last_fixed_grf_write
, n
);
1118 } else if (inst
->src
[i
].is_accumulator()) {
1119 add_dep(last_accumulator_write
, n
);
1120 } else if (inst
->src
[i
].file
== ARF
) {
1121 add_barrier_deps(n
);
1125 if (inst
->base_mrf
!= -1) {
1126 for (int i
= 0; i
< inst
->mlen
; i
++) {
1127 /* It looks like the MRF regs are released in the send
1128 * instruction once it's sent, not when the result comes
1131 add_dep(last_mrf_write
[inst
->base_mrf
+ i
], n
);
1135 if (const unsigned mask
= inst
->flags_read(v
->devinfo
)) {
1136 assert(mask
< (1 << ARRAY_SIZE(last_conditional_mod
)));
1138 for (unsigned i
= 0; i
< ARRAY_SIZE(last_conditional_mod
); i
++) {
1139 if (mask
& (1 << i
))
1140 add_dep(last_conditional_mod
[i
], n
);
1144 if (inst
->reads_accumulator_implicitly()) {
1145 add_dep(last_accumulator_write
, n
);
1148 /* write-after-write deps. */
1149 if (inst
->dst
.file
== VGRF
) {
1150 if (post_reg_alloc
) {
1151 for (unsigned r
= 0; r
< regs_written(inst
); r
++) {
1152 add_dep(last_grf_write
[inst
->dst
.nr
+ r
], n
);
1153 last_grf_write
[inst
->dst
.nr
+ r
] = n
;
1156 for (unsigned r
= 0; r
< regs_written(inst
); r
++) {
1157 add_dep(last_grf_write
[inst
->dst
.nr
* 16 +
1158 inst
->dst
.offset
/ REG_SIZE
+ r
], n
);
1159 last_grf_write
[inst
->dst
.nr
* 16 +
1160 inst
->dst
.offset
/ REG_SIZE
+ r
] = n
;
1163 } else if (inst
->dst
.file
== MRF
) {
1164 int reg
= inst
->dst
.nr
& ~BRW_MRF_COMPR4
;
1166 add_dep(last_mrf_write
[reg
], n
);
1167 last_mrf_write
[reg
] = n
;
1168 if (is_compressed(inst
)) {
1169 if (inst
->dst
.nr
& BRW_MRF_COMPR4
)
1173 add_dep(last_mrf_write
[reg
], n
);
1174 last_mrf_write
[reg
] = n
;
1176 } else if (inst
->dst
.file
== FIXED_GRF
) {
1177 if (post_reg_alloc
) {
1178 for (unsigned r
= 0; r
< regs_written(inst
); r
++)
1179 last_grf_write
[inst
->dst
.nr
+ r
] = n
;
1181 last_fixed_grf_write
= n
;
1183 } else if (inst
->dst
.is_accumulator()) {
1184 add_dep(last_accumulator_write
, n
);
1185 last_accumulator_write
= n
;
1186 } else if (inst
->dst
.file
== ARF
&& !inst
->dst
.is_null()) {
1187 add_barrier_deps(n
);
1190 if (inst
->mlen
> 0 && inst
->base_mrf
!= -1) {
1191 for (int i
= 0; i
< v
->implied_mrf_writes(inst
); i
++) {
1192 add_dep(last_mrf_write
[inst
->base_mrf
+ i
], n
);
1193 last_mrf_write
[inst
->base_mrf
+ i
] = n
;
1197 if (const unsigned mask
= inst
->flags_written()) {
1198 assert(mask
< (1 << ARRAY_SIZE(last_conditional_mod
)));
1200 for (unsigned i
= 0; i
< ARRAY_SIZE(last_conditional_mod
); i
++) {
1201 if (mask
& (1 << i
)) {
1202 add_dep(last_conditional_mod
[i
], n
, 0);
1203 last_conditional_mod
[i
] = n
;
1208 if (inst
->writes_accumulator_implicitly(v
->devinfo
) &&
1209 !inst
->dst
.is_accumulator()) {
1210 add_dep(last_accumulator_write
, n
);
1211 last_accumulator_write
= n
;
1215 /* bottom-to-top dependencies: WAR */
1216 memset(last_grf_write
, 0, sizeof(schedule_node
*) * grf_count
* 16);
1217 memset(last_mrf_write
, 0, sizeof(last_mrf_write
));
1218 memset(last_conditional_mod
, 0, sizeof(last_conditional_mod
));
1219 last_accumulator_write
= NULL
;
1220 last_fixed_grf_write
= NULL
;
1222 foreach_in_list_reverse_safe(schedule_node
, n
, &instructions
) {
1223 fs_inst
*inst
= (fs_inst
*)n
->inst
;
1225 /* write-after-read deps. */
1226 for (int i
= 0; i
< inst
->sources
; i
++) {
1227 if (inst
->src
[i
].file
== VGRF
) {
1228 if (post_reg_alloc
) {
1229 for (unsigned r
= 0; r
< regs_read(inst
, i
); r
++)
1230 add_dep(n
, last_grf_write
[inst
->src
[i
].nr
+ r
], 0);
1232 for (unsigned r
= 0; r
< regs_read(inst
, i
); r
++) {
1233 add_dep(n
, last_grf_write
[inst
->src
[i
].nr
* 16 +
1234 inst
->src
[i
].offset
/ REG_SIZE
+ r
], 0);
1237 } else if (inst
->src
[i
].file
== FIXED_GRF
) {
1238 if (post_reg_alloc
) {
1239 for (unsigned r
= 0; r
< regs_read(inst
, i
); r
++)
1240 add_dep(n
, last_grf_write
[inst
->src
[i
].nr
+ r
], 0);
1242 add_dep(n
, last_fixed_grf_write
, 0);
1244 } else if (inst
->src
[i
].is_accumulator()) {
1245 add_dep(n
, last_accumulator_write
, 0);
1246 } else if (inst
->src
[i
].file
== ARF
) {
1247 add_barrier_deps(n
);
1251 if (inst
->base_mrf
!= -1) {
1252 for (int i
= 0; i
< inst
->mlen
; i
++) {
1253 /* It looks like the MRF regs are released in the send
1254 * instruction once it's sent, not when the result comes
1257 add_dep(n
, last_mrf_write
[inst
->base_mrf
+ i
], 2);
1261 if (const unsigned mask
= inst
->flags_read(v
->devinfo
)) {
1262 assert(mask
< (1 << ARRAY_SIZE(last_conditional_mod
)));
1264 for (unsigned i
= 0; i
< ARRAY_SIZE(last_conditional_mod
); i
++) {
1265 if (mask
& (1 << i
))
1266 add_dep(n
, last_conditional_mod
[i
]);
1270 if (inst
->reads_accumulator_implicitly()) {
1271 add_dep(n
, last_accumulator_write
);
1274 /* Update the things this instruction wrote, so earlier reads
1275 * can mark this as WAR dependency.
1277 if (inst
->dst
.file
== VGRF
) {
1278 if (post_reg_alloc
) {
1279 for (unsigned r
= 0; r
< regs_written(inst
); r
++)
1280 last_grf_write
[inst
->dst
.nr
+ r
] = n
;
1282 for (unsigned r
= 0; r
< regs_written(inst
); r
++) {
1283 last_grf_write
[inst
->dst
.nr
* 16 +
1284 inst
->dst
.offset
/ REG_SIZE
+ r
] = n
;
1287 } else if (inst
->dst
.file
== MRF
) {
1288 int reg
= inst
->dst
.nr
& ~BRW_MRF_COMPR4
;
1290 last_mrf_write
[reg
] = n
;
1292 if (is_compressed(inst
)) {
1293 if (inst
->dst
.nr
& BRW_MRF_COMPR4
)
1298 last_mrf_write
[reg
] = n
;
1300 } else if (inst
->dst
.file
== FIXED_GRF
) {
1301 if (post_reg_alloc
) {
1302 for (unsigned r
= 0; r
< regs_written(inst
); r
++)
1303 last_grf_write
[inst
->dst
.nr
+ r
] = n
;
1305 last_fixed_grf_write
= n
;
1307 } else if (inst
->dst
.is_accumulator()) {
1308 last_accumulator_write
= n
;
1309 } else if (inst
->dst
.file
== ARF
&& !inst
->dst
.is_null()) {
1310 add_barrier_deps(n
);
1313 if (inst
->mlen
> 0 && inst
->base_mrf
!= -1) {
1314 for (int i
= 0; i
< v
->implied_mrf_writes(inst
); i
++) {
1315 last_mrf_write
[inst
->base_mrf
+ i
] = n
;
1319 if (const unsigned mask
= inst
->flags_written()) {
1320 assert(mask
< (1 << ARRAY_SIZE(last_conditional_mod
)));
1322 for (unsigned i
= 0; i
< ARRAY_SIZE(last_conditional_mod
); i
++) {
1323 if (mask
& (1 << i
))
1324 last_conditional_mod
[i
] = n
;
1328 if (inst
->writes_accumulator_implicitly(v
->devinfo
)) {
1329 last_accumulator_write
= n
;
1333 free(last_grf_write
);
1337 vec4_instruction_scheduler::calculate_deps()
1339 schedule_node
*last_grf_write
[grf_count
];
1340 schedule_node
*last_mrf_write
[BRW_MAX_MRF(v
->devinfo
->gen
)];
1341 schedule_node
*last_conditional_mod
= NULL
;
1342 schedule_node
*last_accumulator_write
= NULL
;
1343 /* Fixed HW registers are assumed to be separate from the virtual
1344 * GRFs, so they can be tracked separately. We don't really write
1345 * to fixed GRFs much, so don't bother tracking them on a more
1348 schedule_node
*last_fixed_grf_write
= NULL
;
1350 memset(last_grf_write
, 0, sizeof(last_grf_write
));
1351 memset(last_mrf_write
, 0, sizeof(last_mrf_write
));
1353 /* top-to-bottom dependencies: RAW and WAW. */
1354 foreach_in_list(schedule_node
, n
, &instructions
) {
1355 vec4_instruction
*inst
= (vec4_instruction
*)n
->inst
;
1357 if (is_scheduling_barrier(inst
))
1358 add_barrier_deps(n
);
1360 /* read-after-write deps. */
1361 for (int i
= 0; i
< 3; i
++) {
1362 if (inst
->src
[i
].file
== VGRF
) {
1363 for (unsigned j
= 0; j
< regs_read(inst
, i
); ++j
)
1364 add_dep(last_grf_write
[inst
->src
[i
].nr
+ j
], n
);
1365 } else if (inst
->src
[i
].file
== FIXED_GRF
) {
1366 add_dep(last_fixed_grf_write
, n
);
1367 } else if (inst
->src
[i
].is_accumulator()) {
1368 assert(last_accumulator_write
);
1369 add_dep(last_accumulator_write
, n
);
1370 } else if (inst
->src
[i
].file
== ARF
) {
1371 add_barrier_deps(n
);
1375 if (inst
->reads_g0_implicitly())
1376 add_dep(last_fixed_grf_write
, n
);
1378 if (!inst
->is_send_from_grf()) {
1379 for (int i
= 0; i
< inst
->mlen
; i
++) {
1380 /* It looks like the MRF regs are released in the send
1381 * instruction once it's sent, not when the result comes
1384 add_dep(last_mrf_write
[inst
->base_mrf
+ i
], n
);
1388 if (inst
->reads_flag()) {
1389 assert(last_conditional_mod
);
1390 add_dep(last_conditional_mod
, n
);
1393 if (inst
->reads_accumulator_implicitly()) {
1394 assert(last_accumulator_write
);
1395 add_dep(last_accumulator_write
, n
);
1398 /* write-after-write deps. */
1399 if (inst
->dst
.file
== VGRF
) {
1400 for (unsigned j
= 0; j
< regs_written(inst
); ++j
) {
1401 add_dep(last_grf_write
[inst
->dst
.nr
+ j
], n
);
1402 last_grf_write
[inst
->dst
.nr
+ j
] = n
;
1404 } else if (inst
->dst
.file
== MRF
) {
1405 add_dep(last_mrf_write
[inst
->dst
.nr
], n
);
1406 last_mrf_write
[inst
->dst
.nr
] = n
;
1407 } else if (inst
->dst
.file
== FIXED_GRF
) {
1408 last_fixed_grf_write
= n
;
1409 } else if (inst
->dst
.is_accumulator()) {
1410 add_dep(last_accumulator_write
, n
);
1411 last_accumulator_write
= n
;
1412 } else if (inst
->dst
.file
== ARF
&& !inst
->dst
.is_null()) {
1413 add_barrier_deps(n
);
1416 if (inst
->mlen
> 0 && !inst
->is_send_from_grf()) {
1417 for (int i
= 0; i
< v
->implied_mrf_writes(inst
); i
++) {
1418 add_dep(last_mrf_write
[inst
->base_mrf
+ i
], n
);
1419 last_mrf_write
[inst
->base_mrf
+ i
] = n
;
1423 if (inst
->writes_flag()) {
1424 add_dep(last_conditional_mod
, n
, 0);
1425 last_conditional_mod
= n
;
1428 if (inst
->writes_accumulator_implicitly(v
->devinfo
) &&
1429 !inst
->dst
.is_accumulator()) {
1430 add_dep(last_accumulator_write
, n
);
1431 last_accumulator_write
= n
;
1435 /* bottom-to-top dependencies: WAR */
1436 memset(last_grf_write
, 0, sizeof(last_grf_write
));
1437 memset(last_mrf_write
, 0, sizeof(last_mrf_write
));
1438 last_conditional_mod
= NULL
;
1439 last_accumulator_write
= NULL
;
1440 last_fixed_grf_write
= NULL
;
1442 foreach_in_list_reverse_safe(schedule_node
, n
, &instructions
) {
1443 vec4_instruction
*inst
= (vec4_instruction
*)n
->inst
;
1445 /* write-after-read deps. */
1446 for (int i
= 0; i
< 3; i
++) {
1447 if (inst
->src
[i
].file
== VGRF
) {
1448 for (unsigned j
= 0; j
< regs_read(inst
, i
); ++j
)
1449 add_dep(n
, last_grf_write
[inst
->src
[i
].nr
+ j
]);
1450 } else if (inst
->src
[i
].file
== FIXED_GRF
) {
1451 add_dep(n
, last_fixed_grf_write
);
1452 } else if (inst
->src
[i
].is_accumulator()) {
1453 add_dep(n
, last_accumulator_write
);
1454 } else if (inst
->src
[i
].file
== ARF
) {
1455 add_barrier_deps(n
);
1459 if (!inst
->is_send_from_grf()) {
1460 for (int i
= 0; i
< inst
->mlen
; i
++) {
1461 /* It looks like the MRF regs are released in the send
1462 * instruction once it's sent, not when the result comes
1465 add_dep(n
, last_mrf_write
[inst
->base_mrf
+ i
], 2);
1469 if (inst
->reads_flag()) {
1470 add_dep(n
, last_conditional_mod
);
1473 if (inst
->reads_accumulator_implicitly()) {
1474 add_dep(n
, last_accumulator_write
);
1477 /* Update the things this instruction wrote, so earlier reads
1478 * can mark this as WAR dependency.
1480 if (inst
->dst
.file
== VGRF
) {
1481 for (unsigned j
= 0; j
< regs_written(inst
); ++j
)
1482 last_grf_write
[inst
->dst
.nr
+ j
] = n
;
1483 } else if (inst
->dst
.file
== MRF
) {
1484 last_mrf_write
[inst
->dst
.nr
] = n
;
1485 } else if (inst
->dst
.file
== FIXED_GRF
) {
1486 last_fixed_grf_write
= n
;
1487 } else if (inst
->dst
.is_accumulator()) {
1488 last_accumulator_write
= n
;
1489 } else if (inst
->dst
.file
== ARF
&& !inst
->dst
.is_null()) {
1490 add_barrier_deps(n
);
1493 if (inst
->mlen
> 0 && !inst
->is_send_from_grf()) {
1494 for (int i
= 0; i
< v
->implied_mrf_writes(inst
); i
++) {
1495 last_mrf_write
[inst
->base_mrf
+ i
] = n
;
1499 if (inst
->writes_flag()) {
1500 last_conditional_mod
= n
;
1503 if (inst
->writes_accumulator_implicitly(v
->devinfo
)) {
1504 last_accumulator_write
= n
;
1510 fs_instruction_scheduler::choose_instruction_to_schedule()
1512 schedule_node
*chosen
= NULL
;
1514 if (mode
== SCHEDULE_PRE
|| mode
== SCHEDULE_POST
) {
1515 int chosen_time
= 0;
1517 /* Of the instructions ready to execute or the closest to being ready,
1518 * choose the one most likely to unblock an early program exit, or
1519 * otherwise the oldest one.
1521 foreach_in_list(schedule_node
, n
, &instructions
) {
1523 exit_unblocked_time(n
) < exit_unblocked_time(chosen
) ||
1524 (exit_unblocked_time(n
) == exit_unblocked_time(chosen
) &&
1525 n
->unblocked_time
< chosen_time
)) {
1527 chosen_time
= n
->unblocked_time
;
1531 /* Before register allocation, we don't care about the latencies of
1532 * instructions. All we care about is reducing live intervals of
1533 * variables so that we can avoid register spilling, or get SIMD16
1534 * shaders which naturally do a better job of hiding instruction
1537 foreach_in_list(schedule_node
, n
, &instructions
) {
1538 fs_inst
*inst
= (fs_inst
*)n
->inst
;
1545 /* Most important: If we can definitely reduce register pressure, do
1548 int register_pressure_benefit
= get_register_pressure_benefit(n
->inst
);
1549 int chosen_register_pressure_benefit
=
1550 get_register_pressure_benefit(chosen
->inst
);
1552 if (register_pressure_benefit
> 0 &&
1553 register_pressure_benefit
> chosen_register_pressure_benefit
) {
1556 } else if (chosen_register_pressure_benefit
> 0 &&
1557 (register_pressure_benefit
<
1558 chosen_register_pressure_benefit
)) {
1562 if (mode
== SCHEDULE_PRE_LIFO
) {
1563 /* Prefer instructions that recently became available for
1564 * scheduling. These are the things that are most likely to
1565 * (eventually) make a variable dead and reduce register pressure.
1566 * Typical register pressure estimates don't work for us because
1567 * most of our pressure comes from texturing, where no single
1568 * instruction to schedule will make a vec4 value dead.
1570 if (n
->cand_generation
> chosen
->cand_generation
) {
1573 } else if (n
->cand_generation
< chosen
->cand_generation
) {
1577 /* On MRF-using chips, prefer non-SEND instructions. If we don't
1578 * do this, then because we prefer instructions that just became
1579 * candidates, we'll end up in a pattern of scheduling a SEND,
1580 * then the MRFs for the next SEND, then the next SEND, then the
1581 * MRFs, etc., without ever consuming the results of a send.
1583 if (v
->devinfo
->gen
< 7) {
1584 fs_inst
*chosen_inst
= (fs_inst
*)chosen
->inst
;
1586 /* We use size_written > 4 * exec_size as our test for the kind
1587 * of send instruction to avoid -- only sends generate many
1588 * regs, and a single-result send is probably actually reducing
1589 * register pressure.
1591 if (inst
->size_written
<= 4 * inst
->exec_size
&&
1592 chosen_inst
->size_written
> 4 * chosen_inst
->exec_size
) {
1595 } else if (inst
->size_written
> chosen_inst
->size_written
) {
1601 /* For instructions pushed on the cands list at the same time, prefer
1602 * the one with the highest delay to the end of the program. This is
1603 * most likely to have its values able to be consumed first (such as
1604 * for a large tree of lowered ubo loads, which appear reversed in
1605 * the instruction stream with respect to when they can be consumed).
1607 if (n
->delay
> chosen
->delay
) {
1610 } else if (n
->delay
< chosen
->delay
) {
1614 /* Prefer the node most likely to unblock an early program exit.
1616 if (exit_unblocked_time(n
) < exit_unblocked_time(chosen
)) {
1619 } else if (exit_unblocked_time(n
) > exit_unblocked_time(chosen
)) {
1623 /* If all other metrics are equal, we prefer the first instruction in
1624 * the list (program execution).
1633 vec4_instruction_scheduler::choose_instruction_to_schedule()
1635 schedule_node
*chosen
= NULL
;
1636 int chosen_time
= 0;
1638 /* Of the instructions ready to execute or the closest to being ready,
1639 * choose the oldest one.
1641 foreach_in_list(schedule_node
, n
, &instructions
) {
1642 if (!chosen
|| n
->unblocked_time
< chosen_time
) {
1644 chosen_time
= n
->unblocked_time
;
1652 fs_instruction_scheduler::issue_time(backend_instruction
*inst
)
1654 const unsigned overhead
= v
->bank_conflict_cycles((fs_inst
*)inst
);
1655 if (is_compressed((fs_inst
*)inst
))
1656 return 4 + overhead
;
1658 return 2 + overhead
;
1662 vec4_instruction_scheduler::issue_time(backend_instruction
*)
1664 /* We always execute as two vec4s in parallel. */
1669 instruction_scheduler::schedule_instructions(bblock_t
*block
)
1671 const struct gen_device_info
*devinfo
= bs
->devinfo
;
1673 if (!post_reg_alloc
)
1674 reg_pressure
= reg_pressure_in
[block
->num
];
1675 block_idx
= block
->num
;
1677 /* Remove non-DAG heads from the list. */
1678 foreach_in_list_safe(schedule_node
, n
, &instructions
) {
1679 if (n
->parent_count
!= 0)
1683 unsigned cand_generation
= 1;
1684 while (!instructions
.is_empty()) {
1685 schedule_node
*chosen
= choose_instruction_to_schedule();
1687 /* Schedule this instruction. */
1690 chosen
->inst
->exec_node::remove();
1691 block
->instructions
.push_tail(chosen
->inst
);
1692 instructions_to_schedule
--;
1694 if (!post_reg_alloc
) {
1695 reg_pressure
-= get_register_pressure_benefit(chosen
->inst
);
1696 update_register_pressure(chosen
->inst
);
1699 /* If we expected a delay for scheduling, then bump the clock to reflect
1700 * that. In reality, the hardware will switch to another hyperthread
1701 * and may not return to dispatching our thread for a while even after
1702 * we're unblocked. After this, we have the time when the chosen
1703 * instruction will start executing.
1705 time
= MAX2(time
, chosen
->unblocked_time
);
1707 /* Update the clock for how soon an instruction could start after the
1710 time
+= issue_time(chosen
->inst
);
1713 fprintf(stderr
, "clock %4d, scheduled: ", time
);
1714 bs
->dump_instruction(chosen
->inst
);
1715 if (!post_reg_alloc
)
1716 fprintf(stderr
, "(register pressure %d)\n", reg_pressure
);
1719 /* Now that we've scheduled a new instruction, some of its
1720 * children can be promoted to the list of instructions ready to
1721 * be scheduled. Update the children's unblocked time for this
1722 * DAG edge as we do so.
1724 for (int i
= chosen
->child_count
- 1; i
>= 0; i
--) {
1725 schedule_node
*child
= chosen
->children
[i
];
1727 child
->unblocked_time
= MAX2(child
->unblocked_time
,
1728 time
+ chosen
->child_latency
[i
]);
1731 fprintf(stderr
, "\tchild %d, %d parents: ", i
, child
->parent_count
);
1732 bs
->dump_instruction(child
->inst
);
1735 child
->cand_generation
= cand_generation
;
1736 child
->parent_count
--;
1737 if (child
->parent_count
== 0) {
1739 fprintf(stderr
, "\t\tnow available\n");
1741 instructions
.push_head(child
);
1746 /* Shared resource: the mathbox. There's one mathbox per EU on Gen6+
1747 * but it's more limited pre-gen6, so if we send something off to it then
1748 * the next math instruction isn't going to make progress until the first
1751 if (devinfo
->gen
< 6 && chosen
->inst
->is_math()) {
1752 foreach_in_list(schedule_node
, n
, &instructions
) {
1753 if (n
->inst
->is_math())
1754 n
->unblocked_time
= MAX2(n
->unblocked_time
,
1755 time
+ chosen
->latency
);
1760 assert(instructions_to_schedule
== 0);
1762 block
->cycle_count
= time
;
1765 static unsigned get_cycle_count(cfg_t
*cfg
)
1767 unsigned count
= 0, multiplier
= 1;
1768 foreach_block(block
, cfg
) {
1769 if (block
->start()->opcode
== BRW_OPCODE_DO
)
1770 multiplier
*= 10; /* assume that loops execute ~10 times */
1772 count
+= block
->cycle_count
* multiplier
;
1774 if (block
->end()->opcode
== BRW_OPCODE_WHILE
)
1782 instruction_scheduler::run(cfg_t
*cfg
)
1784 if (debug
&& !post_reg_alloc
) {
1785 fprintf(stderr
, "\nInstructions before scheduling (reg_alloc %d)\n",
1787 bs
->dump_instructions();
1790 if (!post_reg_alloc
)
1791 setup_liveness(cfg
);
1793 foreach_block(block
, cfg
) {
1794 if (reads_remaining
) {
1795 memset(reads_remaining
, 0,
1796 grf_count
* sizeof(*reads_remaining
));
1797 memset(hw_reads_remaining
, 0,
1798 hw_reg_count
* sizeof(*hw_reads_remaining
));
1799 memset(written
, 0, grf_count
* sizeof(*written
));
1801 foreach_inst_in_block(fs_inst
, inst
, block
)
1802 count_reads_remaining(inst
);
1805 add_insts_from_block(block
);
1812 schedule_instructions(block
);
1815 if (debug
&& !post_reg_alloc
) {
1816 fprintf(stderr
, "\nInstructions after scheduling (reg_alloc %d)\n",
1818 bs
->dump_instructions();
1821 cfg
->cycle_count
= get_cycle_count(cfg
);
1825 fs_visitor::schedule_instructions(instruction_scheduler_mode mode
)
1827 if (mode
!= SCHEDULE_POST
)
1828 calculate_live_intervals();
1831 if (mode
== SCHEDULE_POST
)
1832 grf_count
= grf_used
;
1834 grf_count
= alloc
.count
;
1836 fs_instruction_scheduler
sched(this, grf_count
, first_non_payload_grf
,
1837 cfg
->num_blocks
, mode
);
1840 invalidate_live_intervals();
1844 vec4_visitor::opt_schedule_instructions()
1846 vec4_instruction_scheduler
sched(this, prog_data
->total_grf
);
1849 invalidate_live_intervals();