2 * Copyright © 2010 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Eric Anholt <eric@anholt.net>
29 #include "brw_fs_live_variables.h"
32 #include "brw_shader.h"
36 /** @file brw_fs_schedule_instructions.cpp
38 * List scheduling of FS instructions.
40 * The basic model of the list scheduler is to take a basic block,
41 * compute a DAG of the dependencies (RAW ordering with latency, WAW
42 * ordering with latency, WAR ordering), and make a list of the DAG heads.
43 * Heuristically pick a DAG head, then put all the children that are
44 * now DAG heads into the list of things to schedule.
46 * The heuristic is the important part. We're trying to be cheap,
47 * since actually computing the optimal scheduling is NP complete.
48 * What we do is track a "current clock". When we schedule a node, we
49 * update the earliest-unblocked clock time of its children, and
50 * increment the clock. Then, when trying to schedule, we just pick
51 * the earliest-unblocked instruction to schedule.
53 * Note that often there will be many things which could execute
54 * immediately, and there are a range of heuristic options to choose
55 * from in picking among those.
58 static bool debug
= false;
60 class instruction_scheduler
;
62 class schedule_node
: public exec_node
65 schedule_node(backend_instruction
*inst
, instruction_scheduler
*sched
);
66 void set_latency_gen4();
67 void set_latency_gen7(bool is_haswell
);
69 backend_instruction
*inst
;
70 schedule_node
**children
;
79 * Which iteration of pushing groups of children onto the candidates list
80 * this node was a part of.
82 unsigned cand_generation
;
85 * This is the sum of the instruction's latency plus the maximum delay of
86 * its children, or just the issue_time if it's a leaf node.
91 * Preferred exit node among the (direct or indirect) successors of this
92 * node. Among the scheduler nodes blocked by this node, this will be the
93 * one that may cause earliest program termination, or NULL if none of the
94 * successors is an exit node.
100 * Lower bound of the scheduling time after which one of the instructions
101 * blocked by this node may lead to program termination.
103 * exit_unblocked_time() determines a strict partial ordering relation '«' on
104 * the set of scheduler nodes as follows:
106 * n « m <-> exit_unblocked_time(n) < exit_unblocked_time(m)
108 * which can be used to heuristically order nodes according to how early they
109 * can unblock an exit node and lead to program termination.
112 exit_unblocked_time(const schedule_node
*n
)
114 return n
->exit
? n
->exit
->unblocked_time
: INT_MAX
;
118 schedule_node::set_latency_gen4()
121 int math_latency
= 22;
123 switch (inst
->opcode
) {
124 case SHADER_OPCODE_RCP
:
125 this->latency
= 1 * chans
* math_latency
;
127 case SHADER_OPCODE_RSQ
:
128 this->latency
= 2 * chans
* math_latency
;
130 case SHADER_OPCODE_INT_QUOTIENT
:
131 case SHADER_OPCODE_SQRT
:
132 case SHADER_OPCODE_LOG2
:
133 /* full precision log. partial is 2. */
134 this->latency
= 3 * chans
* math_latency
;
136 case SHADER_OPCODE_INT_REMAINDER
:
137 case SHADER_OPCODE_EXP2
:
138 /* full precision. partial is 3, same throughput. */
139 this->latency
= 4 * chans
* math_latency
;
141 case SHADER_OPCODE_POW
:
142 this->latency
= 8 * chans
* math_latency
;
144 case SHADER_OPCODE_SIN
:
145 case SHADER_OPCODE_COS
:
146 /* minimum latency, max is 12 rounds. */
147 this->latency
= 5 * chans
* math_latency
;
156 schedule_node::set_latency_gen7(bool is_haswell
)
158 switch (inst
->opcode
) {
161 * (since the last two src operands are in different register banks):
162 * mad(8) g4<1>F g2.2<4,4,1>F.x g2<4,4,1>F.x g3.1<4,4,1>F.x { align16 WE_normal 1Q };
164 * 3 cycles on IVB, 4 on HSW
165 * (since the last two src operands are in the same register bank):
166 * mad(8) g4<1>F g2.2<4,4,1>F.x g2<4,4,1>F.x g2.1<4,4,1>F.x { align16 WE_normal 1Q };
168 * 18 cycles on IVB, 16 on HSW
169 * (since the last two src operands are in different register banks):
170 * mad(8) g4<1>F g2.2<4,4,1>F.x g2<4,4,1>F.x g3.1<4,4,1>F.x { align16 WE_normal 1Q };
171 * mov(8) null g4<4,5,1>F { align16 WE_normal 1Q };
173 * 20 cycles on IVB, 18 on HSW
174 * (since the last two src operands are in the same register bank):
175 * mad(8) g4<1>F g2.2<4,4,1>F.x g2<4,4,1>F.x g2.1<4,4,1>F.x { align16 WE_normal 1Q };
176 * mov(8) null g4<4,4,1>F { align16 WE_normal 1Q };
179 /* Our register allocator doesn't know about register banks, so use the
182 latency
= is_haswell
? 16 : 18;
187 * (since the last two src operands are in different register banks):
188 * lrp(8) g4<1>F g2.2<4,4,1>F.x g2<4,4,1>F.x g3.1<4,4,1>F.x { align16 WE_normal 1Q };
190 * 3 cycles on IVB, 4 on HSW
191 * (since the last two src operands are in the same register bank):
192 * lrp(8) g4<1>F g2.2<4,4,1>F.x g2<4,4,1>F.x g2.1<4,4,1>F.x { align16 WE_normal 1Q };
194 * 16 cycles on IVB, 14 on HSW
195 * (since the last two src operands are in different register banks):
196 * lrp(8) g4<1>F g2.2<4,4,1>F.x g2<4,4,1>F.x g3.1<4,4,1>F.x { align16 WE_normal 1Q };
197 * mov(8) null g4<4,4,1>F { align16 WE_normal 1Q };
200 * (since the last two src operands are in the same register bank):
201 * lrp(8) g4<1>F g2.2<4,4,1>F.x g2<4,4,1>F.x g2.1<4,4,1>F.x { align16 WE_normal 1Q };
202 * mov(8) null g4<4,4,1>F { align16 WE_normal 1Q };
205 /* Our register allocator doesn't know about register banks, so use the
211 case SHADER_OPCODE_RCP
:
212 case SHADER_OPCODE_RSQ
:
213 case SHADER_OPCODE_SQRT
:
214 case SHADER_OPCODE_LOG2
:
215 case SHADER_OPCODE_EXP2
:
216 case SHADER_OPCODE_SIN
:
217 case SHADER_OPCODE_COS
:
219 * math inv(8) g4<1>F g2<0,1,0>F null { align1 WE_normal 1Q };
222 * math inv(8) g4<1>F g2<0,1,0>F null { align1 WE_normal 1Q };
223 * mov(8) null g4<8,8,1>F { align1 WE_normal 1Q };
225 * Same for exp2, log2, rsq, sqrt, sin, cos.
227 latency
= is_haswell
? 14 : 16;
230 case SHADER_OPCODE_POW
:
232 * math pow(8) g4<1>F g2<0,1,0>F g2.1<0,1,0>F { align1 WE_normal 1Q };
235 * math pow(8) g4<1>F g2<0,1,0>F g2.1<0,1,0>F { align1 WE_normal 1Q };
236 * mov(8) null g4<8,8,1>F { align1 WE_normal 1Q };
238 latency
= is_haswell
? 22 : 24;
241 case SHADER_OPCODE_TEX
:
242 case SHADER_OPCODE_TXD
:
243 case SHADER_OPCODE_TXF
:
244 case SHADER_OPCODE_TXF_LZ
:
245 case SHADER_OPCODE_TXL
:
246 case SHADER_OPCODE_TXL_LZ
:
248 * mov(8) g115<1>F 0F { align1 WE_normal 1Q };
249 * mov(8) g114<1>F 0F { align1 WE_normal 1Q };
250 * send(8) g4<1>UW g114<8,8,1>F
251 * sampler (10, 0, 0, 1) mlen 2 rlen 4 { align1 WE_normal 1Q };
253 * 697 +/-49 cycles (min 610, n=26):
254 * mov(8) g115<1>F 0F { align1 WE_normal 1Q };
255 * mov(8) g114<1>F 0F { align1 WE_normal 1Q };
256 * send(8) g4<1>UW g114<8,8,1>F
257 * sampler (10, 0, 0, 1) mlen 2 rlen 4 { align1 WE_normal 1Q };
258 * mov(8) null g4<8,8,1>F { align1 WE_normal 1Q };
260 * So the latency on our first texture load of the batchbuffer takes
261 * ~700 cycles, since the caches are cold at that point.
263 * 840 +/- 92 cycles (min 720, n=25):
264 * mov(8) g115<1>F 0F { align1 WE_normal 1Q };
265 * mov(8) g114<1>F 0F { align1 WE_normal 1Q };
266 * send(8) g4<1>UW g114<8,8,1>F
267 * sampler (10, 0, 0, 1) mlen 2 rlen 4 { align1 WE_normal 1Q };
268 * mov(8) null g4<8,8,1>F { align1 WE_normal 1Q };
269 * send(8) g4<1>UW g114<8,8,1>F
270 * sampler (10, 0, 0, 1) mlen 2 rlen 4 { align1 WE_normal 1Q };
271 * mov(8) null g4<8,8,1>F { align1 WE_normal 1Q };
273 * On the second load, it takes just an extra ~140 cycles, and after
274 * accounting for the 14 cycles of the MOV's latency, that makes ~130.
276 * 683 +/- 49 cycles (min = 602, n=47):
277 * mov(8) g115<1>F 0F { align1 WE_normal 1Q };
278 * mov(8) g114<1>F 0F { align1 WE_normal 1Q };
279 * send(8) g4<1>UW g114<8,8,1>F
280 * sampler (10, 0, 0, 1) mlen 2 rlen 4 { align1 WE_normal 1Q };
281 * send(8) g50<1>UW g114<8,8,1>F
282 * sampler (10, 0, 0, 1) mlen 2 rlen 4 { align1 WE_normal 1Q };
283 * mov(8) null g4<8,8,1>F { align1 WE_normal 1Q };
285 * The unit appears to be pipelined, since this matches up with the
286 * cache-cold case, despite there being two loads here. If you replace
287 * the g4 in the MOV to null with g50, it's still 693 +/- 52 (n=39).
289 * So, take some number between the cache-hot 140 cycles and the
290 * cache-cold 700 cycles. No particular tuning was done on this.
292 * I haven't done significant testing of the non-TEX opcodes. TXL at
293 * least looked about the same as TEX.
298 case SHADER_OPCODE_TXS
:
299 /* Testing textureSize(sampler2D, 0), one load was 420 +/- 41
301 * mov(8) g114<1>UD 0D { align1 WE_normal 1Q };
302 * send(8) g6<1>UW g114<8,8,1>F
303 * sampler (10, 0, 10, 1) mlen 1 rlen 4 { align1 WE_normal 1Q };
304 * mov(16) g6<1>F g6<8,8,1>D { align1 WE_normal 1Q };
307 * Two loads was 535 +/- 30 cycles (n=19):
308 * mov(16) g114<1>UD 0D { align1 WE_normal 1H };
309 * send(16) g6<1>UW g114<8,8,1>F
310 * sampler (10, 0, 10, 2) mlen 2 rlen 8 { align1 WE_normal 1H };
311 * mov(16) g114<1>UD 0D { align1 WE_normal 1H };
312 * mov(16) g6<1>F g6<8,8,1>D { align1 WE_normal 1H };
313 * send(16) g8<1>UW g114<8,8,1>F
314 * sampler (10, 0, 10, 2) mlen 2 rlen 8 { align1 WE_normal 1H };
315 * mov(16) g8<1>F g8<8,8,1>D { align1 WE_normal 1H };
316 * add(16) g6<1>F g6<8,8,1>F g8<8,8,1>F { align1 WE_normal 1H };
318 * Since the only caches that should matter are just the
319 * instruction/state cache containing the surface state, assume that we
320 * always have hot caches.
325 case FS_OPCODE_VARYING_PULL_CONSTANT_LOAD_GEN4
:
326 case FS_OPCODE_VARYING_PULL_CONSTANT_LOAD_GEN7
:
327 case FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD
:
328 case FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD_GEN7
:
329 case VS_OPCODE_PULL_CONSTANT_LOAD
:
330 /* testing using varying-index pull constants:
333 * mov(8) g4<1>D g2.1<0,1,0>F { align1 WE_normal 1Q };
334 * send(8) g4<1>F g4<8,8,1>D
335 * data (9, 2, 3) mlen 1 rlen 1 { align1 WE_normal 1Q };
338 * mov(8) g4<1>D g2.1<0,1,0>F { align1 WE_normal 1Q };
339 * send(8) g4<1>F g4<8,8,1>D
340 * data (9, 2, 3) mlen 1 rlen 1 { align1 WE_normal 1Q };
341 * mov(8) null g4<8,8,1>F { align1 WE_normal 1Q };
344 * mov(8) g4<1>D g2.1<0,1,0>F { align1 WE_normal 1Q };
345 * send(8) g4<1>F g4<8,8,1>D
346 * data (9, 2, 3) mlen 1 rlen 1 { align1 WE_normal 1Q };
347 * mov(8) null g4<8,8,1>F { align1 WE_normal 1Q };
348 * send(8) g4<1>F g4<8,8,1>D
349 * data (9, 2, 3) mlen 1 rlen 1 { align1 WE_normal 1Q };
350 * mov(8) null g4<8,8,1>F { align1 WE_normal 1Q };
352 * So, if it's cache-hot, it's about 140. If it's cache cold, it's
353 * about 460. We expect to mostly be cache hot, so pick something more
359 case SHADER_OPCODE_GEN7_SCRATCH_READ
:
360 /* Testing a load from offset 0, that had been previously written:
362 * send(8) g114<1>UW g0<8,8,1>F data (0, 0, 0) mlen 1 rlen 1 { align1 WE_normal 1Q };
363 * mov(8) null g114<8,8,1>F { align1 WE_normal 1Q };
365 * The cycles spent seemed to be grouped around 40-50 (as low as 38),
366 * then around 140. Presumably this is cache hit vs miss.
371 case SHADER_OPCODE_UNTYPED_ATOMIC
:
372 case SHADER_OPCODE_TYPED_ATOMIC
:
374 * mov(8) g112<1>ud 0x00000000ud { align1 WE_all 1Q };
375 * mov(1) g112.7<1>ud g1.7<0,1,0>ud { align1 WE_all };
376 * mov(8) g113<1>ud 0x00000000ud { align1 WE_normal 1Q };
377 * send(8) g4<1>ud g112<8,8,1>ud
378 * data (38, 5, 6) mlen 2 rlen 1 { align1 WE_normal 1Q };
380 * Running it 100 times as fragment shader on a 128x128 quad
381 * gives an average latency of 13867 cycles per atomic op,
382 * standard deviation 3%. Note that this is a rather
383 * pessimistic estimate, the actual latency in cases with few
384 * collisions between threads and favorable pipelining has been
385 * seen to be reduced by a factor of 100.
390 case SHADER_OPCODE_UNTYPED_SURFACE_READ
:
391 case SHADER_OPCODE_UNTYPED_SURFACE_WRITE
:
392 case SHADER_OPCODE_TYPED_SURFACE_READ
:
393 case SHADER_OPCODE_TYPED_SURFACE_WRITE
:
395 * mov(8) g112<1>UD 0x00000000UD { align1 WE_all 1Q };
396 * mov(1) g112.7<1>UD g1.7<0,1,0>UD { align1 WE_all };
397 * mov(8) g113<1>UD 0x00000000UD { align1 WE_normal 1Q };
398 * send(8) g4<1>UD g112<8,8,1>UD
399 * data (38, 6, 5) mlen 2 rlen 1 { align1 WE_normal 1Q };
401 * . [repeats 8 times]
403 * mov(8) g112<1>UD 0x00000000UD { align1 WE_all 1Q };
404 * mov(1) g112.7<1>UD g1.7<0,1,0>UD { align1 WE_all };
405 * mov(8) g113<1>UD 0x00000000UD { align1 WE_normal 1Q };
406 * send(8) g4<1>UD g112<8,8,1>UD
407 * data (38, 6, 5) mlen 2 rlen 1 { align1 WE_normal 1Q };
409 * Running it 100 times as fragment shader on a 128x128 quad
410 * gives an average latency of 583 cycles per surface read,
411 * standard deviation 0.9%.
413 latency
= is_haswell
? 300 : 600;
418 * mul(8) g4<1>F g2<0,1,0>F 0.5F { align1 WE_normal 1Q };
421 * mul(8) g4<1>F g2<0,1,0>F 0.5F { align1 WE_normal 1Q };
422 * mov(8) null g4<8,8,1>F { align1 WE_normal 1Q };
429 class instruction_scheduler
{
431 instruction_scheduler(backend_shader
*s
, int grf_count
,
432 int hw_reg_count
, int block_count
,
433 instruction_scheduler_mode mode
)
436 this->mem_ctx
= ralloc_context(NULL
);
437 this->grf_count
= grf_count
;
438 this->hw_reg_count
= hw_reg_count
;
439 this->instructions
.make_empty();
440 this->instructions_to_schedule
= 0;
441 this->post_reg_alloc
= (mode
== SCHEDULE_POST
);
443 if (!post_reg_alloc
) {
444 this->reg_pressure_in
= rzalloc_array(mem_ctx
, int, block_count
);
446 this->livein
= ralloc_array(mem_ctx
, BITSET_WORD
*, block_count
);
447 for (int i
= 0; i
< block_count
; i
++)
448 this->livein
[i
] = rzalloc_array(mem_ctx
, BITSET_WORD
,
449 BITSET_WORDS(grf_count
));
451 this->liveout
= ralloc_array(mem_ctx
, BITSET_WORD
*, block_count
);
452 for (int i
= 0; i
< block_count
; i
++)
453 this->liveout
[i
] = rzalloc_array(mem_ctx
, BITSET_WORD
,
454 BITSET_WORDS(grf_count
));
456 this->hw_liveout
= ralloc_array(mem_ctx
, BITSET_WORD
*, block_count
);
457 for (int i
= 0; i
< block_count
; i
++)
458 this->hw_liveout
[i
] = rzalloc_array(mem_ctx
, BITSET_WORD
,
459 BITSET_WORDS(hw_reg_count
));
461 this->written
= rzalloc_array(mem_ctx
, bool, grf_count
);
463 this->reads_remaining
= rzalloc_array(mem_ctx
, int, grf_count
);
465 this->hw_reads_remaining
= rzalloc_array(mem_ctx
, int, hw_reg_count
);
467 this->reg_pressure_in
= NULL
;
469 this->liveout
= NULL
;
470 this->hw_liveout
= NULL
;
471 this->written
= NULL
;
472 this->reads_remaining
= NULL
;
473 this->hw_reads_remaining
= NULL
;
477 ~instruction_scheduler()
479 ralloc_free(this->mem_ctx
);
481 void add_barrier_deps(schedule_node
*n
);
482 void add_dep(schedule_node
*before
, schedule_node
*after
, int latency
);
483 void add_dep(schedule_node
*before
, schedule_node
*after
);
485 void run(cfg_t
*cfg
);
486 void add_insts_from_block(bblock_t
*block
);
487 void compute_delays();
488 void compute_exits();
489 virtual void calculate_deps() = 0;
490 virtual schedule_node
*choose_instruction_to_schedule() = 0;
493 * Returns how many cycles it takes the instruction to issue.
495 * Instructions in gen hardware are handled one simd4 vector at a time,
496 * with 1 cycle per vector dispatched. Thus SIMD8 pixel shaders take 2
497 * cycles to dispatch and SIMD16 (compressed) instructions take 4.
499 virtual int issue_time(backend_instruction
*inst
) = 0;
501 virtual void count_reads_remaining(backend_instruction
*inst
) = 0;
502 virtual void setup_liveness(cfg_t
*cfg
) = 0;
503 virtual void update_register_pressure(backend_instruction
*inst
) = 0;
504 virtual int get_register_pressure_benefit(backend_instruction
*inst
) = 0;
506 void schedule_instructions(bblock_t
*block
);
511 int instructions_to_schedule
;
516 exec_list instructions
;
519 instruction_scheduler_mode mode
;
522 * The register pressure at the beginning of each basic block.
525 int *reg_pressure_in
;
528 * The virtual GRF's whose range overlaps the beginning of each basic block.
531 BITSET_WORD
**livein
;
534 * The virtual GRF's whose range overlaps the end of each basic block.
537 BITSET_WORD
**liveout
;
540 * The hardware GRF's whose range overlaps the end of each basic block.
543 BITSET_WORD
**hw_liveout
;
546 * Whether we've scheduled a write for this virtual GRF yet.
552 * How many reads we haven't scheduled for this virtual GRF yet.
555 int *reads_remaining
;
558 * How many reads we haven't scheduled for this hardware GRF yet.
561 int *hw_reads_remaining
;
564 class fs_instruction_scheduler
: public instruction_scheduler
567 fs_instruction_scheduler(fs_visitor
*v
, int grf_count
, int hw_reg_count
,
569 instruction_scheduler_mode mode
);
570 void calculate_deps();
571 bool is_compressed(fs_inst
*inst
);
572 schedule_node
*choose_instruction_to_schedule();
573 int issue_time(backend_instruction
*inst
);
576 void count_reads_remaining(backend_instruction
*inst
);
577 void setup_liveness(cfg_t
*cfg
);
578 void update_register_pressure(backend_instruction
*inst
);
579 int get_register_pressure_benefit(backend_instruction
*inst
);
582 fs_instruction_scheduler::fs_instruction_scheduler(fs_visitor
*v
,
583 int grf_count
, int hw_reg_count
,
585 instruction_scheduler_mode mode
)
586 : instruction_scheduler(v
, grf_count
, hw_reg_count
, block_count
, mode
),
592 is_src_duplicate(fs_inst
*inst
, int src
)
594 for (int i
= 0; i
< src
; i
++)
595 if (inst
->src
[i
].equals(inst
->src
[src
]))
602 fs_instruction_scheduler::count_reads_remaining(backend_instruction
*be
)
604 fs_inst
*inst
= (fs_inst
*)be
;
606 if (!reads_remaining
)
609 for (int i
= 0; i
< inst
->sources
; i
++) {
610 if (is_src_duplicate(inst
, i
))
613 if (inst
->src
[i
].file
== VGRF
) {
614 reads_remaining
[inst
->src
[i
].nr
]++;
615 } else if (inst
->src
[i
].file
== FIXED_GRF
) {
616 if (inst
->src
[i
].nr
>= hw_reg_count
)
619 for (unsigned j
= 0; j
< regs_read(inst
, i
); j
++)
620 hw_reads_remaining
[inst
->src
[i
].nr
+ j
]++;
626 fs_instruction_scheduler::setup_liveness(cfg_t
*cfg
)
628 /* First, compute liveness on a per-GRF level using the in/out sets from
629 * liveness calculation.
631 for (int block
= 0; block
< cfg
->num_blocks
; block
++) {
632 for (int i
= 0; i
< v
->live_intervals
->num_vars
; i
++) {
633 if (BITSET_TEST(v
->live_intervals
->block_data
[block
].livein
, i
)) {
634 int vgrf
= v
->live_intervals
->vgrf_from_var
[i
];
635 if (!BITSET_TEST(livein
[block
], vgrf
)) {
636 reg_pressure_in
[block
] += v
->alloc
.sizes
[vgrf
];
637 BITSET_SET(livein
[block
], vgrf
);
641 if (BITSET_TEST(v
->live_intervals
->block_data
[block
].liveout
, i
))
642 BITSET_SET(liveout
[block
], v
->live_intervals
->vgrf_from_var
[i
]);
646 /* Now, extend the live in/live out sets for when a range crosses a block
647 * boundary, which matches what our register allocator/interference code
648 * does to account for force_writemask_all and incompatible exec_mask's.
650 for (int block
= 0; block
< cfg
->num_blocks
- 1; block
++) {
651 for (int i
= 0; i
< grf_count
; i
++) {
652 if (v
->virtual_grf_start
[i
] <= cfg
->blocks
[block
]->end_ip
&&
653 v
->virtual_grf_end
[i
] >= cfg
->blocks
[block
+ 1]->start_ip
) {
654 if (!BITSET_TEST(livein
[block
+ 1], i
)) {
655 reg_pressure_in
[block
+ 1] += v
->alloc
.sizes
[i
];
656 BITSET_SET(livein
[block
+ 1], i
);
659 BITSET_SET(liveout
[block
], i
);
664 int payload_last_use_ip
[hw_reg_count
];
665 v
->calculate_payload_ranges(hw_reg_count
, payload_last_use_ip
);
667 for (int i
= 0; i
< hw_reg_count
; i
++) {
668 if (payload_last_use_ip
[i
] == -1)
671 for (int block
= 0; block
< cfg
->num_blocks
; block
++) {
672 if (cfg
->blocks
[block
]->start_ip
<= payload_last_use_ip
[i
])
673 reg_pressure_in
[block
]++;
675 if (cfg
->blocks
[block
]->end_ip
<= payload_last_use_ip
[i
])
676 BITSET_SET(hw_liveout
[block
], i
);
682 fs_instruction_scheduler::update_register_pressure(backend_instruction
*be
)
684 fs_inst
*inst
= (fs_inst
*)be
;
686 if (!reads_remaining
)
689 if (inst
->dst
.file
== VGRF
) {
690 written
[inst
->dst
.nr
] = true;
693 for (int i
= 0; i
< inst
->sources
; i
++) {
694 if (is_src_duplicate(inst
, i
))
697 if (inst
->src
[i
].file
== VGRF
) {
698 reads_remaining
[inst
->src
[i
].nr
]--;
699 } else if (inst
->src
[i
].file
== FIXED_GRF
&&
700 inst
->src
[i
].nr
< hw_reg_count
) {
701 for (unsigned off
= 0; off
< regs_read(inst
, i
); off
++)
702 hw_reads_remaining
[inst
->src
[i
].nr
+ off
]--;
708 fs_instruction_scheduler::get_register_pressure_benefit(backend_instruction
*be
)
710 fs_inst
*inst
= (fs_inst
*)be
;
713 if (inst
->dst
.file
== VGRF
) {
714 if (!BITSET_TEST(livein
[block_idx
], inst
->dst
.nr
) &&
715 !written
[inst
->dst
.nr
])
716 benefit
-= v
->alloc
.sizes
[inst
->dst
.nr
];
719 for (int i
= 0; i
< inst
->sources
; i
++) {
720 if (is_src_duplicate(inst
, i
))
723 if (inst
->src
[i
].file
== VGRF
&&
724 !BITSET_TEST(liveout
[block_idx
], inst
->src
[i
].nr
) &&
725 reads_remaining
[inst
->src
[i
].nr
] == 1)
726 benefit
+= v
->alloc
.sizes
[inst
->src
[i
].nr
];
728 if (inst
->src
[i
].file
== FIXED_GRF
&&
729 inst
->src
[i
].nr
< hw_reg_count
) {
730 for (unsigned off
= 0; off
< regs_read(inst
, i
); off
++) {
731 int reg
= inst
->src
[i
].nr
+ off
;
732 if (!BITSET_TEST(hw_liveout
[block_idx
], reg
) &&
733 hw_reads_remaining
[reg
] == 1) {
743 class vec4_instruction_scheduler
: public instruction_scheduler
746 vec4_instruction_scheduler(vec4_visitor
*v
, int grf_count
);
747 void calculate_deps();
748 schedule_node
*choose_instruction_to_schedule();
749 int issue_time(backend_instruction
*inst
);
752 void count_reads_remaining(backend_instruction
*inst
);
753 void setup_liveness(cfg_t
*cfg
);
754 void update_register_pressure(backend_instruction
*inst
);
755 int get_register_pressure_benefit(backend_instruction
*inst
);
758 vec4_instruction_scheduler::vec4_instruction_scheduler(vec4_visitor
*v
,
760 : instruction_scheduler(v
, grf_count
, 0, 0, SCHEDULE_POST
),
766 vec4_instruction_scheduler::count_reads_remaining(backend_instruction
*)
771 vec4_instruction_scheduler::setup_liveness(cfg_t
*)
776 vec4_instruction_scheduler::update_register_pressure(backend_instruction
*)
781 vec4_instruction_scheduler::get_register_pressure_benefit(backend_instruction
*)
786 schedule_node::schedule_node(backend_instruction
*inst
,
787 instruction_scheduler
*sched
)
789 const struct gen_device_info
*devinfo
= sched
->bs
->devinfo
;
792 this->child_array_size
= 0;
793 this->children
= NULL
;
794 this->child_latency
= NULL
;
795 this->child_count
= 0;
796 this->parent_count
= 0;
797 this->unblocked_time
= 0;
798 this->cand_generation
= 0;
802 /* We can't measure Gen6 timings directly but expect them to be much
803 * closer to Gen7 than Gen4.
805 if (!sched
->post_reg_alloc
)
807 else if (devinfo
->gen
>= 6)
808 set_latency_gen7(devinfo
->is_haswell
);
814 instruction_scheduler::add_insts_from_block(bblock_t
*block
)
816 foreach_inst_in_block(backend_instruction
, inst
, block
) {
817 schedule_node
*n
= new(mem_ctx
) schedule_node(inst
, this);
819 instructions
.push_tail(n
);
822 this->instructions_to_schedule
= block
->end_ip
- block
->start_ip
+ 1;
825 /** Computation of the delay member of each node. */
827 instruction_scheduler::compute_delays()
829 foreach_in_list_reverse(schedule_node
, n
, &instructions
) {
830 if (!n
->child_count
) {
831 n
->delay
= issue_time(n
->inst
);
833 for (int i
= 0; i
< n
->child_count
; i
++) {
834 assert(n
->children
[i
]->delay
);
835 n
->delay
= MAX2(n
->delay
, n
->latency
+ n
->children
[i
]->delay
);
842 instruction_scheduler::compute_exits()
844 /* Calculate a lower bound of the scheduling time of each node in the
845 * graph. This is analogous to the node's critical path but calculated
846 * from the top instead of from the bottom of the block.
848 foreach_in_list(schedule_node
, n
, &instructions
) {
849 for (int i
= 0; i
< n
->child_count
; i
++) {
850 n
->children
[i
]->unblocked_time
=
851 MAX2(n
->children
[i
]->unblocked_time
,
852 n
->unblocked_time
+ issue_time(n
->inst
) + n
->child_latency
[i
]);
856 /* Calculate the exit of each node by induction based on the exit nodes of
857 * its children. The preferred exit of a node is the one among the exit
858 * nodes of its children which can be unblocked first according to the
859 * optimistic unblocked time estimate calculated above.
861 foreach_in_list_reverse(schedule_node
, n
, &instructions
) {
862 n
->exit
= (n
->inst
->opcode
== FS_OPCODE_DISCARD_JUMP
? n
: NULL
);
864 for (int i
= 0; i
< n
->child_count
; i
++) {
865 if (exit_unblocked_time(n
->children
[i
]) < exit_unblocked_time(n
))
866 n
->exit
= n
->children
[i
]->exit
;
872 * Add a dependency between two instruction nodes.
874 * The @after node will be scheduled after @before. We will try to
875 * schedule it @latency cycles after @before, but no guarantees there.
878 instruction_scheduler::add_dep(schedule_node
*before
, schedule_node
*after
,
881 if (!before
|| !after
)
884 assert(before
!= after
);
886 for (int i
= 0; i
< before
->child_count
; i
++) {
887 if (before
->children
[i
] == after
) {
888 before
->child_latency
[i
] = MAX2(before
->child_latency
[i
], latency
);
893 if (before
->child_array_size
<= before
->child_count
) {
894 if (before
->child_array_size
< 16)
895 before
->child_array_size
= 16;
897 before
->child_array_size
*= 2;
899 before
->children
= reralloc(mem_ctx
, before
->children
,
901 before
->child_array_size
);
902 before
->child_latency
= reralloc(mem_ctx
, before
->child_latency
,
903 int, before
->child_array_size
);
906 before
->children
[before
->child_count
] = after
;
907 before
->child_latency
[before
->child_count
] = latency
;
908 before
->child_count
++;
909 after
->parent_count
++;
913 instruction_scheduler::add_dep(schedule_node
*before
, schedule_node
*after
)
918 add_dep(before
, after
, before
->latency
);
922 is_scheduling_barrier(const backend_instruction
*inst
)
924 return inst
->opcode
== FS_OPCODE_PLACEHOLDER_HALT
||
925 inst
->is_control_flow() ||
926 inst
->has_side_effects();
930 * Sometimes we really want this node to execute after everything that
931 * was before it and before everything that followed it. This adds
935 instruction_scheduler::add_barrier_deps(schedule_node
*n
)
937 schedule_node
*prev
= (schedule_node
*)n
->prev
;
938 schedule_node
*next
= (schedule_node
*)n
->next
;
941 while (!prev
->is_head_sentinel()) {
943 if (is_scheduling_barrier(prev
->inst
))
945 prev
= (schedule_node
*)prev
->prev
;
950 while (!next
->is_tail_sentinel()) {
952 if (is_scheduling_barrier(next
->inst
))
954 next
= (schedule_node
*)next
->next
;
959 /* instruction scheduling needs to be aware of when an MRF write
960 * actually writes 2 MRFs.
963 fs_instruction_scheduler::is_compressed(fs_inst
*inst
)
965 return inst
->exec_size
== 16;
969 fs_instruction_scheduler::calculate_deps()
971 /* Pre-register-allocation, this tracks the last write per VGRF offset.
972 * After register allocation, reg_offsets are gone and we track individual
975 schedule_node
*last_grf_write
[grf_count
* 16];
976 schedule_node
*last_mrf_write
[BRW_MAX_MRF(v
->devinfo
->gen
)];
977 schedule_node
*last_conditional_mod
[8] = {};
978 schedule_node
*last_accumulator_write
= NULL
;
979 /* Fixed HW registers are assumed to be separate from the virtual
980 * GRFs, so they can be tracked separately. We don't really write
981 * to fixed GRFs much, so don't bother tracking them on a more
984 schedule_node
*last_fixed_grf_write
= NULL
;
986 memset(last_grf_write
, 0, sizeof(last_grf_write
));
987 memset(last_mrf_write
, 0, sizeof(last_mrf_write
));
989 /* top-to-bottom dependencies: RAW and WAW. */
990 foreach_in_list(schedule_node
, n
, &instructions
) {
991 fs_inst
*inst
= (fs_inst
*)n
->inst
;
993 if (is_scheduling_barrier(inst
))
996 /* read-after-write deps. */
997 for (int i
= 0; i
< inst
->sources
; i
++) {
998 if (inst
->src
[i
].file
== VGRF
) {
999 if (post_reg_alloc
) {
1000 for (unsigned r
= 0; r
< regs_read(inst
, i
); r
++)
1001 add_dep(last_grf_write
[inst
->src
[i
].nr
+ r
], n
);
1003 for (unsigned r
= 0; r
< regs_read(inst
, i
); r
++) {
1004 add_dep(last_grf_write
[inst
->src
[i
].nr
* 16 +
1005 inst
->src
[i
].offset
/ REG_SIZE
+ r
], n
);
1008 } else if (inst
->src
[i
].file
== FIXED_GRF
) {
1009 if (post_reg_alloc
) {
1010 for (unsigned r
= 0; r
< regs_read(inst
, i
); r
++)
1011 add_dep(last_grf_write
[inst
->src
[i
].nr
+ r
], n
);
1013 add_dep(last_fixed_grf_write
, n
);
1015 } else if (inst
->src
[i
].is_accumulator()) {
1016 add_dep(last_accumulator_write
, n
);
1017 } else if (inst
->src
[i
].file
== ARF
) {
1018 add_barrier_deps(n
);
1022 if (inst
->base_mrf
!= -1) {
1023 for (int i
= 0; i
< inst
->mlen
; i
++) {
1024 /* It looks like the MRF regs are released in the send
1025 * instruction once it's sent, not when the result comes
1028 add_dep(last_mrf_write
[inst
->base_mrf
+ i
], n
);
1032 if (const unsigned mask
= inst
->flags_read(v
->devinfo
)) {
1033 assert(mask
< (1 << ARRAY_SIZE(last_conditional_mod
)));
1035 for (unsigned i
= 0; i
< ARRAY_SIZE(last_conditional_mod
); i
++) {
1036 if (mask
& (1 << i
))
1037 add_dep(last_conditional_mod
[i
], n
);
1041 if (inst
->reads_accumulator_implicitly()) {
1042 add_dep(last_accumulator_write
, n
);
1045 /* write-after-write deps. */
1046 if (inst
->dst
.file
== VGRF
) {
1047 if (post_reg_alloc
) {
1048 for (unsigned r
= 0; r
< regs_written(inst
); r
++) {
1049 add_dep(last_grf_write
[inst
->dst
.nr
+ r
], n
);
1050 last_grf_write
[inst
->dst
.nr
+ r
] = n
;
1053 for (unsigned r
= 0; r
< regs_written(inst
); r
++) {
1054 add_dep(last_grf_write
[inst
->dst
.nr
* 16 +
1055 inst
->dst
.offset
/ REG_SIZE
+ r
], n
);
1056 last_grf_write
[inst
->dst
.nr
* 16 +
1057 inst
->dst
.offset
/ REG_SIZE
+ r
] = n
;
1060 } else if (inst
->dst
.file
== MRF
) {
1061 int reg
= inst
->dst
.nr
& ~BRW_MRF_COMPR4
;
1063 add_dep(last_mrf_write
[reg
], n
);
1064 last_mrf_write
[reg
] = n
;
1065 if (is_compressed(inst
)) {
1066 if (inst
->dst
.nr
& BRW_MRF_COMPR4
)
1070 add_dep(last_mrf_write
[reg
], n
);
1071 last_mrf_write
[reg
] = n
;
1073 } else if (inst
->dst
.file
== FIXED_GRF
) {
1074 if (post_reg_alloc
) {
1075 for (unsigned r
= 0; r
< regs_written(inst
); r
++)
1076 last_grf_write
[inst
->dst
.nr
+ r
] = n
;
1078 last_fixed_grf_write
= n
;
1080 } else if (inst
->dst
.is_accumulator()) {
1081 add_dep(last_accumulator_write
, n
);
1082 last_accumulator_write
= n
;
1083 } else if (inst
->dst
.file
== ARF
&& !inst
->dst
.is_null()) {
1084 add_barrier_deps(n
);
1087 if (inst
->mlen
> 0 && inst
->base_mrf
!= -1) {
1088 for (int i
= 0; i
< v
->implied_mrf_writes(inst
); i
++) {
1089 add_dep(last_mrf_write
[inst
->base_mrf
+ i
], n
);
1090 last_mrf_write
[inst
->base_mrf
+ i
] = n
;
1094 if (const unsigned mask
= inst
->flags_written()) {
1095 assert(mask
< (1 << ARRAY_SIZE(last_conditional_mod
)));
1097 for (unsigned i
= 0; i
< ARRAY_SIZE(last_conditional_mod
); i
++) {
1098 if (mask
& (1 << i
)) {
1099 add_dep(last_conditional_mod
[i
], n
, 0);
1100 last_conditional_mod
[i
] = n
;
1105 if (inst
->writes_accumulator_implicitly(v
->devinfo
) &&
1106 !inst
->dst
.is_accumulator()) {
1107 add_dep(last_accumulator_write
, n
);
1108 last_accumulator_write
= n
;
1112 /* bottom-to-top dependencies: WAR */
1113 memset(last_grf_write
, 0, sizeof(last_grf_write
));
1114 memset(last_mrf_write
, 0, sizeof(last_mrf_write
));
1115 memset(last_conditional_mod
, 0, sizeof(last_conditional_mod
));
1116 last_accumulator_write
= NULL
;
1117 last_fixed_grf_write
= NULL
;
1119 foreach_in_list_reverse_safe(schedule_node
, n
, &instructions
) {
1120 fs_inst
*inst
= (fs_inst
*)n
->inst
;
1122 /* write-after-read deps. */
1123 for (int i
= 0; i
< inst
->sources
; i
++) {
1124 if (inst
->src
[i
].file
== VGRF
) {
1125 if (post_reg_alloc
) {
1126 for (unsigned r
= 0; r
< regs_read(inst
, i
); r
++)
1127 add_dep(n
, last_grf_write
[inst
->src
[i
].nr
+ r
], 0);
1129 for (unsigned r
= 0; r
< regs_read(inst
, i
); r
++) {
1130 add_dep(n
, last_grf_write
[inst
->src
[i
].nr
* 16 +
1131 inst
->src
[i
].offset
/ REG_SIZE
+ r
], 0);
1134 } else if (inst
->src
[i
].file
== FIXED_GRF
) {
1135 if (post_reg_alloc
) {
1136 for (unsigned r
= 0; r
< regs_read(inst
, i
); r
++)
1137 add_dep(n
, last_grf_write
[inst
->src
[i
].nr
+ r
], 0);
1139 add_dep(n
, last_fixed_grf_write
, 0);
1141 } else if (inst
->src
[i
].is_accumulator()) {
1142 add_dep(n
, last_accumulator_write
, 0);
1143 } else if (inst
->src
[i
].file
== ARF
) {
1144 add_barrier_deps(n
);
1148 if (inst
->base_mrf
!= -1) {
1149 for (int i
= 0; i
< inst
->mlen
; i
++) {
1150 /* It looks like the MRF regs are released in the send
1151 * instruction once it's sent, not when the result comes
1154 add_dep(n
, last_mrf_write
[inst
->base_mrf
+ i
], 2);
1158 if (const unsigned mask
= inst
->flags_read(v
->devinfo
)) {
1159 assert(mask
< (1 << ARRAY_SIZE(last_conditional_mod
)));
1161 for (unsigned i
= 0; i
< ARRAY_SIZE(last_conditional_mod
); i
++) {
1162 if (mask
& (1 << i
))
1163 add_dep(n
, last_conditional_mod
[i
]);
1167 if (inst
->reads_accumulator_implicitly()) {
1168 add_dep(n
, last_accumulator_write
);
1171 /* Update the things this instruction wrote, so earlier reads
1172 * can mark this as WAR dependency.
1174 if (inst
->dst
.file
== VGRF
) {
1175 if (post_reg_alloc
) {
1176 for (unsigned r
= 0; r
< regs_written(inst
); r
++)
1177 last_grf_write
[inst
->dst
.nr
+ r
] = n
;
1179 for (unsigned r
= 0; r
< regs_written(inst
); r
++) {
1180 last_grf_write
[inst
->dst
.nr
* 16 +
1181 inst
->dst
.offset
/ REG_SIZE
+ r
] = n
;
1184 } else if (inst
->dst
.file
== MRF
) {
1185 int reg
= inst
->dst
.nr
& ~BRW_MRF_COMPR4
;
1187 last_mrf_write
[reg
] = n
;
1189 if (is_compressed(inst
)) {
1190 if (inst
->dst
.nr
& BRW_MRF_COMPR4
)
1195 last_mrf_write
[reg
] = n
;
1197 } else if (inst
->dst
.file
== FIXED_GRF
) {
1198 if (post_reg_alloc
) {
1199 for (unsigned r
= 0; r
< regs_written(inst
); r
++)
1200 last_grf_write
[inst
->dst
.nr
+ r
] = n
;
1202 last_fixed_grf_write
= n
;
1204 } else if (inst
->dst
.is_accumulator()) {
1205 last_accumulator_write
= n
;
1206 } else if (inst
->dst
.file
== ARF
&& !inst
->dst
.is_null()) {
1207 add_barrier_deps(n
);
1210 if (inst
->mlen
> 0 && inst
->base_mrf
!= -1) {
1211 for (int i
= 0; i
< v
->implied_mrf_writes(inst
); i
++) {
1212 last_mrf_write
[inst
->base_mrf
+ i
] = n
;
1216 if (const unsigned mask
= inst
->flags_written()) {
1217 assert(mask
< (1 << ARRAY_SIZE(last_conditional_mod
)));
1219 for (unsigned i
= 0; i
< ARRAY_SIZE(last_conditional_mod
); i
++) {
1220 if (mask
& (1 << i
))
1221 last_conditional_mod
[i
] = n
;
1225 if (inst
->writes_accumulator_implicitly(v
->devinfo
)) {
1226 last_accumulator_write
= n
;
1232 vec4_instruction_scheduler::calculate_deps()
1234 schedule_node
*last_grf_write
[grf_count
];
1235 schedule_node
*last_mrf_write
[BRW_MAX_MRF(v
->devinfo
->gen
)];
1236 schedule_node
*last_conditional_mod
= NULL
;
1237 schedule_node
*last_accumulator_write
= NULL
;
1238 /* Fixed HW registers are assumed to be separate from the virtual
1239 * GRFs, so they can be tracked separately. We don't really write
1240 * to fixed GRFs much, so don't bother tracking them on a more
1243 schedule_node
*last_fixed_grf_write
= NULL
;
1245 memset(last_grf_write
, 0, sizeof(last_grf_write
));
1246 memset(last_mrf_write
, 0, sizeof(last_mrf_write
));
1248 /* top-to-bottom dependencies: RAW and WAW. */
1249 foreach_in_list(schedule_node
, n
, &instructions
) {
1250 vec4_instruction
*inst
= (vec4_instruction
*)n
->inst
;
1252 if (is_scheduling_barrier(inst
))
1253 add_barrier_deps(n
);
1255 /* read-after-write deps. */
1256 for (int i
= 0; i
< 3; i
++) {
1257 if (inst
->src
[i
].file
== VGRF
) {
1258 for (unsigned j
= 0; j
< regs_read(inst
, i
); ++j
)
1259 add_dep(last_grf_write
[inst
->src
[i
].nr
+ j
], n
);
1260 } else if (inst
->src
[i
].file
== FIXED_GRF
) {
1261 add_dep(last_fixed_grf_write
, n
);
1262 } else if (inst
->src
[i
].is_accumulator()) {
1263 assert(last_accumulator_write
);
1264 add_dep(last_accumulator_write
, n
);
1265 } else if (inst
->src
[i
].file
== ARF
) {
1266 add_barrier_deps(n
);
1270 if (inst
->reads_g0_implicitly())
1271 add_dep(last_fixed_grf_write
, n
);
1273 if (!inst
->is_send_from_grf()) {
1274 for (int i
= 0; i
< inst
->mlen
; i
++) {
1275 /* It looks like the MRF regs are released in the send
1276 * instruction once it's sent, not when the result comes
1279 add_dep(last_mrf_write
[inst
->base_mrf
+ i
], n
);
1283 if (inst
->reads_flag()) {
1284 assert(last_conditional_mod
);
1285 add_dep(last_conditional_mod
, n
);
1288 if (inst
->reads_accumulator_implicitly()) {
1289 assert(last_accumulator_write
);
1290 add_dep(last_accumulator_write
, n
);
1293 /* write-after-write deps. */
1294 if (inst
->dst
.file
== VGRF
) {
1295 for (unsigned j
= 0; j
< regs_written(inst
); ++j
) {
1296 add_dep(last_grf_write
[inst
->dst
.nr
+ j
], n
);
1297 last_grf_write
[inst
->dst
.nr
+ j
] = n
;
1299 } else if (inst
->dst
.file
== MRF
) {
1300 add_dep(last_mrf_write
[inst
->dst
.nr
], n
);
1301 last_mrf_write
[inst
->dst
.nr
] = n
;
1302 } else if (inst
->dst
.file
== FIXED_GRF
) {
1303 last_fixed_grf_write
= n
;
1304 } else if (inst
->dst
.is_accumulator()) {
1305 add_dep(last_accumulator_write
, n
);
1306 last_accumulator_write
= n
;
1307 } else if (inst
->dst
.file
== ARF
&& !inst
->dst
.is_null()) {
1308 add_barrier_deps(n
);
1311 if (inst
->mlen
> 0 && !inst
->is_send_from_grf()) {
1312 for (int i
= 0; i
< v
->implied_mrf_writes(inst
); i
++) {
1313 add_dep(last_mrf_write
[inst
->base_mrf
+ i
], n
);
1314 last_mrf_write
[inst
->base_mrf
+ i
] = n
;
1318 if (inst
->writes_flag()) {
1319 add_dep(last_conditional_mod
, n
, 0);
1320 last_conditional_mod
= n
;
1323 if (inst
->writes_accumulator_implicitly(v
->devinfo
) &&
1324 !inst
->dst
.is_accumulator()) {
1325 add_dep(last_accumulator_write
, n
);
1326 last_accumulator_write
= n
;
1330 /* bottom-to-top dependencies: WAR */
1331 memset(last_grf_write
, 0, sizeof(last_grf_write
));
1332 memset(last_mrf_write
, 0, sizeof(last_mrf_write
));
1333 last_conditional_mod
= NULL
;
1334 last_accumulator_write
= NULL
;
1335 last_fixed_grf_write
= NULL
;
1337 foreach_in_list_reverse_safe(schedule_node
, n
, &instructions
) {
1338 vec4_instruction
*inst
= (vec4_instruction
*)n
->inst
;
1340 /* write-after-read deps. */
1341 for (int i
= 0; i
< 3; i
++) {
1342 if (inst
->src
[i
].file
== VGRF
) {
1343 for (unsigned j
= 0; j
< regs_read(inst
, i
); ++j
)
1344 add_dep(n
, last_grf_write
[inst
->src
[i
].nr
+ j
]);
1345 } else if (inst
->src
[i
].file
== FIXED_GRF
) {
1346 add_dep(n
, last_fixed_grf_write
);
1347 } else if (inst
->src
[i
].is_accumulator()) {
1348 add_dep(n
, last_accumulator_write
);
1349 } else if (inst
->src
[i
].file
== ARF
) {
1350 add_barrier_deps(n
);
1354 if (!inst
->is_send_from_grf()) {
1355 for (int i
= 0; i
< inst
->mlen
; i
++) {
1356 /* It looks like the MRF regs are released in the send
1357 * instruction once it's sent, not when the result comes
1360 add_dep(n
, last_mrf_write
[inst
->base_mrf
+ i
], 2);
1364 if (inst
->reads_flag()) {
1365 add_dep(n
, last_conditional_mod
);
1368 if (inst
->reads_accumulator_implicitly()) {
1369 add_dep(n
, last_accumulator_write
);
1372 /* Update the things this instruction wrote, so earlier reads
1373 * can mark this as WAR dependency.
1375 if (inst
->dst
.file
== VGRF
) {
1376 for (unsigned j
= 0; j
< regs_written(inst
); ++j
)
1377 last_grf_write
[inst
->dst
.nr
+ j
] = n
;
1378 } else if (inst
->dst
.file
== MRF
) {
1379 last_mrf_write
[inst
->dst
.nr
] = n
;
1380 } else if (inst
->dst
.file
== FIXED_GRF
) {
1381 last_fixed_grf_write
= n
;
1382 } else if (inst
->dst
.is_accumulator()) {
1383 last_accumulator_write
= n
;
1384 } else if (inst
->dst
.file
== ARF
&& !inst
->dst
.is_null()) {
1385 add_barrier_deps(n
);
1388 if (inst
->mlen
> 0 && !inst
->is_send_from_grf()) {
1389 for (int i
= 0; i
< v
->implied_mrf_writes(inst
); i
++) {
1390 last_mrf_write
[inst
->base_mrf
+ i
] = n
;
1394 if (inst
->writes_flag()) {
1395 last_conditional_mod
= n
;
1398 if (inst
->writes_accumulator_implicitly(v
->devinfo
)) {
1399 last_accumulator_write
= n
;
1405 fs_instruction_scheduler::choose_instruction_to_schedule()
1407 schedule_node
*chosen
= NULL
;
1409 if (mode
== SCHEDULE_PRE
|| mode
== SCHEDULE_POST
) {
1410 int chosen_time
= 0;
1412 /* Of the instructions ready to execute or the closest to being ready,
1413 * choose the one most likely to unblock an early program exit, or
1414 * otherwise the oldest one.
1416 foreach_in_list(schedule_node
, n
, &instructions
) {
1418 exit_unblocked_time(n
) < exit_unblocked_time(chosen
) ||
1419 (exit_unblocked_time(n
) == exit_unblocked_time(chosen
) &&
1420 n
->unblocked_time
< chosen_time
)) {
1422 chosen_time
= n
->unblocked_time
;
1426 /* Before register allocation, we don't care about the latencies of
1427 * instructions. All we care about is reducing live intervals of
1428 * variables so that we can avoid register spilling, or get SIMD16
1429 * shaders which naturally do a better job of hiding instruction
1432 foreach_in_list(schedule_node
, n
, &instructions
) {
1433 fs_inst
*inst
= (fs_inst
*)n
->inst
;
1440 /* Most important: If we can definitely reduce register pressure, do
1443 int register_pressure_benefit
= get_register_pressure_benefit(n
->inst
);
1444 int chosen_register_pressure_benefit
=
1445 get_register_pressure_benefit(chosen
->inst
);
1447 if (register_pressure_benefit
> 0 &&
1448 register_pressure_benefit
> chosen_register_pressure_benefit
) {
1451 } else if (chosen_register_pressure_benefit
> 0 &&
1452 (register_pressure_benefit
<
1453 chosen_register_pressure_benefit
)) {
1457 if (mode
== SCHEDULE_PRE_LIFO
) {
1458 /* Prefer instructions that recently became available for
1459 * scheduling. These are the things that are most likely to
1460 * (eventually) make a variable dead and reduce register pressure.
1461 * Typical register pressure estimates don't work for us because
1462 * most of our pressure comes from texturing, where no single
1463 * instruction to schedule will make a vec4 value dead.
1465 if (n
->cand_generation
> chosen
->cand_generation
) {
1468 } else if (n
->cand_generation
< chosen
->cand_generation
) {
1472 /* On MRF-using chips, prefer non-SEND instructions. If we don't
1473 * do this, then because we prefer instructions that just became
1474 * candidates, we'll end up in a pattern of scheduling a SEND,
1475 * then the MRFs for the next SEND, then the next SEND, then the
1476 * MRFs, etc., without ever consuming the results of a send.
1478 if (v
->devinfo
->gen
< 7) {
1479 fs_inst
*chosen_inst
= (fs_inst
*)chosen
->inst
;
1481 /* We use size_written > 4 * exec_size as our test for the kind
1482 * of send instruction to avoid -- only sends generate many
1483 * regs, and a single-result send is probably actually reducing
1484 * register pressure.
1486 if (inst
->size_written
<= 4 * inst
->exec_size
&&
1487 chosen_inst
->size_written
> 4 * chosen_inst
->exec_size
) {
1490 } else if (inst
->size_written
> chosen_inst
->size_written
) {
1496 /* For instructions pushed on the cands list at the same time, prefer
1497 * the one with the highest delay to the end of the program. This is
1498 * most likely to have its values able to be consumed first (such as
1499 * for a large tree of lowered ubo loads, which appear reversed in
1500 * the instruction stream with respect to when they can be consumed).
1502 if (n
->delay
> chosen
->delay
) {
1505 } else if (n
->delay
< chosen
->delay
) {
1509 /* Prefer the node most likely to unblock an early program exit.
1511 if (exit_unblocked_time(n
) < exit_unblocked_time(chosen
)) {
1514 } else if (exit_unblocked_time(n
) > exit_unblocked_time(chosen
)) {
1518 /* If all other metrics are equal, we prefer the first instruction in
1519 * the list (program execution).
1528 vec4_instruction_scheduler::choose_instruction_to_schedule()
1530 schedule_node
*chosen
= NULL
;
1531 int chosen_time
= 0;
1533 /* Of the instructions ready to execute or the closest to being ready,
1534 * choose the oldest one.
1536 foreach_in_list(schedule_node
, n
, &instructions
) {
1537 if (!chosen
|| n
->unblocked_time
< chosen_time
) {
1539 chosen_time
= n
->unblocked_time
;
1547 fs_instruction_scheduler::issue_time(backend_instruction
*inst
)
1549 const unsigned overhead
= v
->bank_conflict_cycles((fs_inst
*)inst
);
1550 if (is_compressed((fs_inst
*)inst
))
1551 return 4 + overhead
;
1553 return 2 + overhead
;
1557 vec4_instruction_scheduler::issue_time(backend_instruction
*)
1559 /* We always execute as two vec4s in parallel. */
1564 instruction_scheduler::schedule_instructions(bblock_t
*block
)
1566 const struct gen_device_info
*devinfo
= bs
->devinfo
;
1568 if (!post_reg_alloc
)
1569 reg_pressure
= reg_pressure_in
[block
->num
];
1570 block_idx
= block
->num
;
1572 /* Remove non-DAG heads from the list. */
1573 foreach_in_list_safe(schedule_node
, n
, &instructions
) {
1574 if (n
->parent_count
!= 0)
1578 unsigned cand_generation
= 1;
1579 while (!instructions
.is_empty()) {
1580 schedule_node
*chosen
= choose_instruction_to_schedule();
1582 /* Schedule this instruction. */
1585 chosen
->inst
->exec_node::remove();
1586 block
->instructions
.push_tail(chosen
->inst
);
1587 instructions_to_schedule
--;
1589 if (!post_reg_alloc
) {
1590 reg_pressure
-= get_register_pressure_benefit(chosen
->inst
);
1591 update_register_pressure(chosen
->inst
);
1594 /* If we expected a delay for scheduling, then bump the clock to reflect
1595 * that. In reality, the hardware will switch to another hyperthread
1596 * and may not return to dispatching our thread for a while even after
1597 * we're unblocked. After this, we have the time when the chosen
1598 * instruction will start executing.
1600 time
= MAX2(time
, chosen
->unblocked_time
);
1602 /* Update the clock for how soon an instruction could start after the
1605 time
+= issue_time(chosen
->inst
);
1608 fprintf(stderr
, "clock %4d, scheduled: ", time
);
1609 bs
->dump_instruction(chosen
->inst
);
1610 if (!post_reg_alloc
)
1611 fprintf(stderr
, "(register pressure %d)\n", reg_pressure
);
1614 /* Now that we've scheduled a new instruction, some of its
1615 * children can be promoted to the list of instructions ready to
1616 * be scheduled. Update the children's unblocked time for this
1617 * DAG edge as we do so.
1619 for (int i
= chosen
->child_count
- 1; i
>= 0; i
--) {
1620 schedule_node
*child
= chosen
->children
[i
];
1622 child
->unblocked_time
= MAX2(child
->unblocked_time
,
1623 time
+ chosen
->child_latency
[i
]);
1626 fprintf(stderr
, "\tchild %d, %d parents: ", i
, child
->parent_count
);
1627 bs
->dump_instruction(child
->inst
);
1630 child
->cand_generation
= cand_generation
;
1631 child
->parent_count
--;
1632 if (child
->parent_count
== 0) {
1634 fprintf(stderr
, "\t\tnow available\n");
1636 instructions
.push_head(child
);
1641 /* Shared resource: the mathbox. There's one mathbox per EU on Gen6+
1642 * but it's more limited pre-gen6, so if we send something off to it then
1643 * the next math instruction isn't going to make progress until the first
1646 if (devinfo
->gen
< 6 && chosen
->inst
->is_math()) {
1647 foreach_in_list(schedule_node
, n
, &instructions
) {
1648 if (n
->inst
->is_math())
1649 n
->unblocked_time
= MAX2(n
->unblocked_time
,
1650 time
+ chosen
->latency
);
1655 assert(instructions_to_schedule
== 0);
1657 block
->cycle_count
= time
;
1660 static unsigned get_cycle_count(cfg_t
*cfg
)
1662 unsigned count
= 0, multiplier
= 1;
1663 foreach_block(block
, cfg
) {
1664 if (block
->start()->opcode
== BRW_OPCODE_DO
)
1665 multiplier
*= 10; /* assume that loops execute ~10 times */
1667 count
+= block
->cycle_count
* multiplier
;
1669 if (block
->end()->opcode
== BRW_OPCODE_WHILE
)
1677 instruction_scheduler::run(cfg_t
*cfg
)
1679 if (debug
&& !post_reg_alloc
) {
1680 fprintf(stderr
, "\nInstructions before scheduling (reg_alloc %d)\n",
1682 bs
->dump_instructions();
1685 if (!post_reg_alloc
)
1686 setup_liveness(cfg
);
1688 foreach_block(block
, cfg
) {
1689 if (reads_remaining
) {
1690 memset(reads_remaining
, 0,
1691 grf_count
* sizeof(*reads_remaining
));
1692 memset(hw_reads_remaining
, 0,
1693 hw_reg_count
* sizeof(*hw_reads_remaining
));
1694 memset(written
, 0, grf_count
* sizeof(*written
));
1696 foreach_inst_in_block(fs_inst
, inst
, block
)
1697 count_reads_remaining(inst
);
1700 add_insts_from_block(block
);
1707 schedule_instructions(block
);
1710 if (debug
&& !post_reg_alloc
) {
1711 fprintf(stderr
, "\nInstructions after scheduling (reg_alloc %d)\n",
1713 bs
->dump_instructions();
1716 cfg
->cycle_count
= get_cycle_count(cfg
);
1720 fs_visitor::schedule_instructions(instruction_scheduler_mode mode
)
1722 if (mode
!= SCHEDULE_POST
)
1723 calculate_live_intervals();
1726 if (mode
== SCHEDULE_POST
)
1727 grf_count
= grf_used
;
1729 grf_count
= alloc
.count
;
1731 fs_instruction_scheduler
sched(this, grf_count
, first_non_payload_grf
,
1732 cfg
->num_blocks
, mode
);
1735 invalidate_live_intervals();
1739 vec4_visitor::opt_schedule_instructions()
1741 vec4_instruction_scheduler
sched(this, prog_data
->total_grf
);
1744 invalidate_live_intervals();