2 * Copyright © 2010 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Eric Anholt <eric@anholt.net>
29 #include "brw_fs_live_variables.h"
32 #include "brw_shader.h"
36 /** @file brw_fs_schedule_instructions.cpp
38 * List scheduling of FS instructions.
40 * The basic model of the list scheduler is to take a basic block,
41 * compute a DAG of the dependencies (RAW ordering with latency, WAW
42 * ordering with latency, WAR ordering), and make a list of the DAG heads.
43 * Heuristically pick a DAG head, then put all the children that are
44 * now DAG heads into the list of things to schedule.
46 * The heuristic is the important part. We're trying to be cheap,
47 * since actually computing the optimal scheduling is NP complete.
48 * What we do is track a "current clock". When we schedule a node, we
49 * update the earliest-unblocked clock time of its children, and
50 * increment the clock. Then, when trying to schedule, we just pick
51 * the earliest-unblocked instruction to schedule.
53 * Note that often there will be many things which could execute
54 * immediately, and there are a range of heuristic options to choose
55 * from in picking among those.
58 static bool debug
= false;
60 class instruction_scheduler
;
62 class schedule_node
: public exec_node
65 schedule_node(backend_instruction
*inst
, instruction_scheduler
*sched
);
66 void set_latency_gen4();
67 void set_latency_gen7(bool is_haswell
);
69 backend_instruction
*inst
;
70 schedule_node
**children
;
79 * Which iteration of pushing groups of children onto the candidates list
80 * this node was a part of.
82 unsigned cand_generation
;
85 * This is the sum of the instruction's latency plus the maximum delay of
86 * its children, or just the issue_time if it's a leaf node.
91 * Preferred exit node among the (direct or indirect) successors of this
92 * node. Among the scheduler nodes blocked by this node, this will be the
93 * one that may cause earliest program termination, or NULL if none of the
94 * successors is an exit node.
100 * Lower bound of the scheduling time after which one of the instructions
101 * blocked by this node may lead to program termination.
103 * exit_unblocked_time() determines a strict partial ordering relation '«' on
104 * the set of scheduler nodes as follows:
106 * n « m <-> exit_unblocked_time(n) < exit_unblocked_time(m)
108 * which can be used to heuristically order nodes according to how early they
109 * can unblock an exit node and lead to program termination.
112 exit_unblocked_time(const schedule_node
*n
)
114 return n
->exit
? n
->exit
->unblocked_time
: INT_MAX
;
118 schedule_node::set_latency_gen4()
121 int math_latency
= 22;
123 switch (inst
->opcode
) {
124 case SHADER_OPCODE_RCP
:
125 this->latency
= 1 * chans
* math_latency
;
127 case SHADER_OPCODE_RSQ
:
128 this->latency
= 2 * chans
* math_latency
;
130 case SHADER_OPCODE_INT_QUOTIENT
:
131 case SHADER_OPCODE_SQRT
:
132 case SHADER_OPCODE_LOG2
:
133 /* full precision log. partial is 2. */
134 this->latency
= 3 * chans
* math_latency
;
136 case SHADER_OPCODE_INT_REMAINDER
:
137 case SHADER_OPCODE_EXP2
:
138 /* full precision. partial is 3, same throughput. */
139 this->latency
= 4 * chans
* math_latency
;
141 case SHADER_OPCODE_POW
:
142 this->latency
= 8 * chans
* math_latency
;
144 case SHADER_OPCODE_SIN
:
145 case SHADER_OPCODE_COS
:
146 /* minimum latency, max is 12 rounds. */
147 this->latency
= 5 * chans
* math_latency
;
156 schedule_node::set_latency_gen7(bool is_haswell
)
158 switch (inst
->opcode
) {
161 * (since the last two src operands are in different register banks):
162 * mad(8) g4<1>F g2.2<4,4,1>F.x g2<4,4,1>F.x g3.1<4,4,1>F.x { align16 WE_normal 1Q };
164 * 3 cycles on IVB, 4 on HSW
165 * (since the last two src operands are in the same register bank):
166 * mad(8) g4<1>F g2.2<4,4,1>F.x g2<4,4,1>F.x g2.1<4,4,1>F.x { align16 WE_normal 1Q };
168 * 18 cycles on IVB, 16 on HSW
169 * (since the last two src operands are in different register banks):
170 * mad(8) g4<1>F g2.2<4,4,1>F.x g2<4,4,1>F.x g3.1<4,4,1>F.x { align16 WE_normal 1Q };
171 * mov(8) null g4<4,5,1>F { align16 WE_normal 1Q };
173 * 20 cycles on IVB, 18 on HSW
174 * (since the last two src operands are in the same register bank):
175 * mad(8) g4<1>F g2.2<4,4,1>F.x g2<4,4,1>F.x g2.1<4,4,1>F.x { align16 WE_normal 1Q };
176 * mov(8) null g4<4,4,1>F { align16 WE_normal 1Q };
179 /* Our register allocator doesn't know about register banks, so use the
182 latency
= is_haswell
? 16 : 18;
187 * (since the last two src operands are in different register banks):
188 * lrp(8) g4<1>F g2.2<4,4,1>F.x g2<4,4,1>F.x g3.1<4,4,1>F.x { align16 WE_normal 1Q };
190 * 3 cycles on IVB, 4 on HSW
191 * (since the last two src operands are in the same register bank):
192 * lrp(8) g4<1>F g2.2<4,4,1>F.x g2<4,4,1>F.x g2.1<4,4,1>F.x { align16 WE_normal 1Q };
194 * 16 cycles on IVB, 14 on HSW
195 * (since the last two src operands are in different register banks):
196 * lrp(8) g4<1>F g2.2<4,4,1>F.x g2<4,4,1>F.x g3.1<4,4,1>F.x { align16 WE_normal 1Q };
197 * mov(8) null g4<4,4,1>F { align16 WE_normal 1Q };
200 * (since the last two src operands are in the same register bank):
201 * lrp(8) g4<1>F g2.2<4,4,1>F.x g2<4,4,1>F.x g2.1<4,4,1>F.x { align16 WE_normal 1Q };
202 * mov(8) null g4<4,4,1>F { align16 WE_normal 1Q };
205 /* Our register allocator doesn't know about register banks, so use the
211 case SHADER_OPCODE_RCP
:
212 case SHADER_OPCODE_RSQ
:
213 case SHADER_OPCODE_SQRT
:
214 case SHADER_OPCODE_LOG2
:
215 case SHADER_OPCODE_EXP2
:
216 case SHADER_OPCODE_SIN
:
217 case SHADER_OPCODE_COS
:
219 * math inv(8) g4<1>F g2<0,1,0>F null { align1 WE_normal 1Q };
222 * math inv(8) g4<1>F g2<0,1,0>F null { align1 WE_normal 1Q };
223 * mov(8) null g4<8,8,1>F { align1 WE_normal 1Q };
225 * Same for exp2, log2, rsq, sqrt, sin, cos.
227 latency
= is_haswell
? 14 : 16;
230 case SHADER_OPCODE_POW
:
232 * math pow(8) g4<1>F g2<0,1,0>F g2.1<0,1,0>F { align1 WE_normal 1Q };
235 * math pow(8) g4<1>F g2<0,1,0>F g2.1<0,1,0>F { align1 WE_normal 1Q };
236 * mov(8) null g4<8,8,1>F { align1 WE_normal 1Q };
238 latency
= is_haswell
? 22 : 24;
241 case SHADER_OPCODE_TEX
:
242 case SHADER_OPCODE_TXD
:
243 case SHADER_OPCODE_TXF
:
244 case SHADER_OPCODE_TXF_LZ
:
245 case SHADER_OPCODE_TXL
:
246 case SHADER_OPCODE_TXL_LZ
:
248 * mov(8) g115<1>F 0F { align1 WE_normal 1Q };
249 * mov(8) g114<1>F 0F { align1 WE_normal 1Q };
250 * send(8) g4<1>UW g114<8,8,1>F
251 * sampler (10, 0, 0, 1) mlen 2 rlen 4 { align1 WE_normal 1Q };
253 * 697 +/-49 cycles (min 610, n=26):
254 * mov(8) g115<1>F 0F { align1 WE_normal 1Q };
255 * mov(8) g114<1>F 0F { align1 WE_normal 1Q };
256 * send(8) g4<1>UW g114<8,8,1>F
257 * sampler (10, 0, 0, 1) mlen 2 rlen 4 { align1 WE_normal 1Q };
258 * mov(8) null g4<8,8,1>F { align1 WE_normal 1Q };
260 * So the latency on our first texture load of the batchbuffer takes
261 * ~700 cycles, since the caches are cold at that point.
263 * 840 +/- 92 cycles (min 720, n=25):
264 * mov(8) g115<1>F 0F { align1 WE_normal 1Q };
265 * mov(8) g114<1>F 0F { align1 WE_normal 1Q };
266 * send(8) g4<1>UW g114<8,8,1>F
267 * sampler (10, 0, 0, 1) mlen 2 rlen 4 { align1 WE_normal 1Q };
268 * mov(8) null g4<8,8,1>F { align1 WE_normal 1Q };
269 * send(8) g4<1>UW g114<8,8,1>F
270 * sampler (10, 0, 0, 1) mlen 2 rlen 4 { align1 WE_normal 1Q };
271 * mov(8) null g4<8,8,1>F { align1 WE_normal 1Q };
273 * On the second load, it takes just an extra ~140 cycles, and after
274 * accounting for the 14 cycles of the MOV's latency, that makes ~130.
276 * 683 +/- 49 cycles (min = 602, n=47):
277 * mov(8) g115<1>F 0F { align1 WE_normal 1Q };
278 * mov(8) g114<1>F 0F { align1 WE_normal 1Q };
279 * send(8) g4<1>UW g114<8,8,1>F
280 * sampler (10, 0, 0, 1) mlen 2 rlen 4 { align1 WE_normal 1Q };
281 * send(8) g50<1>UW g114<8,8,1>F
282 * sampler (10, 0, 0, 1) mlen 2 rlen 4 { align1 WE_normal 1Q };
283 * mov(8) null g4<8,8,1>F { align1 WE_normal 1Q };
285 * The unit appears to be pipelined, since this matches up with the
286 * cache-cold case, despite there being two loads here. If you replace
287 * the g4 in the MOV to null with g50, it's still 693 +/- 52 (n=39).
289 * So, take some number between the cache-hot 140 cycles and the
290 * cache-cold 700 cycles. No particular tuning was done on this.
292 * I haven't done significant testing of the non-TEX opcodes. TXL at
293 * least looked about the same as TEX.
298 case SHADER_OPCODE_TXS
:
299 /* Testing textureSize(sampler2D, 0), one load was 420 +/- 41
301 * mov(8) g114<1>UD 0D { align1 WE_normal 1Q };
302 * send(8) g6<1>UW g114<8,8,1>F
303 * sampler (10, 0, 10, 1) mlen 1 rlen 4 { align1 WE_normal 1Q };
304 * mov(16) g6<1>F g6<8,8,1>D { align1 WE_normal 1Q };
307 * Two loads was 535 +/- 30 cycles (n=19):
308 * mov(16) g114<1>UD 0D { align1 WE_normal 1H };
309 * send(16) g6<1>UW g114<8,8,1>F
310 * sampler (10, 0, 10, 2) mlen 2 rlen 8 { align1 WE_normal 1H };
311 * mov(16) g114<1>UD 0D { align1 WE_normal 1H };
312 * mov(16) g6<1>F g6<8,8,1>D { align1 WE_normal 1H };
313 * send(16) g8<1>UW g114<8,8,1>F
314 * sampler (10, 0, 10, 2) mlen 2 rlen 8 { align1 WE_normal 1H };
315 * mov(16) g8<1>F g8<8,8,1>D { align1 WE_normal 1H };
316 * add(16) g6<1>F g6<8,8,1>F g8<8,8,1>F { align1 WE_normal 1H };
318 * Since the only caches that should matter are just the
319 * instruction/state cache containing the surface state, assume that we
320 * always have hot caches.
325 case FS_OPCODE_VARYING_PULL_CONSTANT_LOAD_GEN4
:
326 case FS_OPCODE_VARYING_PULL_CONSTANT_LOAD_GEN7
:
327 case FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD
:
328 case FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD_GEN7
:
329 case VS_OPCODE_PULL_CONSTANT_LOAD
:
330 /* testing using varying-index pull constants:
333 * mov(8) g4<1>D g2.1<0,1,0>F { align1 WE_normal 1Q };
334 * send(8) g4<1>F g4<8,8,1>D
335 * data (9, 2, 3) mlen 1 rlen 1 { align1 WE_normal 1Q };
338 * mov(8) g4<1>D g2.1<0,1,0>F { align1 WE_normal 1Q };
339 * send(8) g4<1>F g4<8,8,1>D
340 * data (9, 2, 3) mlen 1 rlen 1 { align1 WE_normal 1Q };
341 * mov(8) null g4<8,8,1>F { align1 WE_normal 1Q };
344 * mov(8) g4<1>D g2.1<0,1,0>F { align1 WE_normal 1Q };
345 * send(8) g4<1>F g4<8,8,1>D
346 * data (9, 2, 3) mlen 1 rlen 1 { align1 WE_normal 1Q };
347 * mov(8) null g4<8,8,1>F { align1 WE_normal 1Q };
348 * send(8) g4<1>F g4<8,8,1>D
349 * data (9, 2, 3) mlen 1 rlen 1 { align1 WE_normal 1Q };
350 * mov(8) null g4<8,8,1>F { align1 WE_normal 1Q };
352 * So, if it's cache-hot, it's about 140. If it's cache cold, it's
353 * about 460. We expect to mostly be cache hot, so pick something more
359 case SHADER_OPCODE_GEN7_SCRATCH_READ
:
360 /* Testing a load from offset 0, that had been previously written:
362 * send(8) g114<1>UW g0<8,8,1>F data (0, 0, 0) mlen 1 rlen 1 { align1 WE_normal 1Q };
363 * mov(8) null g114<8,8,1>F { align1 WE_normal 1Q };
365 * The cycles spent seemed to be grouped around 40-50 (as low as 38),
366 * then around 140. Presumably this is cache hit vs miss.
371 case SHADER_OPCODE_UNTYPED_ATOMIC
:
372 case SHADER_OPCODE_UNTYPED_ATOMIC_FLOAT
:
373 case SHADER_OPCODE_TYPED_ATOMIC
:
375 * mov(8) g112<1>ud 0x00000000ud { align1 WE_all 1Q };
376 * mov(1) g112.7<1>ud g1.7<0,1,0>ud { align1 WE_all };
377 * mov(8) g113<1>ud 0x00000000ud { align1 WE_normal 1Q };
378 * send(8) g4<1>ud g112<8,8,1>ud
379 * data (38, 5, 6) mlen 2 rlen 1 { align1 WE_normal 1Q };
381 * Running it 100 times as fragment shader on a 128x128 quad
382 * gives an average latency of 13867 cycles per atomic op,
383 * standard deviation 3%. Note that this is a rather
384 * pessimistic estimate, the actual latency in cases with few
385 * collisions between threads and favorable pipelining has been
386 * seen to be reduced by a factor of 100.
391 case SHADER_OPCODE_UNTYPED_SURFACE_READ
:
392 case SHADER_OPCODE_UNTYPED_SURFACE_WRITE
:
393 case SHADER_OPCODE_TYPED_SURFACE_READ
:
394 case SHADER_OPCODE_TYPED_SURFACE_WRITE
:
396 * mov(8) g112<1>UD 0x00000000UD { align1 WE_all 1Q };
397 * mov(1) g112.7<1>UD g1.7<0,1,0>UD { align1 WE_all };
398 * mov(8) g113<1>UD 0x00000000UD { align1 WE_normal 1Q };
399 * send(8) g4<1>UD g112<8,8,1>UD
400 * data (38, 6, 5) mlen 2 rlen 1 { align1 WE_normal 1Q };
402 * . [repeats 8 times]
404 * mov(8) g112<1>UD 0x00000000UD { align1 WE_all 1Q };
405 * mov(1) g112.7<1>UD g1.7<0,1,0>UD { align1 WE_all };
406 * mov(8) g113<1>UD 0x00000000UD { align1 WE_normal 1Q };
407 * send(8) g4<1>UD g112<8,8,1>UD
408 * data (38, 6, 5) mlen 2 rlen 1 { align1 WE_normal 1Q };
410 * Running it 100 times as fragment shader on a 128x128 quad
411 * gives an average latency of 583 cycles per surface read,
412 * standard deviation 0.9%.
414 latency
= is_haswell
? 300 : 600;
417 case SHADER_OPCODE_SEND
:
418 switch (inst
->sfid
) {
419 case BRW_SFID_SAMPLER
: {
420 unsigned msg_type
= (inst
->desc
>> 12) & 0x1f;
422 case GEN5_SAMPLER_MESSAGE_SAMPLE_RESINFO
:
423 case GEN6_SAMPLER_MESSAGE_SAMPLE_SAMPLEINFO
:
424 /* See also SHADER_OPCODE_TXS */
429 /* See also SHADER_OPCODE_TEX */
436 case GEN6_SFID_DATAPORT_RENDER_CACHE
:
437 switch ((inst
->desc
>> 14) & 0x1f) {
438 case GEN7_DATAPORT_RC_TYPED_SURFACE_WRITE
:
439 case GEN7_DATAPORT_RC_TYPED_SURFACE_READ
:
440 /* See also SHADER_OPCODE_TYPED_SURFACE_READ */
445 case GEN7_DATAPORT_RC_TYPED_ATOMIC_OP
:
446 /* See also SHADER_OPCODE_TYPED_ATOMIC */
452 unreachable("Unknown render cache message");
456 case GEN7_SFID_DATAPORT_DATA_CACHE
:
457 switch ((inst
->desc
>> 14) & 0x1f) {
458 case HSW_DATAPORT_DC_PORT0_BYTE_SCATTERED_READ
:
459 case HSW_DATAPORT_DC_PORT0_BYTE_SCATTERED_WRITE
:
460 /* We have no data for this but assume it's roughly the same as
461 * untyped surface read/write.
466 case GEN7_DATAPORT_DC_UNTYPED_SURFACE_READ
:
467 case GEN7_DATAPORT_DC_UNTYPED_SURFACE_WRITE
:
468 /* See also SHADER_OPCODE_UNTYPED_SURFACE_READ */
473 case GEN7_DATAPORT_DC_UNTYPED_ATOMIC_OP
:
474 /* See also SHADER_OPCODE_UNTYPED_ATOMIC */
480 unreachable("Unknown data cache message");
484 case HSW_SFID_DATAPORT_DATA_CACHE_1
:
485 switch ((inst
->desc
>> 14) & 0x1f) {
486 case HSW_DATAPORT_DC_PORT1_UNTYPED_SURFACE_READ
:
487 case HSW_DATAPORT_DC_PORT1_UNTYPED_SURFACE_WRITE
:
488 case HSW_DATAPORT_DC_PORT1_TYPED_SURFACE_READ
:
489 case HSW_DATAPORT_DC_PORT1_TYPED_SURFACE_WRITE
:
490 /* See also SHADER_OPCODE_UNTYPED_SURFACE_READ */
494 case HSW_DATAPORT_DC_PORT1_UNTYPED_ATOMIC_OP
:
495 case HSW_DATAPORT_DC_PORT1_UNTYPED_ATOMIC_OP_SIMD4X2
:
496 case HSW_DATAPORT_DC_PORT1_TYPED_ATOMIC_OP_SIMD4X2
:
497 case HSW_DATAPORT_DC_PORT1_TYPED_ATOMIC_OP
:
498 case GEN9_DATAPORT_DC_PORT1_UNTYPED_ATOMIC_FLOAT_OP
:
499 /* See also SHADER_OPCODE_UNTYPED_ATOMIC */
504 unreachable("Unknown data cache message");
509 unreachable("Unknown SFID");
515 * mul(8) g4<1>F g2<0,1,0>F 0.5F { align1 WE_normal 1Q };
518 * mul(8) g4<1>F g2<0,1,0>F 0.5F { align1 WE_normal 1Q };
519 * mov(8) null g4<8,8,1>F { align1 WE_normal 1Q };
526 class instruction_scheduler
{
528 instruction_scheduler(backend_shader
*s
, int grf_count
,
529 unsigned hw_reg_count
, int block_count
,
530 instruction_scheduler_mode mode
)
533 this->mem_ctx
= ralloc_context(NULL
);
534 this->grf_count
= grf_count
;
535 this->hw_reg_count
= hw_reg_count
;
536 this->instructions
.make_empty();
537 this->instructions_to_schedule
= 0;
538 this->post_reg_alloc
= (mode
== SCHEDULE_POST
);
540 if (!post_reg_alloc
) {
541 this->reg_pressure_in
= rzalloc_array(mem_ctx
, int, block_count
);
543 this->livein
= ralloc_array(mem_ctx
, BITSET_WORD
*, block_count
);
544 for (int i
= 0; i
< block_count
; i
++)
545 this->livein
[i
] = rzalloc_array(mem_ctx
, BITSET_WORD
,
546 BITSET_WORDS(grf_count
));
548 this->liveout
= ralloc_array(mem_ctx
, BITSET_WORD
*, block_count
);
549 for (int i
= 0; i
< block_count
; i
++)
550 this->liveout
[i
] = rzalloc_array(mem_ctx
, BITSET_WORD
,
551 BITSET_WORDS(grf_count
));
553 this->hw_liveout
= ralloc_array(mem_ctx
, BITSET_WORD
*, block_count
);
554 for (int i
= 0; i
< block_count
; i
++)
555 this->hw_liveout
[i
] = rzalloc_array(mem_ctx
, BITSET_WORD
,
556 BITSET_WORDS(hw_reg_count
));
558 this->written
= rzalloc_array(mem_ctx
, bool, grf_count
);
560 this->reads_remaining
= rzalloc_array(mem_ctx
, int, grf_count
);
562 this->hw_reads_remaining
= rzalloc_array(mem_ctx
, int, hw_reg_count
);
564 this->reg_pressure_in
= NULL
;
566 this->liveout
= NULL
;
567 this->hw_liveout
= NULL
;
568 this->written
= NULL
;
569 this->reads_remaining
= NULL
;
570 this->hw_reads_remaining
= NULL
;
574 ~instruction_scheduler()
576 ralloc_free(this->mem_ctx
);
578 void add_barrier_deps(schedule_node
*n
);
579 void add_dep(schedule_node
*before
, schedule_node
*after
, int latency
);
580 void add_dep(schedule_node
*before
, schedule_node
*after
);
582 void run(cfg_t
*cfg
);
583 void add_insts_from_block(bblock_t
*block
);
584 void compute_delays();
585 void compute_exits();
586 virtual void calculate_deps() = 0;
587 virtual schedule_node
*choose_instruction_to_schedule() = 0;
590 * Returns how many cycles it takes the instruction to issue.
592 * Instructions in gen hardware are handled one simd4 vector at a time,
593 * with 1 cycle per vector dispatched. Thus SIMD8 pixel shaders take 2
594 * cycles to dispatch and SIMD16 (compressed) instructions take 4.
596 virtual int issue_time(backend_instruction
*inst
) = 0;
598 virtual void count_reads_remaining(backend_instruction
*inst
) = 0;
599 virtual void setup_liveness(cfg_t
*cfg
) = 0;
600 virtual void update_register_pressure(backend_instruction
*inst
) = 0;
601 virtual int get_register_pressure_benefit(backend_instruction
*inst
) = 0;
603 void schedule_instructions(bblock_t
*block
);
608 int instructions_to_schedule
;
610 unsigned hw_reg_count
;
613 exec_list instructions
;
616 instruction_scheduler_mode mode
;
619 * The register pressure at the beginning of each basic block.
622 int *reg_pressure_in
;
625 * The virtual GRF's whose range overlaps the beginning of each basic block.
628 BITSET_WORD
**livein
;
631 * The virtual GRF's whose range overlaps the end of each basic block.
634 BITSET_WORD
**liveout
;
637 * The hardware GRF's whose range overlaps the end of each basic block.
640 BITSET_WORD
**hw_liveout
;
643 * Whether we've scheduled a write for this virtual GRF yet.
649 * How many reads we haven't scheduled for this virtual GRF yet.
652 int *reads_remaining
;
655 * How many reads we haven't scheduled for this hardware GRF yet.
658 int *hw_reads_remaining
;
661 class fs_instruction_scheduler
: public instruction_scheduler
664 fs_instruction_scheduler(fs_visitor
*v
, int grf_count
, int hw_reg_count
,
666 instruction_scheduler_mode mode
);
667 void calculate_deps();
668 bool is_compressed(fs_inst
*inst
);
669 schedule_node
*choose_instruction_to_schedule();
670 int issue_time(backend_instruction
*inst
);
673 void count_reads_remaining(backend_instruction
*inst
);
674 void setup_liveness(cfg_t
*cfg
);
675 void update_register_pressure(backend_instruction
*inst
);
676 int get_register_pressure_benefit(backend_instruction
*inst
);
679 fs_instruction_scheduler::fs_instruction_scheduler(fs_visitor
*v
,
680 int grf_count
, int hw_reg_count
,
682 instruction_scheduler_mode mode
)
683 : instruction_scheduler(v
, grf_count
, hw_reg_count
, block_count
, mode
),
689 is_src_duplicate(fs_inst
*inst
, int src
)
691 for (int i
= 0; i
< src
; i
++)
692 if (inst
->src
[i
].equals(inst
->src
[src
]))
699 fs_instruction_scheduler::count_reads_remaining(backend_instruction
*be
)
701 fs_inst
*inst
= (fs_inst
*)be
;
703 if (!reads_remaining
)
706 for (int i
= 0; i
< inst
->sources
; i
++) {
707 if (is_src_duplicate(inst
, i
))
710 if (inst
->src
[i
].file
== VGRF
) {
711 reads_remaining
[inst
->src
[i
].nr
]++;
712 } else if (inst
->src
[i
].file
== FIXED_GRF
) {
713 if (inst
->src
[i
].nr
>= hw_reg_count
)
716 for (unsigned j
= 0; j
< regs_read(inst
, i
); j
++)
717 hw_reads_remaining
[inst
->src
[i
].nr
+ j
]++;
723 fs_instruction_scheduler::setup_liveness(cfg_t
*cfg
)
725 /* First, compute liveness on a per-GRF level using the in/out sets from
726 * liveness calculation.
728 for (int block
= 0; block
< cfg
->num_blocks
; block
++) {
729 for (int i
= 0; i
< v
->live_intervals
->num_vars
; i
++) {
730 if (BITSET_TEST(v
->live_intervals
->block_data
[block
].livein
, i
)) {
731 int vgrf
= v
->live_intervals
->vgrf_from_var
[i
];
732 if (!BITSET_TEST(livein
[block
], vgrf
)) {
733 reg_pressure_in
[block
] += v
->alloc
.sizes
[vgrf
];
734 BITSET_SET(livein
[block
], vgrf
);
738 if (BITSET_TEST(v
->live_intervals
->block_data
[block
].liveout
, i
))
739 BITSET_SET(liveout
[block
], v
->live_intervals
->vgrf_from_var
[i
]);
743 /* Now, extend the live in/live out sets for when a range crosses a block
744 * boundary, which matches what our register allocator/interference code
745 * does to account for force_writemask_all and incompatible exec_mask's.
747 for (int block
= 0; block
< cfg
->num_blocks
- 1; block
++) {
748 for (int i
= 0; i
< grf_count
; i
++) {
749 if (v
->virtual_grf_start
[i
] <= cfg
->blocks
[block
]->end_ip
&&
750 v
->virtual_grf_end
[i
] >= cfg
->blocks
[block
+ 1]->start_ip
) {
751 if (!BITSET_TEST(livein
[block
+ 1], i
)) {
752 reg_pressure_in
[block
+ 1] += v
->alloc
.sizes
[i
];
753 BITSET_SET(livein
[block
+ 1], i
);
756 BITSET_SET(liveout
[block
], i
);
761 int payload_last_use_ip
[hw_reg_count
];
762 v
->calculate_payload_ranges(hw_reg_count
, payload_last_use_ip
);
764 for (unsigned i
= 0; i
< hw_reg_count
; i
++) {
765 if (payload_last_use_ip
[i
] == -1)
768 for (int block
= 0; block
< cfg
->num_blocks
; block
++) {
769 if (cfg
->blocks
[block
]->start_ip
<= payload_last_use_ip
[i
])
770 reg_pressure_in
[block
]++;
772 if (cfg
->blocks
[block
]->end_ip
<= payload_last_use_ip
[i
])
773 BITSET_SET(hw_liveout
[block
], i
);
779 fs_instruction_scheduler::update_register_pressure(backend_instruction
*be
)
781 fs_inst
*inst
= (fs_inst
*)be
;
783 if (!reads_remaining
)
786 if (inst
->dst
.file
== VGRF
) {
787 written
[inst
->dst
.nr
] = true;
790 for (int i
= 0; i
< inst
->sources
; i
++) {
791 if (is_src_duplicate(inst
, i
))
794 if (inst
->src
[i
].file
== VGRF
) {
795 reads_remaining
[inst
->src
[i
].nr
]--;
796 } else if (inst
->src
[i
].file
== FIXED_GRF
&&
797 inst
->src
[i
].nr
< hw_reg_count
) {
798 for (unsigned off
= 0; off
< regs_read(inst
, i
); off
++)
799 hw_reads_remaining
[inst
->src
[i
].nr
+ off
]--;
805 fs_instruction_scheduler::get_register_pressure_benefit(backend_instruction
*be
)
807 fs_inst
*inst
= (fs_inst
*)be
;
810 if (inst
->dst
.file
== VGRF
) {
811 if (!BITSET_TEST(livein
[block_idx
], inst
->dst
.nr
) &&
812 !written
[inst
->dst
.nr
])
813 benefit
-= v
->alloc
.sizes
[inst
->dst
.nr
];
816 for (int i
= 0; i
< inst
->sources
; i
++) {
817 if (is_src_duplicate(inst
, i
))
820 if (inst
->src
[i
].file
== VGRF
&&
821 !BITSET_TEST(liveout
[block_idx
], inst
->src
[i
].nr
) &&
822 reads_remaining
[inst
->src
[i
].nr
] == 1)
823 benefit
+= v
->alloc
.sizes
[inst
->src
[i
].nr
];
825 if (inst
->src
[i
].file
== FIXED_GRF
&&
826 inst
->src
[i
].nr
< hw_reg_count
) {
827 for (unsigned off
= 0; off
< regs_read(inst
, i
); off
++) {
828 int reg
= inst
->src
[i
].nr
+ off
;
829 if (!BITSET_TEST(hw_liveout
[block_idx
], reg
) &&
830 hw_reads_remaining
[reg
] == 1) {
840 class vec4_instruction_scheduler
: public instruction_scheduler
843 vec4_instruction_scheduler(vec4_visitor
*v
, int grf_count
);
844 void calculate_deps();
845 schedule_node
*choose_instruction_to_schedule();
846 int issue_time(backend_instruction
*inst
);
849 void count_reads_remaining(backend_instruction
*inst
);
850 void setup_liveness(cfg_t
*cfg
);
851 void update_register_pressure(backend_instruction
*inst
);
852 int get_register_pressure_benefit(backend_instruction
*inst
);
855 vec4_instruction_scheduler::vec4_instruction_scheduler(vec4_visitor
*v
,
857 : instruction_scheduler(v
, grf_count
, 0, 0, SCHEDULE_POST
),
863 vec4_instruction_scheduler::count_reads_remaining(backend_instruction
*)
868 vec4_instruction_scheduler::setup_liveness(cfg_t
*)
873 vec4_instruction_scheduler::update_register_pressure(backend_instruction
*)
878 vec4_instruction_scheduler::get_register_pressure_benefit(backend_instruction
*)
883 schedule_node::schedule_node(backend_instruction
*inst
,
884 instruction_scheduler
*sched
)
886 const struct gen_device_info
*devinfo
= sched
->bs
->devinfo
;
889 this->child_array_size
= 0;
890 this->children
= NULL
;
891 this->child_latency
= NULL
;
892 this->child_count
= 0;
893 this->parent_count
= 0;
894 this->unblocked_time
= 0;
895 this->cand_generation
= 0;
899 /* We can't measure Gen6 timings directly but expect them to be much
900 * closer to Gen7 than Gen4.
902 if (!sched
->post_reg_alloc
)
904 else if (devinfo
->gen
>= 6)
905 set_latency_gen7(devinfo
->is_haswell
);
911 instruction_scheduler::add_insts_from_block(bblock_t
*block
)
913 foreach_inst_in_block(backend_instruction
, inst
, block
) {
914 schedule_node
*n
= new(mem_ctx
) schedule_node(inst
, this);
916 instructions
.push_tail(n
);
919 this->instructions_to_schedule
= block
->end_ip
- block
->start_ip
+ 1;
922 /** Computation of the delay member of each node. */
924 instruction_scheduler::compute_delays()
926 foreach_in_list_reverse(schedule_node
, n
, &instructions
) {
927 if (!n
->child_count
) {
928 n
->delay
= issue_time(n
->inst
);
930 for (int i
= 0; i
< n
->child_count
; i
++) {
931 assert(n
->children
[i
]->delay
);
932 n
->delay
= MAX2(n
->delay
, n
->latency
+ n
->children
[i
]->delay
);
939 instruction_scheduler::compute_exits()
941 /* Calculate a lower bound of the scheduling time of each node in the
942 * graph. This is analogous to the node's critical path but calculated
943 * from the top instead of from the bottom of the block.
945 foreach_in_list(schedule_node
, n
, &instructions
) {
946 for (int i
= 0; i
< n
->child_count
; i
++) {
947 n
->children
[i
]->unblocked_time
=
948 MAX2(n
->children
[i
]->unblocked_time
,
949 n
->unblocked_time
+ issue_time(n
->inst
) + n
->child_latency
[i
]);
953 /* Calculate the exit of each node by induction based on the exit nodes of
954 * its children. The preferred exit of a node is the one among the exit
955 * nodes of its children which can be unblocked first according to the
956 * optimistic unblocked time estimate calculated above.
958 foreach_in_list_reverse(schedule_node
, n
, &instructions
) {
959 n
->exit
= (n
->inst
->opcode
== FS_OPCODE_DISCARD_JUMP
? n
: NULL
);
961 for (int i
= 0; i
< n
->child_count
; i
++) {
962 if (exit_unblocked_time(n
->children
[i
]) < exit_unblocked_time(n
))
963 n
->exit
= n
->children
[i
]->exit
;
969 * Add a dependency between two instruction nodes.
971 * The @after node will be scheduled after @before. We will try to
972 * schedule it @latency cycles after @before, but no guarantees there.
975 instruction_scheduler::add_dep(schedule_node
*before
, schedule_node
*after
,
978 if (!before
|| !after
)
981 assert(before
!= after
);
983 for (int i
= 0; i
< before
->child_count
; i
++) {
984 if (before
->children
[i
] == after
) {
985 before
->child_latency
[i
] = MAX2(before
->child_latency
[i
], latency
);
990 if (before
->child_array_size
<= before
->child_count
) {
991 if (before
->child_array_size
< 16)
992 before
->child_array_size
= 16;
994 before
->child_array_size
*= 2;
996 before
->children
= reralloc(mem_ctx
, before
->children
,
998 before
->child_array_size
);
999 before
->child_latency
= reralloc(mem_ctx
, before
->child_latency
,
1000 int, before
->child_array_size
);
1003 before
->children
[before
->child_count
] = after
;
1004 before
->child_latency
[before
->child_count
] = latency
;
1005 before
->child_count
++;
1006 after
->parent_count
++;
1010 instruction_scheduler::add_dep(schedule_node
*before
, schedule_node
*after
)
1015 add_dep(before
, after
, before
->latency
);
1019 is_scheduling_barrier(const backend_instruction
*inst
)
1021 return inst
->opcode
== FS_OPCODE_PLACEHOLDER_HALT
||
1022 inst
->is_control_flow() ||
1023 inst
->has_side_effects();
1027 * Sometimes we really want this node to execute after everything that
1028 * was before it and before everything that followed it. This adds
1029 * the deps to do so.
1032 instruction_scheduler::add_barrier_deps(schedule_node
*n
)
1034 schedule_node
*prev
= (schedule_node
*)n
->prev
;
1035 schedule_node
*next
= (schedule_node
*)n
->next
;
1038 while (!prev
->is_head_sentinel()) {
1039 add_dep(prev
, n
, 0);
1040 if (is_scheduling_barrier(prev
->inst
))
1042 prev
= (schedule_node
*)prev
->prev
;
1047 while (!next
->is_tail_sentinel()) {
1048 add_dep(n
, next
, 0);
1049 if (is_scheduling_barrier(next
->inst
))
1051 next
= (schedule_node
*)next
->next
;
1056 /* instruction scheduling needs to be aware of when an MRF write
1057 * actually writes 2 MRFs.
1060 fs_instruction_scheduler::is_compressed(fs_inst
*inst
)
1062 return inst
->exec_size
== 16;
1066 fs_instruction_scheduler::calculate_deps()
1068 /* Pre-register-allocation, this tracks the last write per VGRF offset.
1069 * After register allocation, reg_offsets are gone and we track individual
1072 schedule_node
**last_grf_write
;
1073 schedule_node
*last_mrf_write
[BRW_MAX_MRF(v
->devinfo
->gen
)];
1074 schedule_node
*last_conditional_mod
[8] = {};
1075 schedule_node
*last_accumulator_write
= NULL
;
1076 /* Fixed HW registers are assumed to be separate from the virtual
1077 * GRFs, so they can be tracked separately. We don't really write
1078 * to fixed GRFs much, so don't bother tracking them on a more
1081 schedule_node
*last_fixed_grf_write
= NULL
;
1083 last_grf_write
= (schedule_node
**)calloc(sizeof(schedule_node
*), grf_count
* 16);
1084 memset(last_mrf_write
, 0, sizeof(last_mrf_write
));
1086 /* top-to-bottom dependencies: RAW and WAW. */
1087 foreach_in_list(schedule_node
, n
, &instructions
) {
1088 fs_inst
*inst
= (fs_inst
*)n
->inst
;
1090 if (is_scheduling_barrier(inst
))
1091 add_barrier_deps(n
);
1093 /* read-after-write deps. */
1094 for (int i
= 0; i
< inst
->sources
; i
++) {
1095 if (inst
->src
[i
].file
== VGRF
) {
1096 if (post_reg_alloc
) {
1097 for (unsigned r
= 0; r
< regs_read(inst
, i
); r
++)
1098 add_dep(last_grf_write
[inst
->src
[i
].nr
+ r
], n
);
1100 for (unsigned r
= 0; r
< regs_read(inst
, i
); r
++) {
1101 add_dep(last_grf_write
[inst
->src
[i
].nr
* 16 +
1102 inst
->src
[i
].offset
/ REG_SIZE
+ r
], n
);
1105 } else if (inst
->src
[i
].file
== FIXED_GRF
) {
1106 if (post_reg_alloc
) {
1107 for (unsigned r
= 0; r
< regs_read(inst
, i
); r
++)
1108 add_dep(last_grf_write
[inst
->src
[i
].nr
+ r
], n
);
1110 add_dep(last_fixed_grf_write
, n
);
1112 } else if (inst
->src
[i
].is_accumulator()) {
1113 add_dep(last_accumulator_write
, n
);
1114 } else if (inst
->src
[i
].file
== ARF
) {
1115 add_barrier_deps(n
);
1119 if (inst
->base_mrf
!= -1) {
1120 for (int i
= 0; i
< inst
->mlen
; i
++) {
1121 /* It looks like the MRF regs are released in the send
1122 * instruction once it's sent, not when the result comes
1125 add_dep(last_mrf_write
[inst
->base_mrf
+ i
], n
);
1129 if (const unsigned mask
= inst
->flags_read(v
->devinfo
)) {
1130 assert(mask
< (1 << ARRAY_SIZE(last_conditional_mod
)));
1132 for (unsigned i
= 0; i
< ARRAY_SIZE(last_conditional_mod
); i
++) {
1133 if (mask
& (1 << i
))
1134 add_dep(last_conditional_mod
[i
], n
);
1138 if (inst
->reads_accumulator_implicitly()) {
1139 add_dep(last_accumulator_write
, n
);
1142 /* write-after-write deps. */
1143 if (inst
->dst
.file
== VGRF
) {
1144 if (post_reg_alloc
) {
1145 for (unsigned r
= 0; r
< regs_written(inst
); r
++) {
1146 add_dep(last_grf_write
[inst
->dst
.nr
+ r
], n
);
1147 last_grf_write
[inst
->dst
.nr
+ r
] = n
;
1150 for (unsigned r
= 0; r
< regs_written(inst
); r
++) {
1151 add_dep(last_grf_write
[inst
->dst
.nr
* 16 +
1152 inst
->dst
.offset
/ REG_SIZE
+ r
], n
);
1153 last_grf_write
[inst
->dst
.nr
* 16 +
1154 inst
->dst
.offset
/ REG_SIZE
+ r
] = n
;
1157 } else if (inst
->dst
.file
== MRF
) {
1158 int reg
= inst
->dst
.nr
& ~BRW_MRF_COMPR4
;
1160 add_dep(last_mrf_write
[reg
], n
);
1161 last_mrf_write
[reg
] = n
;
1162 if (is_compressed(inst
)) {
1163 if (inst
->dst
.nr
& BRW_MRF_COMPR4
)
1167 add_dep(last_mrf_write
[reg
], n
);
1168 last_mrf_write
[reg
] = n
;
1170 } else if (inst
->dst
.file
== FIXED_GRF
) {
1171 if (post_reg_alloc
) {
1172 for (unsigned r
= 0; r
< regs_written(inst
); r
++)
1173 last_grf_write
[inst
->dst
.nr
+ r
] = n
;
1175 last_fixed_grf_write
= n
;
1177 } else if (inst
->dst
.is_accumulator()) {
1178 add_dep(last_accumulator_write
, n
);
1179 last_accumulator_write
= n
;
1180 } else if (inst
->dst
.file
== ARF
&& !inst
->dst
.is_null()) {
1181 add_barrier_deps(n
);
1184 if (inst
->mlen
> 0 && inst
->base_mrf
!= -1) {
1185 for (int i
= 0; i
< v
->implied_mrf_writes(inst
); i
++) {
1186 add_dep(last_mrf_write
[inst
->base_mrf
+ i
], n
);
1187 last_mrf_write
[inst
->base_mrf
+ i
] = n
;
1191 if (const unsigned mask
= inst
->flags_written()) {
1192 assert(mask
< (1 << ARRAY_SIZE(last_conditional_mod
)));
1194 for (unsigned i
= 0; i
< ARRAY_SIZE(last_conditional_mod
); i
++) {
1195 if (mask
& (1 << i
)) {
1196 add_dep(last_conditional_mod
[i
], n
, 0);
1197 last_conditional_mod
[i
] = n
;
1202 if (inst
->writes_accumulator_implicitly(v
->devinfo
) &&
1203 !inst
->dst
.is_accumulator()) {
1204 add_dep(last_accumulator_write
, n
);
1205 last_accumulator_write
= n
;
1209 /* bottom-to-top dependencies: WAR */
1210 memset(last_grf_write
, 0, sizeof(schedule_node
*) * grf_count
* 16);
1211 memset(last_mrf_write
, 0, sizeof(last_mrf_write
));
1212 memset(last_conditional_mod
, 0, sizeof(last_conditional_mod
));
1213 last_accumulator_write
= NULL
;
1214 last_fixed_grf_write
= NULL
;
1216 foreach_in_list_reverse_safe(schedule_node
, n
, &instructions
) {
1217 fs_inst
*inst
= (fs_inst
*)n
->inst
;
1219 /* write-after-read deps. */
1220 for (int i
= 0; i
< inst
->sources
; i
++) {
1221 if (inst
->src
[i
].file
== VGRF
) {
1222 if (post_reg_alloc
) {
1223 for (unsigned r
= 0; r
< regs_read(inst
, i
); r
++)
1224 add_dep(n
, last_grf_write
[inst
->src
[i
].nr
+ r
], 0);
1226 for (unsigned r
= 0; r
< regs_read(inst
, i
); r
++) {
1227 add_dep(n
, last_grf_write
[inst
->src
[i
].nr
* 16 +
1228 inst
->src
[i
].offset
/ REG_SIZE
+ r
], 0);
1231 } else if (inst
->src
[i
].file
== FIXED_GRF
) {
1232 if (post_reg_alloc
) {
1233 for (unsigned r
= 0; r
< regs_read(inst
, i
); r
++)
1234 add_dep(n
, last_grf_write
[inst
->src
[i
].nr
+ r
], 0);
1236 add_dep(n
, last_fixed_grf_write
, 0);
1238 } else if (inst
->src
[i
].is_accumulator()) {
1239 add_dep(n
, last_accumulator_write
, 0);
1240 } else if (inst
->src
[i
].file
== ARF
) {
1241 add_barrier_deps(n
);
1245 if (inst
->base_mrf
!= -1) {
1246 for (int i
= 0; i
< inst
->mlen
; i
++) {
1247 /* It looks like the MRF regs are released in the send
1248 * instruction once it's sent, not when the result comes
1251 add_dep(n
, last_mrf_write
[inst
->base_mrf
+ i
], 2);
1255 if (const unsigned mask
= inst
->flags_read(v
->devinfo
)) {
1256 assert(mask
< (1 << ARRAY_SIZE(last_conditional_mod
)));
1258 for (unsigned i
= 0; i
< ARRAY_SIZE(last_conditional_mod
); i
++) {
1259 if (mask
& (1 << i
))
1260 add_dep(n
, last_conditional_mod
[i
]);
1264 if (inst
->reads_accumulator_implicitly()) {
1265 add_dep(n
, last_accumulator_write
);
1268 /* Update the things this instruction wrote, so earlier reads
1269 * can mark this as WAR dependency.
1271 if (inst
->dst
.file
== VGRF
) {
1272 if (post_reg_alloc
) {
1273 for (unsigned r
= 0; r
< regs_written(inst
); r
++)
1274 last_grf_write
[inst
->dst
.nr
+ r
] = n
;
1276 for (unsigned r
= 0; r
< regs_written(inst
); r
++) {
1277 last_grf_write
[inst
->dst
.nr
* 16 +
1278 inst
->dst
.offset
/ REG_SIZE
+ r
] = n
;
1281 } else if (inst
->dst
.file
== MRF
) {
1282 int reg
= inst
->dst
.nr
& ~BRW_MRF_COMPR4
;
1284 last_mrf_write
[reg
] = n
;
1286 if (is_compressed(inst
)) {
1287 if (inst
->dst
.nr
& BRW_MRF_COMPR4
)
1292 last_mrf_write
[reg
] = n
;
1294 } else if (inst
->dst
.file
== FIXED_GRF
) {
1295 if (post_reg_alloc
) {
1296 for (unsigned r
= 0; r
< regs_written(inst
); r
++)
1297 last_grf_write
[inst
->dst
.nr
+ r
] = n
;
1299 last_fixed_grf_write
= n
;
1301 } else if (inst
->dst
.is_accumulator()) {
1302 last_accumulator_write
= n
;
1303 } else if (inst
->dst
.file
== ARF
&& !inst
->dst
.is_null()) {
1304 add_barrier_deps(n
);
1307 if (inst
->mlen
> 0 && inst
->base_mrf
!= -1) {
1308 for (int i
= 0; i
< v
->implied_mrf_writes(inst
); i
++) {
1309 last_mrf_write
[inst
->base_mrf
+ i
] = n
;
1313 if (const unsigned mask
= inst
->flags_written()) {
1314 assert(mask
< (1 << ARRAY_SIZE(last_conditional_mod
)));
1316 for (unsigned i
= 0; i
< ARRAY_SIZE(last_conditional_mod
); i
++) {
1317 if (mask
& (1 << i
))
1318 last_conditional_mod
[i
] = n
;
1322 if (inst
->writes_accumulator_implicitly(v
->devinfo
)) {
1323 last_accumulator_write
= n
;
1327 free(last_grf_write
);
1331 vec4_instruction_scheduler::calculate_deps()
1333 schedule_node
*last_grf_write
[grf_count
];
1334 schedule_node
*last_mrf_write
[BRW_MAX_MRF(v
->devinfo
->gen
)];
1335 schedule_node
*last_conditional_mod
= NULL
;
1336 schedule_node
*last_accumulator_write
= NULL
;
1337 /* Fixed HW registers are assumed to be separate from the virtual
1338 * GRFs, so they can be tracked separately. We don't really write
1339 * to fixed GRFs much, so don't bother tracking them on a more
1342 schedule_node
*last_fixed_grf_write
= NULL
;
1344 memset(last_grf_write
, 0, sizeof(last_grf_write
));
1345 memset(last_mrf_write
, 0, sizeof(last_mrf_write
));
1347 /* top-to-bottom dependencies: RAW and WAW. */
1348 foreach_in_list(schedule_node
, n
, &instructions
) {
1349 vec4_instruction
*inst
= (vec4_instruction
*)n
->inst
;
1351 if (is_scheduling_barrier(inst
))
1352 add_barrier_deps(n
);
1354 /* read-after-write deps. */
1355 for (int i
= 0; i
< 3; i
++) {
1356 if (inst
->src
[i
].file
== VGRF
) {
1357 for (unsigned j
= 0; j
< regs_read(inst
, i
); ++j
)
1358 add_dep(last_grf_write
[inst
->src
[i
].nr
+ j
], n
);
1359 } else if (inst
->src
[i
].file
== FIXED_GRF
) {
1360 add_dep(last_fixed_grf_write
, n
);
1361 } else if (inst
->src
[i
].is_accumulator()) {
1362 assert(last_accumulator_write
);
1363 add_dep(last_accumulator_write
, n
);
1364 } else if (inst
->src
[i
].file
== ARF
) {
1365 add_barrier_deps(n
);
1369 if (inst
->reads_g0_implicitly())
1370 add_dep(last_fixed_grf_write
, n
);
1372 if (!inst
->is_send_from_grf()) {
1373 for (int i
= 0; i
< inst
->mlen
; i
++) {
1374 /* It looks like the MRF regs are released in the send
1375 * instruction once it's sent, not when the result comes
1378 add_dep(last_mrf_write
[inst
->base_mrf
+ i
], n
);
1382 if (inst
->reads_flag()) {
1383 assert(last_conditional_mod
);
1384 add_dep(last_conditional_mod
, n
);
1387 if (inst
->reads_accumulator_implicitly()) {
1388 assert(last_accumulator_write
);
1389 add_dep(last_accumulator_write
, n
);
1392 /* write-after-write deps. */
1393 if (inst
->dst
.file
== VGRF
) {
1394 for (unsigned j
= 0; j
< regs_written(inst
); ++j
) {
1395 add_dep(last_grf_write
[inst
->dst
.nr
+ j
], n
);
1396 last_grf_write
[inst
->dst
.nr
+ j
] = n
;
1398 } else if (inst
->dst
.file
== MRF
) {
1399 add_dep(last_mrf_write
[inst
->dst
.nr
], n
);
1400 last_mrf_write
[inst
->dst
.nr
] = n
;
1401 } else if (inst
->dst
.file
== FIXED_GRF
) {
1402 last_fixed_grf_write
= n
;
1403 } else if (inst
->dst
.is_accumulator()) {
1404 add_dep(last_accumulator_write
, n
);
1405 last_accumulator_write
= n
;
1406 } else if (inst
->dst
.file
== ARF
&& !inst
->dst
.is_null()) {
1407 add_barrier_deps(n
);
1410 if (inst
->mlen
> 0 && !inst
->is_send_from_grf()) {
1411 for (int i
= 0; i
< v
->implied_mrf_writes(inst
); i
++) {
1412 add_dep(last_mrf_write
[inst
->base_mrf
+ i
], n
);
1413 last_mrf_write
[inst
->base_mrf
+ i
] = n
;
1417 if (inst
->writes_flag()) {
1418 add_dep(last_conditional_mod
, n
, 0);
1419 last_conditional_mod
= n
;
1422 if (inst
->writes_accumulator_implicitly(v
->devinfo
) &&
1423 !inst
->dst
.is_accumulator()) {
1424 add_dep(last_accumulator_write
, n
);
1425 last_accumulator_write
= n
;
1429 /* bottom-to-top dependencies: WAR */
1430 memset(last_grf_write
, 0, sizeof(last_grf_write
));
1431 memset(last_mrf_write
, 0, sizeof(last_mrf_write
));
1432 last_conditional_mod
= NULL
;
1433 last_accumulator_write
= NULL
;
1434 last_fixed_grf_write
= NULL
;
1436 foreach_in_list_reverse_safe(schedule_node
, n
, &instructions
) {
1437 vec4_instruction
*inst
= (vec4_instruction
*)n
->inst
;
1439 /* write-after-read deps. */
1440 for (int i
= 0; i
< 3; i
++) {
1441 if (inst
->src
[i
].file
== VGRF
) {
1442 for (unsigned j
= 0; j
< regs_read(inst
, i
); ++j
)
1443 add_dep(n
, last_grf_write
[inst
->src
[i
].nr
+ j
]);
1444 } else if (inst
->src
[i
].file
== FIXED_GRF
) {
1445 add_dep(n
, last_fixed_grf_write
);
1446 } else if (inst
->src
[i
].is_accumulator()) {
1447 add_dep(n
, last_accumulator_write
);
1448 } else if (inst
->src
[i
].file
== ARF
) {
1449 add_barrier_deps(n
);
1453 if (!inst
->is_send_from_grf()) {
1454 for (int i
= 0; i
< inst
->mlen
; i
++) {
1455 /* It looks like the MRF regs are released in the send
1456 * instruction once it's sent, not when the result comes
1459 add_dep(n
, last_mrf_write
[inst
->base_mrf
+ i
], 2);
1463 if (inst
->reads_flag()) {
1464 add_dep(n
, last_conditional_mod
);
1467 if (inst
->reads_accumulator_implicitly()) {
1468 add_dep(n
, last_accumulator_write
);
1471 /* Update the things this instruction wrote, so earlier reads
1472 * can mark this as WAR dependency.
1474 if (inst
->dst
.file
== VGRF
) {
1475 for (unsigned j
= 0; j
< regs_written(inst
); ++j
)
1476 last_grf_write
[inst
->dst
.nr
+ j
] = n
;
1477 } else if (inst
->dst
.file
== MRF
) {
1478 last_mrf_write
[inst
->dst
.nr
] = n
;
1479 } else if (inst
->dst
.file
== FIXED_GRF
) {
1480 last_fixed_grf_write
= n
;
1481 } else if (inst
->dst
.is_accumulator()) {
1482 last_accumulator_write
= n
;
1483 } else if (inst
->dst
.file
== ARF
&& !inst
->dst
.is_null()) {
1484 add_barrier_deps(n
);
1487 if (inst
->mlen
> 0 && !inst
->is_send_from_grf()) {
1488 for (int i
= 0; i
< v
->implied_mrf_writes(inst
); i
++) {
1489 last_mrf_write
[inst
->base_mrf
+ i
] = n
;
1493 if (inst
->writes_flag()) {
1494 last_conditional_mod
= n
;
1497 if (inst
->writes_accumulator_implicitly(v
->devinfo
)) {
1498 last_accumulator_write
= n
;
1504 fs_instruction_scheduler::choose_instruction_to_schedule()
1506 schedule_node
*chosen
= NULL
;
1508 if (mode
== SCHEDULE_PRE
|| mode
== SCHEDULE_POST
) {
1509 int chosen_time
= 0;
1511 /* Of the instructions ready to execute or the closest to being ready,
1512 * choose the one most likely to unblock an early program exit, or
1513 * otherwise the oldest one.
1515 foreach_in_list(schedule_node
, n
, &instructions
) {
1517 exit_unblocked_time(n
) < exit_unblocked_time(chosen
) ||
1518 (exit_unblocked_time(n
) == exit_unblocked_time(chosen
) &&
1519 n
->unblocked_time
< chosen_time
)) {
1521 chosen_time
= n
->unblocked_time
;
1525 /* Before register allocation, we don't care about the latencies of
1526 * instructions. All we care about is reducing live intervals of
1527 * variables so that we can avoid register spilling, or get SIMD16
1528 * shaders which naturally do a better job of hiding instruction
1531 foreach_in_list(schedule_node
, n
, &instructions
) {
1532 fs_inst
*inst
= (fs_inst
*)n
->inst
;
1539 /* Most important: If we can definitely reduce register pressure, do
1542 int register_pressure_benefit
= get_register_pressure_benefit(n
->inst
);
1543 int chosen_register_pressure_benefit
=
1544 get_register_pressure_benefit(chosen
->inst
);
1546 if (register_pressure_benefit
> 0 &&
1547 register_pressure_benefit
> chosen_register_pressure_benefit
) {
1550 } else if (chosen_register_pressure_benefit
> 0 &&
1551 (register_pressure_benefit
<
1552 chosen_register_pressure_benefit
)) {
1556 if (mode
== SCHEDULE_PRE_LIFO
) {
1557 /* Prefer instructions that recently became available for
1558 * scheduling. These are the things that are most likely to
1559 * (eventually) make a variable dead and reduce register pressure.
1560 * Typical register pressure estimates don't work for us because
1561 * most of our pressure comes from texturing, where no single
1562 * instruction to schedule will make a vec4 value dead.
1564 if (n
->cand_generation
> chosen
->cand_generation
) {
1567 } else if (n
->cand_generation
< chosen
->cand_generation
) {
1571 /* On MRF-using chips, prefer non-SEND instructions. If we don't
1572 * do this, then because we prefer instructions that just became
1573 * candidates, we'll end up in a pattern of scheduling a SEND,
1574 * then the MRFs for the next SEND, then the next SEND, then the
1575 * MRFs, etc., without ever consuming the results of a send.
1577 if (v
->devinfo
->gen
< 7) {
1578 fs_inst
*chosen_inst
= (fs_inst
*)chosen
->inst
;
1580 /* We use size_written > 4 * exec_size as our test for the kind
1581 * of send instruction to avoid -- only sends generate many
1582 * regs, and a single-result send is probably actually reducing
1583 * register pressure.
1585 if (inst
->size_written
<= 4 * inst
->exec_size
&&
1586 chosen_inst
->size_written
> 4 * chosen_inst
->exec_size
) {
1589 } else if (inst
->size_written
> chosen_inst
->size_written
) {
1595 /* For instructions pushed on the cands list at the same time, prefer
1596 * the one with the highest delay to the end of the program. This is
1597 * most likely to have its values able to be consumed first (such as
1598 * for a large tree of lowered ubo loads, which appear reversed in
1599 * the instruction stream with respect to when they can be consumed).
1601 if (n
->delay
> chosen
->delay
) {
1604 } else if (n
->delay
< chosen
->delay
) {
1608 /* Prefer the node most likely to unblock an early program exit.
1610 if (exit_unblocked_time(n
) < exit_unblocked_time(chosen
)) {
1613 } else if (exit_unblocked_time(n
) > exit_unblocked_time(chosen
)) {
1617 /* If all other metrics are equal, we prefer the first instruction in
1618 * the list (program execution).
1627 vec4_instruction_scheduler::choose_instruction_to_schedule()
1629 schedule_node
*chosen
= NULL
;
1630 int chosen_time
= 0;
1632 /* Of the instructions ready to execute or the closest to being ready,
1633 * choose the oldest one.
1635 foreach_in_list(schedule_node
, n
, &instructions
) {
1636 if (!chosen
|| n
->unblocked_time
< chosen_time
) {
1638 chosen_time
= n
->unblocked_time
;
1646 fs_instruction_scheduler::issue_time(backend_instruction
*inst
)
1648 const unsigned overhead
= v
->bank_conflict_cycles((fs_inst
*)inst
);
1649 if (is_compressed((fs_inst
*)inst
))
1650 return 4 + overhead
;
1652 return 2 + overhead
;
1656 vec4_instruction_scheduler::issue_time(backend_instruction
*)
1658 /* We always execute as two vec4s in parallel. */
1663 instruction_scheduler::schedule_instructions(bblock_t
*block
)
1665 const struct gen_device_info
*devinfo
= bs
->devinfo
;
1667 if (!post_reg_alloc
)
1668 reg_pressure
= reg_pressure_in
[block
->num
];
1669 block_idx
= block
->num
;
1671 /* Remove non-DAG heads from the list. */
1672 foreach_in_list_safe(schedule_node
, n
, &instructions
) {
1673 if (n
->parent_count
!= 0)
1677 unsigned cand_generation
= 1;
1678 while (!instructions
.is_empty()) {
1679 schedule_node
*chosen
= choose_instruction_to_schedule();
1681 /* Schedule this instruction. */
1684 chosen
->inst
->exec_node::remove();
1685 block
->instructions
.push_tail(chosen
->inst
);
1686 instructions_to_schedule
--;
1688 if (!post_reg_alloc
) {
1689 reg_pressure
-= get_register_pressure_benefit(chosen
->inst
);
1690 update_register_pressure(chosen
->inst
);
1693 /* If we expected a delay for scheduling, then bump the clock to reflect
1694 * that. In reality, the hardware will switch to another hyperthread
1695 * and may not return to dispatching our thread for a while even after
1696 * we're unblocked. After this, we have the time when the chosen
1697 * instruction will start executing.
1699 time
= MAX2(time
, chosen
->unblocked_time
);
1701 /* Update the clock for how soon an instruction could start after the
1704 time
+= issue_time(chosen
->inst
);
1707 fprintf(stderr
, "clock %4d, scheduled: ", time
);
1708 bs
->dump_instruction(chosen
->inst
);
1709 if (!post_reg_alloc
)
1710 fprintf(stderr
, "(register pressure %d)\n", reg_pressure
);
1713 /* Now that we've scheduled a new instruction, some of its
1714 * children can be promoted to the list of instructions ready to
1715 * be scheduled. Update the children's unblocked time for this
1716 * DAG edge as we do so.
1718 for (int i
= chosen
->child_count
- 1; i
>= 0; i
--) {
1719 schedule_node
*child
= chosen
->children
[i
];
1721 child
->unblocked_time
= MAX2(child
->unblocked_time
,
1722 time
+ chosen
->child_latency
[i
]);
1725 fprintf(stderr
, "\tchild %d, %d parents: ", i
, child
->parent_count
);
1726 bs
->dump_instruction(child
->inst
);
1729 child
->cand_generation
= cand_generation
;
1730 child
->parent_count
--;
1731 if (child
->parent_count
== 0) {
1733 fprintf(stderr
, "\t\tnow available\n");
1735 instructions
.push_head(child
);
1740 /* Shared resource: the mathbox. There's one mathbox per EU on Gen6+
1741 * but it's more limited pre-gen6, so if we send something off to it then
1742 * the next math instruction isn't going to make progress until the first
1745 if (devinfo
->gen
< 6 && chosen
->inst
->is_math()) {
1746 foreach_in_list(schedule_node
, n
, &instructions
) {
1747 if (n
->inst
->is_math())
1748 n
->unblocked_time
= MAX2(n
->unblocked_time
,
1749 time
+ chosen
->latency
);
1754 assert(instructions_to_schedule
== 0);
1756 block
->cycle_count
= time
;
1759 static unsigned get_cycle_count(cfg_t
*cfg
)
1761 unsigned count
= 0, multiplier
= 1;
1762 foreach_block(block
, cfg
) {
1763 if (block
->start()->opcode
== BRW_OPCODE_DO
)
1764 multiplier
*= 10; /* assume that loops execute ~10 times */
1766 count
+= block
->cycle_count
* multiplier
;
1768 if (block
->end()->opcode
== BRW_OPCODE_WHILE
)
1776 instruction_scheduler::run(cfg_t
*cfg
)
1778 if (debug
&& !post_reg_alloc
) {
1779 fprintf(stderr
, "\nInstructions before scheduling (reg_alloc %d)\n",
1781 bs
->dump_instructions();
1784 if (!post_reg_alloc
)
1785 setup_liveness(cfg
);
1787 foreach_block(block
, cfg
) {
1788 if (reads_remaining
) {
1789 memset(reads_remaining
, 0,
1790 grf_count
* sizeof(*reads_remaining
));
1791 memset(hw_reads_remaining
, 0,
1792 hw_reg_count
* sizeof(*hw_reads_remaining
));
1793 memset(written
, 0, grf_count
* sizeof(*written
));
1795 foreach_inst_in_block(fs_inst
, inst
, block
)
1796 count_reads_remaining(inst
);
1799 add_insts_from_block(block
);
1806 schedule_instructions(block
);
1809 if (debug
&& !post_reg_alloc
) {
1810 fprintf(stderr
, "\nInstructions after scheduling (reg_alloc %d)\n",
1812 bs
->dump_instructions();
1815 cfg
->cycle_count
= get_cycle_count(cfg
);
1819 fs_visitor::schedule_instructions(instruction_scheduler_mode mode
)
1821 if (mode
!= SCHEDULE_POST
)
1822 calculate_live_intervals();
1825 if (mode
== SCHEDULE_POST
)
1826 grf_count
= grf_used
;
1828 grf_count
= alloc
.count
;
1830 fs_instruction_scheduler
sched(this, grf_count
, first_non_payload_grf
,
1831 cfg
->num_blocks
, mode
);
1834 invalidate_live_intervals();
1838 vec4_visitor::opt_schedule_instructions()
1840 vec4_instruction_scheduler
sched(this, prog_data
->total_grf
);
1843 invalidate_live_intervals();