2 * Copyright © 2010 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Eric Anholt <eric@anholt.net>
29 #include "brw_fs_live_variables.h"
32 #include "brw_shader.h"
36 /** @file brw_fs_schedule_instructions.cpp
38 * List scheduling of FS instructions.
40 * The basic model of the list scheduler is to take a basic block,
41 * compute a DAG of the dependencies (RAW ordering with latency, WAW
42 * ordering with latency, WAR ordering), and make a list of the DAG heads.
43 * Heuristically pick a DAG head, then put all the children that are
44 * now DAG heads into the list of things to schedule.
46 * The heuristic is the important part. We're trying to be cheap,
47 * since actually computing the optimal scheduling is NP complete.
48 * What we do is track a "current clock". When we schedule a node, we
49 * update the earliest-unblocked clock time of its children, and
50 * increment the clock. Then, when trying to schedule, we just pick
51 * the earliest-unblocked instruction to schedule.
53 * Note that often there will be many things which could execute
54 * immediately, and there are a range of heuristic options to choose
55 * from in picking among those.
58 static bool debug
= false;
60 class instruction_scheduler
;
62 class schedule_node
: public exec_node
65 schedule_node(backend_instruction
*inst
, instruction_scheduler
*sched
);
66 void set_latency_gen4();
67 void set_latency_gen7(bool is_haswell
);
69 backend_instruction
*inst
;
70 schedule_node
**children
;
79 * Which iteration of pushing groups of children onto the candidates list
80 * this node was a part of.
82 unsigned cand_generation
;
85 * This is the sum of the instruction's latency plus the maximum delay of
86 * its children, or just the issue_time if it's a leaf node.
91 * Preferred exit node among the (direct or indirect) successors of this
92 * node. Among the scheduler nodes blocked by this node, this will be the
93 * one that may cause earliest program termination, or NULL if none of the
94 * successors is an exit node.
100 * Lower bound of the scheduling time after which one of the instructions
101 * blocked by this node may lead to program termination.
103 * exit_unblocked_time() determines a strict partial ordering relation '«' on
104 * the set of scheduler nodes as follows:
106 * n « m <-> exit_unblocked_time(n) < exit_unblocked_time(m)
108 * which can be used to heuristically order nodes according to how early they
109 * can unblock an exit node and lead to program termination.
112 exit_unblocked_time(const schedule_node
*n
)
114 return n
->exit
? n
->exit
->unblocked_time
: INT_MAX
;
118 schedule_node::set_latency_gen4()
121 int math_latency
= 22;
123 switch (inst
->opcode
) {
124 case SHADER_OPCODE_RCP
:
125 this->latency
= 1 * chans
* math_latency
;
127 case SHADER_OPCODE_RSQ
:
128 this->latency
= 2 * chans
* math_latency
;
130 case SHADER_OPCODE_INT_QUOTIENT
:
131 case SHADER_OPCODE_SQRT
:
132 case SHADER_OPCODE_LOG2
:
133 /* full precision log. partial is 2. */
134 this->latency
= 3 * chans
* math_latency
;
136 case SHADER_OPCODE_INT_REMAINDER
:
137 case SHADER_OPCODE_EXP2
:
138 /* full precision. partial is 3, same throughput. */
139 this->latency
= 4 * chans
* math_latency
;
141 case SHADER_OPCODE_POW
:
142 this->latency
= 8 * chans
* math_latency
;
144 case SHADER_OPCODE_SIN
:
145 case SHADER_OPCODE_COS
:
146 /* minimum latency, max is 12 rounds. */
147 this->latency
= 5 * chans
* math_latency
;
156 schedule_node::set_latency_gen7(bool is_haswell
)
158 switch (inst
->opcode
) {
161 * (since the last two src operands are in different register banks):
162 * mad(8) g4<1>F g2.2<4,4,1>F.x g2<4,4,1>F.x g3.1<4,4,1>F.x { align16 WE_normal 1Q };
164 * 3 cycles on IVB, 4 on HSW
165 * (since the last two src operands are in the same register bank):
166 * mad(8) g4<1>F g2.2<4,4,1>F.x g2<4,4,1>F.x g2.1<4,4,1>F.x { align16 WE_normal 1Q };
168 * 18 cycles on IVB, 16 on HSW
169 * (since the last two src operands are in different register banks):
170 * mad(8) g4<1>F g2.2<4,4,1>F.x g2<4,4,1>F.x g3.1<4,4,1>F.x { align16 WE_normal 1Q };
171 * mov(8) null g4<4,5,1>F { align16 WE_normal 1Q };
173 * 20 cycles on IVB, 18 on HSW
174 * (since the last two src operands are in the same register bank):
175 * mad(8) g4<1>F g2.2<4,4,1>F.x g2<4,4,1>F.x g2.1<4,4,1>F.x { align16 WE_normal 1Q };
176 * mov(8) null g4<4,4,1>F { align16 WE_normal 1Q };
179 /* Our register allocator doesn't know about register banks, so use the
182 latency
= is_haswell
? 16 : 18;
187 * (since the last two src operands are in different register banks):
188 * lrp(8) g4<1>F g2.2<4,4,1>F.x g2<4,4,1>F.x g3.1<4,4,1>F.x { align16 WE_normal 1Q };
190 * 3 cycles on IVB, 4 on HSW
191 * (since the last two src operands are in the same register bank):
192 * lrp(8) g4<1>F g2.2<4,4,1>F.x g2<4,4,1>F.x g2.1<4,4,1>F.x { align16 WE_normal 1Q };
194 * 16 cycles on IVB, 14 on HSW
195 * (since the last two src operands are in different register banks):
196 * lrp(8) g4<1>F g2.2<4,4,1>F.x g2<4,4,1>F.x g3.1<4,4,1>F.x { align16 WE_normal 1Q };
197 * mov(8) null g4<4,4,1>F { align16 WE_normal 1Q };
200 * (since the last two src operands are in the same register bank):
201 * lrp(8) g4<1>F g2.2<4,4,1>F.x g2<4,4,1>F.x g2.1<4,4,1>F.x { align16 WE_normal 1Q };
202 * mov(8) null g4<4,4,1>F { align16 WE_normal 1Q };
205 /* Our register allocator doesn't know about register banks, so use the
211 case SHADER_OPCODE_RCP
:
212 case SHADER_OPCODE_RSQ
:
213 case SHADER_OPCODE_SQRT
:
214 case SHADER_OPCODE_LOG2
:
215 case SHADER_OPCODE_EXP2
:
216 case SHADER_OPCODE_SIN
:
217 case SHADER_OPCODE_COS
:
219 * math inv(8) g4<1>F g2<0,1,0>F null { align1 WE_normal 1Q };
222 * math inv(8) g4<1>F g2<0,1,0>F null { align1 WE_normal 1Q };
223 * mov(8) null g4<8,8,1>F { align1 WE_normal 1Q };
225 * Same for exp2, log2, rsq, sqrt, sin, cos.
227 latency
= is_haswell
? 14 : 16;
230 case SHADER_OPCODE_POW
:
232 * math pow(8) g4<1>F g2<0,1,0>F g2.1<0,1,0>F { align1 WE_normal 1Q };
235 * math pow(8) g4<1>F g2<0,1,0>F g2.1<0,1,0>F { align1 WE_normal 1Q };
236 * mov(8) null g4<8,8,1>F { align1 WE_normal 1Q };
238 latency
= is_haswell
? 22 : 24;
241 case SHADER_OPCODE_TEX
:
242 case SHADER_OPCODE_TXD
:
243 case SHADER_OPCODE_TXF
:
244 case SHADER_OPCODE_TXF_LZ
:
245 case SHADER_OPCODE_TXL
:
246 case SHADER_OPCODE_TXL_LZ
:
248 * mov(8) g115<1>F 0F { align1 WE_normal 1Q };
249 * mov(8) g114<1>F 0F { align1 WE_normal 1Q };
250 * send(8) g4<1>UW g114<8,8,1>F
251 * sampler (10, 0, 0, 1) mlen 2 rlen 4 { align1 WE_normal 1Q };
253 * 697 +/-49 cycles (min 610, n=26):
254 * mov(8) g115<1>F 0F { align1 WE_normal 1Q };
255 * mov(8) g114<1>F 0F { align1 WE_normal 1Q };
256 * send(8) g4<1>UW g114<8,8,1>F
257 * sampler (10, 0, 0, 1) mlen 2 rlen 4 { align1 WE_normal 1Q };
258 * mov(8) null g4<8,8,1>F { align1 WE_normal 1Q };
260 * So the latency on our first texture load of the batchbuffer takes
261 * ~700 cycles, since the caches are cold at that point.
263 * 840 +/- 92 cycles (min 720, n=25):
264 * mov(8) g115<1>F 0F { align1 WE_normal 1Q };
265 * mov(8) g114<1>F 0F { align1 WE_normal 1Q };
266 * send(8) g4<1>UW g114<8,8,1>F
267 * sampler (10, 0, 0, 1) mlen 2 rlen 4 { align1 WE_normal 1Q };
268 * mov(8) null g4<8,8,1>F { align1 WE_normal 1Q };
269 * send(8) g4<1>UW g114<8,8,1>F
270 * sampler (10, 0, 0, 1) mlen 2 rlen 4 { align1 WE_normal 1Q };
271 * mov(8) null g4<8,8,1>F { align1 WE_normal 1Q };
273 * On the second load, it takes just an extra ~140 cycles, and after
274 * accounting for the 14 cycles of the MOV's latency, that makes ~130.
276 * 683 +/- 49 cycles (min = 602, n=47):
277 * mov(8) g115<1>F 0F { align1 WE_normal 1Q };
278 * mov(8) g114<1>F 0F { align1 WE_normal 1Q };
279 * send(8) g4<1>UW g114<8,8,1>F
280 * sampler (10, 0, 0, 1) mlen 2 rlen 4 { align1 WE_normal 1Q };
281 * send(8) g50<1>UW g114<8,8,1>F
282 * sampler (10, 0, 0, 1) mlen 2 rlen 4 { align1 WE_normal 1Q };
283 * mov(8) null g4<8,8,1>F { align1 WE_normal 1Q };
285 * The unit appears to be pipelined, since this matches up with the
286 * cache-cold case, despite there being two loads here. If you replace
287 * the g4 in the MOV to null with g50, it's still 693 +/- 52 (n=39).
289 * So, take some number between the cache-hot 140 cycles and the
290 * cache-cold 700 cycles. No particular tuning was done on this.
292 * I haven't done significant testing of the non-TEX opcodes. TXL at
293 * least looked about the same as TEX.
298 case SHADER_OPCODE_TXS
:
299 /* Testing textureSize(sampler2D, 0), one load was 420 +/- 41
301 * mov(8) g114<1>UD 0D { align1 WE_normal 1Q };
302 * send(8) g6<1>UW g114<8,8,1>F
303 * sampler (10, 0, 10, 1) mlen 1 rlen 4 { align1 WE_normal 1Q };
304 * mov(16) g6<1>F g6<8,8,1>D { align1 WE_normal 1Q };
307 * Two loads was 535 +/- 30 cycles (n=19):
308 * mov(16) g114<1>UD 0D { align1 WE_normal 1H };
309 * send(16) g6<1>UW g114<8,8,1>F
310 * sampler (10, 0, 10, 2) mlen 2 rlen 8 { align1 WE_normal 1H };
311 * mov(16) g114<1>UD 0D { align1 WE_normal 1H };
312 * mov(16) g6<1>F g6<8,8,1>D { align1 WE_normal 1H };
313 * send(16) g8<1>UW g114<8,8,1>F
314 * sampler (10, 0, 10, 2) mlen 2 rlen 8 { align1 WE_normal 1H };
315 * mov(16) g8<1>F g8<8,8,1>D { align1 WE_normal 1H };
316 * add(16) g6<1>F g6<8,8,1>F g8<8,8,1>F { align1 WE_normal 1H };
318 * Since the only caches that should matter are just the
319 * instruction/state cache containing the surface state, assume that we
320 * always have hot caches.
325 case FS_OPCODE_VARYING_PULL_CONSTANT_LOAD_GEN4
:
326 case FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD
:
327 case FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD_GEN7
:
328 case VS_OPCODE_PULL_CONSTANT_LOAD
:
329 /* testing using varying-index pull constants:
332 * mov(8) g4<1>D g2.1<0,1,0>F { align1 WE_normal 1Q };
333 * send(8) g4<1>F g4<8,8,1>D
334 * data (9, 2, 3) mlen 1 rlen 1 { align1 WE_normal 1Q };
337 * mov(8) g4<1>D g2.1<0,1,0>F { align1 WE_normal 1Q };
338 * send(8) g4<1>F g4<8,8,1>D
339 * data (9, 2, 3) mlen 1 rlen 1 { align1 WE_normal 1Q };
340 * mov(8) null g4<8,8,1>F { align1 WE_normal 1Q };
343 * mov(8) g4<1>D g2.1<0,1,0>F { align1 WE_normal 1Q };
344 * send(8) g4<1>F g4<8,8,1>D
345 * data (9, 2, 3) mlen 1 rlen 1 { align1 WE_normal 1Q };
346 * mov(8) null g4<8,8,1>F { align1 WE_normal 1Q };
347 * send(8) g4<1>F g4<8,8,1>D
348 * data (9, 2, 3) mlen 1 rlen 1 { align1 WE_normal 1Q };
349 * mov(8) null g4<8,8,1>F { align1 WE_normal 1Q };
351 * So, if it's cache-hot, it's about 140. If it's cache cold, it's
352 * about 460. We expect to mostly be cache hot, so pick something more
358 case SHADER_OPCODE_GEN7_SCRATCH_READ
:
359 /* Testing a load from offset 0, that had been previously written:
361 * send(8) g114<1>UW g0<8,8,1>F data (0, 0, 0) mlen 1 rlen 1 { align1 WE_normal 1Q };
362 * mov(8) null g114<8,8,1>F { align1 WE_normal 1Q };
364 * The cycles spent seemed to be grouped around 40-50 (as low as 38),
365 * then around 140. Presumably this is cache hit vs miss.
370 case SHADER_OPCODE_UNTYPED_ATOMIC
:
371 case SHADER_OPCODE_UNTYPED_ATOMIC_FLOAT
:
372 case SHADER_OPCODE_TYPED_ATOMIC
:
374 * mov(8) g112<1>ud 0x00000000ud { align1 WE_all 1Q };
375 * mov(1) g112.7<1>ud g1.7<0,1,0>ud { align1 WE_all };
376 * mov(8) g113<1>ud 0x00000000ud { align1 WE_normal 1Q };
377 * send(8) g4<1>ud g112<8,8,1>ud
378 * data (38, 5, 6) mlen 2 rlen 1 { align1 WE_normal 1Q };
380 * Running it 100 times as fragment shader on a 128x128 quad
381 * gives an average latency of 13867 cycles per atomic op,
382 * standard deviation 3%. Note that this is a rather
383 * pessimistic estimate, the actual latency in cases with few
384 * collisions between threads and favorable pipelining has been
385 * seen to be reduced by a factor of 100.
390 case SHADER_OPCODE_UNTYPED_SURFACE_READ
:
391 case SHADER_OPCODE_UNTYPED_SURFACE_WRITE
:
392 case SHADER_OPCODE_TYPED_SURFACE_READ
:
393 case SHADER_OPCODE_TYPED_SURFACE_WRITE
:
395 * mov(8) g112<1>UD 0x00000000UD { align1 WE_all 1Q };
396 * mov(1) g112.7<1>UD g1.7<0,1,0>UD { align1 WE_all };
397 * mov(8) g113<1>UD 0x00000000UD { align1 WE_normal 1Q };
398 * send(8) g4<1>UD g112<8,8,1>UD
399 * data (38, 6, 5) mlen 2 rlen 1 { align1 WE_normal 1Q };
401 * . [repeats 8 times]
403 * mov(8) g112<1>UD 0x00000000UD { align1 WE_all 1Q };
404 * mov(1) g112.7<1>UD g1.7<0,1,0>UD { align1 WE_all };
405 * mov(8) g113<1>UD 0x00000000UD { align1 WE_normal 1Q };
406 * send(8) g4<1>UD g112<8,8,1>UD
407 * data (38, 6, 5) mlen 2 rlen 1 { align1 WE_normal 1Q };
409 * Running it 100 times as fragment shader on a 128x128 quad
410 * gives an average latency of 583 cycles per surface read,
411 * standard deviation 0.9%.
413 latency
= is_haswell
? 300 : 600;
416 case SHADER_OPCODE_SEND
:
417 switch (inst
->sfid
) {
418 case BRW_SFID_SAMPLER
: {
419 unsigned msg_type
= (inst
->desc
>> 12) & 0x1f;
421 case GEN5_SAMPLER_MESSAGE_SAMPLE_RESINFO
:
422 case GEN6_SAMPLER_MESSAGE_SAMPLE_SAMPLEINFO
:
423 /* See also SHADER_OPCODE_TXS */
428 /* See also SHADER_OPCODE_TEX */
435 case GEN6_SFID_DATAPORT_RENDER_CACHE
:
436 switch ((inst
->desc
>> 14) & 0x1f) {
437 case GEN7_DATAPORT_RC_TYPED_SURFACE_WRITE
:
438 case GEN7_DATAPORT_RC_TYPED_SURFACE_READ
:
439 /* See also SHADER_OPCODE_TYPED_SURFACE_READ */
444 case GEN7_DATAPORT_RC_TYPED_ATOMIC_OP
:
445 /* See also SHADER_OPCODE_TYPED_ATOMIC */
451 unreachable("Unknown render cache message");
455 case GEN7_SFID_DATAPORT_DATA_CACHE
:
456 switch ((inst
->desc
>> 14) & 0x1f) {
457 case HSW_DATAPORT_DC_PORT0_BYTE_SCATTERED_READ
:
458 case HSW_DATAPORT_DC_PORT0_BYTE_SCATTERED_WRITE
:
459 /* We have no data for this but assume it's roughly the same as
460 * untyped surface read/write.
465 case GEN7_DATAPORT_DC_UNTYPED_SURFACE_READ
:
466 case GEN7_DATAPORT_DC_UNTYPED_SURFACE_WRITE
:
467 /* See also SHADER_OPCODE_UNTYPED_SURFACE_READ */
472 case GEN7_DATAPORT_DC_UNTYPED_ATOMIC_OP
:
473 /* See also SHADER_OPCODE_UNTYPED_ATOMIC */
479 unreachable("Unknown data cache message");
483 case HSW_SFID_DATAPORT_DATA_CACHE_1
:
484 switch ((inst
->desc
>> 14) & 0x1f) {
485 case HSW_DATAPORT_DC_PORT1_UNTYPED_SURFACE_READ
:
486 case HSW_DATAPORT_DC_PORT1_UNTYPED_SURFACE_WRITE
:
487 case HSW_DATAPORT_DC_PORT1_TYPED_SURFACE_READ
:
488 case HSW_DATAPORT_DC_PORT1_TYPED_SURFACE_WRITE
:
489 case GEN8_DATAPORT_DC_PORT1_A64_UNTYPED_SURFACE_WRITE
:
490 case GEN8_DATAPORT_DC_PORT1_A64_UNTYPED_SURFACE_READ
:
491 case GEN8_DATAPORT_DC_PORT1_A64_SCATTERED_WRITE
:
492 case GEN9_DATAPORT_DC_PORT1_A64_SCATTERED_READ
:
493 /* See also SHADER_OPCODE_UNTYPED_SURFACE_READ */
497 case HSW_DATAPORT_DC_PORT1_UNTYPED_ATOMIC_OP
:
498 case HSW_DATAPORT_DC_PORT1_UNTYPED_ATOMIC_OP_SIMD4X2
:
499 case HSW_DATAPORT_DC_PORT1_TYPED_ATOMIC_OP_SIMD4X2
:
500 case HSW_DATAPORT_DC_PORT1_TYPED_ATOMIC_OP
:
501 case GEN9_DATAPORT_DC_PORT1_UNTYPED_ATOMIC_FLOAT_OP
:
502 case GEN8_DATAPORT_DC_PORT1_A64_UNTYPED_ATOMIC_OP
:
503 case GEN9_DATAPORT_DC_PORT1_A64_UNTYPED_ATOMIC_FLOAT_OP
:
504 /* See also SHADER_OPCODE_UNTYPED_ATOMIC */
509 unreachable("Unknown data cache message");
514 unreachable("Unknown SFID");
520 * mul(8) g4<1>F g2<0,1,0>F 0.5F { align1 WE_normal 1Q };
523 * mul(8) g4<1>F g2<0,1,0>F 0.5F { align1 WE_normal 1Q };
524 * mov(8) null g4<8,8,1>F { align1 WE_normal 1Q };
531 class instruction_scheduler
{
533 instruction_scheduler(backend_shader
*s
, int grf_count
,
534 unsigned hw_reg_count
, int block_count
,
535 instruction_scheduler_mode mode
)
538 this->mem_ctx
= ralloc_context(NULL
);
539 this->grf_count
= grf_count
;
540 this->hw_reg_count
= hw_reg_count
;
541 this->instructions
.make_empty();
542 this->instructions_to_schedule
= 0;
543 this->post_reg_alloc
= (mode
== SCHEDULE_POST
);
545 if (!post_reg_alloc
) {
546 this->reg_pressure_in
= rzalloc_array(mem_ctx
, int, block_count
);
548 this->livein
= ralloc_array(mem_ctx
, BITSET_WORD
*, block_count
);
549 for (int i
= 0; i
< block_count
; i
++)
550 this->livein
[i
] = rzalloc_array(mem_ctx
, BITSET_WORD
,
551 BITSET_WORDS(grf_count
));
553 this->liveout
= ralloc_array(mem_ctx
, BITSET_WORD
*, block_count
);
554 for (int i
= 0; i
< block_count
; i
++)
555 this->liveout
[i
] = rzalloc_array(mem_ctx
, BITSET_WORD
,
556 BITSET_WORDS(grf_count
));
558 this->hw_liveout
= ralloc_array(mem_ctx
, BITSET_WORD
*, block_count
);
559 for (int i
= 0; i
< block_count
; i
++)
560 this->hw_liveout
[i
] = rzalloc_array(mem_ctx
, BITSET_WORD
,
561 BITSET_WORDS(hw_reg_count
));
563 this->written
= rzalloc_array(mem_ctx
, bool, grf_count
);
565 this->reads_remaining
= rzalloc_array(mem_ctx
, int, grf_count
);
567 this->hw_reads_remaining
= rzalloc_array(mem_ctx
, int, hw_reg_count
);
569 this->reg_pressure_in
= NULL
;
571 this->liveout
= NULL
;
572 this->hw_liveout
= NULL
;
573 this->written
= NULL
;
574 this->reads_remaining
= NULL
;
575 this->hw_reads_remaining
= NULL
;
579 ~instruction_scheduler()
581 ralloc_free(this->mem_ctx
);
583 void add_barrier_deps(schedule_node
*n
);
584 void add_dep(schedule_node
*before
, schedule_node
*after
, int latency
);
585 void add_dep(schedule_node
*before
, schedule_node
*after
);
587 void run(cfg_t
*cfg
);
588 void add_insts_from_block(bblock_t
*block
);
589 void compute_delays();
590 void compute_exits();
591 virtual void calculate_deps() = 0;
592 virtual schedule_node
*choose_instruction_to_schedule() = 0;
595 * Returns how many cycles it takes the instruction to issue.
597 * Instructions in gen hardware are handled one simd4 vector at a time,
598 * with 1 cycle per vector dispatched. Thus SIMD8 pixel shaders take 2
599 * cycles to dispatch and SIMD16 (compressed) instructions take 4.
601 virtual int issue_time(backend_instruction
*inst
) = 0;
603 virtual void count_reads_remaining(backend_instruction
*inst
) = 0;
604 virtual void setup_liveness(cfg_t
*cfg
) = 0;
605 virtual void update_register_pressure(backend_instruction
*inst
) = 0;
606 virtual int get_register_pressure_benefit(backend_instruction
*inst
) = 0;
608 void schedule_instructions(bblock_t
*block
);
613 int instructions_to_schedule
;
615 unsigned hw_reg_count
;
618 exec_list instructions
;
621 instruction_scheduler_mode mode
;
624 * The register pressure at the beginning of each basic block.
627 int *reg_pressure_in
;
630 * The virtual GRF's whose range overlaps the beginning of each basic block.
633 BITSET_WORD
**livein
;
636 * The virtual GRF's whose range overlaps the end of each basic block.
639 BITSET_WORD
**liveout
;
642 * The hardware GRF's whose range overlaps the end of each basic block.
645 BITSET_WORD
**hw_liveout
;
648 * Whether we've scheduled a write for this virtual GRF yet.
654 * How many reads we haven't scheduled for this virtual GRF yet.
657 int *reads_remaining
;
660 * How many reads we haven't scheduled for this hardware GRF yet.
663 int *hw_reads_remaining
;
666 class fs_instruction_scheduler
: public instruction_scheduler
669 fs_instruction_scheduler(fs_visitor
*v
, int grf_count
, int hw_reg_count
,
671 instruction_scheduler_mode mode
);
672 void calculate_deps();
673 bool is_compressed(fs_inst
*inst
);
674 schedule_node
*choose_instruction_to_schedule();
675 int issue_time(backend_instruction
*inst
);
678 void count_reads_remaining(backend_instruction
*inst
);
679 void setup_liveness(cfg_t
*cfg
);
680 void update_register_pressure(backend_instruction
*inst
);
681 int get_register_pressure_benefit(backend_instruction
*inst
);
684 fs_instruction_scheduler::fs_instruction_scheduler(fs_visitor
*v
,
685 int grf_count
, int hw_reg_count
,
687 instruction_scheduler_mode mode
)
688 : instruction_scheduler(v
, grf_count
, hw_reg_count
, block_count
, mode
),
694 is_src_duplicate(fs_inst
*inst
, int src
)
696 for (int i
= 0; i
< src
; i
++)
697 if (inst
->src
[i
].equals(inst
->src
[src
]))
704 fs_instruction_scheduler::count_reads_remaining(backend_instruction
*be
)
706 fs_inst
*inst
= (fs_inst
*)be
;
708 if (!reads_remaining
)
711 for (int i
= 0; i
< inst
->sources
; i
++) {
712 if (is_src_duplicate(inst
, i
))
715 if (inst
->src
[i
].file
== VGRF
) {
716 reads_remaining
[inst
->src
[i
].nr
]++;
717 } else if (inst
->src
[i
].file
== FIXED_GRF
) {
718 if (inst
->src
[i
].nr
>= hw_reg_count
)
721 for (unsigned j
= 0; j
< regs_read(inst
, i
); j
++)
722 hw_reads_remaining
[inst
->src
[i
].nr
+ j
]++;
728 fs_instruction_scheduler::setup_liveness(cfg_t
*cfg
)
730 /* First, compute liveness on a per-GRF level using the in/out sets from
731 * liveness calculation.
733 for (int block
= 0; block
< cfg
->num_blocks
; block
++) {
734 for (int i
= 0; i
< v
->live_intervals
->num_vars
; i
++) {
735 if (BITSET_TEST(v
->live_intervals
->block_data
[block
].livein
, i
)) {
736 int vgrf
= v
->live_intervals
->vgrf_from_var
[i
];
737 if (!BITSET_TEST(livein
[block
], vgrf
)) {
738 reg_pressure_in
[block
] += v
->alloc
.sizes
[vgrf
];
739 BITSET_SET(livein
[block
], vgrf
);
743 if (BITSET_TEST(v
->live_intervals
->block_data
[block
].liveout
, i
))
744 BITSET_SET(liveout
[block
], v
->live_intervals
->vgrf_from_var
[i
]);
748 /* Now, extend the live in/live out sets for when a range crosses a block
749 * boundary, which matches what our register allocator/interference code
750 * does to account for force_writemask_all and incompatible exec_mask's.
752 for (int block
= 0; block
< cfg
->num_blocks
- 1; block
++) {
753 for (int i
= 0; i
< grf_count
; i
++) {
754 if (v
->virtual_grf_start
[i
] <= cfg
->blocks
[block
]->end_ip
&&
755 v
->virtual_grf_end
[i
] >= cfg
->blocks
[block
+ 1]->start_ip
) {
756 if (!BITSET_TEST(livein
[block
+ 1], i
)) {
757 reg_pressure_in
[block
+ 1] += v
->alloc
.sizes
[i
];
758 BITSET_SET(livein
[block
+ 1], i
);
761 BITSET_SET(liveout
[block
], i
);
766 int payload_last_use_ip
[hw_reg_count
];
767 v
->calculate_payload_ranges(hw_reg_count
, payload_last_use_ip
);
769 for (unsigned i
= 0; i
< hw_reg_count
; i
++) {
770 if (payload_last_use_ip
[i
] == -1)
773 for (int block
= 0; block
< cfg
->num_blocks
; block
++) {
774 if (cfg
->blocks
[block
]->start_ip
<= payload_last_use_ip
[i
])
775 reg_pressure_in
[block
]++;
777 if (cfg
->blocks
[block
]->end_ip
<= payload_last_use_ip
[i
])
778 BITSET_SET(hw_liveout
[block
], i
);
784 fs_instruction_scheduler::update_register_pressure(backend_instruction
*be
)
786 fs_inst
*inst
= (fs_inst
*)be
;
788 if (!reads_remaining
)
791 if (inst
->dst
.file
== VGRF
) {
792 written
[inst
->dst
.nr
] = true;
795 for (int i
= 0; i
< inst
->sources
; i
++) {
796 if (is_src_duplicate(inst
, i
))
799 if (inst
->src
[i
].file
== VGRF
) {
800 reads_remaining
[inst
->src
[i
].nr
]--;
801 } else if (inst
->src
[i
].file
== FIXED_GRF
&&
802 inst
->src
[i
].nr
< hw_reg_count
) {
803 for (unsigned off
= 0; off
< regs_read(inst
, i
); off
++)
804 hw_reads_remaining
[inst
->src
[i
].nr
+ off
]--;
810 fs_instruction_scheduler::get_register_pressure_benefit(backend_instruction
*be
)
812 fs_inst
*inst
= (fs_inst
*)be
;
815 if (inst
->dst
.file
== VGRF
) {
816 if (!BITSET_TEST(livein
[block_idx
], inst
->dst
.nr
) &&
817 !written
[inst
->dst
.nr
])
818 benefit
-= v
->alloc
.sizes
[inst
->dst
.nr
];
821 for (int i
= 0; i
< inst
->sources
; i
++) {
822 if (is_src_duplicate(inst
, i
))
825 if (inst
->src
[i
].file
== VGRF
&&
826 !BITSET_TEST(liveout
[block_idx
], inst
->src
[i
].nr
) &&
827 reads_remaining
[inst
->src
[i
].nr
] == 1)
828 benefit
+= v
->alloc
.sizes
[inst
->src
[i
].nr
];
830 if (inst
->src
[i
].file
== FIXED_GRF
&&
831 inst
->src
[i
].nr
< hw_reg_count
) {
832 for (unsigned off
= 0; off
< regs_read(inst
, i
); off
++) {
833 int reg
= inst
->src
[i
].nr
+ off
;
834 if (!BITSET_TEST(hw_liveout
[block_idx
], reg
) &&
835 hw_reads_remaining
[reg
] == 1) {
845 class vec4_instruction_scheduler
: public instruction_scheduler
848 vec4_instruction_scheduler(vec4_visitor
*v
, int grf_count
);
849 void calculate_deps();
850 schedule_node
*choose_instruction_to_schedule();
851 int issue_time(backend_instruction
*inst
);
854 void count_reads_remaining(backend_instruction
*inst
);
855 void setup_liveness(cfg_t
*cfg
);
856 void update_register_pressure(backend_instruction
*inst
);
857 int get_register_pressure_benefit(backend_instruction
*inst
);
860 vec4_instruction_scheduler::vec4_instruction_scheduler(vec4_visitor
*v
,
862 : instruction_scheduler(v
, grf_count
, 0, 0, SCHEDULE_POST
),
868 vec4_instruction_scheduler::count_reads_remaining(backend_instruction
*)
873 vec4_instruction_scheduler::setup_liveness(cfg_t
*)
878 vec4_instruction_scheduler::update_register_pressure(backend_instruction
*)
883 vec4_instruction_scheduler::get_register_pressure_benefit(backend_instruction
*)
888 schedule_node::schedule_node(backend_instruction
*inst
,
889 instruction_scheduler
*sched
)
891 const struct gen_device_info
*devinfo
= sched
->bs
->devinfo
;
894 this->child_array_size
= 0;
895 this->children
= NULL
;
896 this->child_latency
= NULL
;
897 this->child_count
= 0;
898 this->parent_count
= 0;
899 this->unblocked_time
= 0;
900 this->cand_generation
= 0;
904 /* We can't measure Gen6 timings directly but expect them to be much
905 * closer to Gen7 than Gen4.
907 if (!sched
->post_reg_alloc
)
909 else if (devinfo
->gen
>= 6)
910 set_latency_gen7(devinfo
->is_haswell
);
916 instruction_scheduler::add_insts_from_block(bblock_t
*block
)
918 foreach_inst_in_block(backend_instruction
, inst
, block
) {
919 schedule_node
*n
= new(mem_ctx
) schedule_node(inst
, this);
921 instructions
.push_tail(n
);
924 this->instructions_to_schedule
= block
->end_ip
- block
->start_ip
+ 1;
927 /** Computation of the delay member of each node. */
929 instruction_scheduler::compute_delays()
931 foreach_in_list_reverse(schedule_node
, n
, &instructions
) {
932 if (!n
->child_count
) {
933 n
->delay
= issue_time(n
->inst
);
935 for (int i
= 0; i
< n
->child_count
; i
++) {
936 assert(n
->children
[i
]->delay
);
937 n
->delay
= MAX2(n
->delay
, n
->latency
+ n
->children
[i
]->delay
);
944 instruction_scheduler::compute_exits()
946 /* Calculate a lower bound of the scheduling time of each node in the
947 * graph. This is analogous to the node's critical path but calculated
948 * from the top instead of from the bottom of the block.
950 foreach_in_list(schedule_node
, n
, &instructions
) {
951 for (int i
= 0; i
< n
->child_count
; i
++) {
952 n
->children
[i
]->unblocked_time
=
953 MAX2(n
->children
[i
]->unblocked_time
,
954 n
->unblocked_time
+ issue_time(n
->inst
) + n
->child_latency
[i
]);
958 /* Calculate the exit of each node by induction based on the exit nodes of
959 * its children. The preferred exit of a node is the one among the exit
960 * nodes of its children which can be unblocked first according to the
961 * optimistic unblocked time estimate calculated above.
963 foreach_in_list_reverse(schedule_node
, n
, &instructions
) {
964 n
->exit
= (n
->inst
->opcode
== FS_OPCODE_DISCARD_JUMP
? n
: NULL
);
966 for (int i
= 0; i
< n
->child_count
; i
++) {
967 if (exit_unblocked_time(n
->children
[i
]) < exit_unblocked_time(n
))
968 n
->exit
= n
->children
[i
]->exit
;
974 * Add a dependency between two instruction nodes.
976 * The @after node will be scheduled after @before. We will try to
977 * schedule it @latency cycles after @before, but no guarantees there.
980 instruction_scheduler::add_dep(schedule_node
*before
, schedule_node
*after
,
983 if (!before
|| !after
)
986 assert(before
!= after
);
988 for (int i
= 0; i
< before
->child_count
; i
++) {
989 if (before
->children
[i
] == after
) {
990 before
->child_latency
[i
] = MAX2(before
->child_latency
[i
], latency
);
995 if (before
->child_array_size
<= before
->child_count
) {
996 if (before
->child_array_size
< 16)
997 before
->child_array_size
= 16;
999 before
->child_array_size
*= 2;
1001 before
->children
= reralloc(mem_ctx
, before
->children
,
1003 before
->child_array_size
);
1004 before
->child_latency
= reralloc(mem_ctx
, before
->child_latency
,
1005 int, before
->child_array_size
);
1008 before
->children
[before
->child_count
] = after
;
1009 before
->child_latency
[before
->child_count
] = latency
;
1010 before
->child_count
++;
1011 after
->parent_count
++;
1015 instruction_scheduler::add_dep(schedule_node
*before
, schedule_node
*after
)
1020 add_dep(before
, after
, before
->latency
);
1024 is_scheduling_barrier(const backend_instruction
*inst
)
1026 return inst
->opcode
== FS_OPCODE_PLACEHOLDER_HALT
||
1027 inst
->is_control_flow() ||
1028 inst
->has_side_effects();
1032 * Sometimes we really want this node to execute after everything that
1033 * was before it and before everything that followed it. This adds
1034 * the deps to do so.
1037 instruction_scheduler::add_barrier_deps(schedule_node
*n
)
1039 schedule_node
*prev
= (schedule_node
*)n
->prev
;
1040 schedule_node
*next
= (schedule_node
*)n
->next
;
1043 while (!prev
->is_head_sentinel()) {
1044 add_dep(prev
, n
, 0);
1045 if (is_scheduling_barrier(prev
->inst
))
1047 prev
= (schedule_node
*)prev
->prev
;
1052 while (!next
->is_tail_sentinel()) {
1053 add_dep(n
, next
, 0);
1054 if (is_scheduling_barrier(next
->inst
))
1056 next
= (schedule_node
*)next
->next
;
1061 /* instruction scheduling needs to be aware of when an MRF write
1062 * actually writes 2 MRFs.
1065 fs_instruction_scheduler::is_compressed(fs_inst
*inst
)
1067 return inst
->exec_size
== 16;
1071 fs_instruction_scheduler::calculate_deps()
1073 /* Pre-register-allocation, this tracks the last write per VGRF offset.
1074 * After register allocation, reg_offsets are gone and we track individual
1077 schedule_node
**last_grf_write
;
1078 schedule_node
*last_mrf_write
[BRW_MAX_MRF(v
->devinfo
->gen
)];
1079 schedule_node
*last_conditional_mod
[8] = {};
1080 schedule_node
*last_accumulator_write
= NULL
;
1081 /* Fixed HW registers are assumed to be separate from the virtual
1082 * GRFs, so they can be tracked separately. We don't really write
1083 * to fixed GRFs much, so don't bother tracking them on a more
1086 schedule_node
*last_fixed_grf_write
= NULL
;
1088 last_grf_write
= (schedule_node
**)calloc(sizeof(schedule_node
*), grf_count
* 16);
1089 memset(last_mrf_write
, 0, sizeof(last_mrf_write
));
1091 /* top-to-bottom dependencies: RAW and WAW. */
1092 foreach_in_list(schedule_node
, n
, &instructions
) {
1093 fs_inst
*inst
= (fs_inst
*)n
->inst
;
1095 if (is_scheduling_barrier(inst
))
1096 add_barrier_deps(n
);
1098 /* read-after-write deps. */
1099 for (int i
= 0; i
< inst
->sources
; i
++) {
1100 if (inst
->src
[i
].file
== VGRF
) {
1101 if (post_reg_alloc
) {
1102 for (unsigned r
= 0; r
< regs_read(inst
, i
); r
++)
1103 add_dep(last_grf_write
[inst
->src
[i
].nr
+ r
], n
);
1105 for (unsigned r
= 0; r
< regs_read(inst
, i
); r
++) {
1106 add_dep(last_grf_write
[inst
->src
[i
].nr
* 16 +
1107 inst
->src
[i
].offset
/ REG_SIZE
+ r
], n
);
1110 } else if (inst
->src
[i
].file
== FIXED_GRF
) {
1111 if (post_reg_alloc
) {
1112 for (unsigned r
= 0; r
< regs_read(inst
, i
); r
++)
1113 add_dep(last_grf_write
[inst
->src
[i
].nr
+ r
], n
);
1115 add_dep(last_fixed_grf_write
, n
);
1117 } else if (inst
->src
[i
].is_accumulator()) {
1118 add_dep(last_accumulator_write
, n
);
1119 } else if (inst
->src
[i
].file
== ARF
) {
1120 add_barrier_deps(n
);
1124 if (inst
->base_mrf
!= -1) {
1125 for (int i
= 0; i
< inst
->mlen
; i
++) {
1126 /* It looks like the MRF regs are released in the send
1127 * instruction once it's sent, not when the result comes
1130 add_dep(last_mrf_write
[inst
->base_mrf
+ i
], n
);
1134 if (const unsigned mask
= inst
->flags_read(v
->devinfo
)) {
1135 assert(mask
< (1 << ARRAY_SIZE(last_conditional_mod
)));
1137 for (unsigned i
= 0; i
< ARRAY_SIZE(last_conditional_mod
); i
++) {
1138 if (mask
& (1 << i
))
1139 add_dep(last_conditional_mod
[i
], n
);
1143 if (inst
->reads_accumulator_implicitly()) {
1144 add_dep(last_accumulator_write
, n
);
1147 /* write-after-write deps. */
1148 if (inst
->dst
.file
== VGRF
) {
1149 if (post_reg_alloc
) {
1150 for (unsigned r
= 0; r
< regs_written(inst
); r
++) {
1151 add_dep(last_grf_write
[inst
->dst
.nr
+ r
], n
);
1152 last_grf_write
[inst
->dst
.nr
+ r
] = n
;
1155 for (unsigned r
= 0; r
< regs_written(inst
); r
++) {
1156 add_dep(last_grf_write
[inst
->dst
.nr
* 16 +
1157 inst
->dst
.offset
/ REG_SIZE
+ r
], n
);
1158 last_grf_write
[inst
->dst
.nr
* 16 +
1159 inst
->dst
.offset
/ REG_SIZE
+ r
] = n
;
1162 } else if (inst
->dst
.file
== MRF
) {
1163 int reg
= inst
->dst
.nr
& ~BRW_MRF_COMPR4
;
1165 add_dep(last_mrf_write
[reg
], n
);
1166 last_mrf_write
[reg
] = n
;
1167 if (is_compressed(inst
)) {
1168 if (inst
->dst
.nr
& BRW_MRF_COMPR4
)
1172 add_dep(last_mrf_write
[reg
], n
);
1173 last_mrf_write
[reg
] = n
;
1175 } else if (inst
->dst
.file
== FIXED_GRF
) {
1176 if (post_reg_alloc
) {
1177 for (unsigned r
= 0; r
< regs_written(inst
); r
++)
1178 last_grf_write
[inst
->dst
.nr
+ r
] = n
;
1180 last_fixed_grf_write
= n
;
1182 } else if (inst
->dst
.is_accumulator()) {
1183 add_dep(last_accumulator_write
, n
);
1184 last_accumulator_write
= n
;
1185 } else if (inst
->dst
.file
== ARF
&& !inst
->dst
.is_null()) {
1186 add_barrier_deps(n
);
1189 if (inst
->mlen
> 0 && inst
->base_mrf
!= -1) {
1190 for (int i
= 0; i
< v
->implied_mrf_writes(inst
); i
++) {
1191 add_dep(last_mrf_write
[inst
->base_mrf
+ i
], n
);
1192 last_mrf_write
[inst
->base_mrf
+ i
] = n
;
1196 if (const unsigned mask
= inst
->flags_written()) {
1197 assert(mask
< (1 << ARRAY_SIZE(last_conditional_mod
)));
1199 for (unsigned i
= 0; i
< ARRAY_SIZE(last_conditional_mod
); i
++) {
1200 if (mask
& (1 << i
)) {
1201 add_dep(last_conditional_mod
[i
], n
, 0);
1202 last_conditional_mod
[i
] = n
;
1207 if (inst
->writes_accumulator_implicitly(v
->devinfo
) &&
1208 !inst
->dst
.is_accumulator()) {
1209 add_dep(last_accumulator_write
, n
);
1210 last_accumulator_write
= n
;
1214 /* bottom-to-top dependencies: WAR */
1215 memset(last_grf_write
, 0, sizeof(schedule_node
*) * grf_count
* 16);
1216 memset(last_mrf_write
, 0, sizeof(last_mrf_write
));
1217 memset(last_conditional_mod
, 0, sizeof(last_conditional_mod
));
1218 last_accumulator_write
= NULL
;
1219 last_fixed_grf_write
= NULL
;
1221 foreach_in_list_reverse_safe(schedule_node
, n
, &instructions
) {
1222 fs_inst
*inst
= (fs_inst
*)n
->inst
;
1224 /* write-after-read deps. */
1225 for (int i
= 0; i
< inst
->sources
; i
++) {
1226 if (inst
->src
[i
].file
== VGRF
) {
1227 if (post_reg_alloc
) {
1228 for (unsigned r
= 0; r
< regs_read(inst
, i
); r
++)
1229 add_dep(n
, last_grf_write
[inst
->src
[i
].nr
+ r
], 0);
1231 for (unsigned r
= 0; r
< regs_read(inst
, i
); r
++) {
1232 add_dep(n
, last_grf_write
[inst
->src
[i
].nr
* 16 +
1233 inst
->src
[i
].offset
/ REG_SIZE
+ r
], 0);
1236 } else if (inst
->src
[i
].file
== FIXED_GRF
) {
1237 if (post_reg_alloc
) {
1238 for (unsigned r
= 0; r
< regs_read(inst
, i
); r
++)
1239 add_dep(n
, last_grf_write
[inst
->src
[i
].nr
+ r
], 0);
1241 add_dep(n
, last_fixed_grf_write
, 0);
1243 } else if (inst
->src
[i
].is_accumulator()) {
1244 add_dep(n
, last_accumulator_write
, 0);
1245 } else if (inst
->src
[i
].file
== ARF
) {
1246 add_barrier_deps(n
);
1250 if (inst
->base_mrf
!= -1) {
1251 for (int i
= 0; i
< inst
->mlen
; i
++) {
1252 /* It looks like the MRF regs are released in the send
1253 * instruction once it's sent, not when the result comes
1256 add_dep(n
, last_mrf_write
[inst
->base_mrf
+ i
], 2);
1260 if (const unsigned mask
= inst
->flags_read(v
->devinfo
)) {
1261 assert(mask
< (1 << ARRAY_SIZE(last_conditional_mod
)));
1263 for (unsigned i
= 0; i
< ARRAY_SIZE(last_conditional_mod
); i
++) {
1264 if (mask
& (1 << i
))
1265 add_dep(n
, last_conditional_mod
[i
]);
1269 if (inst
->reads_accumulator_implicitly()) {
1270 add_dep(n
, last_accumulator_write
);
1273 /* Update the things this instruction wrote, so earlier reads
1274 * can mark this as WAR dependency.
1276 if (inst
->dst
.file
== VGRF
) {
1277 if (post_reg_alloc
) {
1278 for (unsigned r
= 0; r
< regs_written(inst
); r
++)
1279 last_grf_write
[inst
->dst
.nr
+ r
] = n
;
1281 for (unsigned r
= 0; r
< regs_written(inst
); r
++) {
1282 last_grf_write
[inst
->dst
.nr
* 16 +
1283 inst
->dst
.offset
/ REG_SIZE
+ r
] = n
;
1286 } else if (inst
->dst
.file
== MRF
) {
1287 int reg
= inst
->dst
.nr
& ~BRW_MRF_COMPR4
;
1289 last_mrf_write
[reg
] = n
;
1291 if (is_compressed(inst
)) {
1292 if (inst
->dst
.nr
& BRW_MRF_COMPR4
)
1297 last_mrf_write
[reg
] = n
;
1299 } else if (inst
->dst
.file
== FIXED_GRF
) {
1300 if (post_reg_alloc
) {
1301 for (unsigned r
= 0; r
< regs_written(inst
); r
++)
1302 last_grf_write
[inst
->dst
.nr
+ r
] = n
;
1304 last_fixed_grf_write
= n
;
1306 } else if (inst
->dst
.is_accumulator()) {
1307 last_accumulator_write
= n
;
1308 } else if (inst
->dst
.file
== ARF
&& !inst
->dst
.is_null()) {
1309 add_barrier_deps(n
);
1312 if (inst
->mlen
> 0 && inst
->base_mrf
!= -1) {
1313 for (int i
= 0; i
< v
->implied_mrf_writes(inst
); i
++) {
1314 last_mrf_write
[inst
->base_mrf
+ i
] = n
;
1318 if (const unsigned mask
= inst
->flags_written()) {
1319 assert(mask
< (1 << ARRAY_SIZE(last_conditional_mod
)));
1321 for (unsigned i
= 0; i
< ARRAY_SIZE(last_conditional_mod
); i
++) {
1322 if (mask
& (1 << i
))
1323 last_conditional_mod
[i
] = n
;
1327 if (inst
->writes_accumulator_implicitly(v
->devinfo
)) {
1328 last_accumulator_write
= n
;
1332 free(last_grf_write
);
1336 vec4_instruction_scheduler::calculate_deps()
1338 schedule_node
*last_grf_write
[grf_count
];
1339 schedule_node
*last_mrf_write
[BRW_MAX_MRF(v
->devinfo
->gen
)];
1340 schedule_node
*last_conditional_mod
= NULL
;
1341 schedule_node
*last_accumulator_write
= NULL
;
1342 /* Fixed HW registers are assumed to be separate from the virtual
1343 * GRFs, so they can be tracked separately. We don't really write
1344 * to fixed GRFs much, so don't bother tracking them on a more
1347 schedule_node
*last_fixed_grf_write
= NULL
;
1349 memset(last_grf_write
, 0, sizeof(last_grf_write
));
1350 memset(last_mrf_write
, 0, sizeof(last_mrf_write
));
1352 /* top-to-bottom dependencies: RAW and WAW. */
1353 foreach_in_list(schedule_node
, n
, &instructions
) {
1354 vec4_instruction
*inst
= (vec4_instruction
*)n
->inst
;
1356 if (is_scheduling_barrier(inst
))
1357 add_barrier_deps(n
);
1359 /* read-after-write deps. */
1360 for (int i
= 0; i
< 3; i
++) {
1361 if (inst
->src
[i
].file
== VGRF
) {
1362 for (unsigned j
= 0; j
< regs_read(inst
, i
); ++j
)
1363 add_dep(last_grf_write
[inst
->src
[i
].nr
+ j
], n
);
1364 } else if (inst
->src
[i
].file
== FIXED_GRF
) {
1365 add_dep(last_fixed_grf_write
, n
);
1366 } else if (inst
->src
[i
].is_accumulator()) {
1367 assert(last_accumulator_write
);
1368 add_dep(last_accumulator_write
, n
);
1369 } else if (inst
->src
[i
].file
== ARF
) {
1370 add_barrier_deps(n
);
1374 if (inst
->reads_g0_implicitly())
1375 add_dep(last_fixed_grf_write
, n
);
1377 if (!inst
->is_send_from_grf()) {
1378 for (int i
= 0; i
< inst
->mlen
; i
++) {
1379 /* It looks like the MRF regs are released in the send
1380 * instruction once it's sent, not when the result comes
1383 add_dep(last_mrf_write
[inst
->base_mrf
+ i
], n
);
1387 if (inst
->reads_flag()) {
1388 assert(last_conditional_mod
);
1389 add_dep(last_conditional_mod
, n
);
1392 if (inst
->reads_accumulator_implicitly()) {
1393 assert(last_accumulator_write
);
1394 add_dep(last_accumulator_write
, n
);
1397 /* write-after-write deps. */
1398 if (inst
->dst
.file
== VGRF
) {
1399 for (unsigned j
= 0; j
< regs_written(inst
); ++j
) {
1400 add_dep(last_grf_write
[inst
->dst
.nr
+ j
], n
);
1401 last_grf_write
[inst
->dst
.nr
+ j
] = n
;
1403 } else if (inst
->dst
.file
== MRF
) {
1404 add_dep(last_mrf_write
[inst
->dst
.nr
], n
);
1405 last_mrf_write
[inst
->dst
.nr
] = n
;
1406 } else if (inst
->dst
.file
== FIXED_GRF
) {
1407 last_fixed_grf_write
= n
;
1408 } else if (inst
->dst
.is_accumulator()) {
1409 add_dep(last_accumulator_write
, n
);
1410 last_accumulator_write
= n
;
1411 } else if (inst
->dst
.file
== ARF
&& !inst
->dst
.is_null()) {
1412 add_barrier_deps(n
);
1415 if (inst
->mlen
> 0 && !inst
->is_send_from_grf()) {
1416 for (int i
= 0; i
< v
->implied_mrf_writes(inst
); i
++) {
1417 add_dep(last_mrf_write
[inst
->base_mrf
+ i
], n
);
1418 last_mrf_write
[inst
->base_mrf
+ i
] = n
;
1422 if (inst
->writes_flag()) {
1423 add_dep(last_conditional_mod
, n
, 0);
1424 last_conditional_mod
= n
;
1427 if (inst
->writes_accumulator_implicitly(v
->devinfo
) &&
1428 !inst
->dst
.is_accumulator()) {
1429 add_dep(last_accumulator_write
, n
);
1430 last_accumulator_write
= n
;
1434 /* bottom-to-top dependencies: WAR */
1435 memset(last_grf_write
, 0, sizeof(last_grf_write
));
1436 memset(last_mrf_write
, 0, sizeof(last_mrf_write
));
1437 last_conditional_mod
= NULL
;
1438 last_accumulator_write
= NULL
;
1439 last_fixed_grf_write
= NULL
;
1441 foreach_in_list_reverse_safe(schedule_node
, n
, &instructions
) {
1442 vec4_instruction
*inst
= (vec4_instruction
*)n
->inst
;
1444 /* write-after-read deps. */
1445 for (int i
= 0; i
< 3; i
++) {
1446 if (inst
->src
[i
].file
== VGRF
) {
1447 for (unsigned j
= 0; j
< regs_read(inst
, i
); ++j
)
1448 add_dep(n
, last_grf_write
[inst
->src
[i
].nr
+ j
]);
1449 } else if (inst
->src
[i
].file
== FIXED_GRF
) {
1450 add_dep(n
, last_fixed_grf_write
);
1451 } else if (inst
->src
[i
].is_accumulator()) {
1452 add_dep(n
, last_accumulator_write
);
1453 } else if (inst
->src
[i
].file
== ARF
) {
1454 add_barrier_deps(n
);
1458 if (!inst
->is_send_from_grf()) {
1459 for (int i
= 0; i
< inst
->mlen
; i
++) {
1460 /* It looks like the MRF regs are released in the send
1461 * instruction once it's sent, not when the result comes
1464 add_dep(n
, last_mrf_write
[inst
->base_mrf
+ i
], 2);
1468 if (inst
->reads_flag()) {
1469 add_dep(n
, last_conditional_mod
);
1472 if (inst
->reads_accumulator_implicitly()) {
1473 add_dep(n
, last_accumulator_write
);
1476 /* Update the things this instruction wrote, so earlier reads
1477 * can mark this as WAR dependency.
1479 if (inst
->dst
.file
== VGRF
) {
1480 for (unsigned j
= 0; j
< regs_written(inst
); ++j
)
1481 last_grf_write
[inst
->dst
.nr
+ j
] = n
;
1482 } else if (inst
->dst
.file
== MRF
) {
1483 last_mrf_write
[inst
->dst
.nr
] = n
;
1484 } else if (inst
->dst
.file
== FIXED_GRF
) {
1485 last_fixed_grf_write
= n
;
1486 } else if (inst
->dst
.is_accumulator()) {
1487 last_accumulator_write
= n
;
1488 } else if (inst
->dst
.file
== ARF
&& !inst
->dst
.is_null()) {
1489 add_barrier_deps(n
);
1492 if (inst
->mlen
> 0 && !inst
->is_send_from_grf()) {
1493 for (int i
= 0; i
< v
->implied_mrf_writes(inst
); i
++) {
1494 last_mrf_write
[inst
->base_mrf
+ i
] = n
;
1498 if (inst
->writes_flag()) {
1499 last_conditional_mod
= n
;
1502 if (inst
->writes_accumulator_implicitly(v
->devinfo
)) {
1503 last_accumulator_write
= n
;
1509 fs_instruction_scheduler::choose_instruction_to_schedule()
1511 schedule_node
*chosen
= NULL
;
1513 if (mode
== SCHEDULE_PRE
|| mode
== SCHEDULE_POST
) {
1514 int chosen_time
= 0;
1516 /* Of the instructions ready to execute or the closest to being ready,
1517 * choose the one most likely to unblock an early program exit, or
1518 * otherwise the oldest one.
1520 foreach_in_list(schedule_node
, n
, &instructions
) {
1522 exit_unblocked_time(n
) < exit_unblocked_time(chosen
) ||
1523 (exit_unblocked_time(n
) == exit_unblocked_time(chosen
) &&
1524 n
->unblocked_time
< chosen_time
)) {
1526 chosen_time
= n
->unblocked_time
;
1530 /* Before register allocation, we don't care about the latencies of
1531 * instructions. All we care about is reducing live intervals of
1532 * variables so that we can avoid register spilling, or get SIMD16
1533 * shaders which naturally do a better job of hiding instruction
1536 foreach_in_list(schedule_node
, n
, &instructions
) {
1537 fs_inst
*inst
= (fs_inst
*)n
->inst
;
1544 /* Most important: If we can definitely reduce register pressure, do
1547 int register_pressure_benefit
= get_register_pressure_benefit(n
->inst
);
1548 int chosen_register_pressure_benefit
=
1549 get_register_pressure_benefit(chosen
->inst
);
1551 if (register_pressure_benefit
> 0 &&
1552 register_pressure_benefit
> chosen_register_pressure_benefit
) {
1555 } else if (chosen_register_pressure_benefit
> 0 &&
1556 (register_pressure_benefit
<
1557 chosen_register_pressure_benefit
)) {
1561 if (mode
== SCHEDULE_PRE_LIFO
) {
1562 /* Prefer instructions that recently became available for
1563 * scheduling. These are the things that are most likely to
1564 * (eventually) make a variable dead and reduce register pressure.
1565 * Typical register pressure estimates don't work for us because
1566 * most of our pressure comes from texturing, where no single
1567 * instruction to schedule will make a vec4 value dead.
1569 if (n
->cand_generation
> chosen
->cand_generation
) {
1572 } else if (n
->cand_generation
< chosen
->cand_generation
) {
1576 /* On MRF-using chips, prefer non-SEND instructions. If we don't
1577 * do this, then because we prefer instructions that just became
1578 * candidates, we'll end up in a pattern of scheduling a SEND,
1579 * then the MRFs for the next SEND, then the next SEND, then the
1580 * MRFs, etc., without ever consuming the results of a send.
1582 if (v
->devinfo
->gen
< 7) {
1583 fs_inst
*chosen_inst
= (fs_inst
*)chosen
->inst
;
1585 /* We use size_written > 4 * exec_size as our test for the kind
1586 * of send instruction to avoid -- only sends generate many
1587 * regs, and a single-result send is probably actually reducing
1588 * register pressure.
1590 if (inst
->size_written
<= 4 * inst
->exec_size
&&
1591 chosen_inst
->size_written
> 4 * chosen_inst
->exec_size
) {
1594 } else if (inst
->size_written
> chosen_inst
->size_written
) {
1600 /* For instructions pushed on the cands list at the same time, prefer
1601 * the one with the highest delay to the end of the program. This is
1602 * most likely to have its values able to be consumed first (such as
1603 * for a large tree of lowered ubo loads, which appear reversed in
1604 * the instruction stream with respect to when they can be consumed).
1606 if (n
->delay
> chosen
->delay
) {
1609 } else if (n
->delay
< chosen
->delay
) {
1613 /* Prefer the node most likely to unblock an early program exit.
1615 if (exit_unblocked_time(n
) < exit_unblocked_time(chosen
)) {
1618 } else if (exit_unblocked_time(n
) > exit_unblocked_time(chosen
)) {
1622 /* If all other metrics are equal, we prefer the first instruction in
1623 * the list (program execution).
1632 vec4_instruction_scheduler::choose_instruction_to_schedule()
1634 schedule_node
*chosen
= NULL
;
1635 int chosen_time
= 0;
1637 /* Of the instructions ready to execute or the closest to being ready,
1638 * choose the oldest one.
1640 foreach_in_list(schedule_node
, n
, &instructions
) {
1641 if (!chosen
|| n
->unblocked_time
< chosen_time
) {
1643 chosen_time
= n
->unblocked_time
;
1651 fs_instruction_scheduler::issue_time(backend_instruction
*inst
)
1653 const unsigned overhead
= v
->bank_conflict_cycles((fs_inst
*)inst
);
1654 if (is_compressed((fs_inst
*)inst
))
1655 return 4 + overhead
;
1657 return 2 + overhead
;
1661 vec4_instruction_scheduler::issue_time(backend_instruction
*)
1663 /* We always execute as two vec4s in parallel. */
1668 instruction_scheduler::schedule_instructions(bblock_t
*block
)
1670 const struct gen_device_info
*devinfo
= bs
->devinfo
;
1672 if (!post_reg_alloc
)
1673 reg_pressure
= reg_pressure_in
[block
->num
];
1674 block_idx
= block
->num
;
1676 /* Remove non-DAG heads from the list. */
1677 foreach_in_list_safe(schedule_node
, n
, &instructions
) {
1678 if (n
->parent_count
!= 0)
1682 unsigned cand_generation
= 1;
1683 while (!instructions
.is_empty()) {
1684 schedule_node
*chosen
= choose_instruction_to_schedule();
1686 /* Schedule this instruction. */
1689 chosen
->inst
->exec_node::remove();
1690 block
->instructions
.push_tail(chosen
->inst
);
1691 instructions_to_schedule
--;
1693 if (!post_reg_alloc
) {
1694 reg_pressure
-= get_register_pressure_benefit(chosen
->inst
);
1695 update_register_pressure(chosen
->inst
);
1698 /* If we expected a delay for scheduling, then bump the clock to reflect
1699 * that. In reality, the hardware will switch to another hyperthread
1700 * and may not return to dispatching our thread for a while even after
1701 * we're unblocked. After this, we have the time when the chosen
1702 * instruction will start executing.
1704 time
= MAX2(time
, chosen
->unblocked_time
);
1706 /* Update the clock for how soon an instruction could start after the
1709 time
+= issue_time(chosen
->inst
);
1712 fprintf(stderr
, "clock %4d, scheduled: ", time
);
1713 bs
->dump_instruction(chosen
->inst
);
1714 if (!post_reg_alloc
)
1715 fprintf(stderr
, "(register pressure %d)\n", reg_pressure
);
1718 /* Now that we've scheduled a new instruction, some of its
1719 * children can be promoted to the list of instructions ready to
1720 * be scheduled. Update the children's unblocked time for this
1721 * DAG edge as we do so.
1723 for (int i
= chosen
->child_count
- 1; i
>= 0; i
--) {
1724 schedule_node
*child
= chosen
->children
[i
];
1726 child
->unblocked_time
= MAX2(child
->unblocked_time
,
1727 time
+ chosen
->child_latency
[i
]);
1730 fprintf(stderr
, "\tchild %d, %d parents: ", i
, child
->parent_count
);
1731 bs
->dump_instruction(child
->inst
);
1734 child
->cand_generation
= cand_generation
;
1735 child
->parent_count
--;
1736 if (child
->parent_count
== 0) {
1738 fprintf(stderr
, "\t\tnow available\n");
1740 instructions
.push_head(child
);
1745 /* Shared resource: the mathbox. There's one mathbox per EU on Gen6+
1746 * but it's more limited pre-gen6, so if we send something off to it then
1747 * the next math instruction isn't going to make progress until the first
1750 if (devinfo
->gen
< 6 && chosen
->inst
->is_math()) {
1751 foreach_in_list(schedule_node
, n
, &instructions
) {
1752 if (n
->inst
->is_math())
1753 n
->unblocked_time
= MAX2(n
->unblocked_time
,
1754 time
+ chosen
->latency
);
1759 assert(instructions_to_schedule
== 0);
1761 block
->cycle_count
= time
;
1764 static unsigned get_cycle_count(cfg_t
*cfg
)
1766 unsigned count
= 0, multiplier
= 1;
1767 foreach_block(block
, cfg
) {
1768 if (block
->start()->opcode
== BRW_OPCODE_DO
)
1769 multiplier
*= 10; /* assume that loops execute ~10 times */
1771 count
+= block
->cycle_count
* multiplier
;
1773 if (block
->end()->opcode
== BRW_OPCODE_WHILE
)
1781 instruction_scheduler::run(cfg_t
*cfg
)
1783 if (debug
&& !post_reg_alloc
) {
1784 fprintf(stderr
, "\nInstructions before scheduling (reg_alloc %d)\n",
1786 bs
->dump_instructions();
1789 if (!post_reg_alloc
)
1790 setup_liveness(cfg
);
1792 foreach_block(block
, cfg
) {
1793 if (reads_remaining
) {
1794 memset(reads_remaining
, 0,
1795 grf_count
* sizeof(*reads_remaining
));
1796 memset(hw_reads_remaining
, 0,
1797 hw_reg_count
* sizeof(*hw_reads_remaining
));
1798 memset(written
, 0, grf_count
* sizeof(*written
));
1800 foreach_inst_in_block(fs_inst
, inst
, block
)
1801 count_reads_remaining(inst
);
1804 add_insts_from_block(block
);
1811 schedule_instructions(block
);
1814 if (debug
&& !post_reg_alloc
) {
1815 fprintf(stderr
, "\nInstructions after scheduling (reg_alloc %d)\n",
1817 bs
->dump_instructions();
1820 cfg
->cycle_count
= get_cycle_count(cfg
);
1824 fs_visitor::schedule_instructions(instruction_scheduler_mode mode
)
1826 if (mode
!= SCHEDULE_POST
)
1827 calculate_live_intervals();
1830 if (mode
== SCHEDULE_POST
)
1831 grf_count
= grf_used
;
1833 grf_count
= alloc
.count
;
1835 fs_instruction_scheduler
sched(this, grf_count
, first_non_payload_grf
,
1836 cfg
->num_blocks
, mode
);
1839 invalidate_live_intervals();
1843 vec4_visitor::opt_schedule_instructions()
1845 vec4_instruction_scheduler
sched(this, prog_data
->total_grf
);
1848 invalidate_live_intervals();