2 * Copyright © 2010 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
28 #include "brw_vec4_tes.h"
29 #include "dev/gen_debug.h"
30 #include "main/uniforms.h"
31 #include "util/macros.h"
34 brw_type_for_base_type(const struct glsl_type
*type
)
36 switch (type
->base_type
) {
37 case GLSL_TYPE_FLOAT16
:
38 return BRW_REGISTER_TYPE_HF
;
40 return BRW_REGISTER_TYPE_F
;
43 case GLSL_TYPE_SUBROUTINE
:
44 return BRW_REGISTER_TYPE_D
;
46 return BRW_REGISTER_TYPE_W
;
48 return BRW_REGISTER_TYPE_B
;
50 return BRW_REGISTER_TYPE_UD
;
51 case GLSL_TYPE_UINT16
:
52 return BRW_REGISTER_TYPE_UW
;
54 return BRW_REGISTER_TYPE_UB
;
56 return brw_type_for_base_type(type
->fields
.array
);
57 case GLSL_TYPE_STRUCT
:
58 case GLSL_TYPE_INTERFACE
:
59 case GLSL_TYPE_SAMPLER
:
60 case GLSL_TYPE_ATOMIC_UINT
:
61 /* These should be overridden with the type of the member when
62 * dereferenced into. BRW_REGISTER_TYPE_UD seems like a likely
63 * way to trip up if we don't.
65 return BRW_REGISTER_TYPE_UD
;
67 return BRW_REGISTER_TYPE_UD
;
68 case GLSL_TYPE_DOUBLE
:
69 return BRW_REGISTER_TYPE_DF
;
70 case GLSL_TYPE_UINT64
:
71 return BRW_REGISTER_TYPE_UQ
;
73 return BRW_REGISTER_TYPE_Q
;
76 case GLSL_TYPE_FUNCTION
:
77 unreachable("not reached");
80 return BRW_REGISTER_TYPE_F
;
83 enum brw_conditional_mod
84 brw_conditional_for_comparison(unsigned int op
)
88 return BRW_CONDITIONAL_L
;
90 return BRW_CONDITIONAL_GE
;
92 case ir_binop_all_equal
: /* same as equal for scalars */
93 return BRW_CONDITIONAL_Z
;
95 case ir_binop_any_nequal
: /* same as nequal for scalars */
96 return BRW_CONDITIONAL_NZ
;
98 unreachable("not reached: bad operation for comparison");
103 brw_math_function(enum opcode op
)
106 case SHADER_OPCODE_RCP
:
107 return BRW_MATH_FUNCTION_INV
;
108 case SHADER_OPCODE_RSQ
:
109 return BRW_MATH_FUNCTION_RSQ
;
110 case SHADER_OPCODE_SQRT
:
111 return BRW_MATH_FUNCTION_SQRT
;
112 case SHADER_OPCODE_EXP2
:
113 return BRW_MATH_FUNCTION_EXP
;
114 case SHADER_OPCODE_LOG2
:
115 return BRW_MATH_FUNCTION_LOG
;
116 case SHADER_OPCODE_POW
:
117 return BRW_MATH_FUNCTION_POW
;
118 case SHADER_OPCODE_SIN
:
119 return BRW_MATH_FUNCTION_SIN
;
120 case SHADER_OPCODE_COS
:
121 return BRW_MATH_FUNCTION_COS
;
122 case SHADER_OPCODE_INT_QUOTIENT
:
123 return BRW_MATH_FUNCTION_INT_DIV_QUOTIENT
;
124 case SHADER_OPCODE_INT_REMAINDER
:
125 return BRW_MATH_FUNCTION_INT_DIV_REMAINDER
;
127 unreachable("not reached: unknown math function");
132 brw_texture_offset(const nir_tex_instr
*tex
, unsigned src
,
133 uint32_t *offset_bits_out
)
135 if (!nir_src_is_const(tex
->src
[src
].src
))
138 const unsigned num_components
= nir_tex_instr_src_size(tex
, src
);
140 /* Combine all three offsets into a single unsigned dword:
142 * bits 11:8 - U Offset (X component)
143 * bits 7:4 - V Offset (Y component)
144 * bits 3:0 - R Offset (Z component)
146 uint32_t offset_bits
= 0;
147 for (unsigned i
= 0; i
< num_components
; i
++) {
148 int offset
= nir_src_comp_as_int(tex
->src
[src
].src
, i
);
150 /* offset out of bounds; caller will handle it. */
151 if (offset
> 7 || offset
< -8)
154 const unsigned shift
= 4 * (2 - i
);
155 offset_bits
|= (offset
<< shift
) & (0xF << shift
);
158 *offset_bits_out
= offset_bits
;
164 brw_instruction_name(const struct gen_device_info
*devinfo
, enum opcode op
)
167 case 0 ... NUM_BRW_OPCODES
- 1:
168 /* The DO instruction doesn't exist on Gen6+, but we use it to mark the
169 * start of a loop in the IR.
171 if (devinfo
->gen
>= 6 && op
== BRW_OPCODE_DO
)
174 /* The following conversion opcodes doesn't exist on Gen8+, but we use
175 * then to mark that we want to do the conversion.
177 if (devinfo
->gen
> 7 && op
== BRW_OPCODE_F32TO16
)
180 if (devinfo
->gen
> 7 && op
== BRW_OPCODE_F16TO32
)
183 assert(brw_opcode_desc(devinfo
, op
)->name
);
184 return brw_opcode_desc(devinfo
, op
)->name
;
185 case FS_OPCODE_FB_WRITE
:
187 case FS_OPCODE_FB_WRITE_LOGICAL
:
188 return "fb_write_logical";
189 case FS_OPCODE_REP_FB_WRITE
:
190 return "rep_fb_write";
191 case FS_OPCODE_FB_READ
:
193 case FS_OPCODE_FB_READ_LOGICAL
:
194 return "fb_read_logical";
196 case SHADER_OPCODE_RCP
:
198 case SHADER_OPCODE_RSQ
:
200 case SHADER_OPCODE_SQRT
:
202 case SHADER_OPCODE_EXP2
:
204 case SHADER_OPCODE_LOG2
:
206 case SHADER_OPCODE_POW
:
208 case SHADER_OPCODE_INT_QUOTIENT
:
210 case SHADER_OPCODE_INT_REMAINDER
:
212 case SHADER_OPCODE_SIN
:
214 case SHADER_OPCODE_COS
:
217 case SHADER_OPCODE_SEND
:
220 case SHADER_OPCODE_UNDEF
:
223 case SHADER_OPCODE_TEX
:
225 case SHADER_OPCODE_TEX_LOGICAL
:
226 return "tex_logical";
227 case SHADER_OPCODE_TXD
:
229 case SHADER_OPCODE_TXD_LOGICAL
:
230 return "txd_logical";
231 case SHADER_OPCODE_TXF
:
233 case SHADER_OPCODE_TXF_LOGICAL
:
234 return "txf_logical";
235 case SHADER_OPCODE_TXF_LZ
:
237 case SHADER_OPCODE_TXL
:
239 case SHADER_OPCODE_TXL_LOGICAL
:
240 return "txl_logical";
241 case SHADER_OPCODE_TXL_LZ
:
243 case SHADER_OPCODE_TXS
:
245 case SHADER_OPCODE_TXS_LOGICAL
:
246 return "txs_logical";
249 case FS_OPCODE_TXB_LOGICAL
:
250 return "txb_logical";
251 case SHADER_OPCODE_TXF_CMS
:
253 case SHADER_OPCODE_TXF_CMS_LOGICAL
:
254 return "txf_cms_logical";
255 case SHADER_OPCODE_TXF_CMS_W
:
257 case SHADER_OPCODE_TXF_CMS_W_LOGICAL
:
258 return "txf_cms_w_logical";
259 case SHADER_OPCODE_TXF_UMS
:
261 case SHADER_OPCODE_TXF_UMS_LOGICAL
:
262 return "txf_ums_logical";
263 case SHADER_OPCODE_TXF_MCS
:
265 case SHADER_OPCODE_TXF_MCS_LOGICAL
:
266 return "txf_mcs_logical";
267 case SHADER_OPCODE_LOD
:
269 case SHADER_OPCODE_LOD_LOGICAL
:
270 return "lod_logical";
271 case SHADER_OPCODE_TG4
:
273 case SHADER_OPCODE_TG4_LOGICAL
:
274 return "tg4_logical";
275 case SHADER_OPCODE_TG4_OFFSET
:
277 case SHADER_OPCODE_TG4_OFFSET_LOGICAL
:
278 return "tg4_offset_logical";
279 case SHADER_OPCODE_SAMPLEINFO
:
281 case SHADER_OPCODE_SAMPLEINFO_LOGICAL
:
282 return "sampleinfo_logical";
284 case SHADER_OPCODE_IMAGE_SIZE_LOGICAL
:
285 return "image_size_logical";
287 case SHADER_OPCODE_SHADER_TIME_ADD
:
288 return "shader_time_add";
290 case VEC4_OPCODE_UNTYPED_ATOMIC
:
291 return "untyped_atomic";
292 case SHADER_OPCODE_UNTYPED_ATOMIC_LOGICAL
:
293 return "untyped_atomic_logical";
294 case SHADER_OPCODE_UNTYPED_ATOMIC_FLOAT_LOGICAL
:
295 return "untyped_atomic_float_logical";
296 case VEC4_OPCODE_UNTYPED_SURFACE_READ
:
297 return "untyped_surface_read";
298 case SHADER_OPCODE_UNTYPED_SURFACE_READ_LOGICAL
:
299 return "untyped_surface_read_logical";
300 case VEC4_OPCODE_UNTYPED_SURFACE_WRITE
:
301 return "untyped_surface_write";
302 case SHADER_OPCODE_UNTYPED_SURFACE_WRITE_LOGICAL
:
303 return "untyped_surface_write_logical";
304 case SHADER_OPCODE_A64_UNTYPED_READ_LOGICAL
:
305 return "a64_untyped_read_logical";
306 case SHADER_OPCODE_A64_UNTYPED_WRITE_LOGICAL
:
307 return "a64_untyped_write_logical";
308 case SHADER_OPCODE_A64_BYTE_SCATTERED_READ_LOGICAL
:
309 return "a64_byte_scattered_read_logical";
310 case SHADER_OPCODE_A64_BYTE_SCATTERED_WRITE_LOGICAL
:
311 return "a64_byte_scattered_write_logical";
312 case SHADER_OPCODE_A64_UNTYPED_ATOMIC_LOGICAL
:
313 return "a64_untyped_atomic_logical";
314 case SHADER_OPCODE_A64_UNTYPED_ATOMIC_INT64_LOGICAL
:
315 return "a64_untyped_atomic_int64_logical";
316 case SHADER_OPCODE_A64_UNTYPED_ATOMIC_FLOAT_LOGICAL
:
317 return "a64_untyped_atomic_float_logical";
318 case SHADER_OPCODE_TYPED_ATOMIC_LOGICAL
:
319 return "typed_atomic_logical";
320 case SHADER_OPCODE_TYPED_SURFACE_READ_LOGICAL
:
321 return "typed_surface_read_logical";
322 case SHADER_OPCODE_TYPED_SURFACE_WRITE_LOGICAL
:
323 return "typed_surface_write_logical";
324 case SHADER_OPCODE_MEMORY_FENCE
:
325 return "memory_fence";
326 case FS_OPCODE_SCHEDULING_FENCE
:
327 return "scheduling_fence";
328 case SHADER_OPCODE_INTERLOCK
:
329 /* For an interlock we actually issue a memory fence via sendc. */
332 case SHADER_OPCODE_BYTE_SCATTERED_READ_LOGICAL
:
333 return "byte_scattered_read_logical";
334 case SHADER_OPCODE_BYTE_SCATTERED_WRITE_LOGICAL
:
335 return "byte_scattered_write_logical";
336 case SHADER_OPCODE_DWORD_SCATTERED_READ_LOGICAL
:
337 return "dword_scattered_read_logical";
338 case SHADER_OPCODE_DWORD_SCATTERED_WRITE_LOGICAL
:
339 return "dword_scattered_write_logical";
341 case SHADER_OPCODE_LOAD_PAYLOAD
:
342 return "load_payload";
346 case SHADER_OPCODE_GEN4_SCRATCH_READ
:
347 return "gen4_scratch_read";
348 case SHADER_OPCODE_GEN4_SCRATCH_WRITE
:
349 return "gen4_scratch_write";
350 case SHADER_OPCODE_GEN7_SCRATCH_READ
:
351 return "gen7_scratch_read";
352 case SHADER_OPCODE_URB_WRITE_SIMD8
:
353 return "gen8_urb_write_simd8";
354 case SHADER_OPCODE_URB_WRITE_SIMD8_PER_SLOT
:
355 return "gen8_urb_write_simd8_per_slot";
356 case SHADER_OPCODE_URB_WRITE_SIMD8_MASKED
:
357 return "gen8_urb_write_simd8_masked";
358 case SHADER_OPCODE_URB_WRITE_SIMD8_MASKED_PER_SLOT
:
359 return "gen8_urb_write_simd8_masked_per_slot";
360 case SHADER_OPCODE_URB_READ_SIMD8
:
361 return "urb_read_simd8";
362 case SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT
:
363 return "urb_read_simd8_per_slot";
365 case SHADER_OPCODE_FIND_LIVE_CHANNEL
:
366 return "find_live_channel";
367 case FS_OPCODE_LOAD_LIVE_CHANNELS
:
368 return "load_live_channels";
370 case SHADER_OPCODE_BROADCAST
:
372 case SHADER_OPCODE_SHUFFLE
:
374 case SHADER_OPCODE_SEL_EXEC
:
376 case SHADER_OPCODE_QUAD_SWIZZLE
:
377 return "quad_swizzle";
378 case SHADER_OPCODE_CLUSTER_BROADCAST
:
379 return "cluster_broadcast";
381 case SHADER_OPCODE_GET_BUFFER_SIZE
:
382 return "get_buffer_size";
384 case VEC4_OPCODE_MOV_BYTES
:
386 case VEC4_OPCODE_PACK_BYTES
:
388 case VEC4_OPCODE_UNPACK_UNIFORM
:
389 return "unpack_uniform";
390 case VEC4_OPCODE_DOUBLE_TO_F32
:
391 return "double_to_f32";
392 case VEC4_OPCODE_DOUBLE_TO_D32
:
393 return "double_to_d32";
394 case VEC4_OPCODE_DOUBLE_TO_U32
:
395 return "double_to_u32";
396 case VEC4_OPCODE_TO_DOUBLE
:
397 return "single_to_double";
398 case VEC4_OPCODE_PICK_LOW_32BIT
:
399 return "pick_low_32bit";
400 case VEC4_OPCODE_PICK_HIGH_32BIT
:
401 return "pick_high_32bit";
402 case VEC4_OPCODE_SET_LOW_32BIT
:
403 return "set_low_32bit";
404 case VEC4_OPCODE_SET_HIGH_32BIT
:
405 return "set_high_32bit";
407 case FS_OPCODE_DDX_COARSE
:
409 case FS_OPCODE_DDX_FINE
:
411 case FS_OPCODE_DDY_COARSE
:
413 case FS_OPCODE_DDY_FINE
:
416 case FS_OPCODE_LINTERP
:
419 case FS_OPCODE_PIXEL_X
:
421 case FS_OPCODE_PIXEL_Y
:
424 case FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD
:
425 return "uniform_pull_const";
426 case FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD_GEN7
:
427 return "uniform_pull_const_gen7";
428 case FS_OPCODE_VARYING_PULL_CONSTANT_LOAD_GEN4
:
429 return "varying_pull_const_gen4";
430 case FS_OPCODE_VARYING_PULL_CONSTANT_LOAD_LOGICAL
:
431 return "varying_pull_const_logical";
433 case FS_OPCODE_DISCARD_JUMP
:
434 return "discard_jump";
436 case FS_OPCODE_SET_SAMPLE_ID
:
437 return "set_sample_id";
439 case FS_OPCODE_PACK_HALF_2x16_SPLIT
:
440 return "pack_half_2x16_split";
442 case FS_OPCODE_PLACEHOLDER_HALT
:
443 return "placeholder_halt";
445 case FS_OPCODE_INTERPOLATE_AT_SAMPLE
:
446 return "interp_sample";
447 case FS_OPCODE_INTERPOLATE_AT_SHARED_OFFSET
:
448 return "interp_shared_offset";
449 case FS_OPCODE_INTERPOLATE_AT_PER_SLOT_OFFSET
:
450 return "interp_per_slot_offset";
452 case VS_OPCODE_URB_WRITE
:
453 return "vs_urb_write";
454 case VS_OPCODE_PULL_CONSTANT_LOAD
:
455 return "pull_constant_load";
456 case VS_OPCODE_PULL_CONSTANT_LOAD_GEN7
:
457 return "pull_constant_load_gen7";
459 case VS_OPCODE_SET_SIMD4X2_HEADER_GEN9
:
460 return "set_simd4x2_header_gen9";
462 case VS_OPCODE_UNPACK_FLAGS_SIMD4X2
:
463 return "unpack_flags_simd4x2";
465 case GS_OPCODE_URB_WRITE
:
466 return "gs_urb_write";
467 case GS_OPCODE_URB_WRITE_ALLOCATE
:
468 return "gs_urb_write_allocate";
469 case GS_OPCODE_THREAD_END
:
470 return "gs_thread_end";
471 case GS_OPCODE_SET_WRITE_OFFSET
:
472 return "set_write_offset";
473 case GS_OPCODE_SET_VERTEX_COUNT
:
474 return "set_vertex_count";
475 case GS_OPCODE_SET_DWORD_2
:
476 return "set_dword_2";
477 case GS_OPCODE_PREPARE_CHANNEL_MASKS
:
478 return "prepare_channel_masks";
479 case GS_OPCODE_SET_CHANNEL_MASKS
:
480 return "set_channel_masks";
481 case GS_OPCODE_GET_INSTANCE_ID
:
482 return "get_instance_id";
483 case GS_OPCODE_FF_SYNC
:
485 case GS_OPCODE_SET_PRIMITIVE_ID
:
486 return "set_primitive_id";
487 case GS_OPCODE_SVB_WRITE
:
488 return "gs_svb_write";
489 case GS_OPCODE_SVB_SET_DST_INDEX
:
490 return "gs_svb_set_dst_index";
491 case GS_OPCODE_FF_SYNC_SET_PRIMITIVES
:
492 return "gs_ff_sync_set_primitives";
493 case CS_OPCODE_CS_TERMINATE
:
494 return "cs_terminate";
495 case SHADER_OPCODE_BARRIER
:
497 case SHADER_OPCODE_MULH
:
499 case SHADER_OPCODE_ISUB_SAT
:
501 case SHADER_OPCODE_USUB_SAT
:
503 case SHADER_OPCODE_MOV_INDIRECT
:
504 return "mov_indirect";
506 case VEC4_OPCODE_URB_READ
:
508 case TCS_OPCODE_GET_INSTANCE_ID
:
509 return "tcs_get_instance_id";
510 case TCS_OPCODE_URB_WRITE
:
511 return "tcs_urb_write";
512 case TCS_OPCODE_SET_INPUT_URB_OFFSETS
:
513 return "tcs_set_input_urb_offsets";
514 case TCS_OPCODE_SET_OUTPUT_URB_OFFSETS
:
515 return "tcs_set_output_urb_offsets";
516 case TCS_OPCODE_GET_PRIMITIVE_ID
:
517 return "tcs_get_primitive_id";
518 case TCS_OPCODE_CREATE_BARRIER_HEADER
:
519 return "tcs_create_barrier_header";
520 case TCS_OPCODE_SRC0_010_IS_ZERO
:
521 return "tcs_src0<0,1,0>_is_zero";
522 case TCS_OPCODE_RELEASE_INPUT
:
523 return "tcs_release_input";
524 case TCS_OPCODE_THREAD_END
:
525 return "tcs_thread_end";
526 case TES_OPCODE_CREATE_INPUT_READ_HEADER
:
527 return "tes_create_input_read_header";
528 case TES_OPCODE_ADD_INDIRECT_URB_OFFSET
:
529 return "tes_add_indirect_urb_offset";
530 case TES_OPCODE_GET_PRIMITIVE_ID
:
531 return "tes_get_primitive_id";
533 case SHADER_OPCODE_RND_MODE
:
535 case SHADER_OPCODE_FLOAT_CONTROL_MODE
:
536 return "float_control_mode";
539 unreachable("not reached");
543 brw_saturate_immediate(enum brw_reg_type type
, struct brw_reg
*reg
)
550 } imm
, sat_imm
= { 0 };
552 const unsigned size
= type_sz(type
);
554 /* We want to either do a 32-bit or 64-bit data copy, the type is otherwise
555 * irrelevant, so just check the size of the type and copy from/to an
556 * appropriately sized field.
564 case BRW_REGISTER_TYPE_UD
:
565 case BRW_REGISTER_TYPE_D
:
566 case BRW_REGISTER_TYPE_UW
:
567 case BRW_REGISTER_TYPE_W
:
568 case BRW_REGISTER_TYPE_UQ
:
569 case BRW_REGISTER_TYPE_Q
:
572 case BRW_REGISTER_TYPE_F
:
573 sat_imm
.f
= CLAMP(imm
.f
, 0.0f
, 1.0f
);
575 case BRW_REGISTER_TYPE_DF
:
576 sat_imm
.df
= CLAMP(imm
.df
, 0.0, 1.0);
578 case BRW_REGISTER_TYPE_UB
:
579 case BRW_REGISTER_TYPE_B
:
580 unreachable("no UB/B immediates");
581 case BRW_REGISTER_TYPE_V
:
582 case BRW_REGISTER_TYPE_UV
:
583 case BRW_REGISTER_TYPE_VF
:
584 unreachable("unimplemented: saturate vector immediate");
585 case BRW_REGISTER_TYPE_HF
:
586 unreachable("unimplemented: saturate HF immediate");
587 case BRW_REGISTER_TYPE_NF
:
588 unreachable("no NF immediates");
592 if (imm
.ud
!= sat_imm
.ud
) {
593 reg
->ud
= sat_imm
.ud
;
597 if (imm
.df
!= sat_imm
.df
) {
598 reg
->df
= sat_imm
.df
;
606 brw_negate_immediate(enum brw_reg_type type
, struct brw_reg
*reg
)
609 case BRW_REGISTER_TYPE_D
:
610 case BRW_REGISTER_TYPE_UD
:
613 case BRW_REGISTER_TYPE_W
:
614 case BRW_REGISTER_TYPE_UW
: {
615 uint16_t value
= -(int16_t)reg
->ud
;
616 reg
->ud
= value
| (uint32_t)value
<< 16;
619 case BRW_REGISTER_TYPE_F
:
622 case BRW_REGISTER_TYPE_VF
:
623 reg
->ud
^= 0x80808080;
625 case BRW_REGISTER_TYPE_DF
:
628 case BRW_REGISTER_TYPE_UQ
:
629 case BRW_REGISTER_TYPE_Q
:
630 reg
->d64
= -reg
->d64
;
632 case BRW_REGISTER_TYPE_UB
:
633 case BRW_REGISTER_TYPE_B
:
634 unreachable("no UB/B immediates");
635 case BRW_REGISTER_TYPE_UV
:
636 case BRW_REGISTER_TYPE_V
:
637 assert(!"unimplemented: negate UV/V immediate");
638 case BRW_REGISTER_TYPE_HF
:
639 reg
->ud
^= 0x80008000;
641 case BRW_REGISTER_TYPE_NF
:
642 unreachable("no NF immediates");
649 brw_abs_immediate(enum brw_reg_type type
, struct brw_reg
*reg
)
652 case BRW_REGISTER_TYPE_D
:
653 reg
->d
= abs(reg
->d
);
655 case BRW_REGISTER_TYPE_W
: {
656 uint16_t value
= abs((int16_t)reg
->ud
);
657 reg
->ud
= value
| (uint32_t)value
<< 16;
660 case BRW_REGISTER_TYPE_F
:
661 reg
->f
= fabsf(reg
->f
);
663 case BRW_REGISTER_TYPE_DF
:
664 reg
->df
= fabs(reg
->df
);
666 case BRW_REGISTER_TYPE_VF
:
667 reg
->ud
&= ~0x80808080;
669 case BRW_REGISTER_TYPE_Q
:
670 reg
->d64
= imaxabs(reg
->d64
);
672 case BRW_REGISTER_TYPE_UB
:
673 case BRW_REGISTER_TYPE_B
:
674 unreachable("no UB/B immediates");
675 case BRW_REGISTER_TYPE_UQ
:
676 case BRW_REGISTER_TYPE_UD
:
677 case BRW_REGISTER_TYPE_UW
:
678 case BRW_REGISTER_TYPE_UV
:
679 /* Presumably the absolute value modifier on an unsigned source is a
680 * nop, but it would be nice to confirm.
682 assert(!"unimplemented: abs unsigned immediate");
683 case BRW_REGISTER_TYPE_V
:
684 assert(!"unimplemented: abs V immediate");
685 case BRW_REGISTER_TYPE_HF
:
686 reg
->ud
&= ~0x80008000;
688 case BRW_REGISTER_TYPE_NF
:
689 unreachable("no NF immediates");
695 backend_shader::backend_shader(const struct brw_compiler
*compiler
,
698 const nir_shader
*shader
,
699 struct brw_stage_prog_data
*stage_prog_data
)
700 : compiler(compiler
),
702 devinfo(compiler
->devinfo
),
704 stage_prog_data(stage_prog_data
),
707 stage(shader
->info
.stage
)
709 debug_enabled
= INTEL_DEBUG
& intel_debug_flag_for_shader_stage(stage
);
710 stage_name
= _mesa_shader_stage_to_string(stage
);
711 stage_abbrev
= _mesa_shader_stage_to_abbrev(stage
);
714 backend_shader::~backend_shader()
719 backend_reg::equals(const backend_reg
&r
) const
721 return brw_regs_equal(this, &r
) && offset
== r
.offset
;
725 backend_reg::negative_equals(const backend_reg
&r
) const
727 return brw_regs_negative_equal(this, &r
) && offset
== r
.offset
;
731 backend_reg::is_zero() const
736 assert(type_sz(type
) > 1);
739 case BRW_REGISTER_TYPE_HF
:
740 assert((d
& 0xffff) == ((d
>> 16) & 0xffff));
741 return (d
& 0xffff) == 0 || (d
& 0xffff) == 0x8000;
742 case BRW_REGISTER_TYPE_F
:
744 case BRW_REGISTER_TYPE_DF
:
746 case BRW_REGISTER_TYPE_W
:
747 case BRW_REGISTER_TYPE_UW
:
748 assert((d
& 0xffff) == ((d
>> 16) & 0xffff));
749 return (d
& 0xffff) == 0;
750 case BRW_REGISTER_TYPE_D
:
751 case BRW_REGISTER_TYPE_UD
:
753 case BRW_REGISTER_TYPE_UQ
:
754 case BRW_REGISTER_TYPE_Q
:
762 backend_reg::is_one() const
767 assert(type_sz(type
) > 1);
770 case BRW_REGISTER_TYPE_HF
:
771 assert((d
& 0xffff) == ((d
>> 16) & 0xffff));
772 return (d
& 0xffff) == 0x3c00;
773 case BRW_REGISTER_TYPE_F
:
775 case BRW_REGISTER_TYPE_DF
:
777 case BRW_REGISTER_TYPE_W
:
778 case BRW_REGISTER_TYPE_UW
:
779 assert((d
& 0xffff) == ((d
>> 16) & 0xffff));
780 return (d
& 0xffff) == 1;
781 case BRW_REGISTER_TYPE_D
:
782 case BRW_REGISTER_TYPE_UD
:
784 case BRW_REGISTER_TYPE_UQ
:
785 case BRW_REGISTER_TYPE_Q
:
793 backend_reg::is_negative_one() const
798 assert(type_sz(type
) > 1);
801 case BRW_REGISTER_TYPE_HF
:
802 assert((d
& 0xffff) == ((d
>> 16) & 0xffff));
803 return (d
& 0xffff) == 0xbc00;
804 case BRW_REGISTER_TYPE_F
:
806 case BRW_REGISTER_TYPE_DF
:
808 case BRW_REGISTER_TYPE_W
:
809 assert((d
& 0xffff) == ((d
>> 16) & 0xffff));
810 return (d
& 0xffff) == 0xffff;
811 case BRW_REGISTER_TYPE_D
:
813 case BRW_REGISTER_TYPE_Q
:
821 backend_reg::is_null() const
823 return file
== ARF
&& nr
== BRW_ARF_NULL
;
828 backend_reg::is_accumulator() const
830 return file
== ARF
&& nr
== BRW_ARF_ACCUMULATOR
;
834 backend_instruction::is_commutative() const
842 case SHADER_OPCODE_MULH
:
845 /* MIN and MAX are commutative. */
846 if (conditional_mod
== BRW_CONDITIONAL_GE
||
847 conditional_mod
== BRW_CONDITIONAL_L
) {
857 backend_instruction::is_3src(const struct gen_device_info
*devinfo
) const
859 return ::is_3src(devinfo
, opcode
);
863 backend_instruction::is_tex() const
865 return (opcode
== SHADER_OPCODE_TEX
||
866 opcode
== FS_OPCODE_TXB
||
867 opcode
== SHADER_OPCODE_TXD
||
868 opcode
== SHADER_OPCODE_TXF
||
869 opcode
== SHADER_OPCODE_TXF_LZ
||
870 opcode
== SHADER_OPCODE_TXF_CMS
||
871 opcode
== SHADER_OPCODE_TXF_CMS_W
||
872 opcode
== SHADER_OPCODE_TXF_UMS
||
873 opcode
== SHADER_OPCODE_TXF_MCS
||
874 opcode
== SHADER_OPCODE_TXL
||
875 opcode
== SHADER_OPCODE_TXL_LZ
||
876 opcode
== SHADER_OPCODE_TXS
||
877 opcode
== SHADER_OPCODE_LOD
||
878 opcode
== SHADER_OPCODE_TG4
||
879 opcode
== SHADER_OPCODE_TG4_OFFSET
||
880 opcode
== SHADER_OPCODE_SAMPLEINFO
);
884 backend_instruction::is_math() const
886 return (opcode
== SHADER_OPCODE_RCP
||
887 opcode
== SHADER_OPCODE_RSQ
||
888 opcode
== SHADER_OPCODE_SQRT
||
889 opcode
== SHADER_OPCODE_EXP2
||
890 opcode
== SHADER_OPCODE_LOG2
||
891 opcode
== SHADER_OPCODE_SIN
||
892 opcode
== SHADER_OPCODE_COS
||
893 opcode
== SHADER_OPCODE_INT_QUOTIENT
||
894 opcode
== SHADER_OPCODE_INT_REMAINDER
||
895 opcode
== SHADER_OPCODE_POW
);
899 backend_instruction::is_control_flow() const
903 case BRW_OPCODE_WHILE
:
905 case BRW_OPCODE_ELSE
:
906 case BRW_OPCODE_ENDIF
:
907 case BRW_OPCODE_BREAK
:
908 case BRW_OPCODE_CONTINUE
:
916 backend_instruction::can_do_source_mods() const
919 case BRW_OPCODE_ADDC
:
921 case BRW_OPCODE_BFI1
:
922 case BRW_OPCODE_BFI2
:
923 case BRW_OPCODE_BFREV
:
924 case BRW_OPCODE_CBIT
:
927 case BRW_OPCODE_SUBB
:
928 case SHADER_OPCODE_BROADCAST
:
929 case SHADER_OPCODE_CLUSTER_BROADCAST
:
930 case SHADER_OPCODE_MOV_INDIRECT
:
938 backend_instruction::can_do_saturate() const
948 case BRW_OPCODE_F16TO32
:
949 case BRW_OPCODE_F32TO16
:
950 case BRW_OPCODE_LINE
:
954 case BRW_OPCODE_MATH
:
957 case SHADER_OPCODE_MULH
:
959 case BRW_OPCODE_RNDD
:
960 case BRW_OPCODE_RNDE
:
961 case BRW_OPCODE_RNDU
:
962 case BRW_OPCODE_RNDZ
:
966 case FS_OPCODE_LINTERP
:
967 case SHADER_OPCODE_COS
:
968 case SHADER_OPCODE_EXP2
:
969 case SHADER_OPCODE_LOG2
:
970 case SHADER_OPCODE_POW
:
971 case SHADER_OPCODE_RCP
:
972 case SHADER_OPCODE_RSQ
:
973 case SHADER_OPCODE_SIN
:
974 case SHADER_OPCODE_SQRT
:
982 backend_instruction::can_do_cmod() const
986 case BRW_OPCODE_ADDC
:
991 case BRW_OPCODE_CMPN
:
996 case BRW_OPCODE_F16TO32
:
997 case BRW_OPCODE_F32TO16
:
999 case BRW_OPCODE_LINE
:
1000 case BRW_OPCODE_LRP
:
1001 case BRW_OPCODE_LZD
:
1002 case BRW_OPCODE_MAC
:
1003 case BRW_OPCODE_MACH
:
1004 case BRW_OPCODE_MAD
:
1005 case BRW_OPCODE_MOV
:
1006 case BRW_OPCODE_MUL
:
1007 case BRW_OPCODE_NOT
:
1009 case BRW_OPCODE_PLN
:
1010 case BRW_OPCODE_RNDD
:
1011 case BRW_OPCODE_RNDE
:
1012 case BRW_OPCODE_RNDU
:
1013 case BRW_OPCODE_RNDZ
:
1014 case BRW_OPCODE_SAD2
:
1015 case BRW_OPCODE_SADA2
:
1016 case BRW_OPCODE_SHL
:
1017 case BRW_OPCODE_SHR
:
1018 case BRW_OPCODE_SUBB
:
1019 case BRW_OPCODE_XOR
:
1020 case FS_OPCODE_LINTERP
:
1028 backend_instruction::reads_accumulator_implicitly() const
1031 case BRW_OPCODE_MAC
:
1032 case BRW_OPCODE_MACH
:
1033 case BRW_OPCODE_SADA2
:
1041 backend_instruction::writes_accumulator_implicitly(const struct gen_device_info
*devinfo
) const
1043 return writes_accumulator
||
1044 (devinfo
->gen
< 6 &&
1045 ((opcode
>= BRW_OPCODE_ADD
&& opcode
< BRW_OPCODE_NOP
) ||
1046 (opcode
>= FS_OPCODE_DDX_COARSE
&& opcode
<= FS_OPCODE_LINTERP
))) ||
1047 (opcode
== FS_OPCODE_LINTERP
&&
1048 (!devinfo
->has_pln
|| devinfo
->gen
<= 6));
1052 backend_instruction::has_side_effects() const
1055 case SHADER_OPCODE_SEND
:
1056 return send_has_side_effects
;
1058 case BRW_OPCODE_SYNC
:
1059 case VEC4_OPCODE_UNTYPED_ATOMIC
:
1060 case SHADER_OPCODE_UNTYPED_ATOMIC_LOGICAL
:
1061 case SHADER_OPCODE_UNTYPED_ATOMIC_FLOAT_LOGICAL
:
1062 case SHADER_OPCODE_GEN4_SCRATCH_WRITE
:
1063 case VEC4_OPCODE_UNTYPED_SURFACE_WRITE
:
1064 case SHADER_OPCODE_UNTYPED_SURFACE_WRITE_LOGICAL
:
1065 case SHADER_OPCODE_A64_UNTYPED_WRITE_LOGICAL
:
1066 case SHADER_OPCODE_A64_BYTE_SCATTERED_WRITE_LOGICAL
:
1067 case SHADER_OPCODE_A64_UNTYPED_ATOMIC_LOGICAL
:
1068 case SHADER_OPCODE_A64_UNTYPED_ATOMIC_INT64_LOGICAL
:
1069 case SHADER_OPCODE_A64_UNTYPED_ATOMIC_FLOAT_LOGICAL
:
1070 case SHADER_OPCODE_BYTE_SCATTERED_WRITE_LOGICAL
:
1071 case SHADER_OPCODE_DWORD_SCATTERED_WRITE_LOGICAL
:
1072 case SHADER_OPCODE_TYPED_ATOMIC_LOGICAL
:
1073 case SHADER_OPCODE_TYPED_SURFACE_WRITE_LOGICAL
:
1074 case SHADER_OPCODE_MEMORY_FENCE
:
1075 case SHADER_OPCODE_INTERLOCK
:
1076 case SHADER_OPCODE_URB_WRITE_SIMD8
:
1077 case SHADER_OPCODE_URB_WRITE_SIMD8_PER_SLOT
:
1078 case SHADER_OPCODE_URB_WRITE_SIMD8_MASKED
:
1079 case SHADER_OPCODE_URB_WRITE_SIMD8_MASKED_PER_SLOT
:
1080 case FS_OPCODE_FB_WRITE
:
1081 case FS_OPCODE_FB_WRITE_LOGICAL
:
1082 case FS_OPCODE_REP_FB_WRITE
:
1083 case SHADER_OPCODE_BARRIER
:
1084 case TCS_OPCODE_URB_WRITE
:
1085 case TCS_OPCODE_RELEASE_INPUT
:
1086 case SHADER_OPCODE_RND_MODE
:
1087 case SHADER_OPCODE_FLOAT_CONTROL_MODE
:
1088 case FS_OPCODE_SCHEDULING_FENCE
:
1096 backend_instruction::is_volatile() const
1099 case SHADER_OPCODE_SEND
:
1100 return send_is_volatile
;
1102 case VEC4_OPCODE_UNTYPED_SURFACE_READ
:
1103 case SHADER_OPCODE_UNTYPED_SURFACE_READ_LOGICAL
:
1104 case SHADER_OPCODE_TYPED_SURFACE_READ_LOGICAL
:
1105 case SHADER_OPCODE_BYTE_SCATTERED_READ_LOGICAL
:
1106 case SHADER_OPCODE_DWORD_SCATTERED_READ_LOGICAL
:
1107 case SHADER_OPCODE_A64_UNTYPED_READ_LOGICAL
:
1108 case SHADER_OPCODE_A64_BYTE_SCATTERED_READ_LOGICAL
:
1109 case SHADER_OPCODE_URB_READ_SIMD8
:
1110 case SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT
:
1111 case VEC4_OPCODE_URB_READ
:
1120 inst_is_in_block(const bblock_t
*block
, const backend_instruction
*inst
)
1123 foreach_inst_in_block (backend_instruction
, i
, block
) {
1133 adjust_later_block_ips(bblock_t
*start_block
, int ip_adjustment
)
1135 for (bblock_t
*block_iter
= start_block
->next();
1137 block_iter
= block_iter
->next()) {
1138 block_iter
->start_ip
+= ip_adjustment
;
1139 block_iter
->end_ip
+= ip_adjustment
;
1144 backend_instruction::insert_after(bblock_t
*block
, backend_instruction
*inst
)
1146 assert(this != inst
);
1148 if (!this->is_head_sentinel())
1149 assert(inst_is_in_block(block
, this) || !"Instruction not in block");
1153 adjust_later_block_ips(block
, 1);
1155 exec_node::insert_after(inst
);
1159 backend_instruction::insert_before(bblock_t
*block
, backend_instruction
*inst
)
1161 assert(this != inst
);
1163 if (!this->is_tail_sentinel())
1164 assert(inst_is_in_block(block
, this) || !"Instruction not in block");
1168 adjust_later_block_ips(block
, 1);
1170 exec_node::insert_before(inst
);
1174 backend_instruction::insert_before(bblock_t
*block
, exec_list
*list
)
1176 assert(inst_is_in_block(block
, this) || !"Instruction not in block");
1178 unsigned num_inst
= list
->length();
1180 block
->end_ip
+= num_inst
;
1182 adjust_later_block_ips(block
, num_inst
);
1184 exec_node::insert_before(list
);
1188 backend_instruction::remove(bblock_t
*block
)
1190 assert(inst_is_in_block(block
, this) || !"Instruction not in block");
1192 adjust_later_block_ips(block
, -1);
1194 if (block
->start_ip
== block
->end_ip
) {
1195 block
->cfg
->remove_block(block
);
1200 exec_node::remove();
1204 backend_shader::dump_instructions()
1206 dump_instructions(NULL
);
1210 backend_shader::dump_instructions(const char *name
)
1212 FILE *file
= stderr
;
1213 if (name
&& geteuid() != 0) {
1214 file
= fopen(name
, "w");
1221 foreach_block_and_inst(block
, backend_instruction
, inst
, cfg
) {
1222 if (!unlikely(INTEL_DEBUG
& DEBUG_OPTIMIZER
))
1223 fprintf(file
, "%4d: ", ip
++);
1224 dump_instruction(inst
, file
);
1228 foreach_in_list(backend_instruction
, inst
, &instructions
) {
1229 if (!unlikely(INTEL_DEBUG
& DEBUG_OPTIMIZER
))
1230 fprintf(file
, "%4d: ", ip
++);
1231 dump_instruction(inst
, file
);
1235 if (file
!= stderr
) {
1241 backend_shader::calculate_cfg()
1245 cfg
= new(mem_ctx
) cfg_t(&this->instructions
);
1248 extern "C" const unsigned *
1249 brw_compile_tes(const struct brw_compiler
*compiler
,
1252 const struct brw_tes_prog_key
*key
,
1253 const struct brw_vue_map
*input_vue_map
,
1254 struct brw_tes_prog_data
*prog_data
,
1256 int shader_time_index
,
1257 struct brw_compile_stats
*stats
,
1260 const struct gen_device_info
*devinfo
= compiler
->devinfo
;
1261 const bool is_scalar
= compiler
->scalar_stage
[MESA_SHADER_TESS_EVAL
];
1262 const unsigned *assembly
;
1264 nir
->info
.inputs_read
= key
->inputs_read
;
1265 nir
->info
.patch_inputs_read
= key
->patch_inputs_read
;
1267 brw_nir_apply_key(nir
, compiler
, &key
->base
, 8, is_scalar
);
1268 brw_nir_lower_tes_inputs(nir
, input_vue_map
);
1269 brw_nir_lower_vue_outputs(nir
);
1270 brw_postprocess_nir(nir
, compiler
, is_scalar
);
1272 brw_compute_vue_map(devinfo
, &prog_data
->base
.vue_map
,
1273 nir
->info
.outputs_written
,
1274 nir
->info
.separate_shader
);
1276 unsigned output_size_bytes
= prog_data
->base
.vue_map
.num_slots
* 4 * 4;
1278 assert(output_size_bytes
>= 1);
1279 if (output_size_bytes
> GEN7_MAX_DS_URB_ENTRY_SIZE_BYTES
) {
1281 *error_str
= ralloc_strdup(mem_ctx
, "DS outputs exceed maximum size");
1285 prog_data
->base
.clip_distance_mask
=
1286 ((1 << nir
->info
.clip_distance_array_size
) - 1);
1287 prog_data
->base
.cull_distance_mask
=
1288 ((1 << nir
->info
.cull_distance_array_size
) - 1) <<
1289 nir
->info
.clip_distance_array_size
;
1291 /* URB entry sizes are stored as a multiple of 64 bytes. */
1292 prog_data
->base
.urb_entry_size
= ALIGN(output_size_bytes
, 64) / 64;
1294 /* On Cannonlake software shall not program an allocation size that
1295 * specifies a size that is a multiple of 3 64B (512-bit) cachelines.
1297 if (devinfo
->gen
== 10 &&
1298 prog_data
->base
.urb_entry_size
% 3 == 0)
1299 prog_data
->base
.urb_entry_size
++;
1301 prog_data
->base
.urb_read_length
= 0;
1303 STATIC_ASSERT(BRW_TESS_PARTITIONING_INTEGER
== TESS_SPACING_EQUAL
- 1);
1304 STATIC_ASSERT(BRW_TESS_PARTITIONING_ODD_FRACTIONAL
==
1305 TESS_SPACING_FRACTIONAL_ODD
- 1);
1306 STATIC_ASSERT(BRW_TESS_PARTITIONING_EVEN_FRACTIONAL
==
1307 TESS_SPACING_FRACTIONAL_EVEN
- 1);
1309 prog_data
->partitioning
=
1310 (enum brw_tess_partitioning
) (nir
->info
.tess
.spacing
- 1);
1312 switch (nir
->info
.tess
.primitive_mode
) {
1314 prog_data
->domain
= BRW_TESS_DOMAIN_QUAD
;
1317 prog_data
->domain
= BRW_TESS_DOMAIN_TRI
;
1320 prog_data
->domain
= BRW_TESS_DOMAIN_ISOLINE
;
1323 unreachable("invalid domain shader primitive mode");
1326 if (nir
->info
.tess
.point_mode
) {
1327 prog_data
->output_topology
= BRW_TESS_OUTPUT_TOPOLOGY_POINT
;
1328 } else if (nir
->info
.tess
.primitive_mode
== GL_ISOLINES
) {
1329 prog_data
->output_topology
= BRW_TESS_OUTPUT_TOPOLOGY_LINE
;
1331 /* Hardware winding order is backwards from OpenGL */
1332 prog_data
->output_topology
=
1333 nir
->info
.tess
.ccw
? BRW_TESS_OUTPUT_TOPOLOGY_TRI_CW
1334 : BRW_TESS_OUTPUT_TOPOLOGY_TRI_CCW
;
1337 if (unlikely(INTEL_DEBUG
& DEBUG_TES
)) {
1338 fprintf(stderr
, "TES Input ");
1339 brw_print_vue_map(stderr
, input_vue_map
);
1340 fprintf(stderr
, "TES Output ");
1341 brw_print_vue_map(stderr
, &prog_data
->base
.vue_map
);
1345 fs_visitor
v(compiler
, log_data
, mem_ctx
, &key
->base
,
1346 &prog_data
->base
.base
, nir
, 8,
1347 shader_time_index
, input_vue_map
);
1350 *error_str
= ralloc_strdup(mem_ctx
, v
.fail_msg
);
1354 prog_data
->base
.base
.dispatch_grf_start_reg
= v
.payload
.num_regs
;
1355 prog_data
->base
.dispatch_mode
= DISPATCH_MODE_SIMD8
;
1357 fs_generator
g(compiler
, log_data
, mem_ctx
,
1358 &prog_data
->base
.base
, v
.shader_stats
, false,
1359 MESA_SHADER_TESS_EVAL
);
1360 if (unlikely(INTEL_DEBUG
& DEBUG_TES
)) {
1361 g
.enable_debug(ralloc_asprintf(mem_ctx
,
1362 "%s tessellation evaluation shader %s",
1363 nir
->info
.label
? nir
->info
.label
1368 g
.generate_code(v
.cfg
, 8, stats
);
1370 assembly
= g
.get_assembly();
1372 brw::vec4_tes_visitor
v(compiler
, log_data
, key
, prog_data
,
1373 nir
, mem_ctx
, shader_time_index
);
1376 *error_str
= ralloc_strdup(mem_ctx
, v
.fail_msg
);
1380 if (unlikely(INTEL_DEBUG
& DEBUG_TES
))
1381 v
.dump_instructions();
1383 assembly
= brw_vec4_generate_assembly(compiler
, log_data
, mem_ctx
, nir
,
1384 &prog_data
->base
, v
.cfg
, stats
);