2 * Copyright © 2010 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
28 #include "brw_vec4_tes.h"
29 #include "common/gen_debug.h"
30 #include "main/uniforms.h"
31 #include "util/macros.h"
34 brw_type_for_base_type(const struct glsl_type
*type
)
36 switch (type
->base_type
) {
37 case GLSL_TYPE_FLOAT16
:
38 return BRW_REGISTER_TYPE_HF
;
40 return BRW_REGISTER_TYPE_F
;
43 case GLSL_TYPE_SUBROUTINE
:
44 return BRW_REGISTER_TYPE_D
;
46 return BRW_REGISTER_TYPE_W
;
48 return BRW_REGISTER_TYPE_B
;
50 return BRW_REGISTER_TYPE_UD
;
51 case GLSL_TYPE_UINT16
:
52 return BRW_REGISTER_TYPE_UW
;
54 return BRW_REGISTER_TYPE_UB
;
56 return brw_type_for_base_type(type
->fields
.array
);
57 case GLSL_TYPE_STRUCT
:
58 case GLSL_TYPE_SAMPLER
:
59 case GLSL_TYPE_ATOMIC_UINT
:
60 /* These should be overridden with the type of the member when
61 * dereferenced into. BRW_REGISTER_TYPE_UD seems like a likely
62 * way to trip up if we don't.
64 return BRW_REGISTER_TYPE_UD
;
66 return BRW_REGISTER_TYPE_UD
;
67 case GLSL_TYPE_DOUBLE
:
68 return BRW_REGISTER_TYPE_DF
;
69 case GLSL_TYPE_UINT64
:
70 return BRW_REGISTER_TYPE_UQ
;
72 return BRW_REGISTER_TYPE_Q
;
75 case GLSL_TYPE_INTERFACE
:
76 case GLSL_TYPE_FUNCTION
:
77 unreachable("not reached");
80 return BRW_REGISTER_TYPE_F
;
83 enum brw_conditional_mod
84 brw_conditional_for_comparison(unsigned int op
)
88 return BRW_CONDITIONAL_L
;
90 return BRW_CONDITIONAL_GE
;
92 case ir_binop_all_equal
: /* same as equal for scalars */
93 return BRW_CONDITIONAL_Z
;
95 case ir_binop_any_nequal
: /* same as nequal for scalars */
96 return BRW_CONDITIONAL_NZ
;
98 unreachable("not reached: bad operation for comparison");
103 brw_math_function(enum opcode op
)
106 case SHADER_OPCODE_RCP
:
107 return BRW_MATH_FUNCTION_INV
;
108 case SHADER_OPCODE_RSQ
:
109 return BRW_MATH_FUNCTION_RSQ
;
110 case SHADER_OPCODE_SQRT
:
111 return BRW_MATH_FUNCTION_SQRT
;
112 case SHADER_OPCODE_EXP2
:
113 return BRW_MATH_FUNCTION_EXP
;
114 case SHADER_OPCODE_LOG2
:
115 return BRW_MATH_FUNCTION_LOG
;
116 case SHADER_OPCODE_POW
:
117 return BRW_MATH_FUNCTION_POW
;
118 case SHADER_OPCODE_SIN
:
119 return BRW_MATH_FUNCTION_SIN
;
120 case SHADER_OPCODE_COS
:
121 return BRW_MATH_FUNCTION_COS
;
122 case SHADER_OPCODE_INT_QUOTIENT
:
123 return BRW_MATH_FUNCTION_INT_DIV_QUOTIENT
;
124 case SHADER_OPCODE_INT_REMAINDER
:
125 return BRW_MATH_FUNCTION_INT_DIV_REMAINDER
;
127 unreachable("not reached: unknown math function");
132 brw_texture_offset(int *offsets
, unsigned num_components
, uint32_t *offset_bits
)
134 if (!offsets
) return false; /* nonconstant offset; caller will handle it. */
136 /* offset out of bounds; caller will handle it. */
137 for (unsigned i
= 0; i
< num_components
; i
++)
138 if (offsets
[i
] > 7 || offsets
[i
] < -8)
141 /* Combine all three offsets into a single unsigned dword:
143 * bits 11:8 - U Offset (X component)
144 * bits 7:4 - V Offset (Y component)
145 * bits 3:0 - R Offset (Z component)
148 for (unsigned i
= 0; i
< num_components
; i
++) {
149 const unsigned shift
= 4 * (2 - i
);
150 *offset_bits
|= (offsets
[i
] << shift
) & (0xF << shift
);
156 brw_instruction_name(const struct gen_device_info
*devinfo
, enum opcode op
)
159 case BRW_OPCODE_ILLEGAL
... BRW_OPCODE_NOP
:
160 /* The DO instruction doesn't exist on Gen6+, but we use it to mark the
161 * start of a loop in the IR.
163 if (devinfo
->gen
>= 6 && op
== BRW_OPCODE_DO
)
166 /* The following conversion opcodes doesn't exist on Gen8+, but we use
167 * then to mark that we want to do the conversion.
169 if (devinfo
->gen
> 7 && op
== BRW_OPCODE_F32TO16
)
172 if (devinfo
->gen
> 7 && op
== BRW_OPCODE_F16TO32
)
175 assert(brw_opcode_desc(devinfo
, op
)->name
);
176 return brw_opcode_desc(devinfo
, op
)->name
;
177 case FS_OPCODE_FB_WRITE
:
179 case FS_OPCODE_FB_WRITE_LOGICAL
:
180 return "fb_write_logical";
181 case FS_OPCODE_REP_FB_WRITE
:
182 return "rep_fb_write";
183 case FS_OPCODE_FB_READ
:
185 case FS_OPCODE_FB_READ_LOGICAL
:
186 return "fb_read_logical";
188 case SHADER_OPCODE_RCP
:
190 case SHADER_OPCODE_RSQ
:
192 case SHADER_OPCODE_SQRT
:
194 case SHADER_OPCODE_EXP2
:
196 case SHADER_OPCODE_LOG2
:
198 case SHADER_OPCODE_POW
:
200 case SHADER_OPCODE_INT_QUOTIENT
:
202 case SHADER_OPCODE_INT_REMAINDER
:
204 case SHADER_OPCODE_SIN
:
206 case SHADER_OPCODE_COS
:
209 case SHADER_OPCODE_TEX
:
211 case SHADER_OPCODE_TEX_LOGICAL
:
212 return "tex_logical";
213 case SHADER_OPCODE_TXD
:
215 case SHADER_OPCODE_TXD_LOGICAL
:
216 return "txd_logical";
217 case SHADER_OPCODE_TXF
:
219 case SHADER_OPCODE_TXF_LOGICAL
:
220 return "txf_logical";
221 case SHADER_OPCODE_TXF_LZ
:
223 case SHADER_OPCODE_TXL
:
225 case SHADER_OPCODE_TXL_LOGICAL
:
226 return "txl_logical";
227 case SHADER_OPCODE_TXL_LZ
:
229 case SHADER_OPCODE_TXS
:
231 case SHADER_OPCODE_TXS_LOGICAL
:
232 return "txs_logical";
235 case FS_OPCODE_TXB_LOGICAL
:
236 return "txb_logical";
237 case SHADER_OPCODE_TXF_CMS
:
239 case SHADER_OPCODE_TXF_CMS_LOGICAL
:
240 return "txf_cms_logical";
241 case SHADER_OPCODE_TXF_CMS_W
:
243 case SHADER_OPCODE_TXF_CMS_W_LOGICAL
:
244 return "txf_cms_w_logical";
245 case SHADER_OPCODE_TXF_UMS
:
247 case SHADER_OPCODE_TXF_UMS_LOGICAL
:
248 return "txf_ums_logical";
249 case SHADER_OPCODE_TXF_MCS
:
251 case SHADER_OPCODE_TXF_MCS_LOGICAL
:
252 return "txf_mcs_logical";
253 case SHADER_OPCODE_LOD
:
255 case SHADER_OPCODE_LOD_LOGICAL
:
256 return "lod_logical";
257 case SHADER_OPCODE_TG4
:
259 case SHADER_OPCODE_TG4_LOGICAL
:
260 return "tg4_logical";
261 case SHADER_OPCODE_TG4_OFFSET
:
263 case SHADER_OPCODE_TG4_OFFSET_LOGICAL
:
264 return "tg4_offset_logical";
265 case SHADER_OPCODE_SAMPLEINFO
:
267 case SHADER_OPCODE_SAMPLEINFO_LOGICAL
:
268 return "sampleinfo_logical";
270 case SHADER_OPCODE_SHADER_TIME_ADD
:
271 return "shader_time_add";
273 case SHADER_OPCODE_UNTYPED_ATOMIC
:
274 return "untyped_atomic";
275 case SHADER_OPCODE_UNTYPED_ATOMIC_LOGICAL
:
276 return "untyped_atomic_logical";
277 case SHADER_OPCODE_UNTYPED_SURFACE_READ
:
278 return "untyped_surface_read";
279 case SHADER_OPCODE_UNTYPED_SURFACE_READ_LOGICAL
:
280 return "untyped_surface_read_logical";
281 case SHADER_OPCODE_UNTYPED_SURFACE_WRITE
:
282 return "untyped_surface_write";
283 case SHADER_OPCODE_UNTYPED_SURFACE_WRITE_LOGICAL
:
284 return "untyped_surface_write_logical";
285 case SHADER_OPCODE_TYPED_ATOMIC
:
286 return "typed_atomic";
287 case SHADER_OPCODE_TYPED_ATOMIC_LOGICAL
:
288 return "typed_atomic_logical";
289 case SHADER_OPCODE_TYPED_SURFACE_READ
:
290 return "typed_surface_read";
291 case SHADER_OPCODE_TYPED_SURFACE_READ_LOGICAL
:
292 return "typed_surface_read_logical";
293 case SHADER_OPCODE_TYPED_SURFACE_WRITE
:
294 return "typed_surface_write";
295 case SHADER_OPCODE_TYPED_SURFACE_WRITE_LOGICAL
:
296 return "typed_surface_write_logical";
297 case SHADER_OPCODE_MEMORY_FENCE
:
298 return "memory_fence";
299 case SHADER_OPCODE_INTERLOCK
:
300 /* For an interlock we actually issue a memory fence via sendc. */
303 case SHADER_OPCODE_BYTE_SCATTERED_READ
:
304 return "byte_scattered_read";
305 case SHADER_OPCODE_BYTE_SCATTERED_READ_LOGICAL
:
306 return "byte_scattered_read_logical";
307 case SHADER_OPCODE_BYTE_SCATTERED_WRITE
:
308 return "byte_scattered_write";
309 case SHADER_OPCODE_BYTE_SCATTERED_WRITE_LOGICAL
:
310 return "byte_scattered_write_logical";
312 case SHADER_OPCODE_LOAD_PAYLOAD
:
313 return "load_payload";
317 case SHADER_OPCODE_GEN4_SCRATCH_READ
:
318 return "gen4_scratch_read";
319 case SHADER_OPCODE_GEN4_SCRATCH_WRITE
:
320 return "gen4_scratch_write";
321 case SHADER_OPCODE_GEN7_SCRATCH_READ
:
322 return "gen7_scratch_read";
323 case SHADER_OPCODE_URB_WRITE_SIMD8
:
324 return "gen8_urb_write_simd8";
325 case SHADER_OPCODE_URB_WRITE_SIMD8_PER_SLOT
:
326 return "gen8_urb_write_simd8_per_slot";
327 case SHADER_OPCODE_URB_WRITE_SIMD8_MASKED
:
328 return "gen8_urb_write_simd8_masked";
329 case SHADER_OPCODE_URB_WRITE_SIMD8_MASKED_PER_SLOT
:
330 return "gen8_urb_write_simd8_masked_per_slot";
331 case SHADER_OPCODE_URB_READ_SIMD8
:
332 return "urb_read_simd8";
333 case SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT
:
334 return "urb_read_simd8_per_slot";
336 case SHADER_OPCODE_FIND_LIVE_CHANNEL
:
337 return "find_live_channel";
338 case SHADER_OPCODE_BROADCAST
:
340 case SHADER_OPCODE_SHUFFLE
:
342 case SHADER_OPCODE_SEL_EXEC
:
344 case SHADER_OPCODE_QUAD_SWIZZLE
:
345 return "quad_swizzle";
346 case SHADER_OPCODE_CLUSTER_BROADCAST
:
347 return "cluster_broadcast";
349 case SHADER_OPCODE_GET_BUFFER_SIZE
:
350 return "get_buffer_size";
352 case VEC4_OPCODE_MOV_BYTES
:
354 case VEC4_OPCODE_PACK_BYTES
:
356 case VEC4_OPCODE_UNPACK_UNIFORM
:
357 return "unpack_uniform";
358 case VEC4_OPCODE_DOUBLE_TO_F32
:
359 return "double_to_f32";
360 case VEC4_OPCODE_DOUBLE_TO_D32
:
361 return "double_to_d32";
362 case VEC4_OPCODE_DOUBLE_TO_U32
:
363 return "double_to_u32";
364 case VEC4_OPCODE_TO_DOUBLE
:
365 return "single_to_double";
366 case VEC4_OPCODE_PICK_LOW_32BIT
:
367 return "pick_low_32bit";
368 case VEC4_OPCODE_PICK_HIGH_32BIT
:
369 return "pick_high_32bit";
370 case VEC4_OPCODE_SET_LOW_32BIT
:
371 return "set_low_32bit";
372 case VEC4_OPCODE_SET_HIGH_32BIT
:
373 return "set_high_32bit";
375 case FS_OPCODE_DDX_COARSE
:
377 case FS_OPCODE_DDX_FINE
:
379 case FS_OPCODE_DDY_COARSE
:
381 case FS_OPCODE_DDY_FINE
:
384 case FS_OPCODE_LINTERP
:
387 case FS_OPCODE_PIXEL_X
:
389 case FS_OPCODE_PIXEL_Y
:
392 case FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD
:
393 return "uniform_pull_const";
394 case FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD_GEN7
:
395 return "uniform_pull_const_gen7";
396 case FS_OPCODE_VARYING_PULL_CONSTANT_LOAD_GEN4
:
397 return "varying_pull_const_gen4";
398 case FS_OPCODE_VARYING_PULL_CONSTANT_LOAD_GEN7
:
399 return "varying_pull_const_gen7";
400 case FS_OPCODE_VARYING_PULL_CONSTANT_LOAD_LOGICAL
:
401 return "varying_pull_const_logical";
403 case FS_OPCODE_MOV_DISPATCH_TO_FLAGS
:
404 return "mov_dispatch_to_flags";
405 case FS_OPCODE_DISCARD_JUMP
:
406 return "discard_jump";
408 case FS_OPCODE_SET_SAMPLE_ID
:
409 return "set_sample_id";
411 case FS_OPCODE_PACK_HALF_2x16_SPLIT
:
412 return "pack_half_2x16_split";
413 case FS_OPCODE_UNPACK_HALF_2x16_SPLIT_X
:
414 return "unpack_half_2x16_split_x";
415 case FS_OPCODE_UNPACK_HALF_2x16_SPLIT_Y
:
416 return "unpack_half_2x16_split_y";
418 case FS_OPCODE_PLACEHOLDER_HALT
:
419 return "placeholder_halt";
421 case FS_OPCODE_INTERPOLATE_AT_SAMPLE
:
422 return "interp_sample";
423 case FS_OPCODE_INTERPOLATE_AT_SHARED_OFFSET
:
424 return "interp_shared_offset";
425 case FS_OPCODE_INTERPOLATE_AT_PER_SLOT_OFFSET
:
426 return "interp_per_slot_offset";
428 case VS_OPCODE_URB_WRITE
:
429 return "vs_urb_write";
430 case VS_OPCODE_PULL_CONSTANT_LOAD
:
431 return "pull_constant_load";
432 case VS_OPCODE_PULL_CONSTANT_LOAD_GEN7
:
433 return "pull_constant_load_gen7";
435 case VS_OPCODE_SET_SIMD4X2_HEADER_GEN9
:
436 return "set_simd4x2_header_gen9";
438 case VS_OPCODE_UNPACK_FLAGS_SIMD4X2
:
439 return "unpack_flags_simd4x2";
441 case GS_OPCODE_URB_WRITE
:
442 return "gs_urb_write";
443 case GS_OPCODE_URB_WRITE_ALLOCATE
:
444 return "gs_urb_write_allocate";
445 case GS_OPCODE_THREAD_END
:
446 return "gs_thread_end";
447 case GS_OPCODE_SET_WRITE_OFFSET
:
448 return "set_write_offset";
449 case GS_OPCODE_SET_VERTEX_COUNT
:
450 return "set_vertex_count";
451 case GS_OPCODE_SET_DWORD_2
:
452 return "set_dword_2";
453 case GS_OPCODE_PREPARE_CHANNEL_MASKS
:
454 return "prepare_channel_masks";
455 case GS_OPCODE_SET_CHANNEL_MASKS
:
456 return "set_channel_masks";
457 case GS_OPCODE_GET_INSTANCE_ID
:
458 return "get_instance_id";
459 case GS_OPCODE_FF_SYNC
:
461 case GS_OPCODE_SET_PRIMITIVE_ID
:
462 return "set_primitive_id";
463 case GS_OPCODE_SVB_WRITE
:
464 return "gs_svb_write";
465 case GS_OPCODE_SVB_SET_DST_INDEX
:
466 return "gs_svb_set_dst_index";
467 case GS_OPCODE_FF_SYNC_SET_PRIMITIVES
:
468 return "gs_ff_sync_set_primitives";
469 case CS_OPCODE_CS_TERMINATE
:
470 return "cs_terminate";
471 case SHADER_OPCODE_BARRIER
:
473 case SHADER_OPCODE_MULH
:
475 case SHADER_OPCODE_MOV_INDIRECT
:
476 return "mov_indirect";
478 case VEC4_OPCODE_URB_READ
:
480 case TCS_OPCODE_GET_INSTANCE_ID
:
481 return "tcs_get_instance_id";
482 case TCS_OPCODE_URB_WRITE
:
483 return "tcs_urb_write";
484 case TCS_OPCODE_SET_INPUT_URB_OFFSETS
:
485 return "tcs_set_input_urb_offsets";
486 case TCS_OPCODE_SET_OUTPUT_URB_OFFSETS
:
487 return "tcs_set_output_urb_offsets";
488 case TCS_OPCODE_GET_PRIMITIVE_ID
:
489 return "tcs_get_primitive_id";
490 case TCS_OPCODE_CREATE_BARRIER_HEADER
:
491 return "tcs_create_barrier_header";
492 case TCS_OPCODE_SRC0_010_IS_ZERO
:
493 return "tcs_src0<0,1,0>_is_zero";
494 case TCS_OPCODE_RELEASE_INPUT
:
495 return "tcs_release_input";
496 case TCS_OPCODE_THREAD_END
:
497 return "tcs_thread_end";
498 case TES_OPCODE_CREATE_INPUT_READ_HEADER
:
499 return "tes_create_input_read_header";
500 case TES_OPCODE_ADD_INDIRECT_URB_OFFSET
:
501 return "tes_add_indirect_urb_offset";
502 case TES_OPCODE_GET_PRIMITIVE_ID
:
503 return "tes_get_primitive_id";
505 case SHADER_OPCODE_RND_MODE
:
509 unreachable("not reached");
513 brw_saturate_immediate(enum brw_reg_type type
, struct brw_reg
*reg
)
520 } imm
, sat_imm
= { 0 };
522 const unsigned size
= type_sz(type
);
524 /* We want to either do a 32-bit or 64-bit data copy, the type is otherwise
525 * irrelevant, so just check the size of the type and copy from/to an
526 * appropriately sized field.
534 case BRW_REGISTER_TYPE_UD
:
535 case BRW_REGISTER_TYPE_D
:
536 case BRW_REGISTER_TYPE_UW
:
537 case BRW_REGISTER_TYPE_W
:
538 case BRW_REGISTER_TYPE_UQ
:
539 case BRW_REGISTER_TYPE_Q
:
542 case BRW_REGISTER_TYPE_F
:
543 sat_imm
.f
= CLAMP(imm
.f
, 0.0f
, 1.0f
);
545 case BRW_REGISTER_TYPE_DF
:
546 sat_imm
.df
= CLAMP(imm
.df
, 0.0, 1.0);
548 case BRW_REGISTER_TYPE_UB
:
549 case BRW_REGISTER_TYPE_B
:
550 unreachable("no UB/B immediates");
551 case BRW_REGISTER_TYPE_V
:
552 case BRW_REGISTER_TYPE_UV
:
553 case BRW_REGISTER_TYPE_VF
:
554 unreachable("unimplemented: saturate vector immediate");
555 case BRW_REGISTER_TYPE_HF
:
556 unreachable("unimplemented: saturate HF immediate");
557 case BRW_REGISTER_TYPE_NF
:
558 unreachable("no NF immediates");
562 if (imm
.ud
!= sat_imm
.ud
) {
563 reg
->ud
= sat_imm
.ud
;
567 if (imm
.df
!= sat_imm
.df
) {
568 reg
->df
= sat_imm
.df
;
576 brw_negate_immediate(enum brw_reg_type type
, struct brw_reg
*reg
)
579 case BRW_REGISTER_TYPE_D
:
580 case BRW_REGISTER_TYPE_UD
:
583 case BRW_REGISTER_TYPE_W
:
584 case BRW_REGISTER_TYPE_UW
: {
585 uint16_t value
= -(int16_t)reg
->ud
;
586 reg
->ud
= value
| (uint32_t)value
<< 16;
589 case BRW_REGISTER_TYPE_F
:
592 case BRW_REGISTER_TYPE_VF
:
593 reg
->ud
^= 0x80808080;
595 case BRW_REGISTER_TYPE_DF
:
598 case BRW_REGISTER_TYPE_UQ
:
599 case BRW_REGISTER_TYPE_Q
:
600 reg
->d64
= -reg
->d64
;
602 case BRW_REGISTER_TYPE_UB
:
603 case BRW_REGISTER_TYPE_B
:
604 unreachable("no UB/B immediates");
605 case BRW_REGISTER_TYPE_UV
:
606 case BRW_REGISTER_TYPE_V
:
607 assert(!"unimplemented: negate UV/V immediate");
608 case BRW_REGISTER_TYPE_HF
:
609 reg
->ud
^= 0x80008000;
611 case BRW_REGISTER_TYPE_NF
:
612 unreachable("no NF immediates");
619 brw_abs_immediate(enum brw_reg_type type
, struct brw_reg
*reg
)
622 case BRW_REGISTER_TYPE_D
:
623 reg
->d
= abs(reg
->d
);
625 case BRW_REGISTER_TYPE_W
: {
626 uint16_t value
= abs((int16_t)reg
->ud
);
627 reg
->ud
= value
| (uint32_t)value
<< 16;
630 case BRW_REGISTER_TYPE_F
:
631 reg
->f
= fabsf(reg
->f
);
633 case BRW_REGISTER_TYPE_DF
:
634 reg
->df
= fabs(reg
->df
);
636 case BRW_REGISTER_TYPE_VF
:
637 reg
->ud
&= ~0x80808080;
639 case BRW_REGISTER_TYPE_Q
:
640 reg
->d64
= imaxabs(reg
->d64
);
642 case BRW_REGISTER_TYPE_UB
:
643 case BRW_REGISTER_TYPE_B
:
644 unreachable("no UB/B immediates");
645 case BRW_REGISTER_TYPE_UQ
:
646 case BRW_REGISTER_TYPE_UD
:
647 case BRW_REGISTER_TYPE_UW
:
648 case BRW_REGISTER_TYPE_UV
:
649 /* Presumably the absolute value modifier on an unsigned source is a
650 * nop, but it would be nice to confirm.
652 assert(!"unimplemented: abs unsigned immediate");
653 case BRW_REGISTER_TYPE_V
:
654 assert(!"unimplemented: abs V immediate");
655 case BRW_REGISTER_TYPE_HF
:
656 reg
->ud
&= ~0x80008000;
658 case BRW_REGISTER_TYPE_NF
:
659 unreachable("no NF immediates");
665 backend_shader::backend_shader(const struct brw_compiler
*compiler
,
668 const nir_shader
*shader
,
669 struct brw_stage_prog_data
*stage_prog_data
)
670 : compiler(compiler
),
672 devinfo(compiler
->devinfo
),
674 stage_prog_data(stage_prog_data
),
677 stage(shader
->info
.stage
)
679 debug_enabled
= INTEL_DEBUG
& intel_debug_flag_for_shader_stage(stage
);
680 stage_name
= _mesa_shader_stage_to_string(stage
);
681 stage_abbrev
= _mesa_shader_stage_to_abbrev(stage
);
684 backend_shader::~backend_shader()
689 backend_reg::equals(const backend_reg
&r
) const
691 return brw_regs_equal(this, &r
) && offset
== r
.offset
;
695 backend_reg::negative_equals(const backend_reg
&r
) const
697 return brw_regs_negative_equal(this, &r
) && offset
== r
.offset
;
701 backend_reg::is_zero() const
707 case BRW_REGISTER_TYPE_F
:
709 case BRW_REGISTER_TYPE_DF
:
711 case BRW_REGISTER_TYPE_D
:
712 case BRW_REGISTER_TYPE_UD
:
714 case BRW_REGISTER_TYPE_UQ
:
715 case BRW_REGISTER_TYPE_Q
:
723 backend_reg::is_one() const
729 case BRW_REGISTER_TYPE_F
:
731 case BRW_REGISTER_TYPE_DF
:
733 case BRW_REGISTER_TYPE_D
:
734 case BRW_REGISTER_TYPE_UD
:
736 case BRW_REGISTER_TYPE_UQ
:
737 case BRW_REGISTER_TYPE_Q
:
745 backend_reg::is_negative_one() const
751 case BRW_REGISTER_TYPE_F
:
753 case BRW_REGISTER_TYPE_DF
:
755 case BRW_REGISTER_TYPE_D
:
757 case BRW_REGISTER_TYPE_Q
:
765 backend_reg::is_null() const
767 return file
== ARF
&& nr
== BRW_ARF_NULL
;
772 backend_reg::is_accumulator() const
774 return file
== ARF
&& nr
== BRW_ARF_ACCUMULATOR
;
778 backend_instruction::is_commutative() const
786 case SHADER_OPCODE_MULH
:
789 /* MIN and MAX are commutative. */
790 if (conditional_mod
== BRW_CONDITIONAL_GE
||
791 conditional_mod
== BRW_CONDITIONAL_L
) {
801 backend_instruction::is_3src(const struct gen_device_info
*devinfo
) const
803 return ::is_3src(devinfo
, opcode
);
807 backend_instruction::is_tex() const
809 return (opcode
== SHADER_OPCODE_TEX
||
810 opcode
== FS_OPCODE_TXB
||
811 opcode
== SHADER_OPCODE_TXD
||
812 opcode
== SHADER_OPCODE_TXF
||
813 opcode
== SHADER_OPCODE_TXF_LZ
||
814 opcode
== SHADER_OPCODE_TXF_CMS
||
815 opcode
== SHADER_OPCODE_TXF_CMS_W
||
816 opcode
== SHADER_OPCODE_TXF_UMS
||
817 opcode
== SHADER_OPCODE_TXF_MCS
||
818 opcode
== SHADER_OPCODE_TXL
||
819 opcode
== SHADER_OPCODE_TXL_LZ
||
820 opcode
== SHADER_OPCODE_TXS
||
821 opcode
== SHADER_OPCODE_LOD
||
822 opcode
== SHADER_OPCODE_TG4
||
823 opcode
== SHADER_OPCODE_TG4_OFFSET
||
824 opcode
== SHADER_OPCODE_SAMPLEINFO
);
828 backend_instruction::is_math() const
830 return (opcode
== SHADER_OPCODE_RCP
||
831 opcode
== SHADER_OPCODE_RSQ
||
832 opcode
== SHADER_OPCODE_SQRT
||
833 opcode
== SHADER_OPCODE_EXP2
||
834 opcode
== SHADER_OPCODE_LOG2
||
835 opcode
== SHADER_OPCODE_SIN
||
836 opcode
== SHADER_OPCODE_COS
||
837 opcode
== SHADER_OPCODE_INT_QUOTIENT
||
838 opcode
== SHADER_OPCODE_INT_REMAINDER
||
839 opcode
== SHADER_OPCODE_POW
);
843 backend_instruction::is_control_flow() const
847 case BRW_OPCODE_WHILE
:
849 case BRW_OPCODE_ELSE
:
850 case BRW_OPCODE_ENDIF
:
851 case BRW_OPCODE_BREAK
:
852 case BRW_OPCODE_CONTINUE
:
860 backend_instruction::can_do_source_mods() const
863 case BRW_OPCODE_ADDC
:
865 case BRW_OPCODE_BFI1
:
866 case BRW_OPCODE_BFI2
:
867 case BRW_OPCODE_BFREV
:
868 case BRW_OPCODE_CBIT
:
871 case BRW_OPCODE_SUBB
:
872 case SHADER_OPCODE_BROADCAST
:
873 case SHADER_OPCODE_CLUSTER_BROADCAST
:
874 case SHADER_OPCODE_MOV_INDIRECT
:
882 backend_instruction::can_do_saturate() const
892 case BRW_OPCODE_F16TO32
:
893 case BRW_OPCODE_F32TO16
:
894 case BRW_OPCODE_LINE
:
898 case BRW_OPCODE_MATH
:
901 case SHADER_OPCODE_MULH
:
903 case BRW_OPCODE_RNDD
:
904 case BRW_OPCODE_RNDE
:
905 case BRW_OPCODE_RNDU
:
906 case BRW_OPCODE_RNDZ
:
910 case FS_OPCODE_LINTERP
:
911 case SHADER_OPCODE_COS
:
912 case SHADER_OPCODE_EXP2
:
913 case SHADER_OPCODE_LOG2
:
914 case SHADER_OPCODE_POW
:
915 case SHADER_OPCODE_RCP
:
916 case SHADER_OPCODE_RSQ
:
917 case SHADER_OPCODE_SIN
:
918 case SHADER_OPCODE_SQRT
:
926 backend_instruction::can_do_cmod() const
930 case BRW_OPCODE_ADDC
:
935 case BRW_OPCODE_CMPN
:
940 case BRW_OPCODE_F16TO32
:
941 case BRW_OPCODE_F32TO16
:
943 case BRW_OPCODE_LINE
:
947 case BRW_OPCODE_MACH
:
954 case BRW_OPCODE_RNDD
:
955 case BRW_OPCODE_RNDE
:
956 case BRW_OPCODE_RNDU
:
957 case BRW_OPCODE_RNDZ
:
958 case BRW_OPCODE_SAD2
:
959 case BRW_OPCODE_SADA2
:
962 case BRW_OPCODE_SUBB
:
964 case FS_OPCODE_LINTERP
:
972 backend_instruction::reads_accumulator_implicitly() const
976 case BRW_OPCODE_MACH
:
977 case BRW_OPCODE_SADA2
:
985 backend_instruction::writes_accumulator_implicitly(const struct gen_device_info
*devinfo
) const
987 return writes_accumulator
||
989 ((opcode
>= BRW_OPCODE_ADD
&& opcode
< BRW_OPCODE_NOP
) ||
990 (opcode
>= FS_OPCODE_DDX_COARSE
&& opcode
<= FS_OPCODE_LINTERP
))) ||
991 (opcode
== FS_OPCODE_LINTERP
&&
992 (!devinfo
->has_pln
|| devinfo
->gen
<= 6));
996 backend_instruction::has_side_effects() const
999 case SHADER_OPCODE_UNTYPED_ATOMIC
:
1000 case SHADER_OPCODE_UNTYPED_ATOMIC_LOGICAL
:
1001 case SHADER_OPCODE_GEN4_SCRATCH_WRITE
:
1002 case SHADER_OPCODE_UNTYPED_SURFACE_WRITE
:
1003 case SHADER_OPCODE_UNTYPED_SURFACE_WRITE_LOGICAL
:
1004 case SHADER_OPCODE_BYTE_SCATTERED_WRITE
:
1005 case SHADER_OPCODE_BYTE_SCATTERED_WRITE_LOGICAL
:
1006 case SHADER_OPCODE_TYPED_ATOMIC
:
1007 case SHADER_OPCODE_TYPED_ATOMIC_LOGICAL
:
1008 case SHADER_OPCODE_TYPED_SURFACE_WRITE
:
1009 case SHADER_OPCODE_TYPED_SURFACE_WRITE_LOGICAL
:
1010 case SHADER_OPCODE_MEMORY_FENCE
:
1011 case SHADER_OPCODE_INTERLOCK
:
1012 case SHADER_OPCODE_URB_WRITE_SIMD8
:
1013 case SHADER_OPCODE_URB_WRITE_SIMD8_PER_SLOT
:
1014 case SHADER_OPCODE_URB_WRITE_SIMD8_MASKED
:
1015 case SHADER_OPCODE_URB_WRITE_SIMD8_MASKED_PER_SLOT
:
1016 case FS_OPCODE_FB_WRITE
:
1017 case FS_OPCODE_FB_WRITE_LOGICAL
:
1018 case FS_OPCODE_REP_FB_WRITE
:
1019 case SHADER_OPCODE_BARRIER
:
1020 case TCS_OPCODE_URB_WRITE
:
1021 case TCS_OPCODE_RELEASE_INPUT
:
1022 case SHADER_OPCODE_RND_MODE
:
1030 backend_instruction::is_volatile() const
1033 case SHADER_OPCODE_UNTYPED_SURFACE_READ
:
1034 case SHADER_OPCODE_UNTYPED_SURFACE_READ_LOGICAL
:
1035 case SHADER_OPCODE_TYPED_SURFACE_READ
:
1036 case SHADER_OPCODE_TYPED_SURFACE_READ_LOGICAL
:
1037 case SHADER_OPCODE_BYTE_SCATTERED_READ
:
1038 case SHADER_OPCODE_BYTE_SCATTERED_READ_LOGICAL
:
1039 case SHADER_OPCODE_URB_READ_SIMD8
:
1040 case SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT
:
1041 case VEC4_OPCODE_URB_READ
:
1050 inst_is_in_block(const bblock_t
*block
, const backend_instruction
*inst
)
1053 foreach_inst_in_block (backend_instruction
, i
, block
) {
1063 adjust_later_block_ips(bblock_t
*start_block
, int ip_adjustment
)
1065 for (bblock_t
*block_iter
= start_block
->next();
1067 block_iter
= block_iter
->next()) {
1068 block_iter
->start_ip
+= ip_adjustment
;
1069 block_iter
->end_ip
+= ip_adjustment
;
1074 backend_instruction::insert_after(bblock_t
*block
, backend_instruction
*inst
)
1076 assert(this != inst
);
1078 if (!this->is_head_sentinel())
1079 assert(inst_is_in_block(block
, this) || !"Instruction not in block");
1083 adjust_later_block_ips(block
, 1);
1085 exec_node::insert_after(inst
);
1089 backend_instruction::insert_before(bblock_t
*block
, backend_instruction
*inst
)
1091 assert(this != inst
);
1093 if (!this->is_tail_sentinel())
1094 assert(inst_is_in_block(block
, this) || !"Instruction not in block");
1098 adjust_later_block_ips(block
, 1);
1100 exec_node::insert_before(inst
);
1104 backend_instruction::insert_before(bblock_t
*block
, exec_list
*list
)
1106 assert(inst_is_in_block(block
, this) || !"Instruction not in block");
1108 unsigned num_inst
= list
->length();
1110 block
->end_ip
+= num_inst
;
1112 adjust_later_block_ips(block
, num_inst
);
1114 exec_node::insert_before(list
);
1118 backend_instruction::remove(bblock_t
*block
)
1120 assert(inst_is_in_block(block
, this) || !"Instruction not in block");
1122 adjust_later_block_ips(block
, -1);
1124 if (block
->start_ip
== block
->end_ip
) {
1125 block
->cfg
->remove_block(block
);
1130 exec_node::remove();
1134 backend_shader::dump_instructions()
1136 dump_instructions(NULL
);
1140 backend_shader::dump_instructions(const char *name
)
1142 FILE *file
= stderr
;
1143 if (name
&& geteuid() != 0) {
1144 file
= fopen(name
, "w");
1151 foreach_block_and_inst(block
, backend_instruction
, inst
, cfg
) {
1152 if (!unlikely(INTEL_DEBUG
& DEBUG_OPTIMIZER
))
1153 fprintf(file
, "%4d: ", ip
++);
1154 dump_instruction(inst
, file
);
1158 foreach_in_list(backend_instruction
, inst
, &instructions
) {
1159 if (!unlikely(INTEL_DEBUG
& DEBUG_OPTIMIZER
))
1160 fprintf(file
, "%4d: ", ip
++);
1161 dump_instruction(inst
, file
);
1165 if (file
!= stderr
) {
1171 backend_shader::calculate_cfg()
1175 cfg
= new(mem_ctx
) cfg_t(&this->instructions
);
1178 extern "C" const unsigned *
1179 brw_compile_tes(const struct brw_compiler
*compiler
,
1182 const struct brw_tes_prog_key
*key
,
1183 const struct brw_vue_map
*input_vue_map
,
1184 struct brw_tes_prog_data
*prog_data
,
1185 const nir_shader
*src_shader
,
1186 struct gl_program
*prog
,
1187 int shader_time_index
,
1190 const struct gen_device_info
*devinfo
= compiler
->devinfo
;
1191 const bool is_scalar
= compiler
->scalar_stage
[MESA_SHADER_TESS_EVAL
];
1192 const unsigned *assembly
;
1194 nir_shader
*nir
= nir_shader_clone(mem_ctx
, src_shader
);
1195 nir
->info
.inputs_read
= key
->inputs_read
;
1196 nir
->info
.patch_inputs_read
= key
->patch_inputs_read
;
1198 nir
= brw_nir_apply_sampler_key(nir
, compiler
, &key
->tex
, is_scalar
);
1199 brw_nir_lower_tes_inputs(nir
, input_vue_map
);
1200 brw_nir_lower_vue_outputs(nir
, is_scalar
);
1201 nir
= brw_postprocess_nir(nir
, compiler
, is_scalar
);
1203 brw_compute_vue_map(devinfo
, &prog_data
->base
.vue_map
,
1204 nir
->info
.outputs_written
,
1205 nir
->info
.separate_shader
);
1207 unsigned output_size_bytes
= prog_data
->base
.vue_map
.num_slots
* 4 * 4;
1209 assert(output_size_bytes
>= 1);
1210 if (output_size_bytes
> GEN7_MAX_DS_URB_ENTRY_SIZE_BYTES
) {
1212 *error_str
= ralloc_strdup(mem_ctx
, "DS outputs exceed maximum size");
1216 prog_data
->base
.clip_distance_mask
=
1217 ((1 << nir
->info
.clip_distance_array_size
) - 1);
1218 prog_data
->base
.cull_distance_mask
=
1219 ((1 << nir
->info
.cull_distance_array_size
) - 1) <<
1220 nir
->info
.clip_distance_array_size
;
1222 /* URB entry sizes are stored as a multiple of 64 bytes. */
1223 prog_data
->base
.urb_entry_size
= ALIGN(output_size_bytes
, 64) / 64;
1225 /* On Cannonlake software shall not program an allocation size that
1226 * specifies a size that is a multiple of 3 64B (512-bit) cachelines.
1228 if (devinfo
->gen
== 10 &&
1229 prog_data
->base
.urb_entry_size
% 3 == 0)
1230 prog_data
->base
.urb_entry_size
++;
1232 prog_data
->base
.urb_read_length
= 0;
1234 STATIC_ASSERT(BRW_TESS_PARTITIONING_INTEGER
== TESS_SPACING_EQUAL
- 1);
1235 STATIC_ASSERT(BRW_TESS_PARTITIONING_ODD_FRACTIONAL
==
1236 TESS_SPACING_FRACTIONAL_ODD
- 1);
1237 STATIC_ASSERT(BRW_TESS_PARTITIONING_EVEN_FRACTIONAL
==
1238 TESS_SPACING_FRACTIONAL_EVEN
- 1);
1240 prog_data
->partitioning
=
1241 (enum brw_tess_partitioning
) (nir
->info
.tess
.spacing
- 1);
1243 switch (nir
->info
.tess
.primitive_mode
) {
1245 prog_data
->domain
= BRW_TESS_DOMAIN_QUAD
;
1248 prog_data
->domain
= BRW_TESS_DOMAIN_TRI
;
1251 prog_data
->domain
= BRW_TESS_DOMAIN_ISOLINE
;
1254 unreachable("invalid domain shader primitive mode");
1257 if (nir
->info
.tess
.point_mode
) {
1258 prog_data
->output_topology
= BRW_TESS_OUTPUT_TOPOLOGY_POINT
;
1259 } else if (nir
->info
.tess
.primitive_mode
== GL_ISOLINES
) {
1260 prog_data
->output_topology
= BRW_TESS_OUTPUT_TOPOLOGY_LINE
;
1262 /* Hardware winding order is backwards from OpenGL */
1263 prog_data
->output_topology
=
1264 nir
->info
.tess
.ccw
? BRW_TESS_OUTPUT_TOPOLOGY_TRI_CW
1265 : BRW_TESS_OUTPUT_TOPOLOGY_TRI_CCW
;
1268 if (unlikely(INTEL_DEBUG
& DEBUG_TES
)) {
1269 fprintf(stderr
, "TES Input ");
1270 brw_print_vue_map(stderr
, input_vue_map
);
1271 fprintf(stderr
, "TES Output ");
1272 brw_print_vue_map(stderr
, &prog_data
->base
.vue_map
);
1276 fs_visitor
v(compiler
, log_data
, mem_ctx
, (void *) key
,
1277 &prog_data
->base
.base
, NULL
, nir
, 8,
1278 shader_time_index
, input_vue_map
);
1281 *error_str
= ralloc_strdup(mem_ctx
, v
.fail_msg
);
1285 prog_data
->base
.base
.dispatch_grf_start_reg
= v
.payload
.num_regs
;
1286 prog_data
->base
.dispatch_mode
= DISPATCH_MODE_SIMD8
;
1288 fs_generator
g(compiler
, log_data
, mem_ctx
,
1289 &prog_data
->base
.base
, v
.promoted_constants
, false,
1290 MESA_SHADER_TESS_EVAL
);
1291 if (unlikely(INTEL_DEBUG
& DEBUG_TES
)) {
1292 g
.enable_debug(ralloc_asprintf(mem_ctx
,
1293 "%s tessellation evaluation shader %s",
1294 nir
->info
.label
? nir
->info
.label
1299 g
.generate_code(v
.cfg
, 8);
1301 assembly
= g
.get_assembly();
1303 brw::vec4_tes_visitor
v(compiler
, log_data
, key
, prog_data
,
1304 nir
, mem_ctx
, shader_time_index
);
1307 *error_str
= ralloc_strdup(mem_ctx
, v
.fail_msg
);
1311 if (unlikely(INTEL_DEBUG
& DEBUG_TES
))
1312 v
.dump_instructions();
1314 assembly
= brw_vec4_generate_assembly(compiler
, log_data
, mem_ctx
, nir
,
1315 &prog_data
->base
, v
.cfg
);