src/intel/compiler/brw_shader.cpp

   1 /*
   2  * Copyright © 2010 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  */
  23
  24 #include "brw_cfg.h"
  25 #include "brw_eu.h"
  26 #include "brw_fs.h"
  27 #include "brw_nir.h"
  28 #include "brw_vec4_tes.h"
  29 #include "common/gen_debug.h"
  30 #include "main/uniforms.h"
  31 #include "util/macros.h"
  32
  33 enum brw_reg_type
  34 brw_type_for_base_type(const struct glsl_type *type)
  35 {
  36    switch (type->base_type) {
  37    case GLSL_TYPE_FLOAT16:
  38       return BRW_REGISTER_TYPE_HF;
  39    case GLSL_TYPE_FLOAT:
  40       return BRW_REGISTER_TYPE_F;
  41    case GLSL_TYPE_INT:
  42    case GLSL_TYPE_BOOL:
  43    case GLSL_TYPE_SUBROUTINE:
  44       return BRW_REGISTER_TYPE_D;
  45    case GLSL_TYPE_INT16:
  46       return BRW_REGISTER_TYPE_W;
  47    case GLSL_TYPE_INT8:
  48       return BRW_REGISTER_TYPE_B;
  49    case GLSL_TYPE_UINT:
  50       return BRW_REGISTER_TYPE_UD;
  51    case GLSL_TYPE_UINT16:
  52       return BRW_REGISTER_TYPE_UW;
  53    case GLSL_TYPE_UINT8:
  54       return BRW_REGISTER_TYPE_UB;
  55    case GLSL_TYPE_ARRAY:
  56       return brw_type_for_base_type(type->fields.array);
  57    case GLSL_TYPE_STRUCT:
  58    case GLSL_TYPE_SAMPLER:
  59    case GLSL_TYPE_ATOMIC_UINT:
  60       /* These should be overridden with the type of the member when
  61        * dereferenced into.  BRW_REGISTER_TYPE_UD seems like a likely
  62        * way to trip up if we don't.
  63        */
  64       return BRW_REGISTER_TYPE_UD;
  65    case GLSL_TYPE_IMAGE:
  66       return BRW_REGISTER_TYPE_UD;
  67    case GLSL_TYPE_DOUBLE:
  68       return BRW_REGISTER_TYPE_DF;
  69    case GLSL_TYPE_UINT64:
  70       return BRW_REGISTER_TYPE_UQ;
  71    case GLSL_TYPE_INT64:
  72       return BRW_REGISTER_TYPE_Q;
  73    case GLSL_TYPE_VOID:
  74    case GLSL_TYPE_ERROR:
  75    case GLSL_TYPE_INTERFACE:
  76    case GLSL_TYPE_FUNCTION:
  77       unreachable("not reached");
  78    }
  79
  80    return BRW_REGISTER_TYPE_F;
  81 }
  82
  83 enum brw_conditional_mod
  84 brw_conditional_for_comparison(unsigned int op)
  85 {
  86    switch (op) {
  87    case ir_binop_less:
  88       return BRW_CONDITIONAL_L;
  89    case ir_binop_gequal:
  90       return BRW_CONDITIONAL_GE;
  91    case ir_binop_equal:
  92    case ir_binop_all_equal: /* same as equal for scalars */
  93       return BRW_CONDITIONAL_Z;
  94    case ir_binop_nequal:
  95    case ir_binop_any_nequal: /* same as nequal for scalars */
  96       return BRW_CONDITIONAL_NZ;
  97    default:
  98       unreachable("not reached: bad operation for comparison");
  99    }
 100 }
 101
 102 uint32_t
 103 brw_math_function(enum opcode op)
 104 {
 105    switch (op) {
 106    case SHADER_OPCODE_RCP:
 107       return BRW_MATH_FUNCTION_INV;
 108    case SHADER_OPCODE_RSQ:
 109       return BRW_MATH_FUNCTION_RSQ;
 110    case SHADER_OPCODE_SQRT:
 111       return BRW_MATH_FUNCTION_SQRT;
 112    case SHADER_OPCODE_EXP2:
 113       return BRW_MATH_FUNCTION_EXP;
 114    case SHADER_OPCODE_LOG2:
 115       return BRW_MATH_FUNCTION_LOG;
 116    case SHADER_OPCODE_POW:
 117       return BRW_MATH_FUNCTION_POW;
 118    case SHADER_OPCODE_SIN:
 119       return BRW_MATH_FUNCTION_SIN;
 120    case SHADER_OPCODE_COS:
 121       return BRW_MATH_FUNCTION_COS;
 122    case SHADER_OPCODE_INT_QUOTIENT:
 123       return BRW_MATH_FUNCTION_INT_DIV_QUOTIENT;
 124    case SHADER_OPCODE_INT_REMAINDER:
 125       return BRW_MATH_FUNCTION_INT_DIV_REMAINDER;
 126    default:
 127       unreachable("not reached: unknown math function");
 128    }
 129 }
 130
 131 bool
 132 brw_texture_offset(int *offsets, unsigned num_components, uint32_t *offset_bits)
 133 {
 134    if (!offsets) return false;  /* nonconstant offset; caller will handle it. */
 135
 136    /* offset out of bounds; caller will handle it. */
 137    for (unsigned i = 0; i < num_components; i++)
 138       if (offsets[i] > 7 || offsets[i] < -8)
 139          return false;
 140
 141    /* Combine all three offsets into a single unsigned dword:
 142     *
 143     *    bits 11:8 - U Offset (X component)
 144     *    bits  7:4 - V Offset (Y component)
 145     *    bits  3:0 - R Offset (Z component)
 146     */
 147    *offset_bits = 0;
 148    for (unsigned i = 0; i < num_components; i++) {
 149       const unsigned shift = 4 * (2 - i);
 150       *offset_bits |= (offsets[i] << shift) & (0xF << shift);
 151    }
 152    return true;
 153 }
 154
 155 const char *
 156 brw_instruction_name(const struct gen_device_info *devinfo, enum opcode op)
 157 {
 158    switch (op) {
 159    case BRW_OPCODE_ILLEGAL ... BRW_OPCODE_NOP:
 160       /* The DO instruction doesn't exist on Gen6+, but we use it to mark the
 161        * start of a loop in the IR.
 162        */
 163       if (devinfo->gen >= 6 && op == BRW_OPCODE_DO)
 164          return "do";
 165
 166       /* The following conversion opcodes doesn't exist on Gen8+, but we use
 167        * then to mark that we want to do the conversion.
 168        */
 169       if (devinfo->gen > 7 && op == BRW_OPCODE_F32TO16)
 170          return "f32to16";
 171
 172       if (devinfo->gen > 7 && op == BRW_OPCODE_F16TO32)
 173          return "f16to32";
 174
 175       assert(brw_opcode_desc(devinfo, op)->name);
 176       return brw_opcode_desc(devinfo, op)->name;
 177    case FS_OPCODE_FB_WRITE:
 178       return "fb_write";
 179    case FS_OPCODE_FB_WRITE_LOGICAL:
 180       return "fb_write_logical";
 181    case FS_OPCODE_REP_FB_WRITE:
 182       return "rep_fb_write";
 183    case FS_OPCODE_FB_READ:
 184       return "fb_read";
 185    case FS_OPCODE_FB_READ_LOGICAL:
 186       return "fb_read_logical";
 187
 188    case SHADER_OPCODE_RCP:
 189       return "rcp";
 190    case SHADER_OPCODE_RSQ:
 191       return "rsq";
 192    case SHADER_OPCODE_SQRT:
 193       return "sqrt";
 194    case SHADER_OPCODE_EXP2:
 195       return "exp2";
 196    case SHADER_OPCODE_LOG2:
 197       return "log2";
 198    case SHADER_OPCODE_POW:
 199       return "pow";
 200    case SHADER_OPCODE_INT_QUOTIENT:
 201       return "int_quot";
 202    case SHADER_OPCODE_INT_REMAINDER:
 203       return "int_rem";
 204    case SHADER_OPCODE_SIN:
 205       return "sin";
 206    case SHADER_OPCODE_COS:
 207       return "cos";
 208
 209    case SHADER_OPCODE_TEX:
 210       return "tex";
 211    case SHADER_OPCODE_TEX_LOGICAL:
 212       return "tex_logical";
 213    case SHADER_OPCODE_TXD:
 214       return "txd";
 215    case SHADER_OPCODE_TXD_LOGICAL:
 216       return "txd_logical";
 217    case SHADER_OPCODE_TXF:
 218       return "txf";
 219    case SHADER_OPCODE_TXF_LOGICAL:
 220       return "txf_logical";
 221    case SHADER_OPCODE_TXF_LZ:
 222       return "txf_lz";
 223    case SHADER_OPCODE_TXL:
 224       return "txl";
 225    case SHADER_OPCODE_TXL_LOGICAL:
 226       return "txl_logical";
 227    case SHADER_OPCODE_TXL_LZ:
 228       return "txl_lz";
 229    case SHADER_OPCODE_TXS:
 230       return "txs";
 231    case SHADER_OPCODE_TXS_LOGICAL:
 232       return "txs_logical";
 233    case FS_OPCODE_TXB:
 234       return "txb";
 235    case FS_OPCODE_TXB_LOGICAL:
 236       return "txb_logical";
 237    case SHADER_OPCODE_TXF_CMS:
 238       return "txf_cms";
 239    case SHADER_OPCODE_TXF_CMS_LOGICAL:
 240       return "txf_cms_logical";
 241    case SHADER_OPCODE_TXF_CMS_W:
 242       return "txf_cms_w";
 243    case SHADER_OPCODE_TXF_CMS_W_LOGICAL:
 244       return "txf_cms_w_logical";
 245    case SHADER_OPCODE_TXF_UMS:
 246       return "txf_ums";
 247    case SHADER_OPCODE_TXF_UMS_LOGICAL:
 248       return "txf_ums_logical";
 249    case SHADER_OPCODE_TXF_MCS:
 250       return "txf_mcs";
 251    case SHADER_OPCODE_TXF_MCS_LOGICAL:
 252       return "txf_mcs_logical";
 253    case SHADER_OPCODE_LOD:
 254       return "lod";
 255    case SHADER_OPCODE_LOD_LOGICAL:
 256       return "lod_logical";
 257    case SHADER_OPCODE_TG4:
 258       return "tg4";
 259    case SHADER_OPCODE_TG4_LOGICAL:
 260       return "tg4_logical";
 261    case SHADER_OPCODE_TG4_OFFSET:
 262       return "tg4_offset";
 263    case SHADER_OPCODE_TG4_OFFSET_LOGICAL:
 264       return "tg4_offset_logical";
 265    case SHADER_OPCODE_SAMPLEINFO:
 266       return "sampleinfo";
 267    case SHADER_OPCODE_SAMPLEINFO_LOGICAL:
 268       return "sampleinfo_logical";
 269
 270    case SHADER_OPCODE_IMAGE_SIZE:
 271       return "image_size";
 272
 273    case SHADER_OPCODE_SHADER_TIME_ADD:
 274       return "shader_time_add";
 275
 276    case SHADER_OPCODE_UNTYPED_ATOMIC:
 277       return "untyped_atomic";
 278    case SHADER_OPCODE_UNTYPED_ATOMIC_LOGICAL:
 279       return "untyped_atomic_logical";
 280    case SHADER_OPCODE_UNTYPED_ATOMIC_FLOAT:
 281       return "untyped_atomic_float";
 282    case SHADER_OPCODE_UNTYPED_ATOMIC_FLOAT_LOGICAL:
 283       return "untyped_atomic_float_logical";
 284    case SHADER_OPCODE_UNTYPED_SURFACE_READ:
 285       return "untyped_surface_read";
 286    case SHADER_OPCODE_UNTYPED_SURFACE_READ_LOGICAL:
 287       return "untyped_surface_read_logical";
 288    case SHADER_OPCODE_UNTYPED_SURFACE_WRITE:
 289       return "untyped_surface_write";
 290    case SHADER_OPCODE_UNTYPED_SURFACE_WRITE_LOGICAL:
 291       return "untyped_surface_write_logical";
 292    case SHADER_OPCODE_TYPED_ATOMIC:
 293       return "typed_atomic";
 294    case SHADER_OPCODE_TYPED_ATOMIC_LOGICAL:
 295       return "typed_atomic_logical";
 296    case SHADER_OPCODE_TYPED_SURFACE_READ:
 297       return "typed_surface_read";
 298    case SHADER_OPCODE_TYPED_SURFACE_READ_LOGICAL:
 299       return "typed_surface_read_logical";
 300    case SHADER_OPCODE_TYPED_SURFACE_WRITE:
 301       return "typed_surface_write";
 302    case SHADER_OPCODE_TYPED_SURFACE_WRITE_LOGICAL:
 303       return "typed_surface_write_logical";
 304    case SHADER_OPCODE_MEMORY_FENCE:
 305       return "memory_fence";
 306    case SHADER_OPCODE_INTERLOCK:
 307       /* For an interlock we actually issue a memory fence via sendc. */
 308       return "interlock";
 309
 310    case SHADER_OPCODE_BYTE_SCATTERED_READ:
 311       return "byte_scattered_read";
 312    case SHADER_OPCODE_BYTE_SCATTERED_READ_LOGICAL:
 313       return "byte_scattered_read_logical";
 314    case SHADER_OPCODE_BYTE_SCATTERED_WRITE:
 315       return "byte_scattered_write";
 316    case SHADER_OPCODE_BYTE_SCATTERED_WRITE_LOGICAL:
 317       return "byte_scattered_write_logical";
 318
 319    case SHADER_OPCODE_LOAD_PAYLOAD:
 320       return "load_payload";
 321    case FS_OPCODE_PACK:
 322       return "pack";
 323
 324    case SHADER_OPCODE_GEN4_SCRATCH_READ:
 325       return "gen4_scratch_read";
 326    case SHADER_OPCODE_GEN4_SCRATCH_WRITE:
 327       return "gen4_scratch_write";
 328    case SHADER_OPCODE_GEN7_SCRATCH_READ:
 329       return "gen7_scratch_read";
 330    case SHADER_OPCODE_URB_WRITE_SIMD8:
 331       return "gen8_urb_write_simd8";
 332    case SHADER_OPCODE_URB_WRITE_SIMD8_PER_SLOT:
 333       return "gen8_urb_write_simd8_per_slot";
 334    case SHADER_OPCODE_URB_WRITE_SIMD8_MASKED:
 335       return "gen8_urb_write_simd8_masked";
 336    case SHADER_OPCODE_URB_WRITE_SIMD8_MASKED_PER_SLOT:
 337       return "gen8_urb_write_simd8_masked_per_slot";
 338    case SHADER_OPCODE_URB_READ_SIMD8:
 339       return "urb_read_simd8";
 340    case SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT:
 341       return "urb_read_simd8_per_slot";
 342
 343    case SHADER_OPCODE_FIND_LIVE_CHANNEL:
 344       return "find_live_channel";
 345    case SHADER_OPCODE_BROADCAST:
 346       return "broadcast";
 347    case SHADER_OPCODE_SHUFFLE:
 348       return "shuffle";
 349    case SHADER_OPCODE_SEL_EXEC:
 350       return "sel_exec";
 351    case SHADER_OPCODE_QUAD_SWIZZLE:
 352       return "quad_swizzle";
 353    case SHADER_OPCODE_CLUSTER_BROADCAST:
 354       return "cluster_broadcast";
 355
 356    case SHADER_OPCODE_GET_BUFFER_SIZE:
 357       return "get_buffer_size";
 358
 359    case VEC4_OPCODE_MOV_BYTES:
 360       return "mov_bytes";
 361    case VEC4_OPCODE_PACK_BYTES:
 362       return "pack_bytes";
 363    case VEC4_OPCODE_UNPACK_UNIFORM:
 364       return "unpack_uniform";
 365    case VEC4_OPCODE_DOUBLE_TO_F32:
 366       return "double_to_f32";
 367    case VEC4_OPCODE_DOUBLE_TO_D32:
 368       return "double_to_d32";
 369    case VEC4_OPCODE_DOUBLE_TO_U32:
 370       return "double_to_u32";
 371    case VEC4_OPCODE_TO_DOUBLE:
 372       return "single_to_double";
 373    case VEC4_OPCODE_PICK_LOW_32BIT:
 374       return "pick_low_32bit";
 375    case VEC4_OPCODE_PICK_HIGH_32BIT:
 376       return "pick_high_32bit";
 377    case VEC4_OPCODE_SET_LOW_32BIT:
 378       return "set_low_32bit";
 379    case VEC4_OPCODE_SET_HIGH_32BIT:
 380       return "set_high_32bit";
 381
 382    case FS_OPCODE_DDX_COARSE:
 383       return "ddx_coarse";
 384    case FS_OPCODE_DDX_FINE:
 385       return "ddx_fine";
 386    case FS_OPCODE_DDY_COARSE:
 387       return "ddy_coarse";
 388    case FS_OPCODE_DDY_FINE:
 389       return "ddy_fine";
 390
 391    case FS_OPCODE_LINTERP:
 392       return "linterp";
 393
 394    case FS_OPCODE_PIXEL_X:
 395       return "pixel_x";
 396    case FS_OPCODE_PIXEL_Y:
 397       return "pixel_y";
 398
 399    case FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD:
 400       return "uniform_pull_const";
 401    case FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD_GEN7:
 402       return "uniform_pull_const_gen7";
 403    case FS_OPCODE_VARYING_PULL_CONSTANT_LOAD_GEN4:
 404       return "varying_pull_const_gen4";
 405    case FS_OPCODE_VARYING_PULL_CONSTANT_LOAD_GEN7:
 406       return "varying_pull_const_gen7";
 407    case FS_OPCODE_VARYING_PULL_CONSTANT_LOAD_LOGICAL:
 408       return "varying_pull_const_logical";
 409
 410    case FS_OPCODE_DISCARD_JUMP:
 411       return "discard_jump";
 412
 413    case FS_OPCODE_SET_SAMPLE_ID:
 414       return "set_sample_id";
 415
 416    case FS_OPCODE_PACK_HALF_2x16_SPLIT:
 417       return "pack_half_2x16_split";
 418
 419    case FS_OPCODE_PLACEHOLDER_HALT:
 420       return "placeholder_halt";
 421
 422    case FS_OPCODE_INTERPOLATE_AT_SAMPLE:
 423       return "interp_sample";
 424    case FS_OPCODE_INTERPOLATE_AT_SHARED_OFFSET:
 425       return "interp_shared_offset";
 426    case FS_OPCODE_INTERPOLATE_AT_PER_SLOT_OFFSET:
 427       return "interp_per_slot_offset";
 428
 429    case VS_OPCODE_URB_WRITE:
 430       return "vs_urb_write";
 431    case VS_OPCODE_PULL_CONSTANT_LOAD:
 432       return "pull_constant_load";
 433    case VS_OPCODE_PULL_CONSTANT_LOAD_GEN7:
 434       return "pull_constant_load_gen7";
 435
 436    case VS_OPCODE_SET_SIMD4X2_HEADER_GEN9:
 437       return "set_simd4x2_header_gen9";
 438
 439    case VS_OPCODE_UNPACK_FLAGS_SIMD4X2:
 440       return "unpack_flags_simd4x2";
 441
 442    case GS_OPCODE_URB_WRITE:
 443       return "gs_urb_write";
 444    case GS_OPCODE_URB_WRITE_ALLOCATE:
 445       return "gs_urb_write_allocate";
 446    case GS_OPCODE_THREAD_END:
 447       return "gs_thread_end";
 448    case GS_OPCODE_SET_WRITE_OFFSET:
 449       return "set_write_offset";
 450    case GS_OPCODE_SET_VERTEX_COUNT:
 451       return "set_vertex_count";
 452    case GS_OPCODE_SET_DWORD_2:
 453       return "set_dword_2";
 454    case GS_OPCODE_PREPARE_CHANNEL_MASKS:
 455       return "prepare_channel_masks";
 456    case GS_OPCODE_SET_CHANNEL_MASKS:
 457       return "set_channel_masks";
 458    case GS_OPCODE_GET_INSTANCE_ID:
 459       return "get_instance_id";
 460    case GS_OPCODE_FF_SYNC:
 461       return "ff_sync";
 462    case GS_OPCODE_SET_PRIMITIVE_ID:
 463       return "set_primitive_id";
 464    case GS_OPCODE_SVB_WRITE:
 465       return "gs_svb_write";
 466    case GS_OPCODE_SVB_SET_DST_INDEX:
 467       return "gs_svb_set_dst_index";
 468    case GS_OPCODE_FF_SYNC_SET_PRIMITIVES:
 469       return "gs_ff_sync_set_primitives";
 470    case CS_OPCODE_CS_TERMINATE:
 471       return "cs_terminate";
 472    case SHADER_OPCODE_BARRIER:
 473       return "barrier";
 474    case SHADER_OPCODE_MULH:
 475       return "mulh";
 476    case SHADER_OPCODE_MOV_INDIRECT:
 477       return "mov_indirect";
 478
 479    case VEC4_OPCODE_URB_READ:
 480       return "urb_read";
 481    case TCS_OPCODE_GET_INSTANCE_ID:
 482       return "tcs_get_instance_id";
 483    case TCS_OPCODE_URB_WRITE:
 484       return "tcs_urb_write";
 485    case TCS_OPCODE_SET_INPUT_URB_OFFSETS:
 486       return "tcs_set_input_urb_offsets";
 487    case TCS_OPCODE_SET_OUTPUT_URB_OFFSETS:
 488       return "tcs_set_output_urb_offsets";
 489    case TCS_OPCODE_GET_PRIMITIVE_ID:
 490       return "tcs_get_primitive_id";
 491    case TCS_OPCODE_CREATE_BARRIER_HEADER:
 492       return "tcs_create_barrier_header";
 493    case TCS_OPCODE_SRC0_010_IS_ZERO:
 494       return "tcs_src0<0,1,0>_is_zero";
 495    case TCS_OPCODE_RELEASE_INPUT:
 496       return "tcs_release_input";
 497    case TCS_OPCODE_THREAD_END:
 498       return "tcs_thread_end";
 499    case TES_OPCODE_CREATE_INPUT_READ_HEADER:
 500       return "tes_create_input_read_header";
 501    case TES_OPCODE_ADD_INDIRECT_URB_OFFSET:
 502       return "tes_add_indirect_urb_offset";
 503    case TES_OPCODE_GET_PRIMITIVE_ID:
 504       return "tes_get_primitive_id";
 505
 506    case SHADER_OPCODE_RND_MODE:
 507       return "rnd_mode";
 508    }
 509
 510    unreachable("not reached");
 511 }
 512
 513 bool
 514 brw_saturate_immediate(enum brw_reg_type type, struct brw_reg *reg)
 515 {
 516    union {
 517       unsigned ud;
 518       int d;
 519       float f;
 520       double df;
 521    } imm, sat_imm = { 0 };
 522
 523    const unsigned size = type_sz(type);
 524
 525    /* We want to either do a 32-bit or 64-bit data copy, the type is otherwise
 526     * irrelevant, so just check the size of the type and copy from/to an
 527     * appropriately sized field.
 528     */
 529    if (size < 8)
 530       imm.ud = reg->ud;
 531    else
 532       imm.df = reg->df;
 533
 534    switch (type) {
 535    case BRW_REGISTER_TYPE_UD:
 536    case BRW_REGISTER_TYPE_D:
 537    case BRW_REGISTER_TYPE_UW:
 538    case BRW_REGISTER_TYPE_W:
 539    case BRW_REGISTER_TYPE_UQ:
 540    case BRW_REGISTER_TYPE_Q:
 541       /* Nothing to do. */
 542       return false;
 543    case BRW_REGISTER_TYPE_F:
 544       sat_imm.f = CLAMP(imm.f, 0.0f, 1.0f);
 545       break;
 546    case BRW_REGISTER_TYPE_DF:
 547       sat_imm.df = CLAMP(imm.df, 0.0, 1.0);
 548       break;
 549    case BRW_REGISTER_TYPE_UB:
 550    case BRW_REGISTER_TYPE_B:
 551       unreachable("no UB/B immediates");
 552    case BRW_REGISTER_TYPE_V:
 553    case BRW_REGISTER_TYPE_UV:
 554    case BRW_REGISTER_TYPE_VF:
 555       unreachable("unimplemented: saturate vector immediate");
 556    case BRW_REGISTER_TYPE_HF:
 557       unreachable("unimplemented: saturate HF immediate");
 558    case BRW_REGISTER_TYPE_NF:
 559       unreachable("no NF immediates");
 560    }
 561
 562    if (size < 8) {
 563       if (imm.ud != sat_imm.ud) {
 564          reg->ud = sat_imm.ud;
 565          return true;
 566       }
 567    } else {
 568       if (imm.df != sat_imm.df) {
 569          reg->df = sat_imm.df;
 570          return true;
 571       }
 572    }
 573    return false;
 574 }
 575
 576 bool
 577 brw_negate_immediate(enum brw_reg_type type, struct brw_reg *reg)
 578 {
 579    switch (type) {
 580    case BRW_REGISTER_TYPE_D:
 581    case BRW_REGISTER_TYPE_UD:
 582       reg->d = -reg->d;
 583       return true;
 584    case BRW_REGISTER_TYPE_W:
 585    case BRW_REGISTER_TYPE_UW: {
 586       uint16_t value = -(int16_t)reg->ud;
 587       reg->ud = value | (uint32_t)value << 16;
 588       return true;
 589    }
 590    case BRW_REGISTER_TYPE_F:
 591       reg->f = -reg->f;
 592       return true;
 593    case BRW_REGISTER_TYPE_VF:
 594       reg->ud ^= 0x80808080;
 595       return true;
 596    case BRW_REGISTER_TYPE_DF:
 597       reg->df = -reg->df;
 598       return true;
 599    case BRW_REGISTER_TYPE_UQ:
 600    case BRW_REGISTER_TYPE_Q:
 601       reg->d64 = -reg->d64;
 602       return true;
 603    case BRW_REGISTER_TYPE_UB:
 604    case BRW_REGISTER_TYPE_B:
 605       unreachable("no UB/B immediates");
 606    case BRW_REGISTER_TYPE_UV:
 607    case BRW_REGISTER_TYPE_V:
 608       assert(!"unimplemented: negate UV/V immediate");
 609    case BRW_REGISTER_TYPE_HF:
 610       reg->ud ^= 0x80008000;
 611       return true;
 612    case BRW_REGISTER_TYPE_NF:
 613       unreachable("no NF immediates");
 614    }
 615
 616    return false;
 617 }
 618
 619 bool
 620 brw_abs_immediate(enum brw_reg_type type, struct brw_reg *reg)
 621 {
 622    switch (type) {
 623    case BRW_REGISTER_TYPE_D:
 624       reg->d = abs(reg->d);
 625       return true;
 626    case BRW_REGISTER_TYPE_W: {
 627       uint16_t value = abs((int16_t)reg->ud);
 628       reg->ud = value | (uint32_t)value << 16;
 629       return true;
 630    }
 631    case BRW_REGISTER_TYPE_F:
 632       reg->f = fabsf(reg->f);
 633       return true;
 634    case BRW_REGISTER_TYPE_DF:
 635       reg->df = fabs(reg->df);
 636       return true;
 637    case BRW_REGISTER_TYPE_VF:
 638       reg->ud &= ~0x80808080;
 639       return true;
 640    case BRW_REGISTER_TYPE_Q:
 641       reg->d64 = imaxabs(reg->d64);
 642       return true;
 643    case BRW_REGISTER_TYPE_UB:
 644    case BRW_REGISTER_TYPE_B:
 645       unreachable("no UB/B immediates");
 646    case BRW_REGISTER_TYPE_UQ:
 647    case BRW_REGISTER_TYPE_UD:
 648    case BRW_REGISTER_TYPE_UW:
 649    case BRW_REGISTER_TYPE_UV:
 650       /* Presumably the absolute value modifier on an unsigned source is a
 651        * nop, but it would be nice to confirm.
 652        */
 653       assert(!"unimplemented: abs unsigned immediate");
 654    case BRW_REGISTER_TYPE_V:
 655       assert(!"unimplemented: abs V immediate");
 656    case BRW_REGISTER_TYPE_HF:
 657       reg->ud &= ~0x80008000;
 658       return true;
 659    case BRW_REGISTER_TYPE_NF:
 660       unreachable("no NF immediates");
 661    }
 662
 663    return false;
 664 }
 665
 666 backend_shader::backend_shader(const struct brw_compiler *compiler,
 667                                void *log_data,
 668                                void *mem_ctx,
 669                                const nir_shader *shader,
 670                                struct brw_stage_prog_data *stage_prog_data)
 671    : compiler(compiler),
 672      log_data(log_data),
 673      devinfo(compiler->devinfo),
 674      nir(shader),
 675      stage_prog_data(stage_prog_data),
 676      mem_ctx(mem_ctx),
 677      cfg(NULL),
 678      stage(shader->info.stage)
 679 {
 680    debug_enabled = INTEL_DEBUG & intel_debug_flag_for_shader_stage(stage);
 681    stage_name = _mesa_shader_stage_to_string(stage);
 682    stage_abbrev = _mesa_shader_stage_to_abbrev(stage);
 683 }
 684
 685 backend_shader::~backend_shader()
 686 {
 687 }
 688
 689 bool
 690 backend_reg::equals(const backend_reg &r) const
 691 {
 692    return brw_regs_equal(this, &r) && offset == r.offset;
 693 }
 694
 695 bool
 696 backend_reg::negative_equals(const backend_reg &r) const
 697 {
 698    return brw_regs_negative_equal(this, &r) && offset == r.offset;
 699 }
 700
 701 bool
 702 backend_reg::is_zero() const
 703 {
 704    if (file != IMM)
 705       return false;
 706
 707    switch (type) {
 708    case BRW_REGISTER_TYPE_F:
 709       return f == 0;
 710    case BRW_REGISTER_TYPE_DF:
 711       return df == 0;
 712    case BRW_REGISTER_TYPE_D:
 713    case BRW_REGISTER_TYPE_UD:
 714       return d == 0;
 715    case BRW_REGISTER_TYPE_UQ:
 716    case BRW_REGISTER_TYPE_Q:
 717       return u64 == 0;
 718    default:
 719       return false;
 720    }
 721 }
 722
 723 bool
 724 backend_reg::is_one() const
 725 {
 726    if (file != IMM)
 727       return false;
 728
 729    switch (type) {
 730    case BRW_REGISTER_TYPE_F:
 731       return f == 1.0f;
 732    case BRW_REGISTER_TYPE_DF:
 733       return df == 1.0;
 734    case BRW_REGISTER_TYPE_D:
 735    case BRW_REGISTER_TYPE_UD:
 736       return d == 1;
 737    case BRW_REGISTER_TYPE_UQ:
 738    case BRW_REGISTER_TYPE_Q:
 739       return u64 == 1;
 740    default:
 741       return false;
 742    }
 743 }
 744
 745 bool
 746 backend_reg::is_negative_one() const
 747 {
 748    if (file != IMM)
 749       return false;
 750
 751    switch (type) {
 752    case BRW_REGISTER_TYPE_F:
 753       return f == -1.0;
 754    case BRW_REGISTER_TYPE_DF:
 755       return df == -1.0;
 756    case BRW_REGISTER_TYPE_D:
 757       return d == -1;
 758    case BRW_REGISTER_TYPE_Q:
 759       return d64 == -1;
 760    default:
 761       return false;
 762    }
 763 }
 764
 765 bool
 766 backend_reg::is_null() const
 767 {
 768    return file == ARF && nr == BRW_ARF_NULL;
 769 }
 770
 771
 772 bool
 773 backend_reg::is_accumulator() const
 774 {
 775    return file == ARF && nr == BRW_ARF_ACCUMULATOR;
 776 }
 777
 778 bool
 779 backend_instruction::is_commutative() const
 780 {
 781    switch (opcode) {
 782    case BRW_OPCODE_AND:
 783    case BRW_OPCODE_OR:
 784    case BRW_OPCODE_XOR:
 785    case BRW_OPCODE_ADD:
 786    case BRW_OPCODE_MUL:
 787    case SHADER_OPCODE_MULH:
 788       return true;
 789    case BRW_OPCODE_SEL:
 790       /* MIN and MAX are commutative. */
 791       if (conditional_mod == BRW_CONDITIONAL_GE ||
 792           conditional_mod == BRW_CONDITIONAL_L) {
 793          return true;
 794       }
 795       /* fallthrough */
 796    default:
 797       return false;
 798    }
 799 }
 800
 801 bool
 802 backend_instruction::is_3src(const struct gen_device_info *devinfo) const
 803 {
 804    return ::is_3src(devinfo, opcode);
 805 }
 806
 807 bool
 808 backend_instruction::is_tex() const
 809 {
 810    return (opcode == SHADER_OPCODE_TEX ||
 811            opcode == FS_OPCODE_TXB ||
 812            opcode == SHADER_OPCODE_TXD ||
 813            opcode == SHADER_OPCODE_TXF ||
 814            opcode == SHADER_OPCODE_TXF_LZ ||
 815            opcode == SHADER_OPCODE_TXF_CMS ||
 816            opcode == SHADER_OPCODE_TXF_CMS_W ||
 817            opcode == SHADER_OPCODE_TXF_UMS ||
 818            opcode == SHADER_OPCODE_TXF_MCS ||
 819            opcode == SHADER_OPCODE_TXL ||
 820            opcode == SHADER_OPCODE_TXL_LZ ||
 821            opcode == SHADER_OPCODE_TXS ||
 822            opcode == SHADER_OPCODE_LOD ||
 823            opcode == SHADER_OPCODE_TG4 ||
 824            opcode == SHADER_OPCODE_TG4_OFFSET ||
 825            opcode == SHADER_OPCODE_SAMPLEINFO);
 826 }
 827
 828 bool
 829 backend_instruction::is_math() const
 830 {
 831    return (opcode == SHADER_OPCODE_RCP ||
 832            opcode == SHADER_OPCODE_RSQ ||
 833            opcode == SHADER_OPCODE_SQRT ||
 834            opcode == SHADER_OPCODE_EXP2 ||
 835            opcode == SHADER_OPCODE_LOG2 ||
 836            opcode == SHADER_OPCODE_SIN ||
 837            opcode == SHADER_OPCODE_COS ||
 838            opcode == SHADER_OPCODE_INT_QUOTIENT ||
 839            opcode == SHADER_OPCODE_INT_REMAINDER ||
 840            opcode == SHADER_OPCODE_POW);
 841 }
 842
 843 bool
 844 backend_instruction::is_control_flow() const
 845 {
 846    switch (opcode) {
 847    case BRW_OPCODE_DO:
 848    case BRW_OPCODE_WHILE:
 849    case BRW_OPCODE_IF:
 850    case BRW_OPCODE_ELSE:
 851    case BRW_OPCODE_ENDIF:
 852    case BRW_OPCODE_BREAK:
 853    case BRW_OPCODE_CONTINUE:
 854       return true;
 855    default:
 856       return false;
 857    }
 858 }
 859
 860 bool
 861 backend_instruction::can_do_source_mods() const
 862 {
 863    switch (opcode) {
 864    case BRW_OPCODE_ADDC:
 865    case BRW_OPCODE_BFE:
 866    case BRW_OPCODE_BFI1:
 867    case BRW_OPCODE_BFI2:
 868    case BRW_OPCODE_BFREV:
 869    case BRW_OPCODE_CBIT:
 870    case BRW_OPCODE_FBH:
 871    case BRW_OPCODE_FBL:
 872    case BRW_OPCODE_SUBB:
 873    case SHADER_OPCODE_BROADCAST:
 874    case SHADER_OPCODE_CLUSTER_BROADCAST:
 875    case SHADER_OPCODE_MOV_INDIRECT:
 876       return false;
 877    default:
 878       return true;
 879    }
 880 }
 881
 882 bool
 883 backend_instruction::can_do_saturate() const
 884 {
 885    switch (opcode) {
 886    case BRW_OPCODE_ADD:
 887    case BRW_OPCODE_ASR:
 888    case BRW_OPCODE_AVG:
 889    case BRW_OPCODE_DP2:
 890    case BRW_OPCODE_DP3:
 891    case BRW_OPCODE_DP4:
 892    case BRW_OPCODE_DPH:
 893    case BRW_OPCODE_F16TO32:
 894    case BRW_OPCODE_F32TO16:
 895    case BRW_OPCODE_LINE:
 896    case BRW_OPCODE_LRP:
 897    case BRW_OPCODE_MAC:
 898    case BRW_OPCODE_MAD:
 899    case BRW_OPCODE_MATH:
 900    case BRW_OPCODE_MOV:
 901    case BRW_OPCODE_MUL:
 902    case SHADER_OPCODE_MULH:
 903    case BRW_OPCODE_PLN:
 904    case BRW_OPCODE_RNDD:
 905    case BRW_OPCODE_RNDE:
 906    case BRW_OPCODE_RNDU:
 907    case BRW_OPCODE_RNDZ:
 908    case BRW_OPCODE_SEL:
 909    case BRW_OPCODE_SHL:
 910    case BRW_OPCODE_SHR:
 911    case FS_OPCODE_LINTERP:
 912    case SHADER_OPCODE_COS:
 913    case SHADER_OPCODE_EXP2:
 914    case SHADER_OPCODE_LOG2:
 915    case SHADER_OPCODE_POW:
 916    case SHADER_OPCODE_RCP:
 917    case SHADER_OPCODE_RSQ:
 918    case SHADER_OPCODE_SIN:
 919    case SHADER_OPCODE_SQRT:
 920       return true;
 921    default:
 922       return false;
 923    }
 924 }
 925
 926 bool
 927 backend_instruction::can_do_cmod() const
 928 {
 929    switch (opcode) {
 930    case BRW_OPCODE_ADD:
 931    case BRW_OPCODE_ADDC:
 932    case BRW_OPCODE_AND:
 933    case BRW_OPCODE_ASR:
 934    case BRW_OPCODE_AVG:
 935    case BRW_OPCODE_CMP:
 936    case BRW_OPCODE_CMPN:
 937    case BRW_OPCODE_DP2:
 938    case BRW_OPCODE_DP3:
 939    case BRW_OPCODE_DP4:
 940    case BRW_OPCODE_DPH:
 941    case BRW_OPCODE_F16TO32:
 942    case BRW_OPCODE_F32TO16:
 943    case BRW_OPCODE_FRC:
 944    case BRW_OPCODE_LINE:
 945    case BRW_OPCODE_LRP:
 946    case BRW_OPCODE_LZD:
 947    case BRW_OPCODE_MAC:
 948    case BRW_OPCODE_MACH:
 949    case BRW_OPCODE_MAD:
 950    case BRW_OPCODE_MOV:
 951    case BRW_OPCODE_MUL:
 952    case BRW_OPCODE_NOT:
 953    case BRW_OPCODE_OR:
 954    case BRW_OPCODE_PLN:
 955    case BRW_OPCODE_RNDD:
 956    case BRW_OPCODE_RNDE:
 957    case BRW_OPCODE_RNDU:
 958    case BRW_OPCODE_RNDZ:
 959    case BRW_OPCODE_SAD2:
 960    case BRW_OPCODE_SADA2:
 961    case BRW_OPCODE_SHL:
 962    case BRW_OPCODE_SHR:
 963    case BRW_OPCODE_SUBB:
 964    case BRW_OPCODE_XOR:
 965    case FS_OPCODE_LINTERP:
 966       return true;
 967    default:
 968       return false;
 969    }
 970 }
 971
 972 bool
 973 backend_instruction::reads_accumulator_implicitly() const
 974 {
 975    switch (opcode) {
 976    case BRW_OPCODE_MAC:
 977    case BRW_OPCODE_MACH:
 978    case BRW_OPCODE_SADA2:
 979       return true;
 980    default:
 981       return false;
 982    }
 983 }
 984
 985 bool
 986 backend_instruction::writes_accumulator_implicitly(const struct gen_device_info *devinfo) const
 987 {
 988    return writes_accumulator ||
 989           (devinfo->gen < 6 &&
 990            ((opcode >= BRW_OPCODE_ADD && opcode < BRW_OPCODE_NOP) ||
 991             (opcode >= FS_OPCODE_DDX_COARSE && opcode <= FS_OPCODE_LINTERP))) ||
 992           (opcode == FS_OPCODE_LINTERP &&
 993            (!devinfo->has_pln || devinfo->gen <= 6));
 994 }
 995
 996 bool
 997 backend_instruction::has_side_effects() const
 998 {
 999    switch (opcode) {
1000    case SHADER_OPCODE_UNTYPED_ATOMIC:
1001    case SHADER_OPCODE_UNTYPED_ATOMIC_LOGICAL:
1002    case SHADER_OPCODE_UNTYPED_ATOMIC_FLOAT:
1003    case SHADER_OPCODE_UNTYPED_ATOMIC_FLOAT_LOGICAL:
1004    case SHADER_OPCODE_GEN4_SCRATCH_WRITE:
1005    case SHADER_OPCODE_UNTYPED_SURFACE_WRITE:
1006    case SHADER_OPCODE_UNTYPED_SURFACE_WRITE_LOGICAL:
1007    case SHADER_OPCODE_BYTE_SCATTERED_WRITE:
1008    case SHADER_OPCODE_BYTE_SCATTERED_WRITE_LOGICAL:
1009    case SHADER_OPCODE_TYPED_ATOMIC:
1010    case SHADER_OPCODE_TYPED_ATOMIC_LOGICAL:
1011    case SHADER_OPCODE_TYPED_SURFACE_WRITE:
1012    case SHADER_OPCODE_TYPED_SURFACE_WRITE_LOGICAL:
1013    case SHADER_OPCODE_MEMORY_FENCE:
1014    case SHADER_OPCODE_INTERLOCK:
1015    case SHADER_OPCODE_URB_WRITE_SIMD8:
1016    case SHADER_OPCODE_URB_WRITE_SIMD8_PER_SLOT:
1017    case SHADER_OPCODE_URB_WRITE_SIMD8_MASKED:
1018    case SHADER_OPCODE_URB_WRITE_SIMD8_MASKED_PER_SLOT:
1019    case FS_OPCODE_FB_WRITE:
1020    case FS_OPCODE_FB_WRITE_LOGICAL:
1021    case FS_OPCODE_REP_FB_WRITE:
1022    case SHADER_OPCODE_BARRIER:
1023    case TCS_OPCODE_URB_WRITE:
1024    case TCS_OPCODE_RELEASE_INPUT:
1025    case SHADER_OPCODE_RND_MODE:
1026       return true;
1027    default:
1028       return eot;
1029    }
1030 }
1031
1032 bool
1033 backend_instruction::is_volatile() const
1034 {
1035    switch (opcode) {
1036    case SHADER_OPCODE_UNTYPED_SURFACE_READ:
1037    case SHADER_OPCODE_UNTYPED_SURFACE_READ_LOGICAL:
1038    case SHADER_OPCODE_TYPED_SURFACE_READ:
1039    case SHADER_OPCODE_TYPED_SURFACE_READ_LOGICAL:
1040    case SHADER_OPCODE_BYTE_SCATTERED_READ:
1041    case SHADER_OPCODE_BYTE_SCATTERED_READ_LOGICAL:
1042    case SHADER_OPCODE_URB_READ_SIMD8:
1043    case SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT:
1044    case VEC4_OPCODE_URB_READ:
1045       return true;
1046    default:
1047       return false;
1048    }
1049 }
1050
1051 #ifndef NDEBUG
1052 static bool
1053 inst_is_in_block(const bblock_t *block, const backend_instruction *inst)
1054 {
1055    bool found = false;
1056    foreach_inst_in_block (backend_instruction, i, block) {
1057       if (inst == i) {
1058          found = true;
1059       }
1060    }
1061    return found;
1062 }
1063 #endif
1064
1065 static void
1066 adjust_later_block_ips(bblock_t *start_block, int ip_adjustment)
1067 {
1068    for (bblock_t *block_iter = start_block->next();
1069         block_iter;
1070         block_iter = block_iter->next()) {
1071       block_iter->start_ip += ip_adjustment;
1072       block_iter->end_ip += ip_adjustment;
1073    }
1074 }
1075
1076 void
1077 backend_instruction::insert_after(bblock_t *block, backend_instruction *inst)
1078 {
1079    assert(this != inst);
1080
1081    if (!this->is_head_sentinel())
1082       assert(inst_is_in_block(block, this) || !"Instruction not in block");
1083
1084    block->end_ip++;
1085
1086    adjust_later_block_ips(block, 1);
1087
1088    exec_node::insert_after(inst);
1089 }
1090
1091 void
1092 backend_instruction::insert_before(bblock_t *block, backend_instruction *inst)
1093 {
1094    assert(this != inst);
1095
1096    if (!this->is_tail_sentinel())
1097       assert(inst_is_in_block(block, this) || !"Instruction not in block");
1098
1099    block->end_ip++;
1100
1101    adjust_later_block_ips(block, 1);
1102
1103    exec_node::insert_before(inst);
1104 }
1105
1106 void
1107 backend_instruction::insert_before(bblock_t *block, exec_list *list)
1108 {
1109    assert(inst_is_in_block(block, this) || !"Instruction not in block");
1110
1111    unsigned num_inst = list->length();
1112
1113    block->end_ip += num_inst;
1114
1115    adjust_later_block_ips(block, num_inst);
1116
1117    exec_node::insert_before(list);
1118 }
1119
1120 void
1121 backend_instruction::remove(bblock_t *block)
1122 {
1123    assert(inst_is_in_block(block, this) || !"Instruction not in block");
1124
1125    adjust_later_block_ips(block, -1);
1126
1127    if (block->start_ip == block->end_ip) {
1128       block->cfg->remove_block(block);
1129    } else {
1130       block->end_ip--;
1131    }
1132
1133    exec_node::remove();
1134 }
1135
1136 void
1137 backend_shader::dump_instructions()
1138 {
1139    dump_instructions(NULL);
1140 }
1141
1142 void
1143 backend_shader::dump_instructions(const char *name)
1144 {
1145    FILE *file = stderr;
1146    if (name && geteuid() != 0) {
1147       file = fopen(name, "w");
1148       if (!file)
1149          file = stderr;
1150    }
1151
1152    if (cfg) {
1153       int ip = 0;
1154       foreach_block_and_inst(block, backend_instruction, inst, cfg) {
1155          if (!unlikely(INTEL_DEBUG & DEBUG_OPTIMIZER))
1156             fprintf(file, "%4d: ", ip++);
1157          dump_instruction(inst, file);
1158       }
1159    } else {
1160       int ip = 0;
1161       foreach_in_list(backend_instruction, inst, &instructions) {
1162          if (!unlikely(INTEL_DEBUG & DEBUG_OPTIMIZER))
1163             fprintf(file, "%4d: ", ip++);
1164          dump_instruction(inst, file);
1165       }
1166    }
1167
1168    if (file != stderr) {
1169       fclose(file);
1170    }
1171 }
1172
1173 void
1174 backend_shader::calculate_cfg()
1175 {
1176    if (this->cfg)
1177       return;
1178    cfg = new(mem_ctx) cfg_t(&this->instructions);
1179 }
1180
1181 extern "C" const unsigned *
1182 brw_compile_tes(const struct brw_compiler *compiler,
1183                 void *log_data,
1184                 void *mem_ctx,
1185                 const struct brw_tes_prog_key *key,
1186                 const struct brw_vue_map *input_vue_map,
1187                 struct brw_tes_prog_data *prog_data,
1188                 nir_shader *nir,
1189                 struct gl_program *prog,
1190                 int shader_time_index,
1191                 char **error_str)
1192 {
1193    const struct gen_device_info *devinfo = compiler->devinfo;
1194    const bool is_scalar = compiler->scalar_stage[MESA_SHADER_TESS_EVAL];
1195    const unsigned *assembly;
1196
1197    nir->info.inputs_read = key->inputs_read;
1198    nir->info.patch_inputs_read = key->patch_inputs_read;
1199
1200    nir = brw_nir_apply_sampler_key(nir, compiler, &key->tex, is_scalar);
1201    brw_nir_lower_tes_inputs(nir, input_vue_map);
1202    brw_nir_lower_vue_outputs(nir);
1203    nir = brw_postprocess_nir(nir, compiler, is_scalar);
1204
1205    brw_compute_vue_map(devinfo, &prog_data->base.vue_map,
1206                        nir->info.outputs_written,
1207                        nir->info.separate_shader);
1208
1209    unsigned output_size_bytes = prog_data->base.vue_map.num_slots * 4 * 4;
1210
1211    assert(output_size_bytes >= 1);
1212    if (output_size_bytes > GEN7_MAX_DS_URB_ENTRY_SIZE_BYTES) {
1213       if (error_str)
1214          *error_str = ralloc_strdup(mem_ctx, "DS outputs exceed maximum size");
1215       return NULL;
1216    }
1217
1218    prog_data->base.clip_distance_mask =
1219       ((1 << nir->info.clip_distance_array_size) - 1);
1220    prog_data->base.cull_distance_mask =
1221       ((1 << nir->info.cull_distance_array_size) - 1) <<
1222       nir->info.clip_distance_array_size;
1223
1224    /* URB entry sizes are stored as a multiple of 64 bytes. */
1225    prog_data->base.urb_entry_size = ALIGN(output_size_bytes, 64) / 64;
1226
1227    /* On Cannonlake software shall not program an allocation size that
1228     * specifies a size that is a multiple of 3 64B (512-bit) cachelines.
1229     */
1230    if (devinfo->gen == 10 &&
1231        prog_data->base.urb_entry_size % 3 == 0)
1232       prog_data->base.urb_entry_size++;
1233
1234    prog_data->base.urb_read_length = 0;
1235
1236    STATIC_ASSERT(BRW_TESS_PARTITIONING_INTEGER == TESS_SPACING_EQUAL - 1);
1237    STATIC_ASSERT(BRW_TESS_PARTITIONING_ODD_FRACTIONAL ==
1238                  TESS_SPACING_FRACTIONAL_ODD - 1);
1239    STATIC_ASSERT(BRW_TESS_PARTITIONING_EVEN_FRACTIONAL ==
1240                  TESS_SPACING_FRACTIONAL_EVEN - 1);
1241
1242    prog_data->partitioning =
1243       (enum brw_tess_partitioning) (nir->info.tess.spacing - 1);
1244
1245    switch (nir->info.tess.primitive_mode) {
1246    case GL_QUADS:
1247       prog_data->domain = BRW_TESS_DOMAIN_QUAD;
1248       break;
1249    case GL_TRIANGLES:
1250       prog_data->domain = BRW_TESS_DOMAIN_TRI;
1251       break;
1252    case GL_ISOLINES:
1253       prog_data->domain = BRW_TESS_DOMAIN_ISOLINE;
1254       break;
1255    default:
1256       unreachable("invalid domain shader primitive mode");
1257    }
1258
1259    if (nir->info.tess.point_mode) {
1260       prog_data->output_topology = BRW_TESS_OUTPUT_TOPOLOGY_POINT;
1261    } else if (nir->info.tess.primitive_mode == GL_ISOLINES) {
1262       prog_data->output_topology = BRW_TESS_OUTPUT_TOPOLOGY_LINE;
1263    } else {
1264       /* Hardware winding order is backwards from OpenGL */
1265       prog_data->output_topology =
1266          nir->info.tess.ccw ? BRW_TESS_OUTPUT_TOPOLOGY_TRI_CW
1267                              : BRW_TESS_OUTPUT_TOPOLOGY_TRI_CCW;
1268    }
1269
1270    if (unlikely(INTEL_DEBUG & DEBUG_TES)) {
1271       fprintf(stderr, "TES Input ");
1272       brw_print_vue_map(stderr, input_vue_map);
1273       fprintf(stderr, "TES Output ");
1274       brw_print_vue_map(stderr, &prog_data->base.vue_map);
1275    }
1276
1277    if (is_scalar) {
1278       fs_visitor v(compiler, log_data, mem_ctx, (void *) key,
1279                    &prog_data->base.base, NULL, nir, 8,
1280                    shader_time_index, input_vue_map);
1281       if (!v.run_tes()) {
1282          if (error_str)
1283             *error_str = ralloc_strdup(mem_ctx, v.fail_msg);
1284          return NULL;
1285       }
1286
1287       prog_data->base.base.dispatch_grf_start_reg = v.payload.num_regs;
1288       prog_data->base.dispatch_mode = DISPATCH_MODE_SIMD8;
1289
1290       fs_generator g(compiler, log_data, mem_ctx,
1291                      &prog_data->base.base, v.promoted_constants, false,
1292                      MESA_SHADER_TESS_EVAL);
1293       if (unlikely(INTEL_DEBUG & DEBUG_TES)) {
1294          g.enable_debug(ralloc_asprintf(mem_ctx,
1295                                         "%s tessellation evaluation shader %s",
1296                                         nir->info.label ? nir->info.label
1297                                                         : "unnamed",
1298                                         nir->info.name));
1299       }
1300
1301       g.generate_code(v.cfg, 8);
1302
1303       assembly = g.get_assembly();
1304    } else {
1305       brw::vec4_tes_visitor v(compiler, log_data, key, prog_data,
1306                               nir, mem_ctx, shader_time_index);
1307       if (!v.run()) {
1308          if (error_str)
1309             *error_str = ralloc_strdup(mem_ctx, v.fail_msg);
1310          return NULL;
1311       }
1312
1313       if (unlikely(INTEL_DEBUG & DEBUG_TES))
1314          v.dump_instructions();
1315
1316       assembly = brw_vec4_generate_assembly(compiler, log_data, mem_ctx, nir,
1317                                             &prog_data->base, v.cfg);
1318    }
1319
1320    return assembly;
1321 }