src/intel/compiler/brw_shader.cpp

   1 /*
   2  * Copyright © 2010 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  */
  23
  24 #include "brw_cfg.h"
  25 #include "brw_eu.h"
  26 #include "brw_fs.h"
  27 #include "brw_nir.h"
  28 #include "brw_vec4_tes.h"
  29 #include "dev/gen_debug.h"
  30 #include "main/uniforms.h"
  31 #include "util/macros.h"
  32
  33 enum brw_reg_type
  34 brw_type_for_base_type(const struct glsl_type *type)
  35 {
  36    switch (type->base_type) {
  37    case GLSL_TYPE_FLOAT16:
  38       return BRW_REGISTER_TYPE_HF;
  39    case GLSL_TYPE_FLOAT:
  40       return BRW_REGISTER_TYPE_F;
  41    case GLSL_TYPE_INT:
  42    case GLSL_TYPE_BOOL:
  43    case GLSL_TYPE_SUBROUTINE:
  44       return BRW_REGISTER_TYPE_D;
  45    case GLSL_TYPE_INT16:
  46       return BRW_REGISTER_TYPE_W;
  47    case GLSL_TYPE_INT8:
  48       return BRW_REGISTER_TYPE_B;
  49    case GLSL_TYPE_UINT:
  50       return BRW_REGISTER_TYPE_UD;
  51    case GLSL_TYPE_UINT16:
  52       return BRW_REGISTER_TYPE_UW;
  53    case GLSL_TYPE_UINT8:
  54       return BRW_REGISTER_TYPE_UB;
  55    case GLSL_TYPE_ARRAY:
  56       return brw_type_for_base_type(type->fields.array);
  57    case GLSL_TYPE_STRUCT:
  58    case GLSL_TYPE_INTERFACE:
  59    case GLSL_TYPE_SAMPLER:
  60    case GLSL_TYPE_ATOMIC_UINT:
  61       /* These should be overridden with the type of the member when
  62        * dereferenced into.  BRW_REGISTER_TYPE_UD seems like a likely
  63        * way to trip up if we don't.
  64        */
  65       return BRW_REGISTER_TYPE_UD;
  66    case GLSL_TYPE_IMAGE:
  67       return BRW_REGISTER_TYPE_UD;
  68    case GLSL_TYPE_DOUBLE:
  69       return BRW_REGISTER_TYPE_DF;
  70    case GLSL_TYPE_UINT64:
  71       return BRW_REGISTER_TYPE_UQ;
  72    case GLSL_TYPE_INT64:
  73       return BRW_REGISTER_TYPE_Q;
  74    case GLSL_TYPE_VOID:
  75    case GLSL_TYPE_ERROR:
  76    case GLSL_TYPE_FUNCTION:
  77       unreachable("not reached");
  78    }
  79
  80    return BRW_REGISTER_TYPE_F;
  81 }
  82
  83 enum brw_conditional_mod
  84 brw_conditional_for_comparison(unsigned int op)
  85 {
  86    switch (op) {
  87    case ir_binop_less:
  88       return BRW_CONDITIONAL_L;
  89    case ir_binop_gequal:
  90       return BRW_CONDITIONAL_GE;
  91    case ir_binop_equal:
  92    case ir_binop_all_equal: /* same as equal for scalars */
  93       return BRW_CONDITIONAL_Z;
  94    case ir_binop_nequal:
  95    case ir_binop_any_nequal: /* same as nequal for scalars */
  96       return BRW_CONDITIONAL_NZ;
  97    default:
  98       unreachable("not reached: bad operation for comparison");
  99    }
 100 }
 101
 102 uint32_t
 103 brw_math_function(enum opcode op)
 104 {
 105    switch (op) {
 106    case SHADER_OPCODE_RCP:
 107       return BRW_MATH_FUNCTION_INV;
 108    case SHADER_OPCODE_RSQ:
 109       return BRW_MATH_FUNCTION_RSQ;
 110    case SHADER_OPCODE_SQRT:
 111       return BRW_MATH_FUNCTION_SQRT;
 112    case SHADER_OPCODE_EXP2:
 113       return BRW_MATH_FUNCTION_EXP;
 114    case SHADER_OPCODE_LOG2:
 115       return BRW_MATH_FUNCTION_LOG;
 116    case SHADER_OPCODE_POW:
 117       return BRW_MATH_FUNCTION_POW;
 118    case SHADER_OPCODE_SIN:
 119       return BRW_MATH_FUNCTION_SIN;
 120    case SHADER_OPCODE_COS:
 121       return BRW_MATH_FUNCTION_COS;
 122    case SHADER_OPCODE_INT_QUOTIENT:
 123       return BRW_MATH_FUNCTION_INT_DIV_QUOTIENT;
 124    case SHADER_OPCODE_INT_REMAINDER:
 125       return BRW_MATH_FUNCTION_INT_DIV_REMAINDER;
 126    default:
 127       unreachable("not reached: unknown math function");
 128    }
 129 }
 130
 131 bool
 132 brw_texture_offset(const nir_tex_instr *tex, unsigned src,
 133                    uint32_t *offset_bits_out)
 134 {
 135    if (!nir_src_is_const(tex->src[src].src))
 136       return false;
 137
 138    const unsigned num_components = nir_tex_instr_src_size(tex, src);
 139
 140    /* Combine all three offsets into a single unsigned dword:
 141     *
 142     *    bits 11:8 - U Offset (X component)
 143     *    bits  7:4 - V Offset (Y component)
 144     *    bits  3:0 - R Offset (Z component)
 145     */
 146    uint32_t offset_bits = 0;
 147    for (unsigned i = 0; i < num_components; i++) {
 148       int offset = nir_src_comp_as_int(tex->src[src].src, i);
 149
 150       /* offset out of bounds; caller will handle it. */
 151       if (offset > 7 || offset < -8)
 152          return false;
 153
 154       const unsigned shift = 4 * (2 - i);
 155       offset_bits |= (offset << shift) & (0xF << shift);
 156    }
 157
 158    *offset_bits_out = offset_bits;
 159
 160    return true;
 161 }
 162
 163 const char *
 164 brw_instruction_name(const struct gen_device_info *devinfo, enum opcode op)
 165 {
 166    switch (op) {
 167    case BRW_OPCODE_ILLEGAL ... BRW_OPCODE_NOP:
 168       /* The DO instruction doesn't exist on Gen6+, but we use it to mark the
 169        * start of a loop in the IR.
 170        */
 171       if (devinfo->gen >= 6 && op == BRW_OPCODE_DO)
 172          return "do";
 173
 174       /* The following conversion opcodes doesn't exist on Gen8+, but we use
 175        * then to mark that we want to do the conversion.
 176        */
 177       if (devinfo->gen > 7 && op == BRW_OPCODE_F32TO16)
 178          return "f32to16";
 179
 180       if (devinfo->gen > 7 && op == BRW_OPCODE_F16TO32)
 181          return "f16to32";
 182
 183       assert(brw_opcode_desc(devinfo, op)->name);
 184       return brw_opcode_desc(devinfo, op)->name;
 185    case FS_OPCODE_FB_WRITE:
 186       return "fb_write";
 187    case FS_OPCODE_FB_WRITE_LOGICAL:
 188       return "fb_write_logical";
 189    case FS_OPCODE_REP_FB_WRITE:
 190       return "rep_fb_write";
 191    case FS_OPCODE_FB_READ:
 192       return "fb_read";
 193    case FS_OPCODE_FB_READ_LOGICAL:
 194       return "fb_read_logical";
 195
 196    case SHADER_OPCODE_RCP:
 197       return "rcp";
 198    case SHADER_OPCODE_RSQ:
 199       return "rsq";
 200    case SHADER_OPCODE_SQRT:
 201       return "sqrt";
 202    case SHADER_OPCODE_EXP2:
 203       return "exp2";
 204    case SHADER_OPCODE_LOG2:
 205       return "log2";
 206    case SHADER_OPCODE_POW:
 207       return "pow";
 208    case SHADER_OPCODE_INT_QUOTIENT:
 209       return "int_quot";
 210    case SHADER_OPCODE_INT_REMAINDER:
 211       return "int_rem";
 212    case SHADER_OPCODE_SIN:
 213       return "sin";
 214    case SHADER_OPCODE_COS:
 215       return "cos";
 216
 217    case SHADER_OPCODE_SEND:
 218       return "send";
 219
 220    case SHADER_OPCODE_UNDEF:
 221       return "undef";
 222
 223    case SHADER_OPCODE_TEX:
 224       return "tex";
 225    case SHADER_OPCODE_TEX_LOGICAL:
 226       return "tex_logical";
 227    case SHADER_OPCODE_TXD:
 228       return "txd";
 229    case SHADER_OPCODE_TXD_LOGICAL:
 230       return "txd_logical";
 231    case SHADER_OPCODE_TXF:
 232       return "txf";
 233    case SHADER_OPCODE_TXF_LOGICAL:
 234       return "txf_logical";
 235    case SHADER_OPCODE_TXF_LZ:
 236       return "txf_lz";
 237    case SHADER_OPCODE_TXL:
 238       return "txl";
 239    case SHADER_OPCODE_TXL_LOGICAL:
 240       return "txl_logical";
 241    case SHADER_OPCODE_TXL_LZ:
 242       return "txl_lz";
 243    case SHADER_OPCODE_TXS:
 244       return "txs";
 245    case SHADER_OPCODE_TXS_LOGICAL:
 246       return "txs_logical";
 247    case FS_OPCODE_TXB:
 248       return "txb";
 249    case FS_OPCODE_TXB_LOGICAL:
 250       return "txb_logical";
 251    case SHADER_OPCODE_TXF_CMS:
 252       return "txf_cms";
 253    case SHADER_OPCODE_TXF_CMS_LOGICAL:
 254       return "txf_cms_logical";
 255    case SHADER_OPCODE_TXF_CMS_W:
 256       return "txf_cms_w";
 257    case SHADER_OPCODE_TXF_CMS_W_LOGICAL:
 258       return "txf_cms_w_logical";
 259    case SHADER_OPCODE_TXF_UMS:
 260       return "txf_ums";
 261    case SHADER_OPCODE_TXF_UMS_LOGICAL:
 262       return "txf_ums_logical";
 263    case SHADER_OPCODE_TXF_MCS:
 264       return "txf_mcs";
 265    case SHADER_OPCODE_TXF_MCS_LOGICAL:
 266       return "txf_mcs_logical";
 267    case SHADER_OPCODE_LOD:
 268       return "lod";
 269    case SHADER_OPCODE_LOD_LOGICAL:
 270       return "lod_logical";
 271    case SHADER_OPCODE_TG4:
 272       return "tg4";
 273    case SHADER_OPCODE_TG4_LOGICAL:
 274       return "tg4_logical";
 275    case SHADER_OPCODE_TG4_OFFSET:
 276       return "tg4_offset";
 277    case SHADER_OPCODE_TG4_OFFSET_LOGICAL:
 278       return "tg4_offset_logical";
 279    case SHADER_OPCODE_SAMPLEINFO:
 280       return "sampleinfo";
 281    case SHADER_OPCODE_SAMPLEINFO_LOGICAL:
 282       return "sampleinfo_logical";
 283
 284    case SHADER_OPCODE_IMAGE_SIZE_LOGICAL:
 285       return "image_size_logical";
 286
 287    case SHADER_OPCODE_SHADER_TIME_ADD:
 288       return "shader_time_add";
 289
 290    case VEC4_OPCODE_UNTYPED_ATOMIC:
 291       return "untyped_atomic";
 292    case SHADER_OPCODE_UNTYPED_ATOMIC_LOGICAL:
 293       return "untyped_atomic_logical";
 294    case SHADER_OPCODE_UNTYPED_ATOMIC_FLOAT_LOGICAL:
 295       return "untyped_atomic_float_logical";
 296    case VEC4_OPCODE_UNTYPED_SURFACE_READ:
 297       return "untyped_surface_read";
 298    case SHADER_OPCODE_UNTYPED_SURFACE_READ_LOGICAL:
 299       return "untyped_surface_read_logical";
 300    case VEC4_OPCODE_UNTYPED_SURFACE_WRITE:
 301       return "untyped_surface_write";
 302    case SHADER_OPCODE_UNTYPED_SURFACE_WRITE_LOGICAL:
 303       return "untyped_surface_write_logical";
 304    case SHADER_OPCODE_A64_UNTYPED_READ_LOGICAL:
 305       return "a64_untyped_read_logical";
 306    case SHADER_OPCODE_A64_UNTYPED_WRITE_LOGICAL:
 307       return "a64_untyped_write_logical";
 308    case SHADER_OPCODE_A64_BYTE_SCATTERED_READ_LOGICAL:
 309       return "a64_byte_scattered_read_logical";
 310    case SHADER_OPCODE_A64_BYTE_SCATTERED_WRITE_LOGICAL:
 311       return "a64_byte_scattered_write_logical";
 312    case SHADER_OPCODE_A64_UNTYPED_ATOMIC_LOGICAL:
 313       return "a64_untyped_atomic_logical";
 314    case SHADER_OPCODE_A64_UNTYPED_ATOMIC_INT64_LOGICAL:
 315       return "a64_untyped_atomic_int64_logical";
 316    case SHADER_OPCODE_A64_UNTYPED_ATOMIC_FLOAT_LOGICAL:
 317       return "a64_untyped_atomic_float_logical";
 318    case SHADER_OPCODE_TYPED_ATOMIC_LOGICAL:
 319       return "typed_atomic_logical";
 320    case SHADER_OPCODE_TYPED_SURFACE_READ_LOGICAL:
 321       return "typed_surface_read_logical";
 322    case SHADER_OPCODE_TYPED_SURFACE_WRITE_LOGICAL:
 323       return "typed_surface_write_logical";
 324    case SHADER_OPCODE_MEMORY_FENCE:
 325       return "memory_fence";
 326    case SHADER_OPCODE_INTERLOCK:
 327       /* For an interlock we actually issue a memory fence via sendc. */
 328       return "interlock";
 329
 330    case SHADER_OPCODE_BYTE_SCATTERED_READ_LOGICAL:
 331       return "byte_scattered_read_logical";
 332    case SHADER_OPCODE_BYTE_SCATTERED_WRITE_LOGICAL:
 333       return "byte_scattered_write_logical";
 334
 335    case SHADER_OPCODE_LOAD_PAYLOAD:
 336       return "load_payload";
 337    case FS_OPCODE_PACK:
 338       return "pack";
 339
 340    case SHADER_OPCODE_GEN4_SCRATCH_READ:
 341       return "gen4_scratch_read";
 342    case SHADER_OPCODE_GEN4_SCRATCH_WRITE:
 343       return "gen4_scratch_write";
 344    case SHADER_OPCODE_GEN7_SCRATCH_READ:
 345       return "gen7_scratch_read";
 346    case SHADER_OPCODE_URB_WRITE_SIMD8:
 347       return "gen8_urb_write_simd8";
 348    case SHADER_OPCODE_URB_WRITE_SIMD8_PER_SLOT:
 349       return "gen8_urb_write_simd8_per_slot";
 350    case SHADER_OPCODE_URB_WRITE_SIMD8_MASKED:
 351       return "gen8_urb_write_simd8_masked";
 352    case SHADER_OPCODE_URB_WRITE_SIMD8_MASKED_PER_SLOT:
 353       return "gen8_urb_write_simd8_masked_per_slot";
 354    case SHADER_OPCODE_URB_READ_SIMD8:
 355       return "urb_read_simd8";
 356    case SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT:
 357       return "urb_read_simd8_per_slot";
 358
 359    case SHADER_OPCODE_FIND_LIVE_CHANNEL:
 360       return "find_live_channel";
 361    case SHADER_OPCODE_BROADCAST:
 362       return "broadcast";
 363    case SHADER_OPCODE_SHUFFLE:
 364       return "shuffle";
 365    case SHADER_OPCODE_SEL_EXEC:
 366       return "sel_exec";
 367    case SHADER_OPCODE_QUAD_SWIZZLE:
 368       return "quad_swizzle";
 369    case SHADER_OPCODE_CLUSTER_BROADCAST:
 370       return "cluster_broadcast";
 371
 372    case SHADER_OPCODE_GET_BUFFER_SIZE:
 373       return "get_buffer_size";
 374
 375    case VEC4_OPCODE_MOV_BYTES:
 376       return "mov_bytes";
 377    case VEC4_OPCODE_PACK_BYTES:
 378       return "pack_bytes";
 379    case VEC4_OPCODE_UNPACK_UNIFORM:
 380       return "unpack_uniform";
 381    case VEC4_OPCODE_DOUBLE_TO_F32:
 382       return "double_to_f32";
 383    case VEC4_OPCODE_DOUBLE_TO_D32:
 384       return "double_to_d32";
 385    case VEC4_OPCODE_DOUBLE_TO_U32:
 386       return "double_to_u32";
 387    case VEC4_OPCODE_TO_DOUBLE:
 388       return "single_to_double";
 389    case VEC4_OPCODE_PICK_LOW_32BIT:
 390       return "pick_low_32bit";
 391    case VEC4_OPCODE_PICK_HIGH_32BIT:
 392       return "pick_high_32bit";
 393    case VEC4_OPCODE_SET_LOW_32BIT:
 394       return "set_low_32bit";
 395    case VEC4_OPCODE_SET_HIGH_32BIT:
 396       return "set_high_32bit";
 397
 398    case FS_OPCODE_DDX_COARSE:
 399       return "ddx_coarse";
 400    case FS_OPCODE_DDX_FINE:
 401       return "ddx_fine";
 402    case FS_OPCODE_DDY_COARSE:
 403       return "ddy_coarse";
 404    case FS_OPCODE_DDY_FINE:
 405       return "ddy_fine";
 406
 407    case FS_OPCODE_LINTERP:
 408       return "linterp";
 409
 410    case FS_OPCODE_PIXEL_X:
 411       return "pixel_x";
 412    case FS_OPCODE_PIXEL_Y:
 413       return "pixel_y";
 414
 415    case FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD:
 416       return "uniform_pull_const";
 417    case FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD_GEN7:
 418       return "uniform_pull_const_gen7";
 419    case FS_OPCODE_VARYING_PULL_CONSTANT_LOAD_GEN4:
 420       return "varying_pull_const_gen4";
 421    case FS_OPCODE_VARYING_PULL_CONSTANT_LOAD_LOGICAL:
 422       return "varying_pull_const_logical";
 423
 424    case FS_OPCODE_DISCARD_JUMP:
 425       return "discard_jump";
 426
 427    case FS_OPCODE_SET_SAMPLE_ID:
 428       return "set_sample_id";
 429
 430    case FS_OPCODE_PACK_HALF_2x16_SPLIT:
 431       return "pack_half_2x16_split";
 432
 433    case FS_OPCODE_PLACEHOLDER_HALT:
 434       return "placeholder_halt";
 435
 436    case FS_OPCODE_INTERPOLATE_AT_SAMPLE:
 437       return "interp_sample";
 438    case FS_OPCODE_INTERPOLATE_AT_SHARED_OFFSET:
 439       return "interp_shared_offset";
 440    case FS_OPCODE_INTERPOLATE_AT_PER_SLOT_OFFSET:
 441       return "interp_per_slot_offset";
 442
 443    case VS_OPCODE_URB_WRITE:
 444       return "vs_urb_write";
 445    case VS_OPCODE_PULL_CONSTANT_LOAD:
 446       return "pull_constant_load";
 447    case VS_OPCODE_PULL_CONSTANT_LOAD_GEN7:
 448       return "pull_constant_load_gen7";
 449
 450    case VS_OPCODE_SET_SIMD4X2_HEADER_GEN9:
 451       return "set_simd4x2_header_gen9";
 452
 453    case VS_OPCODE_UNPACK_FLAGS_SIMD4X2:
 454       return "unpack_flags_simd4x2";
 455
 456    case GS_OPCODE_URB_WRITE:
 457       return "gs_urb_write";
 458    case GS_OPCODE_URB_WRITE_ALLOCATE:
 459       return "gs_urb_write_allocate";
 460    case GS_OPCODE_THREAD_END:
 461       return "gs_thread_end";
 462    case GS_OPCODE_SET_WRITE_OFFSET:
 463       return "set_write_offset";
 464    case GS_OPCODE_SET_VERTEX_COUNT:
 465       return "set_vertex_count";
 466    case GS_OPCODE_SET_DWORD_2:
 467       return "set_dword_2";
 468    case GS_OPCODE_PREPARE_CHANNEL_MASKS:
 469       return "prepare_channel_masks";
 470    case GS_OPCODE_SET_CHANNEL_MASKS:
 471       return "set_channel_masks";
 472    case GS_OPCODE_GET_INSTANCE_ID:
 473       return "get_instance_id";
 474    case GS_OPCODE_FF_SYNC:
 475       return "ff_sync";
 476    case GS_OPCODE_SET_PRIMITIVE_ID:
 477       return "set_primitive_id";
 478    case GS_OPCODE_SVB_WRITE:
 479       return "gs_svb_write";
 480    case GS_OPCODE_SVB_SET_DST_INDEX:
 481       return "gs_svb_set_dst_index";
 482    case GS_OPCODE_FF_SYNC_SET_PRIMITIVES:
 483       return "gs_ff_sync_set_primitives";
 484    case CS_OPCODE_CS_TERMINATE:
 485       return "cs_terminate";
 486    case SHADER_OPCODE_BARRIER:
 487       return "barrier";
 488    case SHADER_OPCODE_MULH:
 489       return "mulh";
 490    case SHADER_OPCODE_MOV_INDIRECT:
 491       return "mov_indirect";
 492
 493    case VEC4_OPCODE_URB_READ:
 494       return "urb_read";
 495    case TCS_OPCODE_GET_INSTANCE_ID:
 496       return "tcs_get_instance_id";
 497    case TCS_OPCODE_URB_WRITE:
 498       return "tcs_urb_write";
 499    case TCS_OPCODE_SET_INPUT_URB_OFFSETS:
 500       return "tcs_set_input_urb_offsets";
 501    case TCS_OPCODE_SET_OUTPUT_URB_OFFSETS:
 502       return "tcs_set_output_urb_offsets";
 503    case TCS_OPCODE_GET_PRIMITIVE_ID:
 504       return "tcs_get_primitive_id";
 505    case TCS_OPCODE_CREATE_BARRIER_HEADER:
 506       return "tcs_create_barrier_header";
 507    case TCS_OPCODE_SRC0_010_IS_ZERO:
 508       return "tcs_src0<0,1,0>_is_zero";
 509    case TCS_OPCODE_RELEASE_INPUT:
 510       return "tcs_release_input";
 511    case TCS_OPCODE_THREAD_END:
 512       return "tcs_thread_end";
 513    case TES_OPCODE_CREATE_INPUT_READ_HEADER:
 514       return "tes_create_input_read_header";
 515    case TES_OPCODE_ADD_INDIRECT_URB_OFFSET:
 516       return "tes_add_indirect_urb_offset";
 517    case TES_OPCODE_GET_PRIMITIVE_ID:
 518       return "tes_get_primitive_id";
 519
 520    case SHADER_OPCODE_RND_MODE:
 521       return "rnd_mode";
 522    case SHADER_OPCODE_FLOAT_CONTROL_MODE:
 523       return "float_control_mode";
 524    }
 525
 526    unreachable("not reached");
 527 }
 528
 529 bool
 530 brw_saturate_immediate(enum brw_reg_type type, struct brw_reg *reg)
 531 {
 532    union {
 533       unsigned ud;
 534       int d;
 535       float f;
 536       double df;
 537    } imm, sat_imm = { 0 };
 538
 539    const unsigned size = type_sz(type);
 540
 541    /* We want to either do a 32-bit or 64-bit data copy, the type is otherwise
 542     * irrelevant, so just check the size of the type and copy from/to an
 543     * appropriately sized field.
 544     */
 545    if (size < 8)
 546       imm.ud = reg->ud;
 547    else
 548       imm.df = reg->df;
 549
 550    switch (type) {
 551    case BRW_REGISTER_TYPE_UD:
 552    case BRW_REGISTER_TYPE_D:
 553    case BRW_REGISTER_TYPE_UW:
 554    case BRW_REGISTER_TYPE_W:
 555    case BRW_REGISTER_TYPE_UQ:
 556    case BRW_REGISTER_TYPE_Q:
 557       /* Nothing to do. */
 558       return false;
 559    case BRW_REGISTER_TYPE_F:
 560       sat_imm.f = CLAMP(imm.f, 0.0f, 1.0f);
 561       break;
 562    case BRW_REGISTER_TYPE_DF:
 563       sat_imm.df = CLAMP(imm.df, 0.0, 1.0);
 564       break;
 565    case BRW_REGISTER_TYPE_UB:
 566    case BRW_REGISTER_TYPE_B:
 567       unreachable("no UB/B immediates");
 568    case BRW_REGISTER_TYPE_V:
 569    case BRW_REGISTER_TYPE_UV:
 570    case BRW_REGISTER_TYPE_VF:
 571       unreachable("unimplemented: saturate vector immediate");
 572    case BRW_REGISTER_TYPE_HF:
 573       unreachable("unimplemented: saturate HF immediate");
 574    case BRW_REGISTER_TYPE_NF:
 575       unreachable("no NF immediates");
 576    }
 577
 578    if (size < 8) {
 579       if (imm.ud != sat_imm.ud) {
 580          reg->ud = sat_imm.ud;
 581          return true;
 582       }
 583    } else {
 584       if (imm.df != sat_imm.df) {
 585          reg->df = sat_imm.df;
 586          return true;
 587       }
 588    }
 589    return false;
 590 }
 591
 592 bool
 593 brw_negate_immediate(enum brw_reg_type type, struct brw_reg *reg)
 594 {
 595    switch (type) {
 596    case BRW_REGISTER_TYPE_D:
 597    case BRW_REGISTER_TYPE_UD:
 598       reg->d = -reg->d;
 599       return true;
 600    case BRW_REGISTER_TYPE_W:
 601    case BRW_REGISTER_TYPE_UW: {
 602       uint16_t value = -(int16_t)reg->ud;
 603       reg->ud = value | (uint32_t)value << 16;
 604       return true;
 605    }
 606    case BRW_REGISTER_TYPE_F:
 607       reg->f = -reg->f;
 608       return true;
 609    case BRW_REGISTER_TYPE_VF:
 610       reg->ud ^= 0x80808080;
 611       return true;
 612    case BRW_REGISTER_TYPE_DF:
 613       reg->df = -reg->df;
 614       return true;
 615    case BRW_REGISTER_TYPE_UQ:
 616    case BRW_REGISTER_TYPE_Q:
 617       reg->d64 = -reg->d64;
 618       return true;
 619    case BRW_REGISTER_TYPE_UB:
 620    case BRW_REGISTER_TYPE_B:
 621       unreachable("no UB/B immediates");
 622    case BRW_REGISTER_TYPE_UV:
 623    case BRW_REGISTER_TYPE_V:
 624       assert(!"unimplemented: negate UV/V immediate");
 625    case BRW_REGISTER_TYPE_HF:
 626       reg->ud ^= 0x80008000;
 627       return true;
 628    case BRW_REGISTER_TYPE_NF:
 629       unreachable("no NF immediates");
 630    }
 631
 632    return false;
 633 }
 634
 635 bool
 636 brw_abs_immediate(enum brw_reg_type type, struct brw_reg *reg)
 637 {
 638    switch (type) {
 639    case BRW_REGISTER_TYPE_D:
 640       reg->d = abs(reg->d);
 641       return true;
 642    case BRW_REGISTER_TYPE_W: {
 643       uint16_t value = abs((int16_t)reg->ud);
 644       reg->ud = value | (uint32_t)value << 16;
 645       return true;
 646    }
 647    case BRW_REGISTER_TYPE_F:
 648       reg->f = fabsf(reg->f);
 649       return true;
 650    case BRW_REGISTER_TYPE_DF:
 651       reg->df = fabs(reg->df);
 652       return true;
 653    case BRW_REGISTER_TYPE_VF:
 654       reg->ud &= ~0x80808080;
 655       return true;
 656    case BRW_REGISTER_TYPE_Q:
 657       reg->d64 = imaxabs(reg->d64);
 658       return true;
 659    case BRW_REGISTER_TYPE_UB:
 660    case BRW_REGISTER_TYPE_B:
 661       unreachable("no UB/B immediates");
 662    case BRW_REGISTER_TYPE_UQ:
 663    case BRW_REGISTER_TYPE_UD:
 664    case BRW_REGISTER_TYPE_UW:
 665    case BRW_REGISTER_TYPE_UV:
 666       /* Presumably the absolute value modifier on an unsigned source is a
 667        * nop, but it would be nice to confirm.
 668        */
 669       assert(!"unimplemented: abs unsigned immediate");
 670    case BRW_REGISTER_TYPE_V:
 671       assert(!"unimplemented: abs V immediate");
 672    case BRW_REGISTER_TYPE_HF:
 673       reg->ud &= ~0x80008000;
 674       return true;
 675    case BRW_REGISTER_TYPE_NF:
 676       unreachable("no NF immediates");
 677    }
 678
 679    return false;
 680 }
 681
 682 backend_shader::backend_shader(const struct brw_compiler *compiler,
 683                                void *log_data,
 684                                void *mem_ctx,
 685                                const nir_shader *shader,
 686                                struct brw_stage_prog_data *stage_prog_data)
 687    : compiler(compiler),
 688      log_data(log_data),
 689      devinfo(compiler->devinfo),
 690      nir(shader),
 691      stage_prog_data(stage_prog_data),
 692      mem_ctx(mem_ctx),
 693      cfg(NULL),
 694      stage(shader->info.stage)
 695 {
 696    debug_enabled = INTEL_DEBUG & intel_debug_flag_for_shader_stage(stage);
 697    stage_name = _mesa_shader_stage_to_string(stage);
 698    stage_abbrev = _mesa_shader_stage_to_abbrev(stage);
 699 }
 700
 701 backend_shader::~backend_shader()
 702 {
 703 }
 704
 705 bool
 706 backend_reg::equals(const backend_reg &r) const
 707 {
 708    return brw_regs_equal(this, &r) && offset == r.offset;
 709 }
 710
 711 bool
 712 backend_reg::negative_equals(const backend_reg &r) const
 713 {
 714    return brw_regs_negative_equal(this, &r) && offset == r.offset;
 715 }
 716
 717 bool
 718 backend_reg::is_zero() const
 719 {
 720    if (file != IMM)
 721       return false;
 722
 723    assert(type_sz(type) > 1);
 724
 725    switch (type) {
 726    case BRW_REGISTER_TYPE_HF:
 727       assert((d & 0xffff) == ((d >> 16) & 0xffff));
 728       return (d & 0xffff) == 0 || (d & 0xffff) == 0x8000;
 729    case BRW_REGISTER_TYPE_F:
 730       return f == 0;
 731    case BRW_REGISTER_TYPE_DF:
 732       return df == 0;
 733    case BRW_REGISTER_TYPE_W:
 734    case BRW_REGISTER_TYPE_UW:
 735       assert((d & 0xffff) == ((d >> 16) & 0xffff));
 736       return (d & 0xffff) == 0;
 737    case BRW_REGISTER_TYPE_D:
 738    case BRW_REGISTER_TYPE_UD:
 739       return d == 0;
 740    case BRW_REGISTER_TYPE_UQ:
 741    case BRW_REGISTER_TYPE_Q:
 742       return u64 == 0;
 743    default:
 744       return false;
 745    }
 746 }
 747
 748 bool
 749 backend_reg::is_one() const
 750 {
 751    if (file != IMM)
 752       return false;
 753
 754    assert(type_sz(type) > 1);
 755
 756    switch (type) {
 757    case BRW_REGISTER_TYPE_HF:
 758       assert((d & 0xffff) == ((d >> 16) & 0xffff));
 759       return (d & 0xffff) == 0x3c00;
 760    case BRW_REGISTER_TYPE_F:
 761       return f == 1.0f;
 762    case BRW_REGISTER_TYPE_DF:
 763       return df == 1.0;
 764    case BRW_REGISTER_TYPE_W:
 765    case BRW_REGISTER_TYPE_UW:
 766       assert((d & 0xffff) == ((d >> 16) & 0xffff));
 767       return (d & 0xffff) == 1;
 768    case BRW_REGISTER_TYPE_D:
 769    case BRW_REGISTER_TYPE_UD:
 770       return d == 1;
 771    case BRW_REGISTER_TYPE_UQ:
 772    case BRW_REGISTER_TYPE_Q:
 773       return u64 == 1;
 774    default:
 775       return false;
 776    }
 777 }
 778
 779 bool
 780 backend_reg::is_negative_one() const
 781 {
 782    if (file != IMM)
 783       return false;
 784
 785    assert(type_sz(type) > 1);
 786
 787    switch (type) {
 788    case BRW_REGISTER_TYPE_HF:
 789       assert((d & 0xffff) == ((d >> 16) & 0xffff));
 790       return (d & 0xffff) == 0xbc00;
 791    case BRW_REGISTER_TYPE_F:
 792       return f == -1.0;
 793    case BRW_REGISTER_TYPE_DF:
 794       return df == -1.0;
 795    case BRW_REGISTER_TYPE_W:
 796       assert((d & 0xffff) == ((d >> 16) & 0xffff));
 797       return (d & 0xffff) == 0xffff;
 798    case BRW_REGISTER_TYPE_D:
 799       return d == -1;
 800    case BRW_REGISTER_TYPE_Q:
 801       return d64 == -1;
 802    default:
 803       return false;
 804    }
 805 }
 806
 807 bool
 808 backend_reg::is_null() const
 809 {
 810    return file == ARF && nr == BRW_ARF_NULL;
 811 }
 812
 813
 814 bool
 815 backend_reg::is_accumulator() const
 816 {
 817    return file == ARF && nr == BRW_ARF_ACCUMULATOR;
 818 }
 819
 820 bool
 821 backend_instruction::is_commutative() const
 822 {
 823    switch (opcode) {
 824    case BRW_OPCODE_AND:
 825    case BRW_OPCODE_OR:
 826    case BRW_OPCODE_XOR:
 827    case BRW_OPCODE_ADD:
 828    case BRW_OPCODE_MUL:
 829    case SHADER_OPCODE_MULH:
 830       return true;
 831    case BRW_OPCODE_SEL:
 832       /* MIN and MAX are commutative. */
 833       if (conditional_mod == BRW_CONDITIONAL_GE ||
 834           conditional_mod == BRW_CONDITIONAL_L) {
 835          return true;
 836       }
 837       /* fallthrough */
 838    default:
 839       return false;
 840    }
 841 }
 842
 843 bool
 844 backend_instruction::is_3src(const struct gen_device_info *devinfo) const
 845 {
 846    return ::is_3src(devinfo, opcode);
 847 }
 848
 849 bool
 850 backend_instruction::is_tex() const
 851 {
 852    return (opcode == SHADER_OPCODE_TEX ||
 853            opcode == FS_OPCODE_TXB ||
 854            opcode == SHADER_OPCODE_TXD ||
 855            opcode == SHADER_OPCODE_TXF ||
 856            opcode == SHADER_OPCODE_TXF_LZ ||
 857            opcode == SHADER_OPCODE_TXF_CMS ||
 858            opcode == SHADER_OPCODE_TXF_CMS_W ||
 859            opcode == SHADER_OPCODE_TXF_UMS ||
 860            opcode == SHADER_OPCODE_TXF_MCS ||
 861            opcode == SHADER_OPCODE_TXL ||
 862            opcode == SHADER_OPCODE_TXL_LZ ||
 863            opcode == SHADER_OPCODE_TXS ||
 864            opcode == SHADER_OPCODE_LOD ||
 865            opcode == SHADER_OPCODE_TG4 ||
 866            opcode == SHADER_OPCODE_TG4_OFFSET ||
 867            opcode == SHADER_OPCODE_SAMPLEINFO);
 868 }
 869
 870 bool
 871 backend_instruction::is_math() const
 872 {
 873    return (opcode == SHADER_OPCODE_RCP ||
 874            opcode == SHADER_OPCODE_RSQ ||
 875            opcode == SHADER_OPCODE_SQRT ||
 876            opcode == SHADER_OPCODE_EXP2 ||
 877            opcode == SHADER_OPCODE_LOG2 ||
 878            opcode == SHADER_OPCODE_SIN ||
 879            opcode == SHADER_OPCODE_COS ||
 880            opcode == SHADER_OPCODE_INT_QUOTIENT ||
 881            opcode == SHADER_OPCODE_INT_REMAINDER ||
 882            opcode == SHADER_OPCODE_POW);
 883 }
 884
 885 bool
 886 backend_instruction::is_control_flow() const
 887 {
 888    switch (opcode) {
 889    case BRW_OPCODE_DO:
 890    case BRW_OPCODE_WHILE:
 891    case BRW_OPCODE_IF:
 892    case BRW_OPCODE_ELSE:
 893    case BRW_OPCODE_ENDIF:
 894    case BRW_OPCODE_BREAK:
 895    case BRW_OPCODE_CONTINUE:
 896       return true;
 897    default:
 898       return false;
 899    }
 900 }
 901
 902 bool
 903 backend_instruction::can_do_source_mods() const
 904 {
 905    switch (opcode) {
 906    case BRW_OPCODE_ADDC:
 907    case BRW_OPCODE_BFE:
 908    case BRW_OPCODE_BFI1:
 909    case BRW_OPCODE_BFI2:
 910    case BRW_OPCODE_BFREV:
 911    case BRW_OPCODE_CBIT:
 912    case BRW_OPCODE_FBH:
 913    case BRW_OPCODE_FBL:
 914    case BRW_OPCODE_SUBB:
 915    case SHADER_OPCODE_BROADCAST:
 916    case SHADER_OPCODE_CLUSTER_BROADCAST:
 917    case SHADER_OPCODE_MOV_INDIRECT:
 918       return false;
 919    default:
 920       return true;
 921    }
 922 }
 923
 924 bool
 925 backend_instruction::can_do_saturate() const
 926 {
 927    switch (opcode) {
 928    case BRW_OPCODE_ADD:
 929    case BRW_OPCODE_ASR:
 930    case BRW_OPCODE_AVG:
 931    case BRW_OPCODE_DP2:
 932    case BRW_OPCODE_DP3:
 933    case BRW_OPCODE_DP4:
 934    case BRW_OPCODE_DPH:
 935    case BRW_OPCODE_F16TO32:
 936    case BRW_OPCODE_F32TO16:
 937    case BRW_OPCODE_LINE:
 938    case BRW_OPCODE_LRP:
 939    case BRW_OPCODE_MAC:
 940    case BRW_OPCODE_MAD:
 941    case BRW_OPCODE_MATH:
 942    case BRW_OPCODE_MOV:
 943    case BRW_OPCODE_MUL:
 944    case SHADER_OPCODE_MULH:
 945    case BRW_OPCODE_PLN:
 946    case BRW_OPCODE_RNDD:
 947    case BRW_OPCODE_RNDE:
 948    case BRW_OPCODE_RNDU:
 949    case BRW_OPCODE_RNDZ:
 950    case BRW_OPCODE_SEL:
 951    case BRW_OPCODE_SHL:
 952    case BRW_OPCODE_SHR:
 953    case FS_OPCODE_LINTERP:
 954    case SHADER_OPCODE_COS:
 955    case SHADER_OPCODE_EXP2:
 956    case SHADER_OPCODE_LOG2:
 957    case SHADER_OPCODE_POW:
 958    case SHADER_OPCODE_RCP:
 959    case SHADER_OPCODE_RSQ:
 960    case SHADER_OPCODE_SIN:
 961    case SHADER_OPCODE_SQRT:
 962       return true;
 963    default:
 964       return false;
 965    }
 966 }
 967
 968 bool
 969 backend_instruction::can_do_cmod() const
 970 {
 971    switch (opcode) {
 972    case BRW_OPCODE_ADD:
 973    case BRW_OPCODE_ADDC:
 974    case BRW_OPCODE_AND:
 975    case BRW_OPCODE_ASR:
 976    case BRW_OPCODE_AVG:
 977    case BRW_OPCODE_CMP:
 978    case BRW_OPCODE_CMPN:
 979    case BRW_OPCODE_DP2:
 980    case BRW_OPCODE_DP3:
 981    case BRW_OPCODE_DP4:
 982    case BRW_OPCODE_DPH:
 983    case BRW_OPCODE_F16TO32:
 984    case BRW_OPCODE_F32TO16:
 985    case BRW_OPCODE_FRC:
 986    case BRW_OPCODE_LINE:
 987    case BRW_OPCODE_LRP:
 988    case BRW_OPCODE_LZD:
 989    case BRW_OPCODE_MAC:
 990    case BRW_OPCODE_MACH:
 991    case BRW_OPCODE_MAD:
 992    case BRW_OPCODE_MOV:
 993    case BRW_OPCODE_MUL:
 994    case BRW_OPCODE_NOT:
 995    case BRW_OPCODE_OR:
 996    case BRW_OPCODE_PLN:
 997    case BRW_OPCODE_RNDD:
 998    case BRW_OPCODE_RNDE:
 999    case BRW_OPCODE_RNDU:
1000    case BRW_OPCODE_RNDZ:
1001    case BRW_OPCODE_SAD2:
1002    case BRW_OPCODE_SADA2:
1003    case BRW_OPCODE_SHL:
1004    case BRW_OPCODE_SHR:
1005    case BRW_OPCODE_SUBB:
1006    case BRW_OPCODE_XOR:
1007    case FS_OPCODE_LINTERP:
1008       return true;
1009    default:
1010       return false;
1011    }
1012 }
1013
1014 bool
1015 backend_instruction::reads_accumulator_implicitly() const
1016 {
1017    switch (opcode) {
1018    case BRW_OPCODE_MAC:
1019    case BRW_OPCODE_MACH:
1020    case BRW_OPCODE_SADA2:
1021       return true;
1022    default:
1023       return false;
1024    }
1025 }
1026
1027 bool
1028 backend_instruction::writes_accumulator_implicitly(const struct gen_device_info *devinfo) const
1029 {
1030    return writes_accumulator ||
1031           (devinfo->gen < 6 &&
1032            ((opcode >= BRW_OPCODE_ADD && opcode < BRW_OPCODE_NOP) ||
1033             (opcode >= FS_OPCODE_DDX_COARSE && opcode <= FS_OPCODE_LINTERP))) ||
1034           (opcode == FS_OPCODE_LINTERP &&
1035            (!devinfo->has_pln || devinfo->gen <= 6));
1036 }
1037
1038 bool
1039 backend_instruction::has_side_effects() const
1040 {
1041    switch (opcode) {
1042    case SHADER_OPCODE_SEND:
1043       return send_has_side_effects;
1044
1045    case VEC4_OPCODE_UNTYPED_ATOMIC:
1046    case SHADER_OPCODE_UNTYPED_ATOMIC_LOGICAL:
1047    case SHADER_OPCODE_UNTYPED_ATOMIC_FLOAT_LOGICAL:
1048    case SHADER_OPCODE_GEN4_SCRATCH_WRITE:
1049    case VEC4_OPCODE_UNTYPED_SURFACE_WRITE:
1050    case SHADER_OPCODE_UNTYPED_SURFACE_WRITE_LOGICAL:
1051    case SHADER_OPCODE_A64_UNTYPED_WRITE_LOGICAL:
1052    case SHADER_OPCODE_A64_BYTE_SCATTERED_WRITE_LOGICAL:
1053    case SHADER_OPCODE_A64_UNTYPED_ATOMIC_LOGICAL:
1054    case SHADER_OPCODE_A64_UNTYPED_ATOMIC_INT64_LOGICAL:
1055    case SHADER_OPCODE_A64_UNTYPED_ATOMIC_FLOAT_LOGICAL:
1056    case SHADER_OPCODE_BYTE_SCATTERED_WRITE_LOGICAL:
1057    case SHADER_OPCODE_TYPED_ATOMIC_LOGICAL:
1058    case SHADER_OPCODE_TYPED_SURFACE_WRITE_LOGICAL:
1059    case SHADER_OPCODE_MEMORY_FENCE:
1060    case SHADER_OPCODE_INTERLOCK:
1061    case SHADER_OPCODE_URB_WRITE_SIMD8:
1062    case SHADER_OPCODE_URB_WRITE_SIMD8_PER_SLOT:
1063    case SHADER_OPCODE_URB_WRITE_SIMD8_MASKED:
1064    case SHADER_OPCODE_URB_WRITE_SIMD8_MASKED_PER_SLOT:
1065    case FS_OPCODE_FB_WRITE:
1066    case FS_OPCODE_FB_WRITE_LOGICAL:
1067    case FS_OPCODE_REP_FB_WRITE:
1068    case SHADER_OPCODE_BARRIER:
1069    case TCS_OPCODE_URB_WRITE:
1070    case TCS_OPCODE_RELEASE_INPUT:
1071    case SHADER_OPCODE_RND_MODE:
1072    case SHADER_OPCODE_FLOAT_CONTROL_MODE:
1073       return true;
1074    default:
1075       return eot;
1076    }
1077 }
1078
1079 bool
1080 backend_instruction::is_volatile() const
1081 {
1082    switch (opcode) {
1083    case SHADER_OPCODE_SEND:
1084       return send_is_volatile;
1085
1086    case VEC4_OPCODE_UNTYPED_SURFACE_READ:
1087    case SHADER_OPCODE_UNTYPED_SURFACE_READ_LOGICAL:
1088    case SHADER_OPCODE_TYPED_SURFACE_READ_LOGICAL:
1089    case SHADER_OPCODE_BYTE_SCATTERED_READ_LOGICAL:
1090    case SHADER_OPCODE_A64_UNTYPED_READ_LOGICAL:
1091    case SHADER_OPCODE_A64_BYTE_SCATTERED_READ_LOGICAL:
1092    case SHADER_OPCODE_URB_READ_SIMD8:
1093    case SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT:
1094    case VEC4_OPCODE_URB_READ:
1095       return true;
1096    default:
1097       return false;
1098    }
1099 }
1100
1101 #ifndef NDEBUG
1102 static bool
1103 inst_is_in_block(const bblock_t *block, const backend_instruction *inst)
1104 {
1105    bool found = false;
1106    foreach_inst_in_block (backend_instruction, i, block) {
1107       if (inst == i) {
1108          found = true;
1109       }
1110    }
1111    return found;
1112 }
1113 #endif
1114
1115 static void
1116 adjust_later_block_ips(bblock_t *start_block, int ip_adjustment)
1117 {
1118    for (bblock_t *block_iter = start_block->next();
1119         block_iter;
1120         block_iter = block_iter->next()) {
1121       block_iter->start_ip += ip_adjustment;
1122       block_iter->end_ip += ip_adjustment;
1123    }
1124 }
1125
1126 void
1127 backend_instruction::insert_after(bblock_t *block, backend_instruction *inst)
1128 {
1129    assert(this != inst);
1130
1131    if (!this->is_head_sentinel())
1132       assert(inst_is_in_block(block, this) || !"Instruction not in block");
1133
1134    block->end_ip++;
1135
1136    adjust_later_block_ips(block, 1);
1137
1138    exec_node::insert_after(inst);
1139 }
1140
1141 void
1142 backend_instruction::insert_before(bblock_t *block, backend_instruction *inst)
1143 {
1144    assert(this != inst);
1145
1146    if (!this->is_tail_sentinel())
1147       assert(inst_is_in_block(block, this) || !"Instruction not in block");
1148
1149    block->end_ip++;
1150
1151    adjust_later_block_ips(block, 1);
1152
1153    exec_node::insert_before(inst);
1154 }
1155
1156 void
1157 backend_instruction::insert_before(bblock_t *block, exec_list *list)
1158 {
1159    assert(inst_is_in_block(block, this) || !"Instruction not in block");
1160
1161    unsigned num_inst = list->length();
1162
1163    block->end_ip += num_inst;
1164
1165    adjust_later_block_ips(block, num_inst);
1166
1167    exec_node::insert_before(list);
1168 }
1169
1170 void
1171 backend_instruction::remove(bblock_t *block)
1172 {
1173    assert(inst_is_in_block(block, this) || !"Instruction not in block");
1174
1175    adjust_later_block_ips(block, -1);
1176
1177    if (block->start_ip == block->end_ip) {
1178       block->cfg->remove_block(block);
1179    } else {
1180       block->end_ip--;
1181    }
1182
1183    exec_node::remove();
1184 }
1185
1186 void
1187 backend_shader::dump_instructions()
1188 {
1189    dump_instructions(NULL);
1190 }
1191
1192 void
1193 backend_shader::dump_instructions(const char *name)
1194 {
1195    FILE *file = stderr;
1196    if (name && geteuid() != 0) {
1197       file = fopen(name, "w");
1198       if (!file)
1199          file = stderr;
1200    }
1201
1202    if (cfg) {
1203       int ip = 0;
1204       foreach_block_and_inst(block, backend_instruction, inst, cfg) {
1205          if (!unlikely(INTEL_DEBUG & DEBUG_OPTIMIZER))
1206             fprintf(file, "%4d: ", ip++);
1207          dump_instruction(inst, file);
1208       }
1209    } else {
1210       int ip = 0;
1211       foreach_in_list(backend_instruction, inst, &instructions) {
1212          if (!unlikely(INTEL_DEBUG & DEBUG_OPTIMIZER))
1213             fprintf(file, "%4d: ", ip++);
1214          dump_instruction(inst, file);
1215       }
1216    }
1217
1218    if (file != stderr) {
1219       fclose(file);
1220    }
1221 }
1222
1223 void
1224 backend_shader::calculate_cfg()
1225 {
1226    if (this->cfg)
1227       return;
1228    cfg = new(mem_ctx) cfg_t(&this->instructions);
1229 }
1230
1231 extern "C" const unsigned *
1232 brw_compile_tes(const struct brw_compiler *compiler,
1233                 void *log_data,
1234                 void *mem_ctx,
1235                 const struct brw_tes_prog_key *key,
1236                 const struct brw_vue_map *input_vue_map,
1237                 struct brw_tes_prog_data *prog_data,
1238                 nir_shader *nir,
1239                 int shader_time_index,
1240                 struct brw_compile_stats *stats,
1241                 char **error_str)
1242 {
1243    const struct gen_device_info *devinfo = compiler->devinfo;
1244    const bool is_scalar = compiler->scalar_stage[MESA_SHADER_TESS_EVAL];
1245    const unsigned *assembly;
1246
1247    nir->info.inputs_read = key->inputs_read;
1248    nir->info.patch_inputs_read = key->patch_inputs_read;
1249
1250    brw_nir_apply_key(nir, compiler, &key->base, 8, is_scalar);
1251    brw_nir_lower_tes_inputs(nir, input_vue_map);
1252    brw_nir_lower_vue_outputs(nir);
1253    brw_postprocess_nir(nir, compiler, is_scalar);
1254
1255    brw_compute_vue_map(devinfo, &prog_data->base.vue_map,
1256                        nir->info.outputs_written,
1257                        nir->info.separate_shader);
1258
1259    unsigned output_size_bytes = prog_data->base.vue_map.num_slots * 4 * 4;
1260
1261    assert(output_size_bytes >= 1);
1262    if (output_size_bytes > GEN7_MAX_DS_URB_ENTRY_SIZE_BYTES) {
1263       if (error_str)
1264          *error_str = ralloc_strdup(mem_ctx, "DS outputs exceed maximum size");
1265       return NULL;
1266    }
1267
1268    prog_data->base.clip_distance_mask =
1269       ((1 << nir->info.clip_distance_array_size) - 1);
1270    prog_data->base.cull_distance_mask =
1271       ((1 << nir->info.cull_distance_array_size) - 1) <<
1272       nir->info.clip_distance_array_size;
1273
1274    /* URB entry sizes are stored as a multiple of 64 bytes. */
1275    prog_data->base.urb_entry_size = ALIGN(output_size_bytes, 64) / 64;
1276
1277    /* On Cannonlake software shall not program an allocation size that
1278     * specifies a size that is a multiple of 3 64B (512-bit) cachelines.
1279     */
1280    if (devinfo->gen == 10 &&
1281        prog_data->base.urb_entry_size % 3 == 0)
1282       prog_data->base.urb_entry_size++;
1283
1284    prog_data->base.urb_read_length = 0;
1285
1286    STATIC_ASSERT(BRW_TESS_PARTITIONING_INTEGER == TESS_SPACING_EQUAL - 1);
1287    STATIC_ASSERT(BRW_TESS_PARTITIONING_ODD_FRACTIONAL ==
1288                  TESS_SPACING_FRACTIONAL_ODD - 1);
1289    STATIC_ASSERT(BRW_TESS_PARTITIONING_EVEN_FRACTIONAL ==
1290                  TESS_SPACING_FRACTIONAL_EVEN - 1);
1291
1292    prog_data->partitioning =
1293       (enum brw_tess_partitioning) (nir->info.tess.spacing - 1);
1294
1295    switch (nir->info.tess.primitive_mode) {
1296    case GL_QUADS:
1297       prog_data->domain = BRW_TESS_DOMAIN_QUAD;
1298       break;
1299    case GL_TRIANGLES:
1300       prog_data->domain = BRW_TESS_DOMAIN_TRI;
1301       break;
1302    case GL_ISOLINES:
1303       prog_data->domain = BRW_TESS_DOMAIN_ISOLINE;
1304       break;
1305    default:
1306       unreachable("invalid domain shader primitive mode");
1307    }
1308
1309    if (nir->info.tess.point_mode) {
1310       prog_data->output_topology = BRW_TESS_OUTPUT_TOPOLOGY_POINT;
1311    } else if (nir->info.tess.primitive_mode == GL_ISOLINES) {
1312       prog_data->output_topology = BRW_TESS_OUTPUT_TOPOLOGY_LINE;
1313    } else {
1314       /* Hardware winding order is backwards from OpenGL */
1315       prog_data->output_topology =
1316          nir->info.tess.ccw ? BRW_TESS_OUTPUT_TOPOLOGY_TRI_CW
1317                              : BRW_TESS_OUTPUT_TOPOLOGY_TRI_CCW;
1318    }
1319
1320    if (unlikely(INTEL_DEBUG & DEBUG_TES)) {
1321       fprintf(stderr, "TES Input ");
1322       brw_print_vue_map(stderr, input_vue_map);
1323       fprintf(stderr, "TES Output ");
1324       brw_print_vue_map(stderr, &prog_data->base.vue_map);
1325    }
1326
1327    if (is_scalar) {
1328       fs_visitor v(compiler, log_data, mem_ctx, &key->base,
1329                    &prog_data->base.base, nir, 8,
1330                    shader_time_index, input_vue_map);
1331       if (!v.run_tes()) {
1332          if (error_str)
1333             *error_str = ralloc_strdup(mem_ctx, v.fail_msg);
1334          return NULL;
1335       }
1336
1337       prog_data->base.base.dispatch_grf_start_reg = v.payload.num_regs;
1338       prog_data->base.dispatch_mode = DISPATCH_MODE_SIMD8;
1339
1340       fs_generator g(compiler, log_data, mem_ctx,
1341                      &prog_data->base.base, v.shader_stats, false,
1342                      MESA_SHADER_TESS_EVAL);
1343       if (unlikely(INTEL_DEBUG & DEBUG_TES)) {
1344          g.enable_debug(ralloc_asprintf(mem_ctx,
1345                                         "%s tessellation evaluation shader %s",
1346                                         nir->info.label ? nir->info.label
1347                                                         : "unnamed",
1348                                         nir->info.name));
1349       }
1350
1351       g.generate_code(v.cfg, 8, stats);
1352
1353       assembly = g.get_assembly();
1354    } else {
1355       brw::vec4_tes_visitor v(compiler, log_data, key, prog_data,
1356                               nir, mem_ctx, shader_time_index);
1357       if (!v.run()) {
1358          if (error_str)
1359             *error_str = ralloc_strdup(mem_ctx, v.fail_msg);
1360          return NULL;
1361       }
1362
1363       if (unlikely(INTEL_DEBUG & DEBUG_TES))
1364          v.dump_instructions();
1365
1366       assembly = brw_vec4_generate_assembly(compiler, log_data, mem_ctx, nir,
1367                                             &prog_data->base, v.cfg, stats);
1368    }
1369
1370    return assembly;
1371 }