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[mesa.git] / src / intel / compiler / brw_shader.cpp
1 /*
2 * Copyright © 2010 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 */
23
24 #include "brw_cfg.h"
25 #include "brw_eu.h"
26 #include "brw_fs.h"
27 #include "brw_nir.h"
28 #include "brw_vec4_tes.h"
29 #include "dev/gen_debug.h"
30 #include "main/uniforms.h"
31 #include "util/macros.h"
32
33 enum brw_reg_type
34 brw_type_for_base_type(const struct glsl_type *type)
35 {
36 switch (type->base_type) {
37 case GLSL_TYPE_FLOAT16:
38 return BRW_REGISTER_TYPE_HF;
39 case GLSL_TYPE_FLOAT:
40 return BRW_REGISTER_TYPE_F;
41 case GLSL_TYPE_INT:
42 case GLSL_TYPE_BOOL:
43 case GLSL_TYPE_SUBROUTINE:
44 return BRW_REGISTER_TYPE_D;
45 case GLSL_TYPE_INT16:
46 return BRW_REGISTER_TYPE_W;
47 case GLSL_TYPE_INT8:
48 return BRW_REGISTER_TYPE_B;
49 case GLSL_TYPE_UINT:
50 return BRW_REGISTER_TYPE_UD;
51 case GLSL_TYPE_UINT16:
52 return BRW_REGISTER_TYPE_UW;
53 case GLSL_TYPE_UINT8:
54 return BRW_REGISTER_TYPE_UB;
55 case GLSL_TYPE_ARRAY:
56 return brw_type_for_base_type(type->fields.array);
57 case GLSL_TYPE_STRUCT:
58 case GLSL_TYPE_INTERFACE:
59 case GLSL_TYPE_SAMPLER:
60 case GLSL_TYPE_ATOMIC_UINT:
61 /* These should be overridden with the type of the member when
62 * dereferenced into. BRW_REGISTER_TYPE_UD seems like a likely
63 * way to trip up if we don't.
64 */
65 return BRW_REGISTER_TYPE_UD;
66 case GLSL_TYPE_IMAGE:
67 return BRW_REGISTER_TYPE_UD;
68 case GLSL_TYPE_DOUBLE:
69 return BRW_REGISTER_TYPE_DF;
70 case GLSL_TYPE_UINT64:
71 return BRW_REGISTER_TYPE_UQ;
72 case GLSL_TYPE_INT64:
73 return BRW_REGISTER_TYPE_Q;
74 case GLSL_TYPE_VOID:
75 case GLSL_TYPE_ERROR:
76 case GLSL_TYPE_FUNCTION:
77 unreachable("not reached");
78 }
79
80 return BRW_REGISTER_TYPE_F;
81 }
82
83 enum brw_conditional_mod
84 brw_conditional_for_comparison(unsigned int op)
85 {
86 switch (op) {
87 case ir_binop_less:
88 return BRW_CONDITIONAL_L;
89 case ir_binop_gequal:
90 return BRW_CONDITIONAL_GE;
91 case ir_binop_equal:
92 case ir_binop_all_equal: /* same as equal for scalars */
93 return BRW_CONDITIONAL_Z;
94 case ir_binop_nequal:
95 case ir_binop_any_nequal: /* same as nequal for scalars */
96 return BRW_CONDITIONAL_NZ;
97 default:
98 unreachable("not reached: bad operation for comparison");
99 }
100 }
101
102 uint32_t
103 brw_math_function(enum opcode op)
104 {
105 switch (op) {
106 case SHADER_OPCODE_RCP:
107 return BRW_MATH_FUNCTION_INV;
108 case SHADER_OPCODE_RSQ:
109 return BRW_MATH_FUNCTION_RSQ;
110 case SHADER_OPCODE_SQRT:
111 return BRW_MATH_FUNCTION_SQRT;
112 case SHADER_OPCODE_EXP2:
113 return BRW_MATH_FUNCTION_EXP;
114 case SHADER_OPCODE_LOG2:
115 return BRW_MATH_FUNCTION_LOG;
116 case SHADER_OPCODE_POW:
117 return BRW_MATH_FUNCTION_POW;
118 case SHADER_OPCODE_SIN:
119 return BRW_MATH_FUNCTION_SIN;
120 case SHADER_OPCODE_COS:
121 return BRW_MATH_FUNCTION_COS;
122 case SHADER_OPCODE_INT_QUOTIENT:
123 return BRW_MATH_FUNCTION_INT_DIV_QUOTIENT;
124 case SHADER_OPCODE_INT_REMAINDER:
125 return BRW_MATH_FUNCTION_INT_DIV_REMAINDER;
126 default:
127 unreachable("not reached: unknown math function");
128 }
129 }
130
131 bool
132 brw_texture_offset(const nir_tex_instr *tex, unsigned src,
133 uint32_t *offset_bits_out)
134 {
135 if (!nir_src_is_const(tex->src[src].src))
136 return false;
137
138 const unsigned num_components = nir_tex_instr_src_size(tex, src);
139
140 /* Combine all three offsets into a single unsigned dword:
141 *
142 * bits 11:8 - U Offset (X component)
143 * bits 7:4 - V Offset (Y component)
144 * bits 3:0 - R Offset (Z component)
145 */
146 uint32_t offset_bits = 0;
147 for (unsigned i = 0; i < num_components; i++) {
148 int offset = nir_src_comp_as_int(tex->src[src].src, i);
149
150 /* offset out of bounds; caller will handle it. */
151 if (offset > 7 || offset < -8)
152 return false;
153
154 const unsigned shift = 4 * (2 - i);
155 offset_bits |= (offset << shift) & (0xF << shift);
156 }
157
158 *offset_bits_out = offset_bits;
159
160 return true;
161 }
162
163 const char *
164 brw_instruction_name(const struct gen_device_info *devinfo, enum opcode op)
165 {
166 switch (op) {
167 case 0 ... NUM_BRW_OPCODES - 1:
168 /* The DO instruction doesn't exist on Gen6+, but we use it to mark the
169 * start of a loop in the IR.
170 */
171 if (devinfo->gen >= 6 && op == BRW_OPCODE_DO)
172 return "do";
173
174 /* The following conversion opcodes doesn't exist on Gen8+, but we use
175 * then to mark that we want to do the conversion.
176 */
177 if (devinfo->gen > 7 && op == BRW_OPCODE_F32TO16)
178 return "f32to16";
179
180 if (devinfo->gen > 7 && op == BRW_OPCODE_F16TO32)
181 return "f16to32";
182
183 assert(brw_opcode_desc(devinfo, op)->name);
184 return brw_opcode_desc(devinfo, op)->name;
185 case FS_OPCODE_FB_WRITE:
186 return "fb_write";
187 case FS_OPCODE_FB_WRITE_LOGICAL:
188 return "fb_write_logical";
189 case FS_OPCODE_REP_FB_WRITE:
190 return "rep_fb_write";
191 case FS_OPCODE_FB_READ:
192 return "fb_read";
193 case FS_OPCODE_FB_READ_LOGICAL:
194 return "fb_read_logical";
195
196 case SHADER_OPCODE_RCP:
197 return "rcp";
198 case SHADER_OPCODE_RSQ:
199 return "rsq";
200 case SHADER_OPCODE_SQRT:
201 return "sqrt";
202 case SHADER_OPCODE_EXP2:
203 return "exp2";
204 case SHADER_OPCODE_LOG2:
205 return "log2";
206 case SHADER_OPCODE_POW:
207 return "pow";
208 case SHADER_OPCODE_INT_QUOTIENT:
209 return "int_quot";
210 case SHADER_OPCODE_INT_REMAINDER:
211 return "int_rem";
212 case SHADER_OPCODE_SIN:
213 return "sin";
214 case SHADER_OPCODE_COS:
215 return "cos";
216
217 case SHADER_OPCODE_SEND:
218 return "send";
219
220 case SHADER_OPCODE_UNDEF:
221 return "undef";
222
223 case SHADER_OPCODE_TEX:
224 return "tex";
225 case SHADER_OPCODE_TEX_LOGICAL:
226 return "tex_logical";
227 case SHADER_OPCODE_TXD:
228 return "txd";
229 case SHADER_OPCODE_TXD_LOGICAL:
230 return "txd_logical";
231 case SHADER_OPCODE_TXF:
232 return "txf";
233 case SHADER_OPCODE_TXF_LOGICAL:
234 return "txf_logical";
235 case SHADER_OPCODE_TXF_LZ:
236 return "txf_lz";
237 case SHADER_OPCODE_TXL:
238 return "txl";
239 case SHADER_OPCODE_TXL_LOGICAL:
240 return "txl_logical";
241 case SHADER_OPCODE_TXL_LZ:
242 return "txl_lz";
243 case SHADER_OPCODE_TXS:
244 return "txs";
245 case SHADER_OPCODE_TXS_LOGICAL:
246 return "txs_logical";
247 case FS_OPCODE_TXB:
248 return "txb";
249 case FS_OPCODE_TXB_LOGICAL:
250 return "txb_logical";
251 case SHADER_OPCODE_TXF_CMS:
252 return "txf_cms";
253 case SHADER_OPCODE_TXF_CMS_LOGICAL:
254 return "txf_cms_logical";
255 case SHADER_OPCODE_TXF_CMS_W:
256 return "txf_cms_w";
257 case SHADER_OPCODE_TXF_CMS_W_LOGICAL:
258 return "txf_cms_w_logical";
259 case SHADER_OPCODE_TXF_UMS:
260 return "txf_ums";
261 case SHADER_OPCODE_TXF_UMS_LOGICAL:
262 return "txf_ums_logical";
263 case SHADER_OPCODE_TXF_MCS:
264 return "txf_mcs";
265 case SHADER_OPCODE_TXF_MCS_LOGICAL:
266 return "txf_mcs_logical";
267 case SHADER_OPCODE_LOD:
268 return "lod";
269 case SHADER_OPCODE_LOD_LOGICAL:
270 return "lod_logical";
271 case SHADER_OPCODE_TG4:
272 return "tg4";
273 case SHADER_OPCODE_TG4_LOGICAL:
274 return "tg4_logical";
275 case SHADER_OPCODE_TG4_OFFSET:
276 return "tg4_offset";
277 case SHADER_OPCODE_TG4_OFFSET_LOGICAL:
278 return "tg4_offset_logical";
279 case SHADER_OPCODE_SAMPLEINFO:
280 return "sampleinfo";
281 case SHADER_OPCODE_SAMPLEINFO_LOGICAL:
282 return "sampleinfo_logical";
283
284 case SHADER_OPCODE_IMAGE_SIZE_LOGICAL:
285 return "image_size_logical";
286
287 case SHADER_OPCODE_SHADER_TIME_ADD:
288 return "shader_time_add";
289
290 case VEC4_OPCODE_UNTYPED_ATOMIC:
291 return "untyped_atomic";
292 case SHADER_OPCODE_UNTYPED_ATOMIC_LOGICAL:
293 return "untyped_atomic_logical";
294 case SHADER_OPCODE_UNTYPED_ATOMIC_FLOAT_LOGICAL:
295 return "untyped_atomic_float_logical";
296 case VEC4_OPCODE_UNTYPED_SURFACE_READ:
297 return "untyped_surface_read";
298 case SHADER_OPCODE_UNTYPED_SURFACE_READ_LOGICAL:
299 return "untyped_surface_read_logical";
300 case VEC4_OPCODE_UNTYPED_SURFACE_WRITE:
301 return "untyped_surface_write";
302 case SHADER_OPCODE_UNTYPED_SURFACE_WRITE_LOGICAL:
303 return "untyped_surface_write_logical";
304 case SHADER_OPCODE_A64_UNTYPED_READ_LOGICAL:
305 return "a64_untyped_read_logical";
306 case SHADER_OPCODE_A64_UNTYPED_WRITE_LOGICAL:
307 return "a64_untyped_write_logical";
308 case SHADER_OPCODE_A64_BYTE_SCATTERED_READ_LOGICAL:
309 return "a64_byte_scattered_read_logical";
310 case SHADER_OPCODE_A64_BYTE_SCATTERED_WRITE_LOGICAL:
311 return "a64_byte_scattered_write_logical";
312 case SHADER_OPCODE_A64_UNTYPED_ATOMIC_LOGICAL:
313 return "a64_untyped_atomic_logical";
314 case SHADER_OPCODE_A64_UNTYPED_ATOMIC_INT64_LOGICAL:
315 return "a64_untyped_atomic_int64_logical";
316 case SHADER_OPCODE_A64_UNTYPED_ATOMIC_FLOAT_LOGICAL:
317 return "a64_untyped_atomic_float_logical";
318 case SHADER_OPCODE_TYPED_ATOMIC_LOGICAL:
319 return "typed_atomic_logical";
320 case SHADER_OPCODE_TYPED_SURFACE_READ_LOGICAL:
321 return "typed_surface_read_logical";
322 case SHADER_OPCODE_TYPED_SURFACE_WRITE_LOGICAL:
323 return "typed_surface_write_logical";
324 case SHADER_OPCODE_MEMORY_FENCE:
325 return "memory_fence";
326 case SHADER_OPCODE_INTERLOCK:
327 /* For an interlock we actually issue a memory fence via sendc. */
328 return "interlock";
329
330 case SHADER_OPCODE_BYTE_SCATTERED_READ_LOGICAL:
331 return "byte_scattered_read_logical";
332 case SHADER_OPCODE_BYTE_SCATTERED_WRITE_LOGICAL:
333 return "byte_scattered_write_logical";
334 case SHADER_OPCODE_DWORD_SCATTERED_READ_LOGICAL:
335 return "dword_scattered_read_logical";
336 case SHADER_OPCODE_DWORD_SCATTERED_WRITE_LOGICAL:
337 return "dword_scattered_write_logical";
338
339 case SHADER_OPCODE_LOAD_PAYLOAD:
340 return "load_payload";
341 case FS_OPCODE_PACK:
342 return "pack";
343
344 case SHADER_OPCODE_GEN4_SCRATCH_READ:
345 return "gen4_scratch_read";
346 case SHADER_OPCODE_GEN4_SCRATCH_WRITE:
347 return "gen4_scratch_write";
348 case SHADER_OPCODE_GEN7_SCRATCH_READ:
349 return "gen7_scratch_read";
350 case SHADER_OPCODE_URB_WRITE_SIMD8:
351 return "gen8_urb_write_simd8";
352 case SHADER_OPCODE_URB_WRITE_SIMD8_PER_SLOT:
353 return "gen8_urb_write_simd8_per_slot";
354 case SHADER_OPCODE_URB_WRITE_SIMD8_MASKED:
355 return "gen8_urb_write_simd8_masked";
356 case SHADER_OPCODE_URB_WRITE_SIMD8_MASKED_PER_SLOT:
357 return "gen8_urb_write_simd8_masked_per_slot";
358 case SHADER_OPCODE_URB_READ_SIMD8:
359 return "urb_read_simd8";
360 case SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT:
361 return "urb_read_simd8_per_slot";
362
363 case SHADER_OPCODE_FIND_LIVE_CHANNEL:
364 return "find_live_channel";
365 case SHADER_OPCODE_BROADCAST:
366 return "broadcast";
367 case SHADER_OPCODE_SHUFFLE:
368 return "shuffle";
369 case SHADER_OPCODE_SEL_EXEC:
370 return "sel_exec";
371 case SHADER_OPCODE_QUAD_SWIZZLE:
372 return "quad_swizzle";
373 case SHADER_OPCODE_CLUSTER_BROADCAST:
374 return "cluster_broadcast";
375
376 case SHADER_OPCODE_GET_BUFFER_SIZE:
377 return "get_buffer_size";
378
379 case VEC4_OPCODE_MOV_BYTES:
380 return "mov_bytes";
381 case VEC4_OPCODE_PACK_BYTES:
382 return "pack_bytes";
383 case VEC4_OPCODE_UNPACK_UNIFORM:
384 return "unpack_uniform";
385 case VEC4_OPCODE_DOUBLE_TO_F32:
386 return "double_to_f32";
387 case VEC4_OPCODE_DOUBLE_TO_D32:
388 return "double_to_d32";
389 case VEC4_OPCODE_DOUBLE_TO_U32:
390 return "double_to_u32";
391 case VEC4_OPCODE_TO_DOUBLE:
392 return "single_to_double";
393 case VEC4_OPCODE_PICK_LOW_32BIT:
394 return "pick_low_32bit";
395 case VEC4_OPCODE_PICK_HIGH_32BIT:
396 return "pick_high_32bit";
397 case VEC4_OPCODE_SET_LOW_32BIT:
398 return "set_low_32bit";
399 case VEC4_OPCODE_SET_HIGH_32BIT:
400 return "set_high_32bit";
401
402 case FS_OPCODE_DDX_COARSE:
403 return "ddx_coarse";
404 case FS_OPCODE_DDX_FINE:
405 return "ddx_fine";
406 case FS_OPCODE_DDY_COARSE:
407 return "ddy_coarse";
408 case FS_OPCODE_DDY_FINE:
409 return "ddy_fine";
410
411 case FS_OPCODE_LINTERP:
412 return "linterp";
413
414 case FS_OPCODE_PIXEL_X:
415 return "pixel_x";
416 case FS_OPCODE_PIXEL_Y:
417 return "pixel_y";
418
419 case FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD:
420 return "uniform_pull_const";
421 case FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD_GEN7:
422 return "uniform_pull_const_gen7";
423 case FS_OPCODE_VARYING_PULL_CONSTANT_LOAD_GEN4:
424 return "varying_pull_const_gen4";
425 case FS_OPCODE_VARYING_PULL_CONSTANT_LOAD_LOGICAL:
426 return "varying_pull_const_logical";
427
428 case FS_OPCODE_DISCARD_JUMP:
429 return "discard_jump";
430
431 case FS_OPCODE_SET_SAMPLE_ID:
432 return "set_sample_id";
433
434 case FS_OPCODE_PACK_HALF_2x16_SPLIT:
435 return "pack_half_2x16_split";
436
437 case FS_OPCODE_PLACEHOLDER_HALT:
438 return "placeholder_halt";
439
440 case FS_OPCODE_INTERPOLATE_AT_SAMPLE:
441 return "interp_sample";
442 case FS_OPCODE_INTERPOLATE_AT_SHARED_OFFSET:
443 return "interp_shared_offset";
444 case FS_OPCODE_INTERPOLATE_AT_PER_SLOT_OFFSET:
445 return "interp_per_slot_offset";
446
447 case VS_OPCODE_URB_WRITE:
448 return "vs_urb_write";
449 case VS_OPCODE_PULL_CONSTANT_LOAD:
450 return "pull_constant_load";
451 case VS_OPCODE_PULL_CONSTANT_LOAD_GEN7:
452 return "pull_constant_load_gen7";
453
454 case VS_OPCODE_SET_SIMD4X2_HEADER_GEN9:
455 return "set_simd4x2_header_gen9";
456
457 case VS_OPCODE_UNPACK_FLAGS_SIMD4X2:
458 return "unpack_flags_simd4x2";
459
460 case GS_OPCODE_URB_WRITE:
461 return "gs_urb_write";
462 case GS_OPCODE_URB_WRITE_ALLOCATE:
463 return "gs_urb_write_allocate";
464 case GS_OPCODE_THREAD_END:
465 return "gs_thread_end";
466 case GS_OPCODE_SET_WRITE_OFFSET:
467 return "set_write_offset";
468 case GS_OPCODE_SET_VERTEX_COUNT:
469 return "set_vertex_count";
470 case GS_OPCODE_SET_DWORD_2:
471 return "set_dword_2";
472 case GS_OPCODE_PREPARE_CHANNEL_MASKS:
473 return "prepare_channel_masks";
474 case GS_OPCODE_SET_CHANNEL_MASKS:
475 return "set_channel_masks";
476 case GS_OPCODE_GET_INSTANCE_ID:
477 return "get_instance_id";
478 case GS_OPCODE_FF_SYNC:
479 return "ff_sync";
480 case GS_OPCODE_SET_PRIMITIVE_ID:
481 return "set_primitive_id";
482 case GS_OPCODE_SVB_WRITE:
483 return "gs_svb_write";
484 case GS_OPCODE_SVB_SET_DST_INDEX:
485 return "gs_svb_set_dst_index";
486 case GS_OPCODE_FF_SYNC_SET_PRIMITIVES:
487 return "gs_ff_sync_set_primitives";
488 case CS_OPCODE_CS_TERMINATE:
489 return "cs_terminate";
490 case SHADER_OPCODE_BARRIER:
491 return "barrier";
492 case SHADER_OPCODE_MULH:
493 return "mulh";
494 case SHADER_OPCODE_MOV_INDIRECT:
495 return "mov_indirect";
496
497 case VEC4_OPCODE_URB_READ:
498 return "urb_read";
499 case TCS_OPCODE_GET_INSTANCE_ID:
500 return "tcs_get_instance_id";
501 case TCS_OPCODE_URB_WRITE:
502 return "tcs_urb_write";
503 case TCS_OPCODE_SET_INPUT_URB_OFFSETS:
504 return "tcs_set_input_urb_offsets";
505 case TCS_OPCODE_SET_OUTPUT_URB_OFFSETS:
506 return "tcs_set_output_urb_offsets";
507 case TCS_OPCODE_GET_PRIMITIVE_ID:
508 return "tcs_get_primitive_id";
509 case TCS_OPCODE_CREATE_BARRIER_HEADER:
510 return "tcs_create_barrier_header";
511 case TCS_OPCODE_SRC0_010_IS_ZERO:
512 return "tcs_src0<0,1,0>_is_zero";
513 case TCS_OPCODE_RELEASE_INPUT:
514 return "tcs_release_input";
515 case TCS_OPCODE_THREAD_END:
516 return "tcs_thread_end";
517 case TES_OPCODE_CREATE_INPUT_READ_HEADER:
518 return "tes_create_input_read_header";
519 case TES_OPCODE_ADD_INDIRECT_URB_OFFSET:
520 return "tes_add_indirect_urb_offset";
521 case TES_OPCODE_GET_PRIMITIVE_ID:
522 return "tes_get_primitive_id";
523
524 case SHADER_OPCODE_RND_MODE:
525 return "rnd_mode";
526 case SHADER_OPCODE_FLOAT_CONTROL_MODE:
527 return "float_control_mode";
528 }
529
530 unreachable("not reached");
531 }
532
533 bool
534 brw_saturate_immediate(enum brw_reg_type type, struct brw_reg *reg)
535 {
536 union {
537 unsigned ud;
538 int d;
539 float f;
540 double df;
541 } imm, sat_imm = { 0 };
542
543 const unsigned size = type_sz(type);
544
545 /* We want to either do a 32-bit or 64-bit data copy, the type is otherwise
546 * irrelevant, so just check the size of the type and copy from/to an
547 * appropriately sized field.
548 */
549 if (size < 8)
550 imm.ud = reg->ud;
551 else
552 imm.df = reg->df;
553
554 switch (type) {
555 case BRW_REGISTER_TYPE_UD:
556 case BRW_REGISTER_TYPE_D:
557 case BRW_REGISTER_TYPE_UW:
558 case BRW_REGISTER_TYPE_W:
559 case BRW_REGISTER_TYPE_UQ:
560 case BRW_REGISTER_TYPE_Q:
561 /* Nothing to do. */
562 return false;
563 case BRW_REGISTER_TYPE_F:
564 sat_imm.f = CLAMP(imm.f, 0.0f, 1.0f);
565 break;
566 case BRW_REGISTER_TYPE_DF:
567 sat_imm.df = CLAMP(imm.df, 0.0, 1.0);
568 break;
569 case BRW_REGISTER_TYPE_UB:
570 case BRW_REGISTER_TYPE_B:
571 unreachable("no UB/B immediates");
572 case BRW_REGISTER_TYPE_V:
573 case BRW_REGISTER_TYPE_UV:
574 case BRW_REGISTER_TYPE_VF:
575 unreachable("unimplemented: saturate vector immediate");
576 case BRW_REGISTER_TYPE_HF:
577 unreachable("unimplemented: saturate HF immediate");
578 case BRW_REGISTER_TYPE_NF:
579 unreachable("no NF immediates");
580 }
581
582 if (size < 8) {
583 if (imm.ud != sat_imm.ud) {
584 reg->ud = sat_imm.ud;
585 return true;
586 }
587 } else {
588 if (imm.df != sat_imm.df) {
589 reg->df = sat_imm.df;
590 return true;
591 }
592 }
593 return false;
594 }
595
596 bool
597 brw_negate_immediate(enum brw_reg_type type, struct brw_reg *reg)
598 {
599 switch (type) {
600 case BRW_REGISTER_TYPE_D:
601 case BRW_REGISTER_TYPE_UD:
602 reg->d = -reg->d;
603 return true;
604 case BRW_REGISTER_TYPE_W:
605 case BRW_REGISTER_TYPE_UW: {
606 uint16_t value = -(int16_t)reg->ud;
607 reg->ud = value | (uint32_t)value << 16;
608 return true;
609 }
610 case BRW_REGISTER_TYPE_F:
611 reg->f = -reg->f;
612 return true;
613 case BRW_REGISTER_TYPE_VF:
614 reg->ud ^= 0x80808080;
615 return true;
616 case BRW_REGISTER_TYPE_DF:
617 reg->df = -reg->df;
618 return true;
619 case BRW_REGISTER_TYPE_UQ:
620 case BRW_REGISTER_TYPE_Q:
621 reg->d64 = -reg->d64;
622 return true;
623 case BRW_REGISTER_TYPE_UB:
624 case BRW_REGISTER_TYPE_B:
625 unreachable("no UB/B immediates");
626 case BRW_REGISTER_TYPE_UV:
627 case BRW_REGISTER_TYPE_V:
628 assert(!"unimplemented: negate UV/V immediate");
629 case BRW_REGISTER_TYPE_HF:
630 reg->ud ^= 0x80008000;
631 return true;
632 case BRW_REGISTER_TYPE_NF:
633 unreachable("no NF immediates");
634 }
635
636 return false;
637 }
638
639 bool
640 brw_abs_immediate(enum brw_reg_type type, struct brw_reg *reg)
641 {
642 switch (type) {
643 case BRW_REGISTER_TYPE_D:
644 reg->d = abs(reg->d);
645 return true;
646 case BRW_REGISTER_TYPE_W: {
647 uint16_t value = abs((int16_t)reg->ud);
648 reg->ud = value | (uint32_t)value << 16;
649 return true;
650 }
651 case BRW_REGISTER_TYPE_F:
652 reg->f = fabsf(reg->f);
653 return true;
654 case BRW_REGISTER_TYPE_DF:
655 reg->df = fabs(reg->df);
656 return true;
657 case BRW_REGISTER_TYPE_VF:
658 reg->ud &= ~0x80808080;
659 return true;
660 case BRW_REGISTER_TYPE_Q:
661 reg->d64 = imaxabs(reg->d64);
662 return true;
663 case BRW_REGISTER_TYPE_UB:
664 case BRW_REGISTER_TYPE_B:
665 unreachable("no UB/B immediates");
666 case BRW_REGISTER_TYPE_UQ:
667 case BRW_REGISTER_TYPE_UD:
668 case BRW_REGISTER_TYPE_UW:
669 case BRW_REGISTER_TYPE_UV:
670 /* Presumably the absolute value modifier on an unsigned source is a
671 * nop, but it would be nice to confirm.
672 */
673 assert(!"unimplemented: abs unsigned immediate");
674 case BRW_REGISTER_TYPE_V:
675 assert(!"unimplemented: abs V immediate");
676 case BRW_REGISTER_TYPE_HF:
677 reg->ud &= ~0x80008000;
678 return true;
679 case BRW_REGISTER_TYPE_NF:
680 unreachable("no NF immediates");
681 }
682
683 return false;
684 }
685
686 backend_shader::backend_shader(const struct brw_compiler *compiler,
687 void *log_data,
688 void *mem_ctx,
689 const nir_shader *shader,
690 struct brw_stage_prog_data *stage_prog_data)
691 : compiler(compiler),
692 log_data(log_data),
693 devinfo(compiler->devinfo),
694 nir(shader),
695 stage_prog_data(stage_prog_data),
696 mem_ctx(mem_ctx),
697 cfg(NULL),
698 stage(shader->info.stage)
699 {
700 debug_enabled = INTEL_DEBUG & intel_debug_flag_for_shader_stage(stage);
701 stage_name = _mesa_shader_stage_to_string(stage);
702 stage_abbrev = _mesa_shader_stage_to_abbrev(stage);
703 }
704
705 backend_shader::~backend_shader()
706 {
707 }
708
709 bool
710 backend_reg::equals(const backend_reg &r) const
711 {
712 return brw_regs_equal(this, &r) && offset == r.offset;
713 }
714
715 bool
716 backend_reg::negative_equals(const backend_reg &r) const
717 {
718 return brw_regs_negative_equal(this, &r) && offset == r.offset;
719 }
720
721 bool
722 backend_reg::is_zero() const
723 {
724 if (file != IMM)
725 return false;
726
727 assert(type_sz(type) > 1);
728
729 switch (type) {
730 case BRW_REGISTER_TYPE_HF:
731 assert((d & 0xffff) == ((d >> 16) & 0xffff));
732 return (d & 0xffff) == 0 || (d & 0xffff) == 0x8000;
733 case BRW_REGISTER_TYPE_F:
734 return f == 0;
735 case BRW_REGISTER_TYPE_DF:
736 return df == 0;
737 case BRW_REGISTER_TYPE_W:
738 case BRW_REGISTER_TYPE_UW:
739 assert((d & 0xffff) == ((d >> 16) & 0xffff));
740 return (d & 0xffff) == 0;
741 case BRW_REGISTER_TYPE_D:
742 case BRW_REGISTER_TYPE_UD:
743 return d == 0;
744 case BRW_REGISTER_TYPE_UQ:
745 case BRW_REGISTER_TYPE_Q:
746 return u64 == 0;
747 default:
748 return false;
749 }
750 }
751
752 bool
753 backend_reg::is_one() const
754 {
755 if (file != IMM)
756 return false;
757
758 assert(type_sz(type) > 1);
759
760 switch (type) {
761 case BRW_REGISTER_TYPE_HF:
762 assert((d & 0xffff) == ((d >> 16) & 0xffff));
763 return (d & 0xffff) == 0x3c00;
764 case BRW_REGISTER_TYPE_F:
765 return f == 1.0f;
766 case BRW_REGISTER_TYPE_DF:
767 return df == 1.0;
768 case BRW_REGISTER_TYPE_W:
769 case BRW_REGISTER_TYPE_UW:
770 assert((d & 0xffff) == ((d >> 16) & 0xffff));
771 return (d & 0xffff) == 1;
772 case BRW_REGISTER_TYPE_D:
773 case BRW_REGISTER_TYPE_UD:
774 return d == 1;
775 case BRW_REGISTER_TYPE_UQ:
776 case BRW_REGISTER_TYPE_Q:
777 return u64 == 1;
778 default:
779 return false;
780 }
781 }
782
783 bool
784 backend_reg::is_negative_one() const
785 {
786 if (file != IMM)
787 return false;
788
789 assert(type_sz(type) > 1);
790
791 switch (type) {
792 case BRW_REGISTER_TYPE_HF:
793 assert((d & 0xffff) == ((d >> 16) & 0xffff));
794 return (d & 0xffff) == 0xbc00;
795 case BRW_REGISTER_TYPE_F:
796 return f == -1.0;
797 case BRW_REGISTER_TYPE_DF:
798 return df == -1.0;
799 case BRW_REGISTER_TYPE_W:
800 assert((d & 0xffff) == ((d >> 16) & 0xffff));
801 return (d & 0xffff) == 0xffff;
802 case BRW_REGISTER_TYPE_D:
803 return d == -1;
804 case BRW_REGISTER_TYPE_Q:
805 return d64 == -1;
806 default:
807 return false;
808 }
809 }
810
811 bool
812 backend_reg::is_null() const
813 {
814 return file == ARF && nr == BRW_ARF_NULL;
815 }
816
817
818 bool
819 backend_reg::is_accumulator() const
820 {
821 return file == ARF && nr == BRW_ARF_ACCUMULATOR;
822 }
823
824 bool
825 backend_instruction::is_commutative() const
826 {
827 switch (opcode) {
828 case BRW_OPCODE_AND:
829 case BRW_OPCODE_OR:
830 case BRW_OPCODE_XOR:
831 case BRW_OPCODE_ADD:
832 case BRW_OPCODE_MUL:
833 case SHADER_OPCODE_MULH:
834 return true;
835 case BRW_OPCODE_SEL:
836 /* MIN and MAX are commutative. */
837 if (conditional_mod == BRW_CONDITIONAL_GE ||
838 conditional_mod == BRW_CONDITIONAL_L) {
839 return true;
840 }
841 /* fallthrough */
842 default:
843 return false;
844 }
845 }
846
847 bool
848 backend_instruction::is_3src(const struct gen_device_info *devinfo) const
849 {
850 return ::is_3src(devinfo, opcode);
851 }
852
853 bool
854 backend_instruction::is_tex() const
855 {
856 return (opcode == SHADER_OPCODE_TEX ||
857 opcode == FS_OPCODE_TXB ||
858 opcode == SHADER_OPCODE_TXD ||
859 opcode == SHADER_OPCODE_TXF ||
860 opcode == SHADER_OPCODE_TXF_LZ ||
861 opcode == SHADER_OPCODE_TXF_CMS ||
862 opcode == SHADER_OPCODE_TXF_CMS_W ||
863 opcode == SHADER_OPCODE_TXF_UMS ||
864 opcode == SHADER_OPCODE_TXF_MCS ||
865 opcode == SHADER_OPCODE_TXL ||
866 opcode == SHADER_OPCODE_TXL_LZ ||
867 opcode == SHADER_OPCODE_TXS ||
868 opcode == SHADER_OPCODE_LOD ||
869 opcode == SHADER_OPCODE_TG4 ||
870 opcode == SHADER_OPCODE_TG4_OFFSET ||
871 opcode == SHADER_OPCODE_SAMPLEINFO);
872 }
873
874 bool
875 backend_instruction::is_math() const
876 {
877 return (opcode == SHADER_OPCODE_RCP ||
878 opcode == SHADER_OPCODE_RSQ ||
879 opcode == SHADER_OPCODE_SQRT ||
880 opcode == SHADER_OPCODE_EXP2 ||
881 opcode == SHADER_OPCODE_LOG2 ||
882 opcode == SHADER_OPCODE_SIN ||
883 opcode == SHADER_OPCODE_COS ||
884 opcode == SHADER_OPCODE_INT_QUOTIENT ||
885 opcode == SHADER_OPCODE_INT_REMAINDER ||
886 opcode == SHADER_OPCODE_POW);
887 }
888
889 bool
890 backend_instruction::is_control_flow() const
891 {
892 switch (opcode) {
893 case BRW_OPCODE_DO:
894 case BRW_OPCODE_WHILE:
895 case BRW_OPCODE_IF:
896 case BRW_OPCODE_ELSE:
897 case BRW_OPCODE_ENDIF:
898 case BRW_OPCODE_BREAK:
899 case BRW_OPCODE_CONTINUE:
900 return true;
901 default:
902 return false;
903 }
904 }
905
906 bool
907 backend_instruction::can_do_source_mods() const
908 {
909 switch (opcode) {
910 case BRW_OPCODE_ADDC:
911 case BRW_OPCODE_BFE:
912 case BRW_OPCODE_BFI1:
913 case BRW_OPCODE_BFI2:
914 case BRW_OPCODE_BFREV:
915 case BRW_OPCODE_CBIT:
916 case BRW_OPCODE_FBH:
917 case BRW_OPCODE_FBL:
918 case BRW_OPCODE_SUBB:
919 case SHADER_OPCODE_BROADCAST:
920 case SHADER_OPCODE_CLUSTER_BROADCAST:
921 case SHADER_OPCODE_MOV_INDIRECT:
922 return false;
923 default:
924 return true;
925 }
926 }
927
928 bool
929 backend_instruction::can_do_saturate() const
930 {
931 switch (opcode) {
932 case BRW_OPCODE_ADD:
933 case BRW_OPCODE_ASR:
934 case BRW_OPCODE_AVG:
935 case BRW_OPCODE_DP2:
936 case BRW_OPCODE_DP3:
937 case BRW_OPCODE_DP4:
938 case BRW_OPCODE_DPH:
939 case BRW_OPCODE_F16TO32:
940 case BRW_OPCODE_F32TO16:
941 case BRW_OPCODE_LINE:
942 case BRW_OPCODE_LRP:
943 case BRW_OPCODE_MAC:
944 case BRW_OPCODE_MAD:
945 case BRW_OPCODE_MATH:
946 case BRW_OPCODE_MOV:
947 case BRW_OPCODE_MUL:
948 case SHADER_OPCODE_MULH:
949 case BRW_OPCODE_PLN:
950 case BRW_OPCODE_RNDD:
951 case BRW_OPCODE_RNDE:
952 case BRW_OPCODE_RNDU:
953 case BRW_OPCODE_RNDZ:
954 case BRW_OPCODE_SEL:
955 case BRW_OPCODE_SHL:
956 case BRW_OPCODE_SHR:
957 case FS_OPCODE_LINTERP:
958 case SHADER_OPCODE_COS:
959 case SHADER_OPCODE_EXP2:
960 case SHADER_OPCODE_LOG2:
961 case SHADER_OPCODE_POW:
962 case SHADER_OPCODE_RCP:
963 case SHADER_OPCODE_RSQ:
964 case SHADER_OPCODE_SIN:
965 case SHADER_OPCODE_SQRT:
966 return true;
967 default:
968 return false;
969 }
970 }
971
972 bool
973 backend_instruction::can_do_cmod() const
974 {
975 switch (opcode) {
976 case BRW_OPCODE_ADD:
977 case BRW_OPCODE_ADDC:
978 case BRW_OPCODE_AND:
979 case BRW_OPCODE_ASR:
980 case BRW_OPCODE_AVG:
981 case BRW_OPCODE_CMP:
982 case BRW_OPCODE_CMPN:
983 case BRW_OPCODE_DP2:
984 case BRW_OPCODE_DP3:
985 case BRW_OPCODE_DP4:
986 case BRW_OPCODE_DPH:
987 case BRW_OPCODE_F16TO32:
988 case BRW_OPCODE_F32TO16:
989 case BRW_OPCODE_FRC:
990 case BRW_OPCODE_LINE:
991 case BRW_OPCODE_LRP:
992 case BRW_OPCODE_LZD:
993 case BRW_OPCODE_MAC:
994 case BRW_OPCODE_MACH:
995 case BRW_OPCODE_MAD:
996 case BRW_OPCODE_MOV:
997 case BRW_OPCODE_MUL:
998 case BRW_OPCODE_NOT:
999 case BRW_OPCODE_OR:
1000 case BRW_OPCODE_PLN:
1001 case BRW_OPCODE_RNDD:
1002 case BRW_OPCODE_RNDE:
1003 case BRW_OPCODE_RNDU:
1004 case BRW_OPCODE_RNDZ:
1005 case BRW_OPCODE_SAD2:
1006 case BRW_OPCODE_SADA2:
1007 case BRW_OPCODE_SHL:
1008 case BRW_OPCODE_SHR:
1009 case BRW_OPCODE_SUBB:
1010 case BRW_OPCODE_XOR:
1011 case FS_OPCODE_LINTERP:
1012 return true;
1013 default:
1014 return false;
1015 }
1016 }
1017
1018 bool
1019 backend_instruction::reads_accumulator_implicitly() const
1020 {
1021 switch (opcode) {
1022 case BRW_OPCODE_MAC:
1023 case BRW_OPCODE_MACH:
1024 case BRW_OPCODE_SADA2:
1025 return true;
1026 default:
1027 return false;
1028 }
1029 }
1030
1031 bool
1032 backend_instruction::writes_accumulator_implicitly(const struct gen_device_info *devinfo) const
1033 {
1034 return writes_accumulator ||
1035 (devinfo->gen < 6 &&
1036 ((opcode >= BRW_OPCODE_ADD && opcode < BRW_OPCODE_NOP) ||
1037 (opcode >= FS_OPCODE_DDX_COARSE && opcode <= FS_OPCODE_LINTERP))) ||
1038 (opcode == FS_OPCODE_LINTERP &&
1039 (!devinfo->has_pln || devinfo->gen <= 6));
1040 }
1041
1042 bool
1043 backend_instruction::has_side_effects() const
1044 {
1045 switch (opcode) {
1046 case SHADER_OPCODE_SEND:
1047 return send_has_side_effects;
1048
1049 case BRW_OPCODE_SYNC:
1050 case VEC4_OPCODE_UNTYPED_ATOMIC:
1051 case SHADER_OPCODE_UNTYPED_ATOMIC_LOGICAL:
1052 case SHADER_OPCODE_UNTYPED_ATOMIC_FLOAT_LOGICAL:
1053 case SHADER_OPCODE_GEN4_SCRATCH_WRITE:
1054 case VEC4_OPCODE_UNTYPED_SURFACE_WRITE:
1055 case SHADER_OPCODE_UNTYPED_SURFACE_WRITE_LOGICAL:
1056 case SHADER_OPCODE_A64_UNTYPED_WRITE_LOGICAL:
1057 case SHADER_OPCODE_A64_BYTE_SCATTERED_WRITE_LOGICAL:
1058 case SHADER_OPCODE_A64_UNTYPED_ATOMIC_LOGICAL:
1059 case SHADER_OPCODE_A64_UNTYPED_ATOMIC_INT64_LOGICAL:
1060 case SHADER_OPCODE_A64_UNTYPED_ATOMIC_FLOAT_LOGICAL:
1061 case SHADER_OPCODE_BYTE_SCATTERED_WRITE_LOGICAL:
1062 case SHADER_OPCODE_DWORD_SCATTERED_WRITE_LOGICAL:
1063 case SHADER_OPCODE_TYPED_ATOMIC_LOGICAL:
1064 case SHADER_OPCODE_TYPED_SURFACE_WRITE_LOGICAL:
1065 case SHADER_OPCODE_MEMORY_FENCE:
1066 case SHADER_OPCODE_INTERLOCK:
1067 case SHADER_OPCODE_URB_WRITE_SIMD8:
1068 case SHADER_OPCODE_URB_WRITE_SIMD8_PER_SLOT:
1069 case SHADER_OPCODE_URB_WRITE_SIMD8_MASKED:
1070 case SHADER_OPCODE_URB_WRITE_SIMD8_MASKED_PER_SLOT:
1071 case FS_OPCODE_FB_WRITE:
1072 case FS_OPCODE_FB_WRITE_LOGICAL:
1073 case FS_OPCODE_REP_FB_WRITE:
1074 case SHADER_OPCODE_BARRIER:
1075 case TCS_OPCODE_URB_WRITE:
1076 case TCS_OPCODE_RELEASE_INPUT:
1077 case SHADER_OPCODE_RND_MODE:
1078 case SHADER_OPCODE_FLOAT_CONTROL_MODE:
1079 return true;
1080 default:
1081 return eot;
1082 }
1083 }
1084
1085 bool
1086 backend_instruction::is_volatile() const
1087 {
1088 switch (opcode) {
1089 case SHADER_OPCODE_SEND:
1090 return send_is_volatile;
1091
1092 case VEC4_OPCODE_UNTYPED_SURFACE_READ:
1093 case SHADER_OPCODE_UNTYPED_SURFACE_READ_LOGICAL:
1094 case SHADER_OPCODE_TYPED_SURFACE_READ_LOGICAL:
1095 case SHADER_OPCODE_BYTE_SCATTERED_READ_LOGICAL:
1096 case SHADER_OPCODE_DWORD_SCATTERED_READ_LOGICAL:
1097 case SHADER_OPCODE_A64_UNTYPED_READ_LOGICAL:
1098 case SHADER_OPCODE_A64_BYTE_SCATTERED_READ_LOGICAL:
1099 case SHADER_OPCODE_URB_READ_SIMD8:
1100 case SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT:
1101 case VEC4_OPCODE_URB_READ:
1102 return true;
1103 default:
1104 return false;
1105 }
1106 }
1107
1108 #ifndef NDEBUG
1109 static bool
1110 inst_is_in_block(const bblock_t *block, const backend_instruction *inst)
1111 {
1112 bool found = false;
1113 foreach_inst_in_block (backend_instruction, i, block) {
1114 if (inst == i) {
1115 found = true;
1116 }
1117 }
1118 return found;
1119 }
1120 #endif
1121
1122 static void
1123 adjust_later_block_ips(bblock_t *start_block, int ip_adjustment)
1124 {
1125 for (bblock_t *block_iter = start_block->next();
1126 block_iter;
1127 block_iter = block_iter->next()) {
1128 block_iter->start_ip += ip_adjustment;
1129 block_iter->end_ip += ip_adjustment;
1130 }
1131 }
1132
1133 void
1134 backend_instruction::insert_after(bblock_t *block, backend_instruction *inst)
1135 {
1136 assert(this != inst);
1137
1138 if (!this->is_head_sentinel())
1139 assert(inst_is_in_block(block, this) || !"Instruction not in block");
1140
1141 block->end_ip++;
1142
1143 adjust_later_block_ips(block, 1);
1144
1145 exec_node::insert_after(inst);
1146 }
1147
1148 void
1149 backend_instruction::insert_before(bblock_t *block, backend_instruction *inst)
1150 {
1151 assert(this != inst);
1152
1153 if (!this->is_tail_sentinel())
1154 assert(inst_is_in_block(block, this) || !"Instruction not in block");
1155
1156 block->end_ip++;
1157
1158 adjust_later_block_ips(block, 1);
1159
1160 exec_node::insert_before(inst);
1161 }
1162
1163 void
1164 backend_instruction::insert_before(bblock_t *block, exec_list *list)
1165 {
1166 assert(inst_is_in_block(block, this) || !"Instruction not in block");
1167
1168 unsigned num_inst = list->length();
1169
1170 block->end_ip += num_inst;
1171
1172 adjust_later_block_ips(block, num_inst);
1173
1174 exec_node::insert_before(list);
1175 }
1176
1177 void
1178 backend_instruction::remove(bblock_t *block)
1179 {
1180 assert(inst_is_in_block(block, this) || !"Instruction not in block");
1181
1182 adjust_later_block_ips(block, -1);
1183
1184 if (block->start_ip == block->end_ip) {
1185 block->cfg->remove_block(block);
1186 } else {
1187 block->end_ip--;
1188 }
1189
1190 exec_node::remove();
1191 }
1192
1193 void
1194 backend_shader::dump_instructions()
1195 {
1196 dump_instructions(NULL);
1197 }
1198
1199 void
1200 backend_shader::dump_instructions(const char *name)
1201 {
1202 FILE *file = stderr;
1203 if (name && geteuid() != 0) {
1204 file = fopen(name, "w");
1205 if (!file)
1206 file = stderr;
1207 }
1208
1209 if (cfg) {
1210 int ip = 0;
1211 foreach_block_and_inst(block, backend_instruction, inst, cfg) {
1212 if (!unlikely(INTEL_DEBUG & DEBUG_OPTIMIZER))
1213 fprintf(file, "%4d: ", ip++);
1214 dump_instruction(inst, file);
1215 }
1216 } else {
1217 int ip = 0;
1218 foreach_in_list(backend_instruction, inst, &instructions) {
1219 if (!unlikely(INTEL_DEBUG & DEBUG_OPTIMIZER))
1220 fprintf(file, "%4d: ", ip++);
1221 dump_instruction(inst, file);
1222 }
1223 }
1224
1225 if (file != stderr) {
1226 fclose(file);
1227 }
1228 }
1229
1230 void
1231 backend_shader::calculate_cfg()
1232 {
1233 if (this->cfg)
1234 return;
1235 cfg = new(mem_ctx) cfg_t(&this->instructions);
1236 }
1237
1238 extern "C" const unsigned *
1239 brw_compile_tes(const struct brw_compiler *compiler,
1240 void *log_data,
1241 void *mem_ctx,
1242 const struct brw_tes_prog_key *key,
1243 const struct brw_vue_map *input_vue_map,
1244 struct brw_tes_prog_data *prog_data,
1245 nir_shader *nir,
1246 int shader_time_index,
1247 struct brw_compile_stats *stats,
1248 char **error_str)
1249 {
1250 const struct gen_device_info *devinfo = compiler->devinfo;
1251 const bool is_scalar = compiler->scalar_stage[MESA_SHADER_TESS_EVAL];
1252 const unsigned *assembly;
1253
1254 nir->info.inputs_read = key->inputs_read;
1255 nir->info.patch_inputs_read = key->patch_inputs_read;
1256
1257 brw_nir_apply_key(nir, compiler, &key->base, 8, is_scalar);
1258 brw_nir_lower_tes_inputs(nir, input_vue_map);
1259 brw_nir_lower_vue_outputs(nir);
1260 brw_postprocess_nir(nir, compiler, is_scalar);
1261
1262 brw_compute_vue_map(devinfo, &prog_data->base.vue_map,
1263 nir->info.outputs_written,
1264 nir->info.separate_shader);
1265
1266 unsigned output_size_bytes = prog_data->base.vue_map.num_slots * 4 * 4;
1267
1268 assert(output_size_bytes >= 1);
1269 if (output_size_bytes > GEN7_MAX_DS_URB_ENTRY_SIZE_BYTES) {
1270 if (error_str)
1271 *error_str = ralloc_strdup(mem_ctx, "DS outputs exceed maximum size");
1272 return NULL;
1273 }
1274
1275 prog_data->base.clip_distance_mask =
1276 ((1 << nir->info.clip_distance_array_size) - 1);
1277 prog_data->base.cull_distance_mask =
1278 ((1 << nir->info.cull_distance_array_size) - 1) <<
1279 nir->info.clip_distance_array_size;
1280
1281 /* URB entry sizes are stored as a multiple of 64 bytes. */
1282 prog_data->base.urb_entry_size = ALIGN(output_size_bytes, 64) / 64;
1283
1284 /* On Cannonlake software shall not program an allocation size that
1285 * specifies a size that is a multiple of 3 64B (512-bit) cachelines.
1286 */
1287 if (devinfo->gen == 10 &&
1288 prog_data->base.urb_entry_size % 3 == 0)
1289 prog_data->base.urb_entry_size++;
1290
1291 prog_data->base.urb_read_length = 0;
1292
1293 STATIC_ASSERT(BRW_TESS_PARTITIONING_INTEGER == TESS_SPACING_EQUAL - 1);
1294 STATIC_ASSERT(BRW_TESS_PARTITIONING_ODD_FRACTIONAL ==
1295 TESS_SPACING_FRACTIONAL_ODD - 1);
1296 STATIC_ASSERT(BRW_TESS_PARTITIONING_EVEN_FRACTIONAL ==
1297 TESS_SPACING_FRACTIONAL_EVEN - 1);
1298
1299 prog_data->partitioning =
1300 (enum brw_tess_partitioning) (nir->info.tess.spacing - 1);
1301
1302 switch (nir->info.tess.primitive_mode) {
1303 case GL_QUADS:
1304 prog_data->domain = BRW_TESS_DOMAIN_QUAD;
1305 break;
1306 case GL_TRIANGLES:
1307 prog_data->domain = BRW_TESS_DOMAIN_TRI;
1308 break;
1309 case GL_ISOLINES:
1310 prog_data->domain = BRW_TESS_DOMAIN_ISOLINE;
1311 break;
1312 default:
1313 unreachable("invalid domain shader primitive mode");
1314 }
1315
1316 if (nir->info.tess.point_mode) {
1317 prog_data->output_topology = BRW_TESS_OUTPUT_TOPOLOGY_POINT;
1318 } else if (nir->info.tess.primitive_mode == GL_ISOLINES) {
1319 prog_data->output_topology = BRW_TESS_OUTPUT_TOPOLOGY_LINE;
1320 } else {
1321 /* Hardware winding order is backwards from OpenGL */
1322 prog_data->output_topology =
1323 nir->info.tess.ccw ? BRW_TESS_OUTPUT_TOPOLOGY_TRI_CW
1324 : BRW_TESS_OUTPUT_TOPOLOGY_TRI_CCW;
1325 }
1326
1327 if (unlikely(INTEL_DEBUG & DEBUG_TES)) {
1328 fprintf(stderr, "TES Input ");
1329 brw_print_vue_map(stderr, input_vue_map);
1330 fprintf(stderr, "TES Output ");
1331 brw_print_vue_map(stderr, &prog_data->base.vue_map);
1332 }
1333
1334 if (is_scalar) {
1335 fs_visitor v(compiler, log_data, mem_ctx, &key->base,
1336 &prog_data->base.base, nir, 8,
1337 shader_time_index, input_vue_map);
1338 if (!v.run_tes()) {
1339 if (error_str)
1340 *error_str = ralloc_strdup(mem_ctx, v.fail_msg);
1341 return NULL;
1342 }
1343
1344 prog_data->base.base.dispatch_grf_start_reg = v.payload.num_regs;
1345 prog_data->base.dispatch_mode = DISPATCH_MODE_SIMD8;
1346
1347 fs_generator g(compiler, log_data, mem_ctx,
1348 &prog_data->base.base, v.shader_stats, false,
1349 MESA_SHADER_TESS_EVAL);
1350 if (unlikely(INTEL_DEBUG & DEBUG_TES)) {
1351 g.enable_debug(ralloc_asprintf(mem_ctx,
1352 "%s tessellation evaluation shader %s",
1353 nir->info.label ? nir->info.label
1354 : "unnamed",
1355 nir->info.name));
1356 }
1357
1358 g.generate_code(v.cfg, 8, stats);
1359
1360 assembly = g.get_assembly();
1361 } else {
1362 brw::vec4_tes_visitor v(compiler, log_data, key, prog_data,
1363 nir, mem_ctx, shader_time_index);
1364 if (!v.run()) {
1365 if (error_str)
1366 *error_str = ralloc_strdup(mem_ctx, v.fail_msg);
1367 return NULL;
1368 }
1369
1370 if (unlikely(INTEL_DEBUG & DEBUG_TES))
1371 v.dump_instructions();
1372
1373 assembly = brw_vec4_generate_assembly(compiler, log_data, mem_ctx, nir,
1374 &prog_data->base, v.cfg, stats);
1375 }
1376
1377 return assembly;
1378 }