src/intel/compiler/brw_shader.cpp

   1 /*
   2  * Copyright © 2010 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  */
  23
  24 #include "brw_cfg.h"
  25 #include "brw_eu.h"
  26 #include "brw_fs.h"
  27 #include "brw_nir.h"
  28 #include "brw_vec4_tes.h"
  29 #include "dev/gen_debug.h"
  30 #include "main/uniforms.h"
  31 #include "util/macros.h"
  32
  33 enum brw_reg_type
  34 brw_type_for_base_type(const struct glsl_type *type)
  35 {
  36    switch (type->base_type) {
  37    case GLSL_TYPE_FLOAT16:
  38       return BRW_REGISTER_TYPE_HF;
  39    case GLSL_TYPE_FLOAT:
  40       return BRW_REGISTER_TYPE_F;
  41    case GLSL_TYPE_INT:
  42    case GLSL_TYPE_BOOL:
  43    case GLSL_TYPE_SUBROUTINE:
  44       return BRW_REGISTER_TYPE_D;
  45    case GLSL_TYPE_INT16:
  46       return BRW_REGISTER_TYPE_W;
  47    case GLSL_TYPE_INT8:
  48       return BRW_REGISTER_TYPE_B;
  49    case GLSL_TYPE_UINT:
  50       return BRW_REGISTER_TYPE_UD;
  51    case GLSL_TYPE_UINT16:
  52       return BRW_REGISTER_TYPE_UW;
  53    case GLSL_TYPE_UINT8:
  54       return BRW_REGISTER_TYPE_UB;
  55    case GLSL_TYPE_ARRAY:
  56       return brw_type_for_base_type(type->fields.array);
  57    case GLSL_TYPE_STRUCT:
  58    case GLSL_TYPE_INTERFACE:
  59    case GLSL_TYPE_SAMPLER:
  60    case GLSL_TYPE_ATOMIC_UINT:
  61       /* These should be overridden with the type of the member when
  62        * dereferenced into.  BRW_REGISTER_TYPE_UD seems like a likely
  63        * way to trip up if we don't.
  64        */
  65       return BRW_REGISTER_TYPE_UD;
  66    case GLSL_TYPE_IMAGE:
  67       return BRW_REGISTER_TYPE_UD;
  68    case GLSL_TYPE_DOUBLE:
  69       return BRW_REGISTER_TYPE_DF;
  70    case GLSL_TYPE_UINT64:
  71       return BRW_REGISTER_TYPE_UQ;
  72    case GLSL_TYPE_INT64:
  73       return BRW_REGISTER_TYPE_Q;
  74    case GLSL_TYPE_VOID:
  75    case GLSL_TYPE_ERROR:
  76    case GLSL_TYPE_FUNCTION:
  77       unreachable("not reached");
  78    }
  79
  80    return BRW_REGISTER_TYPE_F;
  81 }
  82
  83 enum brw_conditional_mod
  84 brw_conditional_for_comparison(unsigned int op)
  85 {
  86    switch (op) {
  87    case ir_binop_less:
  88       return BRW_CONDITIONAL_L;
  89    case ir_binop_gequal:
  90       return BRW_CONDITIONAL_GE;
  91    case ir_binop_equal:
  92    case ir_binop_all_equal: /* same as equal for scalars */
  93       return BRW_CONDITIONAL_Z;
  94    case ir_binop_nequal:
  95    case ir_binop_any_nequal: /* same as nequal for scalars */
  96       return BRW_CONDITIONAL_NZ;
  97    default:
  98       unreachable("not reached: bad operation for comparison");
  99    }
 100 }
 101
 102 uint32_t
 103 brw_math_function(enum opcode op)
 104 {
 105    switch (op) {
 106    case SHADER_OPCODE_RCP:
 107       return BRW_MATH_FUNCTION_INV;
 108    case SHADER_OPCODE_RSQ:
 109       return BRW_MATH_FUNCTION_RSQ;
 110    case SHADER_OPCODE_SQRT:
 111       return BRW_MATH_FUNCTION_SQRT;
 112    case SHADER_OPCODE_EXP2:
 113       return BRW_MATH_FUNCTION_EXP;
 114    case SHADER_OPCODE_LOG2:
 115       return BRW_MATH_FUNCTION_LOG;
 116    case SHADER_OPCODE_POW:
 117       return BRW_MATH_FUNCTION_POW;
 118    case SHADER_OPCODE_SIN:
 119       return BRW_MATH_FUNCTION_SIN;
 120    case SHADER_OPCODE_COS:
 121       return BRW_MATH_FUNCTION_COS;
 122    case SHADER_OPCODE_INT_QUOTIENT:
 123       return BRW_MATH_FUNCTION_INT_DIV_QUOTIENT;
 124    case SHADER_OPCODE_INT_REMAINDER:
 125       return BRW_MATH_FUNCTION_INT_DIV_REMAINDER;
 126    default:
 127       unreachable("not reached: unknown math function");
 128    }
 129 }
 130
 131 bool
 132 brw_texture_offset(const nir_tex_instr *tex, unsigned src,
 133                    uint32_t *offset_bits_out)
 134 {
 135    if (!nir_src_is_const(tex->src[src].src))
 136       return false;
 137
 138    const unsigned num_components = nir_tex_instr_src_size(tex, src);
 139
 140    /* Combine all three offsets into a single unsigned dword:
 141     *
 142     *    bits 11:8 - U Offset (X component)
 143     *    bits  7:4 - V Offset (Y component)
 144     *    bits  3:0 - R Offset (Z component)
 145     */
 146    uint32_t offset_bits = 0;
 147    for (unsigned i = 0; i < num_components; i++) {
 148       int offset = nir_src_comp_as_int(tex->src[src].src, i);
 149
 150       /* offset out of bounds; caller will handle it. */
 151       if (offset > 7 || offset < -8)
 152          return false;
 153
 154       const unsigned shift = 4 * (2 - i);
 155       offset_bits |= (offset << shift) & (0xF << shift);
 156    }
 157
 158    *offset_bits_out = offset_bits;
 159
 160    return true;
 161 }
 162
 163 const char *
 164 brw_instruction_name(const struct gen_device_info *devinfo, enum opcode op)
 165 {
 166    switch (op) {
 167    case 0 ... NUM_BRW_OPCODES - 1:
 168       /* The DO instruction doesn't exist on Gen6+, but we use it to mark the
 169        * start of a loop in the IR.
 170        */
 171       if (devinfo->gen >= 6 && op == BRW_OPCODE_DO)
 172          return "do";
 173
 174       /* The following conversion opcodes doesn't exist on Gen8+, but we use
 175        * then to mark that we want to do the conversion.
 176        */
 177       if (devinfo->gen > 7 && op == BRW_OPCODE_F32TO16)
 178          return "f32to16";
 179
 180       if (devinfo->gen > 7 && op == BRW_OPCODE_F16TO32)
 181          return "f16to32";
 182
 183       assert(brw_opcode_desc(devinfo, op)->name);
 184       return brw_opcode_desc(devinfo, op)->name;
 185    case FS_OPCODE_FB_WRITE:
 186       return "fb_write";
 187    case FS_OPCODE_FB_WRITE_LOGICAL:
 188       return "fb_write_logical";
 189    case FS_OPCODE_REP_FB_WRITE:
 190       return "rep_fb_write";
 191    case FS_OPCODE_FB_READ:
 192       return "fb_read";
 193    case FS_OPCODE_FB_READ_LOGICAL:
 194       return "fb_read_logical";
 195
 196    case SHADER_OPCODE_RCP:
 197       return "rcp";
 198    case SHADER_OPCODE_RSQ:
 199       return "rsq";
 200    case SHADER_OPCODE_SQRT:
 201       return "sqrt";
 202    case SHADER_OPCODE_EXP2:
 203       return "exp2";
 204    case SHADER_OPCODE_LOG2:
 205       return "log2";
 206    case SHADER_OPCODE_POW:
 207       return "pow";
 208    case SHADER_OPCODE_INT_QUOTIENT:
 209       return "int_quot";
 210    case SHADER_OPCODE_INT_REMAINDER:
 211       return "int_rem";
 212    case SHADER_OPCODE_SIN:
 213       return "sin";
 214    case SHADER_OPCODE_COS:
 215       return "cos";
 216
 217    case SHADER_OPCODE_SEND:
 218       return "send";
 219
 220    case SHADER_OPCODE_UNDEF:
 221       return "undef";
 222
 223    case SHADER_OPCODE_TEX:
 224       return "tex";
 225    case SHADER_OPCODE_TEX_LOGICAL:
 226       return "tex_logical";
 227    case SHADER_OPCODE_TXD:
 228       return "txd";
 229    case SHADER_OPCODE_TXD_LOGICAL:
 230       return "txd_logical";
 231    case SHADER_OPCODE_TXF:
 232       return "txf";
 233    case SHADER_OPCODE_TXF_LOGICAL:
 234       return "txf_logical";
 235    case SHADER_OPCODE_TXF_LZ:
 236       return "txf_lz";
 237    case SHADER_OPCODE_TXL:
 238       return "txl";
 239    case SHADER_OPCODE_TXL_LOGICAL:
 240       return "txl_logical";
 241    case SHADER_OPCODE_TXL_LZ:
 242       return "txl_lz";
 243    case SHADER_OPCODE_TXS:
 244       return "txs";
 245    case SHADER_OPCODE_TXS_LOGICAL:
 246       return "txs_logical";
 247    case FS_OPCODE_TXB:
 248       return "txb";
 249    case FS_OPCODE_TXB_LOGICAL:
 250       return "txb_logical";
 251    case SHADER_OPCODE_TXF_CMS:
 252       return "txf_cms";
 253    case SHADER_OPCODE_TXF_CMS_LOGICAL:
 254       return "txf_cms_logical";
 255    case SHADER_OPCODE_TXF_CMS_W:
 256       return "txf_cms_w";
 257    case SHADER_OPCODE_TXF_CMS_W_LOGICAL:
 258       return "txf_cms_w_logical";
 259    case SHADER_OPCODE_TXF_UMS:
 260       return "txf_ums";
 261    case SHADER_OPCODE_TXF_UMS_LOGICAL:
 262       return "txf_ums_logical";
 263    case SHADER_OPCODE_TXF_MCS:
 264       return "txf_mcs";
 265    case SHADER_OPCODE_TXF_MCS_LOGICAL:
 266       return "txf_mcs_logical";
 267    case SHADER_OPCODE_LOD:
 268       return "lod";
 269    case SHADER_OPCODE_LOD_LOGICAL:
 270       return "lod_logical";
 271    case SHADER_OPCODE_TG4:
 272       return "tg4";
 273    case SHADER_OPCODE_TG4_LOGICAL:
 274       return "tg4_logical";
 275    case SHADER_OPCODE_TG4_OFFSET:
 276       return "tg4_offset";
 277    case SHADER_OPCODE_TG4_OFFSET_LOGICAL:
 278       return "tg4_offset_logical";
 279    case SHADER_OPCODE_SAMPLEINFO:
 280       return "sampleinfo";
 281    case SHADER_OPCODE_SAMPLEINFO_LOGICAL:
 282       return "sampleinfo_logical";
 283
 284    case SHADER_OPCODE_IMAGE_SIZE_LOGICAL:
 285       return "image_size_logical";
 286
 287    case SHADER_OPCODE_SHADER_TIME_ADD:
 288       return "shader_time_add";
 289
 290    case VEC4_OPCODE_UNTYPED_ATOMIC:
 291       return "untyped_atomic";
 292    case SHADER_OPCODE_UNTYPED_ATOMIC_LOGICAL:
 293       return "untyped_atomic_logical";
 294    case SHADER_OPCODE_UNTYPED_ATOMIC_FLOAT_LOGICAL:
 295       return "untyped_atomic_float_logical";
 296    case VEC4_OPCODE_UNTYPED_SURFACE_READ:
 297       return "untyped_surface_read";
 298    case SHADER_OPCODE_UNTYPED_SURFACE_READ_LOGICAL:
 299       return "untyped_surface_read_logical";
 300    case VEC4_OPCODE_UNTYPED_SURFACE_WRITE:
 301       return "untyped_surface_write";
 302    case SHADER_OPCODE_UNTYPED_SURFACE_WRITE_LOGICAL:
 303       return "untyped_surface_write_logical";
 304    case SHADER_OPCODE_A64_UNTYPED_READ_LOGICAL:
 305       return "a64_untyped_read_logical";
 306    case SHADER_OPCODE_A64_UNTYPED_WRITE_LOGICAL:
 307       return "a64_untyped_write_logical";
 308    case SHADER_OPCODE_A64_BYTE_SCATTERED_READ_LOGICAL:
 309       return "a64_byte_scattered_read_logical";
 310    case SHADER_OPCODE_A64_BYTE_SCATTERED_WRITE_LOGICAL:
 311       return "a64_byte_scattered_write_logical";
 312    case SHADER_OPCODE_A64_UNTYPED_ATOMIC_LOGICAL:
 313       return "a64_untyped_atomic_logical";
 314    case SHADER_OPCODE_A64_UNTYPED_ATOMIC_INT64_LOGICAL:
 315       return "a64_untyped_atomic_int64_logical";
 316    case SHADER_OPCODE_A64_UNTYPED_ATOMIC_FLOAT_LOGICAL:
 317       return "a64_untyped_atomic_float_logical";
 318    case SHADER_OPCODE_TYPED_ATOMIC_LOGICAL:
 319       return "typed_atomic_logical";
 320    case SHADER_OPCODE_TYPED_SURFACE_READ_LOGICAL:
 321       return "typed_surface_read_logical";
 322    case SHADER_OPCODE_TYPED_SURFACE_WRITE_LOGICAL:
 323       return "typed_surface_write_logical";
 324    case SHADER_OPCODE_MEMORY_FENCE:
 325       return "memory_fence";
 326    case FS_OPCODE_SCHEDULING_FENCE:
 327       return "scheduling_fence";
 328    case SHADER_OPCODE_INTERLOCK:
 329       /* For an interlock we actually issue a memory fence via sendc. */
 330       return "interlock";
 331
 332    case SHADER_OPCODE_BYTE_SCATTERED_READ_LOGICAL:
 333       return "byte_scattered_read_logical";
 334    case SHADER_OPCODE_BYTE_SCATTERED_WRITE_LOGICAL:
 335       return "byte_scattered_write_logical";
 336    case SHADER_OPCODE_DWORD_SCATTERED_READ_LOGICAL:
 337       return "dword_scattered_read_logical";
 338    case SHADER_OPCODE_DWORD_SCATTERED_WRITE_LOGICAL:
 339       return "dword_scattered_write_logical";
 340
 341    case SHADER_OPCODE_LOAD_PAYLOAD:
 342       return "load_payload";
 343    case FS_OPCODE_PACK:
 344       return "pack";
 345
 346    case SHADER_OPCODE_GEN4_SCRATCH_READ:
 347       return "gen4_scratch_read";
 348    case SHADER_OPCODE_GEN4_SCRATCH_WRITE:
 349       return "gen4_scratch_write";
 350    case SHADER_OPCODE_GEN7_SCRATCH_READ:
 351       return "gen7_scratch_read";
 352    case SHADER_OPCODE_URB_WRITE_SIMD8:
 353       return "gen8_urb_write_simd8";
 354    case SHADER_OPCODE_URB_WRITE_SIMD8_PER_SLOT:
 355       return "gen8_urb_write_simd8_per_slot";
 356    case SHADER_OPCODE_URB_WRITE_SIMD8_MASKED:
 357       return "gen8_urb_write_simd8_masked";
 358    case SHADER_OPCODE_URB_WRITE_SIMD8_MASKED_PER_SLOT:
 359       return "gen8_urb_write_simd8_masked_per_slot";
 360    case SHADER_OPCODE_URB_READ_SIMD8:
 361       return "urb_read_simd8";
 362    case SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT:
 363       return "urb_read_simd8_per_slot";
 364
 365    case SHADER_OPCODE_FIND_LIVE_CHANNEL:
 366       return "find_live_channel";
 367    case SHADER_OPCODE_BROADCAST:
 368       return "broadcast";
 369    case SHADER_OPCODE_SHUFFLE:
 370       return "shuffle";
 371    case SHADER_OPCODE_SEL_EXEC:
 372       return "sel_exec";
 373    case SHADER_OPCODE_QUAD_SWIZZLE:
 374       return "quad_swizzle";
 375    case SHADER_OPCODE_CLUSTER_BROADCAST:
 376       return "cluster_broadcast";
 377
 378    case SHADER_OPCODE_GET_BUFFER_SIZE:
 379       return "get_buffer_size";
 380
 381    case VEC4_OPCODE_MOV_BYTES:
 382       return "mov_bytes";
 383    case VEC4_OPCODE_PACK_BYTES:
 384       return "pack_bytes";
 385    case VEC4_OPCODE_UNPACK_UNIFORM:
 386       return "unpack_uniform";
 387    case VEC4_OPCODE_DOUBLE_TO_F32:
 388       return "double_to_f32";
 389    case VEC4_OPCODE_DOUBLE_TO_D32:
 390       return "double_to_d32";
 391    case VEC4_OPCODE_DOUBLE_TO_U32:
 392       return "double_to_u32";
 393    case VEC4_OPCODE_TO_DOUBLE:
 394       return "single_to_double";
 395    case VEC4_OPCODE_PICK_LOW_32BIT:
 396       return "pick_low_32bit";
 397    case VEC4_OPCODE_PICK_HIGH_32BIT:
 398       return "pick_high_32bit";
 399    case VEC4_OPCODE_SET_LOW_32BIT:
 400       return "set_low_32bit";
 401    case VEC4_OPCODE_SET_HIGH_32BIT:
 402       return "set_high_32bit";
 403
 404    case FS_OPCODE_DDX_COARSE:
 405       return "ddx_coarse";
 406    case FS_OPCODE_DDX_FINE:
 407       return "ddx_fine";
 408    case FS_OPCODE_DDY_COARSE:
 409       return "ddy_coarse";
 410    case FS_OPCODE_DDY_FINE:
 411       return "ddy_fine";
 412
 413    case FS_OPCODE_LINTERP:
 414       return "linterp";
 415
 416    case FS_OPCODE_PIXEL_X:
 417       return "pixel_x";
 418    case FS_OPCODE_PIXEL_Y:
 419       return "pixel_y";
 420
 421    case FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD:
 422       return "uniform_pull_const";
 423    case FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD_GEN7:
 424       return "uniform_pull_const_gen7";
 425    case FS_OPCODE_VARYING_PULL_CONSTANT_LOAD_GEN4:
 426       return "varying_pull_const_gen4";
 427    case FS_OPCODE_VARYING_PULL_CONSTANT_LOAD_LOGICAL:
 428       return "varying_pull_const_logical";
 429
 430    case FS_OPCODE_DISCARD_JUMP:
 431       return "discard_jump";
 432
 433    case FS_OPCODE_SET_SAMPLE_ID:
 434       return "set_sample_id";
 435
 436    case FS_OPCODE_PACK_HALF_2x16_SPLIT:
 437       return "pack_half_2x16_split";
 438
 439    case FS_OPCODE_PLACEHOLDER_HALT:
 440       return "placeholder_halt";
 441
 442    case FS_OPCODE_INTERPOLATE_AT_SAMPLE:
 443       return "interp_sample";
 444    case FS_OPCODE_INTERPOLATE_AT_SHARED_OFFSET:
 445       return "interp_shared_offset";
 446    case FS_OPCODE_INTERPOLATE_AT_PER_SLOT_OFFSET:
 447       return "interp_per_slot_offset";
 448
 449    case VS_OPCODE_URB_WRITE:
 450       return "vs_urb_write";
 451    case VS_OPCODE_PULL_CONSTANT_LOAD:
 452       return "pull_constant_load";
 453    case VS_OPCODE_PULL_CONSTANT_LOAD_GEN7:
 454       return "pull_constant_load_gen7";
 455
 456    case VS_OPCODE_SET_SIMD4X2_HEADER_GEN9:
 457       return "set_simd4x2_header_gen9";
 458
 459    case VS_OPCODE_UNPACK_FLAGS_SIMD4X2:
 460       return "unpack_flags_simd4x2";
 461
 462    case GS_OPCODE_URB_WRITE:
 463       return "gs_urb_write";
 464    case GS_OPCODE_URB_WRITE_ALLOCATE:
 465       return "gs_urb_write_allocate";
 466    case GS_OPCODE_THREAD_END:
 467       return "gs_thread_end";
 468    case GS_OPCODE_SET_WRITE_OFFSET:
 469       return "set_write_offset";
 470    case GS_OPCODE_SET_VERTEX_COUNT:
 471       return "set_vertex_count";
 472    case GS_OPCODE_SET_DWORD_2:
 473       return "set_dword_2";
 474    case GS_OPCODE_PREPARE_CHANNEL_MASKS:
 475       return "prepare_channel_masks";
 476    case GS_OPCODE_SET_CHANNEL_MASKS:
 477       return "set_channel_masks";
 478    case GS_OPCODE_GET_INSTANCE_ID:
 479       return "get_instance_id";
 480    case GS_OPCODE_FF_SYNC:
 481       return "ff_sync";
 482    case GS_OPCODE_SET_PRIMITIVE_ID:
 483       return "set_primitive_id";
 484    case GS_OPCODE_SVB_WRITE:
 485       return "gs_svb_write";
 486    case GS_OPCODE_SVB_SET_DST_INDEX:
 487       return "gs_svb_set_dst_index";
 488    case GS_OPCODE_FF_SYNC_SET_PRIMITIVES:
 489       return "gs_ff_sync_set_primitives";
 490    case CS_OPCODE_CS_TERMINATE:
 491       return "cs_terminate";
 492    case SHADER_OPCODE_BARRIER:
 493       return "barrier";
 494    case SHADER_OPCODE_MULH:
 495       return "mulh";
 496    case SHADER_OPCODE_MOV_INDIRECT:
 497       return "mov_indirect";
 498
 499    case VEC4_OPCODE_URB_READ:
 500       return "urb_read";
 501    case TCS_OPCODE_GET_INSTANCE_ID:
 502       return "tcs_get_instance_id";
 503    case TCS_OPCODE_URB_WRITE:
 504       return "tcs_urb_write";
 505    case TCS_OPCODE_SET_INPUT_URB_OFFSETS:
 506       return "tcs_set_input_urb_offsets";
 507    case TCS_OPCODE_SET_OUTPUT_URB_OFFSETS:
 508       return "tcs_set_output_urb_offsets";
 509    case TCS_OPCODE_GET_PRIMITIVE_ID:
 510       return "tcs_get_primitive_id";
 511    case TCS_OPCODE_CREATE_BARRIER_HEADER:
 512       return "tcs_create_barrier_header";
 513    case TCS_OPCODE_SRC0_010_IS_ZERO:
 514       return "tcs_src0<0,1,0>_is_zero";
 515    case TCS_OPCODE_RELEASE_INPUT:
 516       return "tcs_release_input";
 517    case TCS_OPCODE_THREAD_END:
 518       return "tcs_thread_end";
 519    case TES_OPCODE_CREATE_INPUT_READ_HEADER:
 520       return "tes_create_input_read_header";
 521    case TES_OPCODE_ADD_INDIRECT_URB_OFFSET:
 522       return "tes_add_indirect_urb_offset";
 523    case TES_OPCODE_GET_PRIMITIVE_ID:
 524       return "tes_get_primitive_id";
 525
 526    case SHADER_OPCODE_RND_MODE:
 527       return "rnd_mode";
 528    case SHADER_OPCODE_FLOAT_CONTROL_MODE:
 529       return "float_control_mode";
 530    }
 531
 532    unreachable("not reached");
 533 }
 534
 535 bool
 536 brw_saturate_immediate(enum brw_reg_type type, struct brw_reg *reg)
 537 {
 538    union {
 539       unsigned ud;
 540       int d;
 541       float f;
 542       double df;
 543    } imm, sat_imm = { 0 };
 544
 545    const unsigned size = type_sz(type);
 546
 547    /* We want to either do a 32-bit or 64-bit data copy, the type is otherwise
 548     * irrelevant, so just check the size of the type and copy from/to an
 549     * appropriately sized field.
 550     */
 551    if (size < 8)
 552       imm.ud = reg->ud;
 553    else
 554       imm.df = reg->df;
 555
 556    switch (type) {
 557    case BRW_REGISTER_TYPE_UD:
 558    case BRW_REGISTER_TYPE_D:
 559    case BRW_REGISTER_TYPE_UW:
 560    case BRW_REGISTER_TYPE_W:
 561    case BRW_REGISTER_TYPE_UQ:
 562    case BRW_REGISTER_TYPE_Q:
 563       /* Nothing to do. */
 564       return false;
 565    case BRW_REGISTER_TYPE_F:
 566       sat_imm.f = CLAMP(imm.f, 0.0f, 1.0f);
 567       break;
 568    case BRW_REGISTER_TYPE_DF:
 569       sat_imm.df = CLAMP(imm.df, 0.0, 1.0);
 570       break;
 571    case BRW_REGISTER_TYPE_UB:
 572    case BRW_REGISTER_TYPE_B:
 573       unreachable("no UB/B immediates");
 574    case BRW_REGISTER_TYPE_V:
 575    case BRW_REGISTER_TYPE_UV:
 576    case BRW_REGISTER_TYPE_VF:
 577       unreachable("unimplemented: saturate vector immediate");
 578    case BRW_REGISTER_TYPE_HF:
 579       unreachable("unimplemented: saturate HF immediate");
 580    case BRW_REGISTER_TYPE_NF:
 581       unreachable("no NF immediates");
 582    }
 583
 584    if (size < 8) {
 585       if (imm.ud != sat_imm.ud) {
 586          reg->ud = sat_imm.ud;
 587          return true;
 588       }
 589    } else {
 590       if (imm.df != sat_imm.df) {
 591          reg->df = sat_imm.df;
 592          return true;
 593       }
 594    }
 595    return false;
 596 }
 597
 598 bool
 599 brw_negate_immediate(enum brw_reg_type type, struct brw_reg *reg)
 600 {
 601    switch (type) {
 602    case BRW_REGISTER_TYPE_D:
 603    case BRW_REGISTER_TYPE_UD:
 604       reg->d = -reg->d;
 605       return true;
 606    case BRW_REGISTER_TYPE_W:
 607    case BRW_REGISTER_TYPE_UW: {
 608       uint16_t value = -(int16_t)reg->ud;
 609       reg->ud = value | (uint32_t)value << 16;
 610       return true;
 611    }
 612    case BRW_REGISTER_TYPE_F:
 613       reg->f = -reg->f;
 614       return true;
 615    case BRW_REGISTER_TYPE_VF:
 616       reg->ud ^= 0x80808080;
 617       return true;
 618    case BRW_REGISTER_TYPE_DF:
 619       reg->df = -reg->df;
 620       return true;
 621    case BRW_REGISTER_TYPE_UQ:
 622    case BRW_REGISTER_TYPE_Q:
 623       reg->d64 = -reg->d64;
 624       return true;
 625    case BRW_REGISTER_TYPE_UB:
 626    case BRW_REGISTER_TYPE_B:
 627       unreachable("no UB/B immediates");
 628    case BRW_REGISTER_TYPE_UV:
 629    case BRW_REGISTER_TYPE_V:
 630       assert(!"unimplemented: negate UV/V immediate");
 631    case BRW_REGISTER_TYPE_HF:
 632       reg->ud ^= 0x80008000;
 633       return true;
 634    case BRW_REGISTER_TYPE_NF:
 635       unreachable("no NF immediates");
 636    }
 637
 638    return false;
 639 }
 640
 641 bool
 642 brw_abs_immediate(enum brw_reg_type type, struct brw_reg *reg)
 643 {
 644    switch (type) {
 645    case BRW_REGISTER_TYPE_D:
 646       reg->d = abs(reg->d);
 647       return true;
 648    case BRW_REGISTER_TYPE_W: {
 649       uint16_t value = abs((int16_t)reg->ud);
 650       reg->ud = value | (uint32_t)value << 16;
 651       return true;
 652    }
 653    case BRW_REGISTER_TYPE_F:
 654       reg->f = fabsf(reg->f);
 655       return true;
 656    case BRW_REGISTER_TYPE_DF:
 657       reg->df = fabs(reg->df);
 658       return true;
 659    case BRW_REGISTER_TYPE_VF:
 660       reg->ud &= ~0x80808080;
 661       return true;
 662    case BRW_REGISTER_TYPE_Q:
 663       reg->d64 = imaxabs(reg->d64);
 664       return true;
 665    case BRW_REGISTER_TYPE_UB:
 666    case BRW_REGISTER_TYPE_B:
 667       unreachable("no UB/B immediates");
 668    case BRW_REGISTER_TYPE_UQ:
 669    case BRW_REGISTER_TYPE_UD:
 670    case BRW_REGISTER_TYPE_UW:
 671    case BRW_REGISTER_TYPE_UV:
 672       /* Presumably the absolute value modifier on an unsigned source is a
 673        * nop, but it would be nice to confirm.
 674        */
 675       assert(!"unimplemented: abs unsigned immediate");
 676    case BRW_REGISTER_TYPE_V:
 677       assert(!"unimplemented: abs V immediate");
 678    case BRW_REGISTER_TYPE_HF:
 679       reg->ud &= ~0x80008000;
 680       return true;
 681    case BRW_REGISTER_TYPE_NF:
 682       unreachable("no NF immediates");
 683    }
 684
 685    return false;
 686 }
 687
 688 backend_shader::backend_shader(const struct brw_compiler *compiler,
 689                                void *log_data,
 690                                void *mem_ctx,
 691                                const nir_shader *shader,
 692                                struct brw_stage_prog_data *stage_prog_data)
 693    : compiler(compiler),
 694      log_data(log_data),
 695      devinfo(compiler->devinfo),
 696      nir(shader),
 697      stage_prog_data(stage_prog_data),
 698      mem_ctx(mem_ctx),
 699      cfg(NULL),
 700      stage(shader->info.stage)
 701 {
 702    debug_enabled = INTEL_DEBUG & intel_debug_flag_for_shader_stage(stage);
 703    stage_name = _mesa_shader_stage_to_string(stage);
 704    stage_abbrev = _mesa_shader_stage_to_abbrev(stage);
 705 }
 706
 707 backend_shader::~backend_shader()
 708 {
 709 }
 710
 711 bool
 712 backend_reg::equals(const backend_reg &r) const
 713 {
 714    return brw_regs_equal(this, &r) && offset == r.offset;
 715 }
 716
 717 bool
 718 backend_reg::negative_equals(const backend_reg &r) const
 719 {
 720    return brw_regs_negative_equal(this, &r) && offset == r.offset;
 721 }
 722
 723 bool
 724 backend_reg::is_zero() const
 725 {
 726    if (file != IMM)
 727       return false;
 728
 729    assert(type_sz(type) > 1);
 730
 731    switch (type) {
 732    case BRW_REGISTER_TYPE_HF:
 733       assert((d & 0xffff) == ((d >> 16) & 0xffff));
 734       return (d & 0xffff) == 0 || (d & 0xffff) == 0x8000;
 735    case BRW_REGISTER_TYPE_F:
 736       return f == 0;
 737    case BRW_REGISTER_TYPE_DF:
 738       return df == 0;
 739    case BRW_REGISTER_TYPE_W:
 740    case BRW_REGISTER_TYPE_UW:
 741       assert((d & 0xffff) == ((d >> 16) & 0xffff));
 742       return (d & 0xffff) == 0;
 743    case BRW_REGISTER_TYPE_D:
 744    case BRW_REGISTER_TYPE_UD:
 745       return d == 0;
 746    case BRW_REGISTER_TYPE_UQ:
 747    case BRW_REGISTER_TYPE_Q:
 748       return u64 == 0;
 749    default:
 750       return false;
 751    }
 752 }
 753
 754 bool
 755 backend_reg::is_one() const
 756 {
 757    if (file != IMM)
 758       return false;
 759
 760    assert(type_sz(type) > 1);
 761
 762    switch (type) {
 763    case BRW_REGISTER_TYPE_HF:
 764       assert((d & 0xffff) == ((d >> 16) & 0xffff));
 765       return (d & 0xffff) == 0x3c00;
 766    case BRW_REGISTER_TYPE_F:
 767       return f == 1.0f;
 768    case BRW_REGISTER_TYPE_DF:
 769       return df == 1.0;
 770    case BRW_REGISTER_TYPE_W:
 771    case BRW_REGISTER_TYPE_UW:
 772       assert((d & 0xffff) == ((d >> 16) & 0xffff));
 773       return (d & 0xffff) == 1;
 774    case BRW_REGISTER_TYPE_D:
 775    case BRW_REGISTER_TYPE_UD:
 776       return d == 1;
 777    case BRW_REGISTER_TYPE_UQ:
 778    case BRW_REGISTER_TYPE_Q:
 779       return u64 == 1;
 780    default:
 781       return false;
 782    }
 783 }
 784
 785 bool
 786 backend_reg::is_negative_one() const
 787 {
 788    if (file != IMM)
 789       return false;
 790
 791    assert(type_sz(type) > 1);
 792
 793    switch (type) {
 794    case BRW_REGISTER_TYPE_HF:
 795       assert((d & 0xffff) == ((d >> 16) & 0xffff));
 796       return (d & 0xffff) == 0xbc00;
 797    case BRW_REGISTER_TYPE_F:
 798       return f == -1.0;
 799    case BRW_REGISTER_TYPE_DF:
 800       return df == -1.0;
 801    case BRW_REGISTER_TYPE_W:
 802       assert((d & 0xffff) == ((d >> 16) & 0xffff));
 803       return (d & 0xffff) == 0xffff;
 804    case BRW_REGISTER_TYPE_D:
 805       return d == -1;
 806    case BRW_REGISTER_TYPE_Q:
 807       return d64 == -1;
 808    default:
 809       return false;
 810    }
 811 }
 812
 813 bool
 814 backend_reg::is_null() const
 815 {
 816    return file == ARF && nr == BRW_ARF_NULL;
 817 }
 818
 819
 820 bool
 821 backend_reg::is_accumulator() const
 822 {
 823    return file == ARF && nr == BRW_ARF_ACCUMULATOR;
 824 }
 825
 826 bool
 827 backend_instruction::is_commutative() const
 828 {
 829    switch (opcode) {
 830    case BRW_OPCODE_AND:
 831    case BRW_OPCODE_OR:
 832    case BRW_OPCODE_XOR:
 833    case BRW_OPCODE_ADD:
 834    case BRW_OPCODE_MUL:
 835    case SHADER_OPCODE_MULH:
 836       return true;
 837    case BRW_OPCODE_SEL:
 838       /* MIN and MAX are commutative. */
 839       if (conditional_mod == BRW_CONDITIONAL_GE ||
 840           conditional_mod == BRW_CONDITIONAL_L) {
 841          return true;
 842       }
 843       /* fallthrough */
 844    default:
 845       return false;
 846    }
 847 }
 848
 849 bool
 850 backend_instruction::is_3src(const struct gen_device_info *devinfo) const
 851 {
 852    return ::is_3src(devinfo, opcode);
 853 }
 854
 855 bool
 856 backend_instruction::is_tex() const
 857 {
 858    return (opcode == SHADER_OPCODE_TEX ||
 859            opcode == FS_OPCODE_TXB ||
 860            opcode == SHADER_OPCODE_TXD ||
 861            opcode == SHADER_OPCODE_TXF ||
 862            opcode == SHADER_OPCODE_TXF_LZ ||
 863            opcode == SHADER_OPCODE_TXF_CMS ||
 864            opcode == SHADER_OPCODE_TXF_CMS_W ||
 865            opcode == SHADER_OPCODE_TXF_UMS ||
 866            opcode == SHADER_OPCODE_TXF_MCS ||
 867            opcode == SHADER_OPCODE_TXL ||
 868            opcode == SHADER_OPCODE_TXL_LZ ||
 869            opcode == SHADER_OPCODE_TXS ||
 870            opcode == SHADER_OPCODE_LOD ||
 871            opcode == SHADER_OPCODE_TG4 ||
 872            opcode == SHADER_OPCODE_TG4_OFFSET ||
 873            opcode == SHADER_OPCODE_SAMPLEINFO);
 874 }
 875
 876 bool
 877 backend_instruction::is_math() const
 878 {
 879    return (opcode == SHADER_OPCODE_RCP ||
 880            opcode == SHADER_OPCODE_RSQ ||
 881            opcode == SHADER_OPCODE_SQRT ||
 882            opcode == SHADER_OPCODE_EXP2 ||
 883            opcode == SHADER_OPCODE_LOG2 ||
 884            opcode == SHADER_OPCODE_SIN ||
 885            opcode == SHADER_OPCODE_COS ||
 886            opcode == SHADER_OPCODE_INT_QUOTIENT ||
 887            opcode == SHADER_OPCODE_INT_REMAINDER ||
 888            opcode == SHADER_OPCODE_POW);
 889 }
 890
 891 bool
 892 backend_instruction::is_control_flow() const
 893 {
 894    switch (opcode) {
 895    case BRW_OPCODE_DO:
 896    case BRW_OPCODE_WHILE:
 897    case BRW_OPCODE_IF:
 898    case BRW_OPCODE_ELSE:
 899    case BRW_OPCODE_ENDIF:
 900    case BRW_OPCODE_BREAK:
 901    case BRW_OPCODE_CONTINUE:
 902       return true;
 903    default:
 904       return false;
 905    }
 906 }
 907
 908 bool
 909 backend_instruction::can_do_source_mods() const
 910 {
 911    switch (opcode) {
 912    case BRW_OPCODE_ADDC:
 913    case BRW_OPCODE_BFE:
 914    case BRW_OPCODE_BFI1:
 915    case BRW_OPCODE_BFI2:
 916    case BRW_OPCODE_BFREV:
 917    case BRW_OPCODE_CBIT:
 918    case BRW_OPCODE_FBH:
 919    case BRW_OPCODE_FBL:
 920    case BRW_OPCODE_SUBB:
 921    case SHADER_OPCODE_BROADCAST:
 922    case SHADER_OPCODE_CLUSTER_BROADCAST:
 923    case SHADER_OPCODE_MOV_INDIRECT:
 924       return false;
 925    default:
 926       return true;
 927    }
 928 }
 929
 930 bool
 931 backend_instruction::can_do_saturate() const
 932 {
 933    switch (opcode) {
 934    case BRW_OPCODE_ADD:
 935    case BRW_OPCODE_ASR:
 936    case BRW_OPCODE_AVG:
 937    case BRW_OPCODE_DP2:
 938    case BRW_OPCODE_DP3:
 939    case BRW_OPCODE_DP4:
 940    case BRW_OPCODE_DPH:
 941    case BRW_OPCODE_F16TO32:
 942    case BRW_OPCODE_F32TO16:
 943    case BRW_OPCODE_LINE:
 944    case BRW_OPCODE_LRP:
 945    case BRW_OPCODE_MAC:
 946    case BRW_OPCODE_MAD:
 947    case BRW_OPCODE_MATH:
 948    case BRW_OPCODE_MOV:
 949    case BRW_OPCODE_MUL:
 950    case SHADER_OPCODE_MULH:
 951    case BRW_OPCODE_PLN:
 952    case BRW_OPCODE_RNDD:
 953    case BRW_OPCODE_RNDE:
 954    case BRW_OPCODE_RNDU:
 955    case BRW_OPCODE_RNDZ:
 956    case BRW_OPCODE_SEL:
 957    case BRW_OPCODE_SHL:
 958    case BRW_OPCODE_SHR:
 959    case FS_OPCODE_LINTERP:
 960    case SHADER_OPCODE_COS:
 961    case SHADER_OPCODE_EXP2:
 962    case SHADER_OPCODE_LOG2:
 963    case SHADER_OPCODE_POW:
 964    case SHADER_OPCODE_RCP:
 965    case SHADER_OPCODE_RSQ:
 966    case SHADER_OPCODE_SIN:
 967    case SHADER_OPCODE_SQRT:
 968       return true;
 969    default:
 970       return false;
 971    }
 972 }
 973
 974 bool
 975 backend_instruction::can_do_cmod() const
 976 {
 977    switch (opcode) {
 978    case BRW_OPCODE_ADD:
 979    case BRW_OPCODE_ADDC:
 980    case BRW_OPCODE_AND:
 981    case BRW_OPCODE_ASR:
 982    case BRW_OPCODE_AVG:
 983    case BRW_OPCODE_CMP:
 984    case BRW_OPCODE_CMPN:
 985    case BRW_OPCODE_DP2:
 986    case BRW_OPCODE_DP3:
 987    case BRW_OPCODE_DP4:
 988    case BRW_OPCODE_DPH:
 989    case BRW_OPCODE_F16TO32:
 990    case BRW_OPCODE_F32TO16:
 991    case BRW_OPCODE_FRC:
 992    case BRW_OPCODE_LINE:
 993    case BRW_OPCODE_LRP:
 994    case BRW_OPCODE_LZD:
 995    case BRW_OPCODE_MAC:
 996    case BRW_OPCODE_MACH:
 997    case BRW_OPCODE_MAD:
 998    case BRW_OPCODE_MOV:
 999    case BRW_OPCODE_MUL:
1000    case BRW_OPCODE_NOT:
1001    case BRW_OPCODE_OR:
1002    case BRW_OPCODE_PLN:
1003    case BRW_OPCODE_RNDD:
1004    case BRW_OPCODE_RNDE:
1005    case BRW_OPCODE_RNDU:
1006    case BRW_OPCODE_RNDZ:
1007    case BRW_OPCODE_SAD2:
1008    case BRW_OPCODE_SADA2:
1009    case BRW_OPCODE_SHL:
1010    case BRW_OPCODE_SHR:
1011    case BRW_OPCODE_SUBB:
1012    case BRW_OPCODE_XOR:
1013    case FS_OPCODE_LINTERP:
1014       return true;
1015    default:
1016       return false;
1017    }
1018 }
1019
1020 bool
1021 backend_instruction::reads_accumulator_implicitly() const
1022 {
1023    switch (opcode) {
1024    case BRW_OPCODE_MAC:
1025    case BRW_OPCODE_MACH:
1026    case BRW_OPCODE_SADA2:
1027       return true;
1028    default:
1029       return false;
1030    }
1031 }
1032
1033 bool
1034 backend_instruction::writes_accumulator_implicitly(const struct gen_device_info *devinfo) const
1035 {
1036    return writes_accumulator ||
1037           (devinfo->gen < 6 &&
1038            ((opcode >= BRW_OPCODE_ADD && opcode < BRW_OPCODE_NOP) ||
1039             (opcode >= FS_OPCODE_DDX_COARSE && opcode <= FS_OPCODE_LINTERP))) ||
1040           (opcode == FS_OPCODE_LINTERP &&
1041            (!devinfo->has_pln || devinfo->gen <= 6));
1042 }
1043
1044 bool
1045 backend_instruction::has_side_effects() const
1046 {
1047    switch (opcode) {
1048    case SHADER_OPCODE_SEND:
1049       return send_has_side_effects;
1050
1051    case BRW_OPCODE_SYNC:
1052    case VEC4_OPCODE_UNTYPED_ATOMIC:
1053    case SHADER_OPCODE_UNTYPED_ATOMIC_LOGICAL:
1054    case SHADER_OPCODE_UNTYPED_ATOMIC_FLOAT_LOGICAL:
1055    case SHADER_OPCODE_GEN4_SCRATCH_WRITE:
1056    case VEC4_OPCODE_UNTYPED_SURFACE_WRITE:
1057    case SHADER_OPCODE_UNTYPED_SURFACE_WRITE_LOGICAL:
1058    case SHADER_OPCODE_A64_UNTYPED_WRITE_LOGICAL:
1059    case SHADER_OPCODE_A64_BYTE_SCATTERED_WRITE_LOGICAL:
1060    case SHADER_OPCODE_A64_UNTYPED_ATOMIC_LOGICAL:
1061    case SHADER_OPCODE_A64_UNTYPED_ATOMIC_INT64_LOGICAL:
1062    case SHADER_OPCODE_A64_UNTYPED_ATOMIC_FLOAT_LOGICAL:
1063    case SHADER_OPCODE_BYTE_SCATTERED_WRITE_LOGICAL:
1064    case SHADER_OPCODE_DWORD_SCATTERED_WRITE_LOGICAL:
1065    case SHADER_OPCODE_TYPED_ATOMIC_LOGICAL:
1066    case SHADER_OPCODE_TYPED_SURFACE_WRITE_LOGICAL:
1067    case SHADER_OPCODE_MEMORY_FENCE:
1068    case SHADER_OPCODE_INTERLOCK:
1069    case SHADER_OPCODE_URB_WRITE_SIMD8:
1070    case SHADER_OPCODE_URB_WRITE_SIMD8_PER_SLOT:
1071    case SHADER_OPCODE_URB_WRITE_SIMD8_MASKED:
1072    case SHADER_OPCODE_URB_WRITE_SIMD8_MASKED_PER_SLOT:
1073    case FS_OPCODE_FB_WRITE:
1074    case FS_OPCODE_FB_WRITE_LOGICAL:
1075    case FS_OPCODE_REP_FB_WRITE:
1076    case SHADER_OPCODE_BARRIER:
1077    case TCS_OPCODE_URB_WRITE:
1078    case TCS_OPCODE_RELEASE_INPUT:
1079    case SHADER_OPCODE_RND_MODE:
1080    case SHADER_OPCODE_FLOAT_CONTROL_MODE:
1081    case FS_OPCODE_SCHEDULING_FENCE:
1082       return true;
1083    default:
1084       return eot;
1085    }
1086 }
1087
1088 bool
1089 backend_instruction::is_volatile() const
1090 {
1091    switch (opcode) {
1092    case SHADER_OPCODE_SEND:
1093       return send_is_volatile;
1094
1095    case VEC4_OPCODE_UNTYPED_SURFACE_READ:
1096    case SHADER_OPCODE_UNTYPED_SURFACE_READ_LOGICAL:
1097    case SHADER_OPCODE_TYPED_SURFACE_READ_LOGICAL:
1098    case SHADER_OPCODE_BYTE_SCATTERED_READ_LOGICAL:
1099    case SHADER_OPCODE_DWORD_SCATTERED_READ_LOGICAL:
1100    case SHADER_OPCODE_A64_UNTYPED_READ_LOGICAL:
1101    case SHADER_OPCODE_A64_BYTE_SCATTERED_READ_LOGICAL:
1102    case SHADER_OPCODE_URB_READ_SIMD8:
1103    case SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT:
1104    case VEC4_OPCODE_URB_READ:
1105       return true;
1106    default:
1107       return false;
1108    }
1109 }
1110
1111 #ifndef NDEBUG
1112 static bool
1113 inst_is_in_block(const bblock_t *block, const backend_instruction *inst)
1114 {
1115    bool found = false;
1116    foreach_inst_in_block (backend_instruction, i, block) {
1117       if (inst == i) {
1118          found = true;
1119       }
1120    }
1121    return found;
1122 }
1123 #endif
1124
1125 static void
1126 adjust_later_block_ips(bblock_t *start_block, int ip_adjustment)
1127 {
1128    for (bblock_t *block_iter = start_block->next();
1129         block_iter;
1130         block_iter = block_iter->next()) {
1131       block_iter->start_ip += ip_adjustment;
1132       block_iter->end_ip += ip_adjustment;
1133    }
1134 }
1135
1136 void
1137 backend_instruction::insert_after(bblock_t *block, backend_instruction *inst)
1138 {
1139    assert(this != inst);
1140
1141    if (!this->is_head_sentinel())
1142       assert(inst_is_in_block(block, this) || !"Instruction not in block");
1143
1144    block->end_ip++;
1145
1146    adjust_later_block_ips(block, 1);
1147
1148    exec_node::insert_after(inst);
1149 }
1150
1151 void
1152 backend_instruction::insert_before(bblock_t *block, backend_instruction *inst)
1153 {
1154    assert(this != inst);
1155
1156    if (!this->is_tail_sentinel())
1157       assert(inst_is_in_block(block, this) || !"Instruction not in block");
1158
1159    block->end_ip++;
1160
1161    adjust_later_block_ips(block, 1);
1162
1163    exec_node::insert_before(inst);
1164 }
1165
1166 void
1167 backend_instruction::insert_before(bblock_t *block, exec_list *list)
1168 {
1169    assert(inst_is_in_block(block, this) || !"Instruction not in block");
1170
1171    unsigned num_inst = list->length();
1172
1173    block->end_ip += num_inst;
1174
1175    adjust_later_block_ips(block, num_inst);
1176
1177    exec_node::insert_before(list);
1178 }
1179
1180 void
1181 backend_instruction::remove(bblock_t *block)
1182 {
1183    assert(inst_is_in_block(block, this) || !"Instruction not in block");
1184
1185    adjust_later_block_ips(block, -1);
1186
1187    if (block->start_ip == block->end_ip) {
1188       block->cfg->remove_block(block);
1189    } else {
1190       block->end_ip--;
1191    }
1192
1193    exec_node::remove();
1194 }
1195
1196 void
1197 backend_shader::dump_instructions()
1198 {
1199    dump_instructions(NULL);
1200 }
1201
1202 void
1203 backend_shader::dump_instructions(const char *name)
1204 {
1205    FILE *file = stderr;
1206    if (name && geteuid() != 0) {
1207       file = fopen(name, "w");
1208       if (!file)
1209          file = stderr;
1210    }
1211
1212    if (cfg) {
1213       int ip = 0;
1214       foreach_block_and_inst(block, backend_instruction, inst, cfg) {
1215          if (!unlikely(INTEL_DEBUG & DEBUG_OPTIMIZER))
1216             fprintf(file, "%4d: ", ip++);
1217          dump_instruction(inst, file);
1218       }
1219    } else {
1220       int ip = 0;
1221       foreach_in_list(backend_instruction, inst, &instructions) {
1222          if (!unlikely(INTEL_DEBUG & DEBUG_OPTIMIZER))
1223             fprintf(file, "%4d: ", ip++);
1224          dump_instruction(inst, file);
1225       }
1226    }
1227
1228    if (file != stderr) {
1229       fclose(file);
1230    }
1231 }
1232
1233 void
1234 backend_shader::calculate_cfg()
1235 {
1236    if (this->cfg)
1237       return;
1238    cfg = new(mem_ctx) cfg_t(&this->instructions);
1239 }
1240
1241 extern "C" const unsigned *
1242 brw_compile_tes(const struct brw_compiler *compiler,
1243                 void *log_data,
1244                 void *mem_ctx,
1245                 const struct brw_tes_prog_key *key,
1246                 const struct brw_vue_map *input_vue_map,
1247                 struct brw_tes_prog_data *prog_data,
1248                 nir_shader *nir,
1249                 int shader_time_index,
1250                 struct brw_compile_stats *stats,
1251                 char **error_str)
1252 {
1253    const struct gen_device_info *devinfo = compiler->devinfo;
1254    const bool is_scalar = compiler->scalar_stage[MESA_SHADER_TESS_EVAL];
1255    const unsigned *assembly;
1256
1257    nir->info.inputs_read = key->inputs_read;
1258    nir->info.patch_inputs_read = key->patch_inputs_read;
1259
1260    brw_nir_apply_key(nir, compiler, &key->base, 8, is_scalar);
1261    brw_nir_lower_tes_inputs(nir, input_vue_map);
1262    brw_nir_lower_vue_outputs(nir);
1263    brw_postprocess_nir(nir, compiler, is_scalar);
1264
1265    brw_compute_vue_map(devinfo, &prog_data->base.vue_map,
1266                        nir->info.outputs_written,
1267                        nir->info.separate_shader);
1268
1269    unsigned output_size_bytes = prog_data->base.vue_map.num_slots * 4 * 4;
1270
1271    assert(output_size_bytes >= 1);
1272    if (output_size_bytes > GEN7_MAX_DS_URB_ENTRY_SIZE_BYTES) {
1273       if (error_str)
1274          *error_str = ralloc_strdup(mem_ctx, "DS outputs exceed maximum size");
1275       return NULL;
1276    }
1277
1278    prog_data->base.clip_distance_mask =
1279       ((1 << nir->info.clip_distance_array_size) - 1);
1280    prog_data->base.cull_distance_mask =
1281       ((1 << nir->info.cull_distance_array_size) - 1) <<
1282       nir->info.clip_distance_array_size;
1283
1284    /* URB entry sizes are stored as a multiple of 64 bytes. */
1285    prog_data->base.urb_entry_size = ALIGN(output_size_bytes, 64) / 64;
1286
1287    /* On Cannonlake software shall not program an allocation size that
1288     * specifies a size that is a multiple of 3 64B (512-bit) cachelines.
1289     */
1290    if (devinfo->gen == 10 &&
1291        prog_data->base.urb_entry_size % 3 == 0)
1292       prog_data->base.urb_entry_size++;
1293
1294    prog_data->base.urb_read_length = 0;
1295
1296    STATIC_ASSERT(BRW_TESS_PARTITIONING_INTEGER == TESS_SPACING_EQUAL - 1);
1297    STATIC_ASSERT(BRW_TESS_PARTITIONING_ODD_FRACTIONAL ==
1298                  TESS_SPACING_FRACTIONAL_ODD - 1);
1299    STATIC_ASSERT(BRW_TESS_PARTITIONING_EVEN_FRACTIONAL ==
1300                  TESS_SPACING_FRACTIONAL_EVEN - 1);
1301
1302    prog_data->partitioning =
1303       (enum brw_tess_partitioning) (nir->info.tess.spacing - 1);
1304
1305    switch (nir->info.tess.primitive_mode) {
1306    case GL_QUADS:
1307       prog_data->domain = BRW_TESS_DOMAIN_QUAD;
1308       break;
1309    case GL_TRIANGLES:
1310       prog_data->domain = BRW_TESS_DOMAIN_TRI;
1311       break;
1312    case GL_ISOLINES:
1313       prog_data->domain = BRW_TESS_DOMAIN_ISOLINE;
1314       break;
1315    default:
1316       unreachable("invalid domain shader primitive mode");
1317    }
1318
1319    if (nir->info.tess.point_mode) {
1320       prog_data->output_topology = BRW_TESS_OUTPUT_TOPOLOGY_POINT;
1321    } else if (nir->info.tess.primitive_mode == GL_ISOLINES) {
1322       prog_data->output_topology = BRW_TESS_OUTPUT_TOPOLOGY_LINE;
1323    } else {
1324       /* Hardware winding order is backwards from OpenGL */
1325       prog_data->output_topology =
1326          nir->info.tess.ccw ? BRW_TESS_OUTPUT_TOPOLOGY_TRI_CW
1327                              : BRW_TESS_OUTPUT_TOPOLOGY_TRI_CCW;
1328    }
1329
1330    if (unlikely(INTEL_DEBUG & DEBUG_TES)) {
1331       fprintf(stderr, "TES Input ");
1332       brw_print_vue_map(stderr, input_vue_map);
1333       fprintf(stderr, "TES Output ");
1334       brw_print_vue_map(stderr, &prog_data->base.vue_map);
1335    }
1336
1337    if (is_scalar) {
1338       fs_visitor v(compiler, log_data, mem_ctx, &key->base,
1339                    &prog_data->base.base, nir, 8,
1340                    shader_time_index, input_vue_map);
1341       if (!v.run_tes()) {
1342          if (error_str)
1343             *error_str = ralloc_strdup(mem_ctx, v.fail_msg);
1344          return NULL;
1345       }
1346
1347       prog_data->base.base.dispatch_grf_start_reg = v.payload.num_regs;
1348       prog_data->base.dispatch_mode = DISPATCH_MODE_SIMD8;
1349
1350       fs_generator g(compiler, log_data, mem_ctx,
1351                      &prog_data->base.base, v.shader_stats, false,
1352                      MESA_SHADER_TESS_EVAL);
1353       if (unlikely(INTEL_DEBUG & DEBUG_TES)) {
1354          g.enable_debug(ralloc_asprintf(mem_ctx,
1355                                         "%s tessellation evaluation shader %s",
1356                                         nir->info.label ? nir->info.label
1357                                                         : "unnamed",
1358                                         nir->info.name));
1359       }
1360
1361       g.generate_code(v.cfg, 8, stats);
1362
1363       assembly = g.get_assembly();
1364    } else {
1365       brw::vec4_tes_visitor v(compiler, log_data, key, prog_data,
1366                               nir, mem_ctx, shader_time_index);
1367       if (!v.run()) {
1368          if (error_str)
1369             *error_str = ralloc_strdup(mem_ctx, v.fail_msg);
1370          return NULL;
1371       }
1372
1373       if (unlikely(INTEL_DEBUG & DEBUG_TES))
1374          v.dump_instructions();
1375
1376       assembly = brw_vec4_generate_assembly(compiler, log_data, mem_ctx, nir,
1377                                             &prog_data->base, v.cfg, stats);
1378    }
1379
1380    return assembly;
1381 }