src/intel/compiler/brw_shader.cpp

   1 /*
   2  * Copyright © 2010 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  */
  23
  24 #include "brw_cfg.h"
  25 #include "brw_eu.h"
  26 #include "brw_fs.h"
  27 #include "brw_nir.h"
  28 #include "brw_vec4_tes.h"
  29 #include "common/gen_debug.h"
  30 #include "main/uniforms.h"
  31 #include "util/macros.h"
  32
  33 enum brw_reg_type
  34 brw_type_for_base_type(const struct glsl_type *type)
  35 {
  36    switch (type->base_type) {
  37    case GLSL_TYPE_FLOAT16:
  38       return BRW_REGISTER_TYPE_HF;
  39    case GLSL_TYPE_FLOAT:
  40       return BRW_REGISTER_TYPE_F;
  41    case GLSL_TYPE_INT:
  42    case GLSL_TYPE_BOOL:
  43    case GLSL_TYPE_SUBROUTINE:
  44       return BRW_REGISTER_TYPE_D;
  45    case GLSL_TYPE_INT16:
  46       return BRW_REGISTER_TYPE_W;
  47    case GLSL_TYPE_INT8:
  48       return BRW_REGISTER_TYPE_B;
  49    case GLSL_TYPE_UINT:
  50       return BRW_REGISTER_TYPE_UD;
  51    case GLSL_TYPE_UINT16:
  52       return BRW_REGISTER_TYPE_UW;
  53    case GLSL_TYPE_UINT8:
  54       return BRW_REGISTER_TYPE_UB;
  55    case GLSL_TYPE_ARRAY:
  56       return brw_type_for_base_type(type->fields.array);
  57    case GLSL_TYPE_STRUCT:
  58    case GLSL_TYPE_SAMPLER:
  59    case GLSL_TYPE_ATOMIC_UINT:
  60       /* These should be overridden with the type of the member when
  61        * dereferenced into.  BRW_REGISTER_TYPE_UD seems like a likely
  62        * way to trip up if we don't.
  63        */
  64       return BRW_REGISTER_TYPE_UD;
  65    case GLSL_TYPE_IMAGE:
  66       return BRW_REGISTER_TYPE_UD;
  67    case GLSL_TYPE_DOUBLE:
  68       return BRW_REGISTER_TYPE_DF;
  69    case GLSL_TYPE_UINT64:
  70       return BRW_REGISTER_TYPE_UQ;
  71    case GLSL_TYPE_INT64:
  72       return BRW_REGISTER_TYPE_Q;
  73    case GLSL_TYPE_VOID:
  74    case GLSL_TYPE_ERROR:
  75    case GLSL_TYPE_INTERFACE:
  76    case GLSL_TYPE_FUNCTION:
  77       unreachable("not reached");
  78    }
  79
  80    return BRW_REGISTER_TYPE_F;
  81 }
  82
  83 enum brw_conditional_mod
  84 brw_conditional_for_comparison(unsigned int op)
  85 {
  86    switch (op) {
  87    case ir_binop_less:
  88       return BRW_CONDITIONAL_L;
  89    case ir_binop_gequal:
  90       return BRW_CONDITIONAL_GE;
  91    case ir_binop_equal:
  92    case ir_binop_all_equal: /* same as equal for scalars */
  93       return BRW_CONDITIONAL_Z;
  94    case ir_binop_nequal:
  95    case ir_binop_any_nequal: /* same as nequal for scalars */
  96       return BRW_CONDITIONAL_NZ;
  97    default:
  98       unreachable("not reached: bad operation for comparison");
  99    }
 100 }
 101
 102 uint32_t
 103 brw_math_function(enum opcode op)
 104 {
 105    switch (op) {
 106    case SHADER_OPCODE_RCP:
 107       return BRW_MATH_FUNCTION_INV;
 108    case SHADER_OPCODE_RSQ:
 109       return BRW_MATH_FUNCTION_RSQ;
 110    case SHADER_OPCODE_SQRT:
 111       return BRW_MATH_FUNCTION_SQRT;
 112    case SHADER_OPCODE_EXP2:
 113       return BRW_MATH_FUNCTION_EXP;
 114    case SHADER_OPCODE_LOG2:
 115       return BRW_MATH_FUNCTION_LOG;
 116    case SHADER_OPCODE_POW:
 117       return BRW_MATH_FUNCTION_POW;
 118    case SHADER_OPCODE_SIN:
 119       return BRW_MATH_FUNCTION_SIN;
 120    case SHADER_OPCODE_COS:
 121       return BRW_MATH_FUNCTION_COS;
 122    case SHADER_OPCODE_INT_QUOTIENT:
 123       return BRW_MATH_FUNCTION_INT_DIV_QUOTIENT;
 124    case SHADER_OPCODE_INT_REMAINDER:
 125       return BRW_MATH_FUNCTION_INT_DIV_REMAINDER;
 126    default:
 127       unreachable("not reached: unknown math function");
 128    }
 129 }
 130
 131 bool
 132 brw_texture_offset(int *offsets, unsigned num_components, uint32_t *offset_bits)
 133 {
 134    if (!offsets) return false;  /* nonconstant offset; caller will handle it. */
 135
 136    /* offset out of bounds; caller will handle it. */
 137    for (unsigned i = 0; i < num_components; i++)
 138       if (offsets[i] > 7 || offsets[i] < -8)
 139          return false;
 140
 141    /* Combine all three offsets into a single unsigned dword:
 142     *
 143     *    bits 11:8 - U Offset (X component)
 144     *    bits  7:4 - V Offset (Y component)
 145     *    bits  3:0 - R Offset (Z component)
 146     */
 147    *offset_bits = 0;
 148    for (unsigned i = 0; i < num_components; i++) {
 149       const unsigned shift = 4 * (2 - i);
 150       *offset_bits |= (offsets[i] << shift) & (0xF << shift);
 151    }
 152    return true;
 153 }
 154
 155 const char *
 156 brw_instruction_name(const struct gen_device_info *devinfo, enum opcode op)
 157 {
 158    switch (op) {
 159    case BRW_OPCODE_ILLEGAL ... BRW_OPCODE_NOP:
 160       /* The DO instruction doesn't exist on Gen6+, but we use it to mark the
 161        * start of a loop in the IR.
 162        */
 163       if (devinfo->gen >= 6 && op == BRW_OPCODE_DO)
 164          return "do";
 165
 166       /* The following conversion opcodes doesn't exist on Gen8+, but we use
 167        * then to mark that we want to do the conversion.
 168        */
 169       if (devinfo->gen > 7 && op == BRW_OPCODE_F32TO16)
 170          return "f32to16";
 171
 172       if (devinfo->gen > 7 && op == BRW_OPCODE_F16TO32)
 173          return "f16to32";
 174
 175       assert(brw_opcode_desc(devinfo, op)->name);
 176       return brw_opcode_desc(devinfo, op)->name;
 177    case FS_OPCODE_FB_WRITE:
 178       return "fb_write";
 179    case FS_OPCODE_FB_WRITE_LOGICAL:
 180       return "fb_write_logical";
 181    case FS_OPCODE_REP_FB_WRITE:
 182       return "rep_fb_write";
 183    case FS_OPCODE_FB_READ:
 184       return "fb_read";
 185    case FS_OPCODE_FB_READ_LOGICAL:
 186       return "fb_read_logical";
 187
 188    case SHADER_OPCODE_RCP:
 189       return "rcp";
 190    case SHADER_OPCODE_RSQ:
 191       return "rsq";
 192    case SHADER_OPCODE_SQRT:
 193       return "sqrt";
 194    case SHADER_OPCODE_EXP2:
 195       return "exp2";
 196    case SHADER_OPCODE_LOG2:
 197       return "log2";
 198    case SHADER_OPCODE_POW:
 199       return "pow";
 200    case SHADER_OPCODE_INT_QUOTIENT:
 201       return "int_quot";
 202    case SHADER_OPCODE_INT_REMAINDER:
 203       return "int_rem";
 204    case SHADER_OPCODE_SIN:
 205       return "sin";
 206    case SHADER_OPCODE_COS:
 207       return "cos";
 208
 209    case SHADER_OPCODE_TEX:
 210       return "tex";
 211    case SHADER_OPCODE_TEX_LOGICAL:
 212       return "tex_logical";
 213    case SHADER_OPCODE_TXD:
 214       return "txd";
 215    case SHADER_OPCODE_TXD_LOGICAL:
 216       return "txd_logical";
 217    case SHADER_OPCODE_TXF:
 218       return "txf";
 219    case SHADER_OPCODE_TXF_LOGICAL:
 220       return "txf_logical";
 221    case SHADER_OPCODE_TXF_LZ:
 222       return "txf_lz";
 223    case SHADER_OPCODE_TXL:
 224       return "txl";
 225    case SHADER_OPCODE_TXL_LOGICAL:
 226       return "txl_logical";
 227    case SHADER_OPCODE_TXL_LZ:
 228       return "txl_lz";
 229    case SHADER_OPCODE_TXS:
 230       return "txs";
 231    case SHADER_OPCODE_TXS_LOGICAL:
 232       return "txs_logical";
 233    case FS_OPCODE_TXB:
 234       return "txb";
 235    case FS_OPCODE_TXB_LOGICAL:
 236       return "txb_logical";
 237    case SHADER_OPCODE_TXF_CMS:
 238       return "txf_cms";
 239    case SHADER_OPCODE_TXF_CMS_LOGICAL:
 240       return "txf_cms_logical";
 241    case SHADER_OPCODE_TXF_CMS_W:
 242       return "txf_cms_w";
 243    case SHADER_OPCODE_TXF_CMS_W_LOGICAL:
 244       return "txf_cms_w_logical";
 245    case SHADER_OPCODE_TXF_UMS:
 246       return "txf_ums";
 247    case SHADER_OPCODE_TXF_UMS_LOGICAL:
 248       return "txf_ums_logical";
 249    case SHADER_OPCODE_TXF_MCS:
 250       return "txf_mcs";
 251    case SHADER_OPCODE_TXF_MCS_LOGICAL:
 252       return "txf_mcs_logical";
 253    case SHADER_OPCODE_LOD:
 254       return "lod";
 255    case SHADER_OPCODE_LOD_LOGICAL:
 256       return "lod_logical";
 257    case SHADER_OPCODE_TG4:
 258       return "tg4";
 259    case SHADER_OPCODE_TG4_LOGICAL:
 260       return "tg4_logical";
 261    case SHADER_OPCODE_TG4_OFFSET:
 262       return "tg4_offset";
 263    case SHADER_OPCODE_TG4_OFFSET_LOGICAL:
 264       return "tg4_offset_logical";
 265    case SHADER_OPCODE_SAMPLEINFO:
 266       return "sampleinfo";
 267    case SHADER_OPCODE_SAMPLEINFO_LOGICAL:
 268       return "sampleinfo_logical";
 269
 270    case SHADER_OPCODE_IMAGE_SIZE:
 271       return "image_size";
 272
 273    case SHADER_OPCODE_SHADER_TIME_ADD:
 274       return "shader_time_add";
 275
 276    case SHADER_OPCODE_UNTYPED_ATOMIC:
 277       return "untyped_atomic";
 278    case SHADER_OPCODE_UNTYPED_ATOMIC_LOGICAL:
 279       return "untyped_atomic_logical";
 280    case SHADER_OPCODE_UNTYPED_ATOMIC_FLOAT:
 281       return "untyped_atomic_float";
 282    case SHADER_OPCODE_UNTYPED_ATOMIC_FLOAT_LOGICAL:
 283       return "untyped_atomic_float_logical";
 284    case SHADER_OPCODE_UNTYPED_SURFACE_READ:
 285       return "untyped_surface_read";
 286    case SHADER_OPCODE_UNTYPED_SURFACE_READ_LOGICAL:
 287       return "untyped_surface_read_logical";
 288    case SHADER_OPCODE_UNTYPED_SURFACE_WRITE:
 289       return "untyped_surface_write";
 290    case SHADER_OPCODE_UNTYPED_SURFACE_WRITE_LOGICAL:
 291       return "untyped_surface_write_logical";
 292    case SHADER_OPCODE_TYPED_ATOMIC:
 293       return "typed_atomic";
 294    case SHADER_OPCODE_TYPED_ATOMIC_LOGICAL:
 295       return "typed_atomic_logical";
 296    case SHADER_OPCODE_TYPED_SURFACE_READ:
 297       return "typed_surface_read";
 298    case SHADER_OPCODE_TYPED_SURFACE_READ_LOGICAL:
 299       return "typed_surface_read_logical";
 300    case SHADER_OPCODE_TYPED_SURFACE_WRITE:
 301       return "typed_surface_write";
 302    case SHADER_OPCODE_TYPED_SURFACE_WRITE_LOGICAL:
 303       return "typed_surface_write_logical";
 304    case SHADER_OPCODE_MEMORY_FENCE:
 305       return "memory_fence";
 306    case SHADER_OPCODE_INTERLOCK:
 307       /* For an interlock we actually issue a memory fence via sendc. */
 308       return "interlock";
 309
 310    case SHADER_OPCODE_BYTE_SCATTERED_READ:
 311       return "byte_scattered_read";
 312    case SHADER_OPCODE_BYTE_SCATTERED_READ_LOGICAL:
 313       return "byte_scattered_read_logical";
 314    case SHADER_OPCODE_BYTE_SCATTERED_WRITE:
 315       return "byte_scattered_write";
 316    case SHADER_OPCODE_BYTE_SCATTERED_WRITE_LOGICAL:
 317       return "byte_scattered_write_logical";
 318
 319    case SHADER_OPCODE_LOAD_PAYLOAD:
 320       return "load_payload";
 321    case FS_OPCODE_PACK:
 322       return "pack";
 323
 324    case SHADER_OPCODE_GEN4_SCRATCH_READ:
 325       return "gen4_scratch_read";
 326    case SHADER_OPCODE_GEN4_SCRATCH_WRITE:
 327       return "gen4_scratch_write";
 328    case SHADER_OPCODE_GEN7_SCRATCH_READ:
 329       return "gen7_scratch_read";
 330    case SHADER_OPCODE_URB_WRITE_SIMD8:
 331       return "gen8_urb_write_simd8";
 332    case SHADER_OPCODE_URB_WRITE_SIMD8_PER_SLOT:
 333       return "gen8_urb_write_simd8_per_slot";
 334    case SHADER_OPCODE_URB_WRITE_SIMD8_MASKED:
 335       return "gen8_urb_write_simd8_masked";
 336    case SHADER_OPCODE_URB_WRITE_SIMD8_MASKED_PER_SLOT:
 337       return "gen8_urb_write_simd8_masked_per_slot";
 338    case SHADER_OPCODE_URB_READ_SIMD8:
 339       return "urb_read_simd8";
 340    case SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT:
 341       return "urb_read_simd8_per_slot";
 342
 343    case SHADER_OPCODE_FIND_LIVE_CHANNEL:
 344       return "find_live_channel";
 345    case SHADER_OPCODE_BROADCAST:
 346       return "broadcast";
 347    case SHADER_OPCODE_SHUFFLE:
 348       return "shuffle";
 349    case SHADER_OPCODE_SEL_EXEC:
 350       return "sel_exec";
 351    case SHADER_OPCODE_QUAD_SWIZZLE:
 352       return "quad_swizzle";
 353    case SHADER_OPCODE_CLUSTER_BROADCAST:
 354       return "cluster_broadcast";
 355
 356    case SHADER_OPCODE_GET_BUFFER_SIZE:
 357       return "get_buffer_size";
 358
 359    case VEC4_OPCODE_MOV_BYTES:
 360       return "mov_bytes";
 361    case VEC4_OPCODE_PACK_BYTES:
 362       return "pack_bytes";
 363    case VEC4_OPCODE_UNPACK_UNIFORM:
 364       return "unpack_uniform";
 365    case VEC4_OPCODE_DOUBLE_TO_F32:
 366       return "double_to_f32";
 367    case VEC4_OPCODE_DOUBLE_TO_D32:
 368       return "double_to_d32";
 369    case VEC4_OPCODE_DOUBLE_TO_U32:
 370       return "double_to_u32";
 371    case VEC4_OPCODE_TO_DOUBLE:
 372       return "single_to_double";
 373    case VEC4_OPCODE_PICK_LOW_32BIT:
 374       return "pick_low_32bit";
 375    case VEC4_OPCODE_PICK_HIGH_32BIT:
 376       return "pick_high_32bit";
 377    case VEC4_OPCODE_SET_LOW_32BIT:
 378       return "set_low_32bit";
 379    case VEC4_OPCODE_SET_HIGH_32BIT:
 380       return "set_high_32bit";
 381
 382    case FS_OPCODE_DDX_COARSE:
 383       return "ddx_coarse";
 384    case FS_OPCODE_DDX_FINE:
 385       return "ddx_fine";
 386    case FS_OPCODE_DDY_COARSE:
 387       return "ddy_coarse";
 388    case FS_OPCODE_DDY_FINE:
 389       return "ddy_fine";
 390
 391    case FS_OPCODE_LINTERP:
 392       return "linterp";
 393
 394    case FS_OPCODE_PIXEL_X:
 395       return "pixel_x";
 396    case FS_OPCODE_PIXEL_Y:
 397       return "pixel_y";
 398
 399    case FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD:
 400       return "uniform_pull_const";
 401    case FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD_GEN7:
 402       return "uniform_pull_const_gen7";
 403    case FS_OPCODE_VARYING_PULL_CONSTANT_LOAD_GEN4:
 404       return "varying_pull_const_gen4";
 405    case FS_OPCODE_VARYING_PULL_CONSTANT_LOAD_GEN7:
 406       return "varying_pull_const_gen7";
 407    case FS_OPCODE_VARYING_PULL_CONSTANT_LOAD_LOGICAL:
 408       return "varying_pull_const_logical";
 409
 410    case FS_OPCODE_DISCARD_JUMP:
 411       return "discard_jump";
 412
 413    case FS_OPCODE_SET_SAMPLE_ID:
 414       return "set_sample_id";
 415
 416    case FS_OPCODE_PACK_HALF_2x16_SPLIT:
 417       return "pack_half_2x16_split";
 418    case FS_OPCODE_UNPACK_HALF_2x16_SPLIT_X:
 419       return "unpack_half_2x16_split_x";
 420    case FS_OPCODE_UNPACK_HALF_2x16_SPLIT_Y:
 421       return "unpack_half_2x16_split_y";
 422
 423    case FS_OPCODE_PLACEHOLDER_HALT:
 424       return "placeholder_halt";
 425
 426    case FS_OPCODE_INTERPOLATE_AT_SAMPLE:
 427       return "interp_sample";
 428    case FS_OPCODE_INTERPOLATE_AT_SHARED_OFFSET:
 429       return "interp_shared_offset";
 430    case FS_OPCODE_INTERPOLATE_AT_PER_SLOT_OFFSET:
 431       return "interp_per_slot_offset";
 432
 433    case VS_OPCODE_URB_WRITE:
 434       return "vs_urb_write";
 435    case VS_OPCODE_PULL_CONSTANT_LOAD:
 436       return "pull_constant_load";
 437    case VS_OPCODE_PULL_CONSTANT_LOAD_GEN7:
 438       return "pull_constant_load_gen7";
 439
 440    case VS_OPCODE_SET_SIMD4X2_HEADER_GEN9:
 441       return "set_simd4x2_header_gen9";
 442
 443    case VS_OPCODE_UNPACK_FLAGS_SIMD4X2:
 444       return "unpack_flags_simd4x2";
 445
 446    case GS_OPCODE_URB_WRITE:
 447       return "gs_urb_write";
 448    case GS_OPCODE_URB_WRITE_ALLOCATE:
 449       return "gs_urb_write_allocate";
 450    case GS_OPCODE_THREAD_END:
 451       return "gs_thread_end";
 452    case GS_OPCODE_SET_WRITE_OFFSET:
 453       return "set_write_offset";
 454    case GS_OPCODE_SET_VERTEX_COUNT:
 455       return "set_vertex_count";
 456    case GS_OPCODE_SET_DWORD_2:
 457       return "set_dword_2";
 458    case GS_OPCODE_PREPARE_CHANNEL_MASKS:
 459       return "prepare_channel_masks";
 460    case GS_OPCODE_SET_CHANNEL_MASKS:
 461       return "set_channel_masks";
 462    case GS_OPCODE_GET_INSTANCE_ID:
 463       return "get_instance_id";
 464    case GS_OPCODE_FF_SYNC:
 465       return "ff_sync";
 466    case GS_OPCODE_SET_PRIMITIVE_ID:
 467       return "set_primitive_id";
 468    case GS_OPCODE_SVB_WRITE:
 469       return "gs_svb_write";
 470    case GS_OPCODE_SVB_SET_DST_INDEX:
 471       return "gs_svb_set_dst_index";
 472    case GS_OPCODE_FF_SYNC_SET_PRIMITIVES:
 473       return "gs_ff_sync_set_primitives";
 474    case CS_OPCODE_CS_TERMINATE:
 475       return "cs_terminate";
 476    case SHADER_OPCODE_BARRIER:
 477       return "barrier";
 478    case SHADER_OPCODE_MULH:
 479       return "mulh";
 480    case SHADER_OPCODE_MOV_INDIRECT:
 481       return "mov_indirect";
 482
 483    case VEC4_OPCODE_URB_READ:
 484       return "urb_read";
 485    case TCS_OPCODE_GET_INSTANCE_ID:
 486       return "tcs_get_instance_id";
 487    case TCS_OPCODE_URB_WRITE:
 488       return "tcs_urb_write";
 489    case TCS_OPCODE_SET_INPUT_URB_OFFSETS:
 490       return "tcs_set_input_urb_offsets";
 491    case TCS_OPCODE_SET_OUTPUT_URB_OFFSETS:
 492       return "tcs_set_output_urb_offsets";
 493    case TCS_OPCODE_GET_PRIMITIVE_ID:
 494       return "tcs_get_primitive_id";
 495    case TCS_OPCODE_CREATE_BARRIER_HEADER:
 496       return "tcs_create_barrier_header";
 497    case TCS_OPCODE_SRC0_010_IS_ZERO:
 498       return "tcs_src0<0,1,0>_is_zero";
 499    case TCS_OPCODE_RELEASE_INPUT:
 500       return "tcs_release_input";
 501    case TCS_OPCODE_THREAD_END:
 502       return "tcs_thread_end";
 503    case TES_OPCODE_CREATE_INPUT_READ_HEADER:
 504       return "tes_create_input_read_header";
 505    case TES_OPCODE_ADD_INDIRECT_URB_OFFSET:
 506       return "tes_add_indirect_urb_offset";
 507    case TES_OPCODE_GET_PRIMITIVE_ID:
 508       return "tes_get_primitive_id";
 509
 510    case SHADER_OPCODE_RND_MODE:
 511       return "rnd_mode";
 512    }
 513
 514    unreachable("not reached");
 515 }
 516
 517 bool
 518 brw_saturate_immediate(enum brw_reg_type type, struct brw_reg *reg)
 519 {
 520    union {
 521       unsigned ud;
 522       int d;
 523       float f;
 524       double df;
 525    } imm, sat_imm = { 0 };
 526
 527    const unsigned size = type_sz(type);
 528
 529    /* We want to either do a 32-bit or 64-bit data copy, the type is otherwise
 530     * irrelevant, so just check the size of the type and copy from/to an
 531     * appropriately sized field.
 532     */
 533    if (size < 8)
 534       imm.ud = reg->ud;
 535    else
 536       imm.df = reg->df;
 537
 538    switch (type) {
 539    case BRW_REGISTER_TYPE_UD:
 540    case BRW_REGISTER_TYPE_D:
 541    case BRW_REGISTER_TYPE_UW:
 542    case BRW_REGISTER_TYPE_W:
 543    case BRW_REGISTER_TYPE_UQ:
 544    case BRW_REGISTER_TYPE_Q:
 545       /* Nothing to do. */
 546       return false;
 547    case BRW_REGISTER_TYPE_F:
 548       sat_imm.f = CLAMP(imm.f, 0.0f, 1.0f);
 549       break;
 550    case BRW_REGISTER_TYPE_DF:
 551       sat_imm.df = CLAMP(imm.df, 0.0, 1.0);
 552       break;
 553    case BRW_REGISTER_TYPE_UB:
 554    case BRW_REGISTER_TYPE_B:
 555       unreachable("no UB/B immediates");
 556    case BRW_REGISTER_TYPE_V:
 557    case BRW_REGISTER_TYPE_UV:
 558    case BRW_REGISTER_TYPE_VF:
 559       unreachable("unimplemented: saturate vector immediate");
 560    case BRW_REGISTER_TYPE_HF:
 561       unreachable("unimplemented: saturate HF immediate");
 562    case BRW_REGISTER_TYPE_NF:
 563       unreachable("no NF immediates");
 564    }
 565
 566    if (size < 8) {
 567       if (imm.ud != sat_imm.ud) {
 568          reg->ud = sat_imm.ud;
 569          return true;
 570       }
 571    } else {
 572       if (imm.df != sat_imm.df) {
 573          reg->df = sat_imm.df;
 574          return true;
 575       }
 576    }
 577    return false;
 578 }
 579
 580 bool
 581 brw_negate_immediate(enum brw_reg_type type, struct brw_reg *reg)
 582 {
 583    switch (type) {
 584    case BRW_REGISTER_TYPE_D:
 585    case BRW_REGISTER_TYPE_UD:
 586       reg->d = -reg->d;
 587       return true;
 588    case BRW_REGISTER_TYPE_W:
 589    case BRW_REGISTER_TYPE_UW: {
 590       uint16_t value = -(int16_t)reg->ud;
 591       reg->ud = value | (uint32_t)value << 16;
 592       return true;
 593    }
 594    case BRW_REGISTER_TYPE_F:
 595       reg->f = -reg->f;
 596       return true;
 597    case BRW_REGISTER_TYPE_VF:
 598       reg->ud ^= 0x80808080;
 599       return true;
 600    case BRW_REGISTER_TYPE_DF:
 601       reg->df = -reg->df;
 602       return true;
 603    case BRW_REGISTER_TYPE_UQ:
 604    case BRW_REGISTER_TYPE_Q:
 605       reg->d64 = -reg->d64;
 606       return true;
 607    case BRW_REGISTER_TYPE_UB:
 608    case BRW_REGISTER_TYPE_B:
 609       unreachable("no UB/B immediates");
 610    case BRW_REGISTER_TYPE_UV:
 611    case BRW_REGISTER_TYPE_V:
 612       assert(!"unimplemented: negate UV/V immediate");
 613    case BRW_REGISTER_TYPE_HF:
 614       reg->ud ^= 0x80008000;
 615       return true;
 616    case BRW_REGISTER_TYPE_NF:
 617       unreachable("no NF immediates");
 618    }
 619
 620    return false;
 621 }
 622
 623 bool
 624 brw_abs_immediate(enum brw_reg_type type, struct brw_reg *reg)
 625 {
 626    switch (type) {
 627    case BRW_REGISTER_TYPE_D:
 628       reg->d = abs(reg->d);
 629       return true;
 630    case BRW_REGISTER_TYPE_W: {
 631       uint16_t value = abs((int16_t)reg->ud);
 632       reg->ud = value | (uint32_t)value << 16;
 633       return true;
 634    }
 635    case BRW_REGISTER_TYPE_F:
 636       reg->f = fabsf(reg->f);
 637       return true;
 638    case BRW_REGISTER_TYPE_DF:
 639       reg->df = fabs(reg->df);
 640       return true;
 641    case BRW_REGISTER_TYPE_VF:
 642       reg->ud &= ~0x80808080;
 643       return true;
 644    case BRW_REGISTER_TYPE_Q:
 645       reg->d64 = imaxabs(reg->d64);
 646       return true;
 647    case BRW_REGISTER_TYPE_UB:
 648    case BRW_REGISTER_TYPE_B:
 649       unreachable("no UB/B immediates");
 650    case BRW_REGISTER_TYPE_UQ:
 651    case BRW_REGISTER_TYPE_UD:
 652    case BRW_REGISTER_TYPE_UW:
 653    case BRW_REGISTER_TYPE_UV:
 654       /* Presumably the absolute value modifier on an unsigned source is a
 655        * nop, but it would be nice to confirm.
 656        */
 657       assert(!"unimplemented: abs unsigned immediate");
 658    case BRW_REGISTER_TYPE_V:
 659       assert(!"unimplemented: abs V immediate");
 660    case BRW_REGISTER_TYPE_HF:
 661       reg->ud &= ~0x80008000;
 662       return true;
 663    case BRW_REGISTER_TYPE_NF:
 664       unreachable("no NF immediates");
 665    }
 666
 667    return false;
 668 }
 669
 670 backend_shader::backend_shader(const struct brw_compiler *compiler,
 671                                void *log_data,
 672                                void *mem_ctx,
 673                                const nir_shader *shader,
 674                                struct brw_stage_prog_data *stage_prog_data)
 675    : compiler(compiler),
 676      log_data(log_data),
 677      devinfo(compiler->devinfo),
 678      nir(shader),
 679      stage_prog_data(stage_prog_data),
 680      mem_ctx(mem_ctx),
 681      cfg(NULL),
 682      stage(shader->info.stage)
 683 {
 684    debug_enabled = INTEL_DEBUG & intel_debug_flag_for_shader_stage(stage);
 685    stage_name = _mesa_shader_stage_to_string(stage);
 686    stage_abbrev = _mesa_shader_stage_to_abbrev(stage);
 687 }
 688
 689 backend_shader::~backend_shader()
 690 {
 691 }
 692
 693 bool
 694 backend_reg::equals(const backend_reg &r) const
 695 {
 696    return brw_regs_equal(this, &r) && offset == r.offset;
 697 }
 698
 699 bool
 700 backend_reg::negative_equals(const backend_reg &r) const
 701 {
 702    return brw_regs_negative_equal(this, &r) && offset == r.offset;
 703 }
 704
 705 bool
 706 backend_reg::is_zero() const
 707 {
 708    if (file != IMM)
 709       return false;
 710
 711    switch (type) {
 712    case BRW_REGISTER_TYPE_F:
 713       return f == 0;
 714    case BRW_REGISTER_TYPE_DF:
 715       return df == 0;
 716    case BRW_REGISTER_TYPE_D:
 717    case BRW_REGISTER_TYPE_UD:
 718       return d == 0;
 719    case BRW_REGISTER_TYPE_UQ:
 720    case BRW_REGISTER_TYPE_Q:
 721       return u64 == 0;
 722    default:
 723       return false;
 724    }
 725 }
 726
 727 bool
 728 backend_reg::is_one() const
 729 {
 730    if (file != IMM)
 731       return false;
 732
 733    switch (type) {
 734    case BRW_REGISTER_TYPE_F:
 735       return f == 1.0f;
 736    case BRW_REGISTER_TYPE_DF:
 737       return df == 1.0;
 738    case BRW_REGISTER_TYPE_D:
 739    case BRW_REGISTER_TYPE_UD:
 740       return d == 1;
 741    case BRW_REGISTER_TYPE_UQ:
 742    case BRW_REGISTER_TYPE_Q:
 743       return u64 == 1;
 744    default:
 745       return false;
 746    }
 747 }
 748
 749 bool
 750 backend_reg::is_negative_one() const
 751 {
 752    if (file != IMM)
 753       return false;
 754
 755    switch (type) {
 756    case BRW_REGISTER_TYPE_F:
 757       return f == -1.0;
 758    case BRW_REGISTER_TYPE_DF:
 759       return df == -1.0;
 760    case BRW_REGISTER_TYPE_D:
 761       return d == -1;
 762    case BRW_REGISTER_TYPE_Q:
 763       return d64 == -1;
 764    default:
 765       return false;
 766    }
 767 }
 768
 769 bool
 770 backend_reg::is_null() const
 771 {
 772    return file == ARF && nr == BRW_ARF_NULL;
 773 }
 774
 775
 776 bool
 777 backend_reg::is_accumulator() const
 778 {
 779    return file == ARF && nr == BRW_ARF_ACCUMULATOR;
 780 }
 781
 782 bool
 783 backend_instruction::is_commutative() const
 784 {
 785    switch (opcode) {
 786    case BRW_OPCODE_AND:
 787    case BRW_OPCODE_OR:
 788    case BRW_OPCODE_XOR:
 789    case BRW_OPCODE_ADD:
 790    case BRW_OPCODE_MUL:
 791    case SHADER_OPCODE_MULH:
 792       return true;
 793    case BRW_OPCODE_SEL:
 794       /* MIN and MAX are commutative. */
 795       if (conditional_mod == BRW_CONDITIONAL_GE ||
 796           conditional_mod == BRW_CONDITIONAL_L) {
 797          return true;
 798       }
 799       /* fallthrough */
 800    default:
 801       return false;
 802    }
 803 }
 804
 805 bool
 806 backend_instruction::is_3src(const struct gen_device_info *devinfo) const
 807 {
 808    return ::is_3src(devinfo, opcode);
 809 }
 810
 811 bool
 812 backend_instruction::is_tex() const
 813 {
 814    return (opcode == SHADER_OPCODE_TEX ||
 815            opcode == FS_OPCODE_TXB ||
 816            opcode == SHADER_OPCODE_TXD ||
 817            opcode == SHADER_OPCODE_TXF ||
 818            opcode == SHADER_OPCODE_TXF_LZ ||
 819            opcode == SHADER_OPCODE_TXF_CMS ||
 820            opcode == SHADER_OPCODE_TXF_CMS_W ||
 821            opcode == SHADER_OPCODE_TXF_UMS ||
 822            opcode == SHADER_OPCODE_TXF_MCS ||
 823            opcode == SHADER_OPCODE_TXL ||
 824            opcode == SHADER_OPCODE_TXL_LZ ||
 825            opcode == SHADER_OPCODE_TXS ||
 826            opcode == SHADER_OPCODE_LOD ||
 827            opcode == SHADER_OPCODE_TG4 ||
 828            opcode == SHADER_OPCODE_TG4_OFFSET ||
 829            opcode == SHADER_OPCODE_SAMPLEINFO);
 830 }
 831
 832 bool
 833 backend_instruction::is_math() const
 834 {
 835    return (opcode == SHADER_OPCODE_RCP ||
 836            opcode == SHADER_OPCODE_RSQ ||
 837            opcode == SHADER_OPCODE_SQRT ||
 838            opcode == SHADER_OPCODE_EXP2 ||
 839            opcode == SHADER_OPCODE_LOG2 ||
 840            opcode == SHADER_OPCODE_SIN ||
 841            opcode == SHADER_OPCODE_COS ||
 842            opcode == SHADER_OPCODE_INT_QUOTIENT ||
 843            opcode == SHADER_OPCODE_INT_REMAINDER ||
 844            opcode == SHADER_OPCODE_POW);
 845 }
 846
 847 bool
 848 backend_instruction::is_control_flow() const
 849 {
 850    switch (opcode) {
 851    case BRW_OPCODE_DO:
 852    case BRW_OPCODE_WHILE:
 853    case BRW_OPCODE_IF:
 854    case BRW_OPCODE_ELSE:
 855    case BRW_OPCODE_ENDIF:
 856    case BRW_OPCODE_BREAK:
 857    case BRW_OPCODE_CONTINUE:
 858       return true;
 859    default:
 860       return false;
 861    }
 862 }
 863
 864 bool
 865 backend_instruction::can_do_source_mods() const
 866 {
 867    switch (opcode) {
 868    case BRW_OPCODE_ADDC:
 869    case BRW_OPCODE_BFE:
 870    case BRW_OPCODE_BFI1:
 871    case BRW_OPCODE_BFI2:
 872    case BRW_OPCODE_BFREV:
 873    case BRW_OPCODE_CBIT:
 874    case BRW_OPCODE_FBH:
 875    case BRW_OPCODE_FBL:
 876    case BRW_OPCODE_SUBB:
 877    case SHADER_OPCODE_BROADCAST:
 878    case SHADER_OPCODE_CLUSTER_BROADCAST:
 879    case SHADER_OPCODE_MOV_INDIRECT:
 880       return false;
 881    default:
 882       return true;
 883    }
 884 }
 885
 886 bool
 887 backend_instruction::can_do_saturate() const
 888 {
 889    switch (opcode) {
 890    case BRW_OPCODE_ADD:
 891    case BRW_OPCODE_ASR:
 892    case BRW_OPCODE_AVG:
 893    case BRW_OPCODE_DP2:
 894    case BRW_OPCODE_DP3:
 895    case BRW_OPCODE_DP4:
 896    case BRW_OPCODE_DPH:
 897    case BRW_OPCODE_F16TO32:
 898    case BRW_OPCODE_F32TO16:
 899    case BRW_OPCODE_LINE:
 900    case BRW_OPCODE_LRP:
 901    case BRW_OPCODE_MAC:
 902    case BRW_OPCODE_MAD:
 903    case BRW_OPCODE_MATH:
 904    case BRW_OPCODE_MOV:
 905    case BRW_OPCODE_MUL:
 906    case SHADER_OPCODE_MULH:
 907    case BRW_OPCODE_PLN:
 908    case BRW_OPCODE_RNDD:
 909    case BRW_OPCODE_RNDE:
 910    case BRW_OPCODE_RNDU:
 911    case BRW_OPCODE_RNDZ:
 912    case BRW_OPCODE_SEL:
 913    case BRW_OPCODE_SHL:
 914    case BRW_OPCODE_SHR:
 915    case FS_OPCODE_LINTERP:
 916    case SHADER_OPCODE_COS:
 917    case SHADER_OPCODE_EXP2:
 918    case SHADER_OPCODE_LOG2:
 919    case SHADER_OPCODE_POW:
 920    case SHADER_OPCODE_RCP:
 921    case SHADER_OPCODE_RSQ:
 922    case SHADER_OPCODE_SIN:
 923    case SHADER_OPCODE_SQRT:
 924       return true;
 925    default:
 926       return false;
 927    }
 928 }
 929
 930 bool
 931 backend_instruction::can_do_cmod() const
 932 {
 933    switch (opcode) {
 934    case BRW_OPCODE_ADD:
 935    case BRW_OPCODE_ADDC:
 936    case BRW_OPCODE_AND:
 937    case BRW_OPCODE_ASR:
 938    case BRW_OPCODE_AVG:
 939    case BRW_OPCODE_CMP:
 940    case BRW_OPCODE_CMPN:
 941    case BRW_OPCODE_DP2:
 942    case BRW_OPCODE_DP3:
 943    case BRW_OPCODE_DP4:
 944    case BRW_OPCODE_DPH:
 945    case BRW_OPCODE_F16TO32:
 946    case BRW_OPCODE_F32TO16:
 947    case BRW_OPCODE_FRC:
 948    case BRW_OPCODE_LINE:
 949    case BRW_OPCODE_LRP:
 950    case BRW_OPCODE_LZD:
 951    case BRW_OPCODE_MAC:
 952    case BRW_OPCODE_MACH:
 953    case BRW_OPCODE_MAD:
 954    case BRW_OPCODE_MOV:
 955    case BRW_OPCODE_MUL:
 956    case BRW_OPCODE_NOT:
 957    case BRW_OPCODE_OR:
 958    case BRW_OPCODE_PLN:
 959    case BRW_OPCODE_RNDD:
 960    case BRW_OPCODE_RNDE:
 961    case BRW_OPCODE_RNDU:
 962    case BRW_OPCODE_RNDZ:
 963    case BRW_OPCODE_SAD2:
 964    case BRW_OPCODE_SADA2:
 965    case BRW_OPCODE_SHL:
 966    case BRW_OPCODE_SHR:
 967    case BRW_OPCODE_SUBB:
 968    case BRW_OPCODE_XOR:
 969    case FS_OPCODE_LINTERP:
 970       return true;
 971    default:
 972       return false;
 973    }
 974 }
 975
 976 bool
 977 backend_instruction::reads_accumulator_implicitly() const
 978 {
 979    switch (opcode) {
 980    case BRW_OPCODE_MAC:
 981    case BRW_OPCODE_MACH:
 982    case BRW_OPCODE_SADA2:
 983       return true;
 984    default:
 985       return false;
 986    }
 987 }
 988
 989 bool
 990 backend_instruction::writes_accumulator_implicitly(const struct gen_device_info *devinfo) const
 991 {
 992    return writes_accumulator ||
 993           (devinfo->gen < 6 &&
 994            ((opcode >= BRW_OPCODE_ADD && opcode < BRW_OPCODE_NOP) ||
 995             (opcode >= FS_OPCODE_DDX_COARSE && opcode <= FS_OPCODE_LINTERP))) ||
 996           (opcode == FS_OPCODE_LINTERP &&
 997            (!devinfo->has_pln || devinfo->gen <= 6));
 998 }
 999
1000 bool
1001 backend_instruction::has_side_effects() const
1002 {
1003    switch (opcode) {
1004    case SHADER_OPCODE_UNTYPED_ATOMIC:
1005    case SHADER_OPCODE_UNTYPED_ATOMIC_LOGICAL:
1006    case SHADER_OPCODE_UNTYPED_ATOMIC_FLOAT:
1007    case SHADER_OPCODE_UNTYPED_ATOMIC_FLOAT_LOGICAL:
1008    case SHADER_OPCODE_GEN4_SCRATCH_WRITE:
1009    case SHADER_OPCODE_UNTYPED_SURFACE_WRITE:
1010    case SHADER_OPCODE_UNTYPED_SURFACE_WRITE_LOGICAL:
1011    case SHADER_OPCODE_BYTE_SCATTERED_WRITE:
1012    case SHADER_OPCODE_BYTE_SCATTERED_WRITE_LOGICAL:
1013    case SHADER_OPCODE_TYPED_ATOMIC:
1014    case SHADER_OPCODE_TYPED_ATOMIC_LOGICAL:
1015    case SHADER_OPCODE_TYPED_SURFACE_WRITE:
1016    case SHADER_OPCODE_TYPED_SURFACE_WRITE_LOGICAL:
1017    case SHADER_OPCODE_MEMORY_FENCE:
1018    case SHADER_OPCODE_INTERLOCK:
1019    case SHADER_OPCODE_URB_WRITE_SIMD8:
1020    case SHADER_OPCODE_URB_WRITE_SIMD8_PER_SLOT:
1021    case SHADER_OPCODE_URB_WRITE_SIMD8_MASKED:
1022    case SHADER_OPCODE_URB_WRITE_SIMD8_MASKED_PER_SLOT:
1023    case FS_OPCODE_FB_WRITE:
1024    case FS_OPCODE_FB_WRITE_LOGICAL:
1025    case FS_OPCODE_REP_FB_WRITE:
1026    case SHADER_OPCODE_BARRIER:
1027    case TCS_OPCODE_URB_WRITE:
1028    case TCS_OPCODE_RELEASE_INPUT:
1029    case SHADER_OPCODE_RND_MODE:
1030       return true;
1031    default:
1032       return eot;
1033    }
1034 }
1035
1036 bool
1037 backend_instruction::is_volatile() const
1038 {
1039    switch (opcode) {
1040    case SHADER_OPCODE_UNTYPED_SURFACE_READ:
1041    case SHADER_OPCODE_UNTYPED_SURFACE_READ_LOGICAL:
1042    case SHADER_OPCODE_TYPED_SURFACE_READ:
1043    case SHADER_OPCODE_TYPED_SURFACE_READ_LOGICAL:
1044    case SHADER_OPCODE_BYTE_SCATTERED_READ:
1045    case SHADER_OPCODE_BYTE_SCATTERED_READ_LOGICAL:
1046    case SHADER_OPCODE_URB_READ_SIMD8:
1047    case SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT:
1048    case VEC4_OPCODE_URB_READ:
1049       return true;
1050    default:
1051       return false;
1052    }
1053 }
1054
1055 #ifndef NDEBUG
1056 static bool
1057 inst_is_in_block(const bblock_t *block, const backend_instruction *inst)
1058 {
1059    bool found = false;
1060    foreach_inst_in_block (backend_instruction, i, block) {
1061       if (inst == i) {
1062          found = true;
1063       }
1064    }
1065    return found;
1066 }
1067 #endif
1068
1069 static void
1070 adjust_later_block_ips(bblock_t *start_block, int ip_adjustment)
1071 {
1072    for (bblock_t *block_iter = start_block->next();
1073         block_iter;
1074         block_iter = block_iter->next()) {
1075       block_iter->start_ip += ip_adjustment;
1076       block_iter->end_ip += ip_adjustment;
1077    }
1078 }
1079
1080 void
1081 backend_instruction::insert_after(bblock_t *block, backend_instruction *inst)
1082 {
1083    assert(this != inst);
1084
1085    if (!this->is_head_sentinel())
1086       assert(inst_is_in_block(block, this) || !"Instruction not in block");
1087
1088    block->end_ip++;
1089
1090    adjust_later_block_ips(block, 1);
1091
1092    exec_node::insert_after(inst);
1093 }
1094
1095 void
1096 backend_instruction::insert_before(bblock_t *block, backend_instruction *inst)
1097 {
1098    assert(this != inst);
1099
1100    if (!this->is_tail_sentinel())
1101       assert(inst_is_in_block(block, this) || !"Instruction not in block");
1102
1103    block->end_ip++;
1104
1105    adjust_later_block_ips(block, 1);
1106
1107    exec_node::insert_before(inst);
1108 }
1109
1110 void
1111 backend_instruction::insert_before(bblock_t *block, exec_list *list)
1112 {
1113    assert(inst_is_in_block(block, this) || !"Instruction not in block");
1114
1115    unsigned num_inst = list->length();
1116
1117    block->end_ip += num_inst;
1118
1119    adjust_later_block_ips(block, num_inst);
1120
1121    exec_node::insert_before(list);
1122 }
1123
1124 void
1125 backend_instruction::remove(bblock_t *block)
1126 {
1127    assert(inst_is_in_block(block, this) || !"Instruction not in block");
1128
1129    adjust_later_block_ips(block, -1);
1130
1131    if (block->start_ip == block->end_ip) {
1132       block->cfg->remove_block(block);
1133    } else {
1134       block->end_ip--;
1135    }
1136
1137    exec_node::remove();
1138 }
1139
1140 void
1141 backend_shader::dump_instructions()
1142 {
1143    dump_instructions(NULL);
1144 }
1145
1146 void
1147 backend_shader::dump_instructions(const char *name)
1148 {
1149    FILE *file = stderr;
1150    if (name && geteuid() != 0) {
1151       file = fopen(name, "w");
1152       if (!file)
1153          file = stderr;
1154    }
1155
1156    if (cfg) {
1157       int ip = 0;
1158       foreach_block_and_inst(block, backend_instruction, inst, cfg) {
1159          if (!unlikely(INTEL_DEBUG & DEBUG_OPTIMIZER))
1160             fprintf(file, "%4d: ", ip++);
1161          dump_instruction(inst, file);
1162       }
1163    } else {
1164       int ip = 0;
1165       foreach_in_list(backend_instruction, inst, &instructions) {
1166          if (!unlikely(INTEL_DEBUG & DEBUG_OPTIMIZER))
1167             fprintf(file, "%4d: ", ip++);
1168          dump_instruction(inst, file);
1169       }
1170    }
1171
1172    if (file != stderr) {
1173       fclose(file);
1174    }
1175 }
1176
1177 void
1178 backend_shader::calculate_cfg()
1179 {
1180    if (this->cfg)
1181       return;
1182    cfg = new(mem_ctx) cfg_t(&this->instructions);
1183 }
1184
1185 extern "C" const unsigned *
1186 brw_compile_tes(const struct brw_compiler *compiler,
1187                 void *log_data,
1188                 void *mem_ctx,
1189                 const struct brw_tes_prog_key *key,
1190                 const struct brw_vue_map *input_vue_map,
1191                 struct brw_tes_prog_data *prog_data,
1192                 const nir_shader *src_shader,
1193                 struct gl_program *prog,
1194                 int shader_time_index,
1195                 char **error_str)
1196 {
1197    const struct gen_device_info *devinfo = compiler->devinfo;
1198    const bool is_scalar = compiler->scalar_stage[MESA_SHADER_TESS_EVAL];
1199    const unsigned *assembly;
1200
1201    nir_shader *nir = nir_shader_clone(mem_ctx, src_shader);
1202    nir->info.inputs_read = key->inputs_read;
1203    nir->info.patch_inputs_read = key->patch_inputs_read;
1204
1205    nir = brw_nir_apply_sampler_key(nir, compiler, &key->tex, is_scalar);
1206    brw_nir_lower_tes_inputs(nir, input_vue_map);
1207    brw_nir_lower_vue_outputs(nir);
1208    nir = brw_postprocess_nir(nir, compiler, is_scalar);
1209
1210    brw_compute_vue_map(devinfo, &prog_data->base.vue_map,
1211                        nir->info.outputs_written,
1212                        nir->info.separate_shader);
1213
1214    unsigned output_size_bytes = prog_data->base.vue_map.num_slots * 4 * 4;
1215
1216    assert(output_size_bytes >= 1);
1217    if (output_size_bytes > GEN7_MAX_DS_URB_ENTRY_SIZE_BYTES) {
1218       if (error_str)
1219          *error_str = ralloc_strdup(mem_ctx, "DS outputs exceed maximum size");
1220       return NULL;
1221    }
1222
1223    prog_data->base.clip_distance_mask =
1224       ((1 << nir->info.clip_distance_array_size) - 1);
1225    prog_data->base.cull_distance_mask =
1226       ((1 << nir->info.cull_distance_array_size) - 1) <<
1227       nir->info.clip_distance_array_size;
1228
1229    /* URB entry sizes are stored as a multiple of 64 bytes. */
1230    prog_data->base.urb_entry_size = ALIGN(output_size_bytes, 64) / 64;
1231
1232    /* On Cannonlake software shall not program an allocation size that
1233     * specifies a size that is a multiple of 3 64B (512-bit) cachelines.
1234     */
1235    if (devinfo->gen == 10 &&
1236        prog_data->base.urb_entry_size % 3 == 0)
1237       prog_data->base.urb_entry_size++;
1238
1239    prog_data->base.urb_read_length = 0;
1240
1241    STATIC_ASSERT(BRW_TESS_PARTITIONING_INTEGER == TESS_SPACING_EQUAL - 1);
1242    STATIC_ASSERT(BRW_TESS_PARTITIONING_ODD_FRACTIONAL ==
1243                  TESS_SPACING_FRACTIONAL_ODD - 1);
1244    STATIC_ASSERT(BRW_TESS_PARTITIONING_EVEN_FRACTIONAL ==
1245                  TESS_SPACING_FRACTIONAL_EVEN - 1);
1246
1247    prog_data->partitioning =
1248       (enum brw_tess_partitioning) (nir->info.tess.spacing - 1);
1249
1250    switch (nir->info.tess.primitive_mode) {
1251    case GL_QUADS:
1252       prog_data->domain = BRW_TESS_DOMAIN_QUAD;
1253       break;
1254    case GL_TRIANGLES:
1255       prog_data->domain = BRW_TESS_DOMAIN_TRI;
1256       break;
1257    case GL_ISOLINES:
1258       prog_data->domain = BRW_TESS_DOMAIN_ISOLINE;
1259       break;
1260    default:
1261       unreachable("invalid domain shader primitive mode");
1262    }
1263
1264    if (nir->info.tess.point_mode) {
1265       prog_data->output_topology = BRW_TESS_OUTPUT_TOPOLOGY_POINT;
1266    } else if (nir->info.tess.primitive_mode == GL_ISOLINES) {
1267       prog_data->output_topology = BRW_TESS_OUTPUT_TOPOLOGY_LINE;
1268    } else {
1269       /* Hardware winding order is backwards from OpenGL */
1270       prog_data->output_topology =
1271          nir->info.tess.ccw ? BRW_TESS_OUTPUT_TOPOLOGY_TRI_CW
1272                              : BRW_TESS_OUTPUT_TOPOLOGY_TRI_CCW;
1273    }
1274
1275    if (unlikely(INTEL_DEBUG & DEBUG_TES)) {
1276       fprintf(stderr, "TES Input ");
1277       brw_print_vue_map(stderr, input_vue_map);
1278       fprintf(stderr, "TES Output ");
1279       brw_print_vue_map(stderr, &prog_data->base.vue_map);
1280    }
1281
1282    if (is_scalar) {
1283       fs_visitor v(compiler, log_data, mem_ctx, (void *) key,
1284                    &prog_data->base.base, NULL, nir, 8,
1285                    shader_time_index, input_vue_map);
1286       if (!v.run_tes()) {
1287          if (error_str)
1288             *error_str = ralloc_strdup(mem_ctx, v.fail_msg);
1289          return NULL;
1290       }
1291
1292       prog_data->base.base.dispatch_grf_start_reg = v.payload.num_regs;
1293       prog_data->base.dispatch_mode = DISPATCH_MODE_SIMD8;
1294
1295       fs_generator g(compiler, log_data, mem_ctx,
1296                      &prog_data->base.base, v.promoted_constants, false,
1297                      MESA_SHADER_TESS_EVAL);
1298       if (unlikely(INTEL_DEBUG & DEBUG_TES)) {
1299          g.enable_debug(ralloc_asprintf(mem_ctx,
1300                                         "%s tessellation evaluation shader %s",
1301                                         nir->info.label ? nir->info.label
1302                                                         : "unnamed",
1303                                         nir->info.name));
1304       }
1305
1306       g.generate_code(v.cfg, 8);
1307
1308       assembly = g.get_assembly();
1309    } else {
1310       brw::vec4_tes_visitor v(compiler, log_data, key, prog_data,
1311                               nir, mem_ctx, shader_time_index);
1312       if (!v.run()) {
1313          if (error_str)
1314             *error_str = ralloc_strdup(mem_ctx, v.fail_msg);
1315          return NULL;
1316       }
1317
1318       if (unlikely(INTEL_DEBUG & DEBUG_TES))
1319          v.dump_instructions();
1320
1321       assembly = brw_vec4_generate_assembly(compiler, log_data, mem_ctx, nir,
1322                                             &prog_data->base, v.cfg);
1323    }
1324
1325    return assembly;
1326 }