2 * Copyright © 2010 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
28 #include "brw_vec4_tes.h"
29 #include "dev/gen_debug.h"
30 #include "main/uniforms.h"
31 #include "util/macros.h"
34 brw_type_for_base_type(const struct glsl_type
*type
)
36 switch (type
->base_type
) {
37 case GLSL_TYPE_FLOAT16
:
38 return BRW_REGISTER_TYPE_HF
;
40 return BRW_REGISTER_TYPE_F
;
43 case GLSL_TYPE_SUBROUTINE
:
44 return BRW_REGISTER_TYPE_D
;
46 return BRW_REGISTER_TYPE_W
;
48 return BRW_REGISTER_TYPE_B
;
50 return BRW_REGISTER_TYPE_UD
;
51 case GLSL_TYPE_UINT16
:
52 return BRW_REGISTER_TYPE_UW
;
54 return BRW_REGISTER_TYPE_UB
;
56 return brw_type_for_base_type(type
->fields
.array
);
57 case GLSL_TYPE_STRUCT
:
58 case GLSL_TYPE_INTERFACE
:
59 case GLSL_TYPE_SAMPLER
:
60 case GLSL_TYPE_ATOMIC_UINT
:
61 /* These should be overridden with the type of the member when
62 * dereferenced into. BRW_REGISTER_TYPE_UD seems like a likely
63 * way to trip up if we don't.
65 return BRW_REGISTER_TYPE_UD
;
67 return BRW_REGISTER_TYPE_UD
;
68 case GLSL_TYPE_DOUBLE
:
69 return BRW_REGISTER_TYPE_DF
;
70 case GLSL_TYPE_UINT64
:
71 return BRW_REGISTER_TYPE_UQ
;
73 return BRW_REGISTER_TYPE_Q
;
76 case GLSL_TYPE_FUNCTION
:
77 unreachable("not reached");
80 return BRW_REGISTER_TYPE_F
;
83 enum brw_conditional_mod
84 brw_conditional_for_comparison(unsigned int op
)
88 return BRW_CONDITIONAL_L
;
90 return BRW_CONDITIONAL_GE
;
92 case ir_binop_all_equal
: /* same as equal for scalars */
93 return BRW_CONDITIONAL_Z
;
95 case ir_binop_any_nequal
: /* same as nequal for scalars */
96 return BRW_CONDITIONAL_NZ
;
98 unreachable("not reached: bad operation for comparison");
103 brw_math_function(enum opcode op
)
106 case SHADER_OPCODE_RCP
:
107 return BRW_MATH_FUNCTION_INV
;
108 case SHADER_OPCODE_RSQ
:
109 return BRW_MATH_FUNCTION_RSQ
;
110 case SHADER_OPCODE_SQRT
:
111 return BRW_MATH_FUNCTION_SQRT
;
112 case SHADER_OPCODE_EXP2
:
113 return BRW_MATH_FUNCTION_EXP
;
114 case SHADER_OPCODE_LOG2
:
115 return BRW_MATH_FUNCTION_LOG
;
116 case SHADER_OPCODE_POW
:
117 return BRW_MATH_FUNCTION_POW
;
118 case SHADER_OPCODE_SIN
:
119 return BRW_MATH_FUNCTION_SIN
;
120 case SHADER_OPCODE_COS
:
121 return BRW_MATH_FUNCTION_COS
;
122 case SHADER_OPCODE_INT_QUOTIENT
:
123 return BRW_MATH_FUNCTION_INT_DIV_QUOTIENT
;
124 case SHADER_OPCODE_INT_REMAINDER
:
125 return BRW_MATH_FUNCTION_INT_DIV_REMAINDER
;
127 unreachable("not reached: unknown math function");
132 brw_texture_offset(const nir_tex_instr
*tex
, unsigned src
,
133 uint32_t *offset_bits_out
)
135 if (!nir_src_is_const(tex
->src
[src
].src
))
138 const unsigned num_components
= nir_tex_instr_src_size(tex
, src
);
140 /* Combine all three offsets into a single unsigned dword:
142 * bits 11:8 - U Offset (X component)
143 * bits 7:4 - V Offset (Y component)
144 * bits 3:0 - R Offset (Z component)
146 uint32_t offset_bits
= 0;
147 for (unsigned i
= 0; i
< num_components
; i
++) {
148 int offset
= nir_src_comp_as_int(tex
->src
[src
].src
, i
);
150 /* offset out of bounds; caller will handle it. */
151 if (offset
> 7 || offset
< -8)
154 const unsigned shift
= 4 * (2 - i
);
155 offset_bits
|= (offset
<< shift
) & (0xF << shift
);
158 *offset_bits_out
= offset_bits
;
164 brw_instruction_name(const struct gen_device_info
*devinfo
, enum opcode op
)
167 case BRW_OPCODE_ILLEGAL
... BRW_OPCODE_NOP
:
168 /* The DO instruction doesn't exist on Gen6+, but we use it to mark the
169 * start of a loop in the IR.
171 if (devinfo
->gen
>= 6 && op
== BRW_OPCODE_DO
)
174 /* The following conversion opcodes doesn't exist on Gen8+, but we use
175 * then to mark that we want to do the conversion.
177 if (devinfo
->gen
> 7 && op
== BRW_OPCODE_F32TO16
)
180 if (devinfo
->gen
> 7 && op
== BRW_OPCODE_F16TO32
)
183 assert(brw_opcode_desc(devinfo
, op
)->name
);
184 return brw_opcode_desc(devinfo
, op
)->name
;
185 case FS_OPCODE_FB_WRITE
:
187 case FS_OPCODE_FB_WRITE_LOGICAL
:
188 return "fb_write_logical";
189 case FS_OPCODE_REP_FB_WRITE
:
190 return "rep_fb_write";
191 case FS_OPCODE_FB_READ
:
193 case FS_OPCODE_FB_READ_LOGICAL
:
194 return "fb_read_logical";
196 case SHADER_OPCODE_RCP
:
198 case SHADER_OPCODE_RSQ
:
200 case SHADER_OPCODE_SQRT
:
202 case SHADER_OPCODE_EXP2
:
204 case SHADER_OPCODE_LOG2
:
206 case SHADER_OPCODE_POW
:
208 case SHADER_OPCODE_INT_QUOTIENT
:
210 case SHADER_OPCODE_INT_REMAINDER
:
212 case SHADER_OPCODE_SIN
:
214 case SHADER_OPCODE_COS
:
217 case SHADER_OPCODE_SEND
:
220 case SHADER_OPCODE_TEX
:
222 case SHADER_OPCODE_TEX_LOGICAL
:
223 return "tex_logical";
224 case SHADER_OPCODE_TXD
:
226 case SHADER_OPCODE_TXD_LOGICAL
:
227 return "txd_logical";
228 case SHADER_OPCODE_TXF
:
230 case SHADER_OPCODE_TXF_LOGICAL
:
231 return "txf_logical";
232 case SHADER_OPCODE_TXF_LZ
:
234 case SHADER_OPCODE_TXL
:
236 case SHADER_OPCODE_TXL_LOGICAL
:
237 return "txl_logical";
238 case SHADER_OPCODE_TXL_LZ
:
240 case SHADER_OPCODE_TXS
:
242 case SHADER_OPCODE_TXS_LOGICAL
:
243 return "txs_logical";
246 case FS_OPCODE_TXB_LOGICAL
:
247 return "txb_logical";
248 case SHADER_OPCODE_TXF_CMS
:
250 case SHADER_OPCODE_TXF_CMS_LOGICAL
:
251 return "txf_cms_logical";
252 case SHADER_OPCODE_TXF_CMS_W
:
254 case SHADER_OPCODE_TXF_CMS_W_LOGICAL
:
255 return "txf_cms_w_logical";
256 case SHADER_OPCODE_TXF_UMS
:
258 case SHADER_OPCODE_TXF_UMS_LOGICAL
:
259 return "txf_ums_logical";
260 case SHADER_OPCODE_TXF_MCS
:
262 case SHADER_OPCODE_TXF_MCS_LOGICAL
:
263 return "txf_mcs_logical";
264 case SHADER_OPCODE_LOD
:
266 case SHADER_OPCODE_LOD_LOGICAL
:
267 return "lod_logical";
268 case SHADER_OPCODE_TG4
:
270 case SHADER_OPCODE_TG4_LOGICAL
:
271 return "tg4_logical";
272 case SHADER_OPCODE_TG4_OFFSET
:
274 case SHADER_OPCODE_TG4_OFFSET_LOGICAL
:
275 return "tg4_offset_logical";
276 case SHADER_OPCODE_SAMPLEINFO
:
278 case SHADER_OPCODE_SAMPLEINFO_LOGICAL
:
279 return "sampleinfo_logical";
281 case SHADER_OPCODE_IMAGE_SIZE_LOGICAL
:
282 return "image_size_logical";
284 case SHADER_OPCODE_SHADER_TIME_ADD
:
285 return "shader_time_add";
287 case VEC4_OPCODE_UNTYPED_ATOMIC
:
288 return "untyped_atomic";
289 case SHADER_OPCODE_UNTYPED_ATOMIC_LOGICAL
:
290 return "untyped_atomic_logical";
291 case SHADER_OPCODE_UNTYPED_ATOMIC_FLOAT_LOGICAL
:
292 return "untyped_atomic_float_logical";
293 case VEC4_OPCODE_UNTYPED_SURFACE_READ
:
294 return "untyped_surface_read";
295 case SHADER_OPCODE_UNTYPED_SURFACE_READ_LOGICAL
:
296 return "untyped_surface_read_logical";
297 case VEC4_OPCODE_UNTYPED_SURFACE_WRITE
:
298 return "untyped_surface_write";
299 case SHADER_OPCODE_UNTYPED_SURFACE_WRITE_LOGICAL
:
300 return "untyped_surface_write_logical";
301 case SHADER_OPCODE_A64_UNTYPED_READ_LOGICAL
:
302 return "a64_untyped_read_logical";
303 case SHADER_OPCODE_A64_UNTYPED_WRITE_LOGICAL
:
304 return "a64_untyped_write_logical";
305 case SHADER_OPCODE_A64_BYTE_SCATTERED_READ_LOGICAL
:
306 return "a64_byte_scattered_read_logical";
307 case SHADER_OPCODE_A64_BYTE_SCATTERED_WRITE_LOGICAL
:
308 return "a64_byte_scattered_write_logical";
309 case SHADER_OPCODE_A64_UNTYPED_ATOMIC_LOGICAL
:
310 return "a64_untyped_atomic_logical";
311 case SHADER_OPCODE_A64_UNTYPED_ATOMIC_FLOAT_LOGICAL
:
312 return "a64_untyped_atomic_float_logical";
313 case SHADER_OPCODE_TYPED_ATOMIC_LOGICAL
:
314 return "typed_atomic_logical";
315 case SHADER_OPCODE_TYPED_SURFACE_READ_LOGICAL
:
316 return "typed_surface_read_logical";
317 case SHADER_OPCODE_TYPED_SURFACE_WRITE_LOGICAL
:
318 return "typed_surface_write_logical";
319 case SHADER_OPCODE_MEMORY_FENCE
:
320 return "memory_fence";
321 case SHADER_OPCODE_INTERLOCK
:
322 /* For an interlock we actually issue a memory fence via sendc. */
325 case SHADER_OPCODE_BYTE_SCATTERED_READ_LOGICAL
:
326 return "byte_scattered_read_logical";
327 case SHADER_OPCODE_BYTE_SCATTERED_WRITE_LOGICAL
:
328 return "byte_scattered_write_logical";
330 case SHADER_OPCODE_LOAD_PAYLOAD
:
331 return "load_payload";
335 case SHADER_OPCODE_GEN4_SCRATCH_READ
:
336 return "gen4_scratch_read";
337 case SHADER_OPCODE_GEN4_SCRATCH_WRITE
:
338 return "gen4_scratch_write";
339 case SHADER_OPCODE_GEN7_SCRATCH_READ
:
340 return "gen7_scratch_read";
341 case SHADER_OPCODE_URB_WRITE_SIMD8
:
342 return "gen8_urb_write_simd8";
343 case SHADER_OPCODE_URB_WRITE_SIMD8_PER_SLOT
:
344 return "gen8_urb_write_simd8_per_slot";
345 case SHADER_OPCODE_URB_WRITE_SIMD8_MASKED
:
346 return "gen8_urb_write_simd8_masked";
347 case SHADER_OPCODE_URB_WRITE_SIMD8_MASKED_PER_SLOT
:
348 return "gen8_urb_write_simd8_masked_per_slot";
349 case SHADER_OPCODE_URB_READ_SIMD8
:
350 return "urb_read_simd8";
351 case SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT
:
352 return "urb_read_simd8_per_slot";
354 case SHADER_OPCODE_FIND_LIVE_CHANNEL
:
355 return "find_live_channel";
356 case SHADER_OPCODE_BROADCAST
:
358 case SHADER_OPCODE_SHUFFLE
:
360 case SHADER_OPCODE_SEL_EXEC
:
362 case SHADER_OPCODE_QUAD_SWIZZLE
:
363 return "quad_swizzle";
364 case SHADER_OPCODE_CLUSTER_BROADCAST
:
365 return "cluster_broadcast";
367 case SHADER_OPCODE_GET_BUFFER_SIZE
:
368 return "get_buffer_size";
370 case VEC4_OPCODE_MOV_BYTES
:
372 case VEC4_OPCODE_PACK_BYTES
:
374 case VEC4_OPCODE_UNPACK_UNIFORM
:
375 return "unpack_uniform";
376 case VEC4_OPCODE_DOUBLE_TO_F32
:
377 return "double_to_f32";
378 case VEC4_OPCODE_DOUBLE_TO_D32
:
379 return "double_to_d32";
380 case VEC4_OPCODE_DOUBLE_TO_U32
:
381 return "double_to_u32";
382 case VEC4_OPCODE_TO_DOUBLE
:
383 return "single_to_double";
384 case VEC4_OPCODE_PICK_LOW_32BIT
:
385 return "pick_low_32bit";
386 case VEC4_OPCODE_PICK_HIGH_32BIT
:
387 return "pick_high_32bit";
388 case VEC4_OPCODE_SET_LOW_32BIT
:
389 return "set_low_32bit";
390 case VEC4_OPCODE_SET_HIGH_32BIT
:
391 return "set_high_32bit";
393 case FS_OPCODE_DDX_COARSE
:
395 case FS_OPCODE_DDX_FINE
:
397 case FS_OPCODE_DDY_COARSE
:
399 case FS_OPCODE_DDY_FINE
:
402 case FS_OPCODE_LINTERP
:
405 case FS_OPCODE_PIXEL_X
:
407 case FS_OPCODE_PIXEL_Y
:
410 case FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD
:
411 return "uniform_pull_const";
412 case FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD_GEN7
:
413 return "uniform_pull_const_gen7";
414 case FS_OPCODE_VARYING_PULL_CONSTANT_LOAD_GEN4
:
415 return "varying_pull_const_gen4";
416 case FS_OPCODE_VARYING_PULL_CONSTANT_LOAD_LOGICAL
:
417 return "varying_pull_const_logical";
419 case FS_OPCODE_DISCARD_JUMP
:
420 return "discard_jump";
422 case FS_OPCODE_SET_SAMPLE_ID
:
423 return "set_sample_id";
425 case FS_OPCODE_PACK_HALF_2x16_SPLIT
:
426 return "pack_half_2x16_split";
428 case FS_OPCODE_PLACEHOLDER_HALT
:
429 return "placeholder_halt";
431 case FS_OPCODE_INTERPOLATE_AT_SAMPLE
:
432 return "interp_sample";
433 case FS_OPCODE_INTERPOLATE_AT_SHARED_OFFSET
:
434 return "interp_shared_offset";
435 case FS_OPCODE_INTERPOLATE_AT_PER_SLOT_OFFSET
:
436 return "interp_per_slot_offset";
438 case VS_OPCODE_URB_WRITE
:
439 return "vs_urb_write";
440 case VS_OPCODE_PULL_CONSTANT_LOAD
:
441 return "pull_constant_load";
442 case VS_OPCODE_PULL_CONSTANT_LOAD_GEN7
:
443 return "pull_constant_load_gen7";
445 case VS_OPCODE_SET_SIMD4X2_HEADER_GEN9
:
446 return "set_simd4x2_header_gen9";
448 case VS_OPCODE_UNPACK_FLAGS_SIMD4X2
:
449 return "unpack_flags_simd4x2";
451 case GS_OPCODE_URB_WRITE
:
452 return "gs_urb_write";
453 case GS_OPCODE_URB_WRITE_ALLOCATE
:
454 return "gs_urb_write_allocate";
455 case GS_OPCODE_THREAD_END
:
456 return "gs_thread_end";
457 case GS_OPCODE_SET_WRITE_OFFSET
:
458 return "set_write_offset";
459 case GS_OPCODE_SET_VERTEX_COUNT
:
460 return "set_vertex_count";
461 case GS_OPCODE_SET_DWORD_2
:
462 return "set_dword_2";
463 case GS_OPCODE_PREPARE_CHANNEL_MASKS
:
464 return "prepare_channel_masks";
465 case GS_OPCODE_SET_CHANNEL_MASKS
:
466 return "set_channel_masks";
467 case GS_OPCODE_GET_INSTANCE_ID
:
468 return "get_instance_id";
469 case GS_OPCODE_FF_SYNC
:
471 case GS_OPCODE_SET_PRIMITIVE_ID
:
472 return "set_primitive_id";
473 case GS_OPCODE_SVB_WRITE
:
474 return "gs_svb_write";
475 case GS_OPCODE_SVB_SET_DST_INDEX
:
476 return "gs_svb_set_dst_index";
477 case GS_OPCODE_FF_SYNC_SET_PRIMITIVES
:
478 return "gs_ff_sync_set_primitives";
479 case CS_OPCODE_CS_TERMINATE
:
480 return "cs_terminate";
481 case SHADER_OPCODE_BARRIER
:
483 case SHADER_OPCODE_MULH
:
485 case SHADER_OPCODE_MOV_INDIRECT
:
486 return "mov_indirect";
488 case VEC4_OPCODE_URB_READ
:
490 case TCS_OPCODE_GET_INSTANCE_ID
:
491 return "tcs_get_instance_id";
492 case TCS_OPCODE_URB_WRITE
:
493 return "tcs_urb_write";
494 case TCS_OPCODE_SET_INPUT_URB_OFFSETS
:
495 return "tcs_set_input_urb_offsets";
496 case TCS_OPCODE_SET_OUTPUT_URB_OFFSETS
:
497 return "tcs_set_output_urb_offsets";
498 case TCS_OPCODE_GET_PRIMITIVE_ID
:
499 return "tcs_get_primitive_id";
500 case TCS_OPCODE_CREATE_BARRIER_HEADER
:
501 return "tcs_create_barrier_header";
502 case TCS_OPCODE_SRC0_010_IS_ZERO
:
503 return "tcs_src0<0,1,0>_is_zero";
504 case TCS_OPCODE_RELEASE_INPUT
:
505 return "tcs_release_input";
506 case TCS_OPCODE_THREAD_END
:
507 return "tcs_thread_end";
508 case TES_OPCODE_CREATE_INPUT_READ_HEADER
:
509 return "tes_create_input_read_header";
510 case TES_OPCODE_ADD_INDIRECT_URB_OFFSET
:
511 return "tes_add_indirect_urb_offset";
512 case TES_OPCODE_GET_PRIMITIVE_ID
:
513 return "tes_get_primitive_id";
515 case SHADER_OPCODE_RND_MODE
:
519 unreachable("not reached");
523 brw_saturate_immediate(enum brw_reg_type type
, struct brw_reg
*reg
)
530 } imm
, sat_imm
= { 0 };
532 const unsigned size
= type_sz(type
);
534 /* We want to either do a 32-bit or 64-bit data copy, the type is otherwise
535 * irrelevant, so just check the size of the type and copy from/to an
536 * appropriately sized field.
544 case BRW_REGISTER_TYPE_UD
:
545 case BRW_REGISTER_TYPE_D
:
546 case BRW_REGISTER_TYPE_UW
:
547 case BRW_REGISTER_TYPE_W
:
548 case BRW_REGISTER_TYPE_UQ
:
549 case BRW_REGISTER_TYPE_Q
:
552 case BRW_REGISTER_TYPE_F
:
553 sat_imm
.f
= CLAMP(imm
.f
, 0.0f
, 1.0f
);
555 case BRW_REGISTER_TYPE_DF
:
556 sat_imm
.df
= CLAMP(imm
.df
, 0.0, 1.0);
558 case BRW_REGISTER_TYPE_UB
:
559 case BRW_REGISTER_TYPE_B
:
560 unreachable("no UB/B immediates");
561 case BRW_REGISTER_TYPE_V
:
562 case BRW_REGISTER_TYPE_UV
:
563 case BRW_REGISTER_TYPE_VF
:
564 unreachable("unimplemented: saturate vector immediate");
565 case BRW_REGISTER_TYPE_HF
:
566 unreachable("unimplemented: saturate HF immediate");
567 case BRW_REGISTER_TYPE_NF
:
568 unreachable("no NF immediates");
572 if (imm
.ud
!= sat_imm
.ud
) {
573 reg
->ud
= sat_imm
.ud
;
577 if (imm
.df
!= sat_imm
.df
) {
578 reg
->df
= sat_imm
.df
;
586 brw_negate_immediate(enum brw_reg_type type
, struct brw_reg
*reg
)
589 case BRW_REGISTER_TYPE_D
:
590 case BRW_REGISTER_TYPE_UD
:
593 case BRW_REGISTER_TYPE_W
:
594 case BRW_REGISTER_TYPE_UW
: {
595 uint16_t value
= -(int16_t)reg
->ud
;
596 reg
->ud
= value
| (uint32_t)value
<< 16;
599 case BRW_REGISTER_TYPE_F
:
602 case BRW_REGISTER_TYPE_VF
:
603 reg
->ud
^= 0x80808080;
605 case BRW_REGISTER_TYPE_DF
:
608 case BRW_REGISTER_TYPE_UQ
:
609 case BRW_REGISTER_TYPE_Q
:
610 reg
->d64
= -reg
->d64
;
612 case BRW_REGISTER_TYPE_UB
:
613 case BRW_REGISTER_TYPE_B
:
614 unreachable("no UB/B immediates");
615 case BRW_REGISTER_TYPE_UV
:
616 case BRW_REGISTER_TYPE_V
:
617 assert(!"unimplemented: negate UV/V immediate");
618 case BRW_REGISTER_TYPE_HF
:
619 reg
->ud
^= 0x80008000;
621 case BRW_REGISTER_TYPE_NF
:
622 unreachable("no NF immediates");
629 brw_abs_immediate(enum brw_reg_type type
, struct brw_reg
*reg
)
632 case BRW_REGISTER_TYPE_D
:
633 reg
->d
= abs(reg
->d
);
635 case BRW_REGISTER_TYPE_W
: {
636 uint16_t value
= abs((int16_t)reg
->ud
);
637 reg
->ud
= value
| (uint32_t)value
<< 16;
640 case BRW_REGISTER_TYPE_F
:
641 reg
->f
= fabsf(reg
->f
);
643 case BRW_REGISTER_TYPE_DF
:
644 reg
->df
= fabs(reg
->df
);
646 case BRW_REGISTER_TYPE_VF
:
647 reg
->ud
&= ~0x80808080;
649 case BRW_REGISTER_TYPE_Q
:
650 reg
->d64
= imaxabs(reg
->d64
);
652 case BRW_REGISTER_TYPE_UB
:
653 case BRW_REGISTER_TYPE_B
:
654 unreachable("no UB/B immediates");
655 case BRW_REGISTER_TYPE_UQ
:
656 case BRW_REGISTER_TYPE_UD
:
657 case BRW_REGISTER_TYPE_UW
:
658 case BRW_REGISTER_TYPE_UV
:
659 /* Presumably the absolute value modifier on an unsigned source is a
660 * nop, but it would be nice to confirm.
662 assert(!"unimplemented: abs unsigned immediate");
663 case BRW_REGISTER_TYPE_V
:
664 assert(!"unimplemented: abs V immediate");
665 case BRW_REGISTER_TYPE_HF
:
666 reg
->ud
&= ~0x80008000;
668 case BRW_REGISTER_TYPE_NF
:
669 unreachable("no NF immediates");
675 backend_shader::backend_shader(const struct brw_compiler
*compiler
,
678 const nir_shader
*shader
,
679 struct brw_stage_prog_data
*stage_prog_data
)
680 : compiler(compiler
),
682 devinfo(compiler
->devinfo
),
684 stage_prog_data(stage_prog_data
),
687 stage(shader
->info
.stage
)
689 debug_enabled
= INTEL_DEBUG
& intel_debug_flag_for_shader_stage(stage
);
690 stage_name
= _mesa_shader_stage_to_string(stage
);
691 stage_abbrev
= _mesa_shader_stage_to_abbrev(stage
);
694 backend_shader::~backend_shader()
699 backend_reg::equals(const backend_reg
&r
) const
701 return brw_regs_equal(this, &r
) && offset
== r
.offset
;
705 backend_reg::negative_equals(const backend_reg
&r
) const
707 return brw_regs_negative_equal(this, &r
) && offset
== r
.offset
;
711 backend_reg::is_zero() const
716 assert(type_sz(type
) > 1);
719 case BRW_REGISTER_TYPE_HF
:
720 assert((d
& 0xffff) == ((d
>> 16) & 0xffff));
721 return (d
& 0xffff) == 0 || (d
& 0xffff) == 0x8000;
722 case BRW_REGISTER_TYPE_F
:
724 case BRW_REGISTER_TYPE_DF
:
726 case BRW_REGISTER_TYPE_W
:
727 case BRW_REGISTER_TYPE_UW
:
728 assert((d
& 0xffff) == ((d
>> 16) & 0xffff));
729 return (d
& 0xffff) == 0;
730 case BRW_REGISTER_TYPE_D
:
731 case BRW_REGISTER_TYPE_UD
:
733 case BRW_REGISTER_TYPE_UQ
:
734 case BRW_REGISTER_TYPE_Q
:
742 backend_reg::is_one() const
747 assert(type_sz(type
) > 1);
750 case BRW_REGISTER_TYPE_HF
:
751 assert((d
& 0xffff) == ((d
>> 16) & 0xffff));
752 return (d
& 0xffff) == 0x3c00;
753 case BRW_REGISTER_TYPE_F
:
755 case BRW_REGISTER_TYPE_DF
:
757 case BRW_REGISTER_TYPE_W
:
758 case BRW_REGISTER_TYPE_UW
:
759 assert((d
& 0xffff) == ((d
>> 16) & 0xffff));
760 return (d
& 0xffff) == 1;
761 case BRW_REGISTER_TYPE_D
:
762 case BRW_REGISTER_TYPE_UD
:
764 case BRW_REGISTER_TYPE_UQ
:
765 case BRW_REGISTER_TYPE_Q
:
773 backend_reg::is_negative_one() const
778 assert(type_sz(type
) > 1);
781 case BRW_REGISTER_TYPE_HF
:
782 assert((d
& 0xffff) == ((d
>> 16) & 0xffff));
783 return (d
& 0xffff) == 0xbc00;
784 case BRW_REGISTER_TYPE_F
:
786 case BRW_REGISTER_TYPE_DF
:
788 case BRW_REGISTER_TYPE_W
:
789 assert((d
& 0xffff) == ((d
>> 16) & 0xffff));
790 return (d
& 0xffff) == 0xffff;
791 case BRW_REGISTER_TYPE_D
:
793 case BRW_REGISTER_TYPE_Q
:
801 backend_reg::is_null() const
803 return file
== ARF
&& nr
== BRW_ARF_NULL
;
808 backend_reg::is_accumulator() const
810 return file
== ARF
&& nr
== BRW_ARF_ACCUMULATOR
;
814 backend_instruction::is_commutative() const
822 case SHADER_OPCODE_MULH
:
825 /* MIN and MAX are commutative. */
826 if (conditional_mod
== BRW_CONDITIONAL_GE
||
827 conditional_mod
== BRW_CONDITIONAL_L
) {
837 backend_instruction::is_3src(const struct gen_device_info
*devinfo
) const
839 return ::is_3src(devinfo
, opcode
);
843 backend_instruction::is_tex() const
845 return (opcode
== SHADER_OPCODE_TEX
||
846 opcode
== FS_OPCODE_TXB
||
847 opcode
== SHADER_OPCODE_TXD
||
848 opcode
== SHADER_OPCODE_TXF
||
849 opcode
== SHADER_OPCODE_TXF_LZ
||
850 opcode
== SHADER_OPCODE_TXF_CMS
||
851 opcode
== SHADER_OPCODE_TXF_CMS_W
||
852 opcode
== SHADER_OPCODE_TXF_UMS
||
853 opcode
== SHADER_OPCODE_TXF_MCS
||
854 opcode
== SHADER_OPCODE_TXL
||
855 opcode
== SHADER_OPCODE_TXL_LZ
||
856 opcode
== SHADER_OPCODE_TXS
||
857 opcode
== SHADER_OPCODE_LOD
||
858 opcode
== SHADER_OPCODE_TG4
||
859 opcode
== SHADER_OPCODE_TG4_OFFSET
||
860 opcode
== SHADER_OPCODE_SAMPLEINFO
);
864 backend_instruction::is_math() const
866 return (opcode
== SHADER_OPCODE_RCP
||
867 opcode
== SHADER_OPCODE_RSQ
||
868 opcode
== SHADER_OPCODE_SQRT
||
869 opcode
== SHADER_OPCODE_EXP2
||
870 opcode
== SHADER_OPCODE_LOG2
||
871 opcode
== SHADER_OPCODE_SIN
||
872 opcode
== SHADER_OPCODE_COS
||
873 opcode
== SHADER_OPCODE_INT_QUOTIENT
||
874 opcode
== SHADER_OPCODE_INT_REMAINDER
||
875 opcode
== SHADER_OPCODE_POW
);
879 backend_instruction::is_control_flow() const
883 case BRW_OPCODE_WHILE
:
885 case BRW_OPCODE_ELSE
:
886 case BRW_OPCODE_ENDIF
:
887 case BRW_OPCODE_BREAK
:
888 case BRW_OPCODE_CONTINUE
:
896 backend_instruction::can_do_source_mods() const
899 case BRW_OPCODE_ADDC
:
901 case BRW_OPCODE_BFI1
:
902 case BRW_OPCODE_BFI2
:
903 case BRW_OPCODE_BFREV
:
904 case BRW_OPCODE_CBIT
:
907 case BRW_OPCODE_SUBB
:
908 case SHADER_OPCODE_BROADCAST
:
909 case SHADER_OPCODE_CLUSTER_BROADCAST
:
910 case SHADER_OPCODE_MOV_INDIRECT
:
918 backend_instruction::can_do_saturate() const
928 case BRW_OPCODE_F16TO32
:
929 case BRW_OPCODE_F32TO16
:
930 case BRW_OPCODE_LINE
:
934 case BRW_OPCODE_MATH
:
937 case SHADER_OPCODE_MULH
:
939 case BRW_OPCODE_RNDD
:
940 case BRW_OPCODE_RNDE
:
941 case BRW_OPCODE_RNDU
:
942 case BRW_OPCODE_RNDZ
:
946 case FS_OPCODE_LINTERP
:
947 case SHADER_OPCODE_COS
:
948 case SHADER_OPCODE_EXP2
:
949 case SHADER_OPCODE_LOG2
:
950 case SHADER_OPCODE_POW
:
951 case SHADER_OPCODE_RCP
:
952 case SHADER_OPCODE_RSQ
:
953 case SHADER_OPCODE_SIN
:
954 case SHADER_OPCODE_SQRT
:
962 backend_instruction::can_do_cmod() const
966 case BRW_OPCODE_ADDC
:
971 case BRW_OPCODE_CMPN
:
976 case BRW_OPCODE_F16TO32
:
977 case BRW_OPCODE_F32TO16
:
979 case BRW_OPCODE_LINE
:
983 case BRW_OPCODE_MACH
:
990 case BRW_OPCODE_RNDD
:
991 case BRW_OPCODE_RNDE
:
992 case BRW_OPCODE_RNDU
:
993 case BRW_OPCODE_RNDZ
:
994 case BRW_OPCODE_SAD2
:
995 case BRW_OPCODE_SADA2
:
998 case BRW_OPCODE_SUBB
:
1000 case FS_OPCODE_LINTERP
:
1008 backend_instruction::reads_accumulator_implicitly() const
1011 case BRW_OPCODE_MAC
:
1012 case BRW_OPCODE_MACH
:
1013 case BRW_OPCODE_SADA2
:
1021 backend_instruction::writes_accumulator_implicitly(const struct gen_device_info
*devinfo
) const
1023 return writes_accumulator
||
1024 (devinfo
->gen
< 6 &&
1025 ((opcode
>= BRW_OPCODE_ADD
&& opcode
< BRW_OPCODE_NOP
) ||
1026 (opcode
>= FS_OPCODE_DDX_COARSE
&& opcode
<= FS_OPCODE_LINTERP
))) ||
1027 (opcode
== FS_OPCODE_LINTERP
&&
1028 (!devinfo
->has_pln
|| devinfo
->gen
<= 6));
1032 backend_instruction::has_side_effects() const
1035 case SHADER_OPCODE_SEND
:
1036 return send_has_side_effects
;
1038 case VEC4_OPCODE_UNTYPED_ATOMIC
:
1039 case SHADER_OPCODE_UNTYPED_ATOMIC_LOGICAL
:
1040 case SHADER_OPCODE_UNTYPED_ATOMIC_FLOAT_LOGICAL
:
1041 case SHADER_OPCODE_GEN4_SCRATCH_WRITE
:
1042 case VEC4_OPCODE_UNTYPED_SURFACE_WRITE
:
1043 case SHADER_OPCODE_UNTYPED_SURFACE_WRITE_LOGICAL
:
1044 case SHADER_OPCODE_A64_UNTYPED_WRITE_LOGICAL
:
1045 case SHADER_OPCODE_A64_BYTE_SCATTERED_WRITE_LOGICAL
:
1046 case SHADER_OPCODE_A64_UNTYPED_ATOMIC_LOGICAL
:
1047 case SHADER_OPCODE_A64_UNTYPED_ATOMIC_FLOAT_LOGICAL
:
1048 case SHADER_OPCODE_BYTE_SCATTERED_WRITE_LOGICAL
:
1049 case SHADER_OPCODE_TYPED_ATOMIC_LOGICAL
:
1050 case SHADER_OPCODE_TYPED_SURFACE_WRITE_LOGICAL
:
1051 case SHADER_OPCODE_MEMORY_FENCE
:
1052 case SHADER_OPCODE_INTERLOCK
:
1053 case SHADER_OPCODE_URB_WRITE_SIMD8
:
1054 case SHADER_OPCODE_URB_WRITE_SIMD8_PER_SLOT
:
1055 case SHADER_OPCODE_URB_WRITE_SIMD8_MASKED
:
1056 case SHADER_OPCODE_URB_WRITE_SIMD8_MASKED_PER_SLOT
:
1057 case FS_OPCODE_FB_WRITE
:
1058 case FS_OPCODE_FB_WRITE_LOGICAL
:
1059 case FS_OPCODE_REP_FB_WRITE
:
1060 case SHADER_OPCODE_BARRIER
:
1061 case TCS_OPCODE_URB_WRITE
:
1062 case TCS_OPCODE_RELEASE_INPUT
:
1063 case SHADER_OPCODE_RND_MODE
:
1071 backend_instruction::is_volatile() const
1074 case SHADER_OPCODE_SEND
:
1075 return send_is_volatile
;
1077 case VEC4_OPCODE_UNTYPED_SURFACE_READ
:
1078 case SHADER_OPCODE_UNTYPED_SURFACE_READ_LOGICAL
:
1079 case SHADER_OPCODE_TYPED_SURFACE_READ_LOGICAL
:
1080 case SHADER_OPCODE_BYTE_SCATTERED_READ_LOGICAL
:
1081 case SHADER_OPCODE_A64_UNTYPED_READ_LOGICAL
:
1082 case SHADER_OPCODE_A64_BYTE_SCATTERED_READ_LOGICAL
:
1083 case SHADER_OPCODE_URB_READ_SIMD8
:
1084 case SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT
:
1085 case VEC4_OPCODE_URB_READ
:
1094 inst_is_in_block(const bblock_t
*block
, const backend_instruction
*inst
)
1097 foreach_inst_in_block (backend_instruction
, i
, block
) {
1107 adjust_later_block_ips(bblock_t
*start_block
, int ip_adjustment
)
1109 for (bblock_t
*block_iter
= start_block
->next();
1111 block_iter
= block_iter
->next()) {
1112 block_iter
->start_ip
+= ip_adjustment
;
1113 block_iter
->end_ip
+= ip_adjustment
;
1118 backend_instruction::insert_after(bblock_t
*block
, backend_instruction
*inst
)
1120 assert(this != inst
);
1122 if (!this->is_head_sentinel())
1123 assert(inst_is_in_block(block
, this) || !"Instruction not in block");
1127 adjust_later_block_ips(block
, 1);
1129 exec_node::insert_after(inst
);
1133 backend_instruction::insert_before(bblock_t
*block
, backend_instruction
*inst
)
1135 assert(this != inst
);
1137 if (!this->is_tail_sentinel())
1138 assert(inst_is_in_block(block
, this) || !"Instruction not in block");
1142 adjust_later_block_ips(block
, 1);
1144 exec_node::insert_before(inst
);
1148 backend_instruction::insert_before(bblock_t
*block
, exec_list
*list
)
1150 assert(inst_is_in_block(block
, this) || !"Instruction not in block");
1152 unsigned num_inst
= list
->length();
1154 block
->end_ip
+= num_inst
;
1156 adjust_later_block_ips(block
, num_inst
);
1158 exec_node::insert_before(list
);
1162 backend_instruction::remove(bblock_t
*block
)
1164 assert(inst_is_in_block(block
, this) || !"Instruction not in block");
1166 adjust_later_block_ips(block
, -1);
1168 if (block
->start_ip
== block
->end_ip
) {
1169 block
->cfg
->remove_block(block
);
1174 exec_node::remove();
1178 backend_shader::dump_instructions()
1180 dump_instructions(NULL
);
1184 backend_shader::dump_instructions(const char *name
)
1186 FILE *file
= stderr
;
1187 if (name
&& geteuid() != 0) {
1188 file
= fopen(name
, "w");
1195 foreach_block_and_inst(block
, backend_instruction
, inst
, cfg
) {
1196 if (!unlikely(INTEL_DEBUG
& DEBUG_OPTIMIZER
))
1197 fprintf(file
, "%4d: ", ip
++);
1198 dump_instruction(inst
, file
);
1202 foreach_in_list(backend_instruction
, inst
, &instructions
) {
1203 if (!unlikely(INTEL_DEBUG
& DEBUG_OPTIMIZER
))
1204 fprintf(file
, "%4d: ", ip
++);
1205 dump_instruction(inst
, file
);
1209 if (file
!= stderr
) {
1215 backend_shader::calculate_cfg()
1219 cfg
= new(mem_ctx
) cfg_t(&this->instructions
);
1222 extern "C" const unsigned *
1223 brw_compile_tes(const struct brw_compiler
*compiler
,
1226 const struct brw_tes_prog_key
*key
,
1227 const struct brw_vue_map
*input_vue_map
,
1228 struct brw_tes_prog_data
*prog_data
,
1230 struct gl_program
*prog
,
1231 int shader_time_index
,
1234 const struct gen_device_info
*devinfo
= compiler
->devinfo
;
1235 const bool is_scalar
= compiler
->scalar_stage
[MESA_SHADER_TESS_EVAL
];
1236 const unsigned *assembly
;
1238 nir
->info
.inputs_read
= key
->inputs_read
;
1239 nir
->info
.patch_inputs_read
= key
->patch_inputs_read
;
1241 nir
= brw_nir_apply_sampler_key(nir
, compiler
, &key
->tex
, is_scalar
);
1242 brw_nir_lower_tes_inputs(nir
, input_vue_map
);
1243 brw_nir_lower_vue_outputs(nir
);
1244 nir
= brw_postprocess_nir(nir
, compiler
, is_scalar
);
1246 brw_compute_vue_map(devinfo
, &prog_data
->base
.vue_map
,
1247 nir
->info
.outputs_written
,
1248 nir
->info
.separate_shader
);
1250 unsigned output_size_bytes
= prog_data
->base
.vue_map
.num_slots
* 4 * 4;
1252 assert(output_size_bytes
>= 1);
1253 if (output_size_bytes
> GEN7_MAX_DS_URB_ENTRY_SIZE_BYTES
) {
1255 *error_str
= ralloc_strdup(mem_ctx
, "DS outputs exceed maximum size");
1259 prog_data
->base
.clip_distance_mask
=
1260 ((1 << nir
->info
.clip_distance_array_size
) - 1);
1261 prog_data
->base
.cull_distance_mask
=
1262 ((1 << nir
->info
.cull_distance_array_size
) - 1) <<
1263 nir
->info
.clip_distance_array_size
;
1265 /* URB entry sizes are stored as a multiple of 64 bytes. */
1266 prog_data
->base
.urb_entry_size
= ALIGN(output_size_bytes
, 64) / 64;
1268 /* On Cannonlake software shall not program an allocation size that
1269 * specifies a size that is a multiple of 3 64B (512-bit) cachelines.
1271 if (devinfo
->gen
== 10 &&
1272 prog_data
->base
.urb_entry_size
% 3 == 0)
1273 prog_data
->base
.urb_entry_size
++;
1275 prog_data
->base
.urb_read_length
= 0;
1277 STATIC_ASSERT(BRW_TESS_PARTITIONING_INTEGER
== TESS_SPACING_EQUAL
- 1);
1278 STATIC_ASSERT(BRW_TESS_PARTITIONING_ODD_FRACTIONAL
==
1279 TESS_SPACING_FRACTIONAL_ODD
- 1);
1280 STATIC_ASSERT(BRW_TESS_PARTITIONING_EVEN_FRACTIONAL
==
1281 TESS_SPACING_FRACTIONAL_EVEN
- 1);
1283 prog_data
->partitioning
=
1284 (enum brw_tess_partitioning
) (nir
->info
.tess
.spacing
- 1);
1286 switch (nir
->info
.tess
.primitive_mode
) {
1288 prog_data
->domain
= BRW_TESS_DOMAIN_QUAD
;
1291 prog_data
->domain
= BRW_TESS_DOMAIN_TRI
;
1294 prog_data
->domain
= BRW_TESS_DOMAIN_ISOLINE
;
1297 unreachable("invalid domain shader primitive mode");
1300 if (nir
->info
.tess
.point_mode
) {
1301 prog_data
->output_topology
= BRW_TESS_OUTPUT_TOPOLOGY_POINT
;
1302 } else if (nir
->info
.tess
.primitive_mode
== GL_ISOLINES
) {
1303 prog_data
->output_topology
= BRW_TESS_OUTPUT_TOPOLOGY_LINE
;
1305 /* Hardware winding order is backwards from OpenGL */
1306 prog_data
->output_topology
=
1307 nir
->info
.tess
.ccw
? BRW_TESS_OUTPUT_TOPOLOGY_TRI_CW
1308 : BRW_TESS_OUTPUT_TOPOLOGY_TRI_CCW
;
1311 if (unlikely(INTEL_DEBUG
& DEBUG_TES
)) {
1312 fprintf(stderr
, "TES Input ");
1313 brw_print_vue_map(stderr
, input_vue_map
);
1314 fprintf(stderr
, "TES Output ");
1315 brw_print_vue_map(stderr
, &prog_data
->base
.vue_map
);
1319 fs_visitor
v(compiler
, log_data
, mem_ctx
, (void *) key
,
1320 &prog_data
->base
.base
, NULL
, nir
, 8,
1321 shader_time_index
, input_vue_map
);
1324 *error_str
= ralloc_strdup(mem_ctx
, v
.fail_msg
);
1328 prog_data
->base
.base
.dispatch_grf_start_reg
= v
.payload
.num_regs
;
1329 prog_data
->base
.dispatch_mode
= DISPATCH_MODE_SIMD8
;
1331 fs_generator
g(compiler
, log_data
, mem_ctx
,
1332 &prog_data
->base
.base
, v
.promoted_constants
, false,
1333 MESA_SHADER_TESS_EVAL
);
1334 if (unlikely(INTEL_DEBUG
& DEBUG_TES
)) {
1335 g
.enable_debug(ralloc_asprintf(mem_ctx
,
1336 "%s tessellation evaluation shader %s",
1337 nir
->info
.label
? nir
->info
.label
1342 g
.generate_code(v
.cfg
, 8);
1344 assembly
= g
.get_assembly();
1346 brw::vec4_tes_visitor
v(compiler
, log_data
, key
, prog_data
,
1347 nir
, mem_ctx
, shader_time_index
);
1350 *error_str
= ralloc_strdup(mem_ctx
, v
.fail_msg
);
1354 if (unlikely(INTEL_DEBUG
& DEBUG_TES
))
1355 v
.dump_instructions();
1357 assembly
= brw_vec4_generate_assembly(compiler
, log_data
, mem_ctx
, nir
,
1358 &prog_data
->base
, v
.cfg
);