intel/compiler: Move the destructor from vec4_visitor to backend_shader
[mesa.git] / src / intel / compiler / brw_shader.cpp
1 /*
2 * Copyright © 2010 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 */
23
24 #include "brw_cfg.h"
25 #include "brw_eu.h"
26 #include "brw_fs.h"
27 #include "brw_nir.h"
28 #include "brw_vec4_tes.h"
29 #include "common/gen_debug.h"
30 #include "main/uniforms.h"
31 #include "util/macros.h"
32
33 enum brw_reg_type
34 brw_type_for_base_type(const struct glsl_type *type)
35 {
36 switch (type->base_type) {
37 case GLSL_TYPE_FLOAT:
38 return BRW_REGISTER_TYPE_F;
39 case GLSL_TYPE_INT:
40 case GLSL_TYPE_BOOL:
41 case GLSL_TYPE_SUBROUTINE:
42 return BRW_REGISTER_TYPE_D;
43 case GLSL_TYPE_UINT:
44 return BRW_REGISTER_TYPE_UD;
45 case GLSL_TYPE_ARRAY:
46 return brw_type_for_base_type(type->fields.array);
47 case GLSL_TYPE_STRUCT:
48 case GLSL_TYPE_SAMPLER:
49 case GLSL_TYPE_ATOMIC_UINT:
50 /* These should be overridden with the type of the member when
51 * dereferenced into. BRW_REGISTER_TYPE_UD seems like a likely
52 * way to trip up if we don't.
53 */
54 return BRW_REGISTER_TYPE_UD;
55 case GLSL_TYPE_IMAGE:
56 return BRW_REGISTER_TYPE_UD;
57 case GLSL_TYPE_DOUBLE:
58 return BRW_REGISTER_TYPE_DF;
59 case GLSL_TYPE_UINT64:
60 return BRW_REGISTER_TYPE_UQ;
61 case GLSL_TYPE_INT64:
62 return BRW_REGISTER_TYPE_Q;
63 case GLSL_TYPE_VOID:
64 case GLSL_TYPE_ERROR:
65 case GLSL_TYPE_INTERFACE:
66 case GLSL_TYPE_FUNCTION:
67 unreachable("not reached");
68 }
69
70 return BRW_REGISTER_TYPE_F;
71 }
72
73 enum brw_conditional_mod
74 brw_conditional_for_comparison(unsigned int op)
75 {
76 switch (op) {
77 case ir_binop_less:
78 return BRW_CONDITIONAL_L;
79 case ir_binop_gequal:
80 return BRW_CONDITIONAL_GE;
81 case ir_binop_equal:
82 case ir_binop_all_equal: /* same as equal for scalars */
83 return BRW_CONDITIONAL_Z;
84 case ir_binop_nequal:
85 case ir_binop_any_nequal: /* same as nequal for scalars */
86 return BRW_CONDITIONAL_NZ;
87 default:
88 unreachable("not reached: bad operation for comparison");
89 }
90 }
91
92 uint32_t
93 brw_math_function(enum opcode op)
94 {
95 switch (op) {
96 case SHADER_OPCODE_RCP:
97 return BRW_MATH_FUNCTION_INV;
98 case SHADER_OPCODE_RSQ:
99 return BRW_MATH_FUNCTION_RSQ;
100 case SHADER_OPCODE_SQRT:
101 return BRW_MATH_FUNCTION_SQRT;
102 case SHADER_OPCODE_EXP2:
103 return BRW_MATH_FUNCTION_EXP;
104 case SHADER_OPCODE_LOG2:
105 return BRW_MATH_FUNCTION_LOG;
106 case SHADER_OPCODE_POW:
107 return BRW_MATH_FUNCTION_POW;
108 case SHADER_OPCODE_SIN:
109 return BRW_MATH_FUNCTION_SIN;
110 case SHADER_OPCODE_COS:
111 return BRW_MATH_FUNCTION_COS;
112 case SHADER_OPCODE_INT_QUOTIENT:
113 return BRW_MATH_FUNCTION_INT_DIV_QUOTIENT;
114 case SHADER_OPCODE_INT_REMAINDER:
115 return BRW_MATH_FUNCTION_INT_DIV_REMAINDER;
116 default:
117 unreachable("not reached: unknown math function");
118 }
119 }
120
121 bool
122 brw_texture_offset(int *offsets, unsigned num_components, uint32_t *offset_bits)
123 {
124 if (!offsets) return false; /* nonconstant offset; caller will handle it. */
125
126 /* offset out of bounds; caller will handle it. */
127 for (unsigned i = 0; i < num_components; i++)
128 if (offsets[i] > 7 || offsets[i] < -8)
129 return false;
130
131 /* Combine all three offsets into a single unsigned dword:
132 *
133 * bits 11:8 - U Offset (X component)
134 * bits 7:4 - V Offset (Y component)
135 * bits 3:0 - R Offset (Z component)
136 */
137 *offset_bits = 0;
138 for (unsigned i = 0; i < num_components; i++) {
139 const unsigned shift = 4 * (2 - i);
140 *offset_bits |= (offsets[i] << shift) & (0xF << shift);
141 }
142 return true;
143 }
144
145 const char *
146 brw_instruction_name(const struct gen_device_info *devinfo, enum opcode op)
147 {
148 switch (op) {
149 case BRW_OPCODE_ILLEGAL ... BRW_OPCODE_NOP:
150 /* The DO instruction doesn't exist on Gen6+, but we use it to mark the
151 * start of a loop in the IR.
152 */
153 if (devinfo->gen >= 6 && op == BRW_OPCODE_DO)
154 return "do";
155
156 /* The following conversion opcodes doesn't exist on Gen8+, but we use
157 * then to mark that we want to do the conversion.
158 */
159 if (devinfo->gen > 7 && op == BRW_OPCODE_F32TO16)
160 return "f32to16";
161
162 if (devinfo->gen > 7 && op == BRW_OPCODE_F16TO32)
163 return "f16to32";
164
165 assert(brw_opcode_desc(devinfo, op)->name);
166 return brw_opcode_desc(devinfo, op)->name;
167 case FS_OPCODE_FB_WRITE:
168 return "fb_write";
169 case FS_OPCODE_FB_WRITE_LOGICAL:
170 return "fb_write_logical";
171 case FS_OPCODE_REP_FB_WRITE:
172 return "rep_fb_write";
173 case FS_OPCODE_FB_READ:
174 return "fb_read";
175 case FS_OPCODE_FB_READ_LOGICAL:
176 return "fb_read_logical";
177
178 case SHADER_OPCODE_RCP:
179 return "rcp";
180 case SHADER_OPCODE_RSQ:
181 return "rsq";
182 case SHADER_OPCODE_SQRT:
183 return "sqrt";
184 case SHADER_OPCODE_EXP2:
185 return "exp2";
186 case SHADER_OPCODE_LOG2:
187 return "log2";
188 case SHADER_OPCODE_POW:
189 return "pow";
190 case SHADER_OPCODE_INT_QUOTIENT:
191 return "int_quot";
192 case SHADER_OPCODE_INT_REMAINDER:
193 return "int_rem";
194 case SHADER_OPCODE_SIN:
195 return "sin";
196 case SHADER_OPCODE_COS:
197 return "cos";
198
199 case SHADER_OPCODE_TEX:
200 return "tex";
201 case SHADER_OPCODE_TEX_LOGICAL:
202 return "tex_logical";
203 case SHADER_OPCODE_TXD:
204 return "txd";
205 case SHADER_OPCODE_TXD_LOGICAL:
206 return "txd_logical";
207 case SHADER_OPCODE_TXF:
208 return "txf";
209 case SHADER_OPCODE_TXF_LOGICAL:
210 return "txf_logical";
211 case SHADER_OPCODE_TXF_LZ:
212 return "txf_lz";
213 case SHADER_OPCODE_TXL:
214 return "txl";
215 case SHADER_OPCODE_TXL_LOGICAL:
216 return "txl_logical";
217 case SHADER_OPCODE_TXL_LZ:
218 return "txl_lz";
219 case SHADER_OPCODE_TXS:
220 return "txs";
221 case SHADER_OPCODE_TXS_LOGICAL:
222 return "txs_logical";
223 case FS_OPCODE_TXB:
224 return "txb";
225 case FS_OPCODE_TXB_LOGICAL:
226 return "txb_logical";
227 case SHADER_OPCODE_TXF_CMS:
228 return "txf_cms";
229 case SHADER_OPCODE_TXF_CMS_LOGICAL:
230 return "txf_cms_logical";
231 case SHADER_OPCODE_TXF_CMS_W:
232 return "txf_cms_w";
233 case SHADER_OPCODE_TXF_CMS_W_LOGICAL:
234 return "txf_cms_w_logical";
235 case SHADER_OPCODE_TXF_UMS:
236 return "txf_ums";
237 case SHADER_OPCODE_TXF_UMS_LOGICAL:
238 return "txf_ums_logical";
239 case SHADER_OPCODE_TXF_MCS:
240 return "txf_mcs";
241 case SHADER_OPCODE_TXF_MCS_LOGICAL:
242 return "txf_mcs_logical";
243 case SHADER_OPCODE_LOD:
244 return "lod";
245 case SHADER_OPCODE_LOD_LOGICAL:
246 return "lod_logical";
247 case SHADER_OPCODE_TG4:
248 return "tg4";
249 case SHADER_OPCODE_TG4_LOGICAL:
250 return "tg4_logical";
251 case SHADER_OPCODE_TG4_OFFSET:
252 return "tg4_offset";
253 case SHADER_OPCODE_TG4_OFFSET_LOGICAL:
254 return "tg4_offset_logical";
255 case SHADER_OPCODE_SAMPLEINFO:
256 return "sampleinfo";
257 case SHADER_OPCODE_SAMPLEINFO_LOGICAL:
258 return "sampleinfo_logical";
259
260 case SHADER_OPCODE_SHADER_TIME_ADD:
261 return "shader_time_add";
262
263 case SHADER_OPCODE_UNTYPED_ATOMIC:
264 return "untyped_atomic";
265 case SHADER_OPCODE_UNTYPED_ATOMIC_LOGICAL:
266 return "untyped_atomic_logical";
267 case SHADER_OPCODE_UNTYPED_SURFACE_READ:
268 return "untyped_surface_read";
269 case SHADER_OPCODE_UNTYPED_SURFACE_READ_LOGICAL:
270 return "untyped_surface_read_logical";
271 case SHADER_OPCODE_UNTYPED_SURFACE_WRITE:
272 return "untyped_surface_write";
273 case SHADER_OPCODE_UNTYPED_SURFACE_WRITE_LOGICAL:
274 return "untyped_surface_write_logical";
275 case SHADER_OPCODE_TYPED_ATOMIC:
276 return "typed_atomic";
277 case SHADER_OPCODE_TYPED_ATOMIC_LOGICAL:
278 return "typed_atomic_logical";
279 case SHADER_OPCODE_TYPED_SURFACE_READ:
280 return "typed_surface_read";
281 case SHADER_OPCODE_TYPED_SURFACE_READ_LOGICAL:
282 return "typed_surface_read_logical";
283 case SHADER_OPCODE_TYPED_SURFACE_WRITE:
284 return "typed_surface_write";
285 case SHADER_OPCODE_TYPED_SURFACE_WRITE_LOGICAL:
286 return "typed_surface_write_logical";
287 case SHADER_OPCODE_MEMORY_FENCE:
288 return "memory_fence";
289
290 case SHADER_OPCODE_LOAD_PAYLOAD:
291 return "load_payload";
292 case FS_OPCODE_PACK:
293 return "pack";
294
295 case SHADER_OPCODE_GEN4_SCRATCH_READ:
296 return "gen4_scratch_read";
297 case SHADER_OPCODE_GEN4_SCRATCH_WRITE:
298 return "gen4_scratch_write";
299 case SHADER_OPCODE_GEN7_SCRATCH_READ:
300 return "gen7_scratch_read";
301 case SHADER_OPCODE_URB_WRITE_SIMD8:
302 return "gen8_urb_write_simd8";
303 case SHADER_OPCODE_URB_WRITE_SIMD8_PER_SLOT:
304 return "gen8_urb_write_simd8_per_slot";
305 case SHADER_OPCODE_URB_WRITE_SIMD8_MASKED:
306 return "gen8_urb_write_simd8_masked";
307 case SHADER_OPCODE_URB_WRITE_SIMD8_MASKED_PER_SLOT:
308 return "gen8_urb_write_simd8_masked_per_slot";
309 case SHADER_OPCODE_URB_READ_SIMD8:
310 return "urb_read_simd8";
311 case SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT:
312 return "urb_read_simd8_per_slot";
313
314 case SHADER_OPCODE_FIND_LIVE_CHANNEL:
315 return "find_live_channel";
316 case SHADER_OPCODE_BROADCAST:
317 return "broadcast";
318
319 case VEC4_OPCODE_MOV_BYTES:
320 return "mov_bytes";
321 case VEC4_OPCODE_PACK_BYTES:
322 return "pack_bytes";
323 case VEC4_OPCODE_UNPACK_UNIFORM:
324 return "unpack_uniform";
325 case VEC4_OPCODE_DOUBLE_TO_F32:
326 return "double_to_f32";
327 case VEC4_OPCODE_DOUBLE_TO_D32:
328 return "double_to_d32";
329 case VEC4_OPCODE_DOUBLE_TO_U32:
330 return "double_to_u32";
331 case VEC4_OPCODE_TO_DOUBLE:
332 return "single_to_double";
333 case VEC4_OPCODE_PICK_LOW_32BIT:
334 return "pick_low_32bit";
335 case VEC4_OPCODE_PICK_HIGH_32BIT:
336 return "pick_high_32bit";
337 case VEC4_OPCODE_SET_LOW_32BIT:
338 return "set_low_32bit";
339 case VEC4_OPCODE_SET_HIGH_32BIT:
340 return "set_high_32bit";
341
342 case FS_OPCODE_DDX_COARSE:
343 return "ddx_coarse";
344 case FS_OPCODE_DDX_FINE:
345 return "ddx_fine";
346 case FS_OPCODE_DDY_COARSE:
347 return "ddy_coarse";
348 case FS_OPCODE_DDY_FINE:
349 return "ddy_fine";
350
351 case FS_OPCODE_CINTERP:
352 return "cinterp";
353 case FS_OPCODE_LINTERP:
354 return "linterp";
355
356 case FS_OPCODE_PIXEL_X:
357 return "pixel_x";
358 case FS_OPCODE_PIXEL_Y:
359 return "pixel_y";
360
361 case FS_OPCODE_GET_BUFFER_SIZE:
362 return "fs_get_buffer_size";
363
364 case FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD:
365 return "uniform_pull_const";
366 case FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD_GEN7:
367 return "uniform_pull_const_gen7";
368 case FS_OPCODE_VARYING_PULL_CONSTANT_LOAD_GEN4:
369 return "varying_pull_const_gen4";
370 case FS_OPCODE_VARYING_PULL_CONSTANT_LOAD_GEN7:
371 return "varying_pull_const_gen7";
372 case FS_OPCODE_VARYING_PULL_CONSTANT_LOAD_LOGICAL:
373 return "varying_pull_const_logical";
374
375 case FS_OPCODE_MOV_DISPATCH_TO_FLAGS:
376 return "mov_dispatch_to_flags";
377 case FS_OPCODE_DISCARD_JUMP:
378 return "discard_jump";
379
380 case FS_OPCODE_SET_SAMPLE_ID:
381 return "set_sample_id";
382
383 case FS_OPCODE_PACK_HALF_2x16_SPLIT:
384 return "pack_half_2x16_split";
385 case FS_OPCODE_UNPACK_HALF_2x16_SPLIT_X:
386 return "unpack_half_2x16_split_x";
387 case FS_OPCODE_UNPACK_HALF_2x16_SPLIT_Y:
388 return "unpack_half_2x16_split_y";
389
390 case FS_OPCODE_PLACEHOLDER_HALT:
391 return "placeholder_halt";
392
393 case FS_OPCODE_INTERPOLATE_AT_SAMPLE:
394 return "interp_sample";
395 case FS_OPCODE_INTERPOLATE_AT_SHARED_OFFSET:
396 return "interp_shared_offset";
397 case FS_OPCODE_INTERPOLATE_AT_PER_SLOT_OFFSET:
398 return "interp_per_slot_offset";
399
400 case VS_OPCODE_URB_WRITE:
401 return "vs_urb_write";
402 case VS_OPCODE_PULL_CONSTANT_LOAD:
403 return "pull_constant_load";
404 case VS_OPCODE_PULL_CONSTANT_LOAD_GEN7:
405 return "pull_constant_load_gen7";
406
407 case VS_OPCODE_SET_SIMD4X2_HEADER_GEN9:
408 return "set_simd4x2_header_gen9";
409
410 case VS_OPCODE_GET_BUFFER_SIZE:
411 return "vs_get_buffer_size";
412
413 case VS_OPCODE_UNPACK_FLAGS_SIMD4X2:
414 return "unpack_flags_simd4x2";
415
416 case GS_OPCODE_URB_WRITE:
417 return "gs_urb_write";
418 case GS_OPCODE_URB_WRITE_ALLOCATE:
419 return "gs_urb_write_allocate";
420 case GS_OPCODE_THREAD_END:
421 return "gs_thread_end";
422 case GS_OPCODE_SET_WRITE_OFFSET:
423 return "set_write_offset";
424 case GS_OPCODE_SET_VERTEX_COUNT:
425 return "set_vertex_count";
426 case GS_OPCODE_SET_DWORD_2:
427 return "set_dword_2";
428 case GS_OPCODE_PREPARE_CHANNEL_MASKS:
429 return "prepare_channel_masks";
430 case GS_OPCODE_SET_CHANNEL_MASKS:
431 return "set_channel_masks";
432 case GS_OPCODE_GET_INSTANCE_ID:
433 return "get_instance_id";
434 case GS_OPCODE_FF_SYNC:
435 return "ff_sync";
436 case GS_OPCODE_SET_PRIMITIVE_ID:
437 return "set_primitive_id";
438 case GS_OPCODE_SVB_WRITE:
439 return "gs_svb_write";
440 case GS_OPCODE_SVB_SET_DST_INDEX:
441 return "gs_svb_set_dst_index";
442 case GS_OPCODE_FF_SYNC_SET_PRIMITIVES:
443 return "gs_ff_sync_set_primitives";
444 case CS_OPCODE_CS_TERMINATE:
445 return "cs_terminate";
446 case SHADER_OPCODE_BARRIER:
447 return "barrier";
448 case SHADER_OPCODE_MULH:
449 return "mulh";
450 case SHADER_OPCODE_MOV_INDIRECT:
451 return "mov_indirect";
452
453 case VEC4_OPCODE_URB_READ:
454 return "urb_read";
455 case TCS_OPCODE_GET_INSTANCE_ID:
456 return "tcs_get_instance_id";
457 case TCS_OPCODE_URB_WRITE:
458 return "tcs_urb_write";
459 case TCS_OPCODE_SET_INPUT_URB_OFFSETS:
460 return "tcs_set_input_urb_offsets";
461 case TCS_OPCODE_SET_OUTPUT_URB_OFFSETS:
462 return "tcs_set_output_urb_offsets";
463 case TCS_OPCODE_GET_PRIMITIVE_ID:
464 return "tcs_get_primitive_id";
465 case TCS_OPCODE_CREATE_BARRIER_HEADER:
466 return "tcs_create_barrier_header";
467 case TCS_OPCODE_SRC0_010_IS_ZERO:
468 return "tcs_src0<0,1,0>_is_zero";
469 case TCS_OPCODE_RELEASE_INPUT:
470 return "tcs_release_input";
471 case TCS_OPCODE_THREAD_END:
472 return "tcs_thread_end";
473 case TES_OPCODE_CREATE_INPUT_READ_HEADER:
474 return "tes_create_input_read_header";
475 case TES_OPCODE_ADD_INDIRECT_URB_OFFSET:
476 return "tes_add_indirect_urb_offset";
477 case TES_OPCODE_GET_PRIMITIVE_ID:
478 return "tes_get_primitive_id";
479 }
480
481 unreachable("not reached");
482 }
483
484 bool
485 brw_saturate_immediate(enum brw_reg_type type, struct brw_reg *reg)
486 {
487 union {
488 unsigned ud;
489 int d;
490 float f;
491 double df;
492 } imm, sat_imm = { 0 };
493
494 const unsigned size = type_sz(type);
495
496 /* We want to either do a 32-bit or 64-bit data copy, the type is otherwise
497 * irrelevant, so just check the size of the type and copy from/to an
498 * appropriately sized field.
499 */
500 if (size < 8)
501 imm.ud = reg->ud;
502 else
503 imm.df = reg->df;
504
505 switch (type) {
506 case BRW_REGISTER_TYPE_UD:
507 case BRW_REGISTER_TYPE_D:
508 case BRW_REGISTER_TYPE_UW:
509 case BRW_REGISTER_TYPE_W:
510 case BRW_REGISTER_TYPE_UQ:
511 case BRW_REGISTER_TYPE_Q:
512 /* Nothing to do. */
513 return false;
514 case BRW_REGISTER_TYPE_F:
515 sat_imm.f = CLAMP(imm.f, 0.0f, 1.0f);
516 break;
517 case BRW_REGISTER_TYPE_DF:
518 sat_imm.df = CLAMP(imm.df, 0.0, 1.0);
519 break;
520 case BRW_REGISTER_TYPE_UB:
521 case BRW_REGISTER_TYPE_B:
522 unreachable("no UB/B immediates");
523 case BRW_REGISTER_TYPE_V:
524 case BRW_REGISTER_TYPE_UV:
525 case BRW_REGISTER_TYPE_VF:
526 unreachable("unimplemented: saturate vector immediate");
527 case BRW_REGISTER_TYPE_HF:
528 unreachable("unimplemented: saturate HF immediate");
529 }
530
531 if (size < 8) {
532 if (imm.ud != sat_imm.ud) {
533 reg->ud = sat_imm.ud;
534 return true;
535 }
536 } else {
537 if (imm.df != sat_imm.df) {
538 reg->df = sat_imm.df;
539 return true;
540 }
541 }
542 return false;
543 }
544
545 bool
546 brw_negate_immediate(enum brw_reg_type type, struct brw_reg *reg)
547 {
548 switch (type) {
549 case BRW_REGISTER_TYPE_D:
550 case BRW_REGISTER_TYPE_UD:
551 reg->d = -reg->d;
552 return true;
553 case BRW_REGISTER_TYPE_W:
554 case BRW_REGISTER_TYPE_UW:
555 reg->d = -(int16_t)reg->ud;
556 return true;
557 case BRW_REGISTER_TYPE_F:
558 reg->f = -reg->f;
559 return true;
560 case BRW_REGISTER_TYPE_VF:
561 reg->ud ^= 0x80808080;
562 return true;
563 case BRW_REGISTER_TYPE_DF:
564 reg->df = -reg->df;
565 return true;
566 case BRW_REGISTER_TYPE_UQ:
567 case BRW_REGISTER_TYPE_Q:
568 reg->d64 = -reg->d64;
569 return true;
570 case BRW_REGISTER_TYPE_UB:
571 case BRW_REGISTER_TYPE_B:
572 unreachable("no UB/B immediates");
573 case BRW_REGISTER_TYPE_UV:
574 case BRW_REGISTER_TYPE_V:
575 assert(!"unimplemented: negate UV/V immediate");
576 case BRW_REGISTER_TYPE_HF:
577 assert(!"unimplemented: negate HF immediate");
578 }
579
580 return false;
581 }
582
583 bool
584 brw_abs_immediate(enum brw_reg_type type, struct brw_reg *reg)
585 {
586 switch (type) {
587 case BRW_REGISTER_TYPE_D:
588 reg->d = abs(reg->d);
589 return true;
590 case BRW_REGISTER_TYPE_W:
591 reg->d = abs((int16_t)reg->ud);
592 return true;
593 case BRW_REGISTER_TYPE_F:
594 reg->f = fabsf(reg->f);
595 return true;
596 case BRW_REGISTER_TYPE_DF:
597 reg->df = fabs(reg->df);
598 return true;
599 case BRW_REGISTER_TYPE_VF:
600 reg->ud &= ~0x80808080;
601 return true;
602 case BRW_REGISTER_TYPE_Q:
603 reg->d64 = imaxabs(reg->d64);
604 return true;
605 case BRW_REGISTER_TYPE_UB:
606 case BRW_REGISTER_TYPE_B:
607 unreachable("no UB/B immediates");
608 case BRW_REGISTER_TYPE_UQ:
609 case BRW_REGISTER_TYPE_UD:
610 case BRW_REGISTER_TYPE_UW:
611 case BRW_REGISTER_TYPE_UV:
612 /* Presumably the absolute value modifier on an unsigned source is a
613 * nop, but it would be nice to confirm.
614 */
615 assert(!"unimplemented: abs unsigned immediate");
616 case BRW_REGISTER_TYPE_V:
617 assert(!"unimplemented: abs V immediate");
618 case BRW_REGISTER_TYPE_HF:
619 assert(!"unimplemented: abs HF immediate");
620 }
621
622 return false;
623 }
624
625 /**
626 * Get the appropriate atomic op for an image atomic intrinsic.
627 */
628 unsigned
629 get_atomic_counter_op(nir_intrinsic_op op)
630 {
631 switch (op) {
632 case nir_intrinsic_atomic_counter_inc:
633 return BRW_AOP_INC;
634 case nir_intrinsic_atomic_counter_dec:
635 return BRW_AOP_PREDEC;
636 case nir_intrinsic_atomic_counter_add:
637 return BRW_AOP_ADD;
638 case nir_intrinsic_atomic_counter_min:
639 return BRW_AOP_UMIN;
640 case nir_intrinsic_atomic_counter_max:
641 return BRW_AOP_UMAX;
642 case nir_intrinsic_atomic_counter_and:
643 return BRW_AOP_AND;
644 case nir_intrinsic_atomic_counter_or:
645 return BRW_AOP_OR;
646 case nir_intrinsic_atomic_counter_xor:
647 return BRW_AOP_XOR;
648 case nir_intrinsic_atomic_counter_exchange:
649 return BRW_AOP_MOV;
650 case nir_intrinsic_atomic_counter_comp_swap:
651 return BRW_AOP_CMPWR;
652 default:
653 unreachable("Not reachable.");
654 }
655 }
656
657 backend_shader::backend_shader(const struct brw_compiler *compiler,
658 void *log_data,
659 void *mem_ctx,
660 const nir_shader *shader,
661 struct brw_stage_prog_data *stage_prog_data)
662 : compiler(compiler),
663 log_data(log_data),
664 devinfo(compiler->devinfo),
665 nir(shader),
666 stage_prog_data(stage_prog_data),
667 mem_ctx(mem_ctx),
668 cfg(NULL),
669 stage(shader->info.stage)
670 {
671 debug_enabled = INTEL_DEBUG & intel_debug_flag_for_shader_stage(stage);
672 stage_name = _mesa_shader_stage_to_string(stage);
673 stage_abbrev = _mesa_shader_stage_to_abbrev(stage);
674 }
675
676 backend_shader::~backend_shader()
677 {
678 }
679
680 bool
681 backend_reg::equals(const backend_reg &r) const
682 {
683 return brw_regs_equal(this, &r) && offset == r.offset;
684 }
685
686 bool
687 backend_reg::is_zero() const
688 {
689 if (file != IMM)
690 return false;
691
692 switch (type) {
693 case BRW_REGISTER_TYPE_F:
694 return f == 0;
695 case BRW_REGISTER_TYPE_DF:
696 return df == 0;
697 case BRW_REGISTER_TYPE_D:
698 case BRW_REGISTER_TYPE_UD:
699 return d == 0;
700 case BRW_REGISTER_TYPE_UQ:
701 case BRW_REGISTER_TYPE_Q:
702 return u64 == 0;
703 default:
704 return false;
705 }
706 }
707
708 bool
709 backend_reg::is_one() const
710 {
711 if (file != IMM)
712 return false;
713
714 switch (type) {
715 case BRW_REGISTER_TYPE_F:
716 return f == 1.0f;
717 case BRW_REGISTER_TYPE_DF:
718 return df == 1.0;
719 case BRW_REGISTER_TYPE_D:
720 case BRW_REGISTER_TYPE_UD:
721 return d == 1;
722 case BRW_REGISTER_TYPE_UQ:
723 case BRW_REGISTER_TYPE_Q:
724 return u64 == 1;
725 default:
726 return false;
727 }
728 }
729
730 bool
731 backend_reg::is_negative_one() const
732 {
733 if (file != IMM)
734 return false;
735
736 switch (type) {
737 case BRW_REGISTER_TYPE_F:
738 return f == -1.0;
739 case BRW_REGISTER_TYPE_DF:
740 return df == -1.0;
741 case BRW_REGISTER_TYPE_D:
742 return d == -1;
743 case BRW_REGISTER_TYPE_Q:
744 return d64 == -1;
745 default:
746 return false;
747 }
748 }
749
750 bool
751 backend_reg::is_null() const
752 {
753 return file == ARF && nr == BRW_ARF_NULL;
754 }
755
756
757 bool
758 backend_reg::is_accumulator() const
759 {
760 return file == ARF && nr == BRW_ARF_ACCUMULATOR;
761 }
762
763 bool
764 backend_instruction::is_commutative() const
765 {
766 switch (opcode) {
767 case BRW_OPCODE_AND:
768 case BRW_OPCODE_OR:
769 case BRW_OPCODE_XOR:
770 case BRW_OPCODE_ADD:
771 case BRW_OPCODE_MUL:
772 case SHADER_OPCODE_MULH:
773 return true;
774 case BRW_OPCODE_SEL:
775 /* MIN and MAX are commutative. */
776 if (conditional_mod == BRW_CONDITIONAL_GE ||
777 conditional_mod == BRW_CONDITIONAL_L) {
778 return true;
779 }
780 /* fallthrough */
781 default:
782 return false;
783 }
784 }
785
786 bool
787 backend_instruction::is_3src(const struct gen_device_info *devinfo) const
788 {
789 return ::is_3src(devinfo, opcode);
790 }
791
792 bool
793 backend_instruction::is_tex() const
794 {
795 return (opcode == SHADER_OPCODE_TEX ||
796 opcode == FS_OPCODE_TXB ||
797 opcode == SHADER_OPCODE_TXD ||
798 opcode == SHADER_OPCODE_TXF ||
799 opcode == SHADER_OPCODE_TXF_LZ ||
800 opcode == SHADER_OPCODE_TXF_CMS ||
801 opcode == SHADER_OPCODE_TXF_CMS_W ||
802 opcode == SHADER_OPCODE_TXF_UMS ||
803 opcode == SHADER_OPCODE_TXF_MCS ||
804 opcode == SHADER_OPCODE_TXL ||
805 opcode == SHADER_OPCODE_TXL_LZ ||
806 opcode == SHADER_OPCODE_TXS ||
807 opcode == SHADER_OPCODE_LOD ||
808 opcode == SHADER_OPCODE_TG4 ||
809 opcode == SHADER_OPCODE_TG4_OFFSET ||
810 opcode == SHADER_OPCODE_SAMPLEINFO);
811 }
812
813 bool
814 backend_instruction::is_math() const
815 {
816 return (opcode == SHADER_OPCODE_RCP ||
817 opcode == SHADER_OPCODE_RSQ ||
818 opcode == SHADER_OPCODE_SQRT ||
819 opcode == SHADER_OPCODE_EXP2 ||
820 opcode == SHADER_OPCODE_LOG2 ||
821 opcode == SHADER_OPCODE_SIN ||
822 opcode == SHADER_OPCODE_COS ||
823 opcode == SHADER_OPCODE_INT_QUOTIENT ||
824 opcode == SHADER_OPCODE_INT_REMAINDER ||
825 opcode == SHADER_OPCODE_POW);
826 }
827
828 bool
829 backend_instruction::is_control_flow() const
830 {
831 switch (opcode) {
832 case BRW_OPCODE_DO:
833 case BRW_OPCODE_WHILE:
834 case BRW_OPCODE_IF:
835 case BRW_OPCODE_ELSE:
836 case BRW_OPCODE_ENDIF:
837 case BRW_OPCODE_BREAK:
838 case BRW_OPCODE_CONTINUE:
839 return true;
840 default:
841 return false;
842 }
843 }
844
845 bool
846 backend_instruction::can_do_source_mods() const
847 {
848 switch (opcode) {
849 case BRW_OPCODE_ADDC:
850 case BRW_OPCODE_BFE:
851 case BRW_OPCODE_BFI1:
852 case BRW_OPCODE_BFI2:
853 case BRW_OPCODE_BFREV:
854 case BRW_OPCODE_CBIT:
855 case BRW_OPCODE_FBH:
856 case BRW_OPCODE_FBL:
857 case BRW_OPCODE_SUBB:
858 case SHADER_OPCODE_BROADCAST:
859 case SHADER_OPCODE_MOV_INDIRECT:
860 return false;
861 default:
862 return true;
863 }
864 }
865
866 bool
867 backend_instruction::can_do_saturate() const
868 {
869 switch (opcode) {
870 case BRW_OPCODE_ADD:
871 case BRW_OPCODE_ASR:
872 case BRW_OPCODE_AVG:
873 case BRW_OPCODE_DP2:
874 case BRW_OPCODE_DP3:
875 case BRW_OPCODE_DP4:
876 case BRW_OPCODE_DPH:
877 case BRW_OPCODE_F16TO32:
878 case BRW_OPCODE_F32TO16:
879 case BRW_OPCODE_LINE:
880 case BRW_OPCODE_LRP:
881 case BRW_OPCODE_MAC:
882 case BRW_OPCODE_MAD:
883 case BRW_OPCODE_MATH:
884 case BRW_OPCODE_MOV:
885 case BRW_OPCODE_MUL:
886 case SHADER_OPCODE_MULH:
887 case BRW_OPCODE_PLN:
888 case BRW_OPCODE_RNDD:
889 case BRW_OPCODE_RNDE:
890 case BRW_OPCODE_RNDU:
891 case BRW_OPCODE_RNDZ:
892 case BRW_OPCODE_SEL:
893 case BRW_OPCODE_SHL:
894 case BRW_OPCODE_SHR:
895 case FS_OPCODE_LINTERP:
896 case SHADER_OPCODE_COS:
897 case SHADER_OPCODE_EXP2:
898 case SHADER_OPCODE_LOG2:
899 case SHADER_OPCODE_POW:
900 case SHADER_OPCODE_RCP:
901 case SHADER_OPCODE_RSQ:
902 case SHADER_OPCODE_SIN:
903 case SHADER_OPCODE_SQRT:
904 return true;
905 default:
906 return false;
907 }
908 }
909
910 bool
911 backend_instruction::can_do_cmod() const
912 {
913 switch (opcode) {
914 case BRW_OPCODE_ADD:
915 case BRW_OPCODE_ADDC:
916 case BRW_OPCODE_AND:
917 case BRW_OPCODE_ASR:
918 case BRW_OPCODE_AVG:
919 case BRW_OPCODE_CMP:
920 case BRW_OPCODE_CMPN:
921 case BRW_OPCODE_DP2:
922 case BRW_OPCODE_DP3:
923 case BRW_OPCODE_DP4:
924 case BRW_OPCODE_DPH:
925 case BRW_OPCODE_F16TO32:
926 case BRW_OPCODE_F32TO16:
927 case BRW_OPCODE_FRC:
928 case BRW_OPCODE_LINE:
929 case BRW_OPCODE_LRP:
930 case BRW_OPCODE_LZD:
931 case BRW_OPCODE_MAC:
932 case BRW_OPCODE_MACH:
933 case BRW_OPCODE_MAD:
934 case BRW_OPCODE_MOV:
935 case BRW_OPCODE_MUL:
936 case BRW_OPCODE_NOT:
937 case BRW_OPCODE_OR:
938 case BRW_OPCODE_PLN:
939 case BRW_OPCODE_RNDD:
940 case BRW_OPCODE_RNDE:
941 case BRW_OPCODE_RNDU:
942 case BRW_OPCODE_RNDZ:
943 case BRW_OPCODE_SAD2:
944 case BRW_OPCODE_SADA2:
945 case BRW_OPCODE_SHL:
946 case BRW_OPCODE_SHR:
947 case BRW_OPCODE_SUBB:
948 case BRW_OPCODE_XOR:
949 case FS_OPCODE_CINTERP:
950 case FS_OPCODE_LINTERP:
951 return true;
952 default:
953 return false;
954 }
955 }
956
957 bool
958 backend_instruction::reads_accumulator_implicitly() const
959 {
960 switch (opcode) {
961 case BRW_OPCODE_MAC:
962 case BRW_OPCODE_MACH:
963 case BRW_OPCODE_SADA2:
964 return true;
965 default:
966 return false;
967 }
968 }
969
970 bool
971 backend_instruction::writes_accumulator_implicitly(const struct gen_device_info *devinfo) const
972 {
973 return writes_accumulator ||
974 (devinfo->gen < 6 &&
975 ((opcode >= BRW_OPCODE_ADD && opcode < BRW_OPCODE_NOP) ||
976 (opcode >= FS_OPCODE_DDX_COARSE && opcode <= FS_OPCODE_LINTERP &&
977 opcode != FS_OPCODE_CINTERP)));
978 }
979
980 bool
981 backend_instruction::has_side_effects() const
982 {
983 switch (opcode) {
984 case SHADER_OPCODE_UNTYPED_ATOMIC:
985 case SHADER_OPCODE_UNTYPED_ATOMIC_LOGICAL:
986 case SHADER_OPCODE_GEN4_SCRATCH_WRITE:
987 case SHADER_OPCODE_UNTYPED_SURFACE_WRITE:
988 case SHADER_OPCODE_UNTYPED_SURFACE_WRITE_LOGICAL:
989 case SHADER_OPCODE_TYPED_ATOMIC:
990 case SHADER_OPCODE_TYPED_ATOMIC_LOGICAL:
991 case SHADER_OPCODE_TYPED_SURFACE_WRITE:
992 case SHADER_OPCODE_TYPED_SURFACE_WRITE_LOGICAL:
993 case SHADER_OPCODE_MEMORY_FENCE:
994 case SHADER_OPCODE_URB_WRITE_SIMD8:
995 case SHADER_OPCODE_URB_WRITE_SIMD8_PER_SLOT:
996 case SHADER_OPCODE_URB_WRITE_SIMD8_MASKED:
997 case SHADER_OPCODE_URB_WRITE_SIMD8_MASKED_PER_SLOT:
998 case FS_OPCODE_FB_WRITE:
999 case FS_OPCODE_FB_WRITE_LOGICAL:
1000 case SHADER_OPCODE_BARRIER:
1001 case TCS_OPCODE_URB_WRITE:
1002 case TCS_OPCODE_RELEASE_INPUT:
1003 return true;
1004 default:
1005 return eot;
1006 }
1007 }
1008
1009 bool
1010 backend_instruction::is_volatile() const
1011 {
1012 switch (opcode) {
1013 case SHADER_OPCODE_UNTYPED_SURFACE_READ:
1014 case SHADER_OPCODE_UNTYPED_SURFACE_READ_LOGICAL:
1015 case SHADER_OPCODE_TYPED_SURFACE_READ:
1016 case SHADER_OPCODE_TYPED_SURFACE_READ_LOGICAL:
1017 case SHADER_OPCODE_URB_READ_SIMD8:
1018 case SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT:
1019 case VEC4_OPCODE_URB_READ:
1020 return true;
1021 default:
1022 return false;
1023 }
1024 }
1025
1026 #ifndef NDEBUG
1027 static bool
1028 inst_is_in_block(const bblock_t *block, const backend_instruction *inst)
1029 {
1030 bool found = false;
1031 foreach_inst_in_block (backend_instruction, i, block) {
1032 if (inst == i) {
1033 found = true;
1034 }
1035 }
1036 return found;
1037 }
1038 #endif
1039
1040 static void
1041 adjust_later_block_ips(bblock_t *start_block, int ip_adjustment)
1042 {
1043 for (bblock_t *block_iter = start_block->next();
1044 block_iter;
1045 block_iter = block_iter->next()) {
1046 block_iter->start_ip += ip_adjustment;
1047 block_iter->end_ip += ip_adjustment;
1048 }
1049 }
1050
1051 void
1052 backend_instruction::insert_after(bblock_t *block, backend_instruction *inst)
1053 {
1054 assert(this != inst);
1055
1056 if (!this->is_head_sentinel())
1057 assert(inst_is_in_block(block, this) || !"Instruction not in block");
1058
1059 block->end_ip++;
1060
1061 adjust_later_block_ips(block, 1);
1062
1063 exec_node::insert_after(inst);
1064 }
1065
1066 void
1067 backend_instruction::insert_before(bblock_t *block, backend_instruction *inst)
1068 {
1069 assert(this != inst);
1070
1071 if (!this->is_tail_sentinel())
1072 assert(inst_is_in_block(block, this) || !"Instruction not in block");
1073
1074 block->end_ip++;
1075
1076 adjust_later_block_ips(block, 1);
1077
1078 exec_node::insert_before(inst);
1079 }
1080
1081 void
1082 backend_instruction::insert_before(bblock_t *block, exec_list *list)
1083 {
1084 assert(inst_is_in_block(block, this) || !"Instruction not in block");
1085
1086 unsigned num_inst = list->length();
1087
1088 block->end_ip += num_inst;
1089
1090 adjust_later_block_ips(block, num_inst);
1091
1092 exec_node::insert_before(list);
1093 }
1094
1095 void
1096 backend_instruction::remove(bblock_t *block)
1097 {
1098 assert(inst_is_in_block(block, this) || !"Instruction not in block");
1099
1100 adjust_later_block_ips(block, -1);
1101
1102 if (block->start_ip == block->end_ip) {
1103 block->cfg->remove_block(block);
1104 } else {
1105 block->end_ip--;
1106 }
1107
1108 exec_node::remove();
1109 }
1110
1111 void
1112 backend_shader::dump_instructions()
1113 {
1114 dump_instructions(NULL);
1115 }
1116
1117 void
1118 backend_shader::dump_instructions(const char *name)
1119 {
1120 FILE *file = stderr;
1121 if (name && geteuid() != 0) {
1122 file = fopen(name, "w");
1123 if (!file)
1124 file = stderr;
1125 }
1126
1127 if (cfg) {
1128 int ip = 0;
1129 foreach_block_and_inst(block, backend_instruction, inst, cfg) {
1130 if (!unlikely(INTEL_DEBUG & DEBUG_OPTIMIZER))
1131 fprintf(file, "%4d: ", ip++);
1132 dump_instruction(inst, file);
1133 }
1134 } else {
1135 int ip = 0;
1136 foreach_in_list(backend_instruction, inst, &instructions) {
1137 if (!unlikely(INTEL_DEBUG & DEBUG_OPTIMIZER))
1138 fprintf(file, "%4d: ", ip++);
1139 dump_instruction(inst, file);
1140 }
1141 }
1142
1143 if (file != stderr) {
1144 fclose(file);
1145 }
1146 }
1147
1148 void
1149 backend_shader::calculate_cfg()
1150 {
1151 if (this->cfg)
1152 return;
1153 cfg = new(mem_ctx) cfg_t(&this->instructions);
1154 }
1155
1156 extern "C" const unsigned *
1157 brw_compile_tes(const struct brw_compiler *compiler,
1158 void *log_data,
1159 void *mem_ctx,
1160 const struct brw_tes_prog_key *key,
1161 const struct brw_vue_map *input_vue_map,
1162 struct brw_tes_prog_data *prog_data,
1163 const nir_shader *src_shader,
1164 struct gl_program *prog,
1165 int shader_time_index,
1166 char **error_str)
1167 {
1168 const struct gen_device_info *devinfo = compiler->devinfo;
1169 const bool is_scalar = compiler->scalar_stage[MESA_SHADER_TESS_EVAL];
1170 const unsigned *assembly;
1171
1172 nir_shader *nir = nir_shader_clone(mem_ctx, src_shader);
1173 nir->info.inputs_read = key->inputs_read;
1174 nir->info.patch_inputs_read = key->patch_inputs_read;
1175
1176 nir = brw_nir_apply_sampler_key(nir, compiler, &key->tex, is_scalar);
1177 brw_nir_lower_tes_inputs(nir, input_vue_map);
1178 brw_nir_lower_vue_outputs(nir, is_scalar);
1179 nir = brw_postprocess_nir(nir, compiler, is_scalar);
1180
1181 brw_compute_vue_map(devinfo, &prog_data->base.vue_map,
1182 nir->info.outputs_written,
1183 nir->info.separate_shader);
1184
1185 unsigned output_size_bytes = prog_data->base.vue_map.num_slots * 4 * 4;
1186
1187 assert(output_size_bytes >= 1);
1188 if (output_size_bytes > GEN7_MAX_DS_URB_ENTRY_SIZE_BYTES) {
1189 if (error_str)
1190 *error_str = ralloc_strdup(mem_ctx, "DS outputs exceed maximum size");
1191 return NULL;
1192 }
1193
1194 prog_data->base.clip_distance_mask =
1195 ((1 << nir->info.clip_distance_array_size) - 1);
1196 prog_data->base.cull_distance_mask =
1197 ((1 << nir->info.cull_distance_array_size) - 1) <<
1198 nir->info.clip_distance_array_size;
1199
1200 /* URB entry sizes are stored as a multiple of 64 bytes. */
1201 prog_data->base.urb_entry_size = ALIGN(output_size_bytes, 64) / 64;
1202
1203 /* On Cannonlake software shall not program an allocation size that
1204 * specifies a size that is a multiple of 3 64B (512-bit) cachelines.
1205 */
1206 if (devinfo->gen == 10 &&
1207 prog_data->base.urb_entry_size % 3 == 0)
1208 prog_data->base.urb_entry_size++;
1209
1210 prog_data->base.urb_read_length = 0;
1211
1212 STATIC_ASSERT(BRW_TESS_PARTITIONING_INTEGER == TESS_SPACING_EQUAL - 1);
1213 STATIC_ASSERT(BRW_TESS_PARTITIONING_ODD_FRACTIONAL ==
1214 TESS_SPACING_FRACTIONAL_ODD - 1);
1215 STATIC_ASSERT(BRW_TESS_PARTITIONING_EVEN_FRACTIONAL ==
1216 TESS_SPACING_FRACTIONAL_EVEN - 1);
1217
1218 prog_data->partitioning =
1219 (enum brw_tess_partitioning) (nir->info.tess.spacing - 1);
1220
1221 switch (nir->info.tess.primitive_mode) {
1222 case GL_QUADS:
1223 prog_data->domain = BRW_TESS_DOMAIN_QUAD;
1224 break;
1225 case GL_TRIANGLES:
1226 prog_data->domain = BRW_TESS_DOMAIN_TRI;
1227 break;
1228 case GL_ISOLINES:
1229 prog_data->domain = BRW_TESS_DOMAIN_ISOLINE;
1230 break;
1231 default:
1232 unreachable("invalid domain shader primitive mode");
1233 }
1234
1235 if (nir->info.tess.point_mode) {
1236 prog_data->output_topology = BRW_TESS_OUTPUT_TOPOLOGY_POINT;
1237 } else if (nir->info.tess.primitive_mode == GL_ISOLINES) {
1238 prog_data->output_topology = BRW_TESS_OUTPUT_TOPOLOGY_LINE;
1239 } else {
1240 /* Hardware winding order is backwards from OpenGL */
1241 prog_data->output_topology =
1242 nir->info.tess.ccw ? BRW_TESS_OUTPUT_TOPOLOGY_TRI_CW
1243 : BRW_TESS_OUTPUT_TOPOLOGY_TRI_CCW;
1244 }
1245
1246 if (unlikely(INTEL_DEBUG & DEBUG_TES)) {
1247 fprintf(stderr, "TES Input ");
1248 brw_print_vue_map(stderr, input_vue_map);
1249 fprintf(stderr, "TES Output ");
1250 brw_print_vue_map(stderr, &prog_data->base.vue_map);
1251 }
1252
1253 if (is_scalar) {
1254 fs_visitor v(compiler, log_data, mem_ctx, (void *) key,
1255 &prog_data->base.base, NULL, nir, 8,
1256 shader_time_index, input_vue_map);
1257 if (!v.run_tes()) {
1258 if (error_str)
1259 *error_str = ralloc_strdup(mem_ctx, v.fail_msg);
1260 return NULL;
1261 }
1262
1263 prog_data->base.base.dispatch_grf_start_reg = v.payload.num_regs;
1264 prog_data->base.dispatch_mode = DISPATCH_MODE_SIMD8;
1265
1266 fs_generator g(compiler, log_data, mem_ctx, (void *) key,
1267 &prog_data->base.base, v.promoted_constants, false,
1268 MESA_SHADER_TESS_EVAL);
1269 if (unlikely(INTEL_DEBUG & DEBUG_TES)) {
1270 g.enable_debug(ralloc_asprintf(mem_ctx,
1271 "%s tessellation evaluation shader %s",
1272 nir->info.label ? nir->info.label
1273 : "unnamed",
1274 nir->info.name));
1275 }
1276
1277 g.generate_code(v.cfg, 8);
1278
1279 assembly = g.get_assembly(&prog_data->base.base.program_size);
1280 } else {
1281 brw::vec4_tes_visitor v(compiler, log_data, key, prog_data,
1282 nir, mem_ctx, shader_time_index);
1283 if (!v.run()) {
1284 if (error_str)
1285 *error_str = ralloc_strdup(mem_ctx, v.fail_msg);
1286 return NULL;
1287 }
1288
1289 if (unlikely(INTEL_DEBUG & DEBUG_TES))
1290 v.dump_instructions();
1291
1292 assembly = brw_vec4_generate_assembly(compiler, log_data, mem_ctx, nir,
1293 &prog_data->base, v.cfg,
1294 &prog_data->base.base.program_size);
1295 }
1296
1297 return assembly;
1298 }