src/intel/compiler/brw_shader.cpp

   1 /*
   2  * Copyright © 2010 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  */
  23
  24 #include "brw_cfg.h"
  25 #include "brw_eu.h"
  26 #include "brw_fs.h"
  27 #include "brw_nir.h"
  28 #include "brw_vec4_tes.h"
  29 #include "common/gen_debug.h"
  30 #include "main/uniforms.h"
  31 #include "util/macros.h"
  32
  33 enum brw_reg_type
  34 brw_type_for_base_type(const struct glsl_type *type)
  35 {
  36    switch (type->base_type) {
  37    case GLSL_TYPE_FLOAT16:
  38       return BRW_REGISTER_TYPE_HF;
  39    case GLSL_TYPE_FLOAT:
  40       return BRW_REGISTER_TYPE_F;
  41    case GLSL_TYPE_INT:
  42    case GLSL_TYPE_BOOL:
  43    case GLSL_TYPE_SUBROUTINE:
  44       return BRW_REGISTER_TYPE_D;
  45    case GLSL_TYPE_INT16:
  46       return BRW_REGISTER_TYPE_W;
  47    case GLSL_TYPE_INT8:
  48       return BRW_REGISTER_TYPE_B;
  49    case GLSL_TYPE_UINT:
  50       return BRW_REGISTER_TYPE_UD;
  51    case GLSL_TYPE_UINT16:
  52       return BRW_REGISTER_TYPE_UW;
  53    case GLSL_TYPE_UINT8:
  54       return BRW_REGISTER_TYPE_UB;
  55    case GLSL_TYPE_ARRAY:
  56       return brw_type_for_base_type(type->fields.array);
  57    case GLSL_TYPE_STRUCT:
  58    case GLSL_TYPE_SAMPLER:
  59    case GLSL_TYPE_ATOMIC_UINT:
  60       /* These should be overridden with the type of the member when
  61        * dereferenced into.  BRW_REGISTER_TYPE_UD seems like a likely
  62        * way to trip up if we don't.
  63        */
  64       return BRW_REGISTER_TYPE_UD;
  65    case GLSL_TYPE_IMAGE:
  66       return BRW_REGISTER_TYPE_UD;
  67    case GLSL_TYPE_DOUBLE:
  68       return BRW_REGISTER_TYPE_DF;
  69    case GLSL_TYPE_UINT64:
  70       return BRW_REGISTER_TYPE_UQ;
  71    case GLSL_TYPE_INT64:
  72       return BRW_REGISTER_TYPE_Q;
  73    case GLSL_TYPE_VOID:
  74    case GLSL_TYPE_ERROR:
  75    case GLSL_TYPE_INTERFACE:
  76    case GLSL_TYPE_FUNCTION:
  77       unreachable("not reached");
  78    }
  79
  80    return BRW_REGISTER_TYPE_F;
  81 }
  82
  83 enum brw_conditional_mod
  84 brw_conditional_for_comparison(unsigned int op)
  85 {
  86    switch (op) {
  87    case ir_binop_less:
  88       return BRW_CONDITIONAL_L;
  89    case ir_binop_gequal:
  90       return BRW_CONDITIONAL_GE;
  91    case ir_binop_equal:
  92    case ir_binop_all_equal: /* same as equal for scalars */
  93       return BRW_CONDITIONAL_Z;
  94    case ir_binop_nequal:
  95    case ir_binop_any_nequal: /* same as nequal for scalars */
  96       return BRW_CONDITIONAL_NZ;
  97    default:
  98       unreachable("not reached: bad operation for comparison");
  99    }
 100 }
 101
 102 uint32_t
 103 brw_math_function(enum opcode op)
 104 {
 105    switch (op) {
 106    case SHADER_OPCODE_RCP:
 107       return BRW_MATH_FUNCTION_INV;
 108    case SHADER_OPCODE_RSQ:
 109       return BRW_MATH_FUNCTION_RSQ;
 110    case SHADER_OPCODE_SQRT:
 111       return BRW_MATH_FUNCTION_SQRT;
 112    case SHADER_OPCODE_EXP2:
 113       return BRW_MATH_FUNCTION_EXP;
 114    case SHADER_OPCODE_LOG2:
 115       return BRW_MATH_FUNCTION_LOG;
 116    case SHADER_OPCODE_POW:
 117       return BRW_MATH_FUNCTION_POW;
 118    case SHADER_OPCODE_SIN:
 119       return BRW_MATH_FUNCTION_SIN;
 120    case SHADER_OPCODE_COS:
 121       return BRW_MATH_FUNCTION_COS;
 122    case SHADER_OPCODE_INT_QUOTIENT:
 123       return BRW_MATH_FUNCTION_INT_DIV_QUOTIENT;
 124    case SHADER_OPCODE_INT_REMAINDER:
 125       return BRW_MATH_FUNCTION_INT_DIV_REMAINDER;
 126    default:
 127       unreachable("not reached: unknown math function");
 128    }
 129 }
 130
 131 bool
 132 brw_texture_offset(int *offsets, unsigned num_components, uint32_t *offset_bits)
 133 {
 134    if (!offsets) return false;  /* nonconstant offset; caller will handle it. */
 135
 136    /* offset out of bounds; caller will handle it. */
 137    for (unsigned i = 0; i < num_components; i++)
 138       if (offsets[i] > 7 || offsets[i] < -8)
 139          return false;
 140
 141    /* Combine all three offsets into a single unsigned dword:
 142     *
 143     *    bits 11:8 - U Offset (X component)
 144     *    bits  7:4 - V Offset (Y component)
 145     *    bits  3:0 - R Offset (Z component)
 146     */
 147    *offset_bits = 0;
 148    for (unsigned i = 0; i < num_components; i++) {
 149       const unsigned shift = 4 * (2 - i);
 150       *offset_bits |= (offsets[i] << shift) & (0xF << shift);
 151    }
 152    return true;
 153 }
 154
 155 const char *
 156 brw_instruction_name(const struct gen_device_info *devinfo, enum opcode op)
 157 {
 158    switch (op) {
 159    case BRW_OPCODE_ILLEGAL ... BRW_OPCODE_NOP:
 160       /* The DO instruction doesn't exist on Gen6+, but we use it to mark the
 161        * start of a loop in the IR.
 162        */
 163       if (devinfo->gen >= 6 && op == BRW_OPCODE_DO)
 164          return "do";
 165
 166       /* The following conversion opcodes doesn't exist on Gen8+, but we use
 167        * then to mark that we want to do the conversion.
 168        */
 169       if (devinfo->gen > 7 && op == BRW_OPCODE_F32TO16)
 170          return "f32to16";
 171
 172       if (devinfo->gen > 7 && op == BRW_OPCODE_F16TO32)
 173          return "f16to32";
 174
 175       assert(brw_opcode_desc(devinfo, op)->name);
 176       return brw_opcode_desc(devinfo, op)->name;
 177    case FS_OPCODE_FB_WRITE:
 178       return "fb_write";
 179    case FS_OPCODE_FB_WRITE_LOGICAL:
 180       return "fb_write_logical";
 181    case FS_OPCODE_REP_FB_WRITE:
 182       return "rep_fb_write";
 183    case FS_OPCODE_FB_READ:
 184       return "fb_read";
 185    case FS_OPCODE_FB_READ_LOGICAL:
 186       return "fb_read_logical";
 187
 188    case SHADER_OPCODE_RCP:
 189       return "rcp";
 190    case SHADER_OPCODE_RSQ:
 191       return "rsq";
 192    case SHADER_OPCODE_SQRT:
 193       return "sqrt";
 194    case SHADER_OPCODE_EXP2:
 195       return "exp2";
 196    case SHADER_OPCODE_LOG2:
 197       return "log2";
 198    case SHADER_OPCODE_POW:
 199       return "pow";
 200    case SHADER_OPCODE_INT_QUOTIENT:
 201       return "int_quot";
 202    case SHADER_OPCODE_INT_REMAINDER:
 203       return "int_rem";
 204    case SHADER_OPCODE_SIN:
 205       return "sin";
 206    case SHADER_OPCODE_COS:
 207       return "cos";
 208
 209    case SHADER_OPCODE_TEX:
 210       return "tex";
 211    case SHADER_OPCODE_TEX_LOGICAL:
 212       return "tex_logical";
 213    case SHADER_OPCODE_TXD:
 214       return "txd";
 215    case SHADER_OPCODE_TXD_LOGICAL:
 216       return "txd_logical";
 217    case SHADER_OPCODE_TXF:
 218       return "txf";
 219    case SHADER_OPCODE_TXF_LOGICAL:
 220       return "txf_logical";
 221    case SHADER_OPCODE_TXF_LZ:
 222       return "txf_lz";
 223    case SHADER_OPCODE_TXL:
 224       return "txl";
 225    case SHADER_OPCODE_TXL_LOGICAL:
 226       return "txl_logical";
 227    case SHADER_OPCODE_TXL_LZ:
 228       return "txl_lz";
 229    case SHADER_OPCODE_TXS:
 230       return "txs";
 231    case SHADER_OPCODE_TXS_LOGICAL:
 232       return "txs_logical";
 233    case FS_OPCODE_TXB:
 234       return "txb";
 235    case FS_OPCODE_TXB_LOGICAL:
 236       return "txb_logical";
 237    case SHADER_OPCODE_TXF_CMS:
 238       return "txf_cms";
 239    case SHADER_OPCODE_TXF_CMS_LOGICAL:
 240       return "txf_cms_logical";
 241    case SHADER_OPCODE_TXF_CMS_W:
 242       return "txf_cms_w";
 243    case SHADER_OPCODE_TXF_CMS_W_LOGICAL:
 244       return "txf_cms_w_logical";
 245    case SHADER_OPCODE_TXF_UMS:
 246       return "txf_ums";
 247    case SHADER_OPCODE_TXF_UMS_LOGICAL:
 248       return "txf_ums_logical";
 249    case SHADER_OPCODE_TXF_MCS:
 250       return "txf_mcs";
 251    case SHADER_OPCODE_TXF_MCS_LOGICAL:
 252       return "txf_mcs_logical";
 253    case SHADER_OPCODE_LOD:
 254       return "lod";
 255    case SHADER_OPCODE_LOD_LOGICAL:
 256       return "lod_logical";
 257    case SHADER_OPCODE_TG4:
 258       return "tg4";
 259    case SHADER_OPCODE_TG4_LOGICAL:
 260       return "tg4_logical";
 261    case SHADER_OPCODE_TG4_OFFSET:
 262       return "tg4_offset";
 263    case SHADER_OPCODE_TG4_OFFSET_LOGICAL:
 264       return "tg4_offset_logical";
 265    case SHADER_OPCODE_SAMPLEINFO:
 266       return "sampleinfo";
 267    case SHADER_OPCODE_SAMPLEINFO_LOGICAL:
 268       return "sampleinfo_logical";
 269
 270    case SHADER_OPCODE_SHADER_TIME_ADD:
 271       return "shader_time_add";
 272
 273    case SHADER_OPCODE_UNTYPED_ATOMIC:
 274       return "untyped_atomic";
 275    case SHADER_OPCODE_UNTYPED_ATOMIC_LOGICAL:
 276       return "untyped_atomic_logical";
 277    case SHADER_OPCODE_UNTYPED_SURFACE_READ:
 278       return "untyped_surface_read";
 279    case SHADER_OPCODE_UNTYPED_SURFACE_READ_LOGICAL:
 280       return "untyped_surface_read_logical";
 281    case SHADER_OPCODE_UNTYPED_SURFACE_WRITE:
 282       return "untyped_surface_write";
 283    case SHADER_OPCODE_UNTYPED_SURFACE_WRITE_LOGICAL:
 284       return "untyped_surface_write_logical";
 285    case SHADER_OPCODE_TYPED_ATOMIC:
 286       return "typed_atomic";
 287    case SHADER_OPCODE_TYPED_ATOMIC_LOGICAL:
 288       return "typed_atomic_logical";
 289    case SHADER_OPCODE_TYPED_SURFACE_READ:
 290       return "typed_surface_read";
 291    case SHADER_OPCODE_TYPED_SURFACE_READ_LOGICAL:
 292       return "typed_surface_read_logical";
 293    case SHADER_OPCODE_TYPED_SURFACE_WRITE:
 294       return "typed_surface_write";
 295    case SHADER_OPCODE_TYPED_SURFACE_WRITE_LOGICAL:
 296       return "typed_surface_write_logical";
 297    case SHADER_OPCODE_MEMORY_FENCE:
 298       return "memory_fence";
 299    case SHADER_OPCODE_INTERLOCK:
 300       /* For an interlock we actually issue a memory fence via sendc. */
 301       return "interlock";
 302
 303    case SHADER_OPCODE_BYTE_SCATTERED_READ:
 304       return "byte_scattered_read";
 305    case SHADER_OPCODE_BYTE_SCATTERED_READ_LOGICAL:
 306       return "byte_scattered_read_logical";
 307    case SHADER_OPCODE_BYTE_SCATTERED_WRITE:
 308       return "byte_scattered_write";
 309    case SHADER_OPCODE_BYTE_SCATTERED_WRITE_LOGICAL:
 310       return "byte_scattered_write_logical";
 311
 312    case SHADER_OPCODE_LOAD_PAYLOAD:
 313       return "load_payload";
 314    case FS_OPCODE_PACK:
 315       return "pack";
 316
 317    case SHADER_OPCODE_GEN4_SCRATCH_READ:
 318       return "gen4_scratch_read";
 319    case SHADER_OPCODE_GEN4_SCRATCH_WRITE:
 320       return "gen4_scratch_write";
 321    case SHADER_OPCODE_GEN7_SCRATCH_READ:
 322       return "gen7_scratch_read";
 323    case SHADER_OPCODE_URB_WRITE_SIMD8:
 324       return "gen8_urb_write_simd8";
 325    case SHADER_OPCODE_URB_WRITE_SIMD8_PER_SLOT:
 326       return "gen8_urb_write_simd8_per_slot";
 327    case SHADER_OPCODE_URB_WRITE_SIMD8_MASKED:
 328       return "gen8_urb_write_simd8_masked";
 329    case SHADER_OPCODE_URB_WRITE_SIMD8_MASKED_PER_SLOT:
 330       return "gen8_urb_write_simd8_masked_per_slot";
 331    case SHADER_OPCODE_URB_READ_SIMD8:
 332       return "urb_read_simd8";
 333    case SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT:
 334       return "urb_read_simd8_per_slot";
 335
 336    case SHADER_OPCODE_FIND_LIVE_CHANNEL:
 337       return "find_live_channel";
 338    case SHADER_OPCODE_BROADCAST:
 339       return "broadcast";
 340    case SHADER_OPCODE_SHUFFLE:
 341       return "shuffle";
 342    case SHADER_OPCODE_SEL_EXEC:
 343       return "sel_exec";
 344    case SHADER_OPCODE_QUAD_SWIZZLE:
 345       return "quad_swizzle";
 346    case SHADER_OPCODE_CLUSTER_BROADCAST:
 347       return "cluster_broadcast";
 348
 349    case SHADER_OPCODE_GET_BUFFER_SIZE:
 350       return "get_buffer_size";
 351
 352    case VEC4_OPCODE_MOV_BYTES:
 353       return "mov_bytes";
 354    case VEC4_OPCODE_PACK_BYTES:
 355       return "pack_bytes";
 356    case VEC4_OPCODE_UNPACK_UNIFORM:
 357       return "unpack_uniform";
 358    case VEC4_OPCODE_DOUBLE_TO_F32:
 359       return "double_to_f32";
 360    case VEC4_OPCODE_DOUBLE_TO_D32:
 361       return "double_to_d32";
 362    case VEC4_OPCODE_DOUBLE_TO_U32:
 363       return "double_to_u32";
 364    case VEC4_OPCODE_TO_DOUBLE:
 365       return "single_to_double";
 366    case VEC4_OPCODE_PICK_LOW_32BIT:
 367       return "pick_low_32bit";
 368    case VEC4_OPCODE_PICK_HIGH_32BIT:
 369       return "pick_high_32bit";
 370    case VEC4_OPCODE_SET_LOW_32BIT:
 371       return "set_low_32bit";
 372    case VEC4_OPCODE_SET_HIGH_32BIT:
 373       return "set_high_32bit";
 374
 375    case FS_OPCODE_DDX_COARSE:
 376       return "ddx_coarse";
 377    case FS_OPCODE_DDX_FINE:
 378       return "ddx_fine";
 379    case FS_OPCODE_DDY_COARSE:
 380       return "ddy_coarse";
 381    case FS_OPCODE_DDY_FINE:
 382       return "ddy_fine";
 383
 384    case FS_OPCODE_LINTERP:
 385       return "linterp";
 386
 387    case FS_OPCODE_PIXEL_X:
 388       return "pixel_x";
 389    case FS_OPCODE_PIXEL_Y:
 390       return "pixel_y";
 391
 392    case FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD:
 393       return "uniform_pull_const";
 394    case FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD_GEN7:
 395       return "uniform_pull_const_gen7";
 396    case FS_OPCODE_VARYING_PULL_CONSTANT_LOAD_GEN4:
 397       return "varying_pull_const_gen4";
 398    case FS_OPCODE_VARYING_PULL_CONSTANT_LOAD_GEN7:
 399       return "varying_pull_const_gen7";
 400    case FS_OPCODE_VARYING_PULL_CONSTANT_LOAD_LOGICAL:
 401       return "varying_pull_const_logical";
 402
 403    case FS_OPCODE_MOV_DISPATCH_TO_FLAGS:
 404       return "mov_dispatch_to_flags";
 405    case FS_OPCODE_DISCARD_JUMP:
 406       return "discard_jump";
 407
 408    case FS_OPCODE_SET_SAMPLE_ID:
 409       return "set_sample_id";
 410
 411    case FS_OPCODE_PACK_HALF_2x16_SPLIT:
 412       return "pack_half_2x16_split";
 413    case FS_OPCODE_UNPACK_HALF_2x16_SPLIT_X:
 414       return "unpack_half_2x16_split_x";
 415    case FS_OPCODE_UNPACK_HALF_2x16_SPLIT_Y:
 416       return "unpack_half_2x16_split_y";
 417
 418    case FS_OPCODE_PLACEHOLDER_HALT:
 419       return "placeholder_halt";
 420
 421    case FS_OPCODE_INTERPOLATE_AT_SAMPLE:
 422       return "interp_sample";
 423    case FS_OPCODE_INTERPOLATE_AT_SHARED_OFFSET:
 424       return "interp_shared_offset";
 425    case FS_OPCODE_INTERPOLATE_AT_PER_SLOT_OFFSET:
 426       return "interp_per_slot_offset";
 427
 428    case VS_OPCODE_URB_WRITE:
 429       return "vs_urb_write";
 430    case VS_OPCODE_PULL_CONSTANT_LOAD:
 431       return "pull_constant_load";
 432    case VS_OPCODE_PULL_CONSTANT_LOAD_GEN7:
 433       return "pull_constant_load_gen7";
 434
 435    case VS_OPCODE_SET_SIMD4X2_HEADER_GEN9:
 436       return "set_simd4x2_header_gen9";
 437
 438    case VS_OPCODE_UNPACK_FLAGS_SIMD4X2:
 439       return "unpack_flags_simd4x2";
 440
 441    case GS_OPCODE_URB_WRITE:
 442       return "gs_urb_write";
 443    case GS_OPCODE_URB_WRITE_ALLOCATE:
 444       return "gs_urb_write_allocate";
 445    case GS_OPCODE_THREAD_END:
 446       return "gs_thread_end";
 447    case GS_OPCODE_SET_WRITE_OFFSET:
 448       return "set_write_offset";
 449    case GS_OPCODE_SET_VERTEX_COUNT:
 450       return "set_vertex_count";
 451    case GS_OPCODE_SET_DWORD_2:
 452       return "set_dword_2";
 453    case GS_OPCODE_PREPARE_CHANNEL_MASKS:
 454       return "prepare_channel_masks";
 455    case GS_OPCODE_SET_CHANNEL_MASKS:
 456       return "set_channel_masks";
 457    case GS_OPCODE_GET_INSTANCE_ID:
 458       return "get_instance_id";
 459    case GS_OPCODE_FF_SYNC:
 460       return "ff_sync";
 461    case GS_OPCODE_SET_PRIMITIVE_ID:
 462       return "set_primitive_id";
 463    case GS_OPCODE_SVB_WRITE:
 464       return "gs_svb_write";
 465    case GS_OPCODE_SVB_SET_DST_INDEX:
 466       return "gs_svb_set_dst_index";
 467    case GS_OPCODE_FF_SYNC_SET_PRIMITIVES:
 468       return "gs_ff_sync_set_primitives";
 469    case CS_OPCODE_CS_TERMINATE:
 470       return "cs_terminate";
 471    case SHADER_OPCODE_BARRIER:
 472       return "barrier";
 473    case SHADER_OPCODE_MULH:
 474       return "mulh";
 475    case SHADER_OPCODE_MOV_INDIRECT:
 476       return "mov_indirect";
 477
 478    case VEC4_OPCODE_URB_READ:
 479       return "urb_read";
 480    case TCS_OPCODE_GET_INSTANCE_ID:
 481       return "tcs_get_instance_id";
 482    case TCS_OPCODE_URB_WRITE:
 483       return "tcs_urb_write";
 484    case TCS_OPCODE_SET_INPUT_URB_OFFSETS:
 485       return "tcs_set_input_urb_offsets";
 486    case TCS_OPCODE_SET_OUTPUT_URB_OFFSETS:
 487       return "tcs_set_output_urb_offsets";
 488    case TCS_OPCODE_GET_PRIMITIVE_ID:
 489       return "tcs_get_primitive_id";
 490    case TCS_OPCODE_CREATE_BARRIER_HEADER:
 491       return "tcs_create_barrier_header";
 492    case TCS_OPCODE_SRC0_010_IS_ZERO:
 493       return "tcs_src0<0,1,0>_is_zero";
 494    case TCS_OPCODE_RELEASE_INPUT:
 495       return "tcs_release_input";
 496    case TCS_OPCODE_THREAD_END:
 497       return "tcs_thread_end";
 498    case TES_OPCODE_CREATE_INPUT_READ_HEADER:
 499       return "tes_create_input_read_header";
 500    case TES_OPCODE_ADD_INDIRECT_URB_OFFSET:
 501       return "tes_add_indirect_urb_offset";
 502    case TES_OPCODE_GET_PRIMITIVE_ID:
 503       return "tes_get_primitive_id";
 504
 505    case SHADER_OPCODE_RND_MODE:
 506       return "rnd_mode";
 507    }
 508
 509    unreachable("not reached");
 510 }
 511
 512 bool
 513 brw_saturate_immediate(enum brw_reg_type type, struct brw_reg *reg)
 514 {
 515    union {
 516       unsigned ud;
 517       int d;
 518       float f;
 519       double df;
 520    } imm, sat_imm = { 0 };
 521
 522    const unsigned size = type_sz(type);
 523
 524    /* We want to either do a 32-bit or 64-bit data copy, the type is otherwise
 525     * irrelevant, so just check the size of the type and copy from/to an
 526     * appropriately sized field.
 527     */
 528    if (size < 8)
 529       imm.ud = reg->ud;
 530    else
 531       imm.df = reg->df;
 532
 533    switch (type) {
 534    case BRW_REGISTER_TYPE_UD:
 535    case BRW_REGISTER_TYPE_D:
 536    case BRW_REGISTER_TYPE_UW:
 537    case BRW_REGISTER_TYPE_W:
 538    case BRW_REGISTER_TYPE_UQ:
 539    case BRW_REGISTER_TYPE_Q:
 540       /* Nothing to do. */
 541       return false;
 542    case BRW_REGISTER_TYPE_F:
 543       sat_imm.f = CLAMP(imm.f, 0.0f, 1.0f);
 544       break;
 545    case BRW_REGISTER_TYPE_DF:
 546       sat_imm.df = CLAMP(imm.df, 0.0, 1.0);
 547       break;
 548    case BRW_REGISTER_TYPE_UB:
 549    case BRW_REGISTER_TYPE_B:
 550       unreachable("no UB/B immediates");
 551    case BRW_REGISTER_TYPE_V:
 552    case BRW_REGISTER_TYPE_UV:
 553    case BRW_REGISTER_TYPE_VF:
 554       unreachable("unimplemented: saturate vector immediate");
 555    case BRW_REGISTER_TYPE_HF:
 556       unreachable("unimplemented: saturate HF immediate");
 557    case BRW_REGISTER_TYPE_NF:
 558       unreachable("no NF immediates");
 559    }
 560
 561    if (size < 8) {
 562       if (imm.ud != sat_imm.ud) {
 563          reg->ud = sat_imm.ud;
 564          return true;
 565       }
 566    } else {
 567       if (imm.df != sat_imm.df) {
 568          reg->df = sat_imm.df;
 569          return true;
 570       }
 571    }
 572    return false;
 573 }
 574
 575 bool
 576 brw_negate_immediate(enum brw_reg_type type, struct brw_reg *reg)
 577 {
 578    switch (type) {
 579    case BRW_REGISTER_TYPE_D:
 580    case BRW_REGISTER_TYPE_UD:
 581       reg->d = -reg->d;
 582       return true;
 583    case BRW_REGISTER_TYPE_W:
 584    case BRW_REGISTER_TYPE_UW: {
 585       uint16_t value = -(int16_t)reg->ud;
 586       reg->ud = value | (uint32_t)value << 16;
 587       return true;
 588    }
 589    case BRW_REGISTER_TYPE_F:
 590       reg->f = -reg->f;
 591       return true;
 592    case BRW_REGISTER_TYPE_VF:
 593       reg->ud ^= 0x80808080;
 594       return true;
 595    case BRW_REGISTER_TYPE_DF:
 596       reg->df = -reg->df;
 597       return true;
 598    case BRW_REGISTER_TYPE_UQ:
 599    case BRW_REGISTER_TYPE_Q:
 600       reg->d64 = -reg->d64;
 601       return true;
 602    case BRW_REGISTER_TYPE_UB:
 603    case BRW_REGISTER_TYPE_B:
 604       unreachable("no UB/B immediates");
 605    case BRW_REGISTER_TYPE_UV:
 606    case BRW_REGISTER_TYPE_V:
 607       assert(!"unimplemented: negate UV/V immediate");
 608    case BRW_REGISTER_TYPE_HF:
 609       reg->ud ^= 0x80008000;
 610       return true;
 611    case BRW_REGISTER_TYPE_NF:
 612       unreachable("no NF immediates");
 613    }
 614
 615    return false;
 616 }
 617
 618 bool
 619 brw_abs_immediate(enum brw_reg_type type, struct brw_reg *reg)
 620 {
 621    switch (type) {
 622    case BRW_REGISTER_TYPE_D:
 623       reg->d = abs(reg->d);
 624       return true;
 625    case BRW_REGISTER_TYPE_W: {
 626       uint16_t value = abs((int16_t)reg->ud);
 627       reg->ud = value | (uint32_t)value << 16;
 628       return true;
 629    }
 630    case BRW_REGISTER_TYPE_F:
 631       reg->f = fabsf(reg->f);
 632       return true;
 633    case BRW_REGISTER_TYPE_DF:
 634       reg->df = fabs(reg->df);
 635       return true;
 636    case BRW_REGISTER_TYPE_VF:
 637       reg->ud &= ~0x80808080;
 638       return true;
 639    case BRW_REGISTER_TYPE_Q:
 640       reg->d64 = imaxabs(reg->d64);
 641       return true;
 642    case BRW_REGISTER_TYPE_UB:
 643    case BRW_REGISTER_TYPE_B:
 644       unreachable("no UB/B immediates");
 645    case BRW_REGISTER_TYPE_UQ:
 646    case BRW_REGISTER_TYPE_UD:
 647    case BRW_REGISTER_TYPE_UW:
 648    case BRW_REGISTER_TYPE_UV:
 649       /* Presumably the absolute value modifier on an unsigned source is a
 650        * nop, but it would be nice to confirm.
 651        */
 652       assert(!"unimplemented: abs unsigned immediate");
 653    case BRW_REGISTER_TYPE_V:
 654       assert(!"unimplemented: abs V immediate");
 655    case BRW_REGISTER_TYPE_HF:
 656       reg->ud &= ~0x80008000;
 657       return true;
 658    case BRW_REGISTER_TYPE_NF:
 659       unreachable("no NF immediates");
 660    }
 661
 662    return false;
 663 }
 664
 665 backend_shader::backend_shader(const struct brw_compiler *compiler,
 666                                void *log_data,
 667                                void *mem_ctx,
 668                                const nir_shader *shader,
 669                                struct brw_stage_prog_data *stage_prog_data)
 670    : compiler(compiler),
 671      log_data(log_data),
 672      devinfo(compiler->devinfo),
 673      nir(shader),
 674      stage_prog_data(stage_prog_data),
 675      mem_ctx(mem_ctx),
 676      cfg(NULL),
 677      stage(shader->info.stage)
 678 {
 679    debug_enabled = INTEL_DEBUG & intel_debug_flag_for_shader_stage(stage);
 680    stage_name = _mesa_shader_stage_to_string(stage);
 681    stage_abbrev = _mesa_shader_stage_to_abbrev(stage);
 682 }
 683
 684 backend_shader::~backend_shader()
 685 {
 686 }
 687
 688 bool
 689 backend_reg::equals(const backend_reg &r) const
 690 {
 691    return brw_regs_equal(this, &r) && offset == r.offset;
 692 }
 693
 694 bool
 695 backend_reg::negative_equals(const backend_reg &r) const
 696 {
 697    return brw_regs_negative_equal(this, &r) && offset == r.offset;
 698 }
 699
 700 bool
 701 backend_reg::is_zero() const
 702 {
 703    if (file != IMM)
 704       return false;
 705
 706    switch (type) {
 707    case BRW_REGISTER_TYPE_F:
 708       return f == 0;
 709    case BRW_REGISTER_TYPE_DF:
 710       return df == 0;
 711    case BRW_REGISTER_TYPE_D:
 712    case BRW_REGISTER_TYPE_UD:
 713       return d == 0;
 714    case BRW_REGISTER_TYPE_UQ:
 715    case BRW_REGISTER_TYPE_Q:
 716       return u64 == 0;
 717    default:
 718       return false;
 719    }
 720 }
 721
 722 bool
 723 backend_reg::is_one() const
 724 {
 725    if (file != IMM)
 726       return false;
 727
 728    switch (type) {
 729    case BRW_REGISTER_TYPE_F:
 730       return f == 1.0f;
 731    case BRW_REGISTER_TYPE_DF:
 732       return df == 1.0;
 733    case BRW_REGISTER_TYPE_D:
 734    case BRW_REGISTER_TYPE_UD:
 735       return d == 1;
 736    case BRW_REGISTER_TYPE_UQ:
 737    case BRW_REGISTER_TYPE_Q:
 738       return u64 == 1;
 739    default:
 740       return false;
 741    }
 742 }
 743
 744 bool
 745 backend_reg::is_negative_one() const
 746 {
 747    if (file != IMM)
 748       return false;
 749
 750    switch (type) {
 751    case BRW_REGISTER_TYPE_F:
 752       return f == -1.0;
 753    case BRW_REGISTER_TYPE_DF:
 754       return df == -1.0;
 755    case BRW_REGISTER_TYPE_D:
 756       return d == -1;
 757    case BRW_REGISTER_TYPE_Q:
 758       return d64 == -1;
 759    default:
 760       return false;
 761    }
 762 }
 763
 764 bool
 765 backend_reg::is_null() const
 766 {
 767    return file == ARF && nr == BRW_ARF_NULL;
 768 }
 769
 770
 771 bool
 772 backend_reg::is_accumulator() const
 773 {
 774    return file == ARF && nr == BRW_ARF_ACCUMULATOR;
 775 }
 776
 777 bool
 778 backend_instruction::is_commutative() const
 779 {
 780    switch (opcode) {
 781    case BRW_OPCODE_AND:
 782    case BRW_OPCODE_OR:
 783    case BRW_OPCODE_XOR:
 784    case BRW_OPCODE_ADD:
 785    case BRW_OPCODE_MUL:
 786    case SHADER_OPCODE_MULH:
 787       return true;
 788    case BRW_OPCODE_SEL:
 789       /* MIN and MAX are commutative. */
 790       if (conditional_mod == BRW_CONDITIONAL_GE ||
 791           conditional_mod == BRW_CONDITIONAL_L) {
 792          return true;
 793       }
 794       /* fallthrough */
 795    default:
 796       return false;
 797    }
 798 }
 799
 800 bool
 801 backend_instruction::is_3src(const struct gen_device_info *devinfo) const
 802 {
 803    return ::is_3src(devinfo, opcode);
 804 }
 805
 806 bool
 807 backend_instruction::is_tex() const
 808 {
 809    return (opcode == SHADER_OPCODE_TEX ||
 810            opcode == FS_OPCODE_TXB ||
 811            opcode == SHADER_OPCODE_TXD ||
 812            opcode == SHADER_OPCODE_TXF ||
 813            opcode == SHADER_OPCODE_TXF_LZ ||
 814            opcode == SHADER_OPCODE_TXF_CMS ||
 815            opcode == SHADER_OPCODE_TXF_CMS_W ||
 816            opcode == SHADER_OPCODE_TXF_UMS ||
 817            opcode == SHADER_OPCODE_TXF_MCS ||
 818            opcode == SHADER_OPCODE_TXL ||
 819            opcode == SHADER_OPCODE_TXL_LZ ||
 820            opcode == SHADER_OPCODE_TXS ||
 821            opcode == SHADER_OPCODE_LOD ||
 822            opcode == SHADER_OPCODE_TG4 ||
 823            opcode == SHADER_OPCODE_TG4_OFFSET ||
 824            opcode == SHADER_OPCODE_SAMPLEINFO);
 825 }
 826
 827 bool
 828 backend_instruction::is_math() const
 829 {
 830    return (opcode == SHADER_OPCODE_RCP ||
 831            opcode == SHADER_OPCODE_RSQ ||
 832            opcode == SHADER_OPCODE_SQRT ||
 833            opcode == SHADER_OPCODE_EXP2 ||
 834            opcode == SHADER_OPCODE_LOG2 ||
 835            opcode == SHADER_OPCODE_SIN ||
 836            opcode == SHADER_OPCODE_COS ||
 837            opcode == SHADER_OPCODE_INT_QUOTIENT ||
 838            opcode == SHADER_OPCODE_INT_REMAINDER ||
 839            opcode == SHADER_OPCODE_POW);
 840 }
 841
 842 bool
 843 backend_instruction::is_control_flow() const
 844 {
 845    switch (opcode) {
 846    case BRW_OPCODE_DO:
 847    case BRW_OPCODE_WHILE:
 848    case BRW_OPCODE_IF:
 849    case BRW_OPCODE_ELSE:
 850    case BRW_OPCODE_ENDIF:
 851    case BRW_OPCODE_BREAK:
 852    case BRW_OPCODE_CONTINUE:
 853       return true;
 854    default:
 855       return false;
 856    }
 857 }
 858
 859 bool
 860 backend_instruction::can_do_source_mods() const
 861 {
 862    switch (opcode) {
 863    case BRW_OPCODE_ADDC:
 864    case BRW_OPCODE_BFE:
 865    case BRW_OPCODE_BFI1:
 866    case BRW_OPCODE_BFI2:
 867    case BRW_OPCODE_BFREV:
 868    case BRW_OPCODE_CBIT:
 869    case BRW_OPCODE_FBH:
 870    case BRW_OPCODE_FBL:
 871    case BRW_OPCODE_SUBB:
 872    case SHADER_OPCODE_BROADCAST:
 873    case SHADER_OPCODE_CLUSTER_BROADCAST:
 874    case SHADER_OPCODE_MOV_INDIRECT:
 875       return false;
 876    default:
 877       return true;
 878    }
 879 }
 880
 881 bool
 882 backend_instruction::can_do_saturate() const
 883 {
 884    switch (opcode) {
 885    case BRW_OPCODE_ADD:
 886    case BRW_OPCODE_ASR:
 887    case BRW_OPCODE_AVG:
 888    case BRW_OPCODE_DP2:
 889    case BRW_OPCODE_DP3:
 890    case BRW_OPCODE_DP4:
 891    case BRW_OPCODE_DPH:
 892    case BRW_OPCODE_F16TO32:
 893    case BRW_OPCODE_F32TO16:
 894    case BRW_OPCODE_LINE:
 895    case BRW_OPCODE_LRP:
 896    case BRW_OPCODE_MAC:
 897    case BRW_OPCODE_MAD:
 898    case BRW_OPCODE_MATH:
 899    case BRW_OPCODE_MOV:
 900    case BRW_OPCODE_MUL:
 901    case SHADER_OPCODE_MULH:
 902    case BRW_OPCODE_PLN:
 903    case BRW_OPCODE_RNDD:
 904    case BRW_OPCODE_RNDE:
 905    case BRW_OPCODE_RNDU:
 906    case BRW_OPCODE_RNDZ:
 907    case BRW_OPCODE_SEL:
 908    case BRW_OPCODE_SHL:
 909    case BRW_OPCODE_SHR:
 910    case FS_OPCODE_LINTERP:
 911    case SHADER_OPCODE_COS:
 912    case SHADER_OPCODE_EXP2:
 913    case SHADER_OPCODE_LOG2:
 914    case SHADER_OPCODE_POW:
 915    case SHADER_OPCODE_RCP:
 916    case SHADER_OPCODE_RSQ:
 917    case SHADER_OPCODE_SIN:
 918    case SHADER_OPCODE_SQRT:
 919       return true;
 920    default:
 921       return false;
 922    }
 923 }
 924
 925 bool
 926 backend_instruction::can_do_cmod() const
 927 {
 928    switch (opcode) {
 929    case BRW_OPCODE_ADD:
 930    case BRW_OPCODE_ADDC:
 931    case BRW_OPCODE_AND:
 932    case BRW_OPCODE_ASR:
 933    case BRW_OPCODE_AVG:
 934    case BRW_OPCODE_CMP:
 935    case BRW_OPCODE_CMPN:
 936    case BRW_OPCODE_DP2:
 937    case BRW_OPCODE_DP3:
 938    case BRW_OPCODE_DP4:
 939    case BRW_OPCODE_DPH:
 940    case BRW_OPCODE_F16TO32:
 941    case BRW_OPCODE_F32TO16:
 942    case BRW_OPCODE_FRC:
 943    case BRW_OPCODE_LINE:
 944    case BRW_OPCODE_LRP:
 945    case BRW_OPCODE_LZD:
 946    case BRW_OPCODE_MAC:
 947    case BRW_OPCODE_MACH:
 948    case BRW_OPCODE_MAD:
 949    case BRW_OPCODE_MOV:
 950    case BRW_OPCODE_MUL:
 951    case BRW_OPCODE_NOT:
 952    case BRW_OPCODE_OR:
 953    case BRW_OPCODE_PLN:
 954    case BRW_OPCODE_RNDD:
 955    case BRW_OPCODE_RNDE:
 956    case BRW_OPCODE_RNDU:
 957    case BRW_OPCODE_RNDZ:
 958    case BRW_OPCODE_SAD2:
 959    case BRW_OPCODE_SADA2:
 960    case BRW_OPCODE_SHL:
 961    case BRW_OPCODE_SHR:
 962    case BRW_OPCODE_SUBB:
 963    case BRW_OPCODE_XOR:
 964    case FS_OPCODE_LINTERP:
 965       return true;
 966    default:
 967       return false;
 968    }
 969 }
 970
 971 bool
 972 backend_instruction::reads_accumulator_implicitly() const
 973 {
 974    switch (opcode) {
 975    case BRW_OPCODE_MAC:
 976    case BRW_OPCODE_MACH:
 977    case BRW_OPCODE_SADA2:
 978       return true;
 979    default:
 980       return false;
 981    }
 982 }
 983
 984 bool
 985 backend_instruction::writes_accumulator_implicitly(const struct gen_device_info *devinfo) const
 986 {
 987    return writes_accumulator ||
 988           (devinfo->gen < 6 &&
 989            ((opcode >= BRW_OPCODE_ADD && opcode < BRW_OPCODE_NOP) ||
 990             (opcode >= FS_OPCODE_DDX_COARSE && opcode <= FS_OPCODE_LINTERP))) ||
 991           (opcode == FS_OPCODE_LINTERP && !devinfo->has_pln);
 992 }
 993
 994 bool
 995 backend_instruction::has_side_effects() const
 996 {
 997    switch (opcode) {
 998    case SHADER_OPCODE_UNTYPED_ATOMIC:
 999    case SHADER_OPCODE_UNTYPED_ATOMIC_LOGICAL:
1000    case SHADER_OPCODE_GEN4_SCRATCH_WRITE:
1001    case SHADER_OPCODE_UNTYPED_SURFACE_WRITE:
1002    case SHADER_OPCODE_UNTYPED_SURFACE_WRITE_LOGICAL:
1003    case SHADER_OPCODE_BYTE_SCATTERED_WRITE:
1004    case SHADER_OPCODE_BYTE_SCATTERED_WRITE_LOGICAL:
1005    case SHADER_OPCODE_TYPED_ATOMIC:
1006    case SHADER_OPCODE_TYPED_ATOMIC_LOGICAL:
1007    case SHADER_OPCODE_TYPED_SURFACE_WRITE:
1008    case SHADER_OPCODE_TYPED_SURFACE_WRITE_LOGICAL:
1009    case SHADER_OPCODE_MEMORY_FENCE:
1010    case SHADER_OPCODE_INTERLOCK:
1011    case SHADER_OPCODE_URB_WRITE_SIMD8:
1012    case SHADER_OPCODE_URB_WRITE_SIMD8_PER_SLOT:
1013    case SHADER_OPCODE_URB_WRITE_SIMD8_MASKED:
1014    case SHADER_OPCODE_URB_WRITE_SIMD8_MASKED_PER_SLOT:
1015    case FS_OPCODE_FB_WRITE:
1016    case FS_OPCODE_FB_WRITE_LOGICAL:
1017    case FS_OPCODE_REP_FB_WRITE:
1018    case SHADER_OPCODE_BARRIER:
1019    case TCS_OPCODE_URB_WRITE:
1020    case TCS_OPCODE_RELEASE_INPUT:
1021    case SHADER_OPCODE_RND_MODE:
1022       return true;
1023    default:
1024       return eot;
1025    }
1026 }
1027
1028 bool
1029 backend_instruction::is_volatile() const
1030 {
1031    switch (opcode) {
1032    case SHADER_OPCODE_UNTYPED_SURFACE_READ:
1033    case SHADER_OPCODE_UNTYPED_SURFACE_READ_LOGICAL:
1034    case SHADER_OPCODE_TYPED_SURFACE_READ:
1035    case SHADER_OPCODE_TYPED_SURFACE_READ_LOGICAL:
1036    case SHADER_OPCODE_BYTE_SCATTERED_READ:
1037    case SHADER_OPCODE_BYTE_SCATTERED_READ_LOGICAL:
1038    case SHADER_OPCODE_URB_READ_SIMD8:
1039    case SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT:
1040    case VEC4_OPCODE_URB_READ:
1041       return true;
1042    default:
1043       return false;
1044    }
1045 }
1046
1047 #ifndef NDEBUG
1048 static bool
1049 inst_is_in_block(const bblock_t *block, const backend_instruction *inst)
1050 {
1051    bool found = false;
1052    foreach_inst_in_block (backend_instruction, i, block) {
1053       if (inst == i) {
1054          found = true;
1055       }
1056    }
1057    return found;
1058 }
1059 #endif
1060
1061 static void
1062 adjust_later_block_ips(bblock_t *start_block, int ip_adjustment)
1063 {
1064    for (bblock_t *block_iter = start_block->next();
1065         block_iter;
1066         block_iter = block_iter->next()) {
1067       block_iter->start_ip += ip_adjustment;
1068       block_iter->end_ip += ip_adjustment;
1069    }
1070 }
1071
1072 void
1073 backend_instruction::insert_after(bblock_t *block, backend_instruction *inst)
1074 {
1075    assert(this != inst);
1076
1077    if (!this->is_head_sentinel())
1078       assert(inst_is_in_block(block, this) || !"Instruction not in block");
1079
1080    block->end_ip++;
1081
1082    adjust_later_block_ips(block, 1);
1083
1084    exec_node::insert_after(inst);
1085 }
1086
1087 void
1088 backend_instruction::insert_before(bblock_t *block, backend_instruction *inst)
1089 {
1090    assert(this != inst);
1091
1092    if (!this->is_tail_sentinel())
1093       assert(inst_is_in_block(block, this) || !"Instruction not in block");
1094
1095    block->end_ip++;
1096
1097    adjust_later_block_ips(block, 1);
1098
1099    exec_node::insert_before(inst);
1100 }
1101
1102 void
1103 backend_instruction::insert_before(bblock_t *block, exec_list *list)
1104 {
1105    assert(inst_is_in_block(block, this) || !"Instruction not in block");
1106
1107    unsigned num_inst = list->length();
1108
1109    block->end_ip += num_inst;
1110
1111    adjust_later_block_ips(block, num_inst);
1112
1113    exec_node::insert_before(list);
1114 }
1115
1116 void
1117 backend_instruction::remove(bblock_t *block)
1118 {
1119    assert(inst_is_in_block(block, this) || !"Instruction not in block");
1120
1121    adjust_later_block_ips(block, -1);
1122
1123    if (block->start_ip == block->end_ip) {
1124       block->cfg->remove_block(block);
1125    } else {
1126       block->end_ip--;
1127    }
1128
1129    exec_node::remove();
1130 }
1131
1132 void
1133 backend_shader::dump_instructions()
1134 {
1135    dump_instructions(NULL);
1136 }
1137
1138 void
1139 backend_shader::dump_instructions(const char *name)
1140 {
1141    FILE *file = stderr;
1142    if (name && geteuid() != 0) {
1143       file = fopen(name, "w");
1144       if (!file)
1145          file = stderr;
1146    }
1147
1148    if (cfg) {
1149       int ip = 0;
1150       foreach_block_and_inst(block, backend_instruction, inst, cfg) {
1151          if (!unlikely(INTEL_DEBUG & DEBUG_OPTIMIZER))
1152             fprintf(file, "%4d: ", ip++);
1153          dump_instruction(inst, file);
1154       }
1155    } else {
1156       int ip = 0;
1157       foreach_in_list(backend_instruction, inst, &instructions) {
1158          if (!unlikely(INTEL_DEBUG & DEBUG_OPTIMIZER))
1159             fprintf(file, "%4d: ", ip++);
1160          dump_instruction(inst, file);
1161       }
1162    }
1163
1164    if (file != stderr) {
1165       fclose(file);
1166    }
1167 }
1168
1169 void
1170 backend_shader::calculate_cfg()
1171 {
1172    if (this->cfg)
1173       return;
1174    cfg = new(mem_ctx) cfg_t(&this->instructions);
1175 }
1176
1177 extern "C" const unsigned *
1178 brw_compile_tes(const struct brw_compiler *compiler,
1179                 void *log_data,
1180                 void *mem_ctx,
1181                 const struct brw_tes_prog_key *key,
1182                 const struct brw_vue_map *input_vue_map,
1183                 struct brw_tes_prog_data *prog_data,
1184                 const nir_shader *src_shader,
1185                 struct gl_program *prog,
1186                 int shader_time_index,
1187                 char **error_str)
1188 {
1189    const struct gen_device_info *devinfo = compiler->devinfo;
1190    const bool is_scalar = compiler->scalar_stage[MESA_SHADER_TESS_EVAL];
1191    const unsigned *assembly;
1192
1193    nir_shader *nir = nir_shader_clone(mem_ctx, src_shader);
1194    nir->info.inputs_read = key->inputs_read;
1195    nir->info.patch_inputs_read = key->patch_inputs_read;
1196
1197    nir = brw_nir_apply_sampler_key(nir, compiler, &key->tex, is_scalar);
1198    brw_nir_lower_tes_inputs(nir, input_vue_map);
1199    brw_nir_lower_vue_outputs(nir, is_scalar);
1200    nir = brw_postprocess_nir(nir, compiler, is_scalar);
1201
1202    brw_compute_vue_map(devinfo, &prog_data->base.vue_map,
1203                        nir->info.outputs_written,
1204                        nir->info.separate_shader);
1205
1206    unsigned output_size_bytes = prog_data->base.vue_map.num_slots * 4 * 4;
1207
1208    assert(output_size_bytes >= 1);
1209    if (output_size_bytes > GEN7_MAX_DS_URB_ENTRY_SIZE_BYTES) {
1210       if (error_str)
1211          *error_str = ralloc_strdup(mem_ctx, "DS outputs exceed maximum size");
1212       return NULL;
1213    }
1214
1215    prog_data->base.clip_distance_mask =
1216       ((1 << nir->info.clip_distance_array_size) - 1);
1217    prog_data->base.cull_distance_mask =
1218       ((1 << nir->info.cull_distance_array_size) - 1) <<
1219       nir->info.clip_distance_array_size;
1220
1221    /* URB entry sizes are stored as a multiple of 64 bytes. */
1222    prog_data->base.urb_entry_size = ALIGN(output_size_bytes, 64) / 64;
1223
1224    /* On Cannonlake software shall not program an allocation size that
1225     * specifies a size that is a multiple of 3 64B (512-bit) cachelines.
1226     */
1227    if (devinfo->gen == 10 &&
1228        prog_data->base.urb_entry_size % 3 == 0)
1229       prog_data->base.urb_entry_size++;
1230
1231    prog_data->base.urb_read_length = 0;
1232
1233    STATIC_ASSERT(BRW_TESS_PARTITIONING_INTEGER == TESS_SPACING_EQUAL - 1);
1234    STATIC_ASSERT(BRW_TESS_PARTITIONING_ODD_FRACTIONAL ==
1235                  TESS_SPACING_FRACTIONAL_ODD - 1);
1236    STATIC_ASSERT(BRW_TESS_PARTITIONING_EVEN_FRACTIONAL ==
1237                  TESS_SPACING_FRACTIONAL_EVEN - 1);
1238
1239    prog_data->partitioning =
1240       (enum brw_tess_partitioning) (nir->info.tess.spacing - 1);
1241
1242    switch (nir->info.tess.primitive_mode) {
1243    case GL_QUADS:
1244       prog_data->domain = BRW_TESS_DOMAIN_QUAD;
1245       break;
1246    case GL_TRIANGLES:
1247       prog_data->domain = BRW_TESS_DOMAIN_TRI;
1248       break;
1249    case GL_ISOLINES:
1250       prog_data->domain = BRW_TESS_DOMAIN_ISOLINE;
1251       break;
1252    default:
1253       unreachable("invalid domain shader primitive mode");
1254    }
1255
1256    if (nir->info.tess.point_mode) {
1257       prog_data->output_topology = BRW_TESS_OUTPUT_TOPOLOGY_POINT;
1258    } else if (nir->info.tess.primitive_mode == GL_ISOLINES) {
1259       prog_data->output_topology = BRW_TESS_OUTPUT_TOPOLOGY_LINE;
1260    } else {
1261       /* Hardware winding order is backwards from OpenGL */
1262       prog_data->output_topology =
1263          nir->info.tess.ccw ? BRW_TESS_OUTPUT_TOPOLOGY_TRI_CW
1264                              : BRW_TESS_OUTPUT_TOPOLOGY_TRI_CCW;
1265    }
1266
1267    if (unlikely(INTEL_DEBUG & DEBUG_TES)) {
1268       fprintf(stderr, "TES Input ");
1269       brw_print_vue_map(stderr, input_vue_map);
1270       fprintf(stderr, "TES Output ");
1271       brw_print_vue_map(stderr, &prog_data->base.vue_map);
1272    }
1273
1274    if (is_scalar) {
1275       fs_visitor v(compiler, log_data, mem_ctx, (void *) key,
1276                    &prog_data->base.base, NULL, nir, 8,
1277                    shader_time_index, input_vue_map);
1278       if (!v.run_tes()) {
1279          if (error_str)
1280             *error_str = ralloc_strdup(mem_ctx, v.fail_msg);
1281          return NULL;
1282       }
1283
1284       prog_data->base.base.dispatch_grf_start_reg = v.payload.num_regs;
1285       prog_data->base.dispatch_mode = DISPATCH_MODE_SIMD8;
1286
1287       fs_generator g(compiler, log_data, mem_ctx,
1288                      &prog_data->base.base, v.promoted_constants, false,
1289                      MESA_SHADER_TESS_EVAL);
1290       if (unlikely(INTEL_DEBUG & DEBUG_TES)) {
1291          g.enable_debug(ralloc_asprintf(mem_ctx,
1292                                         "%s tessellation evaluation shader %s",
1293                                         nir->info.label ? nir->info.label
1294                                                         : "unnamed",
1295                                         nir->info.name));
1296       }
1297
1298       g.generate_code(v.cfg, 8);
1299
1300       assembly = g.get_assembly();
1301    } else {
1302       brw::vec4_tes_visitor v(compiler, log_data, key, prog_data,
1303                               nir, mem_ctx, shader_time_index);
1304       if (!v.run()) {
1305          if (error_str)
1306             *error_str = ralloc_strdup(mem_ctx, v.fail_msg);
1307          return NULL;
1308       }
1309
1310       if (unlikely(INTEL_DEBUG & DEBUG_TES))
1311          v.dump_instructions();
1312
1313       assembly = brw_vec4_generate_assembly(compiler, log_data, mem_ctx, nir,
1314                                             &prog_data->base, v.cfg);
1315    }
1316
1317    return assembly;
1318 }