2 * Copyright © 2010 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
28 #include "brw_vec4_tes.h"
29 #include "common/gen_debug.h"
30 #include "main/uniforms.h"
31 #include "util/macros.h"
34 brw_type_for_base_type(const struct glsl_type
*type
)
36 switch (type
->base_type
) {
38 return BRW_REGISTER_TYPE_F
;
41 case GLSL_TYPE_SUBROUTINE
:
42 return BRW_REGISTER_TYPE_D
;
44 return BRW_REGISTER_TYPE_UD
;
46 return brw_type_for_base_type(type
->fields
.array
);
47 case GLSL_TYPE_STRUCT
:
48 case GLSL_TYPE_SAMPLER
:
49 case GLSL_TYPE_ATOMIC_UINT
:
50 /* These should be overridden with the type of the member when
51 * dereferenced into. BRW_REGISTER_TYPE_UD seems like a likely
52 * way to trip up if we don't.
54 return BRW_REGISTER_TYPE_UD
;
56 return BRW_REGISTER_TYPE_UD
;
57 case GLSL_TYPE_DOUBLE
:
58 return BRW_REGISTER_TYPE_DF
;
59 case GLSL_TYPE_UINT64
:
60 return BRW_REGISTER_TYPE_UQ
;
62 return BRW_REGISTER_TYPE_Q
;
65 case GLSL_TYPE_INTERFACE
:
66 case GLSL_TYPE_FUNCTION
:
67 unreachable("not reached");
70 return BRW_REGISTER_TYPE_F
;
73 enum brw_conditional_mod
74 brw_conditional_for_comparison(unsigned int op
)
78 return BRW_CONDITIONAL_L
;
79 case ir_binop_greater
:
80 return BRW_CONDITIONAL_G
;
82 return BRW_CONDITIONAL_LE
;
84 return BRW_CONDITIONAL_GE
;
86 case ir_binop_all_equal
: /* same as equal for scalars */
87 return BRW_CONDITIONAL_Z
;
89 case ir_binop_any_nequal
: /* same as nequal for scalars */
90 return BRW_CONDITIONAL_NZ
;
92 unreachable("not reached: bad operation for comparison");
97 brw_math_function(enum opcode op
)
100 case SHADER_OPCODE_RCP
:
101 return BRW_MATH_FUNCTION_INV
;
102 case SHADER_OPCODE_RSQ
:
103 return BRW_MATH_FUNCTION_RSQ
;
104 case SHADER_OPCODE_SQRT
:
105 return BRW_MATH_FUNCTION_SQRT
;
106 case SHADER_OPCODE_EXP2
:
107 return BRW_MATH_FUNCTION_EXP
;
108 case SHADER_OPCODE_LOG2
:
109 return BRW_MATH_FUNCTION_LOG
;
110 case SHADER_OPCODE_POW
:
111 return BRW_MATH_FUNCTION_POW
;
112 case SHADER_OPCODE_SIN
:
113 return BRW_MATH_FUNCTION_SIN
;
114 case SHADER_OPCODE_COS
:
115 return BRW_MATH_FUNCTION_COS
;
116 case SHADER_OPCODE_INT_QUOTIENT
:
117 return BRW_MATH_FUNCTION_INT_DIV_QUOTIENT
;
118 case SHADER_OPCODE_INT_REMAINDER
:
119 return BRW_MATH_FUNCTION_INT_DIV_REMAINDER
;
121 unreachable("not reached: unknown math function");
126 brw_texture_offset(int *offsets
, unsigned num_components
, uint32_t *offset_bits
)
128 if (!offsets
) return false; /* nonconstant offset; caller will handle it. */
130 /* offset out of bounds; caller will handle it. */
131 for (unsigned i
= 0; i
< num_components
; i
++)
132 if (offsets
[i
] > 7 || offsets
[i
] < -8)
135 /* Combine all three offsets into a single unsigned dword:
137 * bits 11:8 - U Offset (X component)
138 * bits 7:4 - V Offset (Y component)
139 * bits 3:0 - R Offset (Z component)
142 for (unsigned i
= 0; i
< num_components
; i
++) {
143 const unsigned shift
= 4 * (2 - i
);
144 *offset_bits
|= (offsets
[i
] << shift
) & (0xF << shift
);
150 brw_instruction_name(const struct gen_device_info
*devinfo
, enum opcode op
)
153 case BRW_OPCODE_ILLEGAL
... BRW_OPCODE_NOP
:
154 /* The DO instruction doesn't exist on Gen6+, but we use it to mark the
155 * start of a loop in the IR.
157 if (devinfo
->gen
>= 6 && op
== BRW_OPCODE_DO
)
160 /* The following conversion opcodes doesn't exist on Gen8+, but we use
161 * then to mark that we want to do the conversion.
163 if (devinfo
->gen
> 7 && op
== BRW_OPCODE_F32TO16
)
166 if (devinfo
->gen
> 7 && op
== BRW_OPCODE_F16TO32
)
169 assert(brw_opcode_desc(devinfo
, op
)->name
);
170 return brw_opcode_desc(devinfo
, op
)->name
;
171 case FS_OPCODE_FB_WRITE
:
173 case FS_OPCODE_FB_WRITE_LOGICAL
:
174 return "fb_write_logical";
175 case FS_OPCODE_REP_FB_WRITE
:
176 return "rep_fb_write";
177 case FS_OPCODE_FB_READ
:
179 case FS_OPCODE_FB_READ_LOGICAL
:
180 return "fb_read_logical";
182 case SHADER_OPCODE_RCP
:
184 case SHADER_OPCODE_RSQ
:
186 case SHADER_OPCODE_SQRT
:
188 case SHADER_OPCODE_EXP2
:
190 case SHADER_OPCODE_LOG2
:
192 case SHADER_OPCODE_POW
:
194 case SHADER_OPCODE_INT_QUOTIENT
:
196 case SHADER_OPCODE_INT_REMAINDER
:
198 case SHADER_OPCODE_SIN
:
200 case SHADER_OPCODE_COS
:
203 case SHADER_OPCODE_TEX
:
205 case SHADER_OPCODE_TEX_LOGICAL
:
206 return "tex_logical";
207 case SHADER_OPCODE_TXD
:
209 case SHADER_OPCODE_TXD_LOGICAL
:
210 return "txd_logical";
211 case SHADER_OPCODE_TXF
:
213 case SHADER_OPCODE_TXF_LOGICAL
:
214 return "txf_logical";
215 case SHADER_OPCODE_TXF_LZ
:
217 case SHADER_OPCODE_TXL
:
219 case SHADER_OPCODE_TXL_LOGICAL
:
220 return "txl_logical";
221 case SHADER_OPCODE_TXL_LZ
:
223 case SHADER_OPCODE_TXS
:
225 case SHADER_OPCODE_TXS_LOGICAL
:
226 return "txs_logical";
229 case FS_OPCODE_TXB_LOGICAL
:
230 return "txb_logical";
231 case SHADER_OPCODE_TXF_CMS
:
233 case SHADER_OPCODE_TXF_CMS_LOGICAL
:
234 return "txf_cms_logical";
235 case SHADER_OPCODE_TXF_CMS_W
:
237 case SHADER_OPCODE_TXF_CMS_W_LOGICAL
:
238 return "txf_cms_w_logical";
239 case SHADER_OPCODE_TXF_UMS
:
241 case SHADER_OPCODE_TXF_UMS_LOGICAL
:
242 return "txf_ums_logical";
243 case SHADER_OPCODE_TXF_MCS
:
245 case SHADER_OPCODE_TXF_MCS_LOGICAL
:
246 return "txf_mcs_logical";
247 case SHADER_OPCODE_LOD
:
249 case SHADER_OPCODE_LOD_LOGICAL
:
250 return "lod_logical";
251 case SHADER_OPCODE_TG4
:
253 case SHADER_OPCODE_TG4_LOGICAL
:
254 return "tg4_logical";
255 case SHADER_OPCODE_TG4_OFFSET
:
257 case SHADER_OPCODE_TG4_OFFSET_LOGICAL
:
258 return "tg4_offset_logical";
259 case SHADER_OPCODE_SAMPLEINFO
:
261 case SHADER_OPCODE_SAMPLEINFO_LOGICAL
:
262 return "sampleinfo_logical";
264 case SHADER_OPCODE_SHADER_TIME_ADD
:
265 return "shader_time_add";
267 case SHADER_OPCODE_UNTYPED_ATOMIC
:
268 return "untyped_atomic";
269 case SHADER_OPCODE_UNTYPED_ATOMIC_LOGICAL
:
270 return "untyped_atomic_logical";
271 case SHADER_OPCODE_UNTYPED_SURFACE_READ
:
272 return "untyped_surface_read";
273 case SHADER_OPCODE_UNTYPED_SURFACE_READ_LOGICAL
:
274 return "untyped_surface_read_logical";
275 case SHADER_OPCODE_UNTYPED_SURFACE_WRITE
:
276 return "untyped_surface_write";
277 case SHADER_OPCODE_UNTYPED_SURFACE_WRITE_LOGICAL
:
278 return "untyped_surface_write_logical";
279 case SHADER_OPCODE_TYPED_ATOMIC
:
280 return "typed_atomic";
281 case SHADER_OPCODE_TYPED_ATOMIC_LOGICAL
:
282 return "typed_atomic_logical";
283 case SHADER_OPCODE_TYPED_SURFACE_READ
:
284 return "typed_surface_read";
285 case SHADER_OPCODE_TYPED_SURFACE_READ_LOGICAL
:
286 return "typed_surface_read_logical";
287 case SHADER_OPCODE_TYPED_SURFACE_WRITE
:
288 return "typed_surface_write";
289 case SHADER_OPCODE_TYPED_SURFACE_WRITE_LOGICAL
:
290 return "typed_surface_write_logical";
291 case SHADER_OPCODE_MEMORY_FENCE
:
292 return "memory_fence";
294 case SHADER_OPCODE_LOAD_PAYLOAD
:
295 return "load_payload";
299 case SHADER_OPCODE_GEN4_SCRATCH_READ
:
300 return "gen4_scratch_read";
301 case SHADER_OPCODE_GEN4_SCRATCH_WRITE
:
302 return "gen4_scratch_write";
303 case SHADER_OPCODE_GEN7_SCRATCH_READ
:
304 return "gen7_scratch_read";
305 case SHADER_OPCODE_URB_WRITE_SIMD8
:
306 return "gen8_urb_write_simd8";
307 case SHADER_OPCODE_URB_WRITE_SIMD8_PER_SLOT
:
308 return "gen8_urb_write_simd8_per_slot";
309 case SHADER_OPCODE_URB_WRITE_SIMD8_MASKED
:
310 return "gen8_urb_write_simd8_masked";
311 case SHADER_OPCODE_URB_WRITE_SIMD8_MASKED_PER_SLOT
:
312 return "gen8_urb_write_simd8_masked_per_slot";
313 case SHADER_OPCODE_URB_READ_SIMD8
:
314 return "urb_read_simd8";
315 case SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT
:
316 return "urb_read_simd8_per_slot";
318 case SHADER_OPCODE_FIND_LIVE_CHANNEL
:
319 return "find_live_channel";
320 case SHADER_OPCODE_BROADCAST
:
323 case VEC4_OPCODE_MOV_BYTES
:
325 case VEC4_OPCODE_PACK_BYTES
:
327 case VEC4_OPCODE_UNPACK_UNIFORM
:
328 return "unpack_uniform";
329 case VEC4_OPCODE_DOUBLE_TO_F32
:
330 return "double_to_f32";
331 case VEC4_OPCODE_DOUBLE_TO_D32
:
332 return "double_to_d32";
333 case VEC4_OPCODE_DOUBLE_TO_U32
:
334 return "double_to_u32";
335 case VEC4_OPCODE_TO_DOUBLE
:
336 return "single_to_double";
337 case VEC4_OPCODE_PICK_LOW_32BIT
:
338 return "pick_low_32bit";
339 case VEC4_OPCODE_PICK_HIGH_32BIT
:
340 return "pick_high_32bit";
341 case VEC4_OPCODE_SET_LOW_32BIT
:
342 return "set_low_32bit";
343 case VEC4_OPCODE_SET_HIGH_32BIT
:
344 return "set_high_32bit";
346 case FS_OPCODE_DDX_COARSE
:
348 case FS_OPCODE_DDX_FINE
:
350 case FS_OPCODE_DDY_COARSE
:
352 case FS_OPCODE_DDY_FINE
:
355 case FS_OPCODE_CINTERP
:
357 case FS_OPCODE_LINTERP
:
360 case FS_OPCODE_PIXEL_X
:
362 case FS_OPCODE_PIXEL_Y
:
365 case FS_OPCODE_GET_BUFFER_SIZE
:
366 return "fs_get_buffer_size";
368 case FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD
:
369 return "uniform_pull_const";
370 case FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD_GEN7
:
371 return "uniform_pull_const_gen7";
372 case FS_OPCODE_VARYING_PULL_CONSTANT_LOAD_GEN4
:
373 return "varying_pull_const_gen4";
374 case FS_OPCODE_VARYING_PULL_CONSTANT_LOAD_GEN7
:
375 return "varying_pull_const_gen7";
376 case FS_OPCODE_VARYING_PULL_CONSTANT_LOAD_LOGICAL
:
377 return "varying_pull_const_logical";
379 case FS_OPCODE_MOV_DISPATCH_TO_FLAGS
:
380 return "mov_dispatch_to_flags";
381 case FS_OPCODE_DISCARD_JUMP
:
382 return "discard_jump";
384 case FS_OPCODE_SET_SAMPLE_ID
:
385 return "set_sample_id";
387 case FS_OPCODE_PACK_HALF_2x16_SPLIT
:
388 return "pack_half_2x16_split";
389 case FS_OPCODE_UNPACK_HALF_2x16_SPLIT_X
:
390 return "unpack_half_2x16_split_x";
391 case FS_OPCODE_UNPACK_HALF_2x16_SPLIT_Y
:
392 return "unpack_half_2x16_split_y";
394 case FS_OPCODE_PLACEHOLDER_HALT
:
395 return "placeholder_halt";
397 case FS_OPCODE_INTERPOLATE_AT_SAMPLE
:
398 return "interp_sample";
399 case FS_OPCODE_INTERPOLATE_AT_SHARED_OFFSET
:
400 return "interp_shared_offset";
401 case FS_OPCODE_INTERPOLATE_AT_PER_SLOT_OFFSET
:
402 return "interp_per_slot_offset";
404 case VS_OPCODE_URB_WRITE
:
405 return "vs_urb_write";
406 case VS_OPCODE_PULL_CONSTANT_LOAD
:
407 return "pull_constant_load";
408 case VS_OPCODE_PULL_CONSTANT_LOAD_GEN7
:
409 return "pull_constant_load_gen7";
411 case VS_OPCODE_SET_SIMD4X2_HEADER_GEN9
:
412 return "set_simd4x2_header_gen9";
414 case VS_OPCODE_GET_BUFFER_SIZE
:
415 return "vs_get_buffer_size";
417 case VS_OPCODE_UNPACK_FLAGS_SIMD4X2
:
418 return "unpack_flags_simd4x2";
420 case GS_OPCODE_URB_WRITE
:
421 return "gs_urb_write";
422 case GS_OPCODE_URB_WRITE_ALLOCATE
:
423 return "gs_urb_write_allocate";
424 case GS_OPCODE_THREAD_END
:
425 return "gs_thread_end";
426 case GS_OPCODE_SET_WRITE_OFFSET
:
427 return "set_write_offset";
428 case GS_OPCODE_SET_VERTEX_COUNT
:
429 return "set_vertex_count";
430 case GS_OPCODE_SET_DWORD_2
:
431 return "set_dword_2";
432 case GS_OPCODE_PREPARE_CHANNEL_MASKS
:
433 return "prepare_channel_masks";
434 case GS_OPCODE_SET_CHANNEL_MASKS
:
435 return "set_channel_masks";
436 case GS_OPCODE_GET_INSTANCE_ID
:
437 return "get_instance_id";
438 case GS_OPCODE_FF_SYNC
:
440 case GS_OPCODE_SET_PRIMITIVE_ID
:
441 return "set_primitive_id";
442 case GS_OPCODE_SVB_WRITE
:
443 return "gs_svb_write";
444 case GS_OPCODE_SVB_SET_DST_INDEX
:
445 return "gs_svb_set_dst_index";
446 case GS_OPCODE_FF_SYNC_SET_PRIMITIVES
:
447 return "gs_ff_sync_set_primitives";
448 case CS_OPCODE_CS_TERMINATE
:
449 return "cs_terminate";
450 case SHADER_OPCODE_BARRIER
:
452 case SHADER_OPCODE_MULH
:
454 case SHADER_OPCODE_MOV_INDIRECT
:
455 return "mov_indirect";
457 case VEC4_OPCODE_URB_READ
:
459 case TCS_OPCODE_GET_INSTANCE_ID
:
460 return "tcs_get_instance_id";
461 case TCS_OPCODE_URB_WRITE
:
462 return "tcs_urb_write";
463 case TCS_OPCODE_SET_INPUT_URB_OFFSETS
:
464 return "tcs_set_input_urb_offsets";
465 case TCS_OPCODE_SET_OUTPUT_URB_OFFSETS
:
466 return "tcs_set_output_urb_offsets";
467 case TCS_OPCODE_GET_PRIMITIVE_ID
:
468 return "tcs_get_primitive_id";
469 case TCS_OPCODE_CREATE_BARRIER_HEADER
:
470 return "tcs_create_barrier_header";
471 case TCS_OPCODE_SRC0_010_IS_ZERO
:
472 return "tcs_src0<0,1,0>_is_zero";
473 case TCS_OPCODE_RELEASE_INPUT
:
474 return "tcs_release_input";
475 case TCS_OPCODE_THREAD_END
:
476 return "tcs_thread_end";
477 case TES_OPCODE_CREATE_INPUT_READ_HEADER
:
478 return "tes_create_input_read_header";
479 case TES_OPCODE_ADD_INDIRECT_URB_OFFSET
:
480 return "tes_add_indirect_urb_offset";
481 case TES_OPCODE_GET_PRIMITIVE_ID
:
482 return "tes_get_primitive_id";
485 unreachable("not reached");
489 brw_saturate_immediate(enum brw_reg_type type
, struct brw_reg
*reg
)
496 } imm
, sat_imm
= { 0 };
498 const unsigned size
= type_sz(type
);
500 /* We want to either do a 32-bit or 64-bit data copy, the type is otherwise
501 * irrelevant, so just check the size of the type and copy from/to an
502 * appropriately sized field.
510 case BRW_REGISTER_TYPE_UD
:
511 case BRW_REGISTER_TYPE_D
:
512 case BRW_REGISTER_TYPE_UW
:
513 case BRW_REGISTER_TYPE_W
:
514 case BRW_REGISTER_TYPE_UQ
:
515 case BRW_REGISTER_TYPE_Q
:
518 case BRW_REGISTER_TYPE_F
:
519 sat_imm
.f
= CLAMP(imm
.f
, 0.0f
, 1.0f
);
521 case BRW_REGISTER_TYPE_DF
:
522 sat_imm
.df
= CLAMP(imm
.df
, 0.0, 1.0);
524 case BRW_REGISTER_TYPE_UB
:
525 case BRW_REGISTER_TYPE_B
:
526 unreachable("no UB/B immediates");
527 case BRW_REGISTER_TYPE_V
:
528 case BRW_REGISTER_TYPE_UV
:
529 case BRW_REGISTER_TYPE_VF
:
530 unreachable("unimplemented: saturate vector immediate");
531 case BRW_REGISTER_TYPE_HF
:
532 unreachable("unimplemented: saturate HF immediate");
536 if (imm
.ud
!= sat_imm
.ud
) {
537 reg
->ud
= sat_imm
.ud
;
541 if (imm
.df
!= sat_imm
.df
) {
542 reg
->df
= sat_imm
.df
;
550 brw_negate_immediate(enum brw_reg_type type
, struct brw_reg
*reg
)
553 case BRW_REGISTER_TYPE_D
:
554 case BRW_REGISTER_TYPE_UD
:
557 case BRW_REGISTER_TYPE_W
:
558 case BRW_REGISTER_TYPE_UW
:
559 reg
->d
= -(int16_t)reg
->ud
;
561 case BRW_REGISTER_TYPE_F
:
564 case BRW_REGISTER_TYPE_VF
:
565 reg
->ud
^= 0x80808080;
567 case BRW_REGISTER_TYPE_DF
:
570 case BRW_REGISTER_TYPE_UQ
:
571 case BRW_REGISTER_TYPE_Q
:
572 reg
->d64
= -reg
->d64
;
574 case BRW_REGISTER_TYPE_UB
:
575 case BRW_REGISTER_TYPE_B
:
576 unreachable("no UB/B immediates");
577 case BRW_REGISTER_TYPE_UV
:
578 case BRW_REGISTER_TYPE_V
:
579 assert(!"unimplemented: negate UV/V immediate");
580 case BRW_REGISTER_TYPE_HF
:
581 assert(!"unimplemented: negate HF immediate");
588 brw_abs_immediate(enum brw_reg_type type
, struct brw_reg
*reg
)
591 case BRW_REGISTER_TYPE_D
:
592 reg
->d
= abs(reg
->d
);
594 case BRW_REGISTER_TYPE_W
:
595 reg
->d
= abs((int16_t)reg
->ud
);
597 case BRW_REGISTER_TYPE_F
:
598 reg
->f
= fabsf(reg
->f
);
600 case BRW_REGISTER_TYPE_DF
:
601 reg
->df
= fabs(reg
->df
);
603 case BRW_REGISTER_TYPE_VF
:
604 reg
->ud
&= ~0x80808080;
606 case BRW_REGISTER_TYPE_Q
:
607 reg
->d64
= imaxabs(reg
->d64
);
609 case BRW_REGISTER_TYPE_UB
:
610 case BRW_REGISTER_TYPE_B
:
611 unreachable("no UB/B immediates");
612 case BRW_REGISTER_TYPE_UQ
:
613 case BRW_REGISTER_TYPE_UD
:
614 case BRW_REGISTER_TYPE_UW
:
615 case BRW_REGISTER_TYPE_UV
:
616 /* Presumably the absolute value modifier on an unsigned source is a
617 * nop, but it would be nice to confirm.
619 assert(!"unimplemented: abs unsigned immediate");
620 case BRW_REGISTER_TYPE_V
:
621 assert(!"unimplemented: abs V immediate");
622 case BRW_REGISTER_TYPE_HF
:
623 assert(!"unimplemented: abs HF immediate");
630 * Get the appropriate atomic op for an image atomic intrinsic.
633 get_atomic_counter_op(nir_intrinsic_op op
)
636 case nir_intrinsic_atomic_counter_inc
:
638 case nir_intrinsic_atomic_counter_dec
:
639 return BRW_AOP_PREDEC
;
640 case nir_intrinsic_atomic_counter_add
:
642 case nir_intrinsic_atomic_counter_min
:
644 case nir_intrinsic_atomic_counter_max
:
646 case nir_intrinsic_atomic_counter_and
:
648 case nir_intrinsic_atomic_counter_or
:
650 case nir_intrinsic_atomic_counter_xor
:
652 case nir_intrinsic_atomic_counter_exchange
:
654 case nir_intrinsic_atomic_counter_comp_swap
:
655 return BRW_AOP_CMPWR
;
657 unreachable("Not reachable.");
661 backend_shader::backend_shader(const struct brw_compiler
*compiler
,
664 const nir_shader
*shader
,
665 struct brw_stage_prog_data
*stage_prog_data
)
666 : compiler(compiler
),
668 devinfo(compiler
->devinfo
),
670 stage_prog_data(stage_prog_data
),
673 stage(shader
->info
.stage
)
675 debug_enabled
= INTEL_DEBUG
& intel_debug_flag_for_shader_stage(stage
);
676 stage_name
= _mesa_shader_stage_to_string(stage
);
677 stage_abbrev
= _mesa_shader_stage_to_abbrev(stage
);
681 backend_reg::equals(const backend_reg
&r
) const
683 return brw_regs_equal(this, &r
) && offset
== r
.offset
;
687 backend_reg::is_zero() const
693 case BRW_REGISTER_TYPE_F
:
695 case BRW_REGISTER_TYPE_DF
:
697 case BRW_REGISTER_TYPE_D
:
698 case BRW_REGISTER_TYPE_UD
:
700 case BRW_REGISTER_TYPE_UQ
:
701 case BRW_REGISTER_TYPE_Q
:
709 backend_reg::is_one() const
715 case BRW_REGISTER_TYPE_F
:
717 case BRW_REGISTER_TYPE_DF
:
719 case BRW_REGISTER_TYPE_D
:
720 case BRW_REGISTER_TYPE_UD
:
722 case BRW_REGISTER_TYPE_UQ
:
723 case BRW_REGISTER_TYPE_Q
:
731 backend_reg::is_negative_one() const
737 case BRW_REGISTER_TYPE_F
:
739 case BRW_REGISTER_TYPE_DF
:
741 case BRW_REGISTER_TYPE_D
:
743 case BRW_REGISTER_TYPE_Q
:
751 backend_reg::is_null() const
753 return file
== ARF
&& nr
== BRW_ARF_NULL
;
758 backend_reg::is_accumulator() const
760 return file
== ARF
&& nr
== BRW_ARF_ACCUMULATOR
;
764 backend_instruction::is_commutative() const
772 case SHADER_OPCODE_MULH
:
775 /* MIN and MAX are commutative. */
776 if (conditional_mod
== BRW_CONDITIONAL_GE
||
777 conditional_mod
== BRW_CONDITIONAL_L
) {
787 backend_instruction::is_3src(const struct gen_device_info
*devinfo
) const
789 return ::is_3src(devinfo
, opcode
);
793 backend_instruction::is_tex() const
795 return (opcode
== SHADER_OPCODE_TEX
||
796 opcode
== FS_OPCODE_TXB
||
797 opcode
== SHADER_OPCODE_TXD
||
798 opcode
== SHADER_OPCODE_TXF
||
799 opcode
== SHADER_OPCODE_TXF_LZ
||
800 opcode
== SHADER_OPCODE_TXF_CMS
||
801 opcode
== SHADER_OPCODE_TXF_CMS_W
||
802 opcode
== SHADER_OPCODE_TXF_UMS
||
803 opcode
== SHADER_OPCODE_TXF_MCS
||
804 opcode
== SHADER_OPCODE_TXL
||
805 opcode
== SHADER_OPCODE_TXL_LZ
||
806 opcode
== SHADER_OPCODE_TXS
||
807 opcode
== SHADER_OPCODE_LOD
||
808 opcode
== SHADER_OPCODE_TG4
||
809 opcode
== SHADER_OPCODE_TG4_OFFSET
||
810 opcode
== SHADER_OPCODE_SAMPLEINFO
);
814 backend_instruction::is_math() const
816 return (opcode
== SHADER_OPCODE_RCP
||
817 opcode
== SHADER_OPCODE_RSQ
||
818 opcode
== SHADER_OPCODE_SQRT
||
819 opcode
== SHADER_OPCODE_EXP2
||
820 opcode
== SHADER_OPCODE_LOG2
||
821 opcode
== SHADER_OPCODE_SIN
||
822 opcode
== SHADER_OPCODE_COS
||
823 opcode
== SHADER_OPCODE_INT_QUOTIENT
||
824 opcode
== SHADER_OPCODE_INT_REMAINDER
||
825 opcode
== SHADER_OPCODE_POW
);
829 backend_instruction::is_control_flow() const
833 case BRW_OPCODE_WHILE
:
835 case BRW_OPCODE_ELSE
:
836 case BRW_OPCODE_ENDIF
:
837 case BRW_OPCODE_BREAK
:
838 case BRW_OPCODE_CONTINUE
:
846 backend_instruction::can_do_source_mods() const
849 case BRW_OPCODE_ADDC
:
851 case BRW_OPCODE_BFI1
:
852 case BRW_OPCODE_BFI2
:
853 case BRW_OPCODE_BFREV
:
854 case BRW_OPCODE_CBIT
:
857 case BRW_OPCODE_SUBB
:
865 backend_instruction::can_do_saturate() const
875 case BRW_OPCODE_F16TO32
:
876 case BRW_OPCODE_F32TO16
:
877 case BRW_OPCODE_LINE
:
881 case BRW_OPCODE_MATH
:
884 case SHADER_OPCODE_MULH
:
886 case BRW_OPCODE_RNDD
:
887 case BRW_OPCODE_RNDE
:
888 case BRW_OPCODE_RNDU
:
889 case BRW_OPCODE_RNDZ
:
893 case FS_OPCODE_LINTERP
:
894 case SHADER_OPCODE_COS
:
895 case SHADER_OPCODE_EXP2
:
896 case SHADER_OPCODE_LOG2
:
897 case SHADER_OPCODE_POW
:
898 case SHADER_OPCODE_RCP
:
899 case SHADER_OPCODE_RSQ
:
900 case SHADER_OPCODE_SIN
:
901 case SHADER_OPCODE_SQRT
:
909 backend_instruction::can_do_cmod() const
913 case BRW_OPCODE_ADDC
:
918 case BRW_OPCODE_CMPN
:
923 case BRW_OPCODE_F16TO32
:
924 case BRW_OPCODE_F32TO16
:
926 case BRW_OPCODE_LINE
:
930 case BRW_OPCODE_MACH
:
937 case BRW_OPCODE_RNDD
:
938 case BRW_OPCODE_RNDE
:
939 case BRW_OPCODE_RNDU
:
940 case BRW_OPCODE_RNDZ
:
941 case BRW_OPCODE_SAD2
:
942 case BRW_OPCODE_SADA2
:
945 case BRW_OPCODE_SUBB
:
947 case FS_OPCODE_CINTERP
:
948 case FS_OPCODE_LINTERP
:
956 backend_instruction::reads_accumulator_implicitly() const
960 case BRW_OPCODE_MACH
:
961 case BRW_OPCODE_SADA2
:
969 backend_instruction::writes_accumulator_implicitly(const struct gen_device_info
*devinfo
) const
971 return writes_accumulator
||
973 ((opcode
>= BRW_OPCODE_ADD
&& opcode
< BRW_OPCODE_NOP
) ||
974 (opcode
>= FS_OPCODE_DDX_COARSE
&& opcode
<= FS_OPCODE_LINTERP
&&
975 opcode
!= FS_OPCODE_CINTERP
)));
979 backend_instruction::has_side_effects() const
982 case SHADER_OPCODE_UNTYPED_ATOMIC
:
983 case SHADER_OPCODE_UNTYPED_ATOMIC_LOGICAL
:
984 case SHADER_OPCODE_GEN4_SCRATCH_WRITE
:
985 case SHADER_OPCODE_UNTYPED_SURFACE_WRITE
:
986 case SHADER_OPCODE_UNTYPED_SURFACE_WRITE_LOGICAL
:
987 case SHADER_OPCODE_TYPED_ATOMIC
:
988 case SHADER_OPCODE_TYPED_ATOMIC_LOGICAL
:
989 case SHADER_OPCODE_TYPED_SURFACE_WRITE
:
990 case SHADER_OPCODE_TYPED_SURFACE_WRITE_LOGICAL
:
991 case SHADER_OPCODE_MEMORY_FENCE
:
992 case SHADER_OPCODE_URB_WRITE_SIMD8
:
993 case SHADER_OPCODE_URB_WRITE_SIMD8_PER_SLOT
:
994 case SHADER_OPCODE_URB_WRITE_SIMD8_MASKED
:
995 case SHADER_OPCODE_URB_WRITE_SIMD8_MASKED_PER_SLOT
:
996 case FS_OPCODE_FB_WRITE
:
997 case FS_OPCODE_FB_WRITE_LOGICAL
:
998 case SHADER_OPCODE_BARRIER
:
999 case TCS_OPCODE_URB_WRITE
:
1000 case TCS_OPCODE_RELEASE_INPUT
:
1008 backend_instruction::is_volatile() const
1011 case SHADER_OPCODE_UNTYPED_SURFACE_READ
:
1012 case SHADER_OPCODE_UNTYPED_SURFACE_READ_LOGICAL
:
1013 case SHADER_OPCODE_TYPED_SURFACE_READ
:
1014 case SHADER_OPCODE_TYPED_SURFACE_READ_LOGICAL
:
1015 case SHADER_OPCODE_URB_READ_SIMD8
:
1016 case SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT
:
1017 case VEC4_OPCODE_URB_READ
:
1026 inst_is_in_block(const bblock_t
*block
, const backend_instruction
*inst
)
1029 foreach_inst_in_block (backend_instruction
, i
, block
) {
1039 adjust_later_block_ips(bblock_t
*start_block
, int ip_adjustment
)
1041 for (bblock_t
*block_iter
= start_block
->next();
1043 block_iter
= block_iter
->next()) {
1044 block_iter
->start_ip
+= ip_adjustment
;
1045 block_iter
->end_ip
+= ip_adjustment
;
1050 backend_instruction::insert_after(bblock_t
*block
, backend_instruction
*inst
)
1052 assert(this != inst
);
1054 if (!this->is_head_sentinel())
1055 assert(inst_is_in_block(block
, this) || !"Instruction not in block");
1059 adjust_later_block_ips(block
, 1);
1061 exec_node::insert_after(inst
);
1065 backend_instruction::insert_before(bblock_t
*block
, backend_instruction
*inst
)
1067 assert(this != inst
);
1069 if (!this->is_tail_sentinel())
1070 assert(inst_is_in_block(block
, this) || !"Instruction not in block");
1074 adjust_later_block_ips(block
, 1);
1076 exec_node::insert_before(inst
);
1080 backend_instruction::insert_before(bblock_t
*block
, exec_list
*list
)
1082 assert(inst_is_in_block(block
, this) || !"Instruction not in block");
1084 unsigned num_inst
= list
->length();
1086 block
->end_ip
+= num_inst
;
1088 adjust_later_block_ips(block
, num_inst
);
1090 exec_node::insert_before(list
);
1094 backend_instruction::remove(bblock_t
*block
)
1096 assert(inst_is_in_block(block
, this) || !"Instruction not in block");
1098 adjust_later_block_ips(block
, -1);
1100 if (block
->start_ip
== block
->end_ip
) {
1101 block
->cfg
->remove_block(block
);
1106 exec_node::remove();
1110 backend_shader::dump_instructions()
1112 dump_instructions(NULL
);
1116 backend_shader::dump_instructions(const char *name
)
1118 FILE *file
= stderr
;
1119 if (name
&& geteuid() != 0) {
1120 file
= fopen(name
, "w");
1127 foreach_block_and_inst(block
, backend_instruction
, inst
, cfg
) {
1128 if (!unlikely(INTEL_DEBUG
& DEBUG_OPTIMIZER
))
1129 fprintf(file
, "%4d: ", ip
++);
1130 dump_instruction(inst
, file
);
1134 foreach_in_list(backend_instruction
, inst
, &instructions
) {
1135 if (!unlikely(INTEL_DEBUG
& DEBUG_OPTIMIZER
))
1136 fprintf(file
, "%4d: ", ip
++);
1137 dump_instruction(inst
, file
);
1141 if (file
!= stderr
) {
1147 backend_shader::calculate_cfg()
1151 cfg
= new(mem_ctx
) cfg_t(&this->instructions
);
1154 extern "C" const unsigned *
1155 brw_compile_tes(const struct brw_compiler
*compiler
,
1158 const struct brw_tes_prog_key
*key
,
1159 const struct brw_vue_map
*input_vue_map
,
1160 struct brw_tes_prog_data
*prog_data
,
1161 const nir_shader
*src_shader
,
1162 struct gl_program
*prog
,
1163 int shader_time_index
,
1164 unsigned *final_assembly_size
,
1167 const struct gen_device_info
*devinfo
= compiler
->devinfo
;
1168 const bool is_scalar
= compiler
->scalar_stage
[MESA_SHADER_TESS_EVAL
];
1170 nir_shader
*nir
= nir_shader_clone(mem_ctx
, src_shader
);
1171 nir
->info
.inputs_read
= key
->inputs_read
;
1172 nir
->info
.patch_inputs_read
= key
->patch_inputs_read
;
1174 nir
= brw_nir_apply_sampler_key(nir
, compiler
, &key
->tex
, is_scalar
);
1175 brw_nir_lower_tes_inputs(nir
, input_vue_map
);
1176 brw_nir_lower_vue_outputs(nir
, is_scalar
);
1177 nir
= brw_postprocess_nir(nir
, compiler
, is_scalar
);
1179 brw_compute_vue_map(devinfo
, &prog_data
->base
.vue_map
,
1180 nir
->info
.outputs_written
,
1181 nir
->info
.separate_shader
);
1183 unsigned output_size_bytes
= prog_data
->base
.vue_map
.num_slots
* 4 * 4;
1185 assert(output_size_bytes
>= 1);
1186 if (output_size_bytes
> GEN7_MAX_DS_URB_ENTRY_SIZE_BYTES
) {
1188 *error_str
= ralloc_strdup(mem_ctx
, "DS outputs exceed maximum size");
1192 prog_data
->base
.clip_distance_mask
=
1193 ((1 << nir
->info
.clip_distance_array_size
) - 1);
1194 prog_data
->base
.cull_distance_mask
=
1195 ((1 << nir
->info
.cull_distance_array_size
) - 1) <<
1196 nir
->info
.clip_distance_array_size
;
1198 /* URB entry sizes are stored as a multiple of 64 bytes. */
1199 prog_data
->base
.urb_entry_size
= ALIGN(output_size_bytes
, 64) / 64;
1201 /* On Cannonlake software shall not program an allocation size that
1202 * specifies a size that is a multiple of 3 64B (512-bit) cachelines.
1204 if (devinfo
->gen
== 10 &&
1205 prog_data
->base
.urb_entry_size
% 3 == 0)
1206 prog_data
->base
.urb_entry_size
++;
1208 prog_data
->base
.urb_read_length
= 0;
1210 STATIC_ASSERT(BRW_TESS_PARTITIONING_INTEGER
== TESS_SPACING_EQUAL
- 1);
1211 STATIC_ASSERT(BRW_TESS_PARTITIONING_ODD_FRACTIONAL
==
1212 TESS_SPACING_FRACTIONAL_ODD
- 1);
1213 STATIC_ASSERT(BRW_TESS_PARTITIONING_EVEN_FRACTIONAL
==
1214 TESS_SPACING_FRACTIONAL_EVEN
- 1);
1216 prog_data
->partitioning
=
1217 (enum brw_tess_partitioning
) (nir
->info
.tess
.spacing
- 1);
1219 switch (nir
->info
.tess
.primitive_mode
) {
1221 prog_data
->domain
= BRW_TESS_DOMAIN_QUAD
;
1224 prog_data
->domain
= BRW_TESS_DOMAIN_TRI
;
1227 prog_data
->domain
= BRW_TESS_DOMAIN_ISOLINE
;
1230 unreachable("invalid domain shader primitive mode");
1233 if (nir
->info
.tess
.point_mode
) {
1234 prog_data
->output_topology
= BRW_TESS_OUTPUT_TOPOLOGY_POINT
;
1235 } else if (nir
->info
.tess
.primitive_mode
== GL_ISOLINES
) {
1236 prog_data
->output_topology
= BRW_TESS_OUTPUT_TOPOLOGY_LINE
;
1238 /* Hardware winding order is backwards from OpenGL */
1239 prog_data
->output_topology
=
1240 nir
->info
.tess
.ccw
? BRW_TESS_OUTPUT_TOPOLOGY_TRI_CW
1241 : BRW_TESS_OUTPUT_TOPOLOGY_TRI_CCW
;
1244 if (unlikely(INTEL_DEBUG
& DEBUG_TES
)) {
1245 fprintf(stderr
, "TES Input ");
1246 brw_print_vue_map(stderr
, input_vue_map
);
1247 fprintf(stderr
, "TES Output ");
1248 brw_print_vue_map(stderr
, &prog_data
->base
.vue_map
);
1252 fs_visitor
v(compiler
, log_data
, mem_ctx
, (void *) key
,
1253 &prog_data
->base
.base
, NULL
, nir
, 8,
1254 shader_time_index
, input_vue_map
);
1257 *error_str
= ralloc_strdup(mem_ctx
, v
.fail_msg
);
1261 prog_data
->base
.base
.dispatch_grf_start_reg
= v
.payload
.num_regs
;
1262 prog_data
->base
.dispatch_mode
= DISPATCH_MODE_SIMD8
;
1264 fs_generator
g(compiler
, log_data
, mem_ctx
, (void *) key
,
1265 &prog_data
->base
.base
, v
.promoted_constants
, false,
1266 MESA_SHADER_TESS_EVAL
);
1267 if (unlikely(INTEL_DEBUG
& DEBUG_TES
)) {
1268 g
.enable_debug(ralloc_asprintf(mem_ctx
,
1269 "%s tessellation evaluation shader %s",
1270 nir
->info
.label
? nir
->info
.label
1275 g
.generate_code(v
.cfg
, 8);
1277 return g
.get_assembly(final_assembly_size
);
1279 brw::vec4_tes_visitor
v(compiler
, log_data
, key
, prog_data
,
1280 nir
, mem_ctx
, shader_time_index
);
1283 *error_str
= ralloc_strdup(mem_ctx
, v
.fail_msg
);
1287 if (unlikely(INTEL_DEBUG
& DEBUG_TES
))
1288 v
.dump_instructions();
1290 return brw_vec4_generate_assembly(compiler
, log_data
, mem_ctx
, nir
,
1291 &prog_data
->base
, v
.cfg
,
1292 final_assembly_size
);